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Commit | Line | Data |
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74afab7a | 1 | /* |
fd2fa6c1 | 2 | * Local APIC related interfaces to support IOAPIC, MSI, etc. |
74afab7a JL |
3 | * |
4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo | |
5 | * Moved from arch/x86/kernel/apic/io_apic.c. | |
b5dc8e6c JL |
6 | * Jiang Liu <jiang.liu@linux.intel.com> |
7 | * Enable support of hierarchical irqdomains | |
74afab7a JL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/interrupt.h> | |
65d7ed57 | 14 | #include <linux/seq_file.h> |
74afab7a JL |
15 | #include <linux/init.h> |
16 | #include <linux/compiler.h> | |
74afab7a | 17 | #include <linux/slab.h> |
d746d1eb | 18 | #include <asm/irqdomain.h> |
74afab7a JL |
19 | #include <asm/hw_irq.h> |
20 | #include <asm/apic.h> | |
21 | #include <asm/i8259.h> | |
22 | #include <asm/desc.h> | |
23 | #include <asm/irq_remapping.h> | |
24 | ||
8d1e3dca TG |
25 | #include <asm/trace/irq_vectors.h> |
26 | ||
7f3262ed | 27 | struct apic_chip_data { |
ba224fea TG |
28 | struct irq_cfg hw_irq_cfg; |
29 | unsigned int vector; | |
30 | unsigned int prev_vector; | |
029c6e1c TG |
31 | unsigned int cpu; |
32 | unsigned int prev_cpu; | |
69cde000 | 33 | unsigned int irq; |
dccfe314 | 34 | struct hlist_node clist; |
2db1f959 | 35 | unsigned int move_in_progress : 1, |
4900be83 TG |
36 | is_managed : 1, |
37 | can_reserve : 1, | |
38 | has_reserved : 1; | |
7f3262ed JL |
39 | }; |
40 | ||
b5dc8e6c | 41 | struct irq_domain *x86_vector_domain; |
c8f3e518 | 42 | EXPORT_SYMBOL_GPL(x86_vector_domain); |
74afab7a | 43 | static DEFINE_RAW_SPINLOCK(vector_lock); |
69cde000 | 44 | static cpumask_var_t vector_searchmask; |
b5dc8e6c | 45 | static struct irq_chip lapic_controller; |
0fa115da | 46 | static struct irq_matrix *vector_matrix; |
dccfe314 TG |
47 | #ifdef CONFIG_SMP |
48 | static DEFINE_PER_CPU(struct hlist_head, cleanup_list); | |
49 | #endif | |
74afab7a JL |
50 | |
51 | void lock_vector_lock(void) | |
52 | { | |
53 | /* Used to the online set of cpus does not change | |
54 | * during assign_irq_vector. | |
55 | */ | |
56 | raw_spin_lock(&vector_lock); | |
57 | } | |
58 | ||
59 | void unlock_vector_lock(void) | |
60 | { | |
61 | raw_spin_unlock(&vector_lock); | |
62 | } | |
63 | ||
99a1482d TG |
64 | void init_irq_alloc_info(struct irq_alloc_info *info, |
65 | const struct cpumask *mask) | |
66 | { | |
67 | memset(info, 0, sizeof(*info)); | |
68 | info->mask = mask; | |
69 | } | |
70 | ||
71 | void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src) | |
72 | { | |
73 | if (src) | |
74 | *dst = *src; | |
75 | else | |
76 | memset(dst, 0, sizeof(*dst)); | |
77 | } | |
78 | ||
86ba6551 | 79 | static struct apic_chip_data *apic_chip_data(struct irq_data *irqd) |
74afab7a | 80 | { |
86ba6551 | 81 | if (!irqd) |
b5dc8e6c JL |
82 | return NULL; |
83 | ||
86ba6551 TG |
84 | while (irqd->parent_data) |
85 | irqd = irqd->parent_data; | |
b5dc8e6c | 86 | |
86ba6551 | 87 | return irqd->chip_data; |
74afab7a JL |
88 | } |
89 | ||
86ba6551 | 90 | struct irq_cfg *irqd_cfg(struct irq_data *irqd) |
7f3262ed | 91 | { |
86ba6551 | 92 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
7f3262ed | 93 | |
ba224fea | 94 | return apicd ? &apicd->hw_irq_cfg : NULL; |
7f3262ed | 95 | } |
c8f3e518 | 96 | EXPORT_SYMBOL_GPL(irqd_cfg); |
7f3262ed JL |
97 | |
98 | struct irq_cfg *irq_cfg(unsigned int irq) | |
74afab7a | 99 | { |
7f3262ed JL |
100 | return irqd_cfg(irq_get_irq_data(irq)); |
101 | } | |
74afab7a | 102 | |
7f3262ed JL |
103 | static struct apic_chip_data *alloc_apic_chip_data(int node) |
104 | { | |
86ba6551 | 105 | struct apic_chip_data *apicd; |
7f3262ed | 106 | |
86ba6551 | 107 | apicd = kzalloc_node(sizeof(*apicd), GFP_KERNEL, node); |
69cde000 TG |
108 | if (apicd) |
109 | INIT_HLIST_NODE(&apicd->clist); | |
86ba6551 | 110 | return apicd; |
74afab7a JL |
111 | } |
112 | ||
86ba6551 | 113 | static void free_apic_chip_data(struct apic_chip_data *apicd) |
74afab7a | 114 | { |
69cde000 | 115 | kfree(apicd); |
74afab7a JL |
116 | } |
117 | ||
ba224fea TG |
118 | static void apic_update_irq_cfg(struct irq_data *irqd, unsigned int vector, |
119 | unsigned int cpu) | |
74afab7a | 120 | { |
69cde000 | 121 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
74afab7a | 122 | |
69cde000 | 123 | lockdep_assert_held(&vector_lock); |
74afab7a | 124 | |
ba224fea TG |
125 | apicd->hw_irq_cfg.vector = vector; |
126 | apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu); | |
127 | irq_data_update_effective_affinity(irqd, cpumask_of(cpu)); | |
128 | trace_vector_config(irqd->irq, vector, cpu, | |
129 | apicd->hw_irq_cfg.dest_apicid); | |
69cde000 | 130 | } |
74afab7a | 131 | |
69cde000 TG |
132 | static void apic_update_vector(struct irq_data *irqd, unsigned int newvec, |
133 | unsigned int newcpu) | |
134 | { | |
135 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
136 | struct irq_desc *desc = irq_data_to_desc(irqd); | |
74afab7a | 137 | |
69cde000 | 138 | lockdep_assert_held(&vector_lock); |
74afab7a | 139 | |
ba224fea | 140 | trace_vector_update(irqd->irq, newvec, newcpu, apicd->vector, |
69cde000 | 141 | apicd->cpu); |
74afab7a | 142 | |
69cde000 | 143 | /* Setup the vector move, if required */ |
ba224fea | 144 | if (apicd->vector && cpu_online(apicd->cpu)) { |
69cde000 | 145 | apicd->move_in_progress = true; |
ba224fea | 146 | apicd->prev_vector = apicd->vector; |
69cde000 TG |
147 | apicd->prev_cpu = apicd->cpu; |
148 | } else { | |
ba224fea | 149 | apicd->prev_vector = 0; |
69cde000 | 150 | } |
74afab7a | 151 | |
ba224fea | 152 | apicd->vector = newvec; |
69cde000 TG |
153 | apicd->cpu = newcpu; |
154 | BUG_ON(!IS_ERR_OR_NULL(per_cpu(vector_irq, newcpu)[newvec])); | |
155 | per_cpu(vector_irq, newcpu)[newvec] = desc; | |
156 | } | |
74afab7a | 157 | |
2db1f959 TG |
158 | static void vector_assign_managed_shutdown(struct irq_data *irqd) |
159 | { | |
160 | unsigned int cpu = cpumask_first(cpu_online_mask); | |
161 | ||
162 | apic_update_irq_cfg(irqd, MANAGED_IRQ_SHUTDOWN_VECTOR, cpu); | |
163 | } | |
164 | ||
165 | static int reserve_managed_vector(struct irq_data *irqd) | |
166 | { | |
167 | const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd); | |
168 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
169 | unsigned long flags; | |
170 | int ret; | |
171 | ||
172 | raw_spin_lock_irqsave(&vector_lock, flags); | |
173 | apicd->is_managed = true; | |
174 | ret = irq_matrix_reserve_managed(vector_matrix, affmsk); | |
175 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
176 | trace_vector_reserve_managed(irqd->irq, ret); | |
177 | return ret; | |
178 | } | |
179 | ||
4900be83 TG |
180 | static void reserve_irq_vector_locked(struct irq_data *irqd) |
181 | { | |
182 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
183 | ||
184 | irq_matrix_reserve(vector_matrix); | |
185 | apicd->can_reserve = true; | |
186 | apicd->has_reserved = true; | |
945f50a5 | 187 | irqd_set_can_reserve(irqd); |
4900be83 TG |
188 | trace_vector_reserve(irqd->irq, 0); |
189 | vector_assign_managed_shutdown(irqd); | |
190 | } | |
191 | ||
192 | static int reserve_irq_vector(struct irq_data *irqd) | |
193 | { | |
194 | unsigned long flags; | |
195 | ||
196 | raw_spin_lock_irqsave(&vector_lock, flags); | |
197 | reserve_irq_vector_locked(irqd); | |
198 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
199 | return 0; | |
200 | } | |
201 | ||
69cde000 TG |
202 | static int allocate_vector(struct irq_data *irqd, const struct cpumask *dest) |
203 | { | |
204 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
4900be83 | 205 | bool resvd = apicd->has_reserved; |
69cde000 | 206 | unsigned int cpu = apicd->cpu; |
ba224fea TG |
207 | int vector = apicd->vector; |
208 | ||
209 | lockdep_assert_held(&vector_lock); | |
74afab7a | 210 | |
3716fd27 | 211 | /* |
69cde000 TG |
212 | * If the current target CPU is online and in the new requested |
213 | * affinity mask, there is no point in moving the interrupt from | |
214 | * one CPU to another. | |
3716fd27 | 215 | */ |
69cde000 TG |
216 | if (vector && cpu_online(cpu) && cpumask_test_cpu(cpu, dest)) |
217 | return 0; | |
218 | ||
4900be83 | 219 | vector = irq_matrix_alloc(vector_matrix, dest, resvd, &cpu); |
69cde000 TG |
220 | if (vector > 0) |
221 | apic_update_vector(irqd, vector, cpu); | |
4900be83 | 222 | trace_vector_alloc(irqd->irq, vector, resvd, vector); |
69cde000 TG |
223 | return vector; |
224 | } | |
225 | ||
226 | static int assign_vector_locked(struct irq_data *irqd, | |
227 | const struct cpumask *dest) | |
228 | { | |
ba224fea | 229 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
69cde000 TG |
230 | int vector = allocate_vector(irqd, dest); |
231 | ||
232 | if (vector < 0) | |
233 | return vector; | |
234 | ||
ba224fea | 235 | apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu); |
3716fd27 | 236 | return 0; |
74afab7a JL |
237 | } |
238 | ||
69cde000 | 239 | static int assign_irq_vector(struct irq_data *irqd, const struct cpumask *dest) |
74afab7a | 240 | { |
74afab7a | 241 | unsigned long flags; |
69cde000 | 242 | int ret; |
74afab7a JL |
243 | |
244 | raw_spin_lock_irqsave(&vector_lock, flags); | |
69cde000 TG |
245 | cpumask_and(vector_searchmask, dest, cpu_online_mask); |
246 | ret = assign_vector_locked(irqd, vector_searchmask); | |
74afab7a | 247 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
69cde000 | 248 | return ret; |
74afab7a JL |
249 | } |
250 | ||
2db1f959 TG |
251 | static int assign_irq_vector_any_locked(struct irq_data *irqd) |
252 | { | |
d6ffc6ac TG |
253 | /* Get the affinity mask - either irq_default_affinity or (user) set */ |
254 | const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd); | |
2db1f959 TG |
255 | int node = irq_data_get_node(irqd); |
256 | ||
d6ffc6ac TG |
257 | if (node == NUMA_NO_NODE) |
258 | goto all; | |
259 | /* Try the intersection of @affmsk and node mask */ | |
260 | cpumask_and(vector_searchmask, cpumask_of_node(node), affmsk); | |
261 | if (!assign_vector_locked(irqd, vector_searchmask)) | |
262 | return 0; | |
263 | /* Try the node mask */ | |
264 | if (!assign_vector_locked(irqd, cpumask_of_node(node))) | |
265 | return 0; | |
266 | all: | |
267 | /* Try the full affinity mask */ | |
268 | cpumask_and(vector_searchmask, affmsk, cpu_online_mask); | |
269 | if (!assign_vector_locked(irqd, vector_searchmask)) | |
270 | return 0; | |
271 | /* Try the full online mask */ | |
2db1f959 TG |
272 | return assign_vector_locked(irqd, cpu_online_mask); |
273 | } | |
274 | ||
2db1f959 TG |
275 | static int |
276 | assign_irq_vector_policy(struct irq_data *irqd, struct irq_alloc_info *info) | |
486ca539 | 277 | { |
2db1f959 TG |
278 | if (irqd_affinity_is_managed(irqd)) |
279 | return reserve_managed_vector(irqd); | |
258d86ee | 280 | if (info->mask) |
69cde000 | 281 | return assign_irq_vector(irqd, info->mask); |
464d1230 TG |
282 | /* |
283 | * Make only a global reservation with no guarantee. A real vector | |
284 | * is associated at activation time. | |
285 | */ | |
4900be83 | 286 | return reserve_irq_vector(irqd); |
2db1f959 TG |
287 | } |
288 | ||
289 | static int | |
290 | assign_managed_vector(struct irq_data *irqd, const struct cpumask *dest) | |
291 | { | |
292 | const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd); | |
293 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
294 | int vector, cpu; | |
295 | ||
296 | cpumask_and(vector_searchmask, vector_searchmask, affmsk); | |
297 | cpu = cpumask_first(vector_searchmask); | |
298 | if (cpu >= nr_cpu_ids) | |
299 | return -EINVAL; | |
300 | /* set_affinity might call here for nothing */ | |
301 | if (apicd->vector && cpumask_test_cpu(apicd->cpu, vector_searchmask)) | |
486ca539 | 302 | return 0; |
2db1f959 TG |
303 | vector = irq_matrix_alloc_managed(vector_matrix, cpu); |
304 | trace_vector_alloc_managed(irqd->irq, vector, vector); | |
305 | if (vector < 0) | |
306 | return vector; | |
307 | apic_update_vector(irqd, vector, cpu); | |
308 | apic_update_irq_cfg(irqd, vector, cpu); | |
309 | return 0; | |
486ca539 JL |
310 | } |
311 | ||
69cde000 | 312 | static void clear_irq_vector(struct irq_data *irqd) |
74afab7a | 313 | { |
69cde000 | 314 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
2db1f959 | 315 | bool managed = irqd_affinity_is_managed(irqd); |
ba224fea | 316 | unsigned int vector = apicd->vector; |
74afab7a | 317 | |
69cde000 | 318 | lockdep_assert_held(&vector_lock); |
ba224fea | 319 | |
dccfe314 | 320 | if (!vector) |
1bdb8970 | 321 | return; |
74afab7a | 322 | |
ba224fea | 323 | trace_vector_clear(irqd->irq, vector, apicd->cpu, apicd->prev_vector, |
69cde000 TG |
324 | apicd->prev_cpu); |
325 | ||
dccfe314 | 326 | per_cpu(vector_irq, apicd->cpu)[vector] = VECTOR_UNUSED; |
2db1f959 | 327 | irq_matrix_free(vector_matrix, apicd->cpu, vector, managed); |
ba224fea | 328 | apicd->vector = 0; |
74afab7a | 329 | |
dccfe314 | 330 | /* Clean up move in progress */ |
ba224fea | 331 | vector = apicd->prev_vector; |
dccfe314 | 332 | if (!vector) |
74afab7a | 333 | return; |
74afab7a | 334 | |
dccfe314 | 335 | per_cpu(vector_irq, apicd->prev_cpu)[vector] = VECTOR_UNUSED; |
2db1f959 | 336 | irq_matrix_free(vector_matrix, apicd->prev_cpu, vector, managed); |
ba224fea | 337 | apicd->prev_vector = 0; |
86ba6551 | 338 | apicd->move_in_progress = 0; |
dccfe314 | 339 | hlist_del_init(&apicd->clist); |
74afab7a JL |
340 | } |
341 | ||
2db1f959 TG |
342 | static void x86_vector_deactivate(struct irq_domain *dom, struct irq_data *irqd) |
343 | { | |
344 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
345 | unsigned long flags; | |
346 | ||
347 | trace_vector_deactivate(irqd->irq, apicd->is_managed, | |
4900be83 | 348 | apicd->can_reserve, false); |
2db1f959 | 349 | |
4900be83 TG |
350 | /* Regular fixed assigned interrupt */ |
351 | if (!apicd->is_managed && !apicd->can_reserve) | |
352 | return; | |
353 | /* If the interrupt has a global reservation, nothing to do */ | |
354 | if (apicd->has_reserved) | |
2db1f959 TG |
355 | return; |
356 | ||
357 | raw_spin_lock_irqsave(&vector_lock, flags); | |
358 | clear_irq_vector(irqd); | |
4900be83 TG |
359 | if (apicd->can_reserve) |
360 | reserve_irq_vector_locked(irqd); | |
361 | else | |
362 | vector_assign_managed_shutdown(irqd); | |
2db1f959 TG |
363 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
364 | } | |
365 | ||
4900be83 TG |
366 | static int activate_reserved(struct irq_data *irqd) |
367 | { | |
368 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
369 | int ret; | |
370 | ||
371 | ret = assign_irq_vector_any_locked(irqd); | |
bc976233 | 372 | if (!ret) { |
4900be83 | 373 | apicd->has_reserved = false; |
bc976233 TG |
374 | /* |
375 | * Core might have disabled reservation mode after | |
376 | * allocating the irq descriptor. Ideally this should | |
377 | * happen before allocation time, but that would require | |
378 | * completely convoluted ways of transporting that | |
379 | * information. | |
380 | */ | |
381 | if (!irqd_can_reserve(irqd)) | |
382 | apicd->can_reserve = false; | |
383 | } | |
4900be83 TG |
384 | return ret; |
385 | } | |
386 | ||
2db1f959 TG |
387 | static int activate_managed(struct irq_data *irqd) |
388 | { | |
389 | const struct cpumask *dest = irq_data_get_affinity_mask(irqd); | |
390 | int ret; | |
391 | ||
392 | cpumask_and(vector_searchmask, dest, cpu_online_mask); | |
393 | if (WARN_ON_ONCE(cpumask_empty(vector_searchmask))) { | |
394 | /* Something in the core code broke! Survive gracefully */ | |
395 | pr_err("Managed startup for irq %u, but no CPU\n", irqd->irq); | |
396 | return EINVAL; | |
397 | } | |
398 | ||
399 | ret = assign_managed_vector(irqd, vector_searchmask); | |
400 | /* | |
401 | * This should not happen. The vector reservation got buggered. Handle | |
402 | * it gracefully. | |
403 | */ | |
404 | if (WARN_ON_ONCE(ret < 0)) { | |
405 | pr_err("Managed startup irq %u, no vector available\n", | |
406 | irqd->irq); | |
407 | } | |
408 | return ret; | |
409 | } | |
410 | ||
411 | static int x86_vector_activate(struct irq_domain *dom, struct irq_data *irqd, | |
702cb0a0 | 412 | bool reserve) |
2db1f959 TG |
413 | { |
414 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
415 | unsigned long flags; | |
416 | int ret = 0; | |
417 | ||
418 | trace_vector_activate(irqd->irq, apicd->is_managed, | |
702cb0a0 | 419 | apicd->can_reserve, reserve); |
2db1f959 | 420 | |
4900be83 TG |
421 | /* Nothing to do for fixed assigned vectors */ |
422 | if (!apicd->can_reserve && !apicd->is_managed) | |
2db1f959 TG |
423 | return 0; |
424 | ||
425 | raw_spin_lock_irqsave(&vector_lock, flags); | |
702cb0a0 | 426 | if (reserve || irqd_is_managed_and_shutdown(irqd)) |
2db1f959 | 427 | vector_assign_managed_shutdown(irqd); |
4900be83 | 428 | else if (apicd->is_managed) |
2db1f959 | 429 | ret = activate_managed(irqd); |
4900be83 TG |
430 | else if (apicd->has_reserved) |
431 | ret = activate_reserved(irqd); | |
2db1f959 TG |
432 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
433 | return ret; | |
434 | } | |
435 | ||
436 | static void vector_free_reserved_and_managed(struct irq_data *irqd) | |
437 | { | |
438 | const struct cpumask *dest = irq_data_get_affinity_mask(irqd); | |
439 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
440 | ||
4900be83 TG |
441 | trace_vector_teardown(irqd->irq, apicd->is_managed, |
442 | apicd->has_reserved); | |
2db1f959 | 443 | |
4900be83 TG |
444 | if (apicd->has_reserved) |
445 | irq_matrix_remove_reserved(vector_matrix); | |
2db1f959 TG |
446 | if (apicd->is_managed) |
447 | irq_matrix_remove_managed(vector_matrix, dest); | |
448 | } | |
449 | ||
b5dc8e6c JL |
450 | static void x86_vector_free_irqs(struct irq_domain *domain, |
451 | unsigned int virq, unsigned int nr_irqs) | |
452 | { | |
86ba6551 TG |
453 | struct apic_chip_data *apicd; |
454 | struct irq_data *irqd; | |
111abeba | 455 | unsigned long flags; |
b5dc8e6c JL |
456 | int i; |
457 | ||
458 | for (i = 0; i < nr_irqs; i++) { | |
86ba6551 TG |
459 | irqd = irq_domain_get_irq_data(x86_vector_domain, virq + i); |
460 | if (irqd && irqd->chip_data) { | |
111abeba | 461 | raw_spin_lock_irqsave(&vector_lock, flags); |
69cde000 | 462 | clear_irq_vector(irqd); |
2db1f959 | 463 | vector_free_reserved_and_managed(irqd); |
86ba6551 TG |
464 | apicd = irqd->chip_data; |
465 | irq_domain_reset_irq_data(irqd); | |
111abeba | 466 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
86ba6551 | 467 | free_apic_chip_data(apicd); |
b5dc8e6c JL |
468 | } |
469 | } | |
470 | } | |
471 | ||
464d1230 TG |
472 | static bool vector_configure_legacy(unsigned int virq, struct irq_data *irqd, |
473 | struct apic_chip_data *apicd) | |
474 | { | |
475 | unsigned long flags; | |
476 | bool realloc = false; | |
477 | ||
478 | apicd->vector = ISA_IRQ_VECTOR(virq); | |
479 | apicd->cpu = 0; | |
480 | ||
481 | raw_spin_lock_irqsave(&vector_lock, flags); | |
482 | /* | |
483 | * If the interrupt is activated, then it must stay at this vector | |
484 | * position. That's usually the timer interrupt (0). | |
485 | */ | |
486 | if (irqd_is_activated(irqd)) { | |
487 | trace_vector_setup(virq, true, 0); | |
488 | apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu); | |
489 | } else { | |
490 | /* Release the vector */ | |
491 | apicd->can_reserve = true; | |
945f50a5 | 492 | irqd_set_can_reserve(irqd); |
464d1230 TG |
493 | clear_irq_vector(irqd); |
494 | realloc = true; | |
495 | } | |
496 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
497 | return realloc; | |
498 | } | |
499 | ||
b5dc8e6c JL |
500 | static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, |
501 | unsigned int nr_irqs, void *arg) | |
502 | { | |
503 | struct irq_alloc_info *info = arg; | |
86ba6551 TG |
504 | struct apic_chip_data *apicd; |
505 | struct irq_data *irqd; | |
5f2dbbc5 | 506 | int i, err, node; |
b5dc8e6c JL |
507 | |
508 | if (disable_apic) | |
509 | return -ENXIO; | |
510 | ||
511 | /* Currently vector allocator can't guarantee contiguous allocations */ | |
512 | if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) | |
513 | return -ENOSYS; | |
514 | ||
b5dc8e6c | 515 | for (i = 0; i < nr_irqs; i++) { |
86ba6551 TG |
516 | irqd = irq_domain_get_irq_data(domain, virq + i); |
517 | BUG_ON(!irqd); | |
518 | node = irq_data_get_node(irqd); | |
4ef76eb6 TG |
519 | WARN_ON_ONCE(irqd->chip_data); |
520 | apicd = alloc_apic_chip_data(node); | |
86ba6551 | 521 | if (!apicd) { |
b5dc8e6c JL |
522 | err = -ENOMEM; |
523 | goto error; | |
524 | } | |
525 | ||
69cde000 | 526 | apicd->irq = virq + i; |
86ba6551 TG |
527 | irqd->chip = &lapic_controller; |
528 | irqd->chip_data = apicd; | |
529 | irqd->hwirq = virq + i; | |
530 | irqd_set_single_target(irqd); | |
4ef76eb6 | 531 | /* |
69cde000 TG |
532 | * Legacy vectors are already assigned when the IOAPIC |
533 | * takes them over. They stay on the same vector. This is | |
534 | * required for check_timer() to work correctly as it might | |
535 | * switch back to legacy mode. Only update the hardware | |
536 | * config. | |
4ef76eb6 TG |
537 | */ |
538 | if (info->flags & X86_IRQ_ALLOC_LEGACY) { | |
464d1230 TG |
539 | if (!vector_configure_legacy(virq + i, irqd, apicd)) |
540 | continue; | |
4ef76eb6 TG |
541 | } |
542 | ||
2db1f959 | 543 | err = assign_irq_vector_policy(irqd, info); |
69cde000 | 544 | trace_vector_setup(virq + i, false, err); |
b5dc8e6c JL |
545 | if (err) |
546 | goto error; | |
547 | } | |
548 | ||
549 | return 0; | |
550 | ||
551 | error: | |
552 | x86_vector_free_irqs(domain, virq, i + 1); | |
553 | return err; | |
554 | } | |
555 | ||
65d7ed57 | 556 | #ifdef CONFIG_GENERIC_IRQ_DEBUGFS |
d553d03f CIK |
557 | static void x86_vector_debug_show(struct seq_file *m, struct irq_domain *d, |
558 | struct irq_data *irqd, int ind) | |
65d7ed57 | 559 | { |
ba224fea | 560 | unsigned int cpu, vector, prev_cpu, prev_vector; |
65d7ed57 TG |
561 | struct apic_chip_data *apicd; |
562 | unsigned long flags; | |
563 | int irq; | |
564 | ||
565 | if (!irqd) { | |
566 | irq_matrix_debug_show(m, vector_matrix, ind); | |
567 | return; | |
568 | } | |
569 | ||
570 | irq = irqd->irq; | |
571 | if (irq < nr_legacy_irqs() && !test_bit(irq, &io_apic_irqs)) { | |
572 | seq_printf(m, "%*sVector: %5d\n", ind, "", ISA_IRQ_VECTOR(irq)); | |
573 | seq_printf(m, "%*sTarget: Legacy PIC all CPUs\n", ind, ""); | |
574 | return; | |
575 | } | |
576 | ||
577 | apicd = irqd->chip_data; | |
578 | if (!apicd) { | |
579 | seq_printf(m, "%*sVector: Not assigned\n", ind, ""); | |
580 | return; | |
581 | } | |
582 | ||
583 | raw_spin_lock_irqsave(&vector_lock, flags); | |
584 | cpu = apicd->cpu; | |
ba224fea | 585 | vector = apicd->vector; |
65d7ed57 | 586 | prev_cpu = apicd->prev_cpu; |
ba224fea | 587 | prev_vector = apicd->prev_vector; |
65d7ed57 | 588 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
ba224fea | 589 | seq_printf(m, "%*sVector: %5u\n", ind, "", vector); |
65d7ed57 | 590 | seq_printf(m, "%*sTarget: %5u\n", ind, "", cpu); |
ba224fea TG |
591 | if (prev_vector) { |
592 | seq_printf(m, "%*sPrevious vector: %5u\n", ind, "", prev_vector); | |
65d7ed57 TG |
593 | seq_printf(m, "%*sPrevious target: %5u\n", ind, "", prev_cpu); |
594 | } | |
595 | } | |
596 | #endif | |
597 | ||
eb18cf55 | 598 | static const struct irq_domain_ops x86_vector_domain_ops = { |
65d7ed57 TG |
599 | .alloc = x86_vector_alloc_irqs, |
600 | .free = x86_vector_free_irqs, | |
2db1f959 TG |
601 | .activate = x86_vector_activate, |
602 | .deactivate = x86_vector_deactivate, | |
65d7ed57 TG |
603 | #ifdef CONFIG_GENERIC_IRQ_DEBUGFS |
604 | .debug_show = x86_vector_debug_show, | |
605 | #endif | |
b5dc8e6c JL |
606 | }; |
607 | ||
11d686e9 JL |
608 | int __init arch_probe_nr_irqs(void) |
609 | { | |
610 | int nr; | |
611 | ||
612 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) | |
613 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
614 | ||
615 | nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; | |
fd2fa6c1 | 616 | #if defined(CONFIG_PCI_MSI) |
11d686e9 JL |
617 | /* |
618 | * for MSI and HT dyn irq | |
619 | */ | |
620 | if (gsi_top <= NR_IRQS_LEGACY) | |
621 | nr += 8 * nr_cpu_ids; | |
622 | else | |
623 | nr += gsi_top * 16; | |
624 | #endif | |
625 | if (nr < nr_irqs) | |
626 | nr_irqs = nr; | |
627 | ||
8c058b0b VK |
628 | /* |
629 | * We don't know if PIC is present at this point so we need to do | |
630 | * probe() to get the right number of legacy IRQs. | |
631 | */ | |
632 | return legacy_pic->probe(); | |
11d686e9 JL |
633 | } |
634 | ||
0fa115da TG |
635 | void lapic_assign_legacy_vector(unsigned int irq, bool replace) |
636 | { | |
637 | /* | |
638 | * Use assign system here so it wont get accounted as allocated | |
639 | * and moveable in the cpu hotplug check and it prevents managed | |
640 | * irq reservation from touching it. | |
641 | */ | |
642 | irq_matrix_assign_system(vector_matrix, ISA_IRQ_VECTOR(irq), replace); | |
643 | } | |
644 | ||
645 | void __init lapic_assign_system_vectors(void) | |
646 | { | |
647 | unsigned int i, vector = 0; | |
648 | ||
649 | for_each_set_bit_from(vector, system_vectors, NR_VECTORS) | |
650 | irq_matrix_assign_system(vector_matrix, vector, false); | |
651 | ||
652 | if (nr_legacy_irqs() > 1) | |
653 | lapic_assign_legacy_vector(PIC_CASCADE_IR, false); | |
654 | ||
655 | /* System vectors are reserved, online it */ | |
656 | irq_matrix_online(vector_matrix); | |
657 | ||
658 | /* Mark the preallocated legacy interrupts */ | |
659 | for (i = 0; i < nr_legacy_irqs(); i++) { | |
660 | if (i != PIC_CASCADE_IR) | |
661 | irq_matrix_assign(vector_matrix, ISA_IRQ_VECTOR(i)); | |
662 | } | |
663 | } | |
664 | ||
11d686e9 JL |
665 | int __init arch_early_irq_init(void) |
666 | { | |
9d35f859 TG |
667 | struct fwnode_handle *fn; |
668 | ||
9d35f859 TG |
669 | fn = irq_domain_alloc_named_fwnode("VECTOR"); |
670 | BUG_ON(!fn); | |
671 | x86_vector_domain = irq_domain_create_tree(fn, &x86_vector_domain_ops, | |
672 | NULL); | |
b5dc8e6c | 673 | BUG_ON(x86_vector_domain == NULL); |
9d35f859 | 674 | irq_domain_free_fwnode(fn); |
b5dc8e6c JL |
675 | irq_set_default_host(x86_vector_domain); |
676 | ||
52f518a3 JL |
677 | arch_init_msi_domain(x86_vector_domain); |
678 | ||
3716fd27 | 679 | BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL)); |
f7fa7aee | 680 | |
0fa115da TG |
681 | /* |
682 | * Allocate the vector matrix allocator data structure and limit the | |
683 | * search area. | |
684 | */ | |
685 | vector_matrix = irq_alloc_matrix(NR_VECTORS, FIRST_EXTERNAL_VECTOR, | |
686 | FIRST_SYSTEM_VECTOR); | |
687 | BUG_ON(!vector_matrix); | |
688 | ||
11d686e9 JL |
689 | return arch_early_ioapic_init(); |
690 | } | |
691 | ||
ba801640 | 692 | #ifdef CONFIG_SMP |
74afab7a | 693 | |
f0cc6cca TG |
694 | static struct irq_desc *__setup_vector_irq(int vector) |
695 | { | |
696 | int isairq = vector - ISA_IRQ_VECTOR(0); | |
697 | ||
698 | /* Check whether the irq is in the legacy space */ | |
699 | if (isairq < 0 || isairq >= nr_legacy_irqs()) | |
700 | return VECTOR_UNUSED; | |
701 | /* Check whether the irq is handled by the IOAPIC */ | |
702 | if (test_bit(isairq, &io_apic_irqs)) | |
703 | return VECTOR_UNUSED; | |
704 | return irq_to_desc(isairq); | |
705 | } | |
706 | ||
0fa115da TG |
707 | /* Online the local APIC infrastructure and initialize the vectors */ |
708 | void lapic_online(void) | |
74afab7a | 709 | { |
f0cc6cca | 710 | unsigned int vector; |
74afab7a | 711 | |
5a3f75e3 | 712 | lockdep_assert_held(&vector_lock); |
0fa115da TG |
713 | |
714 | /* Online the vector matrix array for this CPU */ | |
715 | irq_matrix_online(vector_matrix); | |
716 | ||
74afab7a | 717 | /* |
f0cc6cca TG |
718 | * The interrupt affinity logic never targets interrupts to offline |
719 | * CPUs. The exception are the legacy PIC interrupts. In general | |
720 | * they are only targeted to CPU0, but depending on the platform | |
721 | * they can be distributed to any online CPU in hardware. The | |
722 | * kernel has no influence on that. So all active legacy vectors | |
723 | * must be installed on all CPUs. All non legacy interrupts can be | |
724 | * cleared. | |
74afab7a | 725 | */ |
f0cc6cca TG |
726 | for (vector = 0; vector < NR_VECTORS; vector++) |
727 | this_cpu_write(vector_irq[vector], __setup_vector_irq(vector)); | |
74afab7a JL |
728 | } |
729 | ||
0fa115da TG |
730 | void lapic_offline(void) |
731 | { | |
732 | lock_vector_lock(); | |
733 | irq_matrix_offline(vector_matrix); | |
734 | unlock_vector_lock(); | |
735 | } | |
736 | ||
ba801640 TG |
737 | static int apic_set_affinity(struct irq_data *irqd, |
738 | const struct cpumask *dest, bool force) | |
739 | { | |
02edee15 | 740 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
ba801640 TG |
741 | int err; |
742 | ||
02edee15 TG |
743 | /* |
744 | * Core code can call here for inactive interrupts. For inactive | |
745 | * interrupts which use managed or reservation mode there is no | |
746 | * point in going through the vector assignment right now as the | |
747 | * activation will assign a vector which fits the destination | |
748 | * cpumask. Let the core code store the destination mask and be | |
749 | * done with it. | |
750 | */ | |
751 | if (!irqd_is_activated(irqd) && | |
752 | (apicd->is_managed || apicd->can_reserve)) | |
753 | return IRQ_SET_MASK_OK; | |
754 | ||
2db1f959 TG |
755 | raw_spin_lock(&vector_lock); |
756 | cpumask_and(vector_searchmask, dest, cpu_online_mask); | |
757 | if (irqd_affinity_is_managed(irqd)) | |
758 | err = assign_managed_vector(irqd, vector_searchmask); | |
759 | else | |
760 | err = assign_vector_locked(irqd, vector_searchmask); | |
761 | raw_spin_unlock(&vector_lock); | |
ba801640 TG |
762 | return err ? err : IRQ_SET_MASK_OK; |
763 | } | |
764 | ||
765 | #else | |
766 | # define apic_set_affinity NULL | |
767 | #endif | |
768 | ||
86ba6551 | 769 | static int apic_retrigger_irq(struct irq_data *irqd) |
74afab7a | 770 | { |
86ba6551 | 771 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
74afab7a | 772 | unsigned long flags; |
74afab7a JL |
773 | |
774 | raw_spin_lock_irqsave(&vector_lock, flags); | |
ba224fea | 775 | apic->send_IPI(apicd->cpu, apicd->vector); |
74afab7a JL |
776 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
777 | ||
778 | return 1; | |
779 | } | |
780 | ||
86ba6551 | 781 | void apic_ack_edge(struct irq_data *irqd) |
74afab7a | 782 | { |
86ba6551 TG |
783 | irq_complete_move(irqd_cfg(irqd)); |
784 | irq_move_irq(irqd); | |
74afab7a JL |
785 | ack_APIC_irq(); |
786 | } | |
787 | ||
b5dc8e6c | 788 | static struct irq_chip lapic_controller = { |
8947dfb2 | 789 | .name = "APIC", |
b5dc8e6c | 790 | .irq_ack = apic_ack_edge, |
68f9f440 | 791 | .irq_set_affinity = apic_set_affinity, |
b5dc8e6c JL |
792 | .irq_retrigger = apic_retrigger_irq, |
793 | }; | |
794 | ||
74afab7a | 795 | #ifdef CONFIG_SMP |
c6c2002b | 796 | |
69cde000 TG |
797 | static void free_moved_vector(struct apic_chip_data *apicd) |
798 | { | |
ba224fea | 799 | unsigned int vector = apicd->prev_vector; |
69cde000 | 800 | unsigned int cpu = apicd->prev_cpu; |
2db1f959 TG |
801 | bool managed = apicd->is_managed; |
802 | ||
803 | /* | |
804 | * This should never happen. Managed interrupts are not | |
805 | * migrated except on CPU down, which does not involve the | |
806 | * cleanup vector. But try to keep the accounting correct | |
807 | * nevertheless. | |
808 | */ | |
809 | WARN_ON_ONCE(managed); | |
69cde000 | 810 | |
0696d059 | 811 | trace_vector_free_moved(apicd->irq, cpu, vector, managed); |
2db1f959 | 812 | irq_matrix_free(vector_matrix, cpu, vector, managed); |
0696d059 | 813 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; |
69cde000 | 814 | hlist_del_init(&apicd->clist); |
ba224fea | 815 | apicd->prev_vector = 0; |
69cde000 TG |
816 | apicd->move_in_progress = 0; |
817 | } | |
818 | ||
c4158ff5 | 819 | asmlinkage __visible void __irq_entry smp_irq_move_cleanup_interrupt(void) |
74afab7a | 820 | { |
dccfe314 TG |
821 | struct hlist_head *clhead = this_cpu_ptr(&cleanup_list); |
822 | struct apic_chip_data *apicd; | |
823 | struct hlist_node *tmp; | |
74afab7a | 824 | |
6af7faf6 | 825 | entering_ack_irq(); |
df54c493 TG |
826 | /* Prevent vectors vanishing under us */ |
827 | raw_spin_lock(&vector_lock); | |
828 | ||
dccfe314 | 829 | hlist_for_each_entry_safe(apicd, tmp, clhead, clist) { |
ba224fea | 830 | unsigned int irr, vector = apicd->prev_vector; |
74afab7a | 831 | |
74afab7a | 832 | /* |
dccfe314 TG |
833 | * Paranoia: Check if the vector that needs to be cleaned |
834 | * up is registered at the APICs IRR. If so, then this is | |
835 | * not the best time to clean it up. Clean it up in the | |
74afab7a | 836 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR |
dccfe314 TG |
837 | * to this CPU. IRQ_MOVE_CLEANUP_VECTOR is the lowest |
838 | * priority external vector, so on return from this | |
839 | * interrupt the device interrupt will happen first. | |
74afab7a | 840 | */ |
dccfe314 TG |
841 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
842 | if (irr & (1U << (vector % 32))) { | |
74afab7a | 843 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); |
dccfe314 | 844 | continue; |
74afab7a | 845 | } |
69cde000 | 846 | free_moved_vector(apicd); |
74afab7a JL |
847 | } |
848 | ||
df54c493 | 849 | raw_spin_unlock(&vector_lock); |
6af7faf6 | 850 | exiting_irq(); |
74afab7a JL |
851 | } |
852 | ||
dccfe314 TG |
853 | static void __send_cleanup_vector(struct apic_chip_data *apicd) |
854 | { | |
855 | unsigned int cpu; | |
856 | ||
857 | raw_spin_lock(&vector_lock); | |
858 | apicd->move_in_progress = 0; | |
859 | cpu = apicd->prev_cpu; | |
860 | if (cpu_online(cpu)) { | |
861 | hlist_add_head(&apicd->clist, per_cpu_ptr(&cleanup_list, cpu)); | |
862 | apic->send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR); | |
863 | } else { | |
ba224fea | 864 | apicd->prev_vector = 0; |
dccfe314 TG |
865 | } |
866 | raw_spin_unlock(&vector_lock); | |
867 | } | |
868 | ||
869 | void send_cleanup_vector(struct irq_cfg *cfg) | |
870 | { | |
871 | struct apic_chip_data *apicd; | |
872 | ||
ba224fea | 873 | apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg); |
dccfe314 TG |
874 | if (apicd->move_in_progress) |
875 | __send_cleanup_vector(apicd); | |
876 | } | |
877 | ||
74afab7a JL |
878 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) |
879 | { | |
86ba6551 | 880 | struct apic_chip_data *apicd; |
74afab7a | 881 | |
ba224fea | 882 | apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg); |
86ba6551 | 883 | if (likely(!apicd->move_in_progress)) |
74afab7a JL |
884 | return; |
885 | ||
ba224fea | 886 | if (vector == apicd->vector && apicd->cpu == smp_processor_id()) |
86ba6551 | 887 | __send_cleanup_vector(apicd); |
74afab7a JL |
888 | } |
889 | ||
890 | void irq_complete_move(struct irq_cfg *cfg) | |
891 | { | |
892 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); | |
893 | } | |
894 | ||
90a2282e | 895 | /* |
551adc60 | 896 | * Called from fixup_irqs() with @desc->lock held and interrupts disabled. |
90a2282e TG |
897 | */ |
898 | void irq_force_complete_move(struct irq_desc *desc) | |
74afab7a | 899 | { |
86ba6551 | 900 | struct apic_chip_data *apicd; |
dccfe314 TG |
901 | struct irq_data *irqd; |
902 | unsigned int vector; | |
56d7d2f4 | 903 | |
db91aa79 MW |
904 | /* |
905 | * The function is called for all descriptors regardless of which | |
906 | * irqdomain they belong to. For example if an IRQ is provided by | |
907 | * an irq_chip as part of a GPIO driver, the chip data for that | |
908 | * descriptor is specific to the irq_chip in question. | |
909 | * | |
910 | * Check first that the chip_data is what we expect | |
911 | * (apic_chip_data) before touching it any further. | |
912 | */ | |
86ba6551 | 913 | irqd = irq_domain_get_irq_data(x86_vector_domain, |
dccfe314 | 914 | irq_desc_get_irq(desc)); |
86ba6551 | 915 | if (!irqd) |
db91aa79 MW |
916 | return; |
917 | ||
dccfe314 | 918 | raw_spin_lock(&vector_lock); |
86ba6551 | 919 | apicd = apic_chip_data(irqd); |
dccfe314 TG |
920 | if (!apicd) |
921 | goto unlock; | |
db91aa79 | 922 | |
dccfe314 | 923 | /* |
ba224fea | 924 | * If prev_vector is empty, no action required. |
dccfe314 | 925 | */ |
ba224fea | 926 | vector = apicd->prev_vector; |
dccfe314 TG |
927 | if (!vector) |
928 | goto unlock; | |
74afab7a | 929 | |
56d7d2f4 | 930 | /* |
dccfe314 | 931 | * This is tricky. If the cleanup of the old vector has not been |
98229aa3 TG |
932 | * done yet, then the following setaffinity call will fail with |
933 | * -EBUSY. This can leave the interrupt in a stale state. | |
934 | * | |
551adc60 TG |
935 | * All CPUs are stuck in stop machine with interrupts disabled so |
936 | * calling __irq_complete_move() would be completely pointless. | |
dccfe314 | 937 | * |
551adc60 TG |
938 | * 1) The interrupt is in move_in_progress state. That means that we |
939 | * have not seen an interrupt since the io_apic was reprogrammed to | |
940 | * the new vector. | |
941 | * | |
942 | * 2) The interrupt has fired on the new vector, but the cleanup IPIs | |
943 | * have not been processed yet. | |
944 | */ | |
86ba6551 | 945 | if (apicd->move_in_progress) { |
98229aa3 | 946 | /* |
551adc60 TG |
947 | * In theory there is a race: |
948 | * | |
949 | * set_ioapic(new_vector) <-- Interrupt is raised before update | |
950 | * is effective, i.e. it's raised on | |
951 | * the old vector. | |
952 | * | |
953 | * So if the target cpu cannot handle that interrupt before | |
954 | * the old vector is cleaned up, we get a spurious interrupt | |
955 | * and in the worst case the ioapic irq line becomes stale. | |
956 | * | |
957 | * But in case of cpu hotplug this should be a non issue | |
958 | * because if the affinity update happens right before all | |
959 | * cpus rendevouz in stop machine, there is no way that the | |
960 | * interrupt can be blocked on the target cpu because all cpus | |
961 | * loops first with interrupts enabled in stop machine, so the | |
962 | * old vector is not yet cleaned up when the interrupt fires. | |
963 | * | |
964 | * So the only way to run into this issue is if the delivery | |
965 | * of the interrupt on the apic/system bus would be delayed | |
966 | * beyond the point where the target cpu disables interrupts | |
967 | * in stop machine. I doubt that it can happen, but at least | |
968 | * there is a theroretical chance. Virtualization might be | |
969 | * able to expose this, but AFAICT the IOAPIC emulation is not | |
970 | * as stupid as the real hardware. | |
971 | * | |
972 | * Anyway, there is nothing we can do about that at this point | |
973 | * w/o refactoring the whole fixup_irq() business completely. | |
974 | * We print at least the irq number and the old vector number, | |
975 | * so we have the necessary information when a problem in that | |
976 | * area arises. | |
98229aa3 | 977 | */ |
551adc60 | 978 | pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n", |
dccfe314 | 979 | irqd->irq, vector); |
98229aa3 | 980 | } |
69cde000 | 981 | free_moved_vector(apicd); |
dccfe314 | 982 | unlock: |
56d7d2f4 | 983 | raw_spin_unlock(&vector_lock); |
74afab7a | 984 | } |
2cffad7b TG |
985 | |
986 | #ifdef CONFIG_HOTPLUG_CPU | |
987 | /* | |
988 | * Note, this is not accurate accounting, but at least good enough to | |
989 | * prevent that the actual interrupt move will run out of vectors. | |
990 | */ | |
991 | int lapic_can_unplug_cpu(void) | |
992 | { | |
993 | unsigned int rsvd, avl, tomove, cpu = smp_processor_id(); | |
994 | int ret = 0; | |
995 | ||
996 | raw_spin_lock(&vector_lock); | |
997 | tomove = irq_matrix_allocated(vector_matrix); | |
998 | avl = irq_matrix_available(vector_matrix, true); | |
999 | if (avl < tomove) { | |
1000 | pr_warn("CPU %u has %u vectors, %u available. Cannot disable CPU\n", | |
1001 | cpu, tomove, avl); | |
1002 | ret = -ENOSPC; | |
1003 | goto out; | |
1004 | } | |
1005 | rsvd = irq_matrix_reserved(vector_matrix); | |
1006 | if (avl < rsvd) { | |
1007 | pr_warn("Reserved vectors %u > available %u. IRQ request may fail\n", | |
1008 | rsvd, avl); | |
1009 | } | |
1010 | out: | |
1011 | raw_spin_unlock(&vector_lock); | |
1012 | return ret; | |
1013 | } | |
1014 | #endif /* HOTPLUG_CPU */ | |
1015 | #endif /* SMP */ | |
74afab7a | 1016 | |
74afab7a JL |
1017 | static void __init print_APIC_field(int base) |
1018 | { | |
1019 | int i; | |
1020 | ||
1021 | printk(KERN_DEBUG); | |
1022 | ||
1023 | for (i = 0; i < 8; i++) | |
1024 | pr_cont("%08x", apic_read(base + i*0x10)); | |
1025 | ||
1026 | pr_cont("\n"); | |
1027 | } | |
1028 | ||
1029 | static void __init print_local_APIC(void *dummy) | |
1030 | { | |
1031 | unsigned int i, v, ver, maxlvt; | |
1032 | u64 icr; | |
1033 | ||
849d3569 JL |
1034 | pr_debug("printing local APIC contents on CPU#%d/%d:\n", |
1035 | smp_processor_id(), hard_smp_processor_id()); | |
74afab7a | 1036 | v = apic_read(APIC_ID); |
849d3569 | 1037 | pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
74afab7a | 1038 | v = apic_read(APIC_LVR); |
849d3569 | 1039 | pr_info("... APIC VERSION: %08x\n", v); |
74afab7a JL |
1040 | ver = GET_APIC_VERSION(v); |
1041 | maxlvt = lapic_get_maxlvt(); | |
1042 | ||
1043 | v = apic_read(APIC_TASKPRI); | |
849d3569 | 1044 | pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); |
74afab7a JL |
1045 | |
1046 | /* !82489DX */ | |
1047 | if (APIC_INTEGRATED(ver)) { | |
1048 | if (!APIC_XAPIC(ver)) { | |
1049 | v = apic_read(APIC_ARBPRI); | |
849d3569 JL |
1050 | pr_debug("... APIC ARBPRI: %08x (%02x)\n", |
1051 | v, v & APIC_ARBPRI_MASK); | |
74afab7a JL |
1052 | } |
1053 | v = apic_read(APIC_PROCPRI); | |
849d3569 | 1054 | pr_debug("... APIC PROCPRI: %08x\n", v); |
74afab7a JL |
1055 | } |
1056 | ||
1057 | /* | |
1058 | * Remote read supported only in the 82489DX and local APIC for | |
1059 | * Pentium processors. | |
1060 | */ | |
1061 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1062 | v = apic_read(APIC_RRR); | |
849d3569 | 1063 | pr_debug("... APIC RRR: %08x\n", v); |
74afab7a JL |
1064 | } |
1065 | ||
1066 | v = apic_read(APIC_LDR); | |
849d3569 | 1067 | pr_debug("... APIC LDR: %08x\n", v); |
74afab7a JL |
1068 | if (!x2apic_enabled()) { |
1069 | v = apic_read(APIC_DFR); | |
849d3569 | 1070 | pr_debug("... APIC DFR: %08x\n", v); |
74afab7a JL |
1071 | } |
1072 | v = apic_read(APIC_SPIV); | |
849d3569 | 1073 | pr_debug("... APIC SPIV: %08x\n", v); |
74afab7a | 1074 | |
849d3569 | 1075 | pr_debug("... APIC ISR field:\n"); |
74afab7a | 1076 | print_APIC_field(APIC_ISR); |
849d3569 | 1077 | pr_debug("... APIC TMR field:\n"); |
74afab7a | 1078 | print_APIC_field(APIC_TMR); |
849d3569 | 1079 | pr_debug("... APIC IRR field:\n"); |
74afab7a JL |
1080 | print_APIC_field(APIC_IRR); |
1081 | ||
1082 | /* !82489DX */ | |
1083 | if (APIC_INTEGRATED(ver)) { | |
1084 | /* Due to the Pentium erratum 3AP. */ | |
1085 | if (maxlvt > 3) | |
1086 | apic_write(APIC_ESR, 0); | |
1087 | ||
1088 | v = apic_read(APIC_ESR); | |
849d3569 | 1089 | pr_debug("... APIC ESR: %08x\n", v); |
74afab7a JL |
1090 | } |
1091 | ||
1092 | icr = apic_icr_read(); | |
849d3569 JL |
1093 | pr_debug("... APIC ICR: %08x\n", (u32)icr); |
1094 | pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
74afab7a JL |
1095 | |
1096 | v = apic_read(APIC_LVTT); | |
849d3569 | 1097 | pr_debug("... APIC LVTT: %08x\n", v); |
74afab7a JL |
1098 | |
1099 | if (maxlvt > 3) { | |
1100 | /* PC is LVT#4. */ | |
1101 | v = apic_read(APIC_LVTPC); | |
849d3569 | 1102 | pr_debug("... APIC LVTPC: %08x\n", v); |
74afab7a JL |
1103 | } |
1104 | v = apic_read(APIC_LVT0); | |
849d3569 | 1105 | pr_debug("... APIC LVT0: %08x\n", v); |
74afab7a | 1106 | v = apic_read(APIC_LVT1); |
849d3569 | 1107 | pr_debug("... APIC LVT1: %08x\n", v); |
74afab7a JL |
1108 | |
1109 | if (maxlvt > 2) { | |
1110 | /* ERR is LVT#3. */ | |
1111 | v = apic_read(APIC_LVTERR); | |
849d3569 | 1112 | pr_debug("... APIC LVTERR: %08x\n", v); |
74afab7a JL |
1113 | } |
1114 | ||
1115 | v = apic_read(APIC_TMICT); | |
849d3569 | 1116 | pr_debug("... APIC TMICT: %08x\n", v); |
74afab7a | 1117 | v = apic_read(APIC_TMCCT); |
849d3569 | 1118 | pr_debug("... APIC TMCCT: %08x\n", v); |
74afab7a | 1119 | v = apic_read(APIC_TDCR); |
849d3569 | 1120 | pr_debug("... APIC TDCR: %08x\n", v); |
74afab7a JL |
1121 | |
1122 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1123 | v = apic_read(APIC_EFEAT); | |
1124 | maxlvt = (v >> 16) & 0xff; | |
849d3569 | 1125 | pr_debug("... APIC EFEAT: %08x\n", v); |
74afab7a | 1126 | v = apic_read(APIC_ECTRL); |
849d3569 | 1127 | pr_debug("... APIC ECTRL: %08x\n", v); |
74afab7a JL |
1128 | for (i = 0; i < maxlvt; i++) { |
1129 | v = apic_read(APIC_EILVTn(i)); | |
849d3569 | 1130 | pr_debug("... APIC EILVT%d: %08x\n", i, v); |
74afab7a JL |
1131 | } |
1132 | } | |
1133 | pr_cont("\n"); | |
1134 | } | |
1135 | ||
1136 | static void __init print_local_APICs(int maxcpu) | |
1137 | { | |
1138 | int cpu; | |
1139 | ||
1140 | if (!maxcpu) | |
1141 | return; | |
1142 | ||
1143 | preempt_disable(); | |
1144 | for_each_online_cpu(cpu) { | |
1145 | if (cpu >= maxcpu) | |
1146 | break; | |
1147 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1148 | } | |
1149 | preempt_enable(); | |
1150 | } | |
1151 | ||
1152 | static void __init print_PIC(void) | |
1153 | { | |
1154 | unsigned int v; | |
1155 | unsigned long flags; | |
1156 | ||
1157 | if (!nr_legacy_irqs()) | |
1158 | return; | |
1159 | ||
849d3569 | 1160 | pr_debug("\nprinting PIC contents\n"); |
74afab7a JL |
1161 | |
1162 | raw_spin_lock_irqsave(&i8259A_lock, flags); | |
1163 | ||
1164 | v = inb(0xa1) << 8 | inb(0x21); | |
849d3569 | 1165 | pr_debug("... PIC IMR: %04x\n", v); |
74afab7a JL |
1166 | |
1167 | v = inb(0xa0) << 8 | inb(0x20); | |
849d3569 | 1168 | pr_debug("... PIC IRR: %04x\n", v); |
74afab7a JL |
1169 | |
1170 | outb(0x0b, 0xa0); | |
1171 | outb(0x0b, 0x20); | |
1172 | v = inb(0xa0) << 8 | inb(0x20); | |
1173 | outb(0x0a, 0xa0); | |
1174 | outb(0x0a, 0x20); | |
1175 | ||
1176 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); | |
1177 | ||
849d3569 | 1178 | pr_debug("... PIC ISR: %04x\n", v); |
74afab7a JL |
1179 | |
1180 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
849d3569 | 1181 | pr_debug("... PIC ELCR: %04x\n", v); |
74afab7a JL |
1182 | } |
1183 | ||
1184 | static int show_lapic __initdata = 1; | |
1185 | static __init int setup_show_lapic(char *arg) | |
1186 | { | |
1187 | int num = -1; | |
1188 | ||
1189 | if (strcmp(arg, "all") == 0) { | |
1190 | show_lapic = CONFIG_NR_CPUS; | |
1191 | } else { | |
1192 | get_option(&arg, &num); | |
1193 | if (num >= 0) | |
1194 | show_lapic = num; | |
1195 | } | |
1196 | ||
1197 | return 1; | |
1198 | } | |
1199 | __setup("show_lapic=", setup_show_lapic); | |
1200 | ||
1201 | static int __init print_ICs(void) | |
1202 | { | |
1203 | if (apic_verbosity == APIC_QUIET) | |
1204 | return 0; | |
1205 | ||
1206 | print_PIC(); | |
1207 | ||
1208 | /* don't print out if apic is not there */ | |
93984fbd | 1209 | if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) |
74afab7a JL |
1210 | return 0; |
1211 | ||
1212 | print_local_APICs(show_lapic); | |
1213 | print_IO_APICs(); | |
1214 | ||
1215 | return 0; | |
1216 | } | |
1217 | ||
1218 | late_initcall(print_ICs); |