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1da177e4 LT |
1 | #include <linux/init.h> |
2 | #include <linux/string.h> | |
3 | #include <linux/delay.h> | |
4 | #include <linux/smp.h> | |
5 | #include <linux/module.h> | |
6 | #include <linux/percpu.h> | |
2b932f6c | 7 | #include <linux/bootmem.h> |
1da177e4 LT |
8 | #include <asm/processor.h> |
9 | #include <asm/i387.h> | |
10 | #include <asm/msr.h> | |
11 | #include <asm/io.h> | |
12 | #include <asm/mmu_context.h> | |
27b07da7 | 13 | #include <asm/mtrr.h> |
a03a3e28 | 14 | #include <asm/mce.h> |
8d4a4300 | 15 | #include <asm/pat.h> |
7e00df58 | 16 | #include <asm/asm.h> |
1da177e4 LT |
17 | #ifdef CONFIG_X86_LOCAL_APIC |
18 | #include <asm/mpspec.h> | |
19 | #include <asm/apic.h> | |
20 | #include <mach_apic.h> | |
21 | #endif | |
22 | ||
23 | #include "cpu.h" | |
24 | ||
7a61d35d | 25 | DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = { |
6842ef0e GOC |
26 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
27 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
28 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
29 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
30 | /* |
31 | * Segments used for calling PnP BIOS have byte granularity. | |
32 | * They code segments and data segments have fixed 64k limits, | |
33 | * the transfer segment sizes are set at run time. | |
34 | */ | |
6842ef0e GOC |
35 | /* 32-bit code */ |
36 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
37 | /* 16-bit code */ | |
38 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
39 | /* 16-bit data */ | |
40 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
41 | /* 16-bit data */ | |
42 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
43 | /* 16-bit data */ | |
44 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
bf504672 RR |
45 | /* |
46 | * The APM segments have byte granularity and their bases | |
47 | * are set at run time. All have 64k limits. | |
48 | */ | |
6842ef0e GOC |
49 | /* 32-bit code */ |
50 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
bf504672 | 51 | /* 16-bit code */ |
6842ef0e GOC |
52 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
53 | /* data */ | |
54 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
bf504672 | 55 | |
6842ef0e GOC |
56 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
57 | [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } }, | |
7a61d35d JF |
58 | } }; |
59 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); | |
ae1ee11b | 60 | |
7d851c8d AK |
61 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
62 | ||
9d31d35b YL |
63 | /* Current gdt points %fs at the "master" per-cpu area: after this, |
64 | * it's on the real one. */ | |
65 | void switch_to_new_gdt(void) | |
66 | { | |
67 | struct desc_ptr gdt_descr; | |
68 | ||
69 | gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id()); | |
70 | gdt_descr.size = GDT_SIZE - 1; | |
71 | load_gdt(&gdt_descr); | |
72 | asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory"); | |
73 | } | |
74 | ||
3bc9b76b | 75 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 76 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 77 | |
10a434fc | 78 | static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 79 | |
34048c9e | 80 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
1da177e4 LT |
81 | { |
82 | /* Not much we can do here... */ | |
83 | /* Check if at least it has cpuid */ | |
84 | if (c->cpuid_level == -1) { | |
85 | /* No cpuid. It must be an ancient CPU */ | |
86 | if (c->x86 == 4) | |
87 | strcpy(c->x86_model_id, "486"); | |
88 | else if (c->x86 == 3) | |
89 | strcpy(c->x86_model_id, "386"); | |
90 | } | |
91 | } | |
92 | ||
95414930 | 93 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 94 | .c_init = default_init, |
fe38d855 | 95 | .c_vendor = "Unknown", |
10a434fc | 96 | .c_x86_vendor = X86_VENDOR_UNKNOWN, |
1da177e4 | 97 | }; |
10a434fc | 98 | static struct cpu_dev *this_cpu __cpuinitdata; |
1da177e4 LT |
99 | |
100 | static int __init cachesize_setup(char *str) | |
101 | { | |
34048c9e | 102 | get_option(&str, &cachesize_override); |
1da177e4 LT |
103 | return 1; |
104 | } | |
105 | __setup("cachesize=", cachesize_setup); | |
106 | ||
3bc9b76b | 107 | int __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
108 | { |
109 | unsigned int *v; | |
110 | char *p, *q; | |
111 | ||
3da99c97 | 112 | if (c->extended_cpuid_level < 0x80000004) |
1da177e4 LT |
113 | return 0; |
114 | ||
115 | v = (unsigned int *) c->x86_model_id; | |
116 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
117 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
118 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
119 | c->x86_model_id[48] = 0; | |
120 | ||
121 | /* Intel chips right-justify this string for some dumb reason; | |
122 | undo that brain damage */ | |
123 | p = q = &c->x86_model_id[0]; | |
34048c9e | 124 | while (*p == ' ') |
1da177e4 | 125 | p++; |
34048c9e PC |
126 | if (p != q) { |
127 | while (*p) | |
1da177e4 | 128 | *q++ = *p++; |
34048c9e | 129 | while (q <= &c->x86_model_id[48]) |
1da177e4 LT |
130 | *q++ = '\0'; /* Zero-pad the rest */ |
131 | } | |
132 | ||
133 | return 1; | |
134 | } | |
135 | ||
136 | ||
3bc9b76b | 137 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 | 138 | { |
9d31d35b | 139 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 140 | |
3da99c97 | 141 | n = c->extended_cpuid_level; |
1da177e4 LT |
142 | |
143 | if (n >= 0x80000005) { | |
9d31d35b | 144 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 145 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
9d31d35b YL |
146 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); |
147 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
1da177e4 LT |
148 | } |
149 | ||
150 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
151 | return; | |
152 | ||
153 | ecx = cpuid_ecx(0x80000006); | |
154 | l2size = ecx >> 16; | |
34048c9e | 155 | |
1da177e4 LT |
156 | /* do processor-specific cache resizing */ |
157 | if (this_cpu->c_size_cache) | |
34048c9e | 158 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
159 | |
160 | /* Allow user to override all this if necessary. */ | |
161 | if (cachesize_override != -1) | |
162 | l2size = cachesize_override; | |
163 | ||
34048c9e | 164 | if (l2size == 0) |
1da177e4 LT |
165 | return; /* Again, no L2 cache is possible */ |
166 | ||
167 | c->x86_cache_size = l2size; | |
168 | ||
169 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
170 | l2size, ecx & 0xFF); | |
171 | } | |
172 | ||
34048c9e PC |
173 | /* |
174 | * Naming convention should be: <Name> [(<Codename>)] | |
175 | * This table only is used unless init_<vendor>() below doesn't set it; | |
176 | * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used | |
177 | * | |
178 | */ | |
1da177e4 LT |
179 | |
180 | /* Look up CPU names by table lookup. */ | |
3bc9b76b | 181 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) |
1da177e4 LT |
182 | { |
183 | struct cpu_model_info *info; | |
184 | ||
34048c9e | 185 | if (c->x86_model >= 16) |
1da177e4 LT |
186 | return NULL; /* Range check */ |
187 | ||
188 | if (!this_cpu) | |
189 | return NULL; | |
190 | ||
191 | info = this_cpu->c_models; | |
192 | ||
193 | while (info && info->family) { | |
194 | if (info->family == c->x86) | |
195 | return info->model_names[c->x86_model]; | |
196 | info++; | |
197 | } | |
198 | return NULL; /* Not found */ | |
199 | } | |
200 | ||
9d31d35b YL |
201 | #ifdef CONFIG_X86_HT |
202 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) | |
203 | { | |
204 | u32 eax, ebx, ecx, edx; | |
205 | int index_msb, core_bits; | |
206 | ||
207 | cpuid(1, &eax, &ebx, &ecx, &edx); | |
208 | ||
209 | if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY)) | |
210 | return; | |
211 | ||
212 | smp_num_siblings = (ebx & 0xff0000) >> 16; | |
213 | ||
214 | if (smp_num_siblings == 1) { | |
215 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
216 | } else if (smp_num_siblings > 1) { | |
217 | ||
218 | if (smp_num_siblings > NR_CPUS) { | |
219 | printk(KERN_WARNING "CPU: Unsupported number of siblings %d", | |
220 | smp_num_siblings); | |
221 | smp_num_siblings = 1; | |
222 | return; | |
223 | } | |
224 | ||
225 | index_msb = get_count_order(smp_num_siblings); | |
226 | c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb); | |
227 | ||
228 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
229 | c->phys_proc_id); | |
230 | ||
231 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
232 | ||
233 | index_msb = get_count_order(smp_num_siblings); | |
234 | ||
235 | core_bits = get_count_order(c->x86_max_cores); | |
236 | ||
237 | c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) & | |
238 | ((1 << core_bits) - 1); | |
239 | ||
240 | if (c->x86_max_cores > 1) | |
241 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
242 | c->cpu_core_id); | |
243 | } | |
244 | } | |
245 | #endif | |
1da177e4 | 246 | |
3da99c97 | 247 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
248 | { |
249 | char *v = c->x86_vendor_id; | |
250 | int i; | |
fe38d855 | 251 | static int printed; |
1da177e4 LT |
252 | |
253 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
254 | if (!cpu_devs[i]) |
255 | break; | |
256 | ||
257 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
258 | (cpu_devs[i]->c_ident[1] && | |
259 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
260 | this_cpu = cpu_devs[i]; | |
261 | c->x86_vendor = this_cpu->c_x86_vendor; | |
262 | return; | |
1da177e4 LT |
263 | } |
264 | } | |
10a434fc | 265 | |
fe38d855 CE |
266 | if (!printed) { |
267 | printed++; | |
268 | printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n"); | |
269 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); | |
270 | } | |
10a434fc | 271 | |
fe38d855 CE |
272 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
273 | this_cpu = &default_cpu; | |
1da177e4 LT |
274 | } |
275 | ||
276 | ||
34048c9e | 277 | static int __init x86_fxsr_setup(char *s) |
1da177e4 | 278 | { |
13530257 AK |
279 | setup_clear_cpu_cap(X86_FEATURE_FXSR); |
280 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
1da177e4 LT |
281 | return 1; |
282 | } | |
283 | __setup("nofxsr", x86_fxsr_setup); | |
284 | ||
285 | ||
34048c9e | 286 | static int __init x86_sep_setup(char *s) |
4f886511 | 287 | { |
13530257 | 288 | setup_clear_cpu_cap(X86_FEATURE_SEP); |
4f886511 CE |
289 | return 1; |
290 | } | |
291 | __setup("nosep", x86_sep_setup); | |
292 | ||
293 | ||
1da177e4 LT |
294 | /* Standard macro to see if a specific flag is changeable */ |
295 | static inline int flag_is_changeable_p(u32 flag) | |
296 | { | |
297 | u32 f1, f2; | |
298 | ||
299 | asm("pushfl\n\t" | |
300 | "pushfl\n\t" | |
301 | "popl %0\n\t" | |
302 | "movl %0,%1\n\t" | |
303 | "xorl %2,%0\n\t" | |
304 | "pushl %0\n\t" | |
305 | "popfl\n\t" | |
306 | "pushfl\n\t" | |
307 | "popl %0\n\t" | |
308 | "popfl\n\t" | |
309 | : "=&r" (f1), "=&r" (f2) | |
310 | : "ir" (flag)); | |
311 | ||
312 | return ((f1^f2) & flag) != 0; | |
313 | } | |
314 | ||
315 | ||
316 | /* Probe for the CPUID instruction */ | |
3bc9b76b | 317 | static int __cpuinit have_cpuid_p(void) |
1da177e4 LT |
318 | { |
319 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
320 | } | |
321 | ||
9d31d35b | 322 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 323 | { |
1da177e4 | 324 | /* Get vendor name */ |
4a148513 HH |
325 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
326 | (unsigned int *)&c->x86_vendor_id[0], | |
327 | (unsigned int *)&c->x86_vendor_id[8], | |
328 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 329 | |
1da177e4 | 330 | c->x86 = 4; |
9d31d35b | 331 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
332 | if (c->cpuid_level >= 0x00000001) { |
333 | u32 junk, tfms, cap0, misc; | |
334 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
9d31d35b YL |
335 | c->x86 = (tfms >> 8) & 0xf; |
336 | c->x86_model = (tfms >> 4) & 0xf; | |
337 | c->x86_mask = tfms & 0xf; | |
f5f786d0 | 338 | if (c->x86 == 0xf) |
1da177e4 | 339 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 340 | if (c->x86 >= 0x6) |
9d31d35b | 341 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
d4387bd3 | 342 | if (cap0 & (1<<19)) { |
d4387bd3 | 343 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 344 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 345 | } |
1da177e4 | 346 | } |
1da177e4 | 347 | } |
3da99c97 YL |
348 | |
349 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
093af8d7 YL |
350 | { |
351 | u32 tfms, xlvl; | |
3da99c97 | 352 | u32 ebx; |
093af8d7 | 353 | |
3da99c97 YL |
354 | /* Intel-defined flags: level 0x00000001 */ |
355 | if (c->cpuid_level >= 0x00000001) { | |
356 | u32 capability, excap; | |
357 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
358 | c->x86_capability[0] = capability; | |
359 | c->x86_capability[4] = excap; | |
360 | } | |
093af8d7 | 361 | |
3da99c97 YL |
362 | /* AMD-defined flags: level 0x80000001 */ |
363 | xlvl = cpuid_eax(0x80000000); | |
364 | c->extended_cpuid_level = xlvl; | |
365 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
366 | if (xlvl >= 0x80000001) { | |
367 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
368 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 369 | } |
093af8d7 | 370 | } |
093af8d7 | 371 | } |
34048c9e PC |
372 | /* |
373 | * Do minimum CPU detection early. | |
374 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
375 | * cache alignment. | |
376 | * The others are not touched to avoid unwanted side effects. | |
377 | * | |
378 | * WARNING: this function is only called on the BP. Don't add code here | |
379 | * that is supposed to run on all CPUs. | |
380 | */ | |
3da99c97 | 381 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 382 | { |
d7cd5611 | 383 | c->x86_cache_alignment = 32; |
d4387bd3 | 384 | c->x86_clflush_size = 32; |
d7cd5611 RR |
385 | |
386 | if (!have_cpuid_p()) | |
387 | return; | |
388 | ||
3da99c97 YL |
389 | c->extended_cpuid_level = 0; |
390 | ||
391 | memset(&c->x86_capability, 0, sizeof c->x86_capability); | |
392 | ||
d7cd5611 RR |
393 | cpu_detect(c); |
394 | ||
3da99c97 | 395 | get_cpu_vendor(c); |
2b16a235 | 396 | |
3da99c97 | 397 | get_cpu_cap(c); |
5031088d | 398 | |
10a434fc YL |
399 | if (this_cpu->c_early_init) |
400 | this_cpu->c_early_init(c); | |
3da99c97 YL |
401 | |
402 | validate_pat_support(c); | |
d7cd5611 RR |
403 | } |
404 | ||
9d31d35b YL |
405 | void __init early_cpu_init(void) |
406 | { | |
10a434fc YL |
407 | struct cpu_dev **cdev; |
408 | int count = 0; | |
409 | ||
410 | printk("KERNEL supported cpus:\n"); | |
411 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { | |
412 | struct cpu_dev *cpudev = *cdev; | |
413 | unsigned int j; | |
9d31d35b | 414 | |
10a434fc YL |
415 | if (count >= X86_VENDOR_NUM) |
416 | break; | |
417 | cpu_devs[count] = cpudev; | |
418 | count++; | |
419 | ||
420 | for (j = 0; j < 2; j++) { | |
421 | if (!cpudev->c_ident[j]) | |
422 | continue; | |
423 | printk(" %s %s\n", cpudev->c_vendor, | |
424 | cpudev->c_ident[j]); | |
425 | } | |
426 | } | |
9d31d35b | 427 | |
9d31d35b YL |
428 | early_identify_cpu(&boot_cpu_data); |
429 | } | |
430 | ||
7e00df58 PA |
431 | /* |
432 | * The NOPL instruction is supposed to exist on all CPUs with | |
433 | * family >= 6, unfortunately, that's not true in practice because | |
434 | * of early VIA chips and (more importantly) broken virtualizers that | |
435 | * are not easy to detect. Hence, probe for it based on first | |
436 | * principles. | |
437 | */ | |
438 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
439 | { | |
440 | const u32 nopl_signature = 0x888c53b1; /* Random number */ | |
441 | u32 has_nopl = nopl_signature; | |
442 | ||
443 | clear_cpu_cap(c, X86_FEATURE_NOPL); | |
444 | if (c->x86 >= 6) { | |
445 | asm volatile("\n" | |
446 | "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */ | |
447 | "2:\n" | |
448 | " .section .fixup,\"ax\"\n" | |
449 | "3: xor %0,%0\n" | |
450 | " jmp 2b\n" | |
451 | " .previous\n" | |
452 | _ASM_EXTABLE(1b,3b) | |
453 | : "+a" (has_nopl)); | |
454 | ||
455 | if (has_nopl == nopl_signature) | |
456 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
457 | } | |
458 | } | |
459 | ||
34048c9e | 460 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 461 | { |
3da99c97 YL |
462 | if (!have_cpuid_p()) |
463 | return; | |
464 | ||
465 | c->extended_cpuid_level = 0; | |
466 | ||
467 | cpu_detect(c); | |
468 | ||
469 | get_cpu_vendor(c); | |
470 | ||
471 | get_cpu_cap(c); | |
472 | ||
473 | if (c->cpuid_level >= 0x00000001) { | |
474 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
96c52749 | 475 | #ifdef CONFIG_X86_HT |
3da99c97 YL |
476 | c->apicid = phys_pkg_id(c->initial_apicid, 0); |
477 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 478 | #else |
3da99c97 | 479 | c->apicid = c->initial_apicid; |
1e9f28fa | 480 | #endif |
3da99c97 | 481 | } |
1da177e4 | 482 | |
3da99c97 YL |
483 | if (c->extended_cpuid_level >= 0x80000004) |
484 | get_model_name(c); /* Default name */ | |
1d67953f | 485 | |
3da99c97 YL |
486 | init_scattered_cpuid_features(c); |
487 | detect_nopl(c); | |
1da177e4 LT |
488 | } |
489 | ||
3bc9b76b | 490 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
1da177e4 | 491 | { |
34048c9e | 492 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { |
1da177e4 | 493 | /* Disable processor serial number */ |
34048c9e PC |
494 | unsigned long lo, hi; |
495 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
1da177e4 | 496 | lo |= 0x200000; |
34048c9e | 497 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); |
1da177e4 | 498 | printk(KERN_NOTICE "CPU serial number disabled.\n"); |
4cbe668a | 499 | clear_cpu_cap(c, X86_FEATURE_PN); |
1da177e4 LT |
500 | |
501 | /* Disabling the serial number may affect the cpuid level */ | |
502 | c->cpuid_level = cpuid_eax(0); | |
503 | } | |
504 | } | |
505 | ||
506 | static int __init x86_serial_nr_setup(char *s) | |
507 | { | |
508 | disable_x86_serial_nr = 0; | |
509 | return 1; | |
510 | } | |
511 | __setup("serialnumber", x86_serial_nr_setup); | |
512 | ||
513 | ||
514 | ||
515 | /* | |
516 | * This does the hard work of actually picking apart the CPU stuff... | |
517 | */ | |
9a250347 | 518 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
519 | { |
520 | int i; | |
521 | ||
522 | c->loops_per_jiffy = loops_per_jiffy; | |
523 | c->x86_cache_size = -1; | |
524 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
525 | c->cpuid_level = -1; /* CPUID not detected */ | |
526 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ | |
527 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
528 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 529 | c->x86_max_cores = 1; |
770d132f | 530 | c->x86_clflush_size = 32; |
1da177e4 LT |
531 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
532 | ||
533 | if (!have_cpuid_p()) { | |
34048c9e PC |
534 | /* |
535 | * First of all, decide if this is a 486 or higher | |
536 | * It's a 486 if we can modify the AC flag | |
537 | */ | |
538 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
1da177e4 LT |
539 | c->x86 = 4; |
540 | else | |
541 | c->x86 = 3; | |
542 | } | |
543 | ||
544 | generic_identify(c); | |
545 | ||
3898534d | 546 | if (this_cpu->c_identify) |
1da177e4 LT |
547 | this_cpu->c_identify(c); |
548 | ||
1da177e4 LT |
549 | /* |
550 | * Vendor-specific initialization. In this section we | |
551 | * canonicalize the feature flags, meaning if there are | |
552 | * features a certain CPU supports which CPUID doesn't | |
553 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
554 | * we handle them here. | |
555 | * | |
556 | * At the end of this section, c->x86_capability better | |
557 | * indicate the features this CPU genuinely supports! | |
558 | */ | |
559 | if (this_cpu->c_init) | |
560 | this_cpu->c_init(c); | |
561 | ||
562 | /* Disable the PN if appropriate */ | |
563 | squash_the_stupid_serial_number(c); | |
564 | ||
565 | /* | |
566 | * The vendor-specific functions might have changed features. Now | |
567 | * we do "generic changes." | |
568 | */ | |
569 | ||
1da177e4 | 570 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 571 | if (!c->x86_model_id[0]) { |
1da177e4 LT |
572 | char *p; |
573 | p = table_lookup_model(c); | |
34048c9e | 574 | if (p) |
1da177e4 LT |
575 | strcpy(c->x86_model_id, p); |
576 | else | |
577 | /* Last resort... */ | |
578 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 579 | c->x86, c->x86_model); |
1da177e4 LT |
580 | } |
581 | ||
1da177e4 LT |
582 | /* |
583 | * On SMP, boot_cpu_data holds the common feature set between | |
584 | * all CPUs; so make sure that we indicate which features are | |
585 | * common between the CPUs. The first time this routine gets | |
586 | * executed, c == &boot_cpu_data. | |
587 | */ | |
34048c9e | 588 | if (c != &boot_cpu_data) { |
1da177e4 | 589 | /* AND the already accumulated flags with these */ |
9d31d35b | 590 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
591 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
592 | } | |
593 | ||
7d851c8d AK |
594 | /* Clear all flags overriden by options */ |
595 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 596 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 597 | |
1da177e4 | 598 | /* Init Machine Check Exception if available. */ |
1da177e4 | 599 | mcheck_init(c); |
30d432df AK |
600 | |
601 | select_idle_routine(c); | |
a6c4e076 | 602 | } |
31ab269a | 603 | |
a6c4e076 JF |
604 | void __init identify_boot_cpu(void) |
605 | { | |
606 | identify_cpu(&boot_cpu_data); | |
607 | sysenter_setup(); | |
6fe940d6 | 608 | enable_sep_cpu(); |
a6c4e076 | 609 | } |
3b520b23 | 610 | |
a6c4e076 JF |
611 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
612 | { | |
613 | BUG_ON(c == &boot_cpu_data); | |
614 | identify_cpu(c); | |
615 | enable_sep_cpu(); | |
616 | mtrr_ap_init(); | |
1da177e4 LT |
617 | } |
618 | ||
a0854a46 YL |
619 | struct msr_range { |
620 | unsigned min; | |
621 | unsigned max; | |
622 | }; | |
623 | ||
624 | static struct msr_range msr_range_array[] __cpuinitdata = { | |
625 | { 0x00000000, 0x00000418}, | |
626 | { 0xc0000000, 0xc000040b}, | |
627 | { 0xc0010000, 0xc0010142}, | |
628 | { 0xc0011000, 0xc001103b}, | |
629 | }; | |
630 | ||
631 | static void __cpuinit print_cpu_msr(void) | |
632 | { | |
633 | unsigned index; | |
634 | u64 val; | |
635 | int i; | |
636 | unsigned index_min, index_max; | |
637 | ||
638 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
639 | index_min = msr_range_array[i].min; | |
640 | index_max = msr_range_array[i].max; | |
641 | for (index = index_min; index < index_max; index++) { | |
642 | if (rdmsrl_amd_safe(index, &val)) | |
643 | continue; | |
644 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
645 | } | |
646 | } | |
647 | } | |
648 | ||
649 | static int show_msr __cpuinitdata; | |
650 | static __init int setup_show_msr(char *arg) | |
651 | { | |
652 | int num; | |
653 | ||
654 | get_option(&arg, &num); | |
655 | ||
656 | if (num > 0) | |
657 | show_msr = num; | |
658 | return 1; | |
659 | } | |
660 | __setup("show_msr=", setup_show_msr); | |
661 | ||
191679fd AK |
662 | static __init int setup_noclflush(char *arg) |
663 | { | |
664 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
665 | return 1; | |
666 | } | |
667 | __setup("noclflush", setup_noclflush); | |
668 | ||
3bc9b76b | 669 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
670 | { |
671 | char *vendor = NULL; | |
672 | ||
673 | if (c->x86_vendor < X86_VENDOR_NUM) | |
674 | vendor = this_cpu->c_vendor; | |
675 | else if (c->cpuid_level >= 0) | |
676 | vendor = c->x86_vendor_id; | |
677 | ||
678 | if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor))) | |
9d31d35b | 679 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 680 | |
9d31d35b YL |
681 | if (c->x86_model_id[0]) |
682 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 683 | else |
9d31d35b | 684 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 685 | |
34048c9e | 686 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 687 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 688 | else |
9d31d35b | 689 | printk(KERN_CONT "\n"); |
a0854a46 YL |
690 | |
691 | #ifdef CONFIG_SMP | |
692 | if (c->cpu_index < show_msr) | |
693 | print_cpu_msr(); | |
694 | #else | |
695 | if (show_msr) | |
696 | print_cpu_msr(); | |
697 | #endif | |
1da177e4 LT |
698 | } |
699 | ||
ac72e788 AK |
700 | static __init int setup_disablecpuid(char *arg) |
701 | { | |
702 | int bit; | |
703 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
704 | setup_clear_cpu_cap(bit); | |
705 | else | |
706 | return 0; | |
707 | return 1; | |
708 | } | |
709 | __setup("clearcpuid=", setup_disablecpuid); | |
710 | ||
3bc9b76b | 711 | cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; |
1da177e4 | 712 | |
7c3576d2 | 713 | /* Make sure %fs is initialized properly in idle threads */ |
6b2fb3c6 | 714 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
715 | { |
716 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 717 | regs->fs = __KERNEL_PERCPU; |
f95d47ca JF |
718 | return regs; |
719 | } | |
720 | ||
d2cbcc49 RR |
721 | /* |
722 | * cpu_init() initializes state that is per-CPU. Some data is already | |
723 | * initialized (naturally) in the bootstrap process, such as the GDT | |
724 | * and IDT. We reload them nevertheless, this function acts as a | |
725 | * 'CPU state barrier', nothing should get across. | |
726 | */ | |
727 | void __cpuinit cpu_init(void) | |
9ee79a3d | 728 | { |
d2cbcc49 RR |
729 | int cpu = smp_processor_id(); |
730 | struct task_struct *curr = current; | |
34048c9e | 731 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 732 | struct thread_struct *thread = &curr->thread; |
62111195 JF |
733 | |
734 | if (cpu_test_and_set(cpu, cpu_initialized)) { | |
735 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); | |
736 | for (;;) local_irq_enable(); | |
737 | } | |
738 | ||
739 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
740 | ||
741 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
742 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 743 | |
4d37e7e3 | 744 | load_idt(&idt_descr); |
c5413fbe | 745 | switch_to_new_gdt(); |
1da177e4 | 746 | |
1da177e4 LT |
747 | /* |
748 | * Set up and load the per-CPU TSS and LDT | |
749 | */ | |
750 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
751 | curr->active_mm = &init_mm; |
752 | if (curr->mm) | |
753 | BUG(); | |
754 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 | 755 | |
faca6227 | 756 | load_sp0(t, thread); |
34048c9e | 757 | set_tss_desc(cpu, t); |
1da177e4 LT |
758 | load_TR_desc(); |
759 | load_LDT(&init_mm.context); | |
760 | ||
22c4e308 | 761 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
762 | /* Set up doublefault TSS pointer in the GDT */ |
763 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 764 | #endif |
1da177e4 | 765 | |
464d1a78 JF |
766 | /* Clear %gs. */ |
767 | asm volatile ("mov %0, %%gs" : : "r" (0)); | |
1da177e4 LT |
768 | |
769 | /* Clear all 6 debug registers: */ | |
4bb0d3ec ZA |
770 | set_debugreg(0, 0); |
771 | set_debugreg(0, 1); | |
772 | set_debugreg(0, 2); | |
773 | set_debugreg(0, 3); | |
774 | set_debugreg(0, 6); | |
775 | set_debugreg(0, 7); | |
1da177e4 LT |
776 | |
777 | /* | |
778 | * Force FPU initialization: | |
779 | */ | |
780 | current_thread_info()->status = 0; | |
781 | clear_used_math(); | |
782 | mxcsr_feature_mask_init(); | |
783 | } | |
e1367daf LS |
784 | |
785 | #ifdef CONFIG_HOTPLUG_CPU | |
3bc9b76b | 786 | void __cpuinit cpu_uninit(void) |
e1367daf LS |
787 | { |
788 | int cpu = raw_smp_processor_id(); | |
789 | cpu_clear(cpu, cpu_initialized); | |
790 | ||
791 | /* lazy TLB state */ | |
792 | per_cpu(cpu_tlbstate, cpu).state = 0; | |
793 | per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm; | |
794 | } | |
795 | #endif |