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Commit | Line | Data |
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f0fc4aff | 1 | #include <linux/bootmem.h> |
9766cdbc | 2 | #include <linux/linkage.h> |
f0fc4aff | 3 | #include <linux/bitops.h> |
9766cdbc | 4 | #include <linux/kernel.h> |
186f4360 | 5 | #include <linux/export.h> |
9766cdbc JSR |
6 | #include <linux/percpu.h> |
7 | #include <linux/string.h> | |
ee098e1a | 8 | #include <linux/ctype.h> |
1da177e4 | 9 | #include <linux/delay.h> |
68e21be2 | 10 | #include <linux/sched/mm.h> |
e6017571 | 11 | #include <linux/sched/clock.h> |
9164bb4a | 12 | #include <linux/sched/task.h> |
9766cdbc | 13 | #include <linux/init.h> |
0f46efeb | 14 | #include <linux/kprobes.h> |
9766cdbc | 15 | #include <linux/kgdb.h> |
1da177e4 | 16 | #include <linux/smp.h> |
9766cdbc | 17 | #include <linux/io.h> |
b51ef52d | 18 | #include <linux/syscore_ops.h> |
9766cdbc JSR |
19 | |
20 | #include <asm/stackprotector.h> | |
cdd6c482 | 21 | #include <asm/perf_event.h> |
1da177e4 | 22 | #include <asm/mmu_context.h> |
49d859d7 | 23 | #include <asm/archrandom.h> |
9766cdbc JSR |
24 | #include <asm/hypervisor.h> |
25 | #include <asm/processor.h> | |
1e02ce4c | 26 | #include <asm/tlbflush.h> |
f649e938 | 27 | #include <asm/debugreg.h> |
9766cdbc | 28 | #include <asm/sections.h> |
f40c3300 | 29 | #include <asm/vsyscall.h> |
8bdbd962 AC |
30 | #include <linux/topology.h> |
31 | #include <linux/cpumask.h> | |
9766cdbc | 32 | #include <asm/pgtable.h> |
60063497 | 33 | #include <linux/atomic.h> |
9766cdbc JSR |
34 | #include <asm/proto.h> |
35 | #include <asm/setup.h> | |
36 | #include <asm/apic.h> | |
37 | #include <asm/desc.h> | |
78f7f1e5 | 38 | #include <asm/fpu/internal.h> |
27b07da7 | 39 | #include <asm/mtrr.h> |
0274f955 | 40 | #include <asm/hwcap2.h> |
8bdbd962 | 41 | #include <linux/numa.h> |
9766cdbc | 42 | #include <asm/asm.h> |
0f6ff2bc | 43 | #include <asm/bugs.h> |
9766cdbc | 44 | #include <asm/cpu.h> |
a03a3e28 | 45 | #include <asm/mce.h> |
9766cdbc | 46 | #include <asm/msr.h> |
8d4a4300 | 47 | #include <asm/pat.h> |
d288e1cf FY |
48 | #include <asm/microcode.h> |
49 | #include <asm/microcode_intel.h> | |
97f85591 DW |
50 | #include <asm/intel-family.h> |
51 | #include <asm/cpu_device_id.h> | |
e641f5f5 IM |
52 | |
53 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 54 | #include <asm/uv/uv.h> |
1da177e4 LT |
55 | #endif |
56 | ||
57 | #include "cpu.h" | |
58 | ||
0274f955 GA |
59 | u32 elf_hwcap2 __read_mostly; |
60 | ||
c2d1cec1 | 61 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 62 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
63 | cpumask_var_t cpu_callout_mask; |
64 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
65 | |
66 | /* representing cpus for which sibling maps can be computed */ | |
67 | cpumask_var_t cpu_sibling_setup_mask; | |
68 | ||
36b25ba4 BP |
69 | /* Number of siblings per CPU package */ |
70 | int smp_num_siblings = 1; | |
71 | EXPORT_SYMBOL(smp_num_siblings); | |
72 | ||
73 | /* Last level cache ID of each logical CPU */ | |
74 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; | |
75 | ||
2f2f52ba | 76 | /* correctly size the local cpu masks */ |
4369f1fb | 77 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
78 | { |
79 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
80 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
81 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
82 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
83 | } | |
84 | ||
148f9bb8 | 85 | static void default_init(struct cpuinfo_x86 *c) |
e8055139 OZ |
86 | { |
87 | #ifdef CONFIG_X86_64 | |
27c13ece | 88 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
89 | #else |
90 | /* Not much we can do here... */ | |
91 | /* Check if at least it has cpuid */ | |
92 | if (c->cpuid_level == -1) { | |
93 | /* No cpuid. It must be an ancient CPU */ | |
94 | if (c->x86 == 4) | |
95 | strcpy(c->x86_model_id, "486"); | |
96 | else if (c->x86 == 3) | |
97 | strcpy(c->x86_model_id, "386"); | |
98 | } | |
99 | #endif | |
100 | } | |
101 | ||
148f9bb8 | 102 | static const struct cpu_dev default_cpu = { |
e8055139 OZ |
103 | .c_init = default_init, |
104 | .c_vendor = "Unknown", | |
105 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
106 | }; | |
107 | ||
148f9bb8 | 108 | static const struct cpu_dev *this_cpu = &default_cpu; |
0a488a53 | 109 | |
06deef89 | 110 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 111 | #ifdef CONFIG_X86_64 |
06deef89 BG |
112 | /* |
113 | * We need valid kernel segments for data and code in long mode too | |
114 | * IRET will check the segment types kkeil 2000/10/28 | |
115 | * Also sysret mandates a special GDT layout | |
116 | * | |
9766cdbc | 117 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
118 | * Hopefully nobody expects them at a fixed place (Wine?) |
119 | */ | |
1e5de182 AM |
120 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
121 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
122 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
123 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
124 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
125 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 126 | #else |
1e5de182 AM |
127 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
128 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
129 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
130 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
131 | /* |
132 | * Segments used for calling PnP BIOS have byte granularity. | |
133 | * They code segments and data segments have fixed 64k limits, | |
134 | * the transfer segment sizes are set at run time. | |
135 | */ | |
6842ef0e | 136 | /* 32-bit code */ |
1e5de182 | 137 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 138 | /* 16-bit code */ |
1e5de182 | 139 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 140 | /* 16-bit data */ |
1e5de182 | 141 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 142 | /* 16-bit data */ |
1e5de182 | 143 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 144 | /* 16-bit data */ |
1e5de182 | 145 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
146 | /* |
147 | * The APM segments have byte granularity and their bases | |
148 | * are set at run time. All have 64k limits. | |
149 | */ | |
6842ef0e | 150 | /* 32-bit code */ |
1e5de182 | 151 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 152 | /* 16-bit code */ |
1e5de182 | 153 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 154 | /* data */ |
72c4d853 | 155 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 156 | |
1e5de182 AM |
157 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
158 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 159 | GDT_STACK_CANARY_INIT |
950ad7ff | 160 | #endif |
06deef89 | 161 | } }; |
7a61d35d | 162 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 163 | |
8c3641e9 | 164 | static int __init x86_mpx_setup(char *s) |
0c752a93 | 165 | { |
8c3641e9 | 166 | /* require an exact match without trailing characters */ |
2cd3949f DH |
167 | if (strlen(s)) |
168 | return 0; | |
0c752a93 | 169 | |
8c3641e9 DH |
170 | /* do not emit a message if the feature is not present */ |
171 | if (!boot_cpu_has(X86_FEATURE_MPX)) | |
172 | return 1; | |
6bad06b7 | 173 | |
8c3641e9 DH |
174 | setup_clear_cpu_cap(X86_FEATURE_MPX); |
175 | pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); | |
b6f42a4a FY |
176 | return 1; |
177 | } | |
8c3641e9 | 178 | __setup("nompx", x86_mpx_setup); |
b6f42a4a | 179 | |
0790c9aa | 180 | #ifdef CONFIG_X86_64 |
c7ad5ad2 | 181 | static int __init x86_nopcid_setup(char *s) |
0790c9aa | 182 | { |
c7ad5ad2 AL |
183 | /* nopcid doesn't accept parameters */ |
184 | if (s) | |
185 | return -EINVAL; | |
0790c9aa AL |
186 | |
187 | /* do not emit a message if the feature is not present */ | |
188 | if (!boot_cpu_has(X86_FEATURE_PCID)) | |
c7ad5ad2 | 189 | return 0; |
0790c9aa AL |
190 | |
191 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
192 | pr_info("nopcid: PCID feature disabled\n"); | |
c7ad5ad2 | 193 | return 0; |
0790c9aa | 194 | } |
c7ad5ad2 | 195 | early_param("nopcid", x86_nopcid_setup); |
0790c9aa AL |
196 | #endif |
197 | ||
d12a72b8 AL |
198 | static int __init x86_noinvpcid_setup(char *s) |
199 | { | |
200 | /* noinvpcid doesn't accept parameters */ | |
201 | if (s) | |
202 | return -EINVAL; | |
203 | ||
204 | /* do not emit a message if the feature is not present */ | |
205 | if (!boot_cpu_has(X86_FEATURE_INVPCID)) | |
206 | return 0; | |
207 | ||
208 | setup_clear_cpu_cap(X86_FEATURE_INVPCID); | |
209 | pr_info("noinvpcid: INVPCID feature disabled\n"); | |
210 | return 0; | |
211 | } | |
212 | early_param("noinvpcid", x86_noinvpcid_setup); | |
213 | ||
ba51dced | 214 | #ifdef CONFIG_X86_32 |
148f9bb8 PG |
215 | static int cachesize_override = -1; |
216 | static int disable_x86_serial_nr = 1; | |
1da177e4 | 217 | |
0a488a53 YL |
218 | static int __init cachesize_setup(char *str) |
219 | { | |
220 | get_option(&str, &cachesize_override); | |
221 | return 1; | |
222 | } | |
223 | __setup("cachesize=", cachesize_setup); | |
224 | ||
0a488a53 YL |
225 | static int __init x86_sep_setup(char *s) |
226 | { | |
227 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
228 | return 1; | |
229 | } | |
230 | __setup("nosep", x86_sep_setup); | |
231 | ||
232 | /* Standard macro to see if a specific flag is changeable */ | |
233 | static inline int flag_is_changeable_p(u32 flag) | |
234 | { | |
235 | u32 f1, f2; | |
236 | ||
94f6bac1 KH |
237 | /* |
238 | * Cyrix and IDT cpus allow disabling of CPUID | |
239 | * so the code below may return different results | |
240 | * when it is executed before and after enabling | |
241 | * the CPUID. Add "volatile" to not allow gcc to | |
242 | * optimize the subsequent calls to this function. | |
243 | */ | |
0f3fa48a IM |
244 | asm volatile ("pushfl \n\t" |
245 | "pushfl \n\t" | |
246 | "popl %0 \n\t" | |
247 | "movl %0, %1 \n\t" | |
248 | "xorl %2, %0 \n\t" | |
249 | "pushl %0 \n\t" | |
250 | "popfl \n\t" | |
251 | "pushfl \n\t" | |
252 | "popl %0 \n\t" | |
253 | "popfl \n\t" | |
254 | ||
94f6bac1 KH |
255 | : "=&r" (f1), "=&r" (f2) |
256 | : "ir" (flag)); | |
0a488a53 YL |
257 | |
258 | return ((f1^f2) & flag) != 0; | |
259 | } | |
260 | ||
261 | /* Probe for the CPUID instruction */ | |
148f9bb8 | 262 | int have_cpuid_p(void) |
0a488a53 YL |
263 | { |
264 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
265 | } | |
266 | ||
148f9bb8 | 267 | static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
0a488a53 | 268 | { |
0f3fa48a IM |
269 | unsigned long lo, hi; |
270 | ||
271 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
272 | return; | |
273 | ||
274 | /* Disable processor serial number: */ | |
275 | ||
276 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
277 | lo |= 0x200000; | |
278 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
279 | ||
1b74dde7 | 280 | pr_notice("CPU serial number disabled.\n"); |
0f3fa48a IM |
281 | clear_cpu_cap(c, X86_FEATURE_PN); |
282 | ||
283 | /* Disabling the serial number may affect the cpuid level */ | |
284 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
285 | } |
286 | ||
287 | static int __init x86_serial_nr_setup(char *s) | |
288 | { | |
289 | disable_x86_serial_nr = 0; | |
290 | return 1; | |
291 | } | |
292 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 293 | #else |
102bbe3a YL |
294 | static inline int flag_is_changeable_p(u32 flag) |
295 | { | |
296 | return 1; | |
297 | } | |
102bbe3a YL |
298 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
299 | { | |
300 | } | |
ba51dced | 301 | #endif |
0a488a53 | 302 | |
de5397ad FY |
303 | static __init int setup_disable_smep(char *arg) |
304 | { | |
b2cc2a07 | 305 | setup_clear_cpu_cap(X86_FEATURE_SMEP); |
0f6ff2bc DH |
306 | /* Check for things that depend on SMEP being enabled: */ |
307 | check_mpx_erratum(&boot_cpu_data); | |
de5397ad FY |
308 | return 1; |
309 | } | |
310 | __setup("nosmep", setup_disable_smep); | |
311 | ||
b2cc2a07 | 312 | static __always_inline void setup_smep(struct cpuinfo_x86 *c) |
de5397ad | 313 | { |
b2cc2a07 | 314 | if (cpu_has(c, X86_FEATURE_SMEP)) |
375074cc | 315 | cr4_set_bits(X86_CR4_SMEP); |
de5397ad FY |
316 | } |
317 | ||
52b6179a PA |
318 | static __init int setup_disable_smap(char *arg) |
319 | { | |
b2cc2a07 | 320 | setup_clear_cpu_cap(X86_FEATURE_SMAP); |
52b6179a PA |
321 | return 1; |
322 | } | |
323 | __setup("nosmap", setup_disable_smap); | |
324 | ||
b2cc2a07 PA |
325 | static __always_inline void setup_smap(struct cpuinfo_x86 *c) |
326 | { | |
581b7f15 | 327 | unsigned long eflags = native_save_fl(); |
b2cc2a07 PA |
328 | |
329 | /* This should have been cleared long ago */ | |
b2cc2a07 PA |
330 | BUG_ON(eflags & X86_EFLAGS_AC); |
331 | ||
03bbd596 PA |
332 | if (cpu_has(c, X86_FEATURE_SMAP)) { |
333 | #ifdef CONFIG_X86_SMAP | |
375074cc | 334 | cr4_set_bits(X86_CR4_SMAP); |
03bbd596 | 335 | #else |
375074cc | 336 | cr4_clear_bits(X86_CR4_SMAP); |
03bbd596 PA |
337 | #endif |
338 | } | |
de5397ad FY |
339 | } |
340 | ||
aa35f896 RN |
341 | static __always_inline void setup_umip(struct cpuinfo_x86 *c) |
342 | { | |
343 | /* Check the boot processor, plus build option for UMIP. */ | |
344 | if (!cpu_feature_enabled(X86_FEATURE_UMIP)) | |
345 | goto out; | |
346 | ||
347 | /* Check the current processor's cpuid bits. */ | |
348 | if (!cpu_has(c, X86_FEATURE_UMIP)) | |
349 | goto out; | |
350 | ||
351 | cr4_set_bits(X86_CR4_UMIP); | |
352 | ||
770c7755 RN |
353 | pr_info("x86/cpu: Activated the Intel User Mode Instruction Prevention (UMIP) CPU feature\n"); |
354 | ||
aa35f896 RN |
355 | return; |
356 | ||
357 | out: | |
358 | /* | |
359 | * Make sure UMIP is disabled in case it was enabled in a | |
360 | * previous boot (e.g., via kexec). | |
361 | */ | |
362 | cr4_clear_bits(X86_CR4_UMIP); | |
363 | } | |
364 | ||
06976945 DH |
365 | /* |
366 | * Protection Keys are not available in 32-bit mode. | |
367 | */ | |
368 | static bool pku_disabled; | |
369 | ||
370 | static __always_inline void setup_pku(struct cpuinfo_x86 *c) | |
371 | { | |
e8df1a95 DH |
372 | /* check the boot processor, plus compile options for PKU: */ |
373 | if (!cpu_feature_enabled(X86_FEATURE_PKU)) | |
374 | return; | |
375 | /* checks the actual processor's cpuid bits: */ | |
06976945 DH |
376 | if (!cpu_has(c, X86_FEATURE_PKU)) |
377 | return; | |
378 | if (pku_disabled) | |
379 | return; | |
380 | ||
381 | cr4_set_bits(X86_CR4_PKE); | |
382 | /* | |
383 | * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE | |
384 | * cpuid bit to be set. We need to ensure that we | |
385 | * update that bit in this CPU's "cpu_info". | |
386 | */ | |
387 | get_cpu_cap(c); | |
388 | } | |
389 | ||
390 | #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS | |
391 | static __init int setup_disable_pku(char *arg) | |
392 | { | |
393 | /* | |
394 | * Do not clear the X86_FEATURE_PKU bit. All of the | |
395 | * runtime checks are against OSPKE so clearing the | |
396 | * bit does nothing. | |
397 | * | |
398 | * This way, we will see "pku" in cpuinfo, but not | |
399 | * "ospke", which is exactly what we want. It shows | |
400 | * that the CPU has PKU, but the OS has not enabled it. | |
401 | * This happens to be exactly how a system would look | |
402 | * if we disabled the config option. | |
403 | */ | |
404 | pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); | |
405 | pku_disabled = true; | |
406 | return 1; | |
407 | } | |
408 | __setup("nopku", setup_disable_pku); | |
409 | #endif /* CONFIG_X86_64 */ | |
410 | ||
b38b0665 PA |
411 | /* |
412 | * Some CPU features depend on higher CPUID levels, which may not always | |
413 | * be available due to CPUID level capping or broken virtualization | |
414 | * software. Add those features to this table to auto-disable them. | |
415 | */ | |
416 | struct cpuid_dependent_feature { | |
417 | u32 feature; | |
418 | u32 level; | |
419 | }; | |
0f3fa48a | 420 | |
148f9bb8 | 421 | static const struct cpuid_dependent_feature |
b38b0665 PA |
422 | cpuid_dependent_features[] = { |
423 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
424 | { X86_FEATURE_DCA, 0x00000009 }, | |
425 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
426 | { 0, 0 } | |
427 | }; | |
428 | ||
148f9bb8 | 429 | static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) |
b38b0665 PA |
430 | { |
431 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 432 | |
b38b0665 | 433 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
434 | |
435 | if (!cpu_has(c, df->feature)) | |
436 | continue; | |
b38b0665 PA |
437 | /* |
438 | * Note: cpuid_level is set to -1 if unavailable, but | |
439 | * extended_extended_level is set to 0 if unavailable | |
440 | * and the legitimate extended levels are all negative | |
441 | * when signed; hence the weird messing around with | |
442 | * signs here... | |
443 | */ | |
0f3fa48a | 444 | if (!((s32)df->level < 0 ? |
f6db44df | 445 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
446 | (s32)df->level > (s32)c->cpuid_level)) |
447 | continue; | |
448 | ||
449 | clear_cpu_cap(c, df->feature); | |
450 | if (!warn) | |
451 | continue; | |
452 | ||
1b74dde7 CY |
453 | pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", |
454 | x86_cap_flag(df->feature), df->level); | |
b38b0665 | 455 | } |
f6db44df | 456 | } |
b38b0665 | 457 | |
102bbe3a YL |
458 | /* |
459 | * Naming convention should be: <Name> [(<Codename>)] | |
460 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
461 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
462 | * isn't used | |
102bbe3a YL |
463 | */ |
464 | ||
465 | /* Look up CPU names by table lookup. */ | |
148f9bb8 | 466 | static const char *table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 467 | { |
09dc68d9 JB |
468 | #ifdef CONFIG_X86_32 |
469 | const struct legacy_cpu_model_info *info; | |
102bbe3a YL |
470 | |
471 | if (c->x86_model >= 16) | |
472 | return NULL; /* Range check */ | |
473 | ||
474 | if (!this_cpu) | |
475 | return NULL; | |
476 | ||
09dc68d9 | 477 | info = this_cpu->legacy_models; |
102bbe3a | 478 | |
09dc68d9 | 479 | while (info->family) { |
102bbe3a YL |
480 | if (info->family == c->x86) |
481 | return info->model_names[c->x86_model]; | |
482 | info++; | |
483 | } | |
09dc68d9 | 484 | #endif |
102bbe3a YL |
485 | return NULL; /* Not found */ |
486 | } | |
487 | ||
6cbd2171 TG |
488 | __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; |
489 | __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; | |
7d851c8d | 490 | |
11e3a840 JF |
491 | void load_percpu_segment(int cpu) |
492 | { | |
493 | #ifdef CONFIG_X86_32 | |
494 | loadsegment(fs, __KERNEL_PERCPU); | |
495 | #else | |
45e876f7 | 496 | __loadsegment_simple(gs, 0); |
11e3a840 JF |
497 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); |
498 | #endif | |
60a5317f | 499 | load_stack_canary_segment(); |
11e3a840 JF |
500 | } |
501 | ||
72f5e08d AL |
502 | #ifdef CONFIG_X86_32 |
503 | /* The 32-bit entry code needs to find cpu_entry_area. */ | |
504 | DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); | |
505 | #endif | |
506 | ||
40e7f949 AL |
507 | #ifdef CONFIG_X86_64 |
508 | /* | |
509 | * Special IST stacks which the CPU switches to when it calls | |
510 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
511 | * limit), all of them are 4K, except the debug stack which | |
512 | * is 8K. | |
513 | */ | |
514 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
515 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
516 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
517 | }; | |
72f5e08d | 518 | #endif |
3386bc8a | 519 | |
45fc8757 TG |
520 | /* Load the original GDT from the per-cpu structure */ |
521 | void load_direct_gdt(int cpu) | |
522 | { | |
523 | struct desc_ptr gdt_descr; | |
524 | ||
525 | gdt_descr.address = (long)get_cpu_gdt_rw(cpu); | |
526 | gdt_descr.size = GDT_SIZE - 1; | |
527 | load_gdt(&gdt_descr); | |
528 | } | |
529 | EXPORT_SYMBOL_GPL(load_direct_gdt); | |
530 | ||
69218e47 TG |
531 | /* Load a fixmap remapping of the per-cpu GDT */ |
532 | void load_fixmap_gdt(int cpu) | |
533 | { | |
534 | struct desc_ptr gdt_descr; | |
535 | ||
536 | gdt_descr.address = (long)get_cpu_gdt_ro(cpu); | |
537 | gdt_descr.size = GDT_SIZE - 1; | |
538 | load_gdt(&gdt_descr); | |
539 | } | |
45fc8757 | 540 | EXPORT_SYMBOL_GPL(load_fixmap_gdt); |
69218e47 | 541 | |
0f3fa48a IM |
542 | /* |
543 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
544 | * it's on the real one. | |
545 | */ | |
552be871 | 546 | void switch_to_new_gdt(int cpu) |
9d31d35b | 547 | { |
45fc8757 TG |
548 | /* Load the original GDT */ |
549 | load_direct_gdt(cpu); | |
2697fbd5 | 550 | /* Reload the per-cpu base */ |
11e3a840 | 551 | load_percpu_segment(cpu); |
9d31d35b YL |
552 | } |
553 | ||
148f9bb8 | 554 | static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 555 | |
148f9bb8 | 556 | static void get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
557 | { |
558 | unsigned int *v; | |
ee098e1a | 559 | char *p, *q, *s; |
1da177e4 | 560 | |
3da99c97 | 561 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 562 | return; |
1da177e4 | 563 | |
0f3fa48a | 564 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
565 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
566 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
567 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
568 | c->x86_model_id[48] = 0; | |
569 | ||
ee098e1a BP |
570 | /* Trim whitespace */ |
571 | p = q = s = &c->x86_model_id[0]; | |
572 | ||
573 | while (*p == ' ') | |
574 | p++; | |
575 | ||
576 | while (*p) { | |
577 | /* Note the last non-whitespace index */ | |
578 | if (!isspace(*p)) | |
579 | s = q; | |
580 | ||
581 | *q++ = *p++; | |
582 | } | |
583 | ||
584 | *(s + 1) = '\0'; | |
1da177e4 LT |
585 | } |
586 | ||
b72c9c97 | 587 | void detect_num_cpu_cores(struct cpuinfo_x86 *c) |
706130c4 DW |
588 | { |
589 | unsigned int eax, ebx, ecx, edx; | |
590 | ||
b72c9c97 | 591 | c->x86_max_cores = 1; |
706130c4 | 592 | if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) |
b72c9c97 | 593 | return; |
706130c4 DW |
594 | |
595 | cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); | |
596 | if (eax & 0x1f) | |
b72c9c97 | 597 | c->x86_max_cores = (eax >> 26) + 1; |
706130c4 DW |
598 | } |
599 | ||
148f9bb8 | 600 | void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 601 | { |
9d31d35b | 602 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 603 | |
3da99c97 | 604 | n = c->extended_cpuid_level; |
1da177e4 LT |
605 | |
606 | if (n >= 0x80000005) { | |
9d31d35b | 607 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 608 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
609 | #ifdef CONFIG_X86_64 |
610 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
611 | c->x86_tlbsize = 0; | |
612 | #endif | |
1da177e4 LT |
613 | } |
614 | ||
615 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
616 | return; | |
617 | ||
0a488a53 | 618 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 619 | l2size = ecx >> 16; |
34048c9e | 620 | |
140fc727 YL |
621 | #ifdef CONFIG_X86_64 |
622 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
623 | #else | |
1da177e4 | 624 | /* do processor-specific cache resizing */ |
09dc68d9 JB |
625 | if (this_cpu->legacy_cache_size) |
626 | l2size = this_cpu->legacy_cache_size(c, l2size); | |
1da177e4 LT |
627 | |
628 | /* Allow user to override all this if necessary. */ | |
629 | if (cachesize_override != -1) | |
630 | l2size = cachesize_override; | |
631 | ||
34048c9e | 632 | if (l2size == 0) |
1da177e4 | 633 | return; /* Again, no L2 cache is possible */ |
140fc727 | 634 | #endif |
1da177e4 LT |
635 | |
636 | c->x86_cache_size = l2size; | |
1da177e4 LT |
637 | } |
638 | ||
e0ba94f1 AS |
639 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
640 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
641 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
642 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
643 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
644 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
dd360393 | 645 | u16 __read_mostly tlb_lld_1g[NR_INFO]; |
e0ba94f1 | 646 | |
f94fe119 | 647 | static void cpu_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
648 | { |
649 | if (this_cpu->c_detect_tlb) | |
650 | this_cpu->c_detect_tlb(c); | |
651 | ||
f94fe119 | 652 | pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", |
e0ba94f1 | 653 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
f94fe119 SH |
654 | tlb_lli_4m[ENTRIES]); |
655 | ||
656 | pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", | |
657 | tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], | |
658 | tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); | |
e0ba94f1 AS |
659 | } |
660 | ||
367d1e0b | 661 | int detect_ht_early(struct cpuinfo_x86 *c) |
1da177e4 | 662 | { |
c8e56d20 | 663 | #ifdef CONFIG_SMP |
0a488a53 | 664 | u32 eax, ebx, ecx, edx; |
1da177e4 | 665 | |
0a488a53 | 666 | if (!cpu_has(c, X86_FEATURE_HT)) |
367d1e0b | 667 | return -1; |
1da177e4 | 668 | |
0a488a53 | 669 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
367d1e0b | 670 | return -1; |
1da177e4 | 671 | |
1cd78776 | 672 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
367d1e0b | 673 | return -1; |
1da177e4 | 674 | |
0a488a53 | 675 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 676 | |
9d31d35b | 677 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
367d1e0b TG |
678 | if (smp_num_siblings == 1) |
679 | pr_info_once("CPU0: Hyper-Threading is disabled\n"); | |
680 | #endif | |
681 | return 0; | |
682 | } | |
9d31d35b | 683 | |
367d1e0b TG |
684 | void detect_ht(struct cpuinfo_x86 *c) |
685 | { | |
686 | #ifdef CONFIG_SMP | |
687 | int index_msb, core_bits; | |
10543e17 | 688 | |
367d1e0b | 689 | if (detect_ht_early(c) < 0) |
10543e17 | 690 | return; |
9d31d35b | 691 | |
0f3fa48a IM |
692 | index_msb = get_count_order(smp_num_siblings); |
693 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 694 | |
0f3fa48a | 695 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 696 | |
0f3fa48a | 697 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 698 | |
0f3fa48a | 699 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 700 | |
0f3fa48a IM |
701 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
702 | ((1 << core_bits) - 1); | |
9d31d35b | 703 | #endif |
97e4db7c | 704 | } |
1da177e4 | 705 | |
148f9bb8 | 706 | static void get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
707 | { |
708 | char *v = c->x86_vendor_id; | |
0f3fa48a | 709 | int i; |
1da177e4 LT |
710 | |
711 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
712 | if (!cpu_devs[i]) |
713 | break; | |
714 | ||
715 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
716 | (cpu_devs[i]->c_ident[1] && | |
717 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 718 | |
10a434fc YL |
719 | this_cpu = cpu_devs[i]; |
720 | c->x86_vendor = this_cpu->c_x86_vendor; | |
721 | return; | |
1da177e4 LT |
722 | } |
723 | } | |
10a434fc | 724 | |
1b74dde7 CY |
725 | pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ |
726 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 727 | |
fe38d855 CE |
728 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
729 | this_cpu = &default_cpu; | |
1da177e4 LT |
730 | } |
731 | ||
148f9bb8 | 732 | void cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 733 | { |
1da177e4 | 734 | /* Get vendor name */ |
4a148513 HH |
735 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
736 | (unsigned int *)&c->x86_vendor_id[0], | |
737 | (unsigned int *)&c->x86_vendor_id[8], | |
738 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 739 | |
1da177e4 | 740 | c->x86 = 4; |
9d31d35b | 741 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
742 | if (c->cpuid_level >= 0x00000001) { |
743 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 744 | |
1da177e4 | 745 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
99f925ce BP |
746 | c->x86 = x86_family(tfms); |
747 | c->x86_model = x86_model(tfms); | |
dd7cc466 | 748 | c->x86_stepping = x86_stepping(tfms); |
0f3fa48a | 749 | |
d4387bd3 | 750 | if (cap0 & (1<<19)) { |
d4387bd3 | 751 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 752 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 753 | } |
1da177e4 | 754 | } |
1da177e4 | 755 | } |
3da99c97 | 756 | |
8bf1ebca AL |
757 | static void apply_forced_caps(struct cpuinfo_x86 *c) |
758 | { | |
759 | int i; | |
760 | ||
6cbd2171 | 761 | for (i = 0; i < NCAPINTS + NBUGINTS; i++) { |
8bf1ebca AL |
762 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; |
763 | c->x86_capability[i] |= cpu_caps_set[i]; | |
764 | } | |
765 | } | |
766 | ||
175130c8 DW |
767 | static void init_speculation_control(struct cpuinfo_x86 *c) |
768 | { | |
769 | /* | |
770 | * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, | |
771 | * and they also have a different bit for STIBP support. Also, | |
772 | * a hypervisor might have set the individual AMD bits even on | |
773 | * Intel CPUs, for finer-grained selection of what's available. | |
175130c8 DW |
774 | */ |
775 | if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { | |
776 | set_cpu_cap(c, X86_FEATURE_IBRS); | |
777 | set_cpu_cap(c, X86_FEATURE_IBPB); | |
50f9b919 | 778 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
175130c8 | 779 | } |
5856293c | 780 | |
175130c8 DW |
781 | if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) |
782 | set_cpu_cap(c, X86_FEATURE_STIBP); | |
5856293c | 783 | |
4d5c8a07 TL |
784 | if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || |
785 | cpu_has(c, X86_FEATURE_VIRT_SSBD)) | |
e48f404c TG |
786 | set_cpu_cap(c, X86_FEATURE_SSBD); |
787 | ||
50f9b919 | 788 | if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { |
5856293c | 789 | set_cpu_cap(c, X86_FEATURE_IBRS); |
50f9b919 TG |
790 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
791 | } | |
5856293c BP |
792 | |
793 | if (cpu_has(c, X86_FEATURE_AMD_IBPB)) | |
794 | set_cpu_cap(c, X86_FEATURE_IBPB); | |
795 | ||
50f9b919 | 796 | if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { |
5856293c | 797 | set_cpu_cap(c, X86_FEATURE_STIBP); |
50f9b919 TG |
798 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
799 | } | |
3b881627 KRW |
800 | |
801 | if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { | |
802 | set_cpu_cap(c, X86_FEATURE_SSBD); | |
803 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); | |
804 | clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); | |
805 | } | |
175130c8 DW |
806 | } |
807 | ||
a015c7c9 BP |
808 | static void init_cqm(struct cpuinfo_x86 *c) |
809 | { | |
cdb3893f FY |
810 | if (!cpu_has(c, X86_FEATURE_CQM_LLC)) { |
811 | c->x86_cache_max_rmid = -1; | |
812 | c->x86_cache_occ_scale = -1; | |
813 | return; | |
814 | } | |
a015c7c9 | 815 | |
cdb3893f FY |
816 | /* will be overridden if occupancy monitoring exists */ |
817 | c->x86_cache_max_rmid = cpuid_ebx(0xf); | |
818 | ||
819 | if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) || | |
820 | cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) || | |
821 | cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) { | |
822 | u32 eax, ebx, ecx, edx; | |
823 | ||
824 | /* QoS sub-leaf, EAX=0Fh, ECX=1 */ | |
825 | cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx); | |
826 | ||
827 | c->x86_cache_max_rmid = ecx; | |
828 | c->x86_cache_occ_scale = ebx; | |
a015c7c9 BP |
829 | } |
830 | } | |
831 | ||
148f9bb8 | 832 | void get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 | 833 | { |
39c06df4 | 834 | u32 eax, ebx, ecx, edx; |
093af8d7 | 835 | |
3da99c97 YL |
836 | /* Intel-defined flags: level 0x00000001 */ |
837 | if (c->cpuid_level >= 0x00000001) { | |
39c06df4 | 838 | cpuid(0x00000001, &eax, &ebx, &ecx, &edx); |
0f3fa48a | 839 | |
39c06df4 BP |
840 | c->x86_capability[CPUID_1_ECX] = ecx; |
841 | c->x86_capability[CPUID_1_EDX] = edx; | |
3da99c97 | 842 | } |
093af8d7 | 843 | |
3df8d920 AL |
844 | /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ |
845 | if (c->cpuid_level >= 0x00000006) | |
846 | c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); | |
847 | ||
bdc802dc PA |
848 | /* Additional Intel-defined flags: level 0x00000007 */ |
849 | if (c->cpuid_level >= 0x00000007) { | |
bdc802dc | 850 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); |
39c06df4 | 851 | c->x86_capability[CPUID_7_0_EBX] = ebx; |
dfb4a70f | 852 | c->x86_capability[CPUID_7_ECX] = ecx; |
38635304 | 853 | c->x86_capability[CPUID_7_EDX] = edx; |
bdc802dc PA |
854 | } |
855 | ||
6229ad27 FY |
856 | /* Extended state features: level 0x0000000d */ |
857 | if (c->cpuid_level >= 0x0000000d) { | |
6229ad27 FY |
858 | cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); |
859 | ||
39c06df4 | 860 | c->x86_capability[CPUID_D_1_EAX] = eax; |
6229ad27 FY |
861 | } |
862 | ||
3da99c97 | 863 | /* AMD-defined flags: level 0x80000001 */ |
39c06df4 BP |
864 | eax = cpuid_eax(0x80000000); |
865 | c->extended_cpuid_level = eax; | |
866 | ||
867 | if ((eax & 0xffff0000) == 0x80000000) { | |
868 | if (eax >= 0x80000001) { | |
869 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
0f3fa48a | 870 | |
39c06df4 BP |
871 | c->x86_capability[CPUID_8000_0001_ECX] = ecx; |
872 | c->x86_capability[CPUID_8000_0001_EDX] = edx; | |
093af8d7 | 873 | } |
093af8d7 | 874 | } |
093af8d7 | 875 | |
71faad43 YG |
876 | if (c->extended_cpuid_level >= 0x80000007) { |
877 | cpuid(0x80000007, &eax, &ebx, &ecx, &edx); | |
878 | ||
879 | c->x86_capability[CPUID_8000_0007_EBX] = ebx; | |
880 | c->x86_power = edx; | |
881 | } | |
882 | ||
5122c890 | 883 | if (c->extended_cpuid_level >= 0x80000008) { |
39c06df4 | 884 | cpuid(0x80000008, &eax, &ebx, &ecx, &edx); |
5122c890 YL |
885 | |
886 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
887 | c->x86_phys_bits = eax & 0xff; | |
39c06df4 | 888 | c->x86_capability[CPUID_8000_0008_EBX] = ebx; |
093af8d7 | 889 | } |
13c6c532 JB |
890 | #ifdef CONFIG_X86_32 |
891 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
892 | c->x86_phys_bits = 36; | |
5122c890 | 893 | #endif |
e3224234 | 894 | |
2ccd71f1 | 895 | if (c->extended_cpuid_level >= 0x8000000a) |
39c06df4 | 896 | c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); |
093af8d7 | 897 | |
1dedefd1 | 898 | init_scattered_cpuid_features(c); |
175130c8 | 899 | init_speculation_control(c); |
a015c7c9 | 900 | init_cqm(c); |
60d34501 AL |
901 | |
902 | /* | |
903 | * Clear/Set all flags overridden by options, after probe. | |
904 | * This needs to happen each time we re-probe, which may happen | |
905 | * several times during CPU initialization. | |
906 | */ | |
907 | apply_forced_caps(c); | |
093af8d7 | 908 | } |
1da177e4 | 909 | |
148f9bb8 | 910 | static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
aef93c8b YL |
911 | { |
912 | #ifdef CONFIG_X86_32 | |
913 | int i; | |
914 | ||
915 | /* | |
916 | * First of all, decide if this is a 486 or higher | |
917 | * It's a 486 if we can modify the AC flag | |
918 | */ | |
919 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
920 | c->x86 = 4; | |
921 | else | |
922 | c->x86 = 3; | |
923 | ||
924 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
925 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
926 | c->x86_vendor_id[0] = 0; | |
927 | cpu_devs[i]->c_identify(c); | |
928 | if (c->x86_vendor_id[0]) { | |
929 | get_cpu_vendor(c); | |
930 | break; | |
931 | } | |
932 | } | |
933 | #endif | |
934 | } | |
935 | ||
cdcb6b8b TG |
936 | #define NO_SPECULATION BIT(0) |
937 | #define NO_MELTDOWN BIT(1) | |
938 | #define NO_SSB BIT(2) | |
939 | #define NO_L1TF BIT(3) | |
191f1f48 | 940 | #define NO_MDS BIT(4) |
480a3088 | 941 | #define MSBDS_ONLY BIT(5) |
3536b6c0 | 942 | #define NO_SWAPGS BIT(6) |
cdcb6b8b TG |
943 | |
944 | #define VULNWL(_vendor, _family, _model, _whitelist) \ | |
945 | { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist } | |
946 | ||
947 | #define VULNWL_INTEL(model, whitelist) \ | |
948 | VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) | |
949 | ||
950 | #define VULNWL_AMD(family, whitelist) \ | |
951 | VULNWL(AMD, family, X86_MODEL_ANY, whitelist) | |
952 | ||
953 | static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { | |
954 | VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), | |
955 | VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), | |
956 | VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), | |
957 | VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), | |
958 | ||
191f1f48 | 959 | /* Intel Family 6 */ |
cdcb6b8b TG |
960 | VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION), |
961 | VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION), | |
962 | VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION), | |
963 | VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION), | |
964 | VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION), | |
965 | ||
3536b6c0 TG |
966 | VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS), |
967 | VULNWL_INTEL(ATOM_SILVERMONT_X, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS), | |
968 | VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS), | |
969 | VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS), | |
970 | VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS), | |
971 | VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS), | |
cdcb6b8b TG |
972 | |
973 | VULNWL_INTEL(CORE_YONAH, NO_SSB), | |
974 | ||
3536b6c0 | 975 | VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS), |
cdcb6b8b | 976 | |
3536b6c0 TG |
977 | VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS), |
978 | VULNWL_INTEL(ATOM_GOLDMONT_X, NO_MDS | NO_L1TF | NO_SWAPGS), | |
979 | VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS), | |
980 | ||
981 | /* | |
982 | * Technically, swapgs isn't serializing on AMD (despite it previously | |
983 | * being documented as such in the APM). But according to AMD, %gs is | |
984 | * updated non-speculatively, and the issuing of %gs-relative memory | |
985 | * operands will be blocked until the %gs update completes, which is | |
986 | * good enough for our purposes. | |
987 | */ | |
191f1f48 AK |
988 | |
989 | /* AMD Family 0xf - 0x12 */ | |
3536b6c0 TG |
990 | VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS), |
991 | VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS), | |
992 | VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS), | |
993 | VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS), | |
cdcb6b8b TG |
994 | |
995 | /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ | |
3536b6c0 | 996 | VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS), |
97f85591 DW |
997 | {} |
998 | }; | |
999 | ||
cdcb6b8b TG |
1000 | static bool __init cpu_matches(unsigned long which) |
1001 | { | |
1002 | const struct x86_cpu_id *m = x86_match_cpu(cpu_vuln_whitelist); | |
d7de9182 | 1003 | |
cdcb6b8b TG |
1004 | return m && !!(m->driver_data & which); |
1005 | } | |
05516ad8 | 1006 | |
0677744a | 1007 | u64 x86_read_arch_cap_msr(void) |
97f85591 DW |
1008 | { |
1009 | u64 ia32_cap = 0; | |
1010 | ||
0677744a PG |
1011 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) |
1012 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); | |
1013 | ||
1014 | return ia32_cap; | |
1015 | } | |
1016 | ||
1017 | static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) | |
1018 | { | |
1019 | u64 ia32_cap = x86_read_arch_cap_msr(); | |
1020 | ||
cdcb6b8b | 1021 | if (cpu_matches(NO_SPECULATION)) |
bd7ad21f DB |
1022 | return; |
1023 | ||
1024 | setup_force_cpu_bug(X86_BUG_SPECTRE_V1); | |
1025 | setup_force_cpu_bug(X86_BUG_SPECTRE_V2); | |
1026 | ||
cdcb6b8b | 1027 | if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO) && |
bb8cadaa | 1028 | !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) |
d7de9182 KRW |
1029 | setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); |
1030 | ||
1044fde9 SP |
1031 | if (ia32_cap & ARCH_CAP_IBRS_ALL) |
1032 | setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); | |
1033 | ||
480a3088 | 1034 | if (!cpu_matches(NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO)) { |
191f1f48 | 1035 | setup_force_cpu_bug(X86_BUG_MDS); |
480a3088 TG |
1036 | if (cpu_matches(MSBDS_ONLY)) |
1037 | setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); | |
1038 | } | |
191f1f48 | 1039 | |
3536b6c0 TG |
1040 | if (!cpu_matches(NO_SWAPGS)) |
1041 | setup_force_cpu_bug(X86_BUG_SWAPGS); | |
1042 | ||
cdcb6b8b | 1043 | if (cpu_matches(NO_MELTDOWN)) |
6d340bf0 | 1044 | return; |
97f85591 | 1045 | |
97f85591 DW |
1046 | /* Rogue Data Cache Load? No! */ |
1047 | if (ia32_cap & ARCH_CAP_RDCL_NO) | |
6d340bf0 | 1048 | return; |
97f85591 | 1049 | |
6d340bf0 | 1050 | setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); |
05516ad8 | 1051 | |
cdcb6b8b | 1052 | if (cpu_matches(NO_L1TF)) |
05516ad8 AK |
1053 | return; |
1054 | ||
1055 | setup_force_cpu_bug(X86_BUG_L1TF); | |
97f85591 DW |
1056 | } |
1057 | ||
34048c9e PC |
1058 | /* |
1059 | * Do minimum CPU detection early. | |
1060 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
1061 | * cache alignment. | |
1062 | * The others are not touched to avoid unwanted side effects. | |
1063 | * | |
a1652bb8 JD |
1064 | * WARNING: this function is only called on the boot CPU. Don't add code |
1065 | * here that is supposed to run on all CPUs. | |
34048c9e | 1066 | */ |
3da99c97 | 1067 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 1068 | { |
6627d242 YL |
1069 | #ifdef CONFIG_X86_64 |
1070 | c->x86_clflush_size = 64; | |
13c6c532 JB |
1071 | c->x86_phys_bits = 36; |
1072 | c->x86_virt_bits = 48; | |
6627d242 | 1073 | #else |
d4387bd3 | 1074 | c->x86_clflush_size = 32; |
13c6c532 JB |
1075 | c->x86_phys_bits = 32; |
1076 | c->x86_virt_bits = 32; | |
6627d242 | 1077 | #endif |
0a488a53 | 1078 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 1079 | |
3da99c97 | 1080 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 1081 | c->extended_cpuid_level = 0; |
d7cd5611 | 1082 | |
aef93c8b | 1083 | /* cyrix could have cpuid enabled via c_identify()*/ |
05fb3c19 AL |
1084 | if (have_cpuid_p()) { |
1085 | cpu_detect(c); | |
1086 | get_cpu_vendor(c); | |
1087 | get_cpu_cap(c); | |
f1f016ed | 1088 | c->x86_cache_bits = c->x86_phys_bits; |
78d1b296 | 1089 | setup_force_cpu_cap(X86_FEATURE_CPUID); |
d7cd5611 | 1090 | |
05fb3c19 AL |
1091 | if (this_cpu->c_early_init) |
1092 | this_cpu->c_early_init(c); | |
12cf105c | 1093 | |
05fb3c19 AL |
1094 | c->cpu_index = 0; |
1095 | filter_cpuid_features(c, false); | |
093af8d7 | 1096 | |
05fb3c19 AL |
1097 | if (this_cpu->c_bsp_init) |
1098 | this_cpu->c_bsp_init(c); | |
78d1b296 BP |
1099 | } else { |
1100 | identify_cpu_without_cpuid(c); | |
1101 | setup_clear_cpu_cap(X86_FEATURE_CPUID); | |
05fb3c19 | 1102 | } |
c3b83598 BP |
1103 | |
1104 | setup_force_cpu_cap(X86_FEATURE_ALWAYS); | |
a89f040f | 1105 | |
6d340bf0 | 1106 | cpu_set_bug_bits(c); |
99c6fa25 | 1107 | |
db52ef74 | 1108 | fpu__init_system(c); |
b8b7abae AL |
1109 | |
1110 | #ifdef CONFIG_X86_32 | |
1111 | /* | |
1112 | * Regardless of whether PCID is enumerated, the SDM says | |
1113 | * that it can't be enabled in 32-bit mode. | |
1114 | */ | |
1115 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
1116 | #endif | |
d7cd5611 RR |
1117 | } |
1118 | ||
9d31d35b YL |
1119 | void __init early_cpu_init(void) |
1120 | { | |
02dde8b4 | 1121 | const struct cpu_dev *const *cdev; |
10a434fc YL |
1122 | int count = 0; |
1123 | ||
ac23f253 | 1124 | #ifdef CONFIG_PROCESSOR_SELECT |
1b74dde7 | 1125 | pr_info("KERNEL supported cpus:\n"); |
31c997ca IM |
1126 | #endif |
1127 | ||
10a434fc | 1128 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 1129 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 1130 | |
10a434fc YL |
1131 | if (count >= X86_VENDOR_NUM) |
1132 | break; | |
1133 | cpu_devs[count] = cpudev; | |
1134 | count++; | |
1135 | ||
ac23f253 | 1136 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
1137 | { |
1138 | unsigned int j; | |
1139 | ||
1140 | for (j = 0; j < 2; j++) { | |
1141 | if (!cpudev->c_ident[j]) | |
1142 | continue; | |
1b74dde7 | 1143 | pr_info(" %s %s\n", cpudev->c_vendor, |
31c997ca IM |
1144 | cpudev->c_ident[j]); |
1145 | } | |
10a434fc | 1146 | } |
0388423d | 1147 | #endif |
10a434fc | 1148 | } |
9d31d35b | 1149 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 1150 | } |
093af8d7 | 1151 | |
b6734c35 | 1152 | /* |
366d4a43 BP |
1153 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; |
1154 | * unfortunately, that's not true in practice because of early VIA | |
1155 | * chips and (more importantly) broken virtualizers that are not easy | |
1156 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
1157 | * probing for it doesn't even work. Disable it completely on 32-bit | |
ba0593bf | 1158 | * unless we can find a reliable way to detect all the broken cases. |
366d4a43 | 1159 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). |
b6734c35 | 1160 | */ |
148f9bb8 | 1161 | static void detect_nopl(struct cpuinfo_x86 *c) |
b6734c35 | 1162 | { |
366d4a43 | 1163 | #ifdef CONFIG_X86_32 |
b6734c35 | 1164 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
366d4a43 BP |
1165 | #else |
1166 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
58a5aac5 | 1167 | #endif |
d7cd5611 | 1168 | } |
58a5aac5 | 1169 | |
7a5d6704 AL |
1170 | static void detect_null_seg_behavior(struct cpuinfo_x86 *c) |
1171 | { | |
1172 | #ifdef CONFIG_X86_64 | |
58a5aac5 | 1173 | /* |
7a5d6704 AL |
1174 | * Empirically, writing zero to a segment selector on AMD does |
1175 | * not clear the base, whereas writing zero to a segment | |
1176 | * selector on Intel does clear the base. Intel's behavior | |
1177 | * allows slightly faster context switches in the common case | |
1178 | * where GS is unused by the prev and next threads. | |
58a5aac5 | 1179 | * |
7a5d6704 AL |
1180 | * Since neither vendor documents this anywhere that I can see, |
1181 | * detect it directly instead of hardcoding the choice by | |
1182 | * vendor. | |
1183 | * | |
1184 | * I've designated AMD's behavior as the "bug" because it's | |
1185 | * counterintuitive and less friendly. | |
58a5aac5 | 1186 | */ |
7a5d6704 AL |
1187 | |
1188 | unsigned long old_base, tmp; | |
1189 | rdmsrl(MSR_FS_BASE, old_base); | |
1190 | wrmsrl(MSR_FS_BASE, 1); | |
1191 | loadsegment(fs, 0); | |
1192 | rdmsrl(MSR_FS_BASE, tmp); | |
1193 | if (tmp != 0) | |
1194 | set_cpu_bug(c, X86_BUG_NULL_SEG); | |
1195 | wrmsrl(MSR_FS_BASE, old_base); | |
366d4a43 | 1196 | #endif |
d7cd5611 RR |
1197 | } |
1198 | ||
148f9bb8 | 1199 | static void generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 1200 | { |
aef93c8b | 1201 | c->extended_cpuid_level = 0; |
1da177e4 | 1202 | |
3da99c97 | 1203 | if (!have_cpuid_p()) |
aef93c8b | 1204 | identify_cpu_without_cpuid(c); |
1d67953f | 1205 | |
aef93c8b | 1206 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 1207 | if (!have_cpuid_p()) |
aef93c8b | 1208 | return; |
1da177e4 | 1209 | |
3da99c97 | 1210 | cpu_detect(c); |
1da177e4 | 1211 | |
3da99c97 | 1212 | get_cpu_vendor(c); |
1da177e4 | 1213 | |
3da99c97 | 1214 | get_cpu_cap(c); |
1da177e4 | 1215 | |
f1f016ed AK |
1216 | c->x86_cache_bits = c->x86_phys_bits; |
1217 | ||
3da99c97 YL |
1218 | if (c->cpuid_level >= 0x00000001) { |
1219 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e | 1220 | #ifdef CONFIG_X86_32 |
c8e56d20 | 1221 | # ifdef CONFIG_SMP |
cb8cc442 | 1222 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 1223 | # else |
3da99c97 | 1224 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
1225 | # endif |
1226 | #endif | |
b89d3b3e | 1227 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 1228 | } |
1da177e4 | 1229 | |
1b05d60d | 1230 | get_model_name(c); /* Default name */ |
1da177e4 | 1231 | |
3da99c97 | 1232 | detect_nopl(c); |
7a5d6704 AL |
1233 | |
1234 | detect_null_seg_behavior(c); | |
0230bb03 AL |
1235 | |
1236 | /* | |
1237 | * ESPFIX is a strange bug. All real CPUs have it. Paravirt | |
1238 | * systems that run Linux at CPL > 0 may or may not have the | |
1239 | * issue, but, even if they have the issue, there's absolutely | |
1240 | * nothing we can do about it because we can't use the real IRET | |
1241 | * instruction. | |
1242 | * | |
1243 | * NB: For the time being, only 32-bit kernels support | |
1244 | * X86_BUG_ESPFIX as such. 64-bit kernels directly choose | |
1245 | * whether to apply espfix using paravirt hooks. If any | |
1246 | * non-paravirt system ever shows up that does *not* have the | |
1247 | * ESPFIX issue, we can change this. | |
1248 | */ | |
1249 | #ifdef CONFIG_X86_32 | |
1250 | # ifdef CONFIG_PARAVIRT | |
1251 | do { | |
1252 | extern void native_iret(void); | |
1253 | if (pv_cpu_ops.iret == native_iret) | |
1254 | set_cpu_bug(c, X86_BUG_ESPFIX); | |
1255 | } while (0); | |
1256 | # else | |
1257 | set_cpu_bug(c, X86_BUG_ESPFIX); | |
1258 | # endif | |
1259 | #endif | |
1da177e4 | 1260 | } |
1da177e4 | 1261 | |
cbc82b17 PWJ |
1262 | static void x86_init_cache_qos(struct cpuinfo_x86 *c) |
1263 | { | |
1264 | /* | |
1265 | * The heavy lifting of max_rmid and cache_occ_scale are handled | |
1266 | * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu | |
1267 | * in case CQM bits really aren't there in this CPU. | |
1268 | */ | |
1269 | if (c != &boot_cpu_data) { | |
1270 | boot_cpu_data.x86_cache_max_rmid = | |
1271 | min(boot_cpu_data.x86_cache_max_rmid, | |
1272 | c->x86_cache_max_rmid); | |
1273 | } | |
1274 | } | |
1275 | ||
d49597fd | 1276 | /* |
9d85eb91 TG |
1277 | * Validate that ACPI/mptables have the same information about the |
1278 | * effective APIC id and update the package map. | |
d49597fd | 1279 | */ |
9d85eb91 | 1280 | static void validate_apic_and_package_id(struct cpuinfo_x86 *c) |
d49597fd TG |
1281 | { |
1282 | #ifdef CONFIG_SMP | |
9d85eb91 | 1283 | unsigned int apicid, cpu = smp_processor_id(); |
d49597fd TG |
1284 | |
1285 | apicid = apic->cpu_present_to_apicid(cpu); | |
d49597fd | 1286 | |
9d85eb91 TG |
1287 | if (apicid != c->apicid) { |
1288 | pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", | |
d49597fd | 1289 | cpu, apicid, c->initial_apicid); |
d49597fd | 1290 | } |
9d85eb91 | 1291 | BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); |
d49597fd TG |
1292 | #else |
1293 | c->logical_proc_id = 0; | |
1294 | #endif | |
1295 | } | |
1296 | ||
1da177e4 LT |
1297 | /* |
1298 | * This does the hard work of actually picking apart the CPU stuff... | |
1299 | */ | |
148f9bb8 | 1300 | static void identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
1301 | { |
1302 | int i; | |
1303 | ||
1304 | c->loops_per_jiffy = loops_per_jiffy; | |
62734cf4 | 1305 | c->x86_cache_size = 0; |
1da177e4 | 1306 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
dd7cc466 | 1307 | c->x86_model = c->x86_stepping = 0; /* So far unknown... */ |
1da177e4 LT |
1308 | c->x86_vendor_id[0] = '\0'; /* Unset */ |
1309 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 1310 | c->x86_max_cores = 1; |
102bbe3a | 1311 | c->x86_coreid_bits = 0; |
79a8b9aa | 1312 | c->cu_id = 0xff; |
11fdd252 | 1313 | #ifdef CONFIG_X86_64 |
102bbe3a | 1314 | c->x86_clflush_size = 64; |
13c6c532 JB |
1315 | c->x86_phys_bits = 36; |
1316 | c->x86_virt_bits = 48; | |
102bbe3a YL |
1317 | #else |
1318 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 1319 | c->x86_clflush_size = 32; |
13c6c532 JB |
1320 | c->x86_phys_bits = 32; |
1321 | c->x86_virt_bits = 32; | |
102bbe3a YL |
1322 | #endif |
1323 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
1324 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
1325 | ||
1da177e4 LT |
1326 | generic_identify(c); |
1327 | ||
3898534d | 1328 | if (this_cpu->c_identify) |
1da177e4 LT |
1329 | this_cpu->c_identify(c); |
1330 | ||
6a6256f9 | 1331 | /* Clear/Set all flags overridden by options, after probe */ |
8bf1ebca | 1332 | apply_forced_caps(c); |
2759c328 | 1333 | |
102bbe3a | 1334 | #ifdef CONFIG_X86_64 |
cb8cc442 | 1335 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
1336 | #endif |
1337 | ||
1da177e4 LT |
1338 | /* |
1339 | * Vendor-specific initialization. In this section we | |
1340 | * canonicalize the feature flags, meaning if there are | |
1341 | * features a certain CPU supports which CPUID doesn't | |
1342 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
1343 | * we handle them here. | |
1344 | * | |
1345 | * At the end of this section, c->x86_capability better | |
1346 | * indicate the features this CPU genuinely supports! | |
1347 | */ | |
1348 | if (this_cpu->c_init) | |
1349 | this_cpu->c_init(c); | |
1350 | ||
1351 | /* Disable the PN if appropriate */ | |
1352 | squash_the_stupid_serial_number(c); | |
1353 | ||
aa35f896 | 1354 | /* Set up SMEP/SMAP/UMIP */ |
b2cc2a07 PA |
1355 | setup_smep(c); |
1356 | setup_smap(c); | |
aa35f896 | 1357 | setup_umip(c); |
b2cc2a07 | 1358 | |
1da177e4 | 1359 | /* |
0f3fa48a IM |
1360 | * The vendor-specific functions might have changed features. |
1361 | * Now we do "generic changes." | |
1da177e4 LT |
1362 | */ |
1363 | ||
b38b0665 PA |
1364 | /* Filter out anything that depends on CPUID levels we don't have */ |
1365 | filter_cpuid_features(c, true); | |
1366 | ||
1da177e4 | 1367 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 1368 | if (!c->x86_model_id[0]) { |
02dde8b4 | 1369 | const char *p; |
1da177e4 | 1370 | p = table_lookup_model(c); |
34048c9e | 1371 | if (p) |
1da177e4 LT |
1372 | strcpy(c->x86_model_id, p); |
1373 | else | |
1374 | /* Last resort... */ | |
1375 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 1376 | c->x86, c->x86_model); |
1da177e4 LT |
1377 | } |
1378 | ||
102bbe3a YL |
1379 | #ifdef CONFIG_X86_64 |
1380 | detect_ht(c); | |
1381 | #endif | |
1382 | ||
49d859d7 | 1383 | x86_init_rdrand(c); |
cbc82b17 | 1384 | x86_init_cache_qos(c); |
06976945 | 1385 | setup_pku(c); |
3e0c3737 YL |
1386 | |
1387 | /* | |
6a6256f9 | 1388 | * Clear/Set all flags overridden by options, need do it |
3e0c3737 YL |
1389 | * before following smp all cpus cap AND. |
1390 | */ | |
8bf1ebca | 1391 | apply_forced_caps(c); |
3e0c3737 | 1392 | |
1da177e4 LT |
1393 | /* |
1394 | * On SMP, boot_cpu_data holds the common feature set between | |
1395 | * all CPUs; so make sure that we indicate which features are | |
1396 | * common between the CPUs. The first time this routine gets | |
1397 | * executed, c == &boot_cpu_data. | |
1398 | */ | |
34048c9e | 1399 | if (c != &boot_cpu_data) { |
1da177e4 | 1400 | /* AND the already accumulated flags with these */ |
9d31d35b | 1401 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 | 1402 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
65fc985b BP |
1403 | |
1404 | /* OR, i.e. replicate the bug flags */ | |
1405 | for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) | |
1406 | c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; | |
1da177e4 LT |
1407 | } |
1408 | ||
1409 | /* Init Machine Check Exception if available. */ | |
5e09954a | 1410 | mcheck_cpu_init(c); |
30d432df AK |
1411 | |
1412 | select_idle_routine(c); | |
102bbe3a | 1413 | |
de2d9445 | 1414 | #ifdef CONFIG_NUMA |
102bbe3a YL |
1415 | numa_add_cpu(smp_processor_id()); |
1416 | #endif | |
a6c4e076 | 1417 | } |
31ab269a | 1418 | |
8b6c0ab1 IM |
1419 | /* |
1420 | * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions | |
1421 | * on 32-bit kernels: | |
1422 | */ | |
cfda7bb9 AL |
1423 | #ifdef CONFIG_X86_32 |
1424 | void enable_sep_cpu(void) | |
1425 | { | |
8b6c0ab1 IM |
1426 | struct tss_struct *tss; |
1427 | int cpu; | |
cfda7bb9 | 1428 | |
b3edfda4 BP |
1429 | if (!boot_cpu_has(X86_FEATURE_SEP)) |
1430 | return; | |
1431 | ||
8b6c0ab1 | 1432 | cpu = get_cpu(); |
c482feef | 1433 | tss = &per_cpu(cpu_tss_rw, cpu); |
8b6c0ab1 | 1434 | |
8b6c0ab1 | 1435 | /* |
cf9328cc AL |
1436 | * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- |
1437 | * see the big comment in struct x86_hw_tss's definition. | |
8b6c0ab1 | 1438 | */ |
cfda7bb9 AL |
1439 | |
1440 | tss->x86_tss.ss1 = __KERNEL_CS; | |
8b6c0ab1 | 1441 | wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); |
4fe2d8b1 | 1442 | wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); |
4c8cd0c5 | 1443 | wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); |
8b6c0ab1 | 1444 | |
cfda7bb9 AL |
1445 | put_cpu(); |
1446 | } | |
e04d645f GC |
1447 | #endif |
1448 | ||
a6c4e076 JF |
1449 | void __init identify_boot_cpu(void) |
1450 | { | |
1451 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 1452 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1453 | sysenter_setup(); |
6fe940d6 | 1454 | enable_sep_cpu(); |
102bbe3a | 1455 | #endif |
5b556332 | 1456 | cpu_detect_tlb(&boot_cpu_data); |
a6c4e076 | 1457 | } |
3b520b23 | 1458 | |
148f9bb8 | 1459 | void identify_secondary_cpu(struct cpuinfo_x86 *c) |
a6c4e076 JF |
1460 | { |
1461 | BUG_ON(c == &boot_cpu_data); | |
1462 | identify_cpu(c); | |
102bbe3a | 1463 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1464 | enable_sep_cpu(); |
102bbe3a | 1465 | #endif |
a6c4e076 | 1466 | mtrr_ap_init(); |
9d85eb91 | 1467 | validate_apic_and_package_id(c); |
23b9eab9 | 1468 | x86_spec_ctrl_setup_ap(); |
1da177e4 LT |
1469 | } |
1470 | ||
191679fd AK |
1471 | static __init int setup_noclflush(char *arg) |
1472 | { | |
840d2830 | 1473 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); |
da4aaa7d | 1474 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); |
191679fd AK |
1475 | return 1; |
1476 | } | |
1477 | __setup("noclflush", setup_noclflush); | |
1478 | ||
148f9bb8 | 1479 | void print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1480 | { |
02dde8b4 | 1481 | const char *vendor = NULL; |
1da177e4 | 1482 | |
0f3fa48a | 1483 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1484 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1485 | } else { |
1486 | if (c->cpuid_level >= 0) | |
1487 | vendor = c->x86_vendor_id; | |
1488 | } | |
1da177e4 | 1489 | |
bd32a8cf | 1490 | if (vendor && !strstr(c->x86_model_id, vendor)) |
1b74dde7 | 1491 | pr_cont("%s ", vendor); |
1da177e4 | 1492 | |
9d31d35b | 1493 | if (c->x86_model_id[0]) |
1b74dde7 | 1494 | pr_cont("%s", c->x86_model_id); |
1da177e4 | 1495 | else |
1b74dde7 | 1496 | pr_cont("%d86", c->x86); |
1da177e4 | 1497 | |
1b74dde7 | 1498 | pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); |
924e101a | 1499 | |
dd7cc466 JZ |
1500 | if (c->x86_stepping || c->cpuid_level >= 0) |
1501 | pr_cont(", stepping: 0x%x)\n", c->x86_stepping); | |
1da177e4 | 1502 | else |
1b74dde7 | 1503 | pr_cont(")\n"); |
1da177e4 LT |
1504 | } |
1505 | ||
0c2a3913 AK |
1506 | /* |
1507 | * clearcpuid= was already parsed in fpu__init_parse_early_param. | |
1508 | * But we need to keep a dummy __setup around otherwise it would | |
1509 | * show up as an environment variable for init. | |
1510 | */ | |
1511 | static __init int setup_clearcpuid(char *arg) | |
ac72e788 | 1512 | { |
ac72e788 AK |
1513 | return 1; |
1514 | } | |
0c2a3913 | 1515 | __setup("clearcpuid=", setup_clearcpuid); |
ac72e788 | 1516 | |
d5494d4f | 1517 | #ifdef CONFIG_X86_64 |
947e76cd | 1518 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
277d5b40 | 1519 | irq_stack_union) __aligned(PAGE_SIZE) __visible; |
0f3fa48a | 1520 | |
bdf977b3 | 1521 | /* |
a7fcf28d AL |
1522 | * The following percpu variables are hot. Align current_task to |
1523 | * cacheline size such that they fall in the same cacheline. | |
bdf977b3 TH |
1524 | */ |
1525 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1526 | &init_task; | |
1527 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1528 | |
bdf977b3 | 1529 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
4950d6d4 | 1530 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE; |
bdf977b3 | 1531 | |
277d5b40 | 1532 | DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; |
d5494d4f | 1533 | |
c2daa3be PZ |
1534 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1535 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
1536 | ||
d5494d4f YL |
1537 | /* May not be marked __init: used by software suspend */ |
1538 | void syscall_init(void) | |
1da177e4 | 1539 | { |
3386bc8a AL |
1540 | extern char _entry_trampoline[]; |
1541 | extern char entry_SYSCALL_64_trampoline[]; | |
1542 | ||
72f5e08d | 1543 | int cpu = smp_processor_id(); |
3386bc8a AL |
1544 | unsigned long SYSCALL64_entry_trampoline = |
1545 | (unsigned long)get_cpu_entry_area(cpu)->entry_trampoline + | |
1546 | (entry_SYSCALL_64_trampoline - _entry_trampoline); | |
72f5e08d | 1547 | |
31ac34ca | 1548 | wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); |
8d4b0678 TG |
1549 | if (static_cpu_has(X86_FEATURE_PTI)) |
1550 | wrmsrl(MSR_LSTAR, SYSCALL64_entry_trampoline); | |
1551 | else | |
1552 | wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); | |
d56fe4bf IM |
1553 | |
1554 | #ifdef CONFIG_IA32_EMULATION | |
47edb651 | 1555 | wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); |
a76c7f46 | 1556 | /* |
487d1edb DV |
1557 | * This only works on Intel CPUs. |
1558 | * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. | |
1559 | * This does not cause SYSENTER to jump to the wrong location, because | |
1560 | * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). | |
a76c7f46 DV |
1561 | */ |
1562 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); | |
4fe2d8b1 | 1563 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1)); |
4c8cd0c5 | 1564 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); |
d56fe4bf | 1565 | #else |
47edb651 | 1566 | wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); |
6b51311c | 1567 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); |
d56fe4bf IM |
1568 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); |
1569 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); | |
d5494d4f | 1570 | #endif |
03ae5768 | 1571 | |
d5494d4f YL |
1572 | /* Flags to clear on syscall */ |
1573 | wrmsrl(MSR_SYSCALL_MASK, | |
63bcff2a | 1574 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| |
8c7aa698 | 1575 | X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); |
1da177e4 | 1576 | } |
62111195 | 1577 | |
d5494d4f YL |
1578 | /* |
1579 | * Copies of the original ist values from the tss are only accessed during | |
1580 | * debugging, no special alignment required. | |
1581 | */ | |
1582 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1583 | ||
228bdaa9 | 1584 | static DEFINE_PER_CPU(unsigned long, debug_stack_addr); |
42181186 | 1585 | DEFINE_PER_CPU(int, debug_stack_usage); |
228bdaa9 SR |
1586 | |
1587 | int is_debug_stack(unsigned long addr) | |
1588 | { | |
89cbc767 CL |
1589 | return __this_cpu_read(debug_stack_usage) || |
1590 | (addr <= __this_cpu_read(debug_stack_addr) && | |
1591 | addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); | |
228bdaa9 | 1592 | } |
0f46efeb | 1593 | NOKPROBE_SYMBOL(is_debug_stack); |
228bdaa9 | 1594 | |
629f4f9d | 1595 | DEFINE_PER_CPU(u32, debug_idt_ctr); |
f8988175 | 1596 | |
228bdaa9 SR |
1597 | void debug_stack_set_zero(void) |
1598 | { | |
629f4f9d SA |
1599 | this_cpu_inc(debug_idt_ctr); |
1600 | load_current_idt(); | |
228bdaa9 | 1601 | } |
0f46efeb | 1602 | NOKPROBE_SYMBOL(debug_stack_set_zero); |
228bdaa9 SR |
1603 | |
1604 | void debug_stack_reset(void) | |
1605 | { | |
629f4f9d | 1606 | if (WARN_ON(!this_cpu_read(debug_idt_ctr))) |
f8988175 | 1607 | return; |
629f4f9d SA |
1608 | if (this_cpu_dec_return(debug_idt_ctr) == 0) |
1609 | load_current_idt(); | |
228bdaa9 | 1610 | } |
0f46efeb | 1611 | NOKPROBE_SYMBOL(debug_stack_reset); |
228bdaa9 | 1612 | |
0f3fa48a | 1613 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1614 | |
bdf977b3 TH |
1615 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1616 | EXPORT_PER_CPU_SYMBOL(current_task); | |
c2daa3be PZ |
1617 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1618 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
bdf977b3 | 1619 | |
a7fcf28d AL |
1620 | /* |
1621 | * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find | |
1622 | * the top of the kernel stack. Use an extra percpu variable to track the | |
1623 | * top of the kernel stack directly. | |
1624 | */ | |
1625 | DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = | |
1626 | (unsigned long)&init_thread_union + THREAD_SIZE; | |
1627 | EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); | |
1628 | ||
60a5317f | 1629 | #ifdef CONFIG_CC_STACKPROTECTOR |
53f82452 | 1630 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1631 | #endif |
d5494d4f | 1632 | |
0f3fa48a | 1633 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1634 | |
9766cdbc JSR |
1635 | /* |
1636 | * Clear all 6 debug registers: | |
1637 | */ | |
1638 | static void clear_all_debug_regs(void) | |
1639 | { | |
1640 | int i; | |
1641 | ||
1642 | for (i = 0; i < 8; i++) { | |
1643 | /* Ignore db4, db5 */ | |
1644 | if ((i == 4) || (i == 5)) | |
1645 | continue; | |
1646 | ||
1647 | set_debugreg(0, i); | |
1648 | } | |
1649 | } | |
c5413fbe | 1650 | |
0bb9fef9 JW |
1651 | #ifdef CONFIG_KGDB |
1652 | /* | |
1653 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1654 | * connection established. | |
1655 | */ | |
1656 | static void dbg_restore_debug_regs(void) | |
1657 | { | |
1658 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1659 | arch_kgdb_ops.correct_hw_break(); | |
1660 | } | |
1661 | #else /* ! CONFIG_KGDB */ | |
1662 | #define dbg_restore_debug_regs() | |
1663 | #endif /* ! CONFIG_KGDB */ | |
1664 | ||
ce4b1b16 IM |
1665 | static void wait_for_master_cpu(int cpu) |
1666 | { | |
1667 | #ifdef CONFIG_SMP | |
1668 | /* | |
1669 | * wait for ACK from master CPU before continuing | |
1670 | * with AP initialization | |
1671 | */ | |
1672 | WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); | |
1673 | while (!cpumask_test_cpu(cpu, cpu_callout_mask)) | |
1674 | cpu_relax(); | |
1675 | #endif | |
1676 | } | |
1677 | ||
d2cbcc49 RR |
1678 | /* |
1679 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1680 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1681 | * and IDT. We reload them nevertheless, this function acts as a | |
1682 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1683 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1684 | */ |
1ba76586 | 1685 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1686 | |
148f9bb8 | 1687 | void cpu_init(void) |
1ba76586 | 1688 | { |
0fe1e009 | 1689 | struct orig_ist *oist; |
1ba76586 | 1690 | struct task_struct *me; |
0f3fa48a IM |
1691 | struct tss_struct *t; |
1692 | unsigned long v; | |
fb59831b | 1693 | int cpu = raw_smp_processor_id(); |
1ba76586 YL |
1694 | int i; |
1695 | ||
ce4b1b16 IM |
1696 | wait_for_master_cpu(cpu); |
1697 | ||
1e02ce4c AL |
1698 | /* |
1699 | * Initialize the CR4 shadow before doing anything that could | |
1700 | * try to read it. | |
1701 | */ | |
1702 | cr4_init_shadow(); | |
1703 | ||
777284b6 BP |
1704 | if (cpu) |
1705 | load_ucode_ap(); | |
e6ebf5de | 1706 | |
c482feef | 1707 | t = &per_cpu(cpu_tss_rw, cpu); |
0fe1e009 | 1708 | oist = &per_cpu(orig_ist, cpu); |
0f3fa48a | 1709 | |
e7a22c1e | 1710 | #ifdef CONFIG_NUMA |
27fd185f | 1711 | if (this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
1712 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
1713 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1714 | #endif |
1ba76586 YL |
1715 | |
1716 | me = current; | |
1717 | ||
2eaad1fd | 1718 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 | 1719 | |
375074cc | 1720 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
1ba76586 YL |
1721 | |
1722 | /* | |
1723 | * Initialize the per-CPU GDT with the boot GDT, | |
1724 | * and set up the GDT descriptor: | |
1725 | */ | |
1726 | ||
552be871 | 1727 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1728 | loadsegment(fs, 0); |
1729 | ||
cf910e83 | 1730 | load_current_idt(); |
1ba76586 YL |
1731 | |
1732 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1733 | syscall_init(); | |
1734 | ||
1735 | wrmsrl(MSR_FS_BASE, 0); | |
1736 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1737 | barrier(); | |
1738 | ||
4763ed4d | 1739 | x86_configure_nx(); |
659006bf | 1740 | x2apic_setup(); |
1ba76586 YL |
1741 | |
1742 | /* | |
1743 | * set up and load the per-CPU TSS | |
1744 | */ | |
0fe1e009 | 1745 | if (!oist->ist[0]) { |
40e7f949 | 1746 | char *estacks = get_cpu_entry_area(cpu)->exception_stacks; |
0f3fa48a | 1747 | |
1ba76586 | 1748 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
0f3fa48a | 1749 | estacks += exception_stack_sizes[v]; |
0fe1e009 | 1750 | oist->ist[v] = t->x86_tss.ist[v] = |
1ba76586 | 1751 | (unsigned long)estacks; |
228bdaa9 SR |
1752 | if (v == DEBUG_STACK-1) |
1753 | per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; | |
1ba76586 YL |
1754 | } |
1755 | } | |
1756 | ||
7fb983b4 | 1757 | t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; |
0f3fa48a | 1758 | |
1ba76586 YL |
1759 | /* |
1760 | * <= is required because the CPU will access up to | |
1761 | * 8 bits beyond the end of the IO permission bitmap. | |
1762 | */ | |
1763 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1764 | t->io_bitmap[i] = ~0UL; | |
1765 | ||
f1f10076 | 1766 | mmgrab(&init_mm); |
1ba76586 | 1767 | me->active_mm = &init_mm; |
8c5dfd25 | 1768 | BUG_ON(me->mm); |
72c0098d | 1769 | initialize_tlbstate_and_flush(); |
1ba76586 YL |
1770 | enter_lazy_tlb(&init_mm, me); |
1771 | ||
20bb8344 | 1772 | /* |
7f2590a1 AL |
1773 | * Initialize the TSS. sp0 points to the entry trampoline stack |
1774 | * regardless of what task is running. | |
20bb8344 | 1775 | */ |
72f5e08d | 1776 | set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); |
1ba76586 | 1777 | load_TR_desc(); |
4fe2d8b1 | 1778 | load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); |
20bb8344 | 1779 | |
37868fe1 | 1780 | load_mm_ldt(&init_mm); |
1ba76586 | 1781 | |
0bb9fef9 JW |
1782 | clear_all_debug_regs(); |
1783 | dbg_restore_debug_regs(); | |
1ba76586 | 1784 | |
21c4cd10 | 1785 | fpu__init_cpu(); |
1ba76586 | 1786 | |
1ba76586 YL |
1787 | if (is_uv_system()) |
1788 | uv_cpu_init(); | |
69218e47 | 1789 | |
69218e47 | 1790 | load_fixmap_gdt(cpu); |
1ba76586 YL |
1791 | } |
1792 | ||
1793 | #else | |
1794 | ||
148f9bb8 | 1795 | void cpu_init(void) |
9ee79a3d | 1796 | { |
d2cbcc49 RR |
1797 | int cpu = smp_processor_id(); |
1798 | struct task_struct *curr = current; | |
c482feef | 1799 | struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu); |
62111195 | 1800 | |
ce4b1b16 | 1801 | wait_for_master_cpu(cpu); |
e6ebf5de | 1802 | |
5b2bdbc8 SR |
1803 | /* |
1804 | * Initialize the CR4 shadow before doing anything that could | |
1805 | * try to read it. | |
1806 | */ | |
1807 | cr4_init_shadow(); | |
1808 | ||
ce4b1b16 | 1809 | show_ucode_info_early(); |
62111195 | 1810 | |
1b74dde7 | 1811 | pr_info("Initializing CPU#%d\n", cpu); |
62111195 | 1812 | |
362f924b | 1813 | if (cpu_feature_enabled(X86_FEATURE_VME) || |
59e21e3d | 1814 | boot_cpu_has(X86_FEATURE_TSC) || |
362f924b | 1815 | boot_cpu_has(X86_FEATURE_DE)) |
375074cc | 1816 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
62111195 | 1817 | |
cf910e83 | 1818 | load_current_idt(); |
552be871 | 1819 | switch_to_new_gdt(cpu); |
1da177e4 | 1820 | |
1da177e4 LT |
1821 | /* |
1822 | * Set up and load the per-CPU TSS and LDT | |
1823 | */ | |
f1f10076 | 1824 | mmgrab(&init_mm); |
62111195 | 1825 | curr->active_mm = &init_mm; |
8c5dfd25 | 1826 | BUG_ON(curr->mm); |
72c0098d | 1827 | initialize_tlbstate_and_flush(); |
62111195 | 1828 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1829 | |
20bb8344 | 1830 | /* |
e62c62f9 JR |
1831 | * Initialize the TSS. sp0 points to the entry trampoline stack |
1832 | * regardless of what task is running. | |
20bb8344 | 1833 | */ |
72f5e08d | 1834 | set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); |
1da177e4 | 1835 | load_TR_desc(); |
e62c62f9 | 1836 | load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); |
20bb8344 | 1837 | |
37868fe1 | 1838 | load_mm_ldt(&init_mm); |
1da177e4 | 1839 | |
7fb983b4 | 1840 | t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; |
f9a196b8 | 1841 | |
22c4e308 | 1842 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1843 | /* Set up doublefault TSS pointer in the GDT */ |
1844 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1845 | #endif |
1da177e4 | 1846 | |
9766cdbc | 1847 | clear_all_debug_regs(); |
0bb9fef9 | 1848 | dbg_restore_debug_regs(); |
1da177e4 | 1849 | |
21c4cd10 | 1850 | fpu__init_cpu(); |
69218e47 | 1851 | |
69218e47 | 1852 | load_fixmap_gdt(cpu); |
1da177e4 | 1853 | } |
1ba76586 | 1854 | #endif |
5700f743 | 1855 | |
b51ef52d LA |
1856 | static void bsp_resume(void) |
1857 | { | |
1858 | if (this_cpu->c_bsp_resume) | |
1859 | this_cpu->c_bsp_resume(&boot_cpu_data); | |
1860 | } | |
1861 | ||
1862 | static struct syscore_ops cpu_syscore_ops = { | |
1863 | .resume = bsp_resume, | |
1864 | }; | |
1865 | ||
1866 | static int __init init_cpu_syscore(void) | |
1867 | { | |
1868 | register_syscore_ops(&cpu_syscore_ops); | |
1869 | return 0; | |
1870 | } | |
1871 | core_initcall(init_cpu_syscore); | |
192f3c3b BP |
1872 | |
1873 | /* | |
1874 | * The microcode loader calls this upon late microcode load to recheck features, | |
1875 | * only when microcode has been updated. Caller holds microcode_mutex and CPU | |
1876 | * hotplug lock. | |
1877 | */ | |
1878 | void microcode_check(void) | |
1879 | { | |
6b697cd8 BP |
1880 | struct cpuinfo_x86 info; |
1881 | ||
192f3c3b | 1882 | perf_check_microcode(); |
6b697cd8 BP |
1883 | |
1884 | /* Reload CPUID max function as it might've changed. */ | |
1885 | info.cpuid_level = cpuid_eax(0); | |
1886 | ||
1887 | /* | |
1888 | * Copy all capability leafs to pick up the synthetic ones so that | |
1889 | * memcmp() below doesn't fail on that. The ones coming from CPUID will | |
1890 | * get overwritten in get_cpu_cap(). | |
1891 | */ | |
1892 | memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); | |
1893 | ||
1894 | get_cpu_cap(&info); | |
1895 | ||
1896 | if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) | |
1897 | return; | |
1898 | ||
1899 | pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); | |
1900 | pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); | |
192f3c3b | 1901 | } |