]>
Commit | Line | Data |
---|---|---|
f0fc4aff | 1 | #include <linux/bootmem.h> |
9766cdbc | 2 | #include <linux/linkage.h> |
f0fc4aff | 3 | #include <linux/bitops.h> |
9766cdbc | 4 | #include <linux/kernel.h> |
f0fc4aff | 5 | #include <linux/module.h> |
9766cdbc JSR |
6 | #include <linux/percpu.h> |
7 | #include <linux/string.h> | |
1da177e4 | 8 | #include <linux/delay.h> |
9766cdbc JSR |
9 | #include <linux/sched.h> |
10 | #include <linux/init.h> | |
11 | #include <linux/kgdb.h> | |
1da177e4 | 12 | #include <linux/smp.h> |
9766cdbc JSR |
13 | #include <linux/io.h> |
14 | ||
15 | #include <asm/stackprotector.h> | |
cdd6c482 | 16 | #include <asm/perf_event.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
49d859d7 | 18 | #include <asm/archrandom.h> |
9766cdbc JSR |
19 | #include <asm/hypervisor.h> |
20 | #include <asm/processor.h> | |
f649e938 | 21 | #include <asm/debugreg.h> |
9766cdbc | 22 | #include <asm/sections.h> |
8bdbd962 AC |
23 | #include <linux/topology.h> |
24 | #include <linux/cpumask.h> | |
9766cdbc | 25 | #include <asm/pgtable.h> |
60063497 | 26 | #include <linux/atomic.h> |
9766cdbc JSR |
27 | #include <asm/proto.h> |
28 | #include <asm/setup.h> | |
29 | #include <asm/apic.h> | |
30 | #include <asm/desc.h> | |
31 | #include <asm/i387.h> | |
1361b83a | 32 | #include <asm/fpu-internal.h> |
27b07da7 | 33 | #include <asm/mtrr.h> |
8bdbd962 | 34 | #include <linux/numa.h> |
9766cdbc JSR |
35 | #include <asm/asm.h> |
36 | #include <asm/cpu.h> | |
a03a3e28 | 37 | #include <asm/mce.h> |
9766cdbc | 38 | #include <asm/msr.h> |
8d4a4300 | 39 | #include <asm/pat.h> |
e641f5f5 IM |
40 | |
41 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 42 | #include <asm/uv/uv.h> |
1da177e4 LT |
43 | #endif |
44 | ||
45 | #include "cpu.h" | |
46 | ||
c2d1cec1 | 47 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 48 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
49 | cpumask_var_t cpu_callout_mask; |
50 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
51 | |
52 | /* representing cpus for which sibling maps can be computed */ | |
53 | cpumask_var_t cpu_sibling_setup_mask; | |
54 | ||
2f2f52ba | 55 | /* correctly size the local cpu masks */ |
4369f1fb | 56 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
57 | { |
58 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
59 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
60 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
61 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
62 | } | |
63 | ||
e8055139 OZ |
64 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
65 | { | |
66 | #ifdef CONFIG_X86_64 | |
27c13ece | 67 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
68 | #else |
69 | /* Not much we can do here... */ | |
70 | /* Check if at least it has cpuid */ | |
71 | if (c->cpuid_level == -1) { | |
72 | /* No cpuid. It must be an ancient CPU */ | |
73 | if (c->x86 == 4) | |
74 | strcpy(c->x86_model_id, "486"); | |
75 | else if (c->x86 == 3) | |
76 | strcpy(c->x86_model_id, "386"); | |
77 | } | |
78 | #endif | |
79 | } | |
80 | ||
81 | static const struct cpu_dev __cpuinitconst default_cpu = { | |
82 | .c_init = default_init, | |
83 | .c_vendor = "Unknown", | |
84 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
85 | }; | |
86 | ||
87 | static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu; | |
0a488a53 | 88 | |
06deef89 | 89 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 90 | #ifdef CONFIG_X86_64 |
06deef89 BG |
91 | /* |
92 | * We need valid kernel segments for data and code in long mode too | |
93 | * IRET will check the segment types kkeil 2000/10/28 | |
94 | * Also sysret mandates a special GDT layout | |
95 | * | |
9766cdbc | 96 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
97 | * Hopefully nobody expects them at a fixed place (Wine?) |
98 | */ | |
1e5de182 AM |
99 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
100 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
101 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
102 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
103 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
104 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 105 | #else |
1e5de182 AM |
106 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
107 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
108 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
109 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
110 | /* |
111 | * Segments used for calling PnP BIOS have byte granularity. | |
112 | * They code segments and data segments have fixed 64k limits, | |
113 | * the transfer segment sizes are set at run time. | |
114 | */ | |
6842ef0e | 115 | /* 32-bit code */ |
1e5de182 | 116 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 117 | /* 16-bit code */ |
1e5de182 | 118 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 119 | /* 16-bit data */ |
1e5de182 | 120 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 121 | /* 16-bit data */ |
1e5de182 | 122 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 123 | /* 16-bit data */ |
1e5de182 | 124 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
125 | /* |
126 | * The APM segments have byte granularity and their bases | |
127 | * are set at run time. All have 64k limits. | |
128 | */ | |
6842ef0e | 129 | /* 32-bit code */ |
1e5de182 | 130 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 131 | /* 16-bit code */ |
1e5de182 | 132 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 133 | /* data */ |
72c4d853 | 134 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 135 | |
1e5de182 AM |
136 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
137 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 138 | GDT_STACK_CANARY_INIT |
950ad7ff | 139 | #endif |
06deef89 | 140 | } }; |
7a61d35d | 141 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 142 | |
0c752a93 SS |
143 | static int __init x86_xsave_setup(char *s) |
144 | { | |
145 | setup_clear_cpu_cap(X86_FEATURE_XSAVE); | |
6bad06b7 | 146 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); |
0c752a93 SS |
147 | return 1; |
148 | } | |
149 | __setup("noxsave", x86_xsave_setup); | |
150 | ||
6bad06b7 SS |
151 | static int __init x86_xsaveopt_setup(char *s) |
152 | { | |
153 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); | |
154 | return 1; | |
155 | } | |
156 | __setup("noxsaveopt", x86_xsaveopt_setup); | |
157 | ||
ba51dced | 158 | #ifdef CONFIG_X86_32 |
3bc9b76b | 159 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 160 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 161 | |
0a488a53 YL |
162 | static int __init cachesize_setup(char *str) |
163 | { | |
164 | get_option(&str, &cachesize_override); | |
165 | return 1; | |
166 | } | |
167 | __setup("cachesize=", cachesize_setup); | |
168 | ||
0a488a53 YL |
169 | static int __init x86_fxsr_setup(char *s) |
170 | { | |
171 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
172 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
173 | return 1; | |
174 | } | |
175 | __setup("nofxsr", x86_fxsr_setup); | |
176 | ||
177 | static int __init x86_sep_setup(char *s) | |
178 | { | |
179 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
180 | return 1; | |
181 | } | |
182 | __setup("nosep", x86_sep_setup); | |
183 | ||
184 | /* Standard macro to see if a specific flag is changeable */ | |
185 | static inline int flag_is_changeable_p(u32 flag) | |
186 | { | |
187 | u32 f1, f2; | |
188 | ||
94f6bac1 KH |
189 | /* |
190 | * Cyrix and IDT cpus allow disabling of CPUID | |
191 | * so the code below may return different results | |
192 | * when it is executed before and after enabling | |
193 | * the CPUID. Add "volatile" to not allow gcc to | |
194 | * optimize the subsequent calls to this function. | |
195 | */ | |
0f3fa48a IM |
196 | asm volatile ("pushfl \n\t" |
197 | "pushfl \n\t" | |
198 | "popl %0 \n\t" | |
199 | "movl %0, %1 \n\t" | |
200 | "xorl %2, %0 \n\t" | |
201 | "pushl %0 \n\t" | |
202 | "popfl \n\t" | |
203 | "pushfl \n\t" | |
204 | "popl %0 \n\t" | |
205 | "popfl \n\t" | |
206 | ||
94f6bac1 KH |
207 | : "=&r" (f1), "=&r" (f2) |
208 | : "ir" (flag)); | |
0a488a53 YL |
209 | |
210 | return ((f1^f2) & flag) != 0; | |
211 | } | |
212 | ||
213 | /* Probe for the CPUID instruction */ | |
214 | static int __cpuinit have_cpuid_p(void) | |
215 | { | |
216 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
217 | } | |
218 | ||
219 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
220 | { | |
0f3fa48a IM |
221 | unsigned long lo, hi; |
222 | ||
223 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
224 | return; | |
225 | ||
226 | /* Disable processor serial number: */ | |
227 | ||
228 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
229 | lo |= 0x200000; | |
230 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
231 | ||
232 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
233 | clear_cpu_cap(c, X86_FEATURE_PN); | |
234 | ||
235 | /* Disabling the serial number may affect the cpuid level */ | |
236 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
237 | } |
238 | ||
239 | static int __init x86_serial_nr_setup(char *s) | |
240 | { | |
241 | disable_x86_serial_nr = 0; | |
242 | return 1; | |
243 | } | |
244 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 245 | #else |
102bbe3a YL |
246 | static inline int flag_is_changeable_p(u32 flag) |
247 | { | |
248 | return 1; | |
249 | } | |
ba51dced YL |
250 | /* Probe for the CPUID instruction */ |
251 | static inline int have_cpuid_p(void) | |
252 | { | |
253 | return 1; | |
254 | } | |
102bbe3a YL |
255 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
256 | { | |
257 | } | |
ba51dced | 258 | #endif |
0a488a53 | 259 | |
82da65da | 260 | static int disable_smep __cpuinitdata; |
de5397ad FY |
261 | static __init int setup_disable_smep(char *arg) |
262 | { | |
263 | disable_smep = 1; | |
264 | return 1; | |
265 | } | |
266 | __setup("nosmep", setup_disable_smep); | |
267 | ||
82da65da | 268 | static __cpuinit void setup_smep(struct cpuinfo_x86 *c) |
de5397ad FY |
269 | { |
270 | if (cpu_has(c, X86_FEATURE_SMEP)) { | |
271 | if (unlikely(disable_smep)) { | |
272 | setup_clear_cpu_cap(X86_FEATURE_SMEP); | |
273 | clear_in_cr4(X86_CR4_SMEP); | |
274 | } else | |
275 | set_in_cr4(X86_CR4_SMEP); | |
276 | } | |
277 | } | |
278 | ||
b38b0665 PA |
279 | /* |
280 | * Some CPU features depend on higher CPUID levels, which may not always | |
281 | * be available due to CPUID level capping or broken virtualization | |
282 | * software. Add those features to this table to auto-disable them. | |
283 | */ | |
284 | struct cpuid_dependent_feature { | |
285 | u32 feature; | |
286 | u32 level; | |
287 | }; | |
0f3fa48a | 288 | |
b38b0665 PA |
289 | static const struct cpuid_dependent_feature __cpuinitconst |
290 | cpuid_dependent_features[] = { | |
291 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
292 | { X86_FEATURE_DCA, 0x00000009 }, | |
293 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
294 | { 0, 0 } | |
295 | }; | |
296 | ||
297 | static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) | |
298 | { | |
299 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 300 | |
b38b0665 | 301 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
302 | |
303 | if (!cpu_has(c, df->feature)) | |
304 | continue; | |
b38b0665 PA |
305 | /* |
306 | * Note: cpuid_level is set to -1 if unavailable, but | |
307 | * extended_extended_level is set to 0 if unavailable | |
308 | * and the legitimate extended levels are all negative | |
309 | * when signed; hence the weird messing around with | |
310 | * signs here... | |
311 | */ | |
0f3fa48a | 312 | if (!((s32)df->level < 0 ? |
f6db44df | 313 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
314 | (s32)df->level > (s32)c->cpuid_level)) |
315 | continue; | |
316 | ||
317 | clear_cpu_cap(c, df->feature); | |
318 | if (!warn) | |
319 | continue; | |
320 | ||
321 | printk(KERN_WARNING | |
322 | "CPU: CPU feature %s disabled, no CPUID level 0x%x\n", | |
323 | x86_cap_flags[df->feature], df->level); | |
b38b0665 | 324 | } |
f6db44df | 325 | } |
b38b0665 | 326 | |
102bbe3a YL |
327 | /* |
328 | * Naming convention should be: <Name> [(<Codename>)] | |
329 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
330 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
331 | * isn't used | |
102bbe3a YL |
332 | */ |
333 | ||
334 | /* Look up CPU names by table lookup. */ | |
02dde8b4 | 335 | static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 336 | { |
02dde8b4 | 337 | const struct cpu_model_info *info; |
102bbe3a YL |
338 | |
339 | if (c->x86_model >= 16) | |
340 | return NULL; /* Range check */ | |
341 | ||
342 | if (!this_cpu) | |
343 | return NULL; | |
344 | ||
345 | info = this_cpu->c_models; | |
346 | ||
347 | while (info && info->family) { | |
348 | if (info->family == c->x86) | |
349 | return info->model_names[c->x86_model]; | |
350 | info++; | |
351 | } | |
352 | return NULL; /* Not found */ | |
353 | } | |
354 | ||
3e0c3737 YL |
355 | __u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata; |
356 | __u32 cpu_caps_set[NCAPINTS] __cpuinitdata; | |
7d851c8d | 357 | |
11e3a840 JF |
358 | void load_percpu_segment(int cpu) |
359 | { | |
360 | #ifdef CONFIG_X86_32 | |
361 | loadsegment(fs, __KERNEL_PERCPU); | |
362 | #else | |
363 | loadsegment(gs, 0); | |
364 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
365 | #endif | |
60a5317f | 366 | load_stack_canary_segment(); |
11e3a840 JF |
367 | } |
368 | ||
0f3fa48a IM |
369 | /* |
370 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
371 | * it's on the real one. | |
372 | */ | |
552be871 | 373 | void switch_to_new_gdt(int cpu) |
9d31d35b YL |
374 | { |
375 | struct desc_ptr gdt_descr; | |
376 | ||
2697fbd5 | 377 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
378 | gdt_descr.size = GDT_SIZE - 1; |
379 | load_gdt(&gdt_descr); | |
2697fbd5 | 380 | /* Reload the per-cpu base */ |
11e3a840 JF |
381 | |
382 | load_percpu_segment(cpu); | |
9d31d35b YL |
383 | } |
384 | ||
02dde8b4 | 385 | static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 386 | |
1b05d60d | 387 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
388 | { |
389 | unsigned int *v; | |
390 | char *p, *q; | |
391 | ||
3da99c97 | 392 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 393 | return; |
1da177e4 | 394 | |
0f3fa48a | 395 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
396 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
397 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
398 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
399 | c->x86_model_id[48] = 0; | |
400 | ||
0f3fa48a IM |
401 | /* |
402 | * Intel chips right-justify this string for some dumb reason; | |
403 | * undo that brain damage: | |
404 | */ | |
1da177e4 | 405 | p = q = &c->x86_model_id[0]; |
34048c9e | 406 | while (*p == ' ') |
9766cdbc | 407 | p++; |
34048c9e | 408 | if (p != q) { |
9766cdbc JSR |
409 | while (*p) |
410 | *q++ = *p++; | |
411 | while (q <= &c->x86_model_id[48]) | |
412 | *q++ = '\0'; /* Zero-pad the rest */ | |
1da177e4 | 413 | } |
1da177e4 LT |
414 | } |
415 | ||
27c13ece | 416 | void __cpuinit cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 417 | { |
9d31d35b | 418 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 419 | |
3da99c97 | 420 | n = c->extended_cpuid_level; |
1da177e4 LT |
421 | |
422 | if (n >= 0x80000005) { | |
9d31d35b | 423 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 424 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
425 | #ifdef CONFIG_X86_64 |
426 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
427 | c->x86_tlbsize = 0; | |
428 | #endif | |
1da177e4 LT |
429 | } |
430 | ||
431 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
432 | return; | |
433 | ||
0a488a53 | 434 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 435 | l2size = ecx >> 16; |
34048c9e | 436 | |
140fc727 YL |
437 | #ifdef CONFIG_X86_64 |
438 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
439 | #else | |
1da177e4 LT |
440 | /* do processor-specific cache resizing */ |
441 | if (this_cpu->c_size_cache) | |
34048c9e | 442 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
443 | |
444 | /* Allow user to override all this if necessary. */ | |
445 | if (cachesize_override != -1) | |
446 | l2size = cachesize_override; | |
447 | ||
34048c9e | 448 | if (l2size == 0) |
1da177e4 | 449 | return; /* Again, no L2 cache is possible */ |
140fc727 | 450 | #endif |
1da177e4 LT |
451 | |
452 | c->x86_cache_size = l2size; | |
1da177e4 LT |
453 | } |
454 | ||
e0ba94f1 AS |
455 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
456 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
457 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
458 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
459 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
460 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
461 | ||
c4211f42 AS |
462 | /* |
463 | * tlb_flushall_shift shows the balance point in replacing cr3 write | |
464 | * with multiple 'invlpg'. It will do this replacement when | |
465 | * flush_tlb_lines <= active_lines/2^tlb_flushall_shift. | |
466 | * If tlb_flushall_shift is -1, means the replacement will be disabled. | |
467 | */ | |
468 | s8 __read_mostly tlb_flushall_shift = -1; | |
469 | ||
e0ba94f1 AS |
470 | void __cpuinit cpu_detect_tlb(struct cpuinfo_x86 *c) |
471 | { | |
472 | if (this_cpu->c_detect_tlb) | |
473 | this_cpu->c_detect_tlb(c); | |
474 | ||
475 | printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \ | |
c4211f42 | 476 | "Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \ |
a9ad773e | 477 | "tlb_flushall_shift: %d\n", |
e0ba94f1 AS |
478 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
479 | tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES], | |
c4211f42 AS |
480 | tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES], |
481 | tlb_flushall_shift); | |
e0ba94f1 AS |
482 | } |
483 | ||
9d31d35b | 484 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 485 | { |
97e4db7c | 486 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
487 | u32 eax, ebx, ecx, edx; |
488 | int index_msb, core_bits; | |
2eaad1fd | 489 | static bool printed; |
1da177e4 | 490 | |
0a488a53 | 491 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 492 | return; |
1da177e4 | 493 | |
0a488a53 YL |
494 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
495 | goto out; | |
1da177e4 | 496 | |
1cd78776 YL |
497 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
498 | return; | |
1da177e4 | 499 | |
0a488a53 | 500 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 501 | |
9d31d35b YL |
502 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
503 | ||
504 | if (smp_num_siblings == 1) { | |
2eaad1fd | 505 | printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); |
0f3fa48a IM |
506 | goto out; |
507 | } | |
9d31d35b | 508 | |
0f3fa48a IM |
509 | if (smp_num_siblings <= 1) |
510 | goto out; | |
9d31d35b | 511 | |
0f3fa48a IM |
512 | index_msb = get_count_order(smp_num_siblings); |
513 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 514 | |
0f3fa48a | 515 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 516 | |
0f3fa48a | 517 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 518 | |
0f3fa48a | 519 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 520 | |
0f3fa48a IM |
521 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
522 | ((1 << core_bits) - 1); | |
1da177e4 | 523 | |
0a488a53 | 524 | out: |
2eaad1fd | 525 | if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { |
0a488a53 YL |
526 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", |
527 | c->phys_proc_id); | |
528 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
529 | c->cpu_core_id); | |
2eaad1fd | 530 | printed = 1; |
9d31d35b | 531 | } |
9d31d35b | 532 | #endif |
97e4db7c | 533 | } |
1da177e4 | 534 | |
3da99c97 | 535 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
536 | { |
537 | char *v = c->x86_vendor_id; | |
0f3fa48a | 538 | int i; |
1da177e4 LT |
539 | |
540 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
541 | if (!cpu_devs[i]) |
542 | break; | |
543 | ||
544 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
545 | (cpu_devs[i]->c_ident[1] && | |
546 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 547 | |
10a434fc YL |
548 | this_cpu = cpu_devs[i]; |
549 | c->x86_vendor = this_cpu->c_x86_vendor; | |
550 | return; | |
1da177e4 LT |
551 | } |
552 | } | |
10a434fc | 553 | |
a9c56953 MK |
554 | printk_once(KERN_ERR |
555 | "CPU: vendor_id '%s' unknown, using generic init.\n" \ | |
556 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 557 | |
fe38d855 CE |
558 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
559 | this_cpu = &default_cpu; | |
1da177e4 LT |
560 | } |
561 | ||
9d31d35b | 562 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 563 | { |
1da177e4 | 564 | /* Get vendor name */ |
4a148513 HH |
565 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
566 | (unsigned int *)&c->x86_vendor_id[0], | |
567 | (unsigned int *)&c->x86_vendor_id[8], | |
568 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 569 | |
1da177e4 | 570 | c->x86 = 4; |
9d31d35b | 571 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
572 | if (c->cpuid_level >= 0x00000001) { |
573 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 574 | |
1da177e4 | 575 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
9d31d35b YL |
576 | c->x86 = (tfms >> 8) & 0xf; |
577 | c->x86_model = (tfms >> 4) & 0xf; | |
578 | c->x86_mask = tfms & 0xf; | |
0f3fa48a | 579 | |
f5f786d0 | 580 | if (c->x86 == 0xf) |
1da177e4 | 581 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 582 | if (c->x86 >= 0x6) |
9d31d35b | 583 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
0f3fa48a | 584 | |
d4387bd3 | 585 | if (cap0 & (1<<19)) { |
d4387bd3 | 586 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 587 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 588 | } |
1da177e4 | 589 | } |
1da177e4 | 590 | } |
3da99c97 | 591 | |
d900329e | 592 | void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 YL |
593 | { |
594 | u32 tfms, xlvl; | |
3da99c97 | 595 | u32 ebx; |
093af8d7 | 596 | |
3da99c97 YL |
597 | /* Intel-defined flags: level 0x00000001 */ |
598 | if (c->cpuid_level >= 0x00000001) { | |
599 | u32 capability, excap; | |
0f3fa48a | 600 | |
3da99c97 YL |
601 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); |
602 | c->x86_capability[0] = capability; | |
603 | c->x86_capability[4] = excap; | |
604 | } | |
093af8d7 | 605 | |
bdc802dc PA |
606 | /* Additional Intel-defined flags: level 0x00000007 */ |
607 | if (c->cpuid_level >= 0x00000007) { | |
608 | u32 eax, ebx, ecx, edx; | |
609 | ||
610 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); | |
611 | ||
2494b030 | 612 | c->x86_capability[9] = ebx; |
bdc802dc PA |
613 | } |
614 | ||
3da99c97 YL |
615 | /* AMD-defined flags: level 0x80000001 */ |
616 | xlvl = cpuid_eax(0x80000000); | |
617 | c->extended_cpuid_level = xlvl; | |
0f3fa48a | 618 | |
3da99c97 YL |
619 | if ((xlvl & 0xffff0000) == 0x80000000) { |
620 | if (xlvl >= 0x80000001) { | |
621 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
622 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 623 | } |
093af8d7 | 624 | } |
093af8d7 | 625 | |
5122c890 YL |
626 | if (c->extended_cpuid_level >= 0x80000008) { |
627 | u32 eax = cpuid_eax(0x80000008); | |
628 | ||
629 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
630 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 631 | } |
13c6c532 JB |
632 | #ifdef CONFIG_X86_32 |
633 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
634 | c->x86_phys_bits = 36; | |
5122c890 | 635 | #endif |
e3224234 YL |
636 | |
637 | if (c->extended_cpuid_level >= 0x80000007) | |
638 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 | 639 | |
1dedefd1 | 640 | init_scattered_cpuid_features(c); |
093af8d7 | 641 | } |
1da177e4 | 642 | |
aef93c8b YL |
643 | static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
644 | { | |
645 | #ifdef CONFIG_X86_32 | |
646 | int i; | |
647 | ||
648 | /* | |
649 | * First of all, decide if this is a 486 or higher | |
650 | * It's a 486 if we can modify the AC flag | |
651 | */ | |
652 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
653 | c->x86 = 4; | |
654 | else | |
655 | c->x86 = 3; | |
656 | ||
657 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
658 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
659 | c->x86_vendor_id[0] = 0; | |
660 | cpu_devs[i]->c_identify(c); | |
661 | if (c->x86_vendor_id[0]) { | |
662 | get_cpu_vendor(c); | |
663 | break; | |
664 | } | |
665 | } | |
666 | #endif | |
667 | } | |
668 | ||
34048c9e PC |
669 | /* |
670 | * Do minimum CPU detection early. | |
671 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
672 | * cache alignment. | |
673 | * The others are not touched to avoid unwanted side effects. | |
674 | * | |
675 | * WARNING: this function is only called on the BP. Don't add code here | |
676 | * that is supposed to run on all CPUs. | |
677 | */ | |
3da99c97 | 678 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 679 | { |
6627d242 YL |
680 | #ifdef CONFIG_X86_64 |
681 | c->x86_clflush_size = 64; | |
13c6c532 JB |
682 | c->x86_phys_bits = 36; |
683 | c->x86_virt_bits = 48; | |
6627d242 | 684 | #else |
d4387bd3 | 685 | c->x86_clflush_size = 32; |
13c6c532 JB |
686 | c->x86_phys_bits = 32; |
687 | c->x86_virt_bits = 32; | |
6627d242 | 688 | #endif |
0a488a53 | 689 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 690 | |
3da99c97 | 691 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 692 | c->extended_cpuid_level = 0; |
d7cd5611 | 693 | |
aef93c8b YL |
694 | if (!have_cpuid_p()) |
695 | identify_cpu_without_cpuid(c); | |
696 | ||
697 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
698 | if (!have_cpuid_p()) |
699 | return; | |
700 | ||
701 | cpu_detect(c); | |
702 | ||
3da99c97 | 703 | get_cpu_vendor(c); |
2b16a235 | 704 | |
3da99c97 | 705 | get_cpu_cap(c); |
12cf105c | 706 | |
10a434fc YL |
707 | if (this_cpu->c_early_init) |
708 | this_cpu->c_early_init(c); | |
093af8d7 | 709 | |
f6e9456c | 710 | c->cpu_index = 0; |
b38b0665 | 711 | filter_cpuid_features(c, false); |
de5397ad FY |
712 | |
713 | setup_smep(c); | |
a110b5ec BP |
714 | |
715 | if (this_cpu->c_bsp_init) | |
716 | this_cpu->c_bsp_init(c); | |
d7cd5611 RR |
717 | } |
718 | ||
9d31d35b YL |
719 | void __init early_cpu_init(void) |
720 | { | |
02dde8b4 | 721 | const struct cpu_dev *const *cdev; |
10a434fc YL |
722 | int count = 0; |
723 | ||
ac23f253 | 724 | #ifdef CONFIG_PROCESSOR_SELECT |
9766cdbc | 725 | printk(KERN_INFO "KERNEL supported cpus:\n"); |
31c997ca IM |
726 | #endif |
727 | ||
10a434fc | 728 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 729 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 730 | |
10a434fc YL |
731 | if (count >= X86_VENDOR_NUM) |
732 | break; | |
733 | cpu_devs[count] = cpudev; | |
734 | count++; | |
735 | ||
ac23f253 | 736 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
737 | { |
738 | unsigned int j; | |
739 | ||
740 | for (j = 0; j < 2; j++) { | |
741 | if (!cpudev->c_ident[j]) | |
742 | continue; | |
743 | printk(KERN_INFO " %s %s\n", cpudev->c_vendor, | |
744 | cpudev->c_ident[j]); | |
745 | } | |
10a434fc | 746 | } |
0388423d | 747 | #endif |
10a434fc | 748 | } |
9d31d35b | 749 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 750 | } |
093af8d7 | 751 | |
b6734c35 | 752 | /* |
366d4a43 BP |
753 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; |
754 | * unfortunately, that's not true in practice because of early VIA | |
755 | * chips and (more importantly) broken virtualizers that are not easy | |
756 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
757 | * probing for it doesn't even work. Disable it completely on 32-bit | |
ba0593bf | 758 | * unless we can find a reliable way to detect all the broken cases. |
366d4a43 | 759 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). |
b6734c35 PA |
760 | */ |
761 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
762 | { | |
366d4a43 | 763 | #ifdef CONFIG_X86_32 |
b6734c35 | 764 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
366d4a43 BP |
765 | #else |
766 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
767 | #endif | |
d7cd5611 RR |
768 | } |
769 | ||
34048c9e | 770 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 771 | { |
aef93c8b | 772 | c->extended_cpuid_level = 0; |
1da177e4 | 773 | |
3da99c97 | 774 | if (!have_cpuid_p()) |
aef93c8b | 775 | identify_cpu_without_cpuid(c); |
1d67953f | 776 | |
aef93c8b | 777 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 778 | if (!have_cpuid_p()) |
aef93c8b | 779 | return; |
1da177e4 | 780 | |
3da99c97 | 781 | cpu_detect(c); |
1da177e4 | 782 | |
3da99c97 | 783 | get_cpu_vendor(c); |
1da177e4 | 784 | |
3da99c97 | 785 | get_cpu_cap(c); |
1da177e4 | 786 | |
3da99c97 YL |
787 | if (c->cpuid_level >= 0x00000001) { |
788 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
789 | #ifdef CONFIG_X86_32 |
790 | # ifdef CONFIG_X86_HT | |
cb8cc442 | 791 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 792 | # else |
3da99c97 | 793 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
794 | # endif |
795 | #endif | |
b89d3b3e | 796 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 797 | } |
1da177e4 | 798 | |
de5397ad FY |
799 | setup_smep(c); |
800 | ||
1b05d60d | 801 | get_model_name(c); /* Default name */ |
1da177e4 | 802 | |
3da99c97 | 803 | detect_nopl(c); |
1da177e4 | 804 | } |
1da177e4 LT |
805 | |
806 | /* | |
807 | * This does the hard work of actually picking apart the CPU stuff... | |
808 | */ | |
9a250347 | 809 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
810 | { |
811 | int i; | |
812 | ||
813 | c->loops_per_jiffy = loops_per_jiffy; | |
814 | c->x86_cache_size = -1; | |
815 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
816 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
817 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
818 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 819 | c->x86_max_cores = 1; |
102bbe3a | 820 | c->x86_coreid_bits = 0; |
11fdd252 | 821 | #ifdef CONFIG_X86_64 |
102bbe3a | 822 | c->x86_clflush_size = 64; |
13c6c532 JB |
823 | c->x86_phys_bits = 36; |
824 | c->x86_virt_bits = 48; | |
102bbe3a YL |
825 | #else |
826 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 827 | c->x86_clflush_size = 32; |
13c6c532 JB |
828 | c->x86_phys_bits = 32; |
829 | c->x86_virt_bits = 32; | |
102bbe3a YL |
830 | #endif |
831 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
832 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
833 | ||
1da177e4 LT |
834 | generic_identify(c); |
835 | ||
3898534d | 836 | if (this_cpu->c_identify) |
1da177e4 LT |
837 | this_cpu->c_identify(c); |
838 | ||
2759c328 YL |
839 | /* Clear/Set all flags overriden by options, after probe */ |
840 | for (i = 0; i < NCAPINTS; i++) { | |
841 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
842 | c->x86_capability[i] |= cpu_caps_set[i]; | |
843 | } | |
844 | ||
102bbe3a | 845 | #ifdef CONFIG_X86_64 |
cb8cc442 | 846 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
847 | #endif |
848 | ||
1da177e4 LT |
849 | /* |
850 | * Vendor-specific initialization. In this section we | |
851 | * canonicalize the feature flags, meaning if there are | |
852 | * features a certain CPU supports which CPUID doesn't | |
853 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
854 | * we handle them here. | |
855 | * | |
856 | * At the end of this section, c->x86_capability better | |
857 | * indicate the features this CPU genuinely supports! | |
858 | */ | |
859 | if (this_cpu->c_init) | |
860 | this_cpu->c_init(c); | |
861 | ||
862 | /* Disable the PN if appropriate */ | |
863 | squash_the_stupid_serial_number(c); | |
864 | ||
865 | /* | |
0f3fa48a IM |
866 | * The vendor-specific functions might have changed features. |
867 | * Now we do "generic changes." | |
1da177e4 LT |
868 | */ |
869 | ||
b38b0665 PA |
870 | /* Filter out anything that depends on CPUID levels we don't have */ |
871 | filter_cpuid_features(c, true); | |
872 | ||
1da177e4 | 873 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 874 | if (!c->x86_model_id[0]) { |
02dde8b4 | 875 | const char *p; |
1da177e4 | 876 | p = table_lookup_model(c); |
34048c9e | 877 | if (p) |
1da177e4 LT |
878 | strcpy(c->x86_model_id, p); |
879 | else | |
880 | /* Last resort... */ | |
881 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 882 | c->x86, c->x86_model); |
1da177e4 LT |
883 | } |
884 | ||
102bbe3a YL |
885 | #ifdef CONFIG_X86_64 |
886 | detect_ht(c); | |
887 | #endif | |
888 | ||
88b094fb | 889 | init_hypervisor(c); |
49d859d7 | 890 | x86_init_rdrand(c); |
3e0c3737 YL |
891 | |
892 | /* | |
893 | * Clear/Set all flags overriden by options, need do it | |
894 | * before following smp all cpus cap AND. | |
895 | */ | |
896 | for (i = 0; i < NCAPINTS; i++) { | |
897 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
898 | c->x86_capability[i] |= cpu_caps_set[i]; | |
899 | } | |
900 | ||
1da177e4 LT |
901 | /* |
902 | * On SMP, boot_cpu_data holds the common feature set between | |
903 | * all CPUs; so make sure that we indicate which features are | |
904 | * common between the CPUs. The first time this routine gets | |
905 | * executed, c == &boot_cpu_data. | |
906 | */ | |
34048c9e | 907 | if (c != &boot_cpu_data) { |
1da177e4 | 908 | /* AND the already accumulated flags with these */ |
9d31d35b | 909 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
910 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
911 | } | |
912 | ||
913 | /* Init Machine Check Exception if available. */ | |
5e09954a | 914 | mcheck_cpu_init(c); |
30d432df AK |
915 | |
916 | select_idle_routine(c); | |
102bbe3a | 917 | |
de2d9445 | 918 | #ifdef CONFIG_NUMA |
102bbe3a YL |
919 | numa_add_cpu(smp_processor_id()); |
920 | #endif | |
a6c4e076 | 921 | } |
31ab269a | 922 | |
e04d645f GC |
923 | #ifdef CONFIG_X86_64 |
924 | static void vgetcpu_set_mode(void) | |
925 | { | |
926 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
927 | vgetcpu_mode = VGETCPU_RDTSCP; | |
928 | else | |
929 | vgetcpu_mode = VGETCPU_LSL; | |
930 | } | |
931 | #endif | |
932 | ||
a6c4e076 JF |
933 | void __init identify_boot_cpu(void) |
934 | { | |
935 | identify_cpu(&boot_cpu_data); | |
02c68a02 | 936 | init_amd_e400_c1e_mask(); |
102bbe3a | 937 | #ifdef CONFIG_X86_32 |
a6c4e076 | 938 | sysenter_setup(); |
6fe940d6 | 939 | enable_sep_cpu(); |
e04d645f GC |
940 | #else |
941 | vgetcpu_set_mode(); | |
102bbe3a | 942 | #endif |
e0ba94f1 AS |
943 | if (boot_cpu_data.cpuid_level >= 2) |
944 | cpu_detect_tlb(&boot_cpu_data); | |
a6c4e076 | 945 | } |
3b520b23 | 946 | |
a6c4e076 JF |
947 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
948 | { | |
949 | BUG_ON(c == &boot_cpu_data); | |
950 | identify_cpu(c); | |
102bbe3a | 951 | #ifdef CONFIG_X86_32 |
a6c4e076 | 952 | enable_sep_cpu(); |
102bbe3a | 953 | #endif |
a6c4e076 | 954 | mtrr_ap_init(); |
1da177e4 LT |
955 | } |
956 | ||
a0854a46 | 957 | struct msr_range { |
0f3fa48a IM |
958 | unsigned min; |
959 | unsigned max; | |
a0854a46 | 960 | }; |
1da177e4 | 961 | |
02dde8b4 | 962 | static const struct msr_range msr_range_array[] __cpuinitconst = { |
a0854a46 YL |
963 | { 0x00000000, 0x00000418}, |
964 | { 0xc0000000, 0xc000040b}, | |
965 | { 0xc0010000, 0xc0010142}, | |
966 | { 0xc0011000, 0xc001103b}, | |
967 | }; | |
1da177e4 | 968 | |
21c3fcf3 | 969 | static void __cpuinit __print_cpu_msr(void) |
a0854a46 | 970 | { |
0f3fa48a | 971 | unsigned index_min, index_max; |
a0854a46 YL |
972 | unsigned index; |
973 | u64 val; | |
974 | int i; | |
a0854a46 YL |
975 | |
976 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
977 | index_min = msr_range_array[i].min; | |
978 | index_max = msr_range_array[i].max; | |
0f3fa48a | 979 | |
a0854a46 | 980 | for (index = index_min; index < index_max; index++) { |
ecd431d9 | 981 | if (rdmsrl_safe(index, &val)) |
a0854a46 YL |
982 | continue; |
983 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 984 | } |
a0854a46 YL |
985 | } |
986 | } | |
94605eff | 987 | |
a0854a46 | 988 | static int show_msr __cpuinitdata; |
0f3fa48a | 989 | |
a0854a46 YL |
990 | static __init int setup_show_msr(char *arg) |
991 | { | |
992 | int num; | |
3dd9d514 | 993 | |
a0854a46 | 994 | get_option(&arg, &num); |
3dd9d514 | 995 | |
a0854a46 YL |
996 | if (num > 0) |
997 | show_msr = num; | |
998 | return 1; | |
1da177e4 | 999 | } |
a0854a46 | 1000 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 1001 | |
191679fd AK |
1002 | static __init int setup_noclflush(char *arg) |
1003 | { | |
1004 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
1005 | return 1; | |
1006 | } | |
1007 | __setup("noclflush", setup_noclflush); | |
1008 | ||
3bc9b76b | 1009 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1010 | { |
02dde8b4 | 1011 | const char *vendor = NULL; |
1da177e4 | 1012 | |
0f3fa48a | 1013 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1014 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1015 | } else { |
1016 | if (c->cpuid_level >= 0) | |
1017 | vendor = c->x86_vendor_id; | |
1018 | } | |
1da177e4 | 1019 | |
bd32a8cf | 1020 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 1021 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 1022 | |
9d31d35b YL |
1023 | if (c->x86_model_id[0]) |
1024 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 1025 | else |
9d31d35b | 1026 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 1027 | |
34048c9e | 1028 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 1029 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 1030 | else |
9d31d35b | 1031 | printk(KERN_CONT "\n"); |
a0854a46 | 1032 | |
0b8b8078 | 1033 | print_cpu_msr(c); |
21c3fcf3 YL |
1034 | } |
1035 | ||
1036 | void __cpuinit print_cpu_msr(struct cpuinfo_x86 *c) | |
1037 | { | |
a0854a46 | 1038 | if (c->cpu_index < show_msr) |
21c3fcf3 | 1039 | __print_cpu_msr(); |
1da177e4 LT |
1040 | } |
1041 | ||
ac72e788 AK |
1042 | static __init int setup_disablecpuid(char *arg) |
1043 | { | |
1044 | int bit; | |
0f3fa48a | 1045 | |
ac72e788 AK |
1046 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) |
1047 | setup_clear_cpu_cap(bit); | |
1048 | else | |
1049 | return 0; | |
0f3fa48a | 1050 | |
ac72e788 AK |
1051 | return 1; |
1052 | } | |
1053 | __setup("clearcpuid=", setup_disablecpuid); | |
1054 | ||
d5494d4f | 1055 | #ifdef CONFIG_X86_64 |
9ff80942 | 1056 | struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; |
228bdaa9 SR |
1057 | struct desc_ptr nmi_idt_descr = { NR_VECTORS * 16 - 1, |
1058 | (unsigned long) nmi_idt_table }; | |
d5494d4f | 1059 | |
947e76cd BG |
1060 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
1061 | irq_stack_union) __aligned(PAGE_SIZE); | |
0f3fa48a | 1062 | |
bdf977b3 TH |
1063 | /* |
1064 | * The following four percpu variables are hot. Align current_task to | |
1065 | * cacheline size such that all four fall in the same cacheline. | |
1066 | */ | |
1067 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1068 | &init_task; | |
1069 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1070 | |
9af45651 BG |
1071 | DEFINE_PER_CPU(unsigned long, kernel_stack) = |
1072 | (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; | |
1073 | EXPORT_PER_CPU_SYMBOL(kernel_stack); | |
1074 | ||
bdf977b3 TH |
1075 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
1076 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; | |
1077 | ||
56895530 | 1078 | DEFINE_PER_CPU(unsigned int, irq_count) = -1; |
d5494d4f | 1079 | |
7e16838d LT |
1080 | DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); |
1081 | ||
0f3fa48a IM |
1082 | /* |
1083 | * Special IST stacks which the CPU switches to when it calls | |
1084 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
1085 | * limit), all of them are 4K, except the debug stack which | |
1086 | * is 8K. | |
1087 | */ | |
1088 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
1089 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1090 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1091 | }; | |
1092 | ||
92d65b23 | 1093 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
3e352aa8 | 1094 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); |
d5494d4f | 1095 | |
d5494d4f YL |
1096 | /* May not be marked __init: used by software suspend */ |
1097 | void syscall_init(void) | |
1da177e4 | 1098 | { |
d5494d4f YL |
1099 | /* |
1100 | * LSTAR and STAR live in a bit strange symbiosis. | |
1101 | * They both write to the same internal register. STAR allows to | |
1102 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
1103 | */ | |
1104 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
1105 | wrmsrl(MSR_LSTAR, system_call); | |
1106 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 1107 | |
d5494d4f YL |
1108 | #ifdef CONFIG_IA32_EMULATION |
1109 | syscall32_cpu_init(); | |
1110 | #endif | |
03ae5768 | 1111 | |
d5494d4f YL |
1112 | /* Flags to clear on syscall */ |
1113 | wrmsrl(MSR_SYSCALL_MASK, | |
1114 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
1da177e4 | 1115 | } |
62111195 | 1116 | |
d5494d4f YL |
1117 | unsigned long kernel_eflags; |
1118 | ||
1119 | /* | |
1120 | * Copies of the original ist values from the tss are only accessed during | |
1121 | * debugging, no special alignment required. | |
1122 | */ | |
1123 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1124 | ||
228bdaa9 | 1125 | static DEFINE_PER_CPU(unsigned long, debug_stack_addr); |
42181186 | 1126 | DEFINE_PER_CPU(int, debug_stack_usage); |
228bdaa9 SR |
1127 | |
1128 | int is_debug_stack(unsigned long addr) | |
1129 | { | |
42181186 SR |
1130 | return __get_cpu_var(debug_stack_usage) || |
1131 | (addr <= __get_cpu_var(debug_stack_addr) && | |
1132 | addr > (__get_cpu_var(debug_stack_addr) - DEBUG_STKSZ)); | |
228bdaa9 SR |
1133 | } |
1134 | ||
f8988175 SR |
1135 | static DEFINE_PER_CPU(u32, debug_stack_use_ctr); |
1136 | ||
228bdaa9 SR |
1137 | void debug_stack_set_zero(void) |
1138 | { | |
f8988175 | 1139 | this_cpu_inc(debug_stack_use_ctr); |
228bdaa9 SR |
1140 | load_idt((const struct desc_ptr *)&nmi_idt_descr); |
1141 | } | |
1142 | ||
1143 | void debug_stack_reset(void) | |
1144 | { | |
f8988175 SR |
1145 | if (WARN_ON(!this_cpu_read(debug_stack_use_ctr))) |
1146 | return; | |
1147 | if (this_cpu_dec_return(debug_stack_use_ctr) == 0) | |
1148 | load_idt((const struct desc_ptr *)&idt_descr); | |
228bdaa9 SR |
1149 | } |
1150 | ||
0f3fa48a | 1151 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1152 | |
bdf977b3 TH |
1153 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1154 | EXPORT_PER_CPU_SYMBOL(current_task); | |
27e74da9 | 1155 | DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); |
bdf977b3 | 1156 | |
60a5317f | 1157 | #ifdef CONFIG_CC_STACKPROTECTOR |
53f82452 | 1158 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1159 | #endif |
d5494d4f | 1160 | |
60a5317f | 1161 | /* Make sure %fs and %gs are initialized properly in idle threads */ |
6b2fb3c6 | 1162 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
1163 | { |
1164 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 1165 | regs->fs = __KERNEL_PERCPU; |
60a5317f | 1166 | regs->gs = __KERNEL_STACK_CANARY; |
0f3fa48a | 1167 | |
f95d47ca JF |
1168 | return regs; |
1169 | } | |
0f3fa48a | 1170 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1171 | |
9766cdbc JSR |
1172 | /* |
1173 | * Clear all 6 debug registers: | |
1174 | */ | |
1175 | static void clear_all_debug_regs(void) | |
1176 | { | |
1177 | int i; | |
1178 | ||
1179 | for (i = 0; i < 8; i++) { | |
1180 | /* Ignore db4, db5 */ | |
1181 | if ((i == 4) || (i == 5)) | |
1182 | continue; | |
1183 | ||
1184 | set_debugreg(0, i); | |
1185 | } | |
1186 | } | |
c5413fbe | 1187 | |
0bb9fef9 JW |
1188 | #ifdef CONFIG_KGDB |
1189 | /* | |
1190 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1191 | * connection established. | |
1192 | */ | |
1193 | static void dbg_restore_debug_regs(void) | |
1194 | { | |
1195 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1196 | arch_kgdb_ops.correct_hw_break(); | |
1197 | } | |
1198 | #else /* ! CONFIG_KGDB */ | |
1199 | #define dbg_restore_debug_regs() | |
1200 | #endif /* ! CONFIG_KGDB */ | |
1201 | ||
d2cbcc49 RR |
1202 | /* |
1203 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1204 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1205 | * and IDT. We reload them nevertheless, this function acts as a | |
1206 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1207 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1208 | */ |
1ba76586 | 1209 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1210 | |
1ba76586 YL |
1211 | void __cpuinit cpu_init(void) |
1212 | { | |
0fe1e009 | 1213 | struct orig_ist *oist; |
1ba76586 | 1214 | struct task_struct *me; |
0f3fa48a IM |
1215 | struct tss_struct *t; |
1216 | unsigned long v; | |
1217 | int cpu; | |
1ba76586 YL |
1218 | int i; |
1219 | ||
0f3fa48a IM |
1220 | cpu = stack_smp_processor_id(); |
1221 | t = &per_cpu(init_tss, cpu); | |
0fe1e009 | 1222 | oist = &per_cpu(orig_ist, cpu); |
0f3fa48a | 1223 | |
e7a22c1e | 1224 | #ifdef CONFIG_NUMA |
c6ae41e7 | 1225 | if (cpu != 0 && this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
1226 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
1227 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1228 | #endif |
1ba76586 YL |
1229 | |
1230 | me = current; | |
1231 | ||
c2d1cec1 | 1232 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) |
1ba76586 YL |
1233 | panic("CPU#%d already initialized!\n", cpu); |
1234 | ||
2eaad1fd | 1235 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 YL |
1236 | |
1237 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1238 | ||
1239 | /* | |
1240 | * Initialize the per-CPU GDT with the boot GDT, | |
1241 | * and set up the GDT descriptor: | |
1242 | */ | |
1243 | ||
552be871 | 1244 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1245 | loadsegment(fs, 0); |
1246 | ||
1ba76586 YL |
1247 | load_idt((const struct desc_ptr *)&idt_descr); |
1248 | ||
1249 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1250 | syscall_init(); | |
1251 | ||
1252 | wrmsrl(MSR_FS_BASE, 0); | |
1253 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1254 | barrier(); | |
1255 | ||
4763ed4d | 1256 | x86_configure_nx(); |
06cd9a7d | 1257 | if (cpu != 0) |
1ba76586 YL |
1258 | enable_x2apic(); |
1259 | ||
1260 | /* | |
1261 | * set up and load the per-CPU TSS | |
1262 | */ | |
0fe1e009 | 1263 | if (!oist->ist[0]) { |
92d65b23 | 1264 | char *estacks = per_cpu(exception_stacks, cpu); |
0f3fa48a | 1265 | |
1ba76586 | 1266 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
0f3fa48a | 1267 | estacks += exception_stack_sizes[v]; |
0fe1e009 | 1268 | oist->ist[v] = t->x86_tss.ist[v] = |
1ba76586 | 1269 | (unsigned long)estacks; |
228bdaa9 SR |
1270 | if (v == DEBUG_STACK-1) |
1271 | per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; | |
1ba76586 YL |
1272 | } |
1273 | } | |
1274 | ||
1275 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
0f3fa48a | 1276 | |
1ba76586 YL |
1277 | /* |
1278 | * <= is required because the CPU will access up to | |
1279 | * 8 bits beyond the end of the IO permission bitmap. | |
1280 | */ | |
1281 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1282 | t->io_bitmap[i] = ~0UL; | |
1283 | ||
1284 | atomic_inc(&init_mm.mm_count); | |
1285 | me->active_mm = &init_mm; | |
8c5dfd25 | 1286 | BUG_ON(me->mm); |
1ba76586 YL |
1287 | enter_lazy_tlb(&init_mm, me); |
1288 | ||
1289 | load_sp0(t, ¤t->thread); | |
1290 | set_tss_desc(cpu, t); | |
1291 | load_TR_desc(); | |
1292 | load_LDT(&init_mm.context); | |
1293 | ||
0bb9fef9 JW |
1294 | clear_all_debug_regs(); |
1295 | dbg_restore_debug_regs(); | |
1ba76586 YL |
1296 | |
1297 | fpu_init(); | |
0e49bf66 | 1298 | xsave_init(); |
1ba76586 YL |
1299 | |
1300 | raw_local_save_flags(kernel_eflags); | |
1301 | ||
1302 | if (is_uv_system()) | |
1303 | uv_cpu_init(); | |
1304 | } | |
1305 | ||
1306 | #else | |
1307 | ||
d2cbcc49 | 1308 | void __cpuinit cpu_init(void) |
9ee79a3d | 1309 | { |
d2cbcc49 RR |
1310 | int cpu = smp_processor_id(); |
1311 | struct task_struct *curr = current; | |
34048c9e | 1312 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1313 | struct thread_struct *thread = &curr->thread; |
62111195 | 1314 | |
c2d1cec1 | 1315 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { |
62111195 | 1316 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); |
9766cdbc JSR |
1317 | for (;;) |
1318 | local_irq_enable(); | |
62111195 JF |
1319 | } |
1320 | ||
1321 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1322 | ||
1323 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1324 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1325 | |
4d37e7e3 | 1326 | load_idt(&idt_descr); |
552be871 | 1327 | switch_to_new_gdt(cpu); |
1da177e4 | 1328 | |
1da177e4 LT |
1329 | /* |
1330 | * Set up and load the per-CPU TSS and LDT | |
1331 | */ | |
1332 | atomic_inc(&init_mm.mm_count); | |
62111195 | 1333 | curr->active_mm = &init_mm; |
8c5dfd25 | 1334 | BUG_ON(curr->mm); |
62111195 | 1335 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1336 | |
faca6227 | 1337 | load_sp0(t, thread); |
34048c9e | 1338 | set_tss_desc(cpu, t); |
1da177e4 LT |
1339 | load_TR_desc(); |
1340 | load_LDT(&init_mm.context); | |
1341 | ||
f9a196b8 TG |
1342 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); |
1343 | ||
22c4e308 | 1344 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1345 | /* Set up doublefault TSS pointer in the GDT */ |
1346 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1347 | #endif |
1da177e4 | 1348 | |
9766cdbc | 1349 | clear_all_debug_regs(); |
0bb9fef9 | 1350 | dbg_restore_debug_regs(); |
1da177e4 | 1351 | |
0e49bf66 | 1352 | fpu_init(); |
dc1e35c6 | 1353 | xsave_init(); |
1da177e4 | 1354 | } |
1ba76586 | 1355 | #endif |