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Commit | Line | Data |
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1da177e4 | 1 | #include <linux/init.h> |
f0fc4aff YL |
2 | #include <linux/kernel.h> |
3 | #include <linux/sched.h> | |
1da177e4 | 4 | #include <linux/string.h> |
f0fc4aff YL |
5 | #include <linux/bootmem.h> |
6 | #include <linux/bitops.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/kgdb.h> | |
9 | #include <linux/topology.h> | |
1da177e4 LT |
10 | #include <linux/delay.h> |
11 | #include <linux/smp.h> | |
1da177e4 | 12 | #include <linux/percpu.h> |
1da177e4 LT |
13 | #include <asm/i387.h> |
14 | #include <asm/msr.h> | |
15 | #include <asm/io.h> | |
f0fc4aff | 16 | #include <asm/linkage.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
27b07da7 | 18 | #include <asm/mtrr.h> |
a03a3e28 | 19 | #include <asm/mce.h> |
8d4a4300 | 20 | #include <asm/pat.h> |
b6734c35 | 21 | #include <asm/asm.h> |
f0fc4aff | 22 | #include <asm/numa.h> |
b342797c | 23 | #include <asm/smp.h> |
f472cdba | 24 | #include <asm/cpu.h> |
06879033 | 25 | #include <asm/cpumask.h> |
1da177e4 LT |
26 | #ifdef CONFIG_X86_LOCAL_APIC |
27 | #include <asm/mpspec.h> | |
28 | #include <asm/apic.h> | |
29 | #include <mach_apic.h> | |
f0fc4aff | 30 | #include <asm/genapic.h> |
bdbcdd48 | 31 | #include <asm/uv/uv.h> |
1da177e4 LT |
32 | #endif |
33 | ||
f0fc4aff YL |
34 | #include <asm/pgtable.h> |
35 | #include <asm/processor.h> | |
36 | #include <asm/desc.h> | |
37 | #include <asm/atomic.h> | |
38 | #include <asm/proto.h> | |
39 | #include <asm/sections.h> | |
40 | #include <asm/setup.h> | |
88b094fb | 41 | #include <asm/hypervisor.h> |
f0fc4aff | 42 | |
1da177e4 LT |
43 | #include "cpu.h" |
44 | ||
c2d1cec1 MT |
45 | #ifdef CONFIG_X86_64 |
46 | ||
47 | /* all of these masks are initialized in setup_cpu_local_masks() */ | |
48 | cpumask_var_t cpu_callin_mask; | |
49 | cpumask_var_t cpu_callout_mask; | |
50 | cpumask_var_t cpu_initialized_mask; | |
51 | ||
52 | /* representing cpus for which sibling maps can be computed */ | |
53 | cpumask_var_t cpu_sibling_setup_mask; | |
54 | ||
2f2f52ba | 55 | /* correctly size the local cpu masks */ |
4369f1fb | 56 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
57 | { |
58 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
59 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
60 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
61 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
62 | } | |
63 | ||
c2d1cec1 MT |
64 | #else /* CONFIG_X86_32 */ |
65 | ||
66 | cpumask_t cpu_callin_map; | |
67 | cpumask_t cpu_callout_map; | |
68 | cpumask_t cpu_initialized; | |
69 | cpumask_t cpu_sibling_setup_map; | |
70 | ||
71 | #endif /* CONFIG_X86_32 */ | |
72 | ||
73 | ||
0a488a53 YL |
74 | static struct cpu_dev *this_cpu __cpuinitdata; |
75 | ||
06deef89 | 76 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 77 | #ifdef CONFIG_X86_64 |
06deef89 BG |
78 | /* |
79 | * We need valid kernel segments for data and code in long mode too | |
80 | * IRET will check the segment types kkeil 2000/10/28 | |
81 | * Also sysret mandates a special GDT layout | |
82 | * | |
83 | * The TLS descriptors are currently at a different place compared to i386. | |
84 | * Hopefully nobody expects them at a fixed place (Wine?) | |
85 | */ | |
950ad7ff YL |
86 | [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, |
87 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, | |
88 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, | |
89 | [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, | |
90 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, | |
91 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, | |
950ad7ff | 92 | #else |
6842ef0e GOC |
93 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
94 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
95 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
96 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
97 | /* |
98 | * Segments used for calling PnP BIOS have byte granularity. | |
99 | * They code segments and data segments have fixed 64k limits, | |
100 | * the transfer segment sizes are set at run time. | |
101 | */ | |
6842ef0e GOC |
102 | /* 32-bit code */ |
103 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
104 | /* 16-bit code */ | |
105 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
106 | /* 16-bit data */ | |
107 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
108 | /* 16-bit data */ | |
109 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
110 | /* 16-bit data */ | |
111 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
bf504672 RR |
112 | /* |
113 | * The APM segments have byte granularity and their bases | |
114 | * are set at run time. All have 64k limits. | |
115 | */ | |
6842ef0e GOC |
116 | /* 32-bit code */ |
117 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
bf504672 | 118 | /* 16-bit code */ |
6842ef0e GOC |
119 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
120 | /* data */ | |
121 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
bf504672 | 122 | |
6842ef0e | 123 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
0dd76d73 | 124 | [GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } }, |
950ad7ff | 125 | #endif |
06deef89 | 126 | } }; |
7a61d35d | 127 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 128 | |
ba51dced | 129 | #ifdef CONFIG_X86_32 |
3bc9b76b | 130 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 131 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 132 | |
0a488a53 YL |
133 | static int __init cachesize_setup(char *str) |
134 | { | |
135 | get_option(&str, &cachesize_override); | |
136 | return 1; | |
137 | } | |
138 | __setup("cachesize=", cachesize_setup); | |
139 | ||
0a488a53 YL |
140 | static int __init x86_fxsr_setup(char *s) |
141 | { | |
142 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
143 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
144 | return 1; | |
145 | } | |
146 | __setup("nofxsr", x86_fxsr_setup); | |
147 | ||
148 | static int __init x86_sep_setup(char *s) | |
149 | { | |
150 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
151 | return 1; | |
152 | } | |
153 | __setup("nosep", x86_sep_setup); | |
154 | ||
155 | /* Standard macro to see if a specific flag is changeable */ | |
156 | static inline int flag_is_changeable_p(u32 flag) | |
157 | { | |
158 | u32 f1, f2; | |
159 | ||
94f6bac1 KH |
160 | /* |
161 | * Cyrix and IDT cpus allow disabling of CPUID | |
162 | * so the code below may return different results | |
163 | * when it is executed before and after enabling | |
164 | * the CPUID. Add "volatile" to not allow gcc to | |
165 | * optimize the subsequent calls to this function. | |
166 | */ | |
167 | asm volatile ("pushfl\n\t" | |
168 | "pushfl\n\t" | |
169 | "popl %0\n\t" | |
170 | "movl %0,%1\n\t" | |
171 | "xorl %2,%0\n\t" | |
172 | "pushl %0\n\t" | |
173 | "popfl\n\t" | |
174 | "pushfl\n\t" | |
175 | "popl %0\n\t" | |
176 | "popfl\n\t" | |
177 | : "=&r" (f1), "=&r" (f2) | |
178 | : "ir" (flag)); | |
0a488a53 YL |
179 | |
180 | return ((f1^f2) & flag) != 0; | |
181 | } | |
182 | ||
183 | /* Probe for the CPUID instruction */ | |
184 | static int __cpuinit have_cpuid_p(void) | |
185 | { | |
186 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
187 | } | |
188 | ||
189 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
190 | { | |
191 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { | |
192 | /* Disable processor serial number */ | |
193 | unsigned long lo, hi; | |
194 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
195 | lo |= 0x200000; | |
196 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
197 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
198 | clear_cpu_cap(c, X86_FEATURE_PN); | |
199 | ||
200 | /* Disabling the serial number may affect the cpuid level */ | |
201 | c->cpuid_level = cpuid_eax(0); | |
202 | } | |
203 | } | |
204 | ||
205 | static int __init x86_serial_nr_setup(char *s) | |
206 | { | |
207 | disable_x86_serial_nr = 0; | |
208 | return 1; | |
209 | } | |
210 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 211 | #else |
102bbe3a YL |
212 | static inline int flag_is_changeable_p(u32 flag) |
213 | { | |
214 | return 1; | |
215 | } | |
ba51dced YL |
216 | /* Probe for the CPUID instruction */ |
217 | static inline int have_cpuid_p(void) | |
218 | { | |
219 | return 1; | |
220 | } | |
102bbe3a YL |
221 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
222 | { | |
223 | } | |
ba51dced | 224 | #endif |
0a488a53 | 225 | |
102bbe3a YL |
226 | /* |
227 | * Naming convention should be: <Name> [(<Codename>)] | |
228 | * This table only is used unless init_<vendor>() below doesn't set it; | |
229 | * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used | |
230 | * | |
231 | */ | |
232 | ||
233 | /* Look up CPU names by table lookup. */ | |
234 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) | |
235 | { | |
236 | struct cpu_model_info *info; | |
237 | ||
238 | if (c->x86_model >= 16) | |
239 | return NULL; /* Range check */ | |
240 | ||
241 | if (!this_cpu) | |
242 | return NULL; | |
243 | ||
244 | info = this_cpu->c_models; | |
245 | ||
246 | while (info && info->family) { | |
247 | if (info->family == c->x86) | |
248 | return info->model_names[c->x86_model]; | |
249 | info++; | |
250 | } | |
251 | return NULL; /* Not found */ | |
252 | } | |
253 | ||
7d851c8d AK |
254 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
255 | ||
11e3a840 JF |
256 | void load_percpu_segment(int cpu) |
257 | { | |
258 | #ifdef CONFIG_X86_32 | |
259 | loadsegment(fs, __KERNEL_PERCPU); | |
260 | #else | |
261 | loadsegment(gs, 0); | |
262 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
263 | #endif | |
264 | } | |
265 | ||
9d31d35b YL |
266 | /* Current gdt points %fs at the "master" per-cpu area: after this, |
267 | * it's on the real one. */ | |
552be871 | 268 | void switch_to_new_gdt(int cpu) |
9d31d35b YL |
269 | { |
270 | struct desc_ptr gdt_descr; | |
271 | ||
2697fbd5 | 272 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
273 | gdt_descr.size = GDT_SIZE - 1; |
274 | load_gdt(&gdt_descr); | |
2697fbd5 | 275 | /* Reload the per-cpu base */ |
11e3a840 JF |
276 | |
277 | load_percpu_segment(cpu); | |
9d31d35b YL |
278 | } |
279 | ||
10a434fc | 280 | static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 281 | |
34048c9e | 282 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
1da177e4 | 283 | { |
b9e67f00 YL |
284 | #ifdef CONFIG_X86_64 |
285 | display_cacheinfo(c); | |
286 | #else | |
1da177e4 LT |
287 | /* Not much we can do here... */ |
288 | /* Check if at least it has cpuid */ | |
289 | if (c->cpuid_level == -1) { | |
290 | /* No cpuid. It must be an ancient CPU */ | |
291 | if (c->x86 == 4) | |
292 | strcpy(c->x86_model_id, "486"); | |
293 | else if (c->x86 == 3) | |
294 | strcpy(c->x86_model_id, "386"); | |
295 | } | |
b9e67f00 | 296 | #endif |
1da177e4 LT |
297 | } |
298 | ||
95414930 | 299 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 300 | .c_init = default_init, |
fe38d855 | 301 | .c_vendor = "Unknown", |
10a434fc | 302 | .c_x86_vendor = X86_VENDOR_UNKNOWN, |
1da177e4 | 303 | }; |
1da177e4 | 304 | |
1b05d60d | 305 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
306 | { |
307 | unsigned int *v; | |
308 | char *p, *q; | |
309 | ||
3da99c97 | 310 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 311 | return; |
1da177e4 LT |
312 | |
313 | v = (unsigned int *) c->x86_model_id; | |
314 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
315 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
316 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
317 | c->x86_model_id[48] = 0; | |
318 | ||
319 | /* Intel chips right-justify this string for some dumb reason; | |
320 | undo that brain damage */ | |
321 | p = q = &c->x86_model_id[0]; | |
34048c9e | 322 | while (*p == ' ') |
1da177e4 | 323 | p++; |
34048c9e PC |
324 | if (p != q) { |
325 | while (*p) | |
1da177e4 | 326 | *q++ = *p++; |
34048c9e | 327 | while (q <= &c->x86_model_id[48]) |
1da177e4 LT |
328 | *q++ = '\0'; /* Zero-pad the rest */ |
329 | } | |
1da177e4 LT |
330 | } |
331 | ||
3bc9b76b | 332 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 | 333 | { |
9d31d35b | 334 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 335 | |
3da99c97 | 336 | n = c->extended_cpuid_level; |
1da177e4 LT |
337 | |
338 | if (n >= 0x80000005) { | |
9d31d35b | 339 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 340 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
9d31d35b YL |
341 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); |
342 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
140fc727 YL |
343 | #ifdef CONFIG_X86_64 |
344 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
345 | c->x86_tlbsize = 0; | |
346 | #endif | |
1da177e4 LT |
347 | } |
348 | ||
349 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
350 | return; | |
351 | ||
0a488a53 | 352 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 353 | l2size = ecx >> 16; |
34048c9e | 354 | |
140fc727 YL |
355 | #ifdef CONFIG_X86_64 |
356 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
357 | #else | |
1da177e4 LT |
358 | /* do processor-specific cache resizing */ |
359 | if (this_cpu->c_size_cache) | |
34048c9e | 360 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
361 | |
362 | /* Allow user to override all this if necessary. */ | |
363 | if (cachesize_override != -1) | |
364 | l2size = cachesize_override; | |
365 | ||
34048c9e | 366 | if (l2size == 0) |
1da177e4 | 367 | return; /* Again, no L2 cache is possible */ |
140fc727 | 368 | #endif |
1da177e4 LT |
369 | |
370 | c->x86_cache_size = l2size; | |
371 | ||
372 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
0a488a53 | 373 | l2size, ecx & 0xFF); |
1da177e4 LT |
374 | } |
375 | ||
9d31d35b | 376 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 377 | { |
97e4db7c | 378 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
379 | u32 eax, ebx, ecx, edx; |
380 | int index_msb, core_bits; | |
1da177e4 | 381 | |
0a488a53 | 382 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 383 | return; |
1da177e4 | 384 | |
0a488a53 YL |
385 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
386 | goto out; | |
1da177e4 | 387 | |
1cd78776 YL |
388 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
389 | return; | |
1da177e4 | 390 | |
0a488a53 | 391 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 392 | |
9d31d35b YL |
393 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
394 | ||
395 | if (smp_num_siblings == 1) { | |
396 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
397 | } else if (smp_num_siblings > 1) { | |
398 | ||
9628937d | 399 | if (smp_num_siblings > nr_cpu_ids) { |
9d31d35b YL |
400 | printk(KERN_WARNING "CPU: Unsupported number of siblings %d", |
401 | smp_num_siblings); | |
402 | smp_num_siblings = 1; | |
403 | return; | |
404 | } | |
405 | ||
406 | index_msb = get_count_order(smp_num_siblings); | |
1cd78776 YL |
407 | #ifdef CONFIG_X86_64 |
408 | c->phys_proc_id = phys_pkg_id(index_msb); | |
409 | #else | |
9d31d35b | 410 | c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb); |
1cd78776 | 411 | #endif |
9d31d35b YL |
412 | |
413 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
414 | ||
415 | index_msb = get_count_order(smp_num_siblings); | |
416 | ||
417 | core_bits = get_count_order(c->x86_max_cores); | |
418 | ||
1cd78776 YL |
419 | #ifdef CONFIG_X86_64 |
420 | c->cpu_core_id = phys_pkg_id(index_msb) & | |
421 | ((1 << core_bits) - 1); | |
422 | #else | |
9d31d35b YL |
423 | c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) & |
424 | ((1 << core_bits) - 1); | |
1cd78776 | 425 | #endif |
1da177e4 | 426 | } |
1da177e4 | 427 | |
0a488a53 YL |
428 | out: |
429 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
430 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
431 | c->phys_proc_id); | |
432 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
433 | c->cpu_core_id); | |
9d31d35b | 434 | } |
9d31d35b | 435 | #endif |
97e4db7c | 436 | } |
1da177e4 | 437 | |
3da99c97 | 438 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
439 | { |
440 | char *v = c->x86_vendor_id; | |
441 | int i; | |
fe38d855 | 442 | static int printed; |
1da177e4 LT |
443 | |
444 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
445 | if (!cpu_devs[i]) |
446 | break; | |
447 | ||
448 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
449 | (cpu_devs[i]->c_ident[1] && | |
450 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
451 | this_cpu = cpu_devs[i]; | |
452 | c->x86_vendor = this_cpu->c_x86_vendor; | |
453 | return; | |
1da177e4 LT |
454 | } |
455 | } | |
10a434fc | 456 | |
fe38d855 CE |
457 | if (!printed) { |
458 | printed++; | |
43603c8d | 459 | printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v); |
fe38d855 CE |
460 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); |
461 | } | |
10a434fc | 462 | |
fe38d855 CE |
463 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
464 | this_cpu = &default_cpu; | |
1da177e4 LT |
465 | } |
466 | ||
9d31d35b | 467 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 468 | { |
1da177e4 | 469 | /* Get vendor name */ |
4a148513 HH |
470 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
471 | (unsigned int *)&c->x86_vendor_id[0], | |
472 | (unsigned int *)&c->x86_vendor_id[8], | |
473 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 474 | |
1da177e4 | 475 | c->x86 = 4; |
9d31d35b | 476 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
477 | if (c->cpuid_level >= 0x00000001) { |
478 | u32 junk, tfms, cap0, misc; | |
479 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
9d31d35b YL |
480 | c->x86 = (tfms >> 8) & 0xf; |
481 | c->x86_model = (tfms >> 4) & 0xf; | |
482 | c->x86_mask = tfms & 0xf; | |
f5f786d0 | 483 | if (c->x86 == 0xf) |
1da177e4 | 484 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 485 | if (c->x86 >= 0x6) |
9d31d35b | 486 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
d4387bd3 | 487 | if (cap0 & (1<<19)) { |
d4387bd3 | 488 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 489 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 490 | } |
1da177e4 | 491 | } |
1da177e4 | 492 | } |
3da99c97 YL |
493 | |
494 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
093af8d7 YL |
495 | { |
496 | u32 tfms, xlvl; | |
3da99c97 | 497 | u32 ebx; |
093af8d7 | 498 | |
3da99c97 YL |
499 | /* Intel-defined flags: level 0x00000001 */ |
500 | if (c->cpuid_level >= 0x00000001) { | |
501 | u32 capability, excap; | |
502 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
503 | c->x86_capability[0] = capability; | |
504 | c->x86_capability[4] = excap; | |
505 | } | |
093af8d7 | 506 | |
3da99c97 YL |
507 | /* AMD-defined flags: level 0x80000001 */ |
508 | xlvl = cpuid_eax(0x80000000); | |
509 | c->extended_cpuid_level = xlvl; | |
510 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
511 | if (xlvl >= 0x80000001) { | |
512 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
513 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 514 | } |
093af8d7 | 515 | } |
093af8d7 | 516 | |
5122c890 | 517 | #ifdef CONFIG_X86_64 |
5122c890 YL |
518 | if (c->extended_cpuid_level >= 0x80000008) { |
519 | u32 eax = cpuid_eax(0x80000008); | |
520 | ||
521 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
522 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 523 | } |
5122c890 | 524 | #endif |
e3224234 YL |
525 | |
526 | if (c->extended_cpuid_level >= 0x80000007) | |
527 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 YL |
528 | |
529 | } | |
1da177e4 | 530 | |
aef93c8b YL |
531 | static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
532 | { | |
533 | #ifdef CONFIG_X86_32 | |
534 | int i; | |
535 | ||
536 | /* | |
537 | * First of all, decide if this is a 486 or higher | |
538 | * It's a 486 if we can modify the AC flag | |
539 | */ | |
540 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
541 | c->x86 = 4; | |
542 | else | |
543 | c->x86 = 3; | |
544 | ||
545 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
546 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
547 | c->x86_vendor_id[0] = 0; | |
548 | cpu_devs[i]->c_identify(c); | |
549 | if (c->x86_vendor_id[0]) { | |
550 | get_cpu_vendor(c); | |
551 | break; | |
552 | } | |
553 | } | |
554 | #endif | |
555 | } | |
556 | ||
34048c9e PC |
557 | /* |
558 | * Do minimum CPU detection early. | |
559 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
560 | * cache alignment. | |
561 | * The others are not touched to avoid unwanted side effects. | |
562 | * | |
563 | * WARNING: this function is only called on the BP. Don't add code here | |
564 | * that is supposed to run on all CPUs. | |
565 | */ | |
3da99c97 | 566 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 567 | { |
6627d242 YL |
568 | #ifdef CONFIG_X86_64 |
569 | c->x86_clflush_size = 64; | |
570 | #else | |
d4387bd3 | 571 | c->x86_clflush_size = 32; |
6627d242 | 572 | #endif |
0a488a53 | 573 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 574 | |
3da99c97 | 575 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 576 | c->extended_cpuid_level = 0; |
d7cd5611 | 577 | |
aef93c8b YL |
578 | if (!have_cpuid_p()) |
579 | identify_cpu_without_cpuid(c); | |
580 | ||
581 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
582 | if (!have_cpuid_p()) |
583 | return; | |
584 | ||
585 | cpu_detect(c); | |
586 | ||
3da99c97 | 587 | get_cpu_vendor(c); |
2b16a235 | 588 | |
3da99c97 | 589 | get_cpu_cap(c); |
12cf105c | 590 | |
10a434fc YL |
591 | if (this_cpu->c_early_init) |
592 | this_cpu->c_early_init(c); | |
093af8d7 | 593 | |
3da99c97 | 594 | validate_pat_support(c); |
bfcb4c1b | 595 | |
1c4acdb4 | 596 | #ifdef CONFIG_SMP |
bfcb4c1b | 597 | c->cpu_index = boot_cpu_id; |
1c4acdb4 | 598 | #endif |
d7cd5611 RR |
599 | } |
600 | ||
9d31d35b YL |
601 | void __init early_cpu_init(void) |
602 | { | |
10a434fc YL |
603 | struct cpu_dev **cdev; |
604 | int count = 0; | |
605 | ||
606 | printk("KERNEL supported cpus:\n"); | |
607 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { | |
608 | struct cpu_dev *cpudev = *cdev; | |
609 | unsigned int j; | |
9d31d35b | 610 | |
10a434fc YL |
611 | if (count >= X86_VENDOR_NUM) |
612 | break; | |
613 | cpu_devs[count] = cpudev; | |
614 | count++; | |
615 | ||
616 | for (j = 0; j < 2; j++) { | |
617 | if (!cpudev->c_ident[j]) | |
618 | continue; | |
619 | printk(" %s %s\n", cpudev->c_vendor, | |
620 | cpudev->c_ident[j]); | |
621 | } | |
622 | } | |
9d31d35b | 623 | |
9d31d35b | 624 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 625 | } |
093af8d7 | 626 | |
b6734c35 PA |
627 | /* |
628 | * The NOPL instruction is supposed to exist on all CPUs with | |
ba0593bf | 629 | * family >= 6; unfortunately, that's not true in practice because |
b6734c35 | 630 | * of early VIA chips and (more importantly) broken virtualizers that |
ba0593bf PA |
631 | * are not easy to detect. In the latter case it doesn't even *fail* |
632 | * reliably, so probing for it doesn't even work. Disable it completely | |
633 | * unless we can find a reliable way to detect all the broken cases. | |
b6734c35 PA |
634 | */ |
635 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
636 | { | |
b6734c35 | 637 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
d7cd5611 RR |
638 | } |
639 | ||
34048c9e | 640 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 641 | { |
aef93c8b | 642 | c->extended_cpuid_level = 0; |
1da177e4 | 643 | |
3da99c97 | 644 | if (!have_cpuid_p()) |
aef93c8b | 645 | identify_cpu_without_cpuid(c); |
1d67953f | 646 | |
aef93c8b | 647 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 648 | if (!have_cpuid_p()) |
aef93c8b | 649 | return; |
1da177e4 | 650 | |
3da99c97 | 651 | cpu_detect(c); |
1da177e4 | 652 | |
3da99c97 | 653 | get_cpu_vendor(c); |
1da177e4 | 654 | |
3da99c97 | 655 | get_cpu_cap(c); |
1da177e4 | 656 | |
3da99c97 YL |
657 | if (c->cpuid_level >= 0x00000001) { |
658 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
659 | #ifdef CONFIG_X86_32 |
660 | # ifdef CONFIG_X86_HT | |
3da99c97 | 661 | c->apicid = phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 662 | # else |
3da99c97 | 663 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
664 | # endif |
665 | #endif | |
1da177e4 | 666 | |
b89d3b3e YL |
667 | #ifdef CONFIG_X86_HT |
668 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 669 | #endif |
3da99c97 | 670 | } |
1da177e4 | 671 | |
1b05d60d | 672 | get_model_name(c); /* Default name */ |
1da177e4 | 673 | |
3da99c97 YL |
674 | init_scattered_cpuid_features(c); |
675 | detect_nopl(c); | |
1da177e4 | 676 | } |
1da177e4 LT |
677 | |
678 | /* | |
679 | * This does the hard work of actually picking apart the CPU stuff... | |
680 | */ | |
9a250347 | 681 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
682 | { |
683 | int i; | |
684 | ||
685 | c->loops_per_jiffy = loops_per_jiffy; | |
686 | c->x86_cache_size = -1; | |
687 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
688 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
689 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
690 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 691 | c->x86_max_cores = 1; |
102bbe3a | 692 | c->x86_coreid_bits = 0; |
11fdd252 | 693 | #ifdef CONFIG_X86_64 |
102bbe3a YL |
694 | c->x86_clflush_size = 64; |
695 | #else | |
696 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 697 | c->x86_clflush_size = 32; |
102bbe3a YL |
698 | #endif |
699 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
700 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
701 | ||
1da177e4 LT |
702 | generic_identify(c); |
703 | ||
3898534d | 704 | if (this_cpu->c_identify) |
1da177e4 LT |
705 | this_cpu->c_identify(c); |
706 | ||
102bbe3a YL |
707 | #ifdef CONFIG_X86_64 |
708 | c->apicid = phys_pkg_id(0); | |
709 | #endif | |
710 | ||
1da177e4 LT |
711 | /* |
712 | * Vendor-specific initialization. In this section we | |
713 | * canonicalize the feature flags, meaning if there are | |
714 | * features a certain CPU supports which CPUID doesn't | |
715 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
716 | * we handle them here. | |
717 | * | |
718 | * At the end of this section, c->x86_capability better | |
719 | * indicate the features this CPU genuinely supports! | |
720 | */ | |
721 | if (this_cpu->c_init) | |
722 | this_cpu->c_init(c); | |
723 | ||
724 | /* Disable the PN if appropriate */ | |
725 | squash_the_stupid_serial_number(c); | |
726 | ||
727 | /* | |
728 | * The vendor-specific functions might have changed features. Now | |
729 | * we do "generic changes." | |
730 | */ | |
731 | ||
1da177e4 | 732 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 733 | if (!c->x86_model_id[0]) { |
1da177e4 LT |
734 | char *p; |
735 | p = table_lookup_model(c); | |
34048c9e | 736 | if (p) |
1da177e4 LT |
737 | strcpy(c->x86_model_id, p); |
738 | else | |
739 | /* Last resort... */ | |
740 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 741 | c->x86, c->x86_model); |
1da177e4 LT |
742 | } |
743 | ||
102bbe3a YL |
744 | #ifdef CONFIG_X86_64 |
745 | detect_ht(c); | |
746 | #endif | |
747 | ||
88b094fb | 748 | init_hypervisor(c); |
1da177e4 LT |
749 | /* |
750 | * On SMP, boot_cpu_data holds the common feature set between | |
751 | * all CPUs; so make sure that we indicate which features are | |
752 | * common between the CPUs. The first time this routine gets | |
753 | * executed, c == &boot_cpu_data. | |
754 | */ | |
34048c9e | 755 | if (c != &boot_cpu_data) { |
1da177e4 | 756 | /* AND the already accumulated flags with these */ |
9d31d35b | 757 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
758 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
759 | } | |
760 | ||
7d851c8d AK |
761 | /* Clear all flags overriden by options */ |
762 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 763 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 764 | |
102bbe3a | 765 | #ifdef CONFIG_X86_MCE |
1da177e4 | 766 | /* Init Machine Check Exception if available. */ |
1da177e4 | 767 | mcheck_init(c); |
102bbe3a | 768 | #endif |
30d432df AK |
769 | |
770 | select_idle_routine(c); | |
102bbe3a YL |
771 | |
772 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
773 | numa_add_cpu(smp_processor_id()); | |
774 | #endif | |
a6c4e076 | 775 | } |
31ab269a | 776 | |
e04d645f GC |
777 | #ifdef CONFIG_X86_64 |
778 | static void vgetcpu_set_mode(void) | |
779 | { | |
780 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
781 | vgetcpu_mode = VGETCPU_RDTSCP; | |
782 | else | |
783 | vgetcpu_mode = VGETCPU_LSL; | |
784 | } | |
785 | #endif | |
786 | ||
a6c4e076 JF |
787 | void __init identify_boot_cpu(void) |
788 | { | |
789 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 790 | #ifdef CONFIG_X86_32 |
a6c4e076 | 791 | sysenter_setup(); |
6fe940d6 | 792 | enable_sep_cpu(); |
e04d645f GC |
793 | #else |
794 | vgetcpu_set_mode(); | |
102bbe3a | 795 | #endif |
a6c4e076 | 796 | } |
3b520b23 | 797 | |
a6c4e076 JF |
798 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
799 | { | |
800 | BUG_ON(c == &boot_cpu_data); | |
801 | identify_cpu(c); | |
102bbe3a | 802 | #ifdef CONFIG_X86_32 |
a6c4e076 | 803 | enable_sep_cpu(); |
102bbe3a | 804 | #endif |
a6c4e076 | 805 | mtrr_ap_init(); |
1da177e4 LT |
806 | } |
807 | ||
a0854a46 YL |
808 | struct msr_range { |
809 | unsigned min; | |
810 | unsigned max; | |
811 | }; | |
1da177e4 | 812 | |
a0854a46 YL |
813 | static struct msr_range msr_range_array[] __cpuinitdata = { |
814 | { 0x00000000, 0x00000418}, | |
815 | { 0xc0000000, 0xc000040b}, | |
816 | { 0xc0010000, 0xc0010142}, | |
817 | { 0xc0011000, 0xc001103b}, | |
818 | }; | |
1da177e4 | 819 | |
a0854a46 YL |
820 | static void __cpuinit print_cpu_msr(void) |
821 | { | |
822 | unsigned index; | |
823 | u64 val; | |
824 | int i; | |
825 | unsigned index_min, index_max; | |
826 | ||
827 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
828 | index_min = msr_range_array[i].min; | |
829 | index_max = msr_range_array[i].max; | |
830 | for (index = index_min; index < index_max; index++) { | |
831 | if (rdmsrl_amd_safe(index, &val)) | |
832 | continue; | |
833 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 834 | } |
a0854a46 YL |
835 | } |
836 | } | |
94605eff | 837 | |
a0854a46 YL |
838 | static int show_msr __cpuinitdata; |
839 | static __init int setup_show_msr(char *arg) | |
840 | { | |
841 | int num; | |
3dd9d514 | 842 | |
a0854a46 | 843 | get_option(&arg, &num); |
3dd9d514 | 844 | |
a0854a46 YL |
845 | if (num > 0) |
846 | show_msr = num; | |
847 | return 1; | |
1da177e4 | 848 | } |
a0854a46 | 849 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 850 | |
191679fd AK |
851 | static __init int setup_noclflush(char *arg) |
852 | { | |
853 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
854 | return 1; | |
855 | } | |
856 | __setup("noclflush", setup_noclflush); | |
857 | ||
3bc9b76b | 858 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
859 | { |
860 | char *vendor = NULL; | |
861 | ||
862 | if (c->x86_vendor < X86_VENDOR_NUM) | |
863 | vendor = this_cpu->c_vendor; | |
864 | else if (c->cpuid_level >= 0) | |
865 | vendor = c->x86_vendor_id; | |
866 | ||
bd32a8cf | 867 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 868 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 869 | |
9d31d35b YL |
870 | if (c->x86_model_id[0]) |
871 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 872 | else |
9d31d35b | 873 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 874 | |
34048c9e | 875 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 876 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 877 | else |
9d31d35b | 878 | printk(KERN_CONT "\n"); |
a0854a46 YL |
879 | |
880 | #ifdef CONFIG_SMP | |
881 | if (c->cpu_index < show_msr) | |
882 | print_cpu_msr(); | |
883 | #else | |
884 | if (show_msr) | |
885 | print_cpu_msr(); | |
886 | #endif | |
1da177e4 LT |
887 | } |
888 | ||
ac72e788 AK |
889 | static __init int setup_disablecpuid(char *arg) |
890 | { | |
891 | int bit; | |
892 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
893 | setup_clear_cpu_cap(bit); | |
894 | else | |
895 | return 0; | |
896 | return 1; | |
897 | } | |
898 | __setup("clearcpuid=", setup_disablecpuid); | |
899 | ||
d5494d4f | 900 | #ifdef CONFIG_X86_64 |
d5494d4f YL |
901 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; |
902 | ||
947e76cd BG |
903 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
904 | irq_stack_union) __aligned(PAGE_SIZE); | |
26f80bd6 BG |
905 | #ifdef CONFIG_SMP |
906 | DEFINE_PER_CPU(char *, irq_stack_ptr); /* will be set during per cpu init */ | |
907 | #else | |
908 | DEFINE_PER_CPU(char *, irq_stack_ptr) = | |
947e76cd | 909 | per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; |
26f80bd6 | 910 | #endif |
d5494d4f | 911 | |
9af45651 BG |
912 | DEFINE_PER_CPU(unsigned long, kernel_stack) = |
913 | (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; | |
914 | EXPORT_PER_CPU_SYMBOL(kernel_stack); | |
915 | ||
56895530 BG |
916 | DEFINE_PER_CPU(unsigned int, irq_count) = -1; |
917 | ||
92d65b23 BG |
918 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
919 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]) | |
920 | __aligned(PAGE_SIZE); | |
d5494d4f YL |
921 | |
922 | extern asmlinkage void ignore_sysret(void); | |
923 | ||
924 | /* May not be marked __init: used by software suspend */ | |
925 | void syscall_init(void) | |
1da177e4 | 926 | { |
d5494d4f YL |
927 | /* |
928 | * LSTAR and STAR live in a bit strange symbiosis. | |
929 | * They both write to the same internal register. STAR allows to | |
930 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
931 | */ | |
932 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
933 | wrmsrl(MSR_LSTAR, system_call); | |
934 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 935 | |
d5494d4f YL |
936 | #ifdef CONFIG_IA32_EMULATION |
937 | syscall32_cpu_init(); | |
938 | #endif | |
03ae5768 | 939 | |
d5494d4f YL |
940 | /* Flags to clear on syscall */ |
941 | wrmsrl(MSR_SYSCALL_MASK, | |
942 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
1da177e4 | 943 | } |
62111195 | 944 | |
d5494d4f YL |
945 | unsigned long kernel_eflags; |
946 | ||
947 | /* | |
948 | * Copies of the original ist values from the tss are only accessed during | |
949 | * debugging, no special alignment required. | |
950 | */ | |
951 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
952 | ||
953 | #else | |
954 | ||
7c3576d2 | 955 | /* Make sure %fs is initialized properly in idle threads */ |
6b2fb3c6 | 956 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
957 | { |
958 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 959 | regs->fs = __KERNEL_PERCPU; |
f95d47ca JF |
960 | return regs; |
961 | } | |
d5494d4f | 962 | #endif |
c5413fbe | 963 | |
d2cbcc49 RR |
964 | /* |
965 | * cpu_init() initializes state that is per-CPU. Some data is already | |
966 | * initialized (naturally) in the bootstrap process, such as the GDT | |
967 | * and IDT. We reload them nevertheless, this function acts as a | |
968 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 969 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 970 | */ |
1ba76586 YL |
971 | #ifdef CONFIG_X86_64 |
972 | void __cpuinit cpu_init(void) | |
973 | { | |
974 | int cpu = stack_smp_processor_id(); | |
975 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
976 | struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); | |
977 | unsigned long v; | |
1ba76586 YL |
978 | struct task_struct *me; |
979 | int i; | |
980 | ||
e7a22c1e BG |
981 | #ifdef CONFIG_NUMA |
982 | if (cpu != 0 && percpu_read(node_number) == 0 && | |
983 | cpu_to_node(cpu) != NUMA_NO_NODE) | |
984 | percpu_write(node_number, cpu_to_node(cpu)); | |
985 | #endif | |
986 | ||
1ba76586 YL |
987 | me = current; |
988 | ||
c2d1cec1 | 989 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) |
1ba76586 YL |
990 | panic("CPU#%d already initialized!\n", cpu); |
991 | ||
992 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
993 | ||
994 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
995 | ||
996 | /* | |
997 | * Initialize the per-CPU GDT with the boot GDT, | |
998 | * and set up the GDT descriptor: | |
999 | */ | |
1000 | ||
552be871 | 1001 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1002 | loadsegment(fs, 0); |
1003 | ||
1ba76586 YL |
1004 | load_idt((const struct desc_ptr *)&idt_descr); |
1005 | ||
1006 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1007 | syscall_init(); | |
1008 | ||
1009 | wrmsrl(MSR_FS_BASE, 0); | |
1010 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1011 | barrier(); | |
1012 | ||
1013 | check_efer(); | |
1014 | if (cpu != 0 && x2apic) | |
1015 | enable_x2apic(); | |
1016 | ||
1017 | /* | |
1018 | * set up and load the per-CPU TSS | |
1019 | */ | |
1020 | if (!orig_ist->ist[0]) { | |
92d65b23 BG |
1021 | static const unsigned int sizes[N_EXCEPTION_STACKS] = { |
1022 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1023 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1ba76586 | 1024 | }; |
92d65b23 | 1025 | char *estacks = per_cpu(exception_stacks, cpu); |
1ba76586 | 1026 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
92d65b23 | 1027 | estacks += sizes[v]; |
1ba76586 YL |
1028 | orig_ist->ist[v] = t->x86_tss.ist[v] = |
1029 | (unsigned long)estacks; | |
1030 | } | |
1031 | } | |
1032 | ||
1033 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
1034 | /* | |
1035 | * <= is required because the CPU will access up to | |
1036 | * 8 bits beyond the end of the IO permission bitmap. | |
1037 | */ | |
1038 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1039 | t->io_bitmap[i] = ~0UL; | |
1040 | ||
1041 | atomic_inc(&init_mm.mm_count); | |
1042 | me->active_mm = &init_mm; | |
1043 | if (me->mm) | |
1044 | BUG(); | |
1045 | enter_lazy_tlb(&init_mm, me); | |
1046 | ||
1047 | load_sp0(t, ¤t->thread); | |
1048 | set_tss_desc(cpu, t); | |
1049 | load_TR_desc(); | |
1050 | load_LDT(&init_mm.context); | |
1051 | ||
1052 | #ifdef CONFIG_KGDB | |
1053 | /* | |
1054 | * If the kgdb is connected no debug regs should be altered. This | |
1055 | * is only applicable when KGDB and a KGDB I/O module are built | |
1056 | * into the kernel and you are using early debugging with | |
1057 | * kgdbwait. KGDB will control the kernel HW breakpoint registers. | |
1058 | */ | |
1059 | if (kgdb_connected && arch_kgdb_ops.correct_hw_break) | |
1060 | arch_kgdb_ops.correct_hw_break(); | |
1061 | else { | |
1062 | #endif | |
1063 | /* | |
1064 | * Clear all 6 debug registers: | |
1065 | */ | |
1066 | ||
1067 | set_debugreg(0UL, 0); | |
1068 | set_debugreg(0UL, 1); | |
1069 | set_debugreg(0UL, 2); | |
1070 | set_debugreg(0UL, 3); | |
1071 | set_debugreg(0UL, 6); | |
1072 | set_debugreg(0UL, 7); | |
1073 | #ifdef CONFIG_KGDB | |
1074 | /* If the kgdb is connected no debug regs should be altered. */ | |
1075 | } | |
1076 | #endif | |
1077 | ||
1078 | fpu_init(); | |
1079 | ||
1080 | raw_local_save_flags(kernel_eflags); | |
1081 | ||
1082 | if (is_uv_system()) | |
1083 | uv_cpu_init(); | |
1084 | } | |
1085 | ||
1086 | #else | |
1087 | ||
d2cbcc49 | 1088 | void __cpuinit cpu_init(void) |
9ee79a3d | 1089 | { |
d2cbcc49 RR |
1090 | int cpu = smp_processor_id(); |
1091 | struct task_struct *curr = current; | |
34048c9e | 1092 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1093 | struct thread_struct *thread = &curr->thread; |
62111195 | 1094 | |
c2d1cec1 | 1095 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { |
62111195 JF |
1096 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); |
1097 | for (;;) local_irq_enable(); | |
1098 | } | |
1099 | ||
1100 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1101 | ||
1102 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1103 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1104 | |
4d37e7e3 | 1105 | load_idt(&idt_descr); |
552be871 | 1106 | switch_to_new_gdt(cpu); |
1da177e4 | 1107 | |
1da177e4 LT |
1108 | /* |
1109 | * Set up and load the per-CPU TSS and LDT | |
1110 | */ | |
1111 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
1112 | curr->active_mm = &init_mm; |
1113 | if (curr->mm) | |
1114 | BUG(); | |
1115 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 | 1116 | |
faca6227 | 1117 | load_sp0(t, thread); |
34048c9e | 1118 | set_tss_desc(cpu, t); |
1da177e4 LT |
1119 | load_TR_desc(); |
1120 | load_LDT(&init_mm.context); | |
1121 | ||
22c4e308 | 1122 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1123 | /* Set up doublefault TSS pointer in the GDT */ |
1124 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1125 | #endif |
1da177e4 | 1126 | |
464d1a78 JF |
1127 | /* Clear %gs. */ |
1128 | asm volatile ("mov %0, %%gs" : : "r" (0)); | |
1da177e4 LT |
1129 | |
1130 | /* Clear all 6 debug registers: */ | |
4bb0d3ec ZA |
1131 | set_debugreg(0, 0); |
1132 | set_debugreg(0, 1); | |
1133 | set_debugreg(0, 2); | |
1134 | set_debugreg(0, 3); | |
1135 | set_debugreg(0, 6); | |
1136 | set_debugreg(0, 7); | |
1da177e4 LT |
1137 | |
1138 | /* | |
1139 | * Force FPU initialization: | |
1140 | */ | |
b359e8a4 SS |
1141 | if (cpu_has_xsave) |
1142 | current_thread_info()->status = TS_XSAVE; | |
1143 | else | |
1144 | current_thread_info()->status = 0; | |
1da177e4 LT |
1145 | clear_used_math(); |
1146 | mxcsr_feature_mask_init(); | |
dc1e35c6 SS |
1147 | |
1148 | /* | |
1149 | * Boot processor to setup the FP and extended state context info. | |
1150 | */ | |
b3572e36 | 1151 | if (smp_processor_id() == boot_cpu_id) |
dc1e35c6 SS |
1152 | init_thread_xstate(); |
1153 | ||
1154 | xsave_init(); | |
1da177e4 | 1155 | } |
e1367daf | 1156 | |
1ba76586 YL |
1157 | |
1158 | #endif |