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1da177e4 | 1 | #include <linux/init.h> |
f0fc4aff YL |
2 | #include <linux/kernel.h> |
3 | #include <linux/sched.h> | |
1da177e4 | 4 | #include <linux/string.h> |
f0fc4aff YL |
5 | #include <linux/bootmem.h> |
6 | #include <linux/bitops.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/kgdb.h> | |
9 | #include <linux/topology.h> | |
1da177e4 LT |
10 | #include <linux/delay.h> |
11 | #include <linux/smp.h> | |
1da177e4 | 12 | #include <linux/percpu.h> |
1da177e4 LT |
13 | #include <asm/i387.h> |
14 | #include <asm/msr.h> | |
15 | #include <asm/io.h> | |
f0fc4aff | 16 | #include <asm/linkage.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
27b07da7 | 18 | #include <asm/mtrr.h> |
a03a3e28 | 19 | #include <asm/mce.h> |
8d4a4300 | 20 | #include <asm/pat.h> |
b6734c35 | 21 | #include <asm/asm.h> |
f0fc4aff | 22 | #include <asm/numa.h> |
b342797c | 23 | #include <asm/smp.h> |
f472cdba | 24 | #include <asm/cpu.h> |
1da177e4 LT |
25 | #ifdef CONFIG_X86_LOCAL_APIC |
26 | #include <asm/mpspec.h> | |
27 | #include <asm/apic.h> | |
28 | #include <mach_apic.h> | |
f0fc4aff | 29 | #include <asm/genapic.h> |
1da177e4 LT |
30 | #endif |
31 | ||
f0fc4aff YL |
32 | #include <asm/pda.h> |
33 | #include <asm/pgtable.h> | |
34 | #include <asm/processor.h> | |
35 | #include <asm/desc.h> | |
36 | #include <asm/atomic.h> | |
37 | #include <asm/proto.h> | |
38 | #include <asm/sections.h> | |
39 | #include <asm/setup.h> | |
88b094fb | 40 | #include <asm/hypervisor.h> |
f0fc4aff | 41 | |
1da177e4 LT |
42 | #include "cpu.h" |
43 | ||
c2d1cec1 MT |
44 | #ifdef CONFIG_X86_64 |
45 | ||
46 | /* all of these masks are initialized in setup_cpu_local_masks() */ | |
47 | cpumask_var_t cpu_callin_mask; | |
48 | cpumask_var_t cpu_callout_mask; | |
49 | cpumask_var_t cpu_initialized_mask; | |
50 | ||
51 | /* representing cpus for which sibling maps can be computed */ | |
52 | cpumask_var_t cpu_sibling_setup_mask; | |
53 | ||
54 | #else /* CONFIG_X86_32 */ | |
55 | ||
56 | cpumask_t cpu_callin_map; | |
57 | cpumask_t cpu_callout_map; | |
58 | cpumask_t cpu_initialized; | |
59 | cpumask_t cpu_sibling_setup_map; | |
60 | ||
61 | #endif /* CONFIG_X86_32 */ | |
62 | ||
63 | ||
0a488a53 YL |
64 | static struct cpu_dev *this_cpu __cpuinitdata; |
65 | ||
950ad7ff YL |
66 | #ifdef CONFIG_X86_64 |
67 | /* We need valid kernel segments for data and code in long mode too | |
68 | * IRET will check the segment types kkeil 2000/10/28 | |
69 | * Also sysret mandates a special GDT layout | |
70 | */ | |
71 | /* The TLS descriptors are currently at a different place compared to i386. | |
72 | Hopefully nobody expects them at a fixed place (Wine?) */ | |
7a61d35d | 73 | DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff YL |
74 | [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, |
75 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, | |
76 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, | |
77 | [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, | |
78 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, | |
79 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, | |
80 | } }; | |
81 | #else | |
63cc8c75 | 82 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
6842ef0e GOC |
83 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
84 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
85 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
86 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
87 | /* |
88 | * Segments used for calling PnP BIOS have byte granularity. | |
89 | * They code segments and data segments have fixed 64k limits, | |
90 | * the transfer segment sizes are set at run time. | |
91 | */ | |
6842ef0e GOC |
92 | /* 32-bit code */ |
93 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
94 | /* 16-bit code */ | |
95 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
96 | /* 16-bit data */ | |
97 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
98 | /* 16-bit data */ | |
99 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
100 | /* 16-bit data */ | |
101 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
bf504672 RR |
102 | /* |
103 | * The APM segments have byte granularity and their bases | |
104 | * are set at run time. All have 64k limits. | |
105 | */ | |
6842ef0e GOC |
106 | /* 32-bit code */ |
107 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
bf504672 | 108 | /* 16-bit code */ |
6842ef0e GOC |
109 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
110 | /* data */ | |
111 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
bf504672 | 112 | |
6842ef0e GOC |
113 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
114 | [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } }, | |
7a61d35d | 115 | } }; |
950ad7ff | 116 | #endif |
7a61d35d | 117 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 118 | |
ba51dced | 119 | #ifdef CONFIG_X86_32 |
3bc9b76b | 120 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 121 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 122 | |
0a488a53 YL |
123 | static int __init cachesize_setup(char *str) |
124 | { | |
125 | get_option(&str, &cachesize_override); | |
126 | return 1; | |
127 | } | |
128 | __setup("cachesize=", cachesize_setup); | |
129 | ||
0a488a53 YL |
130 | static int __init x86_fxsr_setup(char *s) |
131 | { | |
132 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
133 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
134 | return 1; | |
135 | } | |
136 | __setup("nofxsr", x86_fxsr_setup); | |
137 | ||
138 | static int __init x86_sep_setup(char *s) | |
139 | { | |
140 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
141 | return 1; | |
142 | } | |
143 | __setup("nosep", x86_sep_setup); | |
144 | ||
145 | /* Standard macro to see if a specific flag is changeable */ | |
146 | static inline int flag_is_changeable_p(u32 flag) | |
147 | { | |
148 | u32 f1, f2; | |
149 | ||
94f6bac1 KH |
150 | /* |
151 | * Cyrix and IDT cpus allow disabling of CPUID | |
152 | * so the code below may return different results | |
153 | * when it is executed before and after enabling | |
154 | * the CPUID. Add "volatile" to not allow gcc to | |
155 | * optimize the subsequent calls to this function. | |
156 | */ | |
157 | asm volatile ("pushfl\n\t" | |
158 | "pushfl\n\t" | |
159 | "popl %0\n\t" | |
160 | "movl %0,%1\n\t" | |
161 | "xorl %2,%0\n\t" | |
162 | "pushl %0\n\t" | |
163 | "popfl\n\t" | |
164 | "pushfl\n\t" | |
165 | "popl %0\n\t" | |
166 | "popfl\n\t" | |
167 | : "=&r" (f1), "=&r" (f2) | |
168 | : "ir" (flag)); | |
0a488a53 YL |
169 | |
170 | return ((f1^f2) & flag) != 0; | |
171 | } | |
172 | ||
173 | /* Probe for the CPUID instruction */ | |
174 | static int __cpuinit have_cpuid_p(void) | |
175 | { | |
176 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
177 | } | |
178 | ||
179 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
180 | { | |
181 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { | |
182 | /* Disable processor serial number */ | |
183 | unsigned long lo, hi; | |
184 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
185 | lo |= 0x200000; | |
186 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
187 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
188 | clear_cpu_cap(c, X86_FEATURE_PN); | |
189 | ||
190 | /* Disabling the serial number may affect the cpuid level */ | |
191 | c->cpuid_level = cpuid_eax(0); | |
192 | } | |
193 | } | |
194 | ||
195 | static int __init x86_serial_nr_setup(char *s) | |
196 | { | |
197 | disable_x86_serial_nr = 0; | |
198 | return 1; | |
199 | } | |
200 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 201 | #else |
102bbe3a YL |
202 | static inline int flag_is_changeable_p(u32 flag) |
203 | { | |
204 | return 1; | |
205 | } | |
ba51dced YL |
206 | /* Probe for the CPUID instruction */ |
207 | static inline int have_cpuid_p(void) | |
208 | { | |
209 | return 1; | |
210 | } | |
102bbe3a YL |
211 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
212 | { | |
213 | } | |
ba51dced | 214 | #endif |
0a488a53 | 215 | |
102bbe3a YL |
216 | /* |
217 | * Naming convention should be: <Name> [(<Codename>)] | |
218 | * This table only is used unless init_<vendor>() below doesn't set it; | |
219 | * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used | |
220 | * | |
221 | */ | |
222 | ||
223 | /* Look up CPU names by table lookup. */ | |
224 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) | |
225 | { | |
226 | struct cpu_model_info *info; | |
227 | ||
228 | if (c->x86_model >= 16) | |
229 | return NULL; /* Range check */ | |
230 | ||
231 | if (!this_cpu) | |
232 | return NULL; | |
233 | ||
234 | info = this_cpu->c_models; | |
235 | ||
236 | while (info && info->family) { | |
237 | if (info->family == c->x86) | |
238 | return info->model_names[c->x86_model]; | |
239 | info++; | |
240 | } | |
241 | return NULL; /* Not found */ | |
242 | } | |
243 | ||
7d851c8d AK |
244 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
245 | ||
9d31d35b YL |
246 | /* Current gdt points %fs at the "master" per-cpu area: after this, |
247 | * it's on the real one. */ | |
248 | void switch_to_new_gdt(void) | |
249 | { | |
250 | struct desc_ptr gdt_descr; | |
251 | ||
252 | gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id()); | |
253 | gdt_descr.size = GDT_SIZE - 1; | |
254 | load_gdt(&gdt_descr); | |
fab334c1 | 255 | #ifdef CONFIG_X86_32 |
9d31d35b | 256 | asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory"); |
fab334c1 | 257 | #endif |
9d31d35b YL |
258 | } |
259 | ||
10a434fc | 260 | static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 261 | |
34048c9e | 262 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
1da177e4 | 263 | { |
b9e67f00 YL |
264 | #ifdef CONFIG_X86_64 |
265 | display_cacheinfo(c); | |
266 | #else | |
1da177e4 LT |
267 | /* Not much we can do here... */ |
268 | /* Check if at least it has cpuid */ | |
269 | if (c->cpuid_level == -1) { | |
270 | /* No cpuid. It must be an ancient CPU */ | |
271 | if (c->x86 == 4) | |
272 | strcpy(c->x86_model_id, "486"); | |
273 | else if (c->x86 == 3) | |
274 | strcpy(c->x86_model_id, "386"); | |
275 | } | |
b9e67f00 | 276 | #endif |
1da177e4 LT |
277 | } |
278 | ||
95414930 | 279 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 280 | .c_init = default_init, |
fe38d855 | 281 | .c_vendor = "Unknown", |
10a434fc | 282 | .c_x86_vendor = X86_VENDOR_UNKNOWN, |
1da177e4 | 283 | }; |
1da177e4 | 284 | |
1b05d60d | 285 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
286 | { |
287 | unsigned int *v; | |
288 | char *p, *q; | |
289 | ||
3da99c97 | 290 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 291 | return; |
1da177e4 LT |
292 | |
293 | v = (unsigned int *) c->x86_model_id; | |
294 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
295 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
296 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
297 | c->x86_model_id[48] = 0; | |
298 | ||
299 | /* Intel chips right-justify this string for some dumb reason; | |
300 | undo that brain damage */ | |
301 | p = q = &c->x86_model_id[0]; | |
34048c9e | 302 | while (*p == ' ') |
1da177e4 | 303 | p++; |
34048c9e PC |
304 | if (p != q) { |
305 | while (*p) | |
1da177e4 | 306 | *q++ = *p++; |
34048c9e | 307 | while (q <= &c->x86_model_id[48]) |
1da177e4 LT |
308 | *q++ = '\0'; /* Zero-pad the rest */ |
309 | } | |
1da177e4 LT |
310 | } |
311 | ||
3bc9b76b | 312 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 | 313 | { |
9d31d35b | 314 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 315 | |
3da99c97 | 316 | n = c->extended_cpuid_level; |
1da177e4 LT |
317 | |
318 | if (n >= 0x80000005) { | |
9d31d35b | 319 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 320 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
9d31d35b YL |
321 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); |
322 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
140fc727 YL |
323 | #ifdef CONFIG_X86_64 |
324 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
325 | c->x86_tlbsize = 0; | |
326 | #endif | |
1da177e4 LT |
327 | } |
328 | ||
329 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
330 | return; | |
331 | ||
0a488a53 | 332 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 333 | l2size = ecx >> 16; |
34048c9e | 334 | |
140fc727 YL |
335 | #ifdef CONFIG_X86_64 |
336 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
337 | #else | |
1da177e4 LT |
338 | /* do processor-specific cache resizing */ |
339 | if (this_cpu->c_size_cache) | |
34048c9e | 340 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
341 | |
342 | /* Allow user to override all this if necessary. */ | |
343 | if (cachesize_override != -1) | |
344 | l2size = cachesize_override; | |
345 | ||
34048c9e | 346 | if (l2size == 0) |
1da177e4 | 347 | return; /* Again, no L2 cache is possible */ |
140fc727 | 348 | #endif |
1da177e4 LT |
349 | |
350 | c->x86_cache_size = l2size; | |
351 | ||
352 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
0a488a53 | 353 | l2size, ecx & 0xFF); |
1da177e4 LT |
354 | } |
355 | ||
9d31d35b | 356 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 357 | { |
97e4db7c | 358 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
359 | u32 eax, ebx, ecx, edx; |
360 | int index_msb, core_bits; | |
1da177e4 | 361 | |
0a488a53 | 362 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 363 | return; |
1da177e4 | 364 | |
0a488a53 YL |
365 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
366 | goto out; | |
1da177e4 | 367 | |
1cd78776 YL |
368 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
369 | return; | |
1da177e4 | 370 | |
0a488a53 | 371 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 372 | |
9d31d35b YL |
373 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
374 | ||
375 | if (smp_num_siblings == 1) { | |
376 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
377 | } else if (smp_num_siblings > 1) { | |
378 | ||
9628937d | 379 | if (smp_num_siblings > nr_cpu_ids) { |
9d31d35b YL |
380 | printk(KERN_WARNING "CPU: Unsupported number of siblings %d", |
381 | smp_num_siblings); | |
382 | smp_num_siblings = 1; | |
383 | return; | |
384 | } | |
385 | ||
386 | index_msb = get_count_order(smp_num_siblings); | |
1cd78776 YL |
387 | #ifdef CONFIG_X86_64 |
388 | c->phys_proc_id = phys_pkg_id(index_msb); | |
389 | #else | |
9d31d35b | 390 | c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb); |
1cd78776 | 391 | #endif |
9d31d35b YL |
392 | |
393 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
394 | ||
395 | index_msb = get_count_order(smp_num_siblings); | |
396 | ||
397 | core_bits = get_count_order(c->x86_max_cores); | |
398 | ||
1cd78776 YL |
399 | #ifdef CONFIG_X86_64 |
400 | c->cpu_core_id = phys_pkg_id(index_msb) & | |
401 | ((1 << core_bits) - 1); | |
402 | #else | |
9d31d35b YL |
403 | c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) & |
404 | ((1 << core_bits) - 1); | |
1cd78776 | 405 | #endif |
1da177e4 | 406 | } |
1da177e4 | 407 | |
0a488a53 YL |
408 | out: |
409 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
410 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
411 | c->phys_proc_id); | |
412 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
413 | c->cpu_core_id); | |
9d31d35b | 414 | } |
9d31d35b | 415 | #endif |
97e4db7c | 416 | } |
1da177e4 | 417 | |
3da99c97 | 418 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
419 | { |
420 | char *v = c->x86_vendor_id; | |
421 | int i; | |
fe38d855 | 422 | static int printed; |
1da177e4 LT |
423 | |
424 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
425 | if (!cpu_devs[i]) |
426 | break; | |
427 | ||
428 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
429 | (cpu_devs[i]->c_ident[1] && | |
430 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
431 | this_cpu = cpu_devs[i]; | |
432 | c->x86_vendor = this_cpu->c_x86_vendor; | |
433 | return; | |
1da177e4 LT |
434 | } |
435 | } | |
10a434fc | 436 | |
fe38d855 CE |
437 | if (!printed) { |
438 | printed++; | |
43603c8d | 439 | printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v); |
fe38d855 CE |
440 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); |
441 | } | |
10a434fc | 442 | |
fe38d855 CE |
443 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
444 | this_cpu = &default_cpu; | |
1da177e4 LT |
445 | } |
446 | ||
9d31d35b | 447 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 448 | { |
1da177e4 | 449 | /* Get vendor name */ |
4a148513 HH |
450 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
451 | (unsigned int *)&c->x86_vendor_id[0], | |
452 | (unsigned int *)&c->x86_vendor_id[8], | |
453 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 454 | |
1da177e4 | 455 | c->x86 = 4; |
9d31d35b | 456 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
457 | if (c->cpuid_level >= 0x00000001) { |
458 | u32 junk, tfms, cap0, misc; | |
459 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
9d31d35b YL |
460 | c->x86 = (tfms >> 8) & 0xf; |
461 | c->x86_model = (tfms >> 4) & 0xf; | |
462 | c->x86_mask = tfms & 0xf; | |
f5f786d0 | 463 | if (c->x86 == 0xf) |
1da177e4 | 464 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 465 | if (c->x86 >= 0x6) |
9d31d35b | 466 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
d4387bd3 | 467 | if (cap0 & (1<<19)) { |
d4387bd3 | 468 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 469 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 470 | } |
1da177e4 | 471 | } |
1da177e4 | 472 | } |
3da99c97 YL |
473 | |
474 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
093af8d7 YL |
475 | { |
476 | u32 tfms, xlvl; | |
3da99c97 | 477 | u32 ebx; |
093af8d7 | 478 | |
3da99c97 YL |
479 | /* Intel-defined flags: level 0x00000001 */ |
480 | if (c->cpuid_level >= 0x00000001) { | |
481 | u32 capability, excap; | |
482 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
483 | c->x86_capability[0] = capability; | |
484 | c->x86_capability[4] = excap; | |
485 | } | |
093af8d7 | 486 | |
3da99c97 YL |
487 | /* AMD-defined flags: level 0x80000001 */ |
488 | xlvl = cpuid_eax(0x80000000); | |
489 | c->extended_cpuid_level = xlvl; | |
490 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
491 | if (xlvl >= 0x80000001) { | |
492 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
493 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 494 | } |
093af8d7 | 495 | } |
093af8d7 | 496 | |
5122c890 | 497 | #ifdef CONFIG_X86_64 |
5122c890 YL |
498 | if (c->extended_cpuid_level >= 0x80000008) { |
499 | u32 eax = cpuid_eax(0x80000008); | |
500 | ||
501 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
502 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 503 | } |
5122c890 | 504 | #endif |
e3224234 YL |
505 | |
506 | if (c->extended_cpuid_level >= 0x80000007) | |
507 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 YL |
508 | |
509 | } | |
1da177e4 | 510 | |
aef93c8b YL |
511 | static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
512 | { | |
513 | #ifdef CONFIG_X86_32 | |
514 | int i; | |
515 | ||
516 | /* | |
517 | * First of all, decide if this is a 486 or higher | |
518 | * It's a 486 if we can modify the AC flag | |
519 | */ | |
520 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
521 | c->x86 = 4; | |
522 | else | |
523 | c->x86 = 3; | |
524 | ||
525 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
526 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
527 | c->x86_vendor_id[0] = 0; | |
528 | cpu_devs[i]->c_identify(c); | |
529 | if (c->x86_vendor_id[0]) { | |
530 | get_cpu_vendor(c); | |
531 | break; | |
532 | } | |
533 | } | |
534 | #endif | |
535 | } | |
536 | ||
34048c9e PC |
537 | /* |
538 | * Do minimum CPU detection early. | |
539 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
540 | * cache alignment. | |
541 | * The others are not touched to avoid unwanted side effects. | |
542 | * | |
543 | * WARNING: this function is only called on the BP. Don't add code here | |
544 | * that is supposed to run on all CPUs. | |
545 | */ | |
3da99c97 | 546 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 547 | { |
6627d242 YL |
548 | #ifdef CONFIG_X86_64 |
549 | c->x86_clflush_size = 64; | |
550 | #else | |
d4387bd3 | 551 | c->x86_clflush_size = 32; |
6627d242 | 552 | #endif |
0a488a53 | 553 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 554 | |
3da99c97 | 555 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 556 | c->extended_cpuid_level = 0; |
d7cd5611 | 557 | |
aef93c8b YL |
558 | if (!have_cpuid_p()) |
559 | identify_cpu_without_cpuid(c); | |
560 | ||
561 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
562 | if (!have_cpuid_p()) |
563 | return; | |
564 | ||
565 | cpu_detect(c); | |
566 | ||
3da99c97 | 567 | get_cpu_vendor(c); |
2b16a235 | 568 | |
3da99c97 | 569 | get_cpu_cap(c); |
12cf105c | 570 | |
10a434fc YL |
571 | if (this_cpu->c_early_init) |
572 | this_cpu->c_early_init(c); | |
093af8d7 | 573 | |
3da99c97 | 574 | validate_pat_support(c); |
bfcb4c1b | 575 | |
1c4acdb4 | 576 | #ifdef CONFIG_SMP |
bfcb4c1b | 577 | c->cpu_index = boot_cpu_id; |
1c4acdb4 | 578 | #endif |
d7cd5611 RR |
579 | } |
580 | ||
9d31d35b YL |
581 | void __init early_cpu_init(void) |
582 | { | |
10a434fc YL |
583 | struct cpu_dev **cdev; |
584 | int count = 0; | |
585 | ||
586 | printk("KERNEL supported cpus:\n"); | |
587 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { | |
588 | struct cpu_dev *cpudev = *cdev; | |
589 | unsigned int j; | |
9d31d35b | 590 | |
10a434fc YL |
591 | if (count >= X86_VENDOR_NUM) |
592 | break; | |
593 | cpu_devs[count] = cpudev; | |
594 | count++; | |
595 | ||
596 | for (j = 0; j < 2; j++) { | |
597 | if (!cpudev->c_ident[j]) | |
598 | continue; | |
599 | printk(" %s %s\n", cpudev->c_vendor, | |
600 | cpudev->c_ident[j]); | |
601 | } | |
602 | } | |
9d31d35b | 603 | |
9d31d35b | 604 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 605 | } |
093af8d7 | 606 | |
b6734c35 PA |
607 | /* |
608 | * The NOPL instruction is supposed to exist on all CPUs with | |
ba0593bf | 609 | * family >= 6; unfortunately, that's not true in practice because |
b6734c35 | 610 | * of early VIA chips and (more importantly) broken virtualizers that |
ba0593bf PA |
611 | * are not easy to detect. In the latter case it doesn't even *fail* |
612 | * reliably, so probing for it doesn't even work. Disable it completely | |
613 | * unless we can find a reliable way to detect all the broken cases. | |
b6734c35 PA |
614 | */ |
615 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
616 | { | |
b6734c35 | 617 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
d7cd5611 RR |
618 | } |
619 | ||
34048c9e | 620 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 621 | { |
aef93c8b | 622 | c->extended_cpuid_level = 0; |
1da177e4 | 623 | |
3da99c97 | 624 | if (!have_cpuid_p()) |
aef93c8b | 625 | identify_cpu_without_cpuid(c); |
1d67953f | 626 | |
aef93c8b | 627 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 628 | if (!have_cpuid_p()) |
aef93c8b | 629 | return; |
1da177e4 | 630 | |
3da99c97 | 631 | cpu_detect(c); |
1da177e4 | 632 | |
3da99c97 | 633 | get_cpu_vendor(c); |
1da177e4 | 634 | |
3da99c97 | 635 | get_cpu_cap(c); |
1da177e4 | 636 | |
3da99c97 YL |
637 | if (c->cpuid_level >= 0x00000001) { |
638 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
639 | #ifdef CONFIG_X86_32 |
640 | # ifdef CONFIG_X86_HT | |
3da99c97 | 641 | c->apicid = phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 642 | # else |
3da99c97 | 643 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
644 | # endif |
645 | #endif | |
1da177e4 | 646 | |
b89d3b3e YL |
647 | #ifdef CONFIG_X86_HT |
648 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 649 | #endif |
3da99c97 | 650 | } |
1da177e4 | 651 | |
1b05d60d | 652 | get_model_name(c); /* Default name */ |
1da177e4 | 653 | |
3da99c97 YL |
654 | init_scattered_cpuid_features(c); |
655 | detect_nopl(c); | |
1da177e4 | 656 | } |
1da177e4 LT |
657 | |
658 | /* | |
659 | * This does the hard work of actually picking apart the CPU stuff... | |
660 | */ | |
9a250347 | 661 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
662 | { |
663 | int i; | |
664 | ||
665 | c->loops_per_jiffy = loops_per_jiffy; | |
666 | c->x86_cache_size = -1; | |
667 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
668 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
669 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
670 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 671 | c->x86_max_cores = 1; |
102bbe3a | 672 | c->x86_coreid_bits = 0; |
11fdd252 | 673 | #ifdef CONFIG_X86_64 |
102bbe3a YL |
674 | c->x86_clflush_size = 64; |
675 | #else | |
676 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 677 | c->x86_clflush_size = 32; |
102bbe3a YL |
678 | #endif |
679 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
680 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
681 | ||
1da177e4 LT |
682 | generic_identify(c); |
683 | ||
3898534d | 684 | if (this_cpu->c_identify) |
1da177e4 LT |
685 | this_cpu->c_identify(c); |
686 | ||
102bbe3a YL |
687 | #ifdef CONFIG_X86_64 |
688 | c->apicid = phys_pkg_id(0); | |
689 | #endif | |
690 | ||
1da177e4 LT |
691 | /* |
692 | * Vendor-specific initialization. In this section we | |
693 | * canonicalize the feature flags, meaning if there are | |
694 | * features a certain CPU supports which CPUID doesn't | |
695 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
696 | * we handle them here. | |
697 | * | |
698 | * At the end of this section, c->x86_capability better | |
699 | * indicate the features this CPU genuinely supports! | |
700 | */ | |
701 | if (this_cpu->c_init) | |
702 | this_cpu->c_init(c); | |
703 | ||
704 | /* Disable the PN if appropriate */ | |
705 | squash_the_stupid_serial_number(c); | |
706 | ||
707 | /* | |
708 | * The vendor-specific functions might have changed features. Now | |
709 | * we do "generic changes." | |
710 | */ | |
711 | ||
1da177e4 | 712 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 713 | if (!c->x86_model_id[0]) { |
1da177e4 LT |
714 | char *p; |
715 | p = table_lookup_model(c); | |
34048c9e | 716 | if (p) |
1da177e4 LT |
717 | strcpy(c->x86_model_id, p); |
718 | else | |
719 | /* Last resort... */ | |
720 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 721 | c->x86, c->x86_model); |
1da177e4 LT |
722 | } |
723 | ||
102bbe3a YL |
724 | #ifdef CONFIG_X86_64 |
725 | detect_ht(c); | |
726 | #endif | |
727 | ||
88b094fb | 728 | init_hypervisor(c); |
1da177e4 LT |
729 | /* |
730 | * On SMP, boot_cpu_data holds the common feature set between | |
731 | * all CPUs; so make sure that we indicate which features are | |
732 | * common between the CPUs. The first time this routine gets | |
733 | * executed, c == &boot_cpu_data. | |
734 | */ | |
34048c9e | 735 | if (c != &boot_cpu_data) { |
1da177e4 | 736 | /* AND the already accumulated flags with these */ |
9d31d35b | 737 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
738 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
739 | } | |
740 | ||
7d851c8d AK |
741 | /* Clear all flags overriden by options */ |
742 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 743 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 744 | |
102bbe3a | 745 | #ifdef CONFIG_X86_MCE |
1da177e4 | 746 | /* Init Machine Check Exception if available. */ |
1da177e4 | 747 | mcheck_init(c); |
102bbe3a | 748 | #endif |
30d432df AK |
749 | |
750 | select_idle_routine(c); | |
102bbe3a YL |
751 | |
752 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
753 | numa_add_cpu(smp_processor_id()); | |
754 | #endif | |
a6c4e076 | 755 | } |
31ab269a | 756 | |
e04d645f GC |
757 | #ifdef CONFIG_X86_64 |
758 | static void vgetcpu_set_mode(void) | |
759 | { | |
760 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
761 | vgetcpu_mode = VGETCPU_RDTSCP; | |
762 | else | |
763 | vgetcpu_mode = VGETCPU_LSL; | |
764 | } | |
765 | #endif | |
766 | ||
a6c4e076 JF |
767 | void __init identify_boot_cpu(void) |
768 | { | |
769 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 770 | #ifdef CONFIG_X86_32 |
a6c4e076 | 771 | sysenter_setup(); |
6fe940d6 | 772 | enable_sep_cpu(); |
e04d645f GC |
773 | #else |
774 | vgetcpu_set_mode(); | |
102bbe3a | 775 | #endif |
a6c4e076 | 776 | } |
3b520b23 | 777 | |
a6c4e076 JF |
778 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
779 | { | |
780 | BUG_ON(c == &boot_cpu_data); | |
781 | identify_cpu(c); | |
102bbe3a | 782 | #ifdef CONFIG_X86_32 |
a6c4e076 | 783 | enable_sep_cpu(); |
102bbe3a | 784 | #endif |
a6c4e076 | 785 | mtrr_ap_init(); |
1da177e4 LT |
786 | } |
787 | ||
a0854a46 YL |
788 | struct msr_range { |
789 | unsigned min; | |
790 | unsigned max; | |
791 | }; | |
1da177e4 | 792 | |
a0854a46 YL |
793 | static struct msr_range msr_range_array[] __cpuinitdata = { |
794 | { 0x00000000, 0x00000418}, | |
795 | { 0xc0000000, 0xc000040b}, | |
796 | { 0xc0010000, 0xc0010142}, | |
797 | { 0xc0011000, 0xc001103b}, | |
798 | }; | |
1da177e4 | 799 | |
a0854a46 YL |
800 | static void __cpuinit print_cpu_msr(void) |
801 | { | |
802 | unsigned index; | |
803 | u64 val; | |
804 | int i; | |
805 | unsigned index_min, index_max; | |
806 | ||
807 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
808 | index_min = msr_range_array[i].min; | |
809 | index_max = msr_range_array[i].max; | |
810 | for (index = index_min; index < index_max; index++) { | |
811 | if (rdmsrl_amd_safe(index, &val)) | |
812 | continue; | |
813 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 814 | } |
a0854a46 YL |
815 | } |
816 | } | |
94605eff | 817 | |
a0854a46 YL |
818 | static int show_msr __cpuinitdata; |
819 | static __init int setup_show_msr(char *arg) | |
820 | { | |
821 | int num; | |
3dd9d514 | 822 | |
a0854a46 | 823 | get_option(&arg, &num); |
3dd9d514 | 824 | |
a0854a46 YL |
825 | if (num > 0) |
826 | show_msr = num; | |
827 | return 1; | |
1da177e4 | 828 | } |
a0854a46 | 829 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 830 | |
191679fd AK |
831 | static __init int setup_noclflush(char *arg) |
832 | { | |
833 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
834 | return 1; | |
835 | } | |
836 | __setup("noclflush", setup_noclflush); | |
837 | ||
3bc9b76b | 838 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
839 | { |
840 | char *vendor = NULL; | |
841 | ||
842 | if (c->x86_vendor < X86_VENDOR_NUM) | |
843 | vendor = this_cpu->c_vendor; | |
844 | else if (c->cpuid_level >= 0) | |
845 | vendor = c->x86_vendor_id; | |
846 | ||
bd32a8cf | 847 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 848 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 849 | |
9d31d35b YL |
850 | if (c->x86_model_id[0]) |
851 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 852 | else |
9d31d35b | 853 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 854 | |
34048c9e | 855 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 856 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 857 | else |
9d31d35b | 858 | printk(KERN_CONT "\n"); |
a0854a46 YL |
859 | |
860 | #ifdef CONFIG_SMP | |
861 | if (c->cpu_index < show_msr) | |
862 | print_cpu_msr(); | |
863 | #else | |
864 | if (show_msr) | |
865 | print_cpu_msr(); | |
866 | #endif | |
1da177e4 LT |
867 | } |
868 | ||
ac72e788 AK |
869 | static __init int setup_disablecpuid(char *arg) |
870 | { | |
871 | int bit; | |
872 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
873 | setup_clear_cpu_cap(bit); | |
874 | else | |
875 | return 0; | |
876 | return 1; | |
877 | } | |
878 | __setup("clearcpuid=", setup_disablecpuid); | |
879 | ||
d5494d4f YL |
880 | #ifdef CONFIG_X86_64 |
881 | struct x8664_pda **_cpu_pda __read_mostly; | |
882 | EXPORT_SYMBOL(_cpu_pda); | |
883 | ||
884 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; | |
885 | ||
34945ede | 886 | static char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss; |
d5494d4f | 887 | |
2d9cd6c2 | 888 | void __cpuinit pda_init(int cpu) |
d5494d4f YL |
889 | { |
890 | struct x8664_pda *pda = cpu_pda(cpu); | |
891 | ||
892 | /* Setup up data that may be needed in __get_free_pages early */ | |
893 | loadsegment(fs, 0); | |
894 | loadsegment(gs, 0); | |
895 | /* Memory clobbers used to order PDA accessed */ | |
896 | mb(); | |
897 | wrmsrl(MSR_GS_BASE, pda); | |
898 | mb(); | |
899 | ||
900 | pda->cpunumber = cpu; | |
901 | pda->irqcount = -1; | |
902 | pda->kernelstack = (unsigned long)stack_thread_info() - | |
903 | PDA_STACKOFFSET + THREAD_SIZE; | |
904 | pda->active_mm = &init_mm; | |
905 | pda->mmu_state = 0; | |
906 | ||
907 | if (cpu == 0) { | |
908 | /* others are initialized in smpboot.c */ | |
909 | pda->pcurrent = &init_task; | |
910 | pda->irqstackptr = boot_cpu_stack; | |
911 | pda->irqstackptr += IRQSTACKSIZE - 64; | |
912 | } else { | |
913 | if (!pda->irqstackptr) { | |
914 | pda->irqstackptr = (char *) | |
915 | __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER); | |
916 | if (!pda->irqstackptr) | |
917 | panic("cannot allocate irqstack for cpu %d", | |
918 | cpu); | |
919 | pda->irqstackptr += IRQSTACKSIZE - 64; | |
920 | } | |
921 | ||
922 | if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE) | |
923 | pda->nodenumber = cpu_to_node(cpu); | |
924 | } | |
925 | } | |
926 | ||
34945ede JS |
927 | static char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + |
928 | DEBUG_STKSZ] __page_aligned_bss; | |
d5494d4f YL |
929 | |
930 | extern asmlinkage void ignore_sysret(void); | |
931 | ||
932 | /* May not be marked __init: used by software suspend */ | |
933 | void syscall_init(void) | |
1da177e4 | 934 | { |
d5494d4f YL |
935 | /* |
936 | * LSTAR and STAR live in a bit strange symbiosis. | |
937 | * They both write to the same internal register. STAR allows to | |
938 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
939 | */ | |
940 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
941 | wrmsrl(MSR_LSTAR, system_call); | |
942 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 943 | |
d5494d4f YL |
944 | #ifdef CONFIG_IA32_EMULATION |
945 | syscall32_cpu_init(); | |
946 | #endif | |
03ae5768 | 947 | |
d5494d4f YL |
948 | /* Flags to clear on syscall */ |
949 | wrmsrl(MSR_SYSCALL_MASK, | |
950 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
1da177e4 | 951 | } |
62111195 | 952 | |
d5494d4f YL |
953 | unsigned long kernel_eflags; |
954 | ||
955 | /* | |
956 | * Copies of the original ist values from the tss are only accessed during | |
957 | * debugging, no special alignment required. | |
958 | */ | |
959 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
960 | ||
961 | #else | |
962 | ||
7c3576d2 | 963 | /* Make sure %fs is initialized properly in idle threads */ |
6b2fb3c6 | 964 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
965 | { |
966 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 967 | regs->fs = __KERNEL_PERCPU; |
f95d47ca JF |
968 | return regs; |
969 | } | |
d5494d4f | 970 | #endif |
c5413fbe | 971 | |
d2cbcc49 RR |
972 | /* |
973 | * cpu_init() initializes state that is per-CPU. Some data is already | |
974 | * initialized (naturally) in the bootstrap process, such as the GDT | |
975 | * and IDT. We reload them nevertheless, this function acts as a | |
976 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 977 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 978 | */ |
1ba76586 YL |
979 | #ifdef CONFIG_X86_64 |
980 | void __cpuinit cpu_init(void) | |
981 | { | |
982 | int cpu = stack_smp_processor_id(); | |
983 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
984 | struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); | |
985 | unsigned long v; | |
986 | char *estacks = NULL; | |
987 | struct task_struct *me; | |
988 | int i; | |
989 | ||
990 | /* CPU 0 is initialised in head64.c */ | |
991 | if (cpu != 0) | |
992 | pda_init(cpu); | |
993 | else | |
994 | estacks = boot_exception_stacks; | |
995 | ||
996 | me = current; | |
997 | ||
c2d1cec1 | 998 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) |
1ba76586 YL |
999 | panic("CPU#%d already initialized!\n", cpu); |
1000 | ||
1001 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1002 | ||
1003 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1004 | ||
1005 | /* | |
1006 | * Initialize the per-CPU GDT with the boot GDT, | |
1007 | * and set up the GDT descriptor: | |
1008 | */ | |
1009 | ||
1010 | switch_to_new_gdt(); | |
1011 | load_idt((const struct desc_ptr *)&idt_descr); | |
1012 | ||
1013 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1014 | syscall_init(); | |
1015 | ||
1016 | wrmsrl(MSR_FS_BASE, 0); | |
1017 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1018 | barrier(); | |
1019 | ||
1020 | check_efer(); | |
1021 | if (cpu != 0 && x2apic) | |
1022 | enable_x2apic(); | |
1023 | ||
1024 | /* | |
1025 | * set up and load the per-CPU TSS | |
1026 | */ | |
1027 | if (!orig_ist->ist[0]) { | |
1028 | static const unsigned int order[N_EXCEPTION_STACKS] = { | |
1029 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER, | |
1030 | [DEBUG_STACK - 1] = DEBUG_STACK_ORDER | |
1031 | }; | |
1032 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { | |
1033 | if (cpu) { | |
1034 | estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]); | |
1035 | if (!estacks) | |
1036 | panic("Cannot allocate exception " | |
1037 | "stack %ld %d\n", v, cpu); | |
1038 | } | |
1039 | estacks += PAGE_SIZE << order[v]; | |
1040 | orig_ist->ist[v] = t->x86_tss.ist[v] = | |
1041 | (unsigned long)estacks; | |
1042 | } | |
1043 | } | |
1044 | ||
1045 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
1046 | /* | |
1047 | * <= is required because the CPU will access up to | |
1048 | * 8 bits beyond the end of the IO permission bitmap. | |
1049 | */ | |
1050 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1051 | t->io_bitmap[i] = ~0UL; | |
1052 | ||
1053 | atomic_inc(&init_mm.mm_count); | |
1054 | me->active_mm = &init_mm; | |
1055 | if (me->mm) | |
1056 | BUG(); | |
1057 | enter_lazy_tlb(&init_mm, me); | |
1058 | ||
1059 | load_sp0(t, ¤t->thread); | |
1060 | set_tss_desc(cpu, t); | |
1061 | load_TR_desc(); | |
1062 | load_LDT(&init_mm.context); | |
1063 | ||
1064 | #ifdef CONFIG_KGDB | |
1065 | /* | |
1066 | * If the kgdb is connected no debug regs should be altered. This | |
1067 | * is only applicable when KGDB and a KGDB I/O module are built | |
1068 | * into the kernel and you are using early debugging with | |
1069 | * kgdbwait. KGDB will control the kernel HW breakpoint registers. | |
1070 | */ | |
1071 | if (kgdb_connected && arch_kgdb_ops.correct_hw_break) | |
1072 | arch_kgdb_ops.correct_hw_break(); | |
1073 | else { | |
1074 | #endif | |
1075 | /* | |
1076 | * Clear all 6 debug registers: | |
1077 | */ | |
1078 | ||
1079 | set_debugreg(0UL, 0); | |
1080 | set_debugreg(0UL, 1); | |
1081 | set_debugreg(0UL, 2); | |
1082 | set_debugreg(0UL, 3); | |
1083 | set_debugreg(0UL, 6); | |
1084 | set_debugreg(0UL, 7); | |
1085 | #ifdef CONFIG_KGDB | |
1086 | /* If the kgdb is connected no debug regs should be altered. */ | |
1087 | } | |
1088 | #endif | |
1089 | ||
1090 | fpu_init(); | |
1091 | ||
1092 | raw_local_save_flags(kernel_eflags); | |
1093 | ||
1094 | if (is_uv_system()) | |
1095 | uv_cpu_init(); | |
1096 | } | |
1097 | ||
1098 | #else | |
1099 | ||
d2cbcc49 | 1100 | void __cpuinit cpu_init(void) |
9ee79a3d | 1101 | { |
d2cbcc49 RR |
1102 | int cpu = smp_processor_id(); |
1103 | struct task_struct *curr = current; | |
34048c9e | 1104 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1105 | struct thread_struct *thread = &curr->thread; |
62111195 | 1106 | |
c2d1cec1 | 1107 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { |
62111195 JF |
1108 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); |
1109 | for (;;) local_irq_enable(); | |
1110 | } | |
1111 | ||
1112 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1113 | ||
1114 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1115 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1116 | |
4d37e7e3 | 1117 | load_idt(&idt_descr); |
c5413fbe | 1118 | switch_to_new_gdt(); |
1da177e4 | 1119 | |
1da177e4 LT |
1120 | /* |
1121 | * Set up and load the per-CPU TSS and LDT | |
1122 | */ | |
1123 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
1124 | curr->active_mm = &init_mm; |
1125 | if (curr->mm) | |
1126 | BUG(); | |
1127 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 | 1128 | |
faca6227 | 1129 | load_sp0(t, thread); |
34048c9e | 1130 | set_tss_desc(cpu, t); |
1da177e4 LT |
1131 | load_TR_desc(); |
1132 | load_LDT(&init_mm.context); | |
1133 | ||
22c4e308 | 1134 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1135 | /* Set up doublefault TSS pointer in the GDT */ |
1136 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1137 | #endif |
1da177e4 | 1138 | |
464d1a78 JF |
1139 | /* Clear %gs. */ |
1140 | asm volatile ("mov %0, %%gs" : : "r" (0)); | |
1da177e4 LT |
1141 | |
1142 | /* Clear all 6 debug registers: */ | |
4bb0d3ec ZA |
1143 | set_debugreg(0, 0); |
1144 | set_debugreg(0, 1); | |
1145 | set_debugreg(0, 2); | |
1146 | set_debugreg(0, 3); | |
1147 | set_debugreg(0, 6); | |
1148 | set_debugreg(0, 7); | |
1da177e4 LT |
1149 | |
1150 | /* | |
1151 | * Force FPU initialization: | |
1152 | */ | |
b359e8a4 SS |
1153 | if (cpu_has_xsave) |
1154 | current_thread_info()->status = TS_XSAVE; | |
1155 | else | |
1156 | current_thread_info()->status = 0; | |
1da177e4 LT |
1157 | clear_used_math(); |
1158 | mxcsr_feature_mask_init(); | |
dc1e35c6 SS |
1159 | |
1160 | /* | |
1161 | * Boot processor to setup the FP and extended state context info. | |
1162 | */ | |
b3572e36 | 1163 | if (smp_processor_id() == boot_cpu_id) |
dc1e35c6 SS |
1164 | init_thread_xstate(); |
1165 | ||
1166 | xsave_init(); | |
1da177e4 | 1167 | } |
e1367daf | 1168 | |
1ba76586 YL |
1169 | |
1170 | #endif |