]>
Commit | Line | Data |
---|---|---|
f0fc4aff | 1 | #include <linux/bootmem.h> |
9766cdbc | 2 | #include <linux/linkage.h> |
f0fc4aff | 3 | #include <linux/bitops.h> |
9766cdbc | 4 | #include <linux/kernel.h> |
f0fc4aff | 5 | #include <linux/module.h> |
9766cdbc JSR |
6 | #include <linux/percpu.h> |
7 | #include <linux/string.h> | |
ee098e1a | 8 | #include <linux/ctype.h> |
1da177e4 | 9 | #include <linux/delay.h> |
9766cdbc JSR |
10 | #include <linux/sched.h> |
11 | #include <linux/init.h> | |
0f46efeb | 12 | #include <linux/kprobes.h> |
9766cdbc | 13 | #include <linux/kgdb.h> |
1da177e4 | 14 | #include <linux/smp.h> |
9766cdbc | 15 | #include <linux/io.h> |
b51ef52d | 16 | #include <linux/syscore_ops.h> |
9766cdbc JSR |
17 | |
18 | #include <asm/stackprotector.h> | |
cdd6c482 | 19 | #include <asm/perf_event.h> |
1da177e4 | 20 | #include <asm/mmu_context.h> |
49d859d7 | 21 | #include <asm/archrandom.h> |
9766cdbc JSR |
22 | #include <asm/hypervisor.h> |
23 | #include <asm/processor.h> | |
1e02ce4c | 24 | #include <asm/tlbflush.h> |
f649e938 | 25 | #include <asm/debugreg.h> |
9766cdbc | 26 | #include <asm/sections.h> |
f40c3300 | 27 | #include <asm/vsyscall.h> |
8bdbd962 AC |
28 | #include <linux/topology.h> |
29 | #include <linux/cpumask.h> | |
9766cdbc | 30 | #include <asm/pgtable.h> |
60063497 | 31 | #include <linux/atomic.h> |
9766cdbc JSR |
32 | #include <asm/proto.h> |
33 | #include <asm/setup.h> | |
34 | #include <asm/apic.h> | |
35 | #include <asm/desc.h> | |
78f7f1e5 | 36 | #include <asm/fpu/internal.h> |
27b07da7 | 37 | #include <asm/mtrr.h> |
8bdbd962 | 38 | #include <linux/numa.h> |
9766cdbc JSR |
39 | #include <asm/asm.h> |
40 | #include <asm/cpu.h> | |
a03a3e28 | 41 | #include <asm/mce.h> |
9766cdbc | 42 | #include <asm/msr.h> |
8d4a4300 | 43 | #include <asm/pat.h> |
d288e1cf FY |
44 | #include <asm/microcode.h> |
45 | #include <asm/microcode_intel.h> | |
e641f5f5 IM |
46 | |
47 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 48 | #include <asm/uv/uv.h> |
1da177e4 LT |
49 | #endif |
50 | ||
51 | #include "cpu.h" | |
52 | ||
c2d1cec1 | 53 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 54 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
55 | cpumask_var_t cpu_callout_mask; |
56 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
57 | |
58 | /* representing cpus for which sibling maps can be computed */ | |
59 | cpumask_var_t cpu_sibling_setup_mask; | |
60 | ||
2f2f52ba | 61 | /* correctly size the local cpu masks */ |
4369f1fb | 62 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
63 | { |
64 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
65 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
66 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
67 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
68 | } | |
69 | ||
148f9bb8 | 70 | static void default_init(struct cpuinfo_x86 *c) |
e8055139 OZ |
71 | { |
72 | #ifdef CONFIG_X86_64 | |
27c13ece | 73 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
74 | #else |
75 | /* Not much we can do here... */ | |
76 | /* Check if at least it has cpuid */ | |
77 | if (c->cpuid_level == -1) { | |
78 | /* No cpuid. It must be an ancient CPU */ | |
79 | if (c->x86 == 4) | |
80 | strcpy(c->x86_model_id, "486"); | |
81 | else if (c->x86 == 3) | |
82 | strcpy(c->x86_model_id, "386"); | |
83 | } | |
84 | #endif | |
85 | } | |
86 | ||
148f9bb8 | 87 | static const struct cpu_dev default_cpu = { |
e8055139 OZ |
88 | .c_init = default_init, |
89 | .c_vendor = "Unknown", | |
90 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
91 | }; | |
92 | ||
148f9bb8 | 93 | static const struct cpu_dev *this_cpu = &default_cpu; |
0a488a53 | 94 | |
06deef89 | 95 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 96 | #ifdef CONFIG_X86_64 |
06deef89 BG |
97 | /* |
98 | * We need valid kernel segments for data and code in long mode too | |
99 | * IRET will check the segment types kkeil 2000/10/28 | |
100 | * Also sysret mandates a special GDT layout | |
101 | * | |
9766cdbc | 102 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
103 | * Hopefully nobody expects them at a fixed place (Wine?) |
104 | */ | |
1e5de182 AM |
105 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
106 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
107 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
108 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
109 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
110 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 111 | #else |
1e5de182 AM |
112 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
113 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
114 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
115 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
116 | /* |
117 | * Segments used for calling PnP BIOS have byte granularity. | |
118 | * They code segments and data segments have fixed 64k limits, | |
119 | * the transfer segment sizes are set at run time. | |
120 | */ | |
6842ef0e | 121 | /* 32-bit code */ |
1e5de182 | 122 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 123 | /* 16-bit code */ |
1e5de182 | 124 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 125 | /* 16-bit data */ |
1e5de182 | 126 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 127 | /* 16-bit data */ |
1e5de182 | 128 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 129 | /* 16-bit data */ |
1e5de182 | 130 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
131 | /* |
132 | * The APM segments have byte granularity and their bases | |
133 | * are set at run time. All have 64k limits. | |
134 | */ | |
6842ef0e | 135 | /* 32-bit code */ |
1e5de182 | 136 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 137 | /* 16-bit code */ |
1e5de182 | 138 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 139 | /* data */ |
72c4d853 | 140 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 141 | |
1e5de182 AM |
142 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
143 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 144 | GDT_STACK_CANARY_INIT |
950ad7ff | 145 | #endif |
06deef89 | 146 | } }; |
7a61d35d | 147 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 148 | |
8c3641e9 | 149 | static int __init x86_mpx_setup(char *s) |
0c752a93 | 150 | { |
8c3641e9 | 151 | /* require an exact match without trailing characters */ |
2cd3949f DH |
152 | if (strlen(s)) |
153 | return 0; | |
0c752a93 | 154 | |
8c3641e9 DH |
155 | /* do not emit a message if the feature is not present */ |
156 | if (!boot_cpu_has(X86_FEATURE_MPX)) | |
157 | return 1; | |
6bad06b7 | 158 | |
8c3641e9 DH |
159 | setup_clear_cpu_cap(X86_FEATURE_MPX); |
160 | pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); | |
b6f42a4a FY |
161 | return 1; |
162 | } | |
8c3641e9 | 163 | __setup("nompx", x86_mpx_setup); |
b6f42a4a | 164 | |
d12a72b8 AL |
165 | static int __init x86_noinvpcid_setup(char *s) |
166 | { | |
167 | /* noinvpcid doesn't accept parameters */ | |
168 | if (s) | |
169 | return -EINVAL; | |
170 | ||
171 | /* do not emit a message if the feature is not present */ | |
172 | if (!boot_cpu_has(X86_FEATURE_INVPCID)) | |
173 | return 0; | |
174 | ||
175 | setup_clear_cpu_cap(X86_FEATURE_INVPCID); | |
176 | pr_info("noinvpcid: INVPCID feature disabled\n"); | |
177 | return 0; | |
178 | } | |
179 | early_param("noinvpcid", x86_noinvpcid_setup); | |
180 | ||
ba51dced | 181 | #ifdef CONFIG_X86_32 |
148f9bb8 PG |
182 | static int cachesize_override = -1; |
183 | static int disable_x86_serial_nr = 1; | |
1da177e4 | 184 | |
0a488a53 YL |
185 | static int __init cachesize_setup(char *str) |
186 | { | |
187 | get_option(&str, &cachesize_override); | |
188 | return 1; | |
189 | } | |
190 | __setup("cachesize=", cachesize_setup); | |
191 | ||
0a488a53 YL |
192 | static int __init x86_sep_setup(char *s) |
193 | { | |
194 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
195 | return 1; | |
196 | } | |
197 | __setup("nosep", x86_sep_setup); | |
198 | ||
199 | /* Standard macro to see if a specific flag is changeable */ | |
200 | static inline int flag_is_changeable_p(u32 flag) | |
201 | { | |
202 | u32 f1, f2; | |
203 | ||
94f6bac1 KH |
204 | /* |
205 | * Cyrix and IDT cpus allow disabling of CPUID | |
206 | * so the code below may return different results | |
207 | * when it is executed before and after enabling | |
208 | * the CPUID. Add "volatile" to not allow gcc to | |
209 | * optimize the subsequent calls to this function. | |
210 | */ | |
0f3fa48a IM |
211 | asm volatile ("pushfl \n\t" |
212 | "pushfl \n\t" | |
213 | "popl %0 \n\t" | |
214 | "movl %0, %1 \n\t" | |
215 | "xorl %2, %0 \n\t" | |
216 | "pushl %0 \n\t" | |
217 | "popfl \n\t" | |
218 | "pushfl \n\t" | |
219 | "popl %0 \n\t" | |
220 | "popfl \n\t" | |
221 | ||
94f6bac1 KH |
222 | : "=&r" (f1), "=&r" (f2) |
223 | : "ir" (flag)); | |
0a488a53 YL |
224 | |
225 | return ((f1^f2) & flag) != 0; | |
226 | } | |
227 | ||
228 | /* Probe for the CPUID instruction */ | |
148f9bb8 | 229 | int have_cpuid_p(void) |
0a488a53 YL |
230 | { |
231 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
232 | } | |
233 | ||
148f9bb8 | 234 | static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
0a488a53 | 235 | { |
0f3fa48a IM |
236 | unsigned long lo, hi; |
237 | ||
238 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
239 | return; | |
240 | ||
241 | /* Disable processor serial number: */ | |
242 | ||
243 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
244 | lo |= 0x200000; | |
245 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
246 | ||
1b74dde7 | 247 | pr_notice("CPU serial number disabled.\n"); |
0f3fa48a IM |
248 | clear_cpu_cap(c, X86_FEATURE_PN); |
249 | ||
250 | /* Disabling the serial number may affect the cpuid level */ | |
251 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
252 | } |
253 | ||
254 | static int __init x86_serial_nr_setup(char *s) | |
255 | { | |
256 | disable_x86_serial_nr = 0; | |
257 | return 1; | |
258 | } | |
259 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 260 | #else |
102bbe3a YL |
261 | static inline int flag_is_changeable_p(u32 flag) |
262 | { | |
263 | return 1; | |
264 | } | |
102bbe3a YL |
265 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
266 | { | |
267 | } | |
ba51dced | 268 | #endif |
0a488a53 | 269 | |
de5397ad FY |
270 | static __init int setup_disable_smep(char *arg) |
271 | { | |
b2cc2a07 | 272 | setup_clear_cpu_cap(X86_FEATURE_SMEP); |
de5397ad FY |
273 | return 1; |
274 | } | |
275 | __setup("nosmep", setup_disable_smep); | |
276 | ||
b2cc2a07 | 277 | static __always_inline void setup_smep(struct cpuinfo_x86 *c) |
de5397ad | 278 | { |
b2cc2a07 | 279 | if (cpu_has(c, X86_FEATURE_SMEP)) |
375074cc | 280 | cr4_set_bits(X86_CR4_SMEP); |
de5397ad FY |
281 | } |
282 | ||
52b6179a PA |
283 | static __init int setup_disable_smap(char *arg) |
284 | { | |
b2cc2a07 | 285 | setup_clear_cpu_cap(X86_FEATURE_SMAP); |
52b6179a PA |
286 | return 1; |
287 | } | |
288 | __setup("nosmap", setup_disable_smap); | |
289 | ||
b2cc2a07 PA |
290 | static __always_inline void setup_smap(struct cpuinfo_x86 *c) |
291 | { | |
581b7f15 | 292 | unsigned long eflags = native_save_fl(); |
b2cc2a07 PA |
293 | |
294 | /* This should have been cleared long ago */ | |
b2cc2a07 PA |
295 | BUG_ON(eflags & X86_EFLAGS_AC); |
296 | ||
03bbd596 PA |
297 | if (cpu_has(c, X86_FEATURE_SMAP)) { |
298 | #ifdef CONFIG_X86_SMAP | |
375074cc | 299 | cr4_set_bits(X86_CR4_SMAP); |
03bbd596 | 300 | #else |
375074cc | 301 | cr4_clear_bits(X86_CR4_SMAP); |
03bbd596 PA |
302 | #endif |
303 | } | |
de5397ad FY |
304 | } |
305 | ||
b38b0665 PA |
306 | /* |
307 | * Some CPU features depend on higher CPUID levels, which may not always | |
308 | * be available due to CPUID level capping or broken virtualization | |
309 | * software. Add those features to this table to auto-disable them. | |
310 | */ | |
311 | struct cpuid_dependent_feature { | |
312 | u32 feature; | |
313 | u32 level; | |
314 | }; | |
0f3fa48a | 315 | |
148f9bb8 | 316 | static const struct cpuid_dependent_feature |
b38b0665 PA |
317 | cpuid_dependent_features[] = { |
318 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
319 | { X86_FEATURE_DCA, 0x00000009 }, | |
320 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
321 | { 0, 0 } | |
322 | }; | |
323 | ||
148f9bb8 | 324 | static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) |
b38b0665 PA |
325 | { |
326 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 327 | |
b38b0665 | 328 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
329 | |
330 | if (!cpu_has(c, df->feature)) | |
331 | continue; | |
b38b0665 PA |
332 | /* |
333 | * Note: cpuid_level is set to -1 if unavailable, but | |
334 | * extended_extended_level is set to 0 if unavailable | |
335 | * and the legitimate extended levels are all negative | |
336 | * when signed; hence the weird messing around with | |
337 | * signs here... | |
338 | */ | |
0f3fa48a | 339 | if (!((s32)df->level < 0 ? |
f6db44df | 340 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
341 | (s32)df->level > (s32)c->cpuid_level)) |
342 | continue; | |
343 | ||
344 | clear_cpu_cap(c, df->feature); | |
345 | if (!warn) | |
346 | continue; | |
347 | ||
1b74dde7 CY |
348 | pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", |
349 | x86_cap_flag(df->feature), df->level); | |
b38b0665 | 350 | } |
f6db44df | 351 | } |
b38b0665 | 352 | |
102bbe3a YL |
353 | /* |
354 | * Naming convention should be: <Name> [(<Codename>)] | |
355 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
356 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
357 | * isn't used | |
102bbe3a YL |
358 | */ |
359 | ||
360 | /* Look up CPU names by table lookup. */ | |
148f9bb8 | 361 | static const char *table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 362 | { |
09dc68d9 JB |
363 | #ifdef CONFIG_X86_32 |
364 | const struct legacy_cpu_model_info *info; | |
102bbe3a YL |
365 | |
366 | if (c->x86_model >= 16) | |
367 | return NULL; /* Range check */ | |
368 | ||
369 | if (!this_cpu) | |
370 | return NULL; | |
371 | ||
09dc68d9 | 372 | info = this_cpu->legacy_models; |
102bbe3a | 373 | |
09dc68d9 | 374 | while (info->family) { |
102bbe3a YL |
375 | if (info->family == c->x86) |
376 | return info->model_names[c->x86_model]; | |
377 | info++; | |
378 | } | |
09dc68d9 | 379 | #endif |
102bbe3a YL |
380 | return NULL; /* Not found */ |
381 | } | |
382 | ||
148f9bb8 PG |
383 | __u32 cpu_caps_cleared[NCAPINTS]; |
384 | __u32 cpu_caps_set[NCAPINTS]; | |
7d851c8d | 385 | |
11e3a840 JF |
386 | void load_percpu_segment(int cpu) |
387 | { | |
388 | #ifdef CONFIG_X86_32 | |
389 | loadsegment(fs, __KERNEL_PERCPU); | |
390 | #else | |
391 | loadsegment(gs, 0); | |
392 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
393 | #endif | |
60a5317f | 394 | load_stack_canary_segment(); |
11e3a840 JF |
395 | } |
396 | ||
0f3fa48a IM |
397 | /* |
398 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
399 | * it's on the real one. | |
400 | */ | |
552be871 | 401 | void switch_to_new_gdt(int cpu) |
9d31d35b YL |
402 | { |
403 | struct desc_ptr gdt_descr; | |
404 | ||
2697fbd5 | 405 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
406 | gdt_descr.size = GDT_SIZE - 1; |
407 | load_gdt(&gdt_descr); | |
2697fbd5 | 408 | /* Reload the per-cpu base */ |
11e3a840 JF |
409 | |
410 | load_percpu_segment(cpu); | |
9d31d35b YL |
411 | } |
412 | ||
148f9bb8 | 413 | static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 414 | |
148f9bb8 | 415 | static void get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
416 | { |
417 | unsigned int *v; | |
ee098e1a | 418 | char *p, *q, *s; |
1da177e4 | 419 | |
3da99c97 | 420 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 421 | return; |
1da177e4 | 422 | |
0f3fa48a | 423 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
424 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
425 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
426 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
427 | c->x86_model_id[48] = 0; | |
428 | ||
ee098e1a BP |
429 | /* Trim whitespace */ |
430 | p = q = s = &c->x86_model_id[0]; | |
431 | ||
432 | while (*p == ' ') | |
433 | p++; | |
434 | ||
435 | while (*p) { | |
436 | /* Note the last non-whitespace index */ | |
437 | if (!isspace(*p)) | |
438 | s = q; | |
439 | ||
440 | *q++ = *p++; | |
441 | } | |
442 | ||
443 | *(s + 1) = '\0'; | |
1da177e4 LT |
444 | } |
445 | ||
148f9bb8 | 446 | void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 447 | { |
9d31d35b | 448 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 449 | |
3da99c97 | 450 | n = c->extended_cpuid_level; |
1da177e4 LT |
451 | |
452 | if (n >= 0x80000005) { | |
9d31d35b | 453 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 454 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
455 | #ifdef CONFIG_X86_64 |
456 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
457 | c->x86_tlbsize = 0; | |
458 | #endif | |
1da177e4 LT |
459 | } |
460 | ||
461 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
462 | return; | |
463 | ||
0a488a53 | 464 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 465 | l2size = ecx >> 16; |
34048c9e | 466 | |
140fc727 YL |
467 | #ifdef CONFIG_X86_64 |
468 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
469 | #else | |
1da177e4 | 470 | /* do processor-specific cache resizing */ |
09dc68d9 JB |
471 | if (this_cpu->legacy_cache_size) |
472 | l2size = this_cpu->legacy_cache_size(c, l2size); | |
1da177e4 LT |
473 | |
474 | /* Allow user to override all this if necessary. */ | |
475 | if (cachesize_override != -1) | |
476 | l2size = cachesize_override; | |
477 | ||
34048c9e | 478 | if (l2size == 0) |
1da177e4 | 479 | return; /* Again, no L2 cache is possible */ |
140fc727 | 480 | #endif |
1da177e4 LT |
481 | |
482 | c->x86_cache_size = l2size; | |
1da177e4 LT |
483 | } |
484 | ||
e0ba94f1 AS |
485 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
486 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
487 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
488 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
489 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
490 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
dd360393 | 491 | u16 __read_mostly tlb_lld_1g[NR_INFO]; |
e0ba94f1 | 492 | |
f94fe119 | 493 | static void cpu_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
494 | { |
495 | if (this_cpu->c_detect_tlb) | |
496 | this_cpu->c_detect_tlb(c); | |
497 | ||
f94fe119 | 498 | pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", |
e0ba94f1 | 499 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
f94fe119 SH |
500 | tlb_lli_4m[ENTRIES]); |
501 | ||
502 | pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", | |
503 | tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], | |
504 | tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); | |
e0ba94f1 AS |
505 | } |
506 | ||
148f9bb8 | 507 | void detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 508 | { |
c8e56d20 | 509 | #ifdef CONFIG_SMP |
0a488a53 YL |
510 | u32 eax, ebx, ecx, edx; |
511 | int index_msb, core_bits; | |
2eaad1fd | 512 | static bool printed; |
1da177e4 | 513 | |
0a488a53 | 514 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 515 | return; |
1da177e4 | 516 | |
0a488a53 YL |
517 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
518 | goto out; | |
1da177e4 | 519 | |
1cd78776 YL |
520 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
521 | return; | |
1da177e4 | 522 | |
0a488a53 | 523 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 524 | |
9d31d35b YL |
525 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
526 | ||
527 | if (smp_num_siblings == 1) { | |
1b74dde7 | 528 | pr_info_once("CPU0: Hyper-Threading is disabled\n"); |
0f3fa48a IM |
529 | goto out; |
530 | } | |
9d31d35b | 531 | |
0f3fa48a IM |
532 | if (smp_num_siblings <= 1) |
533 | goto out; | |
9d31d35b | 534 | |
0f3fa48a IM |
535 | index_msb = get_count_order(smp_num_siblings); |
536 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 537 | |
0f3fa48a | 538 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 539 | |
0f3fa48a | 540 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 541 | |
0f3fa48a | 542 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 543 | |
0f3fa48a IM |
544 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
545 | ((1 << core_bits) - 1); | |
1da177e4 | 546 | |
0a488a53 | 547 | out: |
2eaad1fd | 548 | if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { |
1b74dde7 CY |
549 | pr_info("CPU: Physical Processor ID: %d\n", |
550 | c->phys_proc_id); | |
551 | pr_info("CPU: Processor Core ID: %d\n", | |
552 | c->cpu_core_id); | |
2eaad1fd | 553 | printed = 1; |
9d31d35b | 554 | } |
9d31d35b | 555 | #endif |
97e4db7c | 556 | } |
1da177e4 | 557 | |
148f9bb8 | 558 | static void get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
559 | { |
560 | char *v = c->x86_vendor_id; | |
0f3fa48a | 561 | int i; |
1da177e4 LT |
562 | |
563 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
564 | if (!cpu_devs[i]) |
565 | break; | |
566 | ||
567 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
568 | (cpu_devs[i]->c_ident[1] && | |
569 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 570 | |
10a434fc YL |
571 | this_cpu = cpu_devs[i]; |
572 | c->x86_vendor = this_cpu->c_x86_vendor; | |
573 | return; | |
1da177e4 LT |
574 | } |
575 | } | |
10a434fc | 576 | |
1b74dde7 CY |
577 | pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ |
578 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 579 | |
fe38d855 CE |
580 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
581 | this_cpu = &default_cpu; | |
1da177e4 LT |
582 | } |
583 | ||
148f9bb8 | 584 | void cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 585 | { |
1da177e4 | 586 | /* Get vendor name */ |
4a148513 HH |
587 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
588 | (unsigned int *)&c->x86_vendor_id[0], | |
589 | (unsigned int *)&c->x86_vendor_id[8], | |
590 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 591 | |
1da177e4 | 592 | c->x86 = 4; |
9d31d35b | 593 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
594 | if (c->cpuid_level >= 0x00000001) { |
595 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 596 | |
1da177e4 | 597 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
99f925ce BP |
598 | c->x86 = x86_family(tfms); |
599 | c->x86_model = x86_model(tfms); | |
600 | c->x86_mask = x86_stepping(tfms); | |
0f3fa48a | 601 | |
d4387bd3 | 602 | if (cap0 & (1<<19)) { |
d4387bd3 | 603 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 604 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 605 | } |
1da177e4 | 606 | } |
1da177e4 | 607 | } |
3da99c97 | 608 | |
148f9bb8 | 609 | void get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 | 610 | { |
39c06df4 | 611 | u32 eax, ebx, ecx, edx; |
093af8d7 | 612 | |
3da99c97 YL |
613 | /* Intel-defined flags: level 0x00000001 */ |
614 | if (c->cpuid_level >= 0x00000001) { | |
39c06df4 | 615 | cpuid(0x00000001, &eax, &ebx, &ecx, &edx); |
0f3fa48a | 616 | |
39c06df4 BP |
617 | c->x86_capability[CPUID_1_ECX] = ecx; |
618 | c->x86_capability[CPUID_1_EDX] = edx; | |
3da99c97 | 619 | } |
093af8d7 | 620 | |
bdc802dc PA |
621 | /* Additional Intel-defined flags: level 0x00000007 */ |
622 | if (c->cpuid_level >= 0x00000007) { | |
bdc802dc PA |
623 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); |
624 | ||
39c06df4 | 625 | c->x86_capability[CPUID_7_0_EBX] = ebx; |
2ccd71f1 | 626 | |
39c06df4 | 627 | c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); |
bdc802dc PA |
628 | } |
629 | ||
6229ad27 FY |
630 | /* Extended state features: level 0x0000000d */ |
631 | if (c->cpuid_level >= 0x0000000d) { | |
6229ad27 FY |
632 | cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); |
633 | ||
39c06df4 | 634 | c->x86_capability[CPUID_D_1_EAX] = eax; |
6229ad27 FY |
635 | } |
636 | ||
cbc82b17 PWJ |
637 | /* Additional Intel-defined flags: level 0x0000000F */ |
638 | if (c->cpuid_level >= 0x0000000F) { | |
cbc82b17 PWJ |
639 | |
640 | /* QoS sub-leaf, EAX=0Fh, ECX=0 */ | |
641 | cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); | |
39c06df4 BP |
642 | c->x86_capability[CPUID_F_0_EDX] = edx; |
643 | ||
cbc82b17 PWJ |
644 | if (cpu_has(c, X86_FEATURE_CQM_LLC)) { |
645 | /* will be overridden if occupancy monitoring exists */ | |
646 | c->x86_cache_max_rmid = ebx; | |
647 | ||
648 | /* QoS sub-leaf, EAX=0Fh, ECX=1 */ | |
649 | cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); | |
39c06df4 BP |
650 | c->x86_capability[CPUID_F_1_EDX] = edx; |
651 | ||
33c3cc7a VS |
652 | if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) || |
653 | ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) || | |
654 | (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) { | |
cbc82b17 PWJ |
655 | c->x86_cache_max_rmid = ecx; |
656 | c->x86_cache_occ_scale = ebx; | |
657 | } | |
658 | } else { | |
659 | c->x86_cache_max_rmid = -1; | |
660 | c->x86_cache_occ_scale = -1; | |
661 | } | |
662 | } | |
663 | ||
3da99c97 | 664 | /* AMD-defined flags: level 0x80000001 */ |
39c06df4 BP |
665 | eax = cpuid_eax(0x80000000); |
666 | c->extended_cpuid_level = eax; | |
667 | ||
668 | if ((eax & 0xffff0000) == 0x80000000) { | |
669 | if (eax >= 0x80000001) { | |
670 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
0f3fa48a | 671 | |
39c06df4 BP |
672 | c->x86_capability[CPUID_8000_0001_ECX] = ecx; |
673 | c->x86_capability[CPUID_8000_0001_EDX] = edx; | |
093af8d7 | 674 | } |
093af8d7 | 675 | } |
093af8d7 | 676 | |
5122c890 | 677 | if (c->extended_cpuid_level >= 0x80000008) { |
39c06df4 | 678 | cpuid(0x80000008, &eax, &ebx, &ecx, &edx); |
5122c890 YL |
679 | |
680 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
681 | c->x86_phys_bits = eax & 0xff; | |
39c06df4 | 682 | c->x86_capability[CPUID_8000_0008_EBX] = ebx; |
093af8d7 | 683 | } |
13c6c532 JB |
684 | #ifdef CONFIG_X86_32 |
685 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
686 | c->x86_phys_bits = 36; | |
5122c890 | 687 | #endif |
e3224234 YL |
688 | |
689 | if (c->extended_cpuid_level >= 0x80000007) | |
690 | c->x86_power = cpuid_edx(0x80000007); | |
2ccd71f1 BP |
691 | |
692 | if (c->extended_cpuid_level >= 0x8000000a) | |
39c06df4 | 693 | c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); |
093af8d7 | 694 | |
1dedefd1 | 695 | init_scattered_cpuid_features(c); |
093af8d7 | 696 | } |
1da177e4 | 697 | |
148f9bb8 | 698 | static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
aef93c8b YL |
699 | { |
700 | #ifdef CONFIG_X86_32 | |
701 | int i; | |
702 | ||
703 | /* | |
704 | * First of all, decide if this is a 486 or higher | |
705 | * It's a 486 if we can modify the AC flag | |
706 | */ | |
707 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
708 | c->x86 = 4; | |
709 | else | |
710 | c->x86 = 3; | |
711 | ||
712 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
713 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
714 | c->x86_vendor_id[0] = 0; | |
715 | cpu_devs[i]->c_identify(c); | |
716 | if (c->x86_vendor_id[0]) { | |
717 | get_cpu_vendor(c); | |
718 | break; | |
719 | } | |
720 | } | |
721 | #endif | |
722 | } | |
723 | ||
34048c9e PC |
724 | /* |
725 | * Do minimum CPU detection early. | |
726 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
727 | * cache alignment. | |
728 | * The others are not touched to avoid unwanted side effects. | |
729 | * | |
730 | * WARNING: this function is only called on the BP. Don't add code here | |
731 | * that is supposed to run on all CPUs. | |
732 | */ | |
3da99c97 | 733 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 734 | { |
6627d242 YL |
735 | #ifdef CONFIG_X86_64 |
736 | c->x86_clflush_size = 64; | |
13c6c532 JB |
737 | c->x86_phys_bits = 36; |
738 | c->x86_virt_bits = 48; | |
6627d242 | 739 | #else |
d4387bd3 | 740 | c->x86_clflush_size = 32; |
13c6c532 JB |
741 | c->x86_phys_bits = 32; |
742 | c->x86_virt_bits = 32; | |
6627d242 | 743 | #endif |
0a488a53 | 744 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 745 | |
3da99c97 | 746 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 747 | c->extended_cpuid_level = 0; |
d7cd5611 | 748 | |
aef93c8b YL |
749 | if (!have_cpuid_p()) |
750 | identify_cpu_without_cpuid(c); | |
751 | ||
752 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
753 | if (!have_cpuid_p()) |
754 | return; | |
755 | ||
756 | cpu_detect(c); | |
3da99c97 | 757 | get_cpu_vendor(c); |
3da99c97 | 758 | get_cpu_cap(c); |
12cf105c | 759 | |
10a434fc YL |
760 | if (this_cpu->c_early_init) |
761 | this_cpu->c_early_init(c); | |
093af8d7 | 762 | |
f6e9456c | 763 | c->cpu_index = 0; |
b38b0665 | 764 | filter_cpuid_features(c, false); |
de5397ad | 765 | |
a110b5ec BP |
766 | if (this_cpu->c_bsp_init) |
767 | this_cpu->c_bsp_init(c); | |
c3b83598 BP |
768 | |
769 | setup_force_cpu_cap(X86_FEATURE_ALWAYS); | |
db52ef74 | 770 | fpu__init_system(c); |
d7cd5611 RR |
771 | } |
772 | ||
9d31d35b YL |
773 | void __init early_cpu_init(void) |
774 | { | |
02dde8b4 | 775 | const struct cpu_dev *const *cdev; |
10a434fc YL |
776 | int count = 0; |
777 | ||
ac23f253 | 778 | #ifdef CONFIG_PROCESSOR_SELECT |
1b74dde7 | 779 | pr_info("KERNEL supported cpus:\n"); |
31c997ca IM |
780 | #endif |
781 | ||
10a434fc | 782 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 783 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 784 | |
10a434fc YL |
785 | if (count >= X86_VENDOR_NUM) |
786 | break; | |
787 | cpu_devs[count] = cpudev; | |
788 | count++; | |
789 | ||
ac23f253 | 790 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
791 | { |
792 | unsigned int j; | |
793 | ||
794 | for (j = 0; j < 2; j++) { | |
795 | if (!cpudev->c_ident[j]) | |
796 | continue; | |
1b74dde7 | 797 | pr_info(" %s %s\n", cpudev->c_vendor, |
31c997ca IM |
798 | cpudev->c_ident[j]); |
799 | } | |
10a434fc | 800 | } |
0388423d | 801 | #endif |
10a434fc | 802 | } |
9d31d35b | 803 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 804 | } |
093af8d7 | 805 | |
b6734c35 | 806 | /* |
366d4a43 BP |
807 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; |
808 | * unfortunately, that's not true in practice because of early VIA | |
809 | * chips and (more importantly) broken virtualizers that are not easy | |
810 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
811 | * probing for it doesn't even work. Disable it completely on 32-bit | |
ba0593bf | 812 | * unless we can find a reliable way to detect all the broken cases. |
366d4a43 | 813 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). |
b6734c35 | 814 | */ |
148f9bb8 | 815 | static void detect_nopl(struct cpuinfo_x86 *c) |
b6734c35 | 816 | { |
366d4a43 | 817 | #ifdef CONFIG_X86_32 |
b6734c35 | 818 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
366d4a43 BP |
819 | #else |
820 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
58a5aac5 AL |
821 | #endif |
822 | ||
823 | /* | |
824 | * ESPFIX is a strange bug. All real CPUs have it. Paravirt | |
825 | * systems that run Linux at CPL > 0 may or may not have the | |
826 | * issue, but, even if they have the issue, there's absolutely | |
827 | * nothing we can do about it because we can't use the real IRET | |
828 | * instruction. | |
829 | * | |
830 | * NB: For the time being, only 32-bit kernels support | |
831 | * X86_BUG_ESPFIX as such. 64-bit kernels directly choose | |
832 | * whether to apply espfix using paravirt hooks. If any | |
833 | * non-paravirt system ever shows up that does *not* have the | |
834 | * ESPFIX issue, we can change this. | |
835 | */ | |
836 | #ifdef CONFIG_X86_32 | |
837 | #ifdef CONFIG_PARAVIRT | |
838 | do { | |
839 | extern void native_iret(void); | |
840 | if (pv_cpu_ops.iret == native_iret) | |
841 | set_cpu_bug(c, X86_BUG_ESPFIX); | |
842 | } while (0); | |
843 | #else | |
844 | set_cpu_bug(c, X86_BUG_ESPFIX); | |
845 | #endif | |
366d4a43 | 846 | #endif |
d7cd5611 RR |
847 | } |
848 | ||
148f9bb8 | 849 | static void generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 850 | { |
aef93c8b | 851 | c->extended_cpuid_level = 0; |
1da177e4 | 852 | |
3da99c97 | 853 | if (!have_cpuid_p()) |
aef93c8b | 854 | identify_cpu_without_cpuid(c); |
1d67953f | 855 | |
aef93c8b | 856 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 857 | if (!have_cpuid_p()) |
aef93c8b | 858 | return; |
1da177e4 | 859 | |
3da99c97 | 860 | cpu_detect(c); |
1da177e4 | 861 | |
3da99c97 | 862 | get_cpu_vendor(c); |
1da177e4 | 863 | |
3da99c97 | 864 | get_cpu_cap(c); |
1da177e4 | 865 | |
3da99c97 YL |
866 | if (c->cpuid_level >= 0x00000001) { |
867 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e | 868 | #ifdef CONFIG_X86_32 |
c8e56d20 | 869 | # ifdef CONFIG_SMP |
cb8cc442 | 870 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 871 | # else |
3da99c97 | 872 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
873 | # endif |
874 | #endif | |
b89d3b3e | 875 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 876 | } |
1da177e4 | 877 | |
1b05d60d | 878 | get_model_name(c); /* Default name */ |
1da177e4 | 879 | |
3da99c97 | 880 | detect_nopl(c); |
1da177e4 | 881 | } |
1da177e4 | 882 | |
cbc82b17 PWJ |
883 | static void x86_init_cache_qos(struct cpuinfo_x86 *c) |
884 | { | |
885 | /* | |
886 | * The heavy lifting of max_rmid and cache_occ_scale are handled | |
887 | * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu | |
888 | * in case CQM bits really aren't there in this CPU. | |
889 | */ | |
890 | if (c != &boot_cpu_data) { | |
891 | boot_cpu_data.x86_cache_max_rmid = | |
892 | min(boot_cpu_data.x86_cache_max_rmid, | |
893 | c->x86_cache_max_rmid); | |
894 | } | |
895 | } | |
896 | ||
1da177e4 LT |
897 | /* |
898 | * This does the hard work of actually picking apart the CPU stuff... | |
899 | */ | |
148f9bb8 | 900 | static void identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
901 | { |
902 | int i; | |
903 | ||
904 | c->loops_per_jiffy = loops_per_jiffy; | |
905 | c->x86_cache_size = -1; | |
906 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
907 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
908 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
909 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 910 | c->x86_max_cores = 1; |
102bbe3a | 911 | c->x86_coreid_bits = 0; |
11fdd252 | 912 | #ifdef CONFIG_X86_64 |
102bbe3a | 913 | c->x86_clflush_size = 64; |
13c6c532 JB |
914 | c->x86_phys_bits = 36; |
915 | c->x86_virt_bits = 48; | |
102bbe3a YL |
916 | #else |
917 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 918 | c->x86_clflush_size = 32; |
13c6c532 JB |
919 | c->x86_phys_bits = 32; |
920 | c->x86_virt_bits = 32; | |
102bbe3a YL |
921 | #endif |
922 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
923 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
924 | ||
1da177e4 LT |
925 | generic_identify(c); |
926 | ||
3898534d | 927 | if (this_cpu->c_identify) |
1da177e4 LT |
928 | this_cpu->c_identify(c); |
929 | ||
6a6256f9 | 930 | /* Clear/Set all flags overridden by options, after probe */ |
2759c328 YL |
931 | for (i = 0; i < NCAPINTS; i++) { |
932 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
933 | c->x86_capability[i] |= cpu_caps_set[i]; | |
934 | } | |
935 | ||
102bbe3a | 936 | #ifdef CONFIG_X86_64 |
cb8cc442 | 937 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
938 | #endif |
939 | ||
1da177e4 LT |
940 | /* |
941 | * Vendor-specific initialization. In this section we | |
942 | * canonicalize the feature flags, meaning if there are | |
943 | * features a certain CPU supports which CPUID doesn't | |
944 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
945 | * we handle them here. | |
946 | * | |
947 | * At the end of this section, c->x86_capability better | |
948 | * indicate the features this CPU genuinely supports! | |
949 | */ | |
950 | if (this_cpu->c_init) | |
951 | this_cpu->c_init(c); | |
952 | ||
953 | /* Disable the PN if appropriate */ | |
954 | squash_the_stupid_serial_number(c); | |
955 | ||
b2cc2a07 PA |
956 | /* Set up SMEP/SMAP */ |
957 | setup_smep(c); | |
958 | setup_smap(c); | |
959 | ||
1da177e4 | 960 | /* |
0f3fa48a IM |
961 | * The vendor-specific functions might have changed features. |
962 | * Now we do "generic changes." | |
1da177e4 LT |
963 | */ |
964 | ||
b38b0665 PA |
965 | /* Filter out anything that depends on CPUID levels we don't have */ |
966 | filter_cpuid_features(c, true); | |
967 | ||
1da177e4 | 968 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 969 | if (!c->x86_model_id[0]) { |
02dde8b4 | 970 | const char *p; |
1da177e4 | 971 | p = table_lookup_model(c); |
34048c9e | 972 | if (p) |
1da177e4 LT |
973 | strcpy(c->x86_model_id, p); |
974 | else | |
975 | /* Last resort... */ | |
976 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 977 | c->x86, c->x86_model); |
1da177e4 LT |
978 | } |
979 | ||
102bbe3a YL |
980 | #ifdef CONFIG_X86_64 |
981 | detect_ht(c); | |
982 | #endif | |
983 | ||
88b094fb | 984 | init_hypervisor(c); |
49d859d7 | 985 | x86_init_rdrand(c); |
cbc82b17 | 986 | x86_init_cache_qos(c); |
3e0c3737 YL |
987 | |
988 | /* | |
6a6256f9 | 989 | * Clear/Set all flags overridden by options, need do it |
3e0c3737 YL |
990 | * before following smp all cpus cap AND. |
991 | */ | |
992 | for (i = 0; i < NCAPINTS; i++) { | |
993 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
994 | c->x86_capability[i] |= cpu_caps_set[i]; | |
995 | } | |
996 | ||
1da177e4 LT |
997 | /* |
998 | * On SMP, boot_cpu_data holds the common feature set between | |
999 | * all CPUs; so make sure that we indicate which features are | |
1000 | * common between the CPUs. The first time this routine gets | |
1001 | * executed, c == &boot_cpu_data. | |
1002 | */ | |
34048c9e | 1003 | if (c != &boot_cpu_data) { |
1da177e4 | 1004 | /* AND the already accumulated flags with these */ |
9d31d35b | 1005 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 | 1006 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
65fc985b BP |
1007 | |
1008 | /* OR, i.e. replicate the bug flags */ | |
1009 | for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) | |
1010 | c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; | |
1da177e4 LT |
1011 | } |
1012 | ||
1013 | /* Init Machine Check Exception if available. */ | |
5e09954a | 1014 | mcheck_cpu_init(c); |
30d432df AK |
1015 | |
1016 | select_idle_routine(c); | |
102bbe3a | 1017 | |
de2d9445 | 1018 | #ifdef CONFIG_NUMA |
102bbe3a YL |
1019 | numa_add_cpu(smp_processor_id()); |
1020 | #endif | |
1f12e32f TG |
1021 | /* The boot/hotplug time assigment got cleared, restore it */ |
1022 | c->logical_proc_id = topology_phys_to_logical_pkg(c->phys_proc_id); | |
a6c4e076 | 1023 | } |
31ab269a | 1024 | |
8b6c0ab1 IM |
1025 | /* |
1026 | * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions | |
1027 | * on 32-bit kernels: | |
1028 | */ | |
cfda7bb9 AL |
1029 | #ifdef CONFIG_X86_32 |
1030 | void enable_sep_cpu(void) | |
1031 | { | |
8b6c0ab1 IM |
1032 | struct tss_struct *tss; |
1033 | int cpu; | |
cfda7bb9 | 1034 | |
8b6c0ab1 IM |
1035 | cpu = get_cpu(); |
1036 | tss = &per_cpu(cpu_tss, cpu); | |
1037 | ||
1038 | if (!boot_cpu_has(X86_FEATURE_SEP)) | |
1039 | goto out; | |
1040 | ||
1041 | /* | |
cf9328cc AL |
1042 | * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- |
1043 | * see the big comment in struct x86_hw_tss's definition. | |
8b6c0ab1 | 1044 | */ |
cfda7bb9 AL |
1045 | |
1046 | tss->x86_tss.ss1 = __KERNEL_CS; | |
8b6c0ab1 IM |
1047 | wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); |
1048 | ||
cf9328cc AL |
1049 | wrmsr(MSR_IA32_SYSENTER_ESP, |
1050 | (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack), | |
1051 | 0); | |
8b6c0ab1 | 1052 | |
4c8cd0c5 | 1053 | wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); |
8b6c0ab1 IM |
1054 | |
1055 | out: | |
cfda7bb9 AL |
1056 | put_cpu(); |
1057 | } | |
e04d645f GC |
1058 | #endif |
1059 | ||
a6c4e076 JF |
1060 | void __init identify_boot_cpu(void) |
1061 | { | |
1062 | identify_cpu(&boot_cpu_data); | |
02c68a02 | 1063 | init_amd_e400_c1e_mask(); |
102bbe3a | 1064 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1065 | sysenter_setup(); |
6fe940d6 | 1066 | enable_sep_cpu(); |
102bbe3a | 1067 | #endif |
5b556332 | 1068 | cpu_detect_tlb(&boot_cpu_data); |
a6c4e076 | 1069 | } |
3b520b23 | 1070 | |
148f9bb8 | 1071 | void identify_secondary_cpu(struct cpuinfo_x86 *c) |
a6c4e076 JF |
1072 | { |
1073 | BUG_ON(c == &boot_cpu_data); | |
1074 | identify_cpu(c); | |
102bbe3a | 1075 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1076 | enable_sep_cpu(); |
102bbe3a | 1077 | #endif |
a6c4e076 | 1078 | mtrr_ap_init(); |
1da177e4 LT |
1079 | } |
1080 | ||
a0854a46 | 1081 | struct msr_range { |
0f3fa48a IM |
1082 | unsigned min; |
1083 | unsigned max; | |
a0854a46 | 1084 | }; |
1da177e4 | 1085 | |
148f9bb8 | 1086 | static const struct msr_range msr_range_array[] = { |
a0854a46 YL |
1087 | { 0x00000000, 0x00000418}, |
1088 | { 0xc0000000, 0xc000040b}, | |
1089 | { 0xc0010000, 0xc0010142}, | |
1090 | { 0xc0011000, 0xc001103b}, | |
1091 | }; | |
1da177e4 | 1092 | |
148f9bb8 | 1093 | static void __print_cpu_msr(void) |
a0854a46 | 1094 | { |
0f3fa48a | 1095 | unsigned index_min, index_max; |
a0854a46 YL |
1096 | unsigned index; |
1097 | u64 val; | |
1098 | int i; | |
a0854a46 YL |
1099 | |
1100 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
1101 | index_min = msr_range_array[i].min; | |
1102 | index_max = msr_range_array[i].max; | |
0f3fa48a | 1103 | |
a0854a46 | 1104 | for (index = index_min; index < index_max; index++) { |
ecd431d9 | 1105 | if (rdmsrl_safe(index, &val)) |
a0854a46 | 1106 | continue; |
1b74dde7 | 1107 | pr_info(" MSR%08x: %016llx\n", index, val); |
1da177e4 | 1108 | } |
a0854a46 YL |
1109 | } |
1110 | } | |
94605eff | 1111 | |
148f9bb8 | 1112 | static int show_msr; |
0f3fa48a | 1113 | |
a0854a46 YL |
1114 | static __init int setup_show_msr(char *arg) |
1115 | { | |
1116 | int num; | |
3dd9d514 | 1117 | |
a0854a46 | 1118 | get_option(&arg, &num); |
3dd9d514 | 1119 | |
a0854a46 YL |
1120 | if (num > 0) |
1121 | show_msr = num; | |
1122 | return 1; | |
1da177e4 | 1123 | } |
a0854a46 | 1124 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 1125 | |
191679fd AK |
1126 | static __init int setup_noclflush(char *arg) |
1127 | { | |
840d2830 | 1128 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); |
da4aaa7d | 1129 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); |
191679fd AK |
1130 | return 1; |
1131 | } | |
1132 | __setup("noclflush", setup_noclflush); | |
1133 | ||
148f9bb8 | 1134 | void print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1135 | { |
02dde8b4 | 1136 | const char *vendor = NULL; |
1da177e4 | 1137 | |
0f3fa48a | 1138 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1139 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1140 | } else { |
1141 | if (c->cpuid_level >= 0) | |
1142 | vendor = c->x86_vendor_id; | |
1143 | } | |
1da177e4 | 1144 | |
bd32a8cf | 1145 | if (vendor && !strstr(c->x86_model_id, vendor)) |
1b74dde7 | 1146 | pr_cont("%s ", vendor); |
1da177e4 | 1147 | |
9d31d35b | 1148 | if (c->x86_model_id[0]) |
1b74dde7 | 1149 | pr_cont("%s", c->x86_model_id); |
1da177e4 | 1150 | else |
1b74dde7 | 1151 | pr_cont("%d86", c->x86); |
1da177e4 | 1152 | |
1b74dde7 | 1153 | pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); |
924e101a | 1154 | |
34048c9e | 1155 | if (c->x86_mask || c->cpuid_level >= 0) |
1b74dde7 | 1156 | pr_cont(", stepping: 0x%x)\n", c->x86_mask); |
1da177e4 | 1157 | else |
1b74dde7 | 1158 | pr_cont(")\n"); |
a0854a46 | 1159 | |
0b8b8078 | 1160 | print_cpu_msr(c); |
21c3fcf3 YL |
1161 | } |
1162 | ||
148f9bb8 | 1163 | void print_cpu_msr(struct cpuinfo_x86 *c) |
21c3fcf3 | 1164 | { |
a0854a46 | 1165 | if (c->cpu_index < show_msr) |
21c3fcf3 | 1166 | __print_cpu_msr(); |
1da177e4 LT |
1167 | } |
1168 | ||
ac72e788 AK |
1169 | static __init int setup_disablecpuid(char *arg) |
1170 | { | |
1171 | int bit; | |
0f3fa48a | 1172 | |
ac72e788 AK |
1173 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) |
1174 | setup_clear_cpu_cap(bit); | |
1175 | else | |
1176 | return 0; | |
0f3fa48a | 1177 | |
ac72e788 AK |
1178 | return 1; |
1179 | } | |
1180 | __setup("clearcpuid=", setup_disablecpuid); | |
1181 | ||
d5494d4f | 1182 | #ifdef CONFIG_X86_64 |
9ff80942 | 1183 | struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; |
629f4f9d SA |
1184 | struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1, |
1185 | (unsigned long) debug_idt_table }; | |
d5494d4f | 1186 | |
947e76cd | 1187 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
277d5b40 | 1188 | irq_stack_union) __aligned(PAGE_SIZE) __visible; |
0f3fa48a | 1189 | |
bdf977b3 | 1190 | /* |
a7fcf28d AL |
1191 | * The following percpu variables are hot. Align current_task to |
1192 | * cacheline size such that they fall in the same cacheline. | |
bdf977b3 TH |
1193 | */ |
1194 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1195 | &init_task; | |
1196 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1197 | |
bdf977b3 TH |
1198 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
1199 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; | |
1200 | ||
277d5b40 | 1201 | DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; |
d5494d4f | 1202 | |
c2daa3be PZ |
1203 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1204 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
1205 | ||
0f3fa48a IM |
1206 | /* |
1207 | * Special IST stacks which the CPU switches to when it calls | |
1208 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
1209 | * limit), all of them are 4K, except the debug stack which | |
1210 | * is 8K. | |
1211 | */ | |
1212 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
1213 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1214 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1215 | }; | |
1216 | ||
92d65b23 | 1217 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
3e352aa8 | 1218 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); |
d5494d4f | 1219 | |
d5494d4f YL |
1220 | /* May not be marked __init: used by software suspend */ |
1221 | void syscall_init(void) | |
1da177e4 | 1222 | { |
d5494d4f YL |
1223 | /* |
1224 | * LSTAR and STAR live in a bit strange symbiosis. | |
1225 | * They both write to the same internal register. STAR allows to | |
1226 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
1227 | */ | |
31ac34ca | 1228 | wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); |
47edb651 | 1229 | wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); |
d56fe4bf IM |
1230 | |
1231 | #ifdef CONFIG_IA32_EMULATION | |
47edb651 | 1232 | wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); |
a76c7f46 | 1233 | /* |
487d1edb DV |
1234 | * This only works on Intel CPUs. |
1235 | * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. | |
1236 | * This does not cause SYSENTER to jump to the wrong location, because | |
1237 | * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). | |
a76c7f46 DV |
1238 | */ |
1239 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); | |
1240 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); | |
4c8cd0c5 | 1241 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); |
d56fe4bf | 1242 | #else |
47edb651 | 1243 | wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); |
6b51311c | 1244 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); |
d56fe4bf IM |
1245 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); |
1246 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); | |
d5494d4f | 1247 | #endif |
03ae5768 | 1248 | |
d5494d4f YL |
1249 | /* Flags to clear on syscall */ |
1250 | wrmsrl(MSR_SYSCALL_MASK, | |
63bcff2a | 1251 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| |
8c7aa698 | 1252 | X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); |
1da177e4 | 1253 | } |
62111195 | 1254 | |
d5494d4f YL |
1255 | /* |
1256 | * Copies of the original ist values from the tss are only accessed during | |
1257 | * debugging, no special alignment required. | |
1258 | */ | |
1259 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1260 | ||
228bdaa9 | 1261 | static DEFINE_PER_CPU(unsigned long, debug_stack_addr); |
42181186 | 1262 | DEFINE_PER_CPU(int, debug_stack_usage); |
228bdaa9 SR |
1263 | |
1264 | int is_debug_stack(unsigned long addr) | |
1265 | { | |
89cbc767 CL |
1266 | return __this_cpu_read(debug_stack_usage) || |
1267 | (addr <= __this_cpu_read(debug_stack_addr) && | |
1268 | addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); | |
228bdaa9 | 1269 | } |
0f46efeb | 1270 | NOKPROBE_SYMBOL(is_debug_stack); |
228bdaa9 | 1271 | |
629f4f9d | 1272 | DEFINE_PER_CPU(u32, debug_idt_ctr); |
f8988175 | 1273 | |
228bdaa9 SR |
1274 | void debug_stack_set_zero(void) |
1275 | { | |
629f4f9d SA |
1276 | this_cpu_inc(debug_idt_ctr); |
1277 | load_current_idt(); | |
228bdaa9 | 1278 | } |
0f46efeb | 1279 | NOKPROBE_SYMBOL(debug_stack_set_zero); |
228bdaa9 SR |
1280 | |
1281 | void debug_stack_reset(void) | |
1282 | { | |
629f4f9d | 1283 | if (WARN_ON(!this_cpu_read(debug_idt_ctr))) |
f8988175 | 1284 | return; |
629f4f9d SA |
1285 | if (this_cpu_dec_return(debug_idt_ctr) == 0) |
1286 | load_current_idt(); | |
228bdaa9 | 1287 | } |
0f46efeb | 1288 | NOKPROBE_SYMBOL(debug_stack_reset); |
228bdaa9 | 1289 | |
0f3fa48a | 1290 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1291 | |
bdf977b3 TH |
1292 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1293 | EXPORT_PER_CPU_SYMBOL(current_task); | |
c2daa3be PZ |
1294 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1295 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
bdf977b3 | 1296 | |
a7fcf28d AL |
1297 | /* |
1298 | * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find | |
1299 | * the top of the kernel stack. Use an extra percpu variable to track the | |
1300 | * top of the kernel stack directly. | |
1301 | */ | |
1302 | DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = | |
1303 | (unsigned long)&init_thread_union + THREAD_SIZE; | |
1304 | EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); | |
1305 | ||
60a5317f | 1306 | #ifdef CONFIG_CC_STACKPROTECTOR |
53f82452 | 1307 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1308 | #endif |
d5494d4f | 1309 | |
0f3fa48a | 1310 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1311 | |
9766cdbc JSR |
1312 | /* |
1313 | * Clear all 6 debug registers: | |
1314 | */ | |
1315 | static void clear_all_debug_regs(void) | |
1316 | { | |
1317 | int i; | |
1318 | ||
1319 | for (i = 0; i < 8; i++) { | |
1320 | /* Ignore db4, db5 */ | |
1321 | if ((i == 4) || (i == 5)) | |
1322 | continue; | |
1323 | ||
1324 | set_debugreg(0, i); | |
1325 | } | |
1326 | } | |
c5413fbe | 1327 | |
0bb9fef9 JW |
1328 | #ifdef CONFIG_KGDB |
1329 | /* | |
1330 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1331 | * connection established. | |
1332 | */ | |
1333 | static void dbg_restore_debug_regs(void) | |
1334 | { | |
1335 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1336 | arch_kgdb_ops.correct_hw_break(); | |
1337 | } | |
1338 | #else /* ! CONFIG_KGDB */ | |
1339 | #define dbg_restore_debug_regs() | |
1340 | #endif /* ! CONFIG_KGDB */ | |
1341 | ||
ce4b1b16 IM |
1342 | static void wait_for_master_cpu(int cpu) |
1343 | { | |
1344 | #ifdef CONFIG_SMP | |
1345 | /* | |
1346 | * wait for ACK from master CPU before continuing | |
1347 | * with AP initialization | |
1348 | */ | |
1349 | WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); | |
1350 | while (!cpumask_test_cpu(cpu, cpu_callout_mask)) | |
1351 | cpu_relax(); | |
1352 | #endif | |
1353 | } | |
1354 | ||
d2cbcc49 RR |
1355 | /* |
1356 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1357 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1358 | * and IDT. We reload them nevertheless, this function acts as a | |
1359 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1360 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1361 | */ |
1ba76586 | 1362 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1363 | |
148f9bb8 | 1364 | void cpu_init(void) |
1ba76586 | 1365 | { |
0fe1e009 | 1366 | struct orig_ist *oist; |
1ba76586 | 1367 | struct task_struct *me; |
0f3fa48a IM |
1368 | struct tss_struct *t; |
1369 | unsigned long v; | |
ce4b1b16 | 1370 | int cpu = stack_smp_processor_id(); |
1ba76586 YL |
1371 | int i; |
1372 | ||
ce4b1b16 IM |
1373 | wait_for_master_cpu(cpu); |
1374 | ||
1e02ce4c AL |
1375 | /* |
1376 | * Initialize the CR4 shadow before doing anything that could | |
1377 | * try to read it. | |
1378 | */ | |
1379 | cr4_init_shadow(); | |
1380 | ||
e6ebf5de FY |
1381 | /* |
1382 | * Load microcode on this cpu if a valid microcode is available. | |
1383 | * This is early microcode loading procedure. | |
1384 | */ | |
1385 | load_ucode_ap(); | |
1386 | ||
24933b82 | 1387 | t = &per_cpu(cpu_tss, cpu); |
0fe1e009 | 1388 | oist = &per_cpu(orig_ist, cpu); |
0f3fa48a | 1389 | |
e7a22c1e | 1390 | #ifdef CONFIG_NUMA |
27fd185f | 1391 | if (this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
1392 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
1393 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1394 | #endif |
1ba76586 YL |
1395 | |
1396 | me = current; | |
1397 | ||
2eaad1fd | 1398 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 | 1399 | |
375074cc | 1400 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
1ba76586 YL |
1401 | |
1402 | /* | |
1403 | * Initialize the per-CPU GDT with the boot GDT, | |
1404 | * and set up the GDT descriptor: | |
1405 | */ | |
1406 | ||
552be871 | 1407 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1408 | loadsegment(fs, 0); |
1409 | ||
cf910e83 | 1410 | load_current_idt(); |
1ba76586 YL |
1411 | |
1412 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1413 | syscall_init(); | |
1414 | ||
1415 | wrmsrl(MSR_FS_BASE, 0); | |
1416 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1417 | barrier(); | |
1418 | ||
4763ed4d | 1419 | x86_configure_nx(); |
659006bf | 1420 | x2apic_setup(); |
1ba76586 YL |
1421 | |
1422 | /* | |
1423 | * set up and load the per-CPU TSS | |
1424 | */ | |
0fe1e009 | 1425 | if (!oist->ist[0]) { |
92d65b23 | 1426 | char *estacks = per_cpu(exception_stacks, cpu); |
0f3fa48a | 1427 | |
1ba76586 | 1428 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
0f3fa48a | 1429 | estacks += exception_stack_sizes[v]; |
0fe1e009 | 1430 | oist->ist[v] = t->x86_tss.ist[v] = |
1ba76586 | 1431 | (unsigned long)estacks; |
228bdaa9 SR |
1432 | if (v == DEBUG_STACK-1) |
1433 | per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; | |
1ba76586 YL |
1434 | } |
1435 | } | |
1436 | ||
1437 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
0f3fa48a | 1438 | |
1ba76586 YL |
1439 | /* |
1440 | * <= is required because the CPU will access up to | |
1441 | * 8 bits beyond the end of the IO permission bitmap. | |
1442 | */ | |
1443 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1444 | t->io_bitmap[i] = ~0UL; | |
1445 | ||
1446 | atomic_inc(&init_mm.mm_count); | |
1447 | me->active_mm = &init_mm; | |
8c5dfd25 | 1448 | BUG_ON(me->mm); |
1ba76586 YL |
1449 | enter_lazy_tlb(&init_mm, me); |
1450 | ||
1451 | load_sp0(t, ¤t->thread); | |
1452 | set_tss_desc(cpu, t); | |
1453 | load_TR_desc(); | |
37868fe1 | 1454 | load_mm_ldt(&init_mm); |
1ba76586 | 1455 | |
0bb9fef9 JW |
1456 | clear_all_debug_regs(); |
1457 | dbg_restore_debug_regs(); | |
1ba76586 | 1458 | |
21c4cd10 | 1459 | fpu__init_cpu(); |
1ba76586 | 1460 | |
1ba76586 YL |
1461 | if (is_uv_system()) |
1462 | uv_cpu_init(); | |
1463 | } | |
1464 | ||
1465 | #else | |
1466 | ||
148f9bb8 | 1467 | void cpu_init(void) |
9ee79a3d | 1468 | { |
d2cbcc49 RR |
1469 | int cpu = smp_processor_id(); |
1470 | struct task_struct *curr = current; | |
24933b82 | 1471 | struct tss_struct *t = &per_cpu(cpu_tss, cpu); |
9ee79a3d | 1472 | struct thread_struct *thread = &curr->thread; |
62111195 | 1473 | |
ce4b1b16 | 1474 | wait_for_master_cpu(cpu); |
e6ebf5de | 1475 | |
5b2bdbc8 SR |
1476 | /* |
1477 | * Initialize the CR4 shadow before doing anything that could | |
1478 | * try to read it. | |
1479 | */ | |
1480 | cr4_init_shadow(); | |
1481 | ||
ce4b1b16 | 1482 | show_ucode_info_early(); |
62111195 | 1483 | |
1b74dde7 | 1484 | pr_info("Initializing CPU#%d\n", cpu); |
62111195 | 1485 | |
362f924b BP |
1486 | if (cpu_feature_enabled(X86_FEATURE_VME) || |
1487 | cpu_has_tsc || | |
1488 | boot_cpu_has(X86_FEATURE_DE)) | |
375074cc | 1489 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
62111195 | 1490 | |
cf910e83 | 1491 | load_current_idt(); |
552be871 | 1492 | switch_to_new_gdt(cpu); |
1da177e4 | 1493 | |
1da177e4 LT |
1494 | /* |
1495 | * Set up and load the per-CPU TSS and LDT | |
1496 | */ | |
1497 | atomic_inc(&init_mm.mm_count); | |
62111195 | 1498 | curr->active_mm = &init_mm; |
8c5dfd25 | 1499 | BUG_ON(curr->mm); |
62111195 | 1500 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1501 | |
faca6227 | 1502 | load_sp0(t, thread); |
34048c9e | 1503 | set_tss_desc(cpu, t); |
1da177e4 | 1504 | load_TR_desc(); |
37868fe1 | 1505 | load_mm_ldt(&init_mm); |
1da177e4 | 1506 | |
f9a196b8 TG |
1507 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); |
1508 | ||
22c4e308 | 1509 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1510 | /* Set up doublefault TSS pointer in the GDT */ |
1511 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1512 | #endif |
1da177e4 | 1513 | |
9766cdbc | 1514 | clear_all_debug_regs(); |
0bb9fef9 | 1515 | dbg_restore_debug_regs(); |
1da177e4 | 1516 | |
21c4cd10 | 1517 | fpu__init_cpu(); |
1da177e4 | 1518 | } |
1ba76586 | 1519 | #endif |
5700f743 | 1520 | |
b51ef52d LA |
1521 | static void bsp_resume(void) |
1522 | { | |
1523 | if (this_cpu->c_bsp_resume) | |
1524 | this_cpu->c_bsp_resume(&boot_cpu_data); | |
1525 | } | |
1526 | ||
1527 | static struct syscore_ops cpu_syscore_ops = { | |
1528 | .resume = bsp_resume, | |
1529 | }; | |
1530 | ||
1531 | static int __init init_cpu_syscore(void) | |
1532 | { | |
1533 | register_syscore_ops(&cpu_syscore_ops); | |
1534 | return 0; | |
1535 | } | |
1536 | core_initcall(init_cpu_syscore); |