]>
Commit | Line | Data |
---|---|---|
f0fc4aff | 1 | #include <linux/bootmem.h> |
9766cdbc | 2 | #include <linux/linkage.h> |
f0fc4aff | 3 | #include <linux/bitops.h> |
9766cdbc | 4 | #include <linux/kernel.h> |
f0fc4aff | 5 | #include <linux/module.h> |
9766cdbc JSR |
6 | #include <linux/percpu.h> |
7 | #include <linux/string.h> | |
1da177e4 | 8 | #include <linux/delay.h> |
9766cdbc JSR |
9 | #include <linux/sched.h> |
10 | #include <linux/init.h> | |
11 | #include <linux/kgdb.h> | |
1da177e4 | 12 | #include <linux/smp.h> |
9766cdbc JSR |
13 | #include <linux/io.h> |
14 | ||
15 | #include <asm/stackprotector.h> | |
cdd6c482 | 16 | #include <asm/perf_event.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
49d859d7 | 18 | #include <asm/archrandom.h> |
9766cdbc JSR |
19 | #include <asm/hypervisor.h> |
20 | #include <asm/processor.h> | |
f649e938 | 21 | #include <asm/debugreg.h> |
9766cdbc | 22 | #include <asm/sections.h> |
8bdbd962 AC |
23 | #include <linux/topology.h> |
24 | #include <linux/cpumask.h> | |
9766cdbc | 25 | #include <asm/pgtable.h> |
60063497 | 26 | #include <linux/atomic.h> |
9766cdbc JSR |
27 | #include <asm/proto.h> |
28 | #include <asm/setup.h> | |
29 | #include <asm/apic.h> | |
30 | #include <asm/desc.h> | |
31 | #include <asm/i387.h> | |
1361b83a | 32 | #include <asm/fpu-internal.h> |
27b07da7 | 33 | #include <asm/mtrr.h> |
8bdbd962 | 34 | #include <linux/numa.h> |
9766cdbc JSR |
35 | #include <asm/asm.h> |
36 | #include <asm/cpu.h> | |
a03a3e28 | 37 | #include <asm/mce.h> |
9766cdbc | 38 | #include <asm/msr.h> |
8d4a4300 | 39 | #include <asm/pat.h> |
d288e1cf FY |
40 | #include <asm/microcode.h> |
41 | #include <asm/microcode_intel.h> | |
e641f5f5 IM |
42 | |
43 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 44 | #include <asm/uv/uv.h> |
1da177e4 LT |
45 | #endif |
46 | ||
47 | #include "cpu.h" | |
48 | ||
c2d1cec1 | 49 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 50 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
51 | cpumask_var_t cpu_callout_mask; |
52 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
53 | |
54 | /* representing cpus for which sibling maps can be computed */ | |
55 | cpumask_var_t cpu_sibling_setup_mask; | |
56 | ||
2f2f52ba | 57 | /* correctly size the local cpu masks */ |
4369f1fb | 58 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
59 | { |
60 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
61 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
62 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
63 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
64 | } | |
65 | ||
148f9bb8 | 66 | static void default_init(struct cpuinfo_x86 *c) |
e8055139 OZ |
67 | { |
68 | #ifdef CONFIG_X86_64 | |
27c13ece | 69 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
70 | #else |
71 | /* Not much we can do here... */ | |
72 | /* Check if at least it has cpuid */ | |
73 | if (c->cpuid_level == -1) { | |
74 | /* No cpuid. It must be an ancient CPU */ | |
75 | if (c->x86 == 4) | |
76 | strcpy(c->x86_model_id, "486"); | |
77 | else if (c->x86 == 3) | |
78 | strcpy(c->x86_model_id, "386"); | |
79 | } | |
80 | #endif | |
81 | } | |
82 | ||
148f9bb8 | 83 | static const struct cpu_dev default_cpu = { |
e8055139 OZ |
84 | .c_init = default_init, |
85 | .c_vendor = "Unknown", | |
86 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
87 | }; | |
88 | ||
148f9bb8 | 89 | static const struct cpu_dev *this_cpu = &default_cpu; |
0a488a53 | 90 | |
06deef89 | 91 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 92 | #ifdef CONFIG_X86_64 |
06deef89 BG |
93 | /* |
94 | * We need valid kernel segments for data and code in long mode too | |
95 | * IRET will check the segment types kkeil 2000/10/28 | |
96 | * Also sysret mandates a special GDT layout | |
97 | * | |
9766cdbc | 98 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
99 | * Hopefully nobody expects them at a fixed place (Wine?) |
100 | */ | |
1e5de182 AM |
101 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
102 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
103 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
104 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
105 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
106 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 107 | #else |
1e5de182 AM |
108 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
109 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
110 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
111 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
112 | /* |
113 | * Segments used for calling PnP BIOS have byte granularity. | |
114 | * They code segments and data segments have fixed 64k limits, | |
115 | * the transfer segment sizes are set at run time. | |
116 | */ | |
6842ef0e | 117 | /* 32-bit code */ |
1e5de182 | 118 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 119 | /* 16-bit code */ |
1e5de182 | 120 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 121 | /* 16-bit data */ |
1e5de182 | 122 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 123 | /* 16-bit data */ |
1e5de182 | 124 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 125 | /* 16-bit data */ |
1e5de182 | 126 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
127 | /* |
128 | * The APM segments have byte granularity and their bases | |
129 | * are set at run time. All have 64k limits. | |
130 | */ | |
6842ef0e | 131 | /* 32-bit code */ |
1e5de182 | 132 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 133 | /* 16-bit code */ |
1e5de182 | 134 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 135 | /* data */ |
72c4d853 | 136 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 137 | |
1e5de182 AM |
138 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
139 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 140 | GDT_STACK_CANARY_INIT |
950ad7ff | 141 | #endif |
06deef89 | 142 | } }; |
7a61d35d | 143 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 144 | |
0c752a93 SS |
145 | static int __init x86_xsave_setup(char *s) |
146 | { | |
147 | setup_clear_cpu_cap(X86_FEATURE_XSAVE); | |
6bad06b7 | 148 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); |
c6fd893d SS |
149 | setup_clear_cpu_cap(X86_FEATURE_AVX); |
150 | setup_clear_cpu_cap(X86_FEATURE_AVX2); | |
0c752a93 SS |
151 | return 1; |
152 | } | |
153 | __setup("noxsave", x86_xsave_setup); | |
154 | ||
6bad06b7 SS |
155 | static int __init x86_xsaveopt_setup(char *s) |
156 | { | |
157 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); | |
158 | return 1; | |
159 | } | |
160 | __setup("noxsaveopt", x86_xsaveopt_setup); | |
161 | ||
ba51dced | 162 | #ifdef CONFIG_X86_32 |
148f9bb8 PG |
163 | static int cachesize_override = -1; |
164 | static int disable_x86_serial_nr = 1; | |
1da177e4 | 165 | |
0a488a53 YL |
166 | static int __init cachesize_setup(char *str) |
167 | { | |
168 | get_option(&str, &cachesize_override); | |
169 | return 1; | |
170 | } | |
171 | __setup("cachesize=", cachesize_setup); | |
172 | ||
0a488a53 YL |
173 | static int __init x86_fxsr_setup(char *s) |
174 | { | |
175 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
176 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
177 | return 1; | |
178 | } | |
179 | __setup("nofxsr", x86_fxsr_setup); | |
180 | ||
181 | static int __init x86_sep_setup(char *s) | |
182 | { | |
183 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
184 | return 1; | |
185 | } | |
186 | __setup("nosep", x86_sep_setup); | |
187 | ||
188 | /* Standard macro to see if a specific flag is changeable */ | |
189 | static inline int flag_is_changeable_p(u32 flag) | |
190 | { | |
191 | u32 f1, f2; | |
192 | ||
94f6bac1 KH |
193 | /* |
194 | * Cyrix and IDT cpus allow disabling of CPUID | |
195 | * so the code below may return different results | |
196 | * when it is executed before and after enabling | |
197 | * the CPUID. Add "volatile" to not allow gcc to | |
198 | * optimize the subsequent calls to this function. | |
199 | */ | |
0f3fa48a IM |
200 | asm volatile ("pushfl \n\t" |
201 | "pushfl \n\t" | |
202 | "popl %0 \n\t" | |
203 | "movl %0, %1 \n\t" | |
204 | "xorl %2, %0 \n\t" | |
205 | "pushl %0 \n\t" | |
206 | "popfl \n\t" | |
207 | "pushfl \n\t" | |
208 | "popl %0 \n\t" | |
209 | "popfl \n\t" | |
210 | ||
94f6bac1 KH |
211 | : "=&r" (f1), "=&r" (f2) |
212 | : "ir" (flag)); | |
0a488a53 YL |
213 | |
214 | return ((f1^f2) & flag) != 0; | |
215 | } | |
216 | ||
217 | /* Probe for the CPUID instruction */ | |
148f9bb8 | 218 | int have_cpuid_p(void) |
0a488a53 YL |
219 | { |
220 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
221 | } | |
222 | ||
148f9bb8 | 223 | static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
0a488a53 | 224 | { |
0f3fa48a IM |
225 | unsigned long lo, hi; |
226 | ||
227 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
228 | return; | |
229 | ||
230 | /* Disable processor serial number: */ | |
231 | ||
232 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
233 | lo |= 0x200000; | |
234 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
235 | ||
236 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
237 | clear_cpu_cap(c, X86_FEATURE_PN); | |
238 | ||
239 | /* Disabling the serial number may affect the cpuid level */ | |
240 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
241 | } |
242 | ||
243 | static int __init x86_serial_nr_setup(char *s) | |
244 | { | |
245 | disable_x86_serial_nr = 0; | |
246 | return 1; | |
247 | } | |
248 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 249 | #else |
102bbe3a YL |
250 | static inline int flag_is_changeable_p(u32 flag) |
251 | { | |
252 | return 1; | |
253 | } | |
102bbe3a YL |
254 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
255 | { | |
256 | } | |
ba51dced | 257 | #endif |
0a488a53 | 258 | |
de5397ad FY |
259 | static __init int setup_disable_smep(char *arg) |
260 | { | |
b2cc2a07 | 261 | setup_clear_cpu_cap(X86_FEATURE_SMEP); |
de5397ad FY |
262 | return 1; |
263 | } | |
264 | __setup("nosmep", setup_disable_smep); | |
265 | ||
b2cc2a07 | 266 | static __always_inline void setup_smep(struct cpuinfo_x86 *c) |
de5397ad | 267 | { |
b2cc2a07 PA |
268 | if (cpu_has(c, X86_FEATURE_SMEP)) |
269 | set_in_cr4(X86_CR4_SMEP); | |
de5397ad FY |
270 | } |
271 | ||
52b6179a PA |
272 | static __init int setup_disable_smap(char *arg) |
273 | { | |
b2cc2a07 | 274 | setup_clear_cpu_cap(X86_FEATURE_SMAP); |
52b6179a PA |
275 | return 1; |
276 | } | |
277 | __setup("nosmap", setup_disable_smap); | |
278 | ||
b2cc2a07 PA |
279 | static __always_inline void setup_smap(struct cpuinfo_x86 *c) |
280 | { | |
281 | unsigned long eflags; | |
282 | ||
283 | /* This should have been cleared long ago */ | |
284 | raw_local_save_flags(eflags); | |
285 | BUG_ON(eflags & X86_EFLAGS_AC); | |
286 | ||
03bbd596 PA |
287 | if (cpu_has(c, X86_FEATURE_SMAP)) { |
288 | #ifdef CONFIG_X86_SMAP | |
b2cc2a07 | 289 | set_in_cr4(X86_CR4_SMAP); |
03bbd596 PA |
290 | #else |
291 | clear_in_cr4(X86_CR4_SMAP); | |
292 | #endif | |
293 | } | |
de5397ad FY |
294 | } |
295 | ||
b38b0665 PA |
296 | /* |
297 | * Some CPU features depend on higher CPUID levels, which may not always | |
298 | * be available due to CPUID level capping or broken virtualization | |
299 | * software. Add those features to this table to auto-disable them. | |
300 | */ | |
301 | struct cpuid_dependent_feature { | |
302 | u32 feature; | |
303 | u32 level; | |
304 | }; | |
0f3fa48a | 305 | |
148f9bb8 | 306 | static const struct cpuid_dependent_feature |
b38b0665 PA |
307 | cpuid_dependent_features[] = { |
308 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
309 | { X86_FEATURE_DCA, 0x00000009 }, | |
310 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
311 | { 0, 0 } | |
312 | }; | |
313 | ||
148f9bb8 | 314 | static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) |
b38b0665 PA |
315 | { |
316 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 317 | |
b38b0665 | 318 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
319 | |
320 | if (!cpu_has(c, df->feature)) | |
321 | continue; | |
b38b0665 PA |
322 | /* |
323 | * Note: cpuid_level is set to -1 if unavailable, but | |
324 | * extended_extended_level is set to 0 if unavailable | |
325 | * and the legitimate extended levels are all negative | |
326 | * when signed; hence the weird messing around with | |
327 | * signs here... | |
328 | */ | |
0f3fa48a | 329 | if (!((s32)df->level < 0 ? |
f6db44df | 330 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
331 | (s32)df->level > (s32)c->cpuid_level)) |
332 | continue; | |
333 | ||
334 | clear_cpu_cap(c, df->feature); | |
335 | if (!warn) | |
336 | continue; | |
337 | ||
338 | printk(KERN_WARNING | |
339 | "CPU: CPU feature %s disabled, no CPUID level 0x%x\n", | |
340 | x86_cap_flags[df->feature], df->level); | |
b38b0665 | 341 | } |
f6db44df | 342 | } |
b38b0665 | 343 | |
102bbe3a YL |
344 | /* |
345 | * Naming convention should be: <Name> [(<Codename>)] | |
346 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
347 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
348 | * isn't used | |
102bbe3a YL |
349 | */ |
350 | ||
351 | /* Look up CPU names by table lookup. */ | |
148f9bb8 | 352 | static const char *table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 353 | { |
09dc68d9 JB |
354 | #ifdef CONFIG_X86_32 |
355 | const struct legacy_cpu_model_info *info; | |
102bbe3a YL |
356 | |
357 | if (c->x86_model >= 16) | |
358 | return NULL; /* Range check */ | |
359 | ||
360 | if (!this_cpu) | |
361 | return NULL; | |
362 | ||
09dc68d9 | 363 | info = this_cpu->legacy_models; |
102bbe3a | 364 | |
09dc68d9 | 365 | while (info->family) { |
102bbe3a YL |
366 | if (info->family == c->x86) |
367 | return info->model_names[c->x86_model]; | |
368 | info++; | |
369 | } | |
09dc68d9 | 370 | #endif |
102bbe3a YL |
371 | return NULL; /* Not found */ |
372 | } | |
373 | ||
148f9bb8 PG |
374 | __u32 cpu_caps_cleared[NCAPINTS]; |
375 | __u32 cpu_caps_set[NCAPINTS]; | |
7d851c8d | 376 | |
11e3a840 JF |
377 | void load_percpu_segment(int cpu) |
378 | { | |
379 | #ifdef CONFIG_X86_32 | |
380 | loadsegment(fs, __KERNEL_PERCPU); | |
381 | #else | |
382 | loadsegment(gs, 0); | |
383 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
384 | #endif | |
60a5317f | 385 | load_stack_canary_segment(); |
11e3a840 JF |
386 | } |
387 | ||
0f3fa48a IM |
388 | /* |
389 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
390 | * it's on the real one. | |
391 | */ | |
552be871 | 392 | void switch_to_new_gdt(int cpu) |
9d31d35b YL |
393 | { |
394 | struct desc_ptr gdt_descr; | |
395 | ||
2697fbd5 | 396 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
397 | gdt_descr.size = GDT_SIZE - 1; |
398 | load_gdt(&gdt_descr); | |
2697fbd5 | 399 | /* Reload the per-cpu base */ |
11e3a840 JF |
400 | |
401 | load_percpu_segment(cpu); | |
9d31d35b YL |
402 | } |
403 | ||
148f9bb8 | 404 | static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 405 | |
148f9bb8 | 406 | static void get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
407 | { |
408 | unsigned int *v; | |
409 | char *p, *q; | |
410 | ||
3da99c97 | 411 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 412 | return; |
1da177e4 | 413 | |
0f3fa48a | 414 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
415 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
416 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
417 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
418 | c->x86_model_id[48] = 0; | |
419 | ||
0f3fa48a IM |
420 | /* |
421 | * Intel chips right-justify this string for some dumb reason; | |
422 | * undo that brain damage: | |
423 | */ | |
1da177e4 | 424 | p = q = &c->x86_model_id[0]; |
34048c9e | 425 | while (*p == ' ') |
9766cdbc | 426 | p++; |
34048c9e | 427 | if (p != q) { |
9766cdbc JSR |
428 | while (*p) |
429 | *q++ = *p++; | |
430 | while (q <= &c->x86_model_id[48]) | |
431 | *q++ = '\0'; /* Zero-pad the rest */ | |
1da177e4 | 432 | } |
1da177e4 LT |
433 | } |
434 | ||
148f9bb8 | 435 | void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 436 | { |
9d31d35b | 437 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 438 | |
3da99c97 | 439 | n = c->extended_cpuid_level; |
1da177e4 LT |
440 | |
441 | if (n >= 0x80000005) { | |
9d31d35b | 442 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 443 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
444 | #ifdef CONFIG_X86_64 |
445 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
446 | c->x86_tlbsize = 0; | |
447 | #endif | |
1da177e4 LT |
448 | } |
449 | ||
450 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
451 | return; | |
452 | ||
0a488a53 | 453 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 454 | l2size = ecx >> 16; |
34048c9e | 455 | |
140fc727 YL |
456 | #ifdef CONFIG_X86_64 |
457 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
458 | #else | |
1da177e4 | 459 | /* do processor-specific cache resizing */ |
09dc68d9 JB |
460 | if (this_cpu->legacy_cache_size) |
461 | l2size = this_cpu->legacy_cache_size(c, l2size); | |
1da177e4 LT |
462 | |
463 | /* Allow user to override all this if necessary. */ | |
464 | if (cachesize_override != -1) | |
465 | l2size = cachesize_override; | |
466 | ||
34048c9e | 467 | if (l2size == 0) |
1da177e4 | 468 | return; /* Again, no L2 cache is possible */ |
140fc727 | 469 | #endif |
1da177e4 LT |
470 | |
471 | c->x86_cache_size = l2size; | |
1da177e4 LT |
472 | } |
473 | ||
e0ba94f1 AS |
474 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
475 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
476 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
477 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
478 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
479 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
dd360393 | 480 | u16 __read_mostly tlb_lld_1g[NR_INFO]; |
e0ba94f1 | 481 | |
c4211f42 AS |
482 | /* |
483 | * tlb_flushall_shift shows the balance point in replacing cr3 write | |
484 | * with multiple 'invlpg'. It will do this replacement when | |
485 | * flush_tlb_lines <= active_lines/2^tlb_flushall_shift. | |
486 | * If tlb_flushall_shift is -1, means the replacement will be disabled. | |
487 | */ | |
488 | s8 __read_mostly tlb_flushall_shift = -1; | |
489 | ||
148f9bb8 | 490 | void cpu_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
491 | { |
492 | if (this_cpu->c_detect_tlb) | |
493 | this_cpu->c_detect_tlb(c); | |
494 | ||
dd360393 KS |
495 | printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" |
496 | "Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n" | |
a9ad773e | 497 | "tlb_flushall_shift: %d\n", |
e0ba94f1 AS |
498 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
499 | tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES], | |
c4211f42 | 500 | tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES], |
dd360393 | 501 | tlb_lld_1g[ENTRIES], tlb_flushall_shift); |
e0ba94f1 AS |
502 | } |
503 | ||
148f9bb8 | 504 | void detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 505 | { |
97e4db7c | 506 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
507 | u32 eax, ebx, ecx, edx; |
508 | int index_msb, core_bits; | |
2eaad1fd | 509 | static bool printed; |
1da177e4 | 510 | |
0a488a53 | 511 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 512 | return; |
1da177e4 | 513 | |
0a488a53 YL |
514 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
515 | goto out; | |
1da177e4 | 516 | |
1cd78776 YL |
517 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
518 | return; | |
1da177e4 | 519 | |
0a488a53 | 520 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 521 | |
9d31d35b YL |
522 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
523 | ||
524 | if (smp_num_siblings == 1) { | |
2eaad1fd | 525 | printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); |
0f3fa48a IM |
526 | goto out; |
527 | } | |
9d31d35b | 528 | |
0f3fa48a IM |
529 | if (smp_num_siblings <= 1) |
530 | goto out; | |
9d31d35b | 531 | |
0f3fa48a IM |
532 | index_msb = get_count_order(smp_num_siblings); |
533 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 534 | |
0f3fa48a | 535 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 536 | |
0f3fa48a | 537 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 538 | |
0f3fa48a | 539 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 540 | |
0f3fa48a IM |
541 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
542 | ((1 << core_bits) - 1); | |
1da177e4 | 543 | |
0a488a53 | 544 | out: |
2eaad1fd | 545 | if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { |
0a488a53 YL |
546 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", |
547 | c->phys_proc_id); | |
548 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
549 | c->cpu_core_id); | |
2eaad1fd | 550 | printed = 1; |
9d31d35b | 551 | } |
9d31d35b | 552 | #endif |
97e4db7c | 553 | } |
1da177e4 | 554 | |
148f9bb8 | 555 | static void get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
556 | { |
557 | char *v = c->x86_vendor_id; | |
0f3fa48a | 558 | int i; |
1da177e4 LT |
559 | |
560 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
561 | if (!cpu_devs[i]) |
562 | break; | |
563 | ||
564 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
565 | (cpu_devs[i]->c_ident[1] && | |
566 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 567 | |
10a434fc YL |
568 | this_cpu = cpu_devs[i]; |
569 | c->x86_vendor = this_cpu->c_x86_vendor; | |
570 | return; | |
1da177e4 LT |
571 | } |
572 | } | |
10a434fc | 573 | |
a9c56953 MK |
574 | printk_once(KERN_ERR |
575 | "CPU: vendor_id '%s' unknown, using generic init.\n" \ | |
576 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 577 | |
fe38d855 CE |
578 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
579 | this_cpu = &default_cpu; | |
1da177e4 LT |
580 | } |
581 | ||
148f9bb8 | 582 | void cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 583 | { |
1da177e4 | 584 | /* Get vendor name */ |
4a148513 HH |
585 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
586 | (unsigned int *)&c->x86_vendor_id[0], | |
587 | (unsigned int *)&c->x86_vendor_id[8], | |
588 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 589 | |
1da177e4 | 590 | c->x86 = 4; |
9d31d35b | 591 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
592 | if (c->cpuid_level >= 0x00000001) { |
593 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 594 | |
1da177e4 | 595 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
9d31d35b YL |
596 | c->x86 = (tfms >> 8) & 0xf; |
597 | c->x86_model = (tfms >> 4) & 0xf; | |
598 | c->x86_mask = tfms & 0xf; | |
0f3fa48a | 599 | |
f5f786d0 | 600 | if (c->x86 == 0xf) |
1da177e4 | 601 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 602 | if (c->x86 >= 0x6) |
9d31d35b | 603 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
0f3fa48a | 604 | |
d4387bd3 | 605 | if (cap0 & (1<<19)) { |
d4387bd3 | 606 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 607 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 608 | } |
1da177e4 | 609 | } |
1da177e4 | 610 | } |
3da99c97 | 611 | |
148f9bb8 | 612 | void get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 YL |
613 | { |
614 | u32 tfms, xlvl; | |
3da99c97 | 615 | u32 ebx; |
093af8d7 | 616 | |
3da99c97 YL |
617 | /* Intel-defined flags: level 0x00000001 */ |
618 | if (c->cpuid_level >= 0x00000001) { | |
619 | u32 capability, excap; | |
0f3fa48a | 620 | |
3da99c97 YL |
621 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); |
622 | c->x86_capability[0] = capability; | |
623 | c->x86_capability[4] = excap; | |
624 | } | |
093af8d7 | 625 | |
bdc802dc PA |
626 | /* Additional Intel-defined flags: level 0x00000007 */ |
627 | if (c->cpuid_level >= 0x00000007) { | |
628 | u32 eax, ebx, ecx, edx; | |
629 | ||
630 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); | |
631 | ||
2494b030 | 632 | c->x86_capability[9] = ebx; |
bdc802dc PA |
633 | } |
634 | ||
3da99c97 YL |
635 | /* AMD-defined flags: level 0x80000001 */ |
636 | xlvl = cpuid_eax(0x80000000); | |
637 | c->extended_cpuid_level = xlvl; | |
0f3fa48a | 638 | |
3da99c97 YL |
639 | if ((xlvl & 0xffff0000) == 0x80000000) { |
640 | if (xlvl >= 0x80000001) { | |
641 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
642 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 643 | } |
093af8d7 | 644 | } |
093af8d7 | 645 | |
5122c890 YL |
646 | if (c->extended_cpuid_level >= 0x80000008) { |
647 | u32 eax = cpuid_eax(0x80000008); | |
648 | ||
649 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
650 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 651 | } |
13c6c532 JB |
652 | #ifdef CONFIG_X86_32 |
653 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
654 | c->x86_phys_bits = 36; | |
5122c890 | 655 | #endif |
e3224234 YL |
656 | |
657 | if (c->extended_cpuid_level >= 0x80000007) | |
658 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 | 659 | |
1dedefd1 | 660 | init_scattered_cpuid_features(c); |
093af8d7 | 661 | } |
1da177e4 | 662 | |
148f9bb8 | 663 | static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
aef93c8b YL |
664 | { |
665 | #ifdef CONFIG_X86_32 | |
666 | int i; | |
667 | ||
668 | /* | |
669 | * First of all, decide if this is a 486 or higher | |
670 | * It's a 486 if we can modify the AC flag | |
671 | */ | |
672 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
673 | c->x86 = 4; | |
674 | else | |
675 | c->x86 = 3; | |
676 | ||
677 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
678 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
679 | c->x86_vendor_id[0] = 0; | |
680 | cpu_devs[i]->c_identify(c); | |
681 | if (c->x86_vendor_id[0]) { | |
682 | get_cpu_vendor(c); | |
683 | break; | |
684 | } | |
685 | } | |
686 | #endif | |
687 | } | |
688 | ||
34048c9e PC |
689 | /* |
690 | * Do minimum CPU detection early. | |
691 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
692 | * cache alignment. | |
693 | * The others are not touched to avoid unwanted side effects. | |
694 | * | |
695 | * WARNING: this function is only called on the BP. Don't add code here | |
696 | * that is supposed to run on all CPUs. | |
697 | */ | |
3da99c97 | 698 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 699 | { |
6627d242 YL |
700 | #ifdef CONFIG_X86_64 |
701 | c->x86_clflush_size = 64; | |
13c6c532 JB |
702 | c->x86_phys_bits = 36; |
703 | c->x86_virt_bits = 48; | |
6627d242 | 704 | #else |
d4387bd3 | 705 | c->x86_clflush_size = 32; |
13c6c532 JB |
706 | c->x86_phys_bits = 32; |
707 | c->x86_virt_bits = 32; | |
6627d242 | 708 | #endif |
0a488a53 | 709 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 710 | |
3da99c97 | 711 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 712 | c->extended_cpuid_level = 0; |
d7cd5611 | 713 | |
aef93c8b YL |
714 | if (!have_cpuid_p()) |
715 | identify_cpu_without_cpuid(c); | |
716 | ||
717 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
718 | if (!have_cpuid_p()) |
719 | return; | |
720 | ||
721 | cpu_detect(c); | |
3da99c97 | 722 | get_cpu_vendor(c); |
3da99c97 | 723 | get_cpu_cap(c); |
60e019eb | 724 | fpu_detect(c); |
12cf105c | 725 | |
10a434fc YL |
726 | if (this_cpu->c_early_init) |
727 | this_cpu->c_early_init(c); | |
093af8d7 | 728 | |
f6e9456c | 729 | c->cpu_index = 0; |
b38b0665 | 730 | filter_cpuid_features(c, false); |
de5397ad | 731 | |
a110b5ec BP |
732 | if (this_cpu->c_bsp_init) |
733 | this_cpu->c_bsp_init(c); | |
c3b83598 BP |
734 | |
735 | setup_force_cpu_cap(X86_FEATURE_ALWAYS); | |
d7cd5611 RR |
736 | } |
737 | ||
9d31d35b YL |
738 | void __init early_cpu_init(void) |
739 | { | |
02dde8b4 | 740 | const struct cpu_dev *const *cdev; |
10a434fc YL |
741 | int count = 0; |
742 | ||
ac23f253 | 743 | #ifdef CONFIG_PROCESSOR_SELECT |
9766cdbc | 744 | printk(KERN_INFO "KERNEL supported cpus:\n"); |
31c997ca IM |
745 | #endif |
746 | ||
10a434fc | 747 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 748 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 749 | |
10a434fc YL |
750 | if (count >= X86_VENDOR_NUM) |
751 | break; | |
752 | cpu_devs[count] = cpudev; | |
753 | count++; | |
754 | ||
ac23f253 | 755 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
756 | { |
757 | unsigned int j; | |
758 | ||
759 | for (j = 0; j < 2; j++) { | |
760 | if (!cpudev->c_ident[j]) | |
761 | continue; | |
762 | printk(KERN_INFO " %s %s\n", cpudev->c_vendor, | |
763 | cpudev->c_ident[j]); | |
764 | } | |
10a434fc | 765 | } |
0388423d | 766 | #endif |
10a434fc | 767 | } |
9d31d35b | 768 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 769 | } |
093af8d7 | 770 | |
b6734c35 | 771 | /* |
366d4a43 BP |
772 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; |
773 | * unfortunately, that's not true in practice because of early VIA | |
774 | * chips and (more importantly) broken virtualizers that are not easy | |
775 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
776 | * probing for it doesn't even work. Disable it completely on 32-bit | |
ba0593bf | 777 | * unless we can find a reliable way to detect all the broken cases. |
366d4a43 | 778 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). |
b6734c35 | 779 | */ |
148f9bb8 | 780 | static void detect_nopl(struct cpuinfo_x86 *c) |
b6734c35 | 781 | { |
366d4a43 | 782 | #ifdef CONFIG_X86_32 |
b6734c35 | 783 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
366d4a43 BP |
784 | #else |
785 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
786 | #endif | |
d7cd5611 RR |
787 | } |
788 | ||
148f9bb8 | 789 | static void generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 790 | { |
aef93c8b | 791 | c->extended_cpuid_level = 0; |
1da177e4 | 792 | |
3da99c97 | 793 | if (!have_cpuid_p()) |
aef93c8b | 794 | identify_cpu_without_cpuid(c); |
1d67953f | 795 | |
aef93c8b | 796 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 797 | if (!have_cpuid_p()) |
aef93c8b | 798 | return; |
1da177e4 | 799 | |
3da99c97 | 800 | cpu_detect(c); |
1da177e4 | 801 | |
3da99c97 | 802 | get_cpu_vendor(c); |
1da177e4 | 803 | |
3da99c97 | 804 | get_cpu_cap(c); |
1da177e4 | 805 | |
3da99c97 YL |
806 | if (c->cpuid_level >= 0x00000001) { |
807 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
808 | #ifdef CONFIG_X86_32 |
809 | # ifdef CONFIG_X86_HT | |
cb8cc442 | 810 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 811 | # else |
3da99c97 | 812 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
813 | # endif |
814 | #endif | |
b89d3b3e | 815 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 816 | } |
1da177e4 | 817 | |
1b05d60d | 818 | get_model_name(c); /* Default name */ |
1da177e4 | 819 | |
3da99c97 | 820 | detect_nopl(c); |
1da177e4 | 821 | } |
1da177e4 LT |
822 | |
823 | /* | |
824 | * This does the hard work of actually picking apart the CPU stuff... | |
825 | */ | |
148f9bb8 | 826 | static void identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
827 | { |
828 | int i; | |
829 | ||
830 | c->loops_per_jiffy = loops_per_jiffy; | |
831 | c->x86_cache_size = -1; | |
832 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
833 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
834 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
835 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 836 | c->x86_max_cores = 1; |
102bbe3a | 837 | c->x86_coreid_bits = 0; |
11fdd252 | 838 | #ifdef CONFIG_X86_64 |
102bbe3a | 839 | c->x86_clflush_size = 64; |
13c6c532 JB |
840 | c->x86_phys_bits = 36; |
841 | c->x86_virt_bits = 48; | |
102bbe3a YL |
842 | #else |
843 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 844 | c->x86_clflush_size = 32; |
13c6c532 JB |
845 | c->x86_phys_bits = 32; |
846 | c->x86_virt_bits = 32; | |
102bbe3a YL |
847 | #endif |
848 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
849 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
850 | ||
1da177e4 LT |
851 | generic_identify(c); |
852 | ||
3898534d | 853 | if (this_cpu->c_identify) |
1da177e4 LT |
854 | this_cpu->c_identify(c); |
855 | ||
2759c328 YL |
856 | /* Clear/Set all flags overriden by options, after probe */ |
857 | for (i = 0; i < NCAPINTS; i++) { | |
858 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
859 | c->x86_capability[i] |= cpu_caps_set[i]; | |
860 | } | |
861 | ||
102bbe3a | 862 | #ifdef CONFIG_X86_64 |
cb8cc442 | 863 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
864 | #endif |
865 | ||
1da177e4 LT |
866 | /* |
867 | * Vendor-specific initialization. In this section we | |
868 | * canonicalize the feature flags, meaning if there are | |
869 | * features a certain CPU supports which CPUID doesn't | |
870 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
871 | * we handle them here. | |
872 | * | |
873 | * At the end of this section, c->x86_capability better | |
874 | * indicate the features this CPU genuinely supports! | |
875 | */ | |
876 | if (this_cpu->c_init) | |
877 | this_cpu->c_init(c); | |
878 | ||
879 | /* Disable the PN if appropriate */ | |
880 | squash_the_stupid_serial_number(c); | |
881 | ||
b2cc2a07 PA |
882 | /* Set up SMEP/SMAP */ |
883 | setup_smep(c); | |
884 | setup_smap(c); | |
885 | ||
1da177e4 | 886 | /* |
0f3fa48a IM |
887 | * The vendor-specific functions might have changed features. |
888 | * Now we do "generic changes." | |
1da177e4 LT |
889 | */ |
890 | ||
b38b0665 PA |
891 | /* Filter out anything that depends on CPUID levels we don't have */ |
892 | filter_cpuid_features(c, true); | |
893 | ||
1da177e4 | 894 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 895 | if (!c->x86_model_id[0]) { |
02dde8b4 | 896 | const char *p; |
1da177e4 | 897 | p = table_lookup_model(c); |
34048c9e | 898 | if (p) |
1da177e4 LT |
899 | strcpy(c->x86_model_id, p); |
900 | else | |
901 | /* Last resort... */ | |
902 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 903 | c->x86, c->x86_model); |
1da177e4 LT |
904 | } |
905 | ||
102bbe3a YL |
906 | #ifdef CONFIG_X86_64 |
907 | detect_ht(c); | |
908 | #endif | |
909 | ||
88b094fb | 910 | init_hypervisor(c); |
49d859d7 | 911 | x86_init_rdrand(c); |
3e0c3737 YL |
912 | |
913 | /* | |
914 | * Clear/Set all flags overriden by options, need do it | |
915 | * before following smp all cpus cap AND. | |
916 | */ | |
917 | for (i = 0; i < NCAPINTS; i++) { | |
918 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
919 | c->x86_capability[i] |= cpu_caps_set[i]; | |
920 | } | |
921 | ||
1da177e4 LT |
922 | /* |
923 | * On SMP, boot_cpu_data holds the common feature set between | |
924 | * all CPUs; so make sure that we indicate which features are | |
925 | * common between the CPUs. The first time this routine gets | |
926 | * executed, c == &boot_cpu_data. | |
927 | */ | |
34048c9e | 928 | if (c != &boot_cpu_data) { |
1da177e4 | 929 | /* AND the already accumulated flags with these */ |
9d31d35b | 930 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 | 931 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
65fc985b BP |
932 | |
933 | /* OR, i.e. replicate the bug flags */ | |
934 | for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) | |
935 | c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; | |
1da177e4 LT |
936 | } |
937 | ||
938 | /* Init Machine Check Exception if available. */ | |
5e09954a | 939 | mcheck_cpu_init(c); |
30d432df AK |
940 | |
941 | select_idle_routine(c); | |
102bbe3a | 942 | |
de2d9445 | 943 | #ifdef CONFIG_NUMA |
102bbe3a YL |
944 | numa_add_cpu(smp_processor_id()); |
945 | #endif | |
a6c4e076 | 946 | } |
31ab269a | 947 | |
e04d645f GC |
948 | #ifdef CONFIG_X86_64 |
949 | static void vgetcpu_set_mode(void) | |
950 | { | |
951 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
952 | vgetcpu_mode = VGETCPU_RDTSCP; | |
953 | else | |
954 | vgetcpu_mode = VGETCPU_LSL; | |
955 | } | |
956 | #endif | |
957 | ||
a6c4e076 JF |
958 | void __init identify_boot_cpu(void) |
959 | { | |
960 | identify_cpu(&boot_cpu_data); | |
02c68a02 | 961 | init_amd_e400_c1e_mask(); |
102bbe3a | 962 | #ifdef CONFIG_X86_32 |
a6c4e076 | 963 | sysenter_setup(); |
6fe940d6 | 964 | enable_sep_cpu(); |
e04d645f GC |
965 | #else |
966 | vgetcpu_set_mode(); | |
102bbe3a | 967 | #endif |
5b556332 | 968 | cpu_detect_tlb(&boot_cpu_data); |
a6c4e076 | 969 | } |
3b520b23 | 970 | |
148f9bb8 | 971 | void identify_secondary_cpu(struct cpuinfo_x86 *c) |
a6c4e076 JF |
972 | { |
973 | BUG_ON(c == &boot_cpu_data); | |
974 | identify_cpu(c); | |
102bbe3a | 975 | #ifdef CONFIG_X86_32 |
a6c4e076 | 976 | enable_sep_cpu(); |
102bbe3a | 977 | #endif |
a6c4e076 | 978 | mtrr_ap_init(); |
1da177e4 LT |
979 | } |
980 | ||
a0854a46 | 981 | struct msr_range { |
0f3fa48a IM |
982 | unsigned min; |
983 | unsigned max; | |
a0854a46 | 984 | }; |
1da177e4 | 985 | |
148f9bb8 | 986 | static const struct msr_range msr_range_array[] = { |
a0854a46 YL |
987 | { 0x00000000, 0x00000418}, |
988 | { 0xc0000000, 0xc000040b}, | |
989 | { 0xc0010000, 0xc0010142}, | |
990 | { 0xc0011000, 0xc001103b}, | |
991 | }; | |
1da177e4 | 992 | |
148f9bb8 | 993 | static void __print_cpu_msr(void) |
a0854a46 | 994 | { |
0f3fa48a | 995 | unsigned index_min, index_max; |
a0854a46 YL |
996 | unsigned index; |
997 | u64 val; | |
998 | int i; | |
a0854a46 YL |
999 | |
1000 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
1001 | index_min = msr_range_array[i].min; | |
1002 | index_max = msr_range_array[i].max; | |
0f3fa48a | 1003 | |
a0854a46 | 1004 | for (index = index_min; index < index_max; index++) { |
ecd431d9 | 1005 | if (rdmsrl_safe(index, &val)) |
a0854a46 YL |
1006 | continue; |
1007 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 1008 | } |
a0854a46 YL |
1009 | } |
1010 | } | |
94605eff | 1011 | |
148f9bb8 | 1012 | static int show_msr; |
0f3fa48a | 1013 | |
a0854a46 YL |
1014 | static __init int setup_show_msr(char *arg) |
1015 | { | |
1016 | int num; | |
3dd9d514 | 1017 | |
a0854a46 | 1018 | get_option(&arg, &num); |
3dd9d514 | 1019 | |
a0854a46 YL |
1020 | if (num > 0) |
1021 | show_msr = num; | |
1022 | return 1; | |
1da177e4 | 1023 | } |
a0854a46 | 1024 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 1025 | |
191679fd AK |
1026 | static __init int setup_noclflush(char *arg) |
1027 | { | |
840d2830 | 1028 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); |
da4aaa7d | 1029 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); |
191679fd AK |
1030 | return 1; |
1031 | } | |
1032 | __setup("noclflush", setup_noclflush); | |
1033 | ||
148f9bb8 | 1034 | void print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1035 | { |
02dde8b4 | 1036 | const char *vendor = NULL; |
1da177e4 | 1037 | |
0f3fa48a | 1038 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1039 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1040 | } else { |
1041 | if (c->cpuid_level >= 0) | |
1042 | vendor = c->x86_vendor_id; | |
1043 | } | |
1da177e4 | 1044 | |
bd32a8cf | 1045 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 1046 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 1047 | |
9d31d35b | 1048 | if (c->x86_model_id[0]) |
924e101a | 1049 | printk(KERN_CONT "%s", strim(c->x86_model_id)); |
1da177e4 | 1050 | else |
9d31d35b | 1051 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 1052 | |
924e101a BP |
1053 | printk(KERN_CONT " (fam: %02x, model: %02x", c->x86, c->x86_model); |
1054 | ||
34048c9e | 1055 | if (c->x86_mask || c->cpuid_level >= 0) |
924e101a | 1056 | printk(KERN_CONT ", stepping: %02x)\n", c->x86_mask); |
1da177e4 | 1057 | else |
924e101a | 1058 | printk(KERN_CONT ")\n"); |
a0854a46 | 1059 | |
0b8b8078 | 1060 | print_cpu_msr(c); |
21c3fcf3 YL |
1061 | } |
1062 | ||
148f9bb8 | 1063 | void print_cpu_msr(struct cpuinfo_x86 *c) |
21c3fcf3 | 1064 | { |
a0854a46 | 1065 | if (c->cpu_index < show_msr) |
21c3fcf3 | 1066 | __print_cpu_msr(); |
1da177e4 LT |
1067 | } |
1068 | ||
ac72e788 AK |
1069 | static __init int setup_disablecpuid(char *arg) |
1070 | { | |
1071 | int bit; | |
0f3fa48a | 1072 | |
ac72e788 AK |
1073 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) |
1074 | setup_clear_cpu_cap(bit); | |
1075 | else | |
1076 | return 0; | |
0f3fa48a | 1077 | |
ac72e788 AK |
1078 | return 1; |
1079 | } | |
1080 | __setup("clearcpuid=", setup_disablecpuid); | |
1081 | ||
198d208d SR |
1082 | DEFINE_PER_CPU(unsigned long, kernel_stack) = |
1083 | (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; | |
1084 | EXPORT_PER_CPU_SYMBOL(kernel_stack); | |
1085 | ||
d5494d4f | 1086 | #ifdef CONFIG_X86_64 |
9ff80942 | 1087 | struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; |
629f4f9d SA |
1088 | struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1, |
1089 | (unsigned long) debug_idt_table }; | |
d5494d4f | 1090 | |
947e76cd | 1091 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
277d5b40 | 1092 | irq_stack_union) __aligned(PAGE_SIZE) __visible; |
0f3fa48a | 1093 | |
bdf977b3 TH |
1094 | /* |
1095 | * The following four percpu variables are hot. Align current_task to | |
1096 | * cacheline size such that all four fall in the same cacheline. | |
1097 | */ | |
1098 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1099 | &init_task; | |
1100 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1101 | |
bdf977b3 TH |
1102 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
1103 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; | |
1104 | ||
277d5b40 | 1105 | DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; |
d5494d4f | 1106 | |
c2daa3be PZ |
1107 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1108 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
1109 | ||
7e16838d LT |
1110 | DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); |
1111 | ||
0f3fa48a IM |
1112 | /* |
1113 | * Special IST stacks which the CPU switches to when it calls | |
1114 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
1115 | * limit), all of them are 4K, except the debug stack which | |
1116 | * is 8K. | |
1117 | */ | |
1118 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
1119 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1120 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1121 | }; | |
1122 | ||
92d65b23 | 1123 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
3e352aa8 | 1124 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); |
d5494d4f | 1125 | |
d5494d4f YL |
1126 | /* May not be marked __init: used by software suspend */ |
1127 | void syscall_init(void) | |
1da177e4 | 1128 | { |
d5494d4f YL |
1129 | /* |
1130 | * LSTAR and STAR live in a bit strange symbiosis. | |
1131 | * They both write to the same internal register. STAR allows to | |
1132 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
1133 | */ | |
1134 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
1135 | wrmsrl(MSR_LSTAR, system_call); | |
1136 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 1137 | |
d5494d4f YL |
1138 | #ifdef CONFIG_IA32_EMULATION |
1139 | syscall32_cpu_init(); | |
1140 | #endif | |
03ae5768 | 1141 | |
d5494d4f YL |
1142 | /* Flags to clear on syscall */ |
1143 | wrmsrl(MSR_SYSCALL_MASK, | |
63bcff2a PA |
1144 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| |
1145 | X86_EFLAGS_IOPL|X86_EFLAGS_AC); | |
1da177e4 | 1146 | } |
62111195 | 1147 | |
d5494d4f YL |
1148 | /* |
1149 | * Copies of the original ist values from the tss are only accessed during | |
1150 | * debugging, no special alignment required. | |
1151 | */ | |
1152 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1153 | ||
228bdaa9 | 1154 | static DEFINE_PER_CPU(unsigned long, debug_stack_addr); |
42181186 | 1155 | DEFINE_PER_CPU(int, debug_stack_usage); |
228bdaa9 SR |
1156 | |
1157 | int is_debug_stack(unsigned long addr) | |
1158 | { | |
42181186 SR |
1159 | return __get_cpu_var(debug_stack_usage) || |
1160 | (addr <= __get_cpu_var(debug_stack_addr) && | |
1161 | addr > (__get_cpu_var(debug_stack_addr) - DEBUG_STKSZ)); | |
228bdaa9 SR |
1162 | } |
1163 | ||
629f4f9d | 1164 | DEFINE_PER_CPU(u32, debug_idt_ctr); |
f8988175 | 1165 | |
228bdaa9 SR |
1166 | void debug_stack_set_zero(void) |
1167 | { | |
629f4f9d SA |
1168 | this_cpu_inc(debug_idt_ctr); |
1169 | load_current_idt(); | |
228bdaa9 SR |
1170 | } |
1171 | ||
1172 | void debug_stack_reset(void) | |
1173 | { | |
629f4f9d | 1174 | if (WARN_ON(!this_cpu_read(debug_idt_ctr))) |
f8988175 | 1175 | return; |
629f4f9d SA |
1176 | if (this_cpu_dec_return(debug_idt_ctr) == 0) |
1177 | load_current_idt(); | |
228bdaa9 SR |
1178 | } |
1179 | ||
0f3fa48a | 1180 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1181 | |
bdf977b3 TH |
1182 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1183 | EXPORT_PER_CPU_SYMBOL(current_task); | |
c2daa3be PZ |
1184 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1185 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
27e74da9 | 1186 | DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); |
bdf977b3 | 1187 | |
60a5317f | 1188 | #ifdef CONFIG_CC_STACKPROTECTOR |
53f82452 | 1189 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1190 | #endif |
d5494d4f | 1191 | |
0f3fa48a | 1192 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1193 | |
9766cdbc JSR |
1194 | /* |
1195 | * Clear all 6 debug registers: | |
1196 | */ | |
1197 | static void clear_all_debug_regs(void) | |
1198 | { | |
1199 | int i; | |
1200 | ||
1201 | for (i = 0; i < 8; i++) { | |
1202 | /* Ignore db4, db5 */ | |
1203 | if ((i == 4) || (i == 5)) | |
1204 | continue; | |
1205 | ||
1206 | set_debugreg(0, i); | |
1207 | } | |
1208 | } | |
c5413fbe | 1209 | |
0bb9fef9 JW |
1210 | #ifdef CONFIG_KGDB |
1211 | /* | |
1212 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1213 | * connection established. | |
1214 | */ | |
1215 | static void dbg_restore_debug_regs(void) | |
1216 | { | |
1217 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1218 | arch_kgdb_ops.correct_hw_break(); | |
1219 | } | |
1220 | #else /* ! CONFIG_KGDB */ | |
1221 | #define dbg_restore_debug_regs() | |
1222 | #endif /* ! CONFIG_KGDB */ | |
1223 | ||
d2cbcc49 RR |
1224 | /* |
1225 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1226 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1227 | * and IDT. We reload them nevertheless, this function acts as a | |
1228 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1229 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1230 | */ |
1ba76586 | 1231 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1232 | |
148f9bb8 | 1233 | void cpu_init(void) |
1ba76586 | 1234 | { |
0fe1e009 | 1235 | struct orig_ist *oist; |
1ba76586 | 1236 | struct task_struct *me; |
0f3fa48a IM |
1237 | struct tss_struct *t; |
1238 | unsigned long v; | |
1239 | int cpu; | |
1ba76586 YL |
1240 | int i; |
1241 | ||
e6ebf5de FY |
1242 | /* |
1243 | * Load microcode on this cpu if a valid microcode is available. | |
1244 | * This is early microcode loading procedure. | |
1245 | */ | |
1246 | load_ucode_ap(); | |
1247 | ||
0f3fa48a IM |
1248 | cpu = stack_smp_processor_id(); |
1249 | t = &per_cpu(init_tss, cpu); | |
0fe1e009 | 1250 | oist = &per_cpu(orig_ist, cpu); |
0f3fa48a | 1251 | |
e7a22c1e | 1252 | #ifdef CONFIG_NUMA |
27fd185f | 1253 | if (this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
1254 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
1255 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1256 | #endif |
1ba76586 YL |
1257 | |
1258 | me = current; | |
1259 | ||
c2d1cec1 | 1260 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) |
1ba76586 YL |
1261 | panic("CPU#%d already initialized!\n", cpu); |
1262 | ||
2eaad1fd | 1263 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 YL |
1264 | |
1265 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1266 | ||
1267 | /* | |
1268 | * Initialize the per-CPU GDT with the boot GDT, | |
1269 | * and set up the GDT descriptor: | |
1270 | */ | |
1271 | ||
552be871 | 1272 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1273 | loadsegment(fs, 0); |
1274 | ||
cf910e83 | 1275 | load_current_idt(); |
1ba76586 YL |
1276 | |
1277 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1278 | syscall_init(); | |
1279 | ||
1280 | wrmsrl(MSR_FS_BASE, 0); | |
1281 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1282 | barrier(); | |
1283 | ||
4763ed4d | 1284 | x86_configure_nx(); |
27fd185f | 1285 | enable_x2apic(); |
1ba76586 YL |
1286 | |
1287 | /* | |
1288 | * set up and load the per-CPU TSS | |
1289 | */ | |
0fe1e009 | 1290 | if (!oist->ist[0]) { |
92d65b23 | 1291 | char *estacks = per_cpu(exception_stacks, cpu); |
0f3fa48a | 1292 | |
1ba76586 | 1293 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
0f3fa48a | 1294 | estacks += exception_stack_sizes[v]; |
0fe1e009 | 1295 | oist->ist[v] = t->x86_tss.ist[v] = |
1ba76586 | 1296 | (unsigned long)estacks; |
228bdaa9 SR |
1297 | if (v == DEBUG_STACK-1) |
1298 | per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; | |
1ba76586 YL |
1299 | } |
1300 | } | |
1301 | ||
1302 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
0f3fa48a | 1303 | |
1ba76586 YL |
1304 | /* |
1305 | * <= is required because the CPU will access up to | |
1306 | * 8 bits beyond the end of the IO permission bitmap. | |
1307 | */ | |
1308 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1309 | t->io_bitmap[i] = ~0UL; | |
1310 | ||
1311 | atomic_inc(&init_mm.mm_count); | |
1312 | me->active_mm = &init_mm; | |
8c5dfd25 | 1313 | BUG_ON(me->mm); |
1ba76586 YL |
1314 | enter_lazy_tlb(&init_mm, me); |
1315 | ||
1316 | load_sp0(t, ¤t->thread); | |
1317 | set_tss_desc(cpu, t); | |
1318 | load_TR_desc(); | |
1319 | load_LDT(&init_mm.context); | |
1320 | ||
0bb9fef9 JW |
1321 | clear_all_debug_regs(); |
1322 | dbg_restore_debug_regs(); | |
1ba76586 YL |
1323 | |
1324 | fpu_init(); | |
1325 | ||
1ba76586 YL |
1326 | if (is_uv_system()) |
1327 | uv_cpu_init(); | |
1328 | } | |
1329 | ||
1330 | #else | |
1331 | ||
148f9bb8 | 1332 | void cpu_init(void) |
9ee79a3d | 1333 | { |
d2cbcc49 RR |
1334 | int cpu = smp_processor_id(); |
1335 | struct task_struct *curr = current; | |
34048c9e | 1336 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1337 | struct thread_struct *thread = &curr->thread; |
62111195 | 1338 | |
e6ebf5de FY |
1339 | show_ucode_info_early(); |
1340 | ||
c2d1cec1 | 1341 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { |
62111195 | 1342 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); |
9766cdbc JSR |
1343 | for (;;) |
1344 | local_irq_enable(); | |
62111195 JF |
1345 | } |
1346 | ||
1347 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1348 | ||
1349 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1350 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1351 | |
cf910e83 | 1352 | load_current_idt(); |
552be871 | 1353 | switch_to_new_gdt(cpu); |
1da177e4 | 1354 | |
1da177e4 LT |
1355 | /* |
1356 | * Set up and load the per-CPU TSS and LDT | |
1357 | */ | |
1358 | atomic_inc(&init_mm.mm_count); | |
62111195 | 1359 | curr->active_mm = &init_mm; |
8c5dfd25 | 1360 | BUG_ON(curr->mm); |
62111195 | 1361 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1362 | |
faca6227 | 1363 | load_sp0(t, thread); |
34048c9e | 1364 | set_tss_desc(cpu, t); |
1da177e4 LT |
1365 | load_TR_desc(); |
1366 | load_LDT(&init_mm.context); | |
1367 | ||
f9a196b8 TG |
1368 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); |
1369 | ||
22c4e308 | 1370 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1371 | /* Set up doublefault TSS pointer in the GDT */ |
1372 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1373 | #endif |
1da177e4 | 1374 | |
9766cdbc | 1375 | clear_all_debug_regs(); |
0bb9fef9 | 1376 | dbg_restore_debug_regs(); |
1da177e4 | 1377 | |
0e49bf66 | 1378 | fpu_init(); |
1da177e4 | 1379 | } |
1ba76586 | 1380 | #endif |
5700f743 BP |
1381 | |
1382 | #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS | |
1383 | void warn_pre_alternatives(void) | |
1384 | { | |
1385 | WARN(1, "You're using static_cpu_has before alternatives have run!\n"); | |
1386 | } | |
1387 | EXPORT_SYMBOL_GPL(warn_pre_alternatives); | |
1388 | #endif | |
4a90a99c BP |
1389 | |
1390 | inline bool __static_cpu_has_safe(u16 bit) | |
1391 | { | |
1392 | return boot_cpu_has(bit); | |
1393 | } | |
1394 | EXPORT_SYMBOL_GPL(__static_cpu_has_safe); |