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Commit | Line | Data |
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f0fc4aff | 1 | #include <linux/bootmem.h> |
9766cdbc | 2 | #include <linux/linkage.h> |
f0fc4aff | 3 | #include <linux/bitops.h> |
9766cdbc | 4 | #include <linux/kernel.h> |
f0fc4aff | 5 | #include <linux/module.h> |
9766cdbc JSR |
6 | #include <linux/percpu.h> |
7 | #include <linux/string.h> | |
1da177e4 | 8 | #include <linux/delay.h> |
9766cdbc JSR |
9 | #include <linux/sched.h> |
10 | #include <linux/init.h> | |
11 | #include <linux/kgdb.h> | |
1da177e4 | 12 | #include <linux/smp.h> |
9766cdbc JSR |
13 | #include <linux/io.h> |
14 | ||
15 | #include <asm/stackprotector.h> | |
cdd6c482 | 16 | #include <asm/perf_event.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
49d859d7 | 18 | #include <asm/archrandom.h> |
9766cdbc JSR |
19 | #include <asm/hypervisor.h> |
20 | #include <asm/processor.h> | |
f649e938 | 21 | #include <asm/debugreg.h> |
9766cdbc | 22 | #include <asm/sections.h> |
f40c3300 | 23 | #include <asm/vsyscall.h> |
8bdbd962 AC |
24 | #include <linux/topology.h> |
25 | #include <linux/cpumask.h> | |
9766cdbc | 26 | #include <asm/pgtable.h> |
60063497 | 27 | #include <linux/atomic.h> |
9766cdbc JSR |
28 | #include <asm/proto.h> |
29 | #include <asm/setup.h> | |
30 | #include <asm/apic.h> | |
31 | #include <asm/desc.h> | |
32 | #include <asm/i387.h> | |
1361b83a | 33 | #include <asm/fpu-internal.h> |
27b07da7 | 34 | #include <asm/mtrr.h> |
8bdbd962 | 35 | #include <linux/numa.h> |
9766cdbc JSR |
36 | #include <asm/asm.h> |
37 | #include <asm/cpu.h> | |
a03a3e28 | 38 | #include <asm/mce.h> |
9766cdbc | 39 | #include <asm/msr.h> |
8d4a4300 | 40 | #include <asm/pat.h> |
d288e1cf FY |
41 | #include <asm/microcode.h> |
42 | #include <asm/microcode_intel.h> | |
e641f5f5 IM |
43 | |
44 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 45 | #include <asm/uv/uv.h> |
1da177e4 LT |
46 | #endif |
47 | ||
48 | #include "cpu.h" | |
49 | ||
c2d1cec1 | 50 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 51 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
52 | cpumask_var_t cpu_callout_mask; |
53 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
54 | |
55 | /* representing cpus for which sibling maps can be computed */ | |
56 | cpumask_var_t cpu_sibling_setup_mask; | |
57 | ||
2f2f52ba | 58 | /* correctly size the local cpu masks */ |
4369f1fb | 59 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
60 | { |
61 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
62 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
63 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
64 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
65 | } | |
66 | ||
148f9bb8 | 67 | static void default_init(struct cpuinfo_x86 *c) |
e8055139 OZ |
68 | { |
69 | #ifdef CONFIG_X86_64 | |
27c13ece | 70 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
71 | #else |
72 | /* Not much we can do here... */ | |
73 | /* Check if at least it has cpuid */ | |
74 | if (c->cpuid_level == -1) { | |
75 | /* No cpuid. It must be an ancient CPU */ | |
76 | if (c->x86 == 4) | |
77 | strcpy(c->x86_model_id, "486"); | |
78 | else if (c->x86 == 3) | |
79 | strcpy(c->x86_model_id, "386"); | |
80 | } | |
81 | #endif | |
82 | } | |
83 | ||
148f9bb8 | 84 | static const struct cpu_dev default_cpu = { |
e8055139 OZ |
85 | .c_init = default_init, |
86 | .c_vendor = "Unknown", | |
87 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
88 | }; | |
89 | ||
148f9bb8 | 90 | static const struct cpu_dev *this_cpu = &default_cpu; |
0a488a53 | 91 | |
06deef89 | 92 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 93 | #ifdef CONFIG_X86_64 |
06deef89 BG |
94 | /* |
95 | * We need valid kernel segments for data and code in long mode too | |
96 | * IRET will check the segment types kkeil 2000/10/28 | |
97 | * Also sysret mandates a special GDT layout | |
98 | * | |
9766cdbc | 99 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
100 | * Hopefully nobody expects them at a fixed place (Wine?) |
101 | */ | |
1e5de182 AM |
102 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
103 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
104 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
105 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
106 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
107 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 108 | #else |
1e5de182 AM |
109 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
110 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
111 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
112 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
113 | /* |
114 | * Segments used for calling PnP BIOS have byte granularity. | |
115 | * They code segments and data segments have fixed 64k limits, | |
116 | * the transfer segment sizes are set at run time. | |
117 | */ | |
6842ef0e | 118 | /* 32-bit code */ |
1e5de182 | 119 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 120 | /* 16-bit code */ |
1e5de182 | 121 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 122 | /* 16-bit data */ |
1e5de182 | 123 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 124 | /* 16-bit data */ |
1e5de182 | 125 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 126 | /* 16-bit data */ |
1e5de182 | 127 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
128 | /* |
129 | * The APM segments have byte granularity and their bases | |
130 | * are set at run time. All have 64k limits. | |
131 | */ | |
6842ef0e | 132 | /* 32-bit code */ |
1e5de182 | 133 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 134 | /* 16-bit code */ |
1e5de182 | 135 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 136 | /* data */ |
72c4d853 | 137 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 138 | |
1e5de182 AM |
139 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
140 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 141 | GDT_STACK_CANARY_INIT |
950ad7ff | 142 | #endif |
06deef89 | 143 | } }; |
7a61d35d | 144 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 145 | |
0c752a93 SS |
146 | static int __init x86_xsave_setup(char *s) |
147 | { | |
148 | setup_clear_cpu_cap(X86_FEATURE_XSAVE); | |
6bad06b7 | 149 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); |
c6fd893d SS |
150 | setup_clear_cpu_cap(X86_FEATURE_AVX); |
151 | setup_clear_cpu_cap(X86_FEATURE_AVX2); | |
0c752a93 SS |
152 | return 1; |
153 | } | |
154 | __setup("noxsave", x86_xsave_setup); | |
155 | ||
6bad06b7 SS |
156 | static int __init x86_xsaveopt_setup(char *s) |
157 | { | |
158 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); | |
159 | return 1; | |
160 | } | |
161 | __setup("noxsaveopt", x86_xsaveopt_setup); | |
162 | ||
ba51dced | 163 | #ifdef CONFIG_X86_32 |
148f9bb8 PG |
164 | static int cachesize_override = -1; |
165 | static int disable_x86_serial_nr = 1; | |
1da177e4 | 166 | |
0a488a53 YL |
167 | static int __init cachesize_setup(char *str) |
168 | { | |
169 | get_option(&str, &cachesize_override); | |
170 | return 1; | |
171 | } | |
172 | __setup("cachesize=", cachesize_setup); | |
173 | ||
0a488a53 YL |
174 | static int __init x86_fxsr_setup(char *s) |
175 | { | |
176 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
177 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
178 | return 1; | |
179 | } | |
180 | __setup("nofxsr", x86_fxsr_setup); | |
181 | ||
182 | static int __init x86_sep_setup(char *s) | |
183 | { | |
184 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
185 | return 1; | |
186 | } | |
187 | __setup("nosep", x86_sep_setup); | |
188 | ||
189 | /* Standard macro to see if a specific flag is changeable */ | |
190 | static inline int flag_is_changeable_p(u32 flag) | |
191 | { | |
192 | u32 f1, f2; | |
193 | ||
94f6bac1 KH |
194 | /* |
195 | * Cyrix and IDT cpus allow disabling of CPUID | |
196 | * so the code below may return different results | |
197 | * when it is executed before and after enabling | |
198 | * the CPUID. Add "volatile" to not allow gcc to | |
199 | * optimize the subsequent calls to this function. | |
200 | */ | |
0f3fa48a IM |
201 | asm volatile ("pushfl \n\t" |
202 | "pushfl \n\t" | |
203 | "popl %0 \n\t" | |
204 | "movl %0, %1 \n\t" | |
205 | "xorl %2, %0 \n\t" | |
206 | "pushl %0 \n\t" | |
207 | "popfl \n\t" | |
208 | "pushfl \n\t" | |
209 | "popl %0 \n\t" | |
210 | "popfl \n\t" | |
211 | ||
94f6bac1 KH |
212 | : "=&r" (f1), "=&r" (f2) |
213 | : "ir" (flag)); | |
0a488a53 YL |
214 | |
215 | return ((f1^f2) & flag) != 0; | |
216 | } | |
217 | ||
218 | /* Probe for the CPUID instruction */ | |
148f9bb8 | 219 | int have_cpuid_p(void) |
0a488a53 YL |
220 | { |
221 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
222 | } | |
223 | ||
148f9bb8 | 224 | static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
0a488a53 | 225 | { |
0f3fa48a IM |
226 | unsigned long lo, hi; |
227 | ||
228 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
229 | return; | |
230 | ||
231 | /* Disable processor serial number: */ | |
232 | ||
233 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
234 | lo |= 0x200000; | |
235 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
236 | ||
237 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
238 | clear_cpu_cap(c, X86_FEATURE_PN); | |
239 | ||
240 | /* Disabling the serial number may affect the cpuid level */ | |
241 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
242 | } |
243 | ||
244 | static int __init x86_serial_nr_setup(char *s) | |
245 | { | |
246 | disable_x86_serial_nr = 0; | |
247 | return 1; | |
248 | } | |
249 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 250 | #else |
102bbe3a YL |
251 | static inline int flag_is_changeable_p(u32 flag) |
252 | { | |
253 | return 1; | |
254 | } | |
102bbe3a YL |
255 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
256 | { | |
257 | } | |
ba51dced | 258 | #endif |
0a488a53 | 259 | |
de5397ad FY |
260 | static __init int setup_disable_smep(char *arg) |
261 | { | |
b2cc2a07 | 262 | setup_clear_cpu_cap(X86_FEATURE_SMEP); |
de5397ad FY |
263 | return 1; |
264 | } | |
265 | __setup("nosmep", setup_disable_smep); | |
266 | ||
b2cc2a07 | 267 | static __always_inline void setup_smep(struct cpuinfo_x86 *c) |
de5397ad | 268 | { |
b2cc2a07 PA |
269 | if (cpu_has(c, X86_FEATURE_SMEP)) |
270 | set_in_cr4(X86_CR4_SMEP); | |
de5397ad FY |
271 | } |
272 | ||
52b6179a PA |
273 | static __init int setup_disable_smap(char *arg) |
274 | { | |
b2cc2a07 | 275 | setup_clear_cpu_cap(X86_FEATURE_SMAP); |
52b6179a PA |
276 | return 1; |
277 | } | |
278 | __setup("nosmap", setup_disable_smap); | |
279 | ||
b2cc2a07 PA |
280 | static __always_inline void setup_smap(struct cpuinfo_x86 *c) |
281 | { | |
282 | unsigned long eflags; | |
283 | ||
284 | /* This should have been cleared long ago */ | |
285 | raw_local_save_flags(eflags); | |
286 | BUG_ON(eflags & X86_EFLAGS_AC); | |
287 | ||
03bbd596 PA |
288 | if (cpu_has(c, X86_FEATURE_SMAP)) { |
289 | #ifdef CONFIG_X86_SMAP | |
b2cc2a07 | 290 | set_in_cr4(X86_CR4_SMAP); |
03bbd596 PA |
291 | #else |
292 | clear_in_cr4(X86_CR4_SMAP); | |
293 | #endif | |
294 | } | |
de5397ad FY |
295 | } |
296 | ||
b38b0665 PA |
297 | /* |
298 | * Some CPU features depend on higher CPUID levels, which may not always | |
299 | * be available due to CPUID level capping or broken virtualization | |
300 | * software. Add those features to this table to auto-disable them. | |
301 | */ | |
302 | struct cpuid_dependent_feature { | |
303 | u32 feature; | |
304 | u32 level; | |
305 | }; | |
0f3fa48a | 306 | |
148f9bb8 | 307 | static const struct cpuid_dependent_feature |
b38b0665 PA |
308 | cpuid_dependent_features[] = { |
309 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
310 | { X86_FEATURE_DCA, 0x00000009 }, | |
311 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
312 | { 0, 0 } | |
313 | }; | |
314 | ||
148f9bb8 | 315 | static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) |
b38b0665 PA |
316 | { |
317 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 318 | |
b38b0665 | 319 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
320 | |
321 | if (!cpu_has(c, df->feature)) | |
322 | continue; | |
b38b0665 PA |
323 | /* |
324 | * Note: cpuid_level is set to -1 if unavailable, but | |
325 | * extended_extended_level is set to 0 if unavailable | |
326 | * and the legitimate extended levels are all negative | |
327 | * when signed; hence the weird messing around with | |
328 | * signs here... | |
329 | */ | |
0f3fa48a | 330 | if (!((s32)df->level < 0 ? |
f6db44df | 331 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
332 | (s32)df->level > (s32)c->cpuid_level)) |
333 | continue; | |
334 | ||
335 | clear_cpu_cap(c, df->feature); | |
336 | if (!warn) | |
337 | continue; | |
338 | ||
339 | printk(KERN_WARNING | |
340 | "CPU: CPU feature %s disabled, no CPUID level 0x%x\n", | |
341 | x86_cap_flags[df->feature], df->level); | |
b38b0665 | 342 | } |
f6db44df | 343 | } |
b38b0665 | 344 | |
102bbe3a YL |
345 | /* |
346 | * Naming convention should be: <Name> [(<Codename>)] | |
347 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
348 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
349 | * isn't used | |
102bbe3a YL |
350 | */ |
351 | ||
352 | /* Look up CPU names by table lookup. */ | |
148f9bb8 | 353 | static const char *table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 354 | { |
09dc68d9 JB |
355 | #ifdef CONFIG_X86_32 |
356 | const struct legacy_cpu_model_info *info; | |
102bbe3a YL |
357 | |
358 | if (c->x86_model >= 16) | |
359 | return NULL; /* Range check */ | |
360 | ||
361 | if (!this_cpu) | |
362 | return NULL; | |
363 | ||
09dc68d9 | 364 | info = this_cpu->legacy_models; |
102bbe3a | 365 | |
09dc68d9 | 366 | while (info->family) { |
102bbe3a YL |
367 | if (info->family == c->x86) |
368 | return info->model_names[c->x86_model]; | |
369 | info++; | |
370 | } | |
09dc68d9 | 371 | #endif |
102bbe3a YL |
372 | return NULL; /* Not found */ |
373 | } | |
374 | ||
148f9bb8 PG |
375 | __u32 cpu_caps_cleared[NCAPINTS]; |
376 | __u32 cpu_caps_set[NCAPINTS]; | |
7d851c8d | 377 | |
11e3a840 JF |
378 | void load_percpu_segment(int cpu) |
379 | { | |
380 | #ifdef CONFIG_X86_32 | |
381 | loadsegment(fs, __KERNEL_PERCPU); | |
382 | #else | |
383 | loadsegment(gs, 0); | |
384 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
385 | #endif | |
60a5317f | 386 | load_stack_canary_segment(); |
11e3a840 JF |
387 | } |
388 | ||
0f3fa48a IM |
389 | /* |
390 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
391 | * it's on the real one. | |
392 | */ | |
552be871 | 393 | void switch_to_new_gdt(int cpu) |
9d31d35b YL |
394 | { |
395 | struct desc_ptr gdt_descr; | |
396 | ||
2697fbd5 | 397 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
398 | gdt_descr.size = GDT_SIZE - 1; |
399 | load_gdt(&gdt_descr); | |
2697fbd5 | 400 | /* Reload the per-cpu base */ |
11e3a840 JF |
401 | |
402 | load_percpu_segment(cpu); | |
9d31d35b YL |
403 | } |
404 | ||
148f9bb8 | 405 | static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 406 | |
148f9bb8 | 407 | static void get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
408 | { |
409 | unsigned int *v; | |
410 | char *p, *q; | |
411 | ||
3da99c97 | 412 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 413 | return; |
1da177e4 | 414 | |
0f3fa48a | 415 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
416 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
417 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
418 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
419 | c->x86_model_id[48] = 0; | |
420 | ||
0f3fa48a IM |
421 | /* |
422 | * Intel chips right-justify this string for some dumb reason; | |
423 | * undo that brain damage: | |
424 | */ | |
1da177e4 | 425 | p = q = &c->x86_model_id[0]; |
34048c9e | 426 | while (*p == ' ') |
9766cdbc | 427 | p++; |
34048c9e | 428 | if (p != q) { |
9766cdbc JSR |
429 | while (*p) |
430 | *q++ = *p++; | |
431 | while (q <= &c->x86_model_id[48]) | |
432 | *q++ = '\0'; /* Zero-pad the rest */ | |
1da177e4 | 433 | } |
1da177e4 LT |
434 | } |
435 | ||
148f9bb8 | 436 | void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 437 | { |
9d31d35b | 438 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 439 | |
3da99c97 | 440 | n = c->extended_cpuid_level; |
1da177e4 LT |
441 | |
442 | if (n >= 0x80000005) { | |
9d31d35b | 443 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 444 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
445 | #ifdef CONFIG_X86_64 |
446 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
447 | c->x86_tlbsize = 0; | |
448 | #endif | |
1da177e4 LT |
449 | } |
450 | ||
451 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
452 | return; | |
453 | ||
0a488a53 | 454 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 455 | l2size = ecx >> 16; |
34048c9e | 456 | |
140fc727 YL |
457 | #ifdef CONFIG_X86_64 |
458 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
459 | #else | |
1da177e4 | 460 | /* do processor-specific cache resizing */ |
09dc68d9 JB |
461 | if (this_cpu->legacy_cache_size) |
462 | l2size = this_cpu->legacy_cache_size(c, l2size); | |
1da177e4 LT |
463 | |
464 | /* Allow user to override all this if necessary. */ | |
465 | if (cachesize_override != -1) | |
466 | l2size = cachesize_override; | |
467 | ||
34048c9e | 468 | if (l2size == 0) |
1da177e4 | 469 | return; /* Again, no L2 cache is possible */ |
140fc727 | 470 | #endif |
1da177e4 LT |
471 | |
472 | c->x86_cache_size = l2size; | |
1da177e4 LT |
473 | } |
474 | ||
e0ba94f1 AS |
475 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
476 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
477 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
478 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
479 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
480 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
dd360393 | 481 | u16 __read_mostly tlb_lld_1g[NR_INFO]; |
e0ba94f1 | 482 | |
c4211f42 AS |
483 | /* |
484 | * tlb_flushall_shift shows the balance point in replacing cr3 write | |
485 | * with multiple 'invlpg'. It will do this replacement when | |
486 | * flush_tlb_lines <= active_lines/2^tlb_flushall_shift. | |
487 | * If tlb_flushall_shift is -1, means the replacement will be disabled. | |
488 | */ | |
489 | s8 __read_mostly tlb_flushall_shift = -1; | |
490 | ||
148f9bb8 | 491 | void cpu_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
492 | { |
493 | if (this_cpu->c_detect_tlb) | |
494 | this_cpu->c_detect_tlb(c); | |
495 | ||
dd360393 KS |
496 | printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" |
497 | "Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n" | |
a9ad773e | 498 | "tlb_flushall_shift: %d\n", |
e0ba94f1 AS |
499 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
500 | tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES], | |
c4211f42 | 501 | tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES], |
dd360393 | 502 | tlb_lld_1g[ENTRIES], tlb_flushall_shift); |
e0ba94f1 AS |
503 | } |
504 | ||
148f9bb8 | 505 | void detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 506 | { |
97e4db7c | 507 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
508 | u32 eax, ebx, ecx, edx; |
509 | int index_msb, core_bits; | |
2eaad1fd | 510 | static bool printed; |
1da177e4 | 511 | |
0a488a53 | 512 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 513 | return; |
1da177e4 | 514 | |
0a488a53 YL |
515 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
516 | goto out; | |
1da177e4 | 517 | |
1cd78776 YL |
518 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
519 | return; | |
1da177e4 | 520 | |
0a488a53 | 521 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 522 | |
9d31d35b YL |
523 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
524 | ||
525 | if (smp_num_siblings == 1) { | |
2eaad1fd | 526 | printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); |
0f3fa48a IM |
527 | goto out; |
528 | } | |
9d31d35b | 529 | |
0f3fa48a IM |
530 | if (smp_num_siblings <= 1) |
531 | goto out; | |
9d31d35b | 532 | |
0f3fa48a IM |
533 | index_msb = get_count_order(smp_num_siblings); |
534 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 535 | |
0f3fa48a | 536 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 537 | |
0f3fa48a | 538 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 539 | |
0f3fa48a | 540 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 541 | |
0f3fa48a IM |
542 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
543 | ((1 << core_bits) - 1); | |
1da177e4 | 544 | |
0a488a53 | 545 | out: |
2eaad1fd | 546 | if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { |
0a488a53 YL |
547 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", |
548 | c->phys_proc_id); | |
549 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
550 | c->cpu_core_id); | |
2eaad1fd | 551 | printed = 1; |
9d31d35b | 552 | } |
9d31d35b | 553 | #endif |
97e4db7c | 554 | } |
1da177e4 | 555 | |
148f9bb8 | 556 | static void get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
557 | { |
558 | char *v = c->x86_vendor_id; | |
0f3fa48a | 559 | int i; |
1da177e4 LT |
560 | |
561 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
562 | if (!cpu_devs[i]) |
563 | break; | |
564 | ||
565 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
566 | (cpu_devs[i]->c_ident[1] && | |
567 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 568 | |
10a434fc YL |
569 | this_cpu = cpu_devs[i]; |
570 | c->x86_vendor = this_cpu->c_x86_vendor; | |
571 | return; | |
1da177e4 LT |
572 | } |
573 | } | |
10a434fc | 574 | |
a9c56953 MK |
575 | printk_once(KERN_ERR |
576 | "CPU: vendor_id '%s' unknown, using generic init.\n" \ | |
577 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 578 | |
fe38d855 CE |
579 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
580 | this_cpu = &default_cpu; | |
1da177e4 LT |
581 | } |
582 | ||
148f9bb8 | 583 | void cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 584 | { |
1da177e4 | 585 | /* Get vendor name */ |
4a148513 HH |
586 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
587 | (unsigned int *)&c->x86_vendor_id[0], | |
588 | (unsigned int *)&c->x86_vendor_id[8], | |
589 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 590 | |
1da177e4 | 591 | c->x86 = 4; |
9d31d35b | 592 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
593 | if (c->cpuid_level >= 0x00000001) { |
594 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 595 | |
1da177e4 | 596 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
9d31d35b YL |
597 | c->x86 = (tfms >> 8) & 0xf; |
598 | c->x86_model = (tfms >> 4) & 0xf; | |
599 | c->x86_mask = tfms & 0xf; | |
0f3fa48a | 600 | |
f5f786d0 | 601 | if (c->x86 == 0xf) |
1da177e4 | 602 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 603 | if (c->x86 >= 0x6) |
9d31d35b | 604 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
0f3fa48a | 605 | |
d4387bd3 | 606 | if (cap0 & (1<<19)) { |
d4387bd3 | 607 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 608 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 609 | } |
1da177e4 | 610 | } |
1da177e4 | 611 | } |
3da99c97 | 612 | |
148f9bb8 | 613 | void get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 YL |
614 | { |
615 | u32 tfms, xlvl; | |
3da99c97 | 616 | u32 ebx; |
093af8d7 | 617 | |
3da99c97 YL |
618 | /* Intel-defined flags: level 0x00000001 */ |
619 | if (c->cpuid_level >= 0x00000001) { | |
620 | u32 capability, excap; | |
0f3fa48a | 621 | |
3da99c97 YL |
622 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); |
623 | c->x86_capability[0] = capability; | |
624 | c->x86_capability[4] = excap; | |
625 | } | |
093af8d7 | 626 | |
bdc802dc PA |
627 | /* Additional Intel-defined flags: level 0x00000007 */ |
628 | if (c->cpuid_level >= 0x00000007) { | |
629 | u32 eax, ebx, ecx, edx; | |
630 | ||
631 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); | |
632 | ||
2494b030 | 633 | c->x86_capability[9] = ebx; |
bdc802dc PA |
634 | } |
635 | ||
3da99c97 YL |
636 | /* AMD-defined flags: level 0x80000001 */ |
637 | xlvl = cpuid_eax(0x80000000); | |
638 | c->extended_cpuid_level = xlvl; | |
0f3fa48a | 639 | |
3da99c97 YL |
640 | if ((xlvl & 0xffff0000) == 0x80000000) { |
641 | if (xlvl >= 0x80000001) { | |
642 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
643 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 644 | } |
093af8d7 | 645 | } |
093af8d7 | 646 | |
5122c890 YL |
647 | if (c->extended_cpuid_level >= 0x80000008) { |
648 | u32 eax = cpuid_eax(0x80000008); | |
649 | ||
650 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
651 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 652 | } |
13c6c532 JB |
653 | #ifdef CONFIG_X86_32 |
654 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
655 | c->x86_phys_bits = 36; | |
5122c890 | 656 | #endif |
e3224234 YL |
657 | |
658 | if (c->extended_cpuid_level >= 0x80000007) | |
659 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 | 660 | |
1dedefd1 | 661 | init_scattered_cpuid_features(c); |
093af8d7 | 662 | } |
1da177e4 | 663 | |
148f9bb8 | 664 | static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
aef93c8b YL |
665 | { |
666 | #ifdef CONFIG_X86_32 | |
667 | int i; | |
668 | ||
669 | /* | |
670 | * First of all, decide if this is a 486 or higher | |
671 | * It's a 486 if we can modify the AC flag | |
672 | */ | |
673 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
674 | c->x86 = 4; | |
675 | else | |
676 | c->x86 = 3; | |
677 | ||
678 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
679 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
680 | c->x86_vendor_id[0] = 0; | |
681 | cpu_devs[i]->c_identify(c); | |
682 | if (c->x86_vendor_id[0]) { | |
683 | get_cpu_vendor(c); | |
684 | break; | |
685 | } | |
686 | } | |
687 | #endif | |
688 | } | |
689 | ||
34048c9e PC |
690 | /* |
691 | * Do minimum CPU detection early. | |
692 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
693 | * cache alignment. | |
694 | * The others are not touched to avoid unwanted side effects. | |
695 | * | |
696 | * WARNING: this function is only called on the BP. Don't add code here | |
697 | * that is supposed to run on all CPUs. | |
698 | */ | |
3da99c97 | 699 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 700 | { |
6627d242 YL |
701 | #ifdef CONFIG_X86_64 |
702 | c->x86_clflush_size = 64; | |
13c6c532 JB |
703 | c->x86_phys_bits = 36; |
704 | c->x86_virt_bits = 48; | |
6627d242 | 705 | #else |
d4387bd3 | 706 | c->x86_clflush_size = 32; |
13c6c532 JB |
707 | c->x86_phys_bits = 32; |
708 | c->x86_virt_bits = 32; | |
6627d242 | 709 | #endif |
0a488a53 | 710 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 711 | |
3da99c97 | 712 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 713 | c->extended_cpuid_level = 0; |
d7cd5611 | 714 | |
aef93c8b YL |
715 | if (!have_cpuid_p()) |
716 | identify_cpu_without_cpuid(c); | |
717 | ||
718 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
719 | if (!have_cpuid_p()) |
720 | return; | |
721 | ||
722 | cpu_detect(c); | |
3da99c97 | 723 | get_cpu_vendor(c); |
3da99c97 | 724 | get_cpu_cap(c); |
60e019eb | 725 | fpu_detect(c); |
12cf105c | 726 | |
10a434fc YL |
727 | if (this_cpu->c_early_init) |
728 | this_cpu->c_early_init(c); | |
093af8d7 | 729 | |
f6e9456c | 730 | c->cpu_index = 0; |
b38b0665 | 731 | filter_cpuid_features(c, false); |
de5397ad | 732 | |
a110b5ec BP |
733 | if (this_cpu->c_bsp_init) |
734 | this_cpu->c_bsp_init(c); | |
c3b83598 BP |
735 | |
736 | setup_force_cpu_cap(X86_FEATURE_ALWAYS); | |
d7cd5611 RR |
737 | } |
738 | ||
9d31d35b YL |
739 | void __init early_cpu_init(void) |
740 | { | |
02dde8b4 | 741 | const struct cpu_dev *const *cdev; |
10a434fc YL |
742 | int count = 0; |
743 | ||
ac23f253 | 744 | #ifdef CONFIG_PROCESSOR_SELECT |
9766cdbc | 745 | printk(KERN_INFO "KERNEL supported cpus:\n"); |
31c997ca IM |
746 | #endif |
747 | ||
10a434fc | 748 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 749 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 750 | |
10a434fc YL |
751 | if (count >= X86_VENDOR_NUM) |
752 | break; | |
753 | cpu_devs[count] = cpudev; | |
754 | count++; | |
755 | ||
ac23f253 | 756 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
757 | { |
758 | unsigned int j; | |
759 | ||
760 | for (j = 0; j < 2; j++) { | |
761 | if (!cpudev->c_ident[j]) | |
762 | continue; | |
763 | printk(KERN_INFO " %s %s\n", cpudev->c_vendor, | |
764 | cpudev->c_ident[j]); | |
765 | } | |
10a434fc | 766 | } |
0388423d | 767 | #endif |
10a434fc | 768 | } |
9d31d35b | 769 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 770 | } |
093af8d7 | 771 | |
b6734c35 | 772 | /* |
366d4a43 BP |
773 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; |
774 | * unfortunately, that's not true in practice because of early VIA | |
775 | * chips and (more importantly) broken virtualizers that are not easy | |
776 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
777 | * probing for it doesn't even work. Disable it completely on 32-bit | |
ba0593bf | 778 | * unless we can find a reliable way to detect all the broken cases. |
366d4a43 | 779 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). |
b6734c35 | 780 | */ |
148f9bb8 | 781 | static void detect_nopl(struct cpuinfo_x86 *c) |
b6734c35 | 782 | { |
366d4a43 | 783 | #ifdef CONFIG_X86_32 |
b6734c35 | 784 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
366d4a43 BP |
785 | #else |
786 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
787 | #endif | |
d7cd5611 RR |
788 | } |
789 | ||
148f9bb8 | 790 | static void generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 791 | { |
aef93c8b | 792 | c->extended_cpuid_level = 0; |
1da177e4 | 793 | |
3da99c97 | 794 | if (!have_cpuid_p()) |
aef93c8b | 795 | identify_cpu_without_cpuid(c); |
1d67953f | 796 | |
aef93c8b | 797 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 798 | if (!have_cpuid_p()) |
aef93c8b | 799 | return; |
1da177e4 | 800 | |
3da99c97 | 801 | cpu_detect(c); |
1da177e4 | 802 | |
3da99c97 | 803 | get_cpu_vendor(c); |
1da177e4 | 804 | |
3da99c97 | 805 | get_cpu_cap(c); |
1da177e4 | 806 | |
3da99c97 YL |
807 | if (c->cpuid_level >= 0x00000001) { |
808 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
809 | #ifdef CONFIG_X86_32 |
810 | # ifdef CONFIG_X86_HT | |
cb8cc442 | 811 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 812 | # else |
3da99c97 | 813 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
814 | # endif |
815 | #endif | |
b89d3b3e | 816 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 817 | } |
1da177e4 | 818 | |
1b05d60d | 819 | get_model_name(c); /* Default name */ |
1da177e4 | 820 | |
3da99c97 | 821 | detect_nopl(c); |
1da177e4 | 822 | } |
1da177e4 LT |
823 | |
824 | /* | |
825 | * This does the hard work of actually picking apart the CPU stuff... | |
826 | */ | |
148f9bb8 | 827 | static void identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
828 | { |
829 | int i; | |
830 | ||
831 | c->loops_per_jiffy = loops_per_jiffy; | |
832 | c->x86_cache_size = -1; | |
833 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
834 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
835 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
836 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 837 | c->x86_max_cores = 1; |
102bbe3a | 838 | c->x86_coreid_bits = 0; |
11fdd252 | 839 | #ifdef CONFIG_X86_64 |
102bbe3a | 840 | c->x86_clflush_size = 64; |
13c6c532 JB |
841 | c->x86_phys_bits = 36; |
842 | c->x86_virt_bits = 48; | |
102bbe3a YL |
843 | #else |
844 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 845 | c->x86_clflush_size = 32; |
13c6c532 JB |
846 | c->x86_phys_bits = 32; |
847 | c->x86_virt_bits = 32; | |
102bbe3a YL |
848 | #endif |
849 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
850 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
851 | ||
1da177e4 LT |
852 | generic_identify(c); |
853 | ||
3898534d | 854 | if (this_cpu->c_identify) |
1da177e4 LT |
855 | this_cpu->c_identify(c); |
856 | ||
2759c328 YL |
857 | /* Clear/Set all flags overriden by options, after probe */ |
858 | for (i = 0; i < NCAPINTS; i++) { | |
859 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
860 | c->x86_capability[i] |= cpu_caps_set[i]; | |
861 | } | |
862 | ||
102bbe3a | 863 | #ifdef CONFIG_X86_64 |
cb8cc442 | 864 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
865 | #endif |
866 | ||
1da177e4 LT |
867 | /* |
868 | * Vendor-specific initialization. In this section we | |
869 | * canonicalize the feature flags, meaning if there are | |
870 | * features a certain CPU supports which CPUID doesn't | |
871 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
872 | * we handle them here. | |
873 | * | |
874 | * At the end of this section, c->x86_capability better | |
875 | * indicate the features this CPU genuinely supports! | |
876 | */ | |
877 | if (this_cpu->c_init) | |
878 | this_cpu->c_init(c); | |
879 | ||
880 | /* Disable the PN if appropriate */ | |
881 | squash_the_stupid_serial_number(c); | |
882 | ||
b2cc2a07 PA |
883 | /* Set up SMEP/SMAP */ |
884 | setup_smep(c); | |
885 | setup_smap(c); | |
886 | ||
1da177e4 | 887 | /* |
0f3fa48a IM |
888 | * The vendor-specific functions might have changed features. |
889 | * Now we do "generic changes." | |
1da177e4 LT |
890 | */ |
891 | ||
b38b0665 PA |
892 | /* Filter out anything that depends on CPUID levels we don't have */ |
893 | filter_cpuid_features(c, true); | |
894 | ||
1da177e4 | 895 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 896 | if (!c->x86_model_id[0]) { |
02dde8b4 | 897 | const char *p; |
1da177e4 | 898 | p = table_lookup_model(c); |
34048c9e | 899 | if (p) |
1da177e4 LT |
900 | strcpy(c->x86_model_id, p); |
901 | else | |
902 | /* Last resort... */ | |
903 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 904 | c->x86, c->x86_model); |
1da177e4 LT |
905 | } |
906 | ||
102bbe3a YL |
907 | #ifdef CONFIG_X86_64 |
908 | detect_ht(c); | |
909 | #endif | |
910 | ||
88b094fb | 911 | init_hypervisor(c); |
49d859d7 | 912 | x86_init_rdrand(c); |
3e0c3737 YL |
913 | |
914 | /* | |
915 | * Clear/Set all flags overriden by options, need do it | |
916 | * before following smp all cpus cap AND. | |
917 | */ | |
918 | for (i = 0; i < NCAPINTS; i++) { | |
919 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
920 | c->x86_capability[i] |= cpu_caps_set[i]; | |
921 | } | |
922 | ||
1da177e4 LT |
923 | /* |
924 | * On SMP, boot_cpu_data holds the common feature set between | |
925 | * all CPUs; so make sure that we indicate which features are | |
926 | * common between the CPUs. The first time this routine gets | |
927 | * executed, c == &boot_cpu_data. | |
928 | */ | |
34048c9e | 929 | if (c != &boot_cpu_data) { |
1da177e4 | 930 | /* AND the already accumulated flags with these */ |
9d31d35b | 931 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 | 932 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
65fc985b BP |
933 | |
934 | /* OR, i.e. replicate the bug flags */ | |
935 | for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) | |
936 | c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; | |
1da177e4 LT |
937 | } |
938 | ||
939 | /* Init Machine Check Exception if available. */ | |
5e09954a | 940 | mcheck_cpu_init(c); |
30d432df AK |
941 | |
942 | select_idle_routine(c); | |
102bbe3a | 943 | |
de2d9445 | 944 | #ifdef CONFIG_NUMA |
102bbe3a YL |
945 | numa_add_cpu(smp_processor_id()); |
946 | #endif | |
a6c4e076 | 947 | } |
31ab269a | 948 | |
e04d645f GC |
949 | #ifdef CONFIG_X86_64 |
950 | static void vgetcpu_set_mode(void) | |
951 | { | |
952 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
953 | vgetcpu_mode = VGETCPU_RDTSCP; | |
954 | else | |
955 | vgetcpu_mode = VGETCPU_LSL; | |
956 | } | |
cfda7bb9 AL |
957 | |
958 | /* May not be __init: called during resume */ | |
959 | static void syscall32_cpu_init(void) | |
960 | { | |
961 | /* Load these always in case some future AMD CPU supports | |
962 | SYSENTER from compat mode too. */ | |
963 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); | |
964 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); | |
965 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)ia32_sysenter_target); | |
966 | ||
967 | wrmsrl(MSR_CSTAR, ia32_cstar_target); | |
968 | } | |
969 | #endif | |
970 | ||
971 | #ifdef CONFIG_X86_32 | |
972 | void enable_sep_cpu(void) | |
973 | { | |
974 | int cpu = get_cpu(); | |
975 | struct tss_struct *tss = &per_cpu(init_tss, cpu); | |
976 | ||
977 | if (!boot_cpu_has(X86_FEATURE_SEP)) { | |
978 | put_cpu(); | |
979 | return; | |
980 | } | |
981 | ||
982 | tss->x86_tss.ss1 = __KERNEL_CS; | |
983 | tss->x86_tss.sp1 = sizeof(struct tss_struct) + (unsigned long) tss; | |
984 | wrmsr(MSR_IA32_SYSENTER_CS, __KERNEL_CS, 0); | |
985 | wrmsr(MSR_IA32_SYSENTER_ESP, tss->x86_tss.sp1, 0); | |
986 | wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long) ia32_sysenter_target, 0); | |
987 | put_cpu(); | |
988 | } | |
e04d645f GC |
989 | #endif |
990 | ||
a6c4e076 JF |
991 | void __init identify_boot_cpu(void) |
992 | { | |
993 | identify_cpu(&boot_cpu_data); | |
02c68a02 | 994 | init_amd_e400_c1e_mask(); |
102bbe3a | 995 | #ifdef CONFIG_X86_32 |
a6c4e076 | 996 | sysenter_setup(); |
6fe940d6 | 997 | enable_sep_cpu(); |
e04d645f GC |
998 | #else |
999 | vgetcpu_set_mode(); | |
102bbe3a | 1000 | #endif |
5b556332 | 1001 | cpu_detect_tlb(&boot_cpu_data); |
a6c4e076 | 1002 | } |
3b520b23 | 1003 | |
148f9bb8 | 1004 | void identify_secondary_cpu(struct cpuinfo_x86 *c) |
a6c4e076 JF |
1005 | { |
1006 | BUG_ON(c == &boot_cpu_data); | |
1007 | identify_cpu(c); | |
102bbe3a | 1008 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1009 | enable_sep_cpu(); |
102bbe3a | 1010 | #endif |
a6c4e076 | 1011 | mtrr_ap_init(); |
1da177e4 LT |
1012 | } |
1013 | ||
a0854a46 | 1014 | struct msr_range { |
0f3fa48a IM |
1015 | unsigned min; |
1016 | unsigned max; | |
a0854a46 | 1017 | }; |
1da177e4 | 1018 | |
148f9bb8 | 1019 | static const struct msr_range msr_range_array[] = { |
a0854a46 YL |
1020 | { 0x00000000, 0x00000418}, |
1021 | { 0xc0000000, 0xc000040b}, | |
1022 | { 0xc0010000, 0xc0010142}, | |
1023 | { 0xc0011000, 0xc001103b}, | |
1024 | }; | |
1da177e4 | 1025 | |
148f9bb8 | 1026 | static void __print_cpu_msr(void) |
a0854a46 | 1027 | { |
0f3fa48a | 1028 | unsigned index_min, index_max; |
a0854a46 YL |
1029 | unsigned index; |
1030 | u64 val; | |
1031 | int i; | |
a0854a46 YL |
1032 | |
1033 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
1034 | index_min = msr_range_array[i].min; | |
1035 | index_max = msr_range_array[i].max; | |
0f3fa48a | 1036 | |
a0854a46 | 1037 | for (index = index_min; index < index_max; index++) { |
ecd431d9 | 1038 | if (rdmsrl_safe(index, &val)) |
a0854a46 YL |
1039 | continue; |
1040 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 1041 | } |
a0854a46 YL |
1042 | } |
1043 | } | |
94605eff | 1044 | |
148f9bb8 | 1045 | static int show_msr; |
0f3fa48a | 1046 | |
a0854a46 YL |
1047 | static __init int setup_show_msr(char *arg) |
1048 | { | |
1049 | int num; | |
3dd9d514 | 1050 | |
a0854a46 | 1051 | get_option(&arg, &num); |
3dd9d514 | 1052 | |
a0854a46 YL |
1053 | if (num > 0) |
1054 | show_msr = num; | |
1055 | return 1; | |
1da177e4 | 1056 | } |
a0854a46 | 1057 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 1058 | |
191679fd AK |
1059 | static __init int setup_noclflush(char *arg) |
1060 | { | |
840d2830 | 1061 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); |
da4aaa7d | 1062 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); |
191679fd AK |
1063 | return 1; |
1064 | } | |
1065 | __setup("noclflush", setup_noclflush); | |
1066 | ||
148f9bb8 | 1067 | void print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1068 | { |
02dde8b4 | 1069 | const char *vendor = NULL; |
1da177e4 | 1070 | |
0f3fa48a | 1071 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1072 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1073 | } else { |
1074 | if (c->cpuid_level >= 0) | |
1075 | vendor = c->x86_vendor_id; | |
1076 | } | |
1da177e4 | 1077 | |
bd32a8cf | 1078 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 1079 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 1080 | |
9d31d35b | 1081 | if (c->x86_model_id[0]) |
924e101a | 1082 | printk(KERN_CONT "%s", strim(c->x86_model_id)); |
1da177e4 | 1083 | else |
9d31d35b | 1084 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 1085 | |
924e101a BP |
1086 | printk(KERN_CONT " (fam: %02x, model: %02x", c->x86, c->x86_model); |
1087 | ||
34048c9e | 1088 | if (c->x86_mask || c->cpuid_level >= 0) |
924e101a | 1089 | printk(KERN_CONT ", stepping: %02x)\n", c->x86_mask); |
1da177e4 | 1090 | else |
924e101a | 1091 | printk(KERN_CONT ")\n"); |
a0854a46 | 1092 | |
0b8b8078 | 1093 | print_cpu_msr(c); |
21c3fcf3 YL |
1094 | } |
1095 | ||
148f9bb8 | 1096 | void print_cpu_msr(struct cpuinfo_x86 *c) |
21c3fcf3 | 1097 | { |
a0854a46 | 1098 | if (c->cpu_index < show_msr) |
21c3fcf3 | 1099 | __print_cpu_msr(); |
1da177e4 LT |
1100 | } |
1101 | ||
ac72e788 AK |
1102 | static __init int setup_disablecpuid(char *arg) |
1103 | { | |
1104 | int bit; | |
0f3fa48a | 1105 | |
ac72e788 AK |
1106 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) |
1107 | setup_clear_cpu_cap(bit); | |
1108 | else | |
1109 | return 0; | |
0f3fa48a | 1110 | |
ac72e788 AK |
1111 | return 1; |
1112 | } | |
1113 | __setup("clearcpuid=", setup_disablecpuid); | |
1114 | ||
198d208d SR |
1115 | DEFINE_PER_CPU(unsigned long, kernel_stack) = |
1116 | (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; | |
1117 | EXPORT_PER_CPU_SYMBOL(kernel_stack); | |
1118 | ||
d5494d4f | 1119 | #ifdef CONFIG_X86_64 |
9ff80942 | 1120 | struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; |
629f4f9d SA |
1121 | struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1, |
1122 | (unsigned long) debug_idt_table }; | |
d5494d4f | 1123 | |
947e76cd | 1124 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
277d5b40 | 1125 | irq_stack_union) __aligned(PAGE_SIZE) __visible; |
0f3fa48a | 1126 | |
bdf977b3 TH |
1127 | /* |
1128 | * The following four percpu variables are hot. Align current_task to | |
1129 | * cacheline size such that all four fall in the same cacheline. | |
1130 | */ | |
1131 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1132 | &init_task; | |
1133 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1134 | |
bdf977b3 TH |
1135 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
1136 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; | |
1137 | ||
277d5b40 | 1138 | DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; |
d5494d4f | 1139 | |
c2daa3be PZ |
1140 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1141 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
1142 | ||
7e16838d LT |
1143 | DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); |
1144 | ||
0f3fa48a IM |
1145 | /* |
1146 | * Special IST stacks which the CPU switches to when it calls | |
1147 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
1148 | * limit), all of them are 4K, except the debug stack which | |
1149 | * is 8K. | |
1150 | */ | |
1151 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
1152 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1153 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1154 | }; | |
1155 | ||
92d65b23 | 1156 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
3e352aa8 | 1157 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); |
d5494d4f | 1158 | |
d5494d4f YL |
1159 | /* May not be marked __init: used by software suspend */ |
1160 | void syscall_init(void) | |
1da177e4 | 1161 | { |
d5494d4f YL |
1162 | /* |
1163 | * LSTAR and STAR live in a bit strange symbiosis. | |
1164 | * They both write to the same internal register. STAR allows to | |
1165 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
1166 | */ | |
1167 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
1168 | wrmsrl(MSR_LSTAR, system_call); | |
1169 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 1170 | |
d5494d4f YL |
1171 | #ifdef CONFIG_IA32_EMULATION |
1172 | syscall32_cpu_init(); | |
1173 | #endif | |
03ae5768 | 1174 | |
d5494d4f YL |
1175 | /* Flags to clear on syscall */ |
1176 | wrmsrl(MSR_SYSCALL_MASK, | |
63bcff2a PA |
1177 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| |
1178 | X86_EFLAGS_IOPL|X86_EFLAGS_AC); | |
1da177e4 | 1179 | } |
62111195 | 1180 | |
d5494d4f YL |
1181 | /* |
1182 | * Copies of the original ist values from the tss are only accessed during | |
1183 | * debugging, no special alignment required. | |
1184 | */ | |
1185 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1186 | ||
228bdaa9 | 1187 | static DEFINE_PER_CPU(unsigned long, debug_stack_addr); |
42181186 | 1188 | DEFINE_PER_CPU(int, debug_stack_usage); |
228bdaa9 SR |
1189 | |
1190 | int is_debug_stack(unsigned long addr) | |
1191 | { | |
42181186 SR |
1192 | return __get_cpu_var(debug_stack_usage) || |
1193 | (addr <= __get_cpu_var(debug_stack_addr) && | |
1194 | addr > (__get_cpu_var(debug_stack_addr) - DEBUG_STKSZ)); | |
228bdaa9 SR |
1195 | } |
1196 | ||
629f4f9d | 1197 | DEFINE_PER_CPU(u32, debug_idt_ctr); |
f8988175 | 1198 | |
228bdaa9 SR |
1199 | void debug_stack_set_zero(void) |
1200 | { | |
629f4f9d SA |
1201 | this_cpu_inc(debug_idt_ctr); |
1202 | load_current_idt(); | |
228bdaa9 SR |
1203 | } |
1204 | ||
1205 | void debug_stack_reset(void) | |
1206 | { | |
629f4f9d | 1207 | if (WARN_ON(!this_cpu_read(debug_idt_ctr))) |
f8988175 | 1208 | return; |
629f4f9d SA |
1209 | if (this_cpu_dec_return(debug_idt_ctr) == 0) |
1210 | load_current_idt(); | |
228bdaa9 SR |
1211 | } |
1212 | ||
0f3fa48a | 1213 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1214 | |
bdf977b3 TH |
1215 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1216 | EXPORT_PER_CPU_SYMBOL(current_task); | |
c2daa3be PZ |
1217 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1218 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
27e74da9 | 1219 | DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); |
bdf977b3 | 1220 | |
60a5317f | 1221 | #ifdef CONFIG_CC_STACKPROTECTOR |
53f82452 | 1222 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1223 | #endif |
d5494d4f | 1224 | |
0f3fa48a | 1225 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1226 | |
9766cdbc JSR |
1227 | /* |
1228 | * Clear all 6 debug registers: | |
1229 | */ | |
1230 | static void clear_all_debug_regs(void) | |
1231 | { | |
1232 | int i; | |
1233 | ||
1234 | for (i = 0; i < 8; i++) { | |
1235 | /* Ignore db4, db5 */ | |
1236 | if ((i == 4) || (i == 5)) | |
1237 | continue; | |
1238 | ||
1239 | set_debugreg(0, i); | |
1240 | } | |
1241 | } | |
c5413fbe | 1242 | |
0bb9fef9 JW |
1243 | #ifdef CONFIG_KGDB |
1244 | /* | |
1245 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1246 | * connection established. | |
1247 | */ | |
1248 | static void dbg_restore_debug_regs(void) | |
1249 | { | |
1250 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1251 | arch_kgdb_ops.correct_hw_break(); | |
1252 | } | |
1253 | #else /* ! CONFIG_KGDB */ | |
1254 | #define dbg_restore_debug_regs() | |
1255 | #endif /* ! CONFIG_KGDB */ | |
1256 | ||
d2cbcc49 RR |
1257 | /* |
1258 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1259 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1260 | * and IDT. We reload them nevertheless, this function acts as a | |
1261 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1262 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1263 | */ |
1ba76586 | 1264 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1265 | |
148f9bb8 | 1266 | void cpu_init(void) |
1ba76586 | 1267 | { |
0fe1e009 | 1268 | struct orig_ist *oist; |
1ba76586 | 1269 | struct task_struct *me; |
0f3fa48a IM |
1270 | struct tss_struct *t; |
1271 | unsigned long v; | |
1272 | int cpu; | |
1ba76586 YL |
1273 | int i; |
1274 | ||
e6ebf5de FY |
1275 | /* |
1276 | * Load microcode on this cpu if a valid microcode is available. | |
1277 | * This is early microcode loading procedure. | |
1278 | */ | |
1279 | load_ucode_ap(); | |
1280 | ||
0f3fa48a IM |
1281 | cpu = stack_smp_processor_id(); |
1282 | t = &per_cpu(init_tss, cpu); | |
0fe1e009 | 1283 | oist = &per_cpu(orig_ist, cpu); |
0f3fa48a | 1284 | |
e7a22c1e | 1285 | #ifdef CONFIG_NUMA |
27fd185f | 1286 | if (this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
1287 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
1288 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1289 | #endif |
1ba76586 YL |
1290 | |
1291 | me = current; | |
1292 | ||
c2d1cec1 | 1293 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) |
1ba76586 YL |
1294 | panic("CPU#%d already initialized!\n", cpu); |
1295 | ||
2eaad1fd | 1296 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 YL |
1297 | |
1298 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1299 | ||
1300 | /* | |
1301 | * Initialize the per-CPU GDT with the boot GDT, | |
1302 | * and set up the GDT descriptor: | |
1303 | */ | |
1304 | ||
552be871 | 1305 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1306 | loadsegment(fs, 0); |
1307 | ||
cf910e83 | 1308 | load_current_idt(); |
1ba76586 YL |
1309 | |
1310 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1311 | syscall_init(); | |
1312 | ||
1313 | wrmsrl(MSR_FS_BASE, 0); | |
1314 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1315 | barrier(); | |
1316 | ||
4763ed4d | 1317 | x86_configure_nx(); |
27fd185f | 1318 | enable_x2apic(); |
1ba76586 YL |
1319 | |
1320 | /* | |
1321 | * set up and load the per-CPU TSS | |
1322 | */ | |
0fe1e009 | 1323 | if (!oist->ist[0]) { |
92d65b23 | 1324 | char *estacks = per_cpu(exception_stacks, cpu); |
0f3fa48a | 1325 | |
1ba76586 | 1326 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
0f3fa48a | 1327 | estacks += exception_stack_sizes[v]; |
0fe1e009 | 1328 | oist->ist[v] = t->x86_tss.ist[v] = |
1ba76586 | 1329 | (unsigned long)estacks; |
228bdaa9 SR |
1330 | if (v == DEBUG_STACK-1) |
1331 | per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; | |
1ba76586 YL |
1332 | } |
1333 | } | |
1334 | ||
1335 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
0f3fa48a | 1336 | |
1ba76586 YL |
1337 | /* |
1338 | * <= is required because the CPU will access up to | |
1339 | * 8 bits beyond the end of the IO permission bitmap. | |
1340 | */ | |
1341 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1342 | t->io_bitmap[i] = ~0UL; | |
1343 | ||
1344 | atomic_inc(&init_mm.mm_count); | |
1345 | me->active_mm = &init_mm; | |
8c5dfd25 | 1346 | BUG_ON(me->mm); |
1ba76586 YL |
1347 | enter_lazy_tlb(&init_mm, me); |
1348 | ||
1349 | load_sp0(t, ¤t->thread); | |
1350 | set_tss_desc(cpu, t); | |
1351 | load_TR_desc(); | |
1352 | load_LDT(&init_mm.context); | |
1353 | ||
0bb9fef9 JW |
1354 | clear_all_debug_regs(); |
1355 | dbg_restore_debug_regs(); | |
1ba76586 YL |
1356 | |
1357 | fpu_init(); | |
1358 | ||
1ba76586 YL |
1359 | if (is_uv_system()) |
1360 | uv_cpu_init(); | |
1361 | } | |
1362 | ||
1363 | #else | |
1364 | ||
148f9bb8 | 1365 | void cpu_init(void) |
9ee79a3d | 1366 | { |
d2cbcc49 RR |
1367 | int cpu = smp_processor_id(); |
1368 | struct task_struct *curr = current; | |
34048c9e | 1369 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1370 | struct thread_struct *thread = &curr->thread; |
62111195 | 1371 | |
e6ebf5de FY |
1372 | show_ucode_info_early(); |
1373 | ||
c2d1cec1 | 1374 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { |
62111195 | 1375 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); |
9766cdbc JSR |
1376 | for (;;) |
1377 | local_irq_enable(); | |
62111195 JF |
1378 | } |
1379 | ||
1380 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1381 | ||
1382 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1383 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1384 | |
cf910e83 | 1385 | load_current_idt(); |
552be871 | 1386 | switch_to_new_gdt(cpu); |
1da177e4 | 1387 | |
1da177e4 LT |
1388 | /* |
1389 | * Set up and load the per-CPU TSS and LDT | |
1390 | */ | |
1391 | atomic_inc(&init_mm.mm_count); | |
62111195 | 1392 | curr->active_mm = &init_mm; |
8c5dfd25 | 1393 | BUG_ON(curr->mm); |
62111195 | 1394 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1395 | |
faca6227 | 1396 | load_sp0(t, thread); |
34048c9e | 1397 | set_tss_desc(cpu, t); |
1da177e4 LT |
1398 | load_TR_desc(); |
1399 | load_LDT(&init_mm.context); | |
1400 | ||
f9a196b8 TG |
1401 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); |
1402 | ||
22c4e308 | 1403 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1404 | /* Set up doublefault TSS pointer in the GDT */ |
1405 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1406 | #endif |
1da177e4 | 1407 | |
9766cdbc | 1408 | clear_all_debug_regs(); |
0bb9fef9 | 1409 | dbg_restore_debug_regs(); |
1da177e4 | 1410 | |
0e49bf66 | 1411 | fpu_init(); |
1da177e4 | 1412 | } |
1ba76586 | 1413 | #endif |
5700f743 BP |
1414 | |
1415 | #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS | |
1416 | void warn_pre_alternatives(void) | |
1417 | { | |
1418 | WARN(1, "You're using static_cpu_has before alternatives have run!\n"); | |
1419 | } | |
1420 | EXPORT_SYMBOL_GPL(warn_pre_alternatives); | |
1421 | #endif | |
4a90a99c BP |
1422 | |
1423 | inline bool __static_cpu_has_safe(u16 bit) | |
1424 | { | |
1425 | return boot_cpu_has(bit); | |
1426 | } | |
1427 | EXPORT_SYMBOL_GPL(__static_cpu_has_safe); |