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Commit | Line | Data |
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f0fc4aff | 1 | #include <linux/bootmem.h> |
9766cdbc | 2 | #include <linux/linkage.h> |
f0fc4aff | 3 | #include <linux/bitops.h> |
9766cdbc | 4 | #include <linux/kernel.h> |
f0fc4aff | 5 | #include <linux/module.h> |
9766cdbc JSR |
6 | #include <linux/percpu.h> |
7 | #include <linux/string.h> | |
1da177e4 | 8 | #include <linux/delay.h> |
9766cdbc JSR |
9 | #include <linux/sched.h> |
10 | #include <linux/init.h> | |
0f46efeb | 11 | #include <linux/kprobes.h> |
9766cdbc | 12 | #include <linux/kgdb.h> |
1da177e4 | 13 | #include <linux/smp.h> |
9766cdbc JSR |
14 | #include <linux/io.h> |
15 | ||
16 | #include <asm/stackprotector.h> | |
cdd6c482 | 17 | #include <asm/perf_event.h> |
1da177e4 | 18 | #include <asm/mmu_context.h> |
49d859d7 | 19 | #include <asm/archrandom.h> |
9766cdbc JSR |
20 | #include <asm/hypervisor.h> |
21 | #include <asm/processor.h> | |
1e02ce4c | 22 | #include <asm/tlbflush.h> |
f649e938 | 23 | #include <asm/debugreg.h> |
9766cdbc | 24 | #include <asm/sections.h> |
f40c3300 | 25 | #include <asm/vsyscall.h> |
8bdbd962 AC |
26 | #include <linux/topology.h> |
27 | #include <linux/cpumask.h> | |
9766cdbc | 28 | #include <asm/pgtable.h> |
60063497 | 29 | #include <linux/atomic.h> |
9766cdbc JSR |
30 | #include <asm/proto.h> |
31 | #include <asm/setup.h> | |
32 | #include <asm/apic.h> | |
33 | #include <asm/desc.h> | |
34 | #include <asm/i387.h> | |
1361b83a | 35 | #include <asm/fpu-internal.h> |
27b07da7 | 36 | #include <asm/mtrr.h> |
8bdbd962 | 37 | #include <linux/numa.h> |
9766cdbc JSR |
38 | #include <asm/asm.h> |
39 | #include <asm/cpu.h> | |
a03a3e28 | 40 | #include <asm/mce.h> |
9766cdbc | 41 | #include <asm/msr.h> |
8d4a4300 | 42 | #include <asm/pat.h> |
d288e1cf FY |
43 | #include <asm/microcode.h> |
44 | #include <asm/microcode_intel.h> | |
e641f5f5 IM |
45 | |
46 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 47 | #include <asm/uv/uv.h> |
1da177e4 LT |
48 | #endif |
49 | ||
50 | #include "cpu.h" | |
51 | ||
c2d1cec1 | 52 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 53 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
54 | cpumask_var_t cpu_callout_mask; |
55 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
56 | |
57 | /* representing cpus for which sibling maps can be computed */ | |
58 | cpumask_var_t cpu_sibling_setup_mask; | |
59 | ||
2f2f52ba | 60 | /* correctly size the local cpu masks */ |
4369f1fb | 61 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
62 | { |
63 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
64 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
65 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
66 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
67 | } | |
68 | ||
148f9bb8 | 69 | static void default_init(struct cpuinfo_x86 *c) |
e8055139 OZ |
70 | { |
71 | #ifdef CONFIG_X86_64 | |
27c13ece | 72 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
73 | #else |
74 | /* Not much we can do here... */ | |
75 | /* Check if at least it has cpuid */ | |
76 | if (c->cpuid_level == -1) { | |
77 | /* No cpuid. It must be an ancient CPU */ | |
78 | if (c->x86 == 4) | |
79 | strcpy(c->x86_model_id, "486"); | |
80 | else if (c->x86 == 3) | |
81 | strcpy(c->x86_model_id, "386"); | |
82 | } | |
83 | #endif | |
84 | } | |
85 | ||
148f9bb8 | 86 | static const struct cpu_dev default_cpu = { |
e8055139 OZ |
87 | .c_init = default_init, |
88 | .c_vendor = "Unknown", | |
89 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
90 | }; | |
91 | ||
148f9bb8 | 92 | static const struct cpu_dev *this_cpu = &default_cpu; |
0a488a53 | 93 | |
06deef89 | 94 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 95 | #ifdef CONFIG_X86_64 |
06deef89 BG |
96 | /* |
97 | * We need valid kernel segments for data and code in long mode too | |
98 | * IRET will check the segment types kkeil 2000/10/28 | |
99 | * Also sysret mandates a special GDT layout | |
100 | * | |
9766cdbc | 101 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
102 | * Hopefully nobody expects them at a fixed place (Wine?) |
103 | */ | |
1e5de182 AM |
104 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
105 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
106 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
107 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
108 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
109 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 110 | #else |
1e5de182 AM |
111 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
112 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
113 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
114 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
115 | /* |
116 | * Segments used for calling PnP BIOS have byte granularity. | |
117 | * They code segments and data segments have fixed 64k limits, | |
118 | * the transfer segment sizes are set at run time. | |
119 | */ | |
6842ef0e | 120 | /* 32-bit code */ |
1e5de182 | 121 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 122 | /* 16-bit code */ |
1e5de182 | 123 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 124 | /* 16-bit data */ |
1e5de182 | 125 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 126 | /* 16-bit data */ |
1e5de182 | 127 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 128 | /* 16-bit data */ |
1e5de182 | 129 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
130 | /* |
131 | * The APM segments have byte granularity and their bases | |
132 | * are set at run time. All have 64k limits. | |
133 | */ | |
6842ef0e | 134 | /* 32-bit code */ |
1e5de182 | 135 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 136 | /* 16-bit code */ |
1e5de182 | 137 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 138 | /* data */ |
72c4d853 | 139 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 140 | |
1e5de182 AM |
141 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
142 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 143 | GDT_STACK_CANARY_INIT |
950ad7ff | 144 | #endif |
06deef89 | 145 | } }; |
7a61d35d | 146 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 147 | |
0c752a93 SS |
148 | static int __init x86_xsave_setup(char *s) |
149 | { | |
2cd3949f DH |
150 | if (strlen(s)) |
151 | return 0; | |
0c752a93 | 152 | setup_clear_cpu_cap(X86_FEATURE_XSAVE); |
6bad06b7 | 153 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); |
b6f42a4a | 154 | setup_clear_cpu_cap(X86_FEATURE_XSAVES); |
c6fd893d SS |
155 | setup_clear_cpu_cap(X86_FEATURE_AVX); |
156 | setup_clear_cpu_cap(X86_FEATURE_AVX2); | |
0c752a93 SS |
157 | return 1; |
158 | } | |
159 | __setup("noxsave", x86_xsave_setup); | |
160 | ||
6bad06b7 SS |
161 | static int __init x86_xsaveopt_setup(char *s) |
162 | { | |
163 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); | |
164 | return 1; | |
165 | } | |
166 | __setup("noxsaveopt", x86_xsaveopt_setup); | |
167 | ||
b6f42a4a FY |
168 | static int __init x86_xsaves_setup(char *s) |
169 | { | |
170 | setup_clear_cpu_cap(X86_FEATURE_XSAVES); | |
171 | return 1; | |
172 | } | |
173 | __setup("noxsaves", x86_xsaves_setup); | |
174 | ||
ba51dced | 175 | #ifdef CONFIG_X86_32 |
148f9bb8 PG |
176 | static int cachesize_override = -1; |
177 | static int disable_x86_serial_nr = 1; | |
1da177e4 | 178 | |
0a488a53 YL |
179 | static int __init cachesize_setup(char *str) |
180 | { | |
181 | get_option(&str, &cachesize_override); | |
182 | return 1; | |
183 | } | |
184 | __setup("cachesize=", cachesize_setup); | |
185 | ||
0a488a53 YL |
186 | static int __init x86_fxsr_setup(char *s) |
187 | { | |
188 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
189 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
190 | return 1; | |
191 | } | |
192 | __setup("nofxsr", x86_fxsr_setup); | |
193 | ||
194 | static int __init x86_sep_setup(char *s) | |
195 | { | |
196 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
197 | return 1; | |
198 | } | |
199 | __setup("nosep", x86_sep_setup); | |
200 | ||
201 | /* Standard macro to see if a specific flag is changeable */ | |
202 | static inline int flag_is_changeable_p(u32 flag) | |
203 | { | |
204 | u32 f1, f2; | |
205 | ||
94f6bac1 KH |
206 | /* |
207 | * Cyrix and IDT cpus allow disabling of CPUID | |
208 | * so the code below may return different results | |
209 | * when it is executed before and after enabling | |
210 | * the CPUID. Add "volatile" to not allow gcc to | |
211 | * optimize the subsequent calls to this function. | |
212 | */ | |
0f3fa48a IM |
213 | asm volatile ("pushfl \n\t" |
214 | "pushfl \n\t" | |
215 | "popl %0 \n\t" | |
216 | "movl %0, %1 \n\t" | |
217 | "xorl %2, %0 \n\t" | |
218 | "pushl %0 \n\t" | |
219 | "popfl \n\t" | |
220 | "pushfl \n\t" | |
221 | "popl %0 \n\t" | |
222 | "popfl \n\t" | |
223 | ||
94f6bac1 KH |
224 | : "=&r" (f1), "=&r" (f2) |
225 | : "ir" (flag)); | |
0a488a53 YL |
226 | |
227 | return ((f1^f2) & flag) != 0; | |
228 | } | |
229 | ||
230 | /* Probe for the CPUID instruction */ | |
148f9bb8 | 231 | int have_cpuid_p(void) |
0a488a53 YL |
232 | { |
233 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
234 | } | |
235 | ||
148f9bb8 | 236 | static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
0a488a53 | 237 | { |
0f3fa48a IM |
238 | unsigned long lo, hi; |
239 | ||
240 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
241 | return; | |
242 | ||
243 | /* Disable processor serial number: */ | |
244 | ||
245 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
246 | lo |= 0x200000; | |
247 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
248 | ||
249 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
250 | clear_cpu_cap(c, X86_FEATURE_PN); | |
251 | ||
252 | /* Disabling the serial number may affect the cpuid level */ | |
253 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
254 | } |
255 | ||
256 | static int __init x86_serial_nr_setup(char *s) | |
257 | { | |
258 | disable_x86_serial_nr = 0; | |
259 | return 1; | |
260 | } | |
261 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 262 | #else |
102bbe3a YL |
263 | static inline int flag_is_changeable_p(u32 flag) |
264 | { | |
265 | return 1; | |
266 | } | |
102bbe3a YL |
267 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
268 | { | |
269 | } | |
ba51dced | 270 | #endif |
0a488a53 | 271 | |
de5397ad FY |
272 | static __init int setup_disable_smep(char *arg) |
273 | { | |
b2cc2a07 | 274 | setup_clear_cpu_cap(X86_FEATURE_SMEP); |
de5397ad FY |
275 | return 1; |
276 | } | |
277 | __setup("nosmep", setup_disable_smep); | |
278 | ||
b2cc2a07 | 279 | static __always_inline void setup_smep(struct cpuinfo_x86 *c) |
de5397ad | 280 | { |
b2cc2a07 | 281 | if (cpu_has(c, X86_FEATURE_SMEP)) |
375074cc | 282 | cr4_set_bits(X86_CR4_SMEP); |
de5397ad FY |
283 | } |
284 | ||
52b6179a PA |
285 | static __init int setup_disable_smap(char *arg) |
286 | { | |
b2cc2a07 | 287 | setup_clear_cpu_cap(X86_FEATURE_SMAP); |
52b6179a PA |
288 | return 1; |
289 | } | |
290 | __setup("nosmap", setup_disable_smap); | |
291 | ||
b2cc2a07 PA |
292 | static __always_inline void setup_smap(struct cpuinfo_x86 *c) |
293 | { | |
294 | unsigned long eflags; | |
295 | ||
296 | /* This should have been cleared long ago */ | |
297 | raw_local_save_flags(eflags); | |
298 | BUG_ON(eflags & X86_EFLAGS_AC); | |
299 | ||
03bbd596 PA |
300 | if (cpu_has(c, X86_FEATURE_SMAP)) { |
301 | #ifdef CONFIG_X86_SMAP | |
375074cc | 302 | cr4_set_bits(X86_CR4_SMAP); |
03bbd596 | 303 | #else |
375074cc | 304 | cr4_clear_bits(X86_CR4_SMAP); |
03bbd596 PA |
305 | #endif |
306 | } | |
de5397ad FY |
307 | } |
308 | ||
b38b0665 PA |
309 | /* |
310 | * Some CPU features depend on higher CPUID levels, which may not always | |
311 | * be available due to CPUID level capping or broken virtualization | |
312 | * software. Add those features to this table to auto-disable them. | |
313 | */ | |
314 | struct cpuid_dependent_feature { | |
315 | u32 feature; | |
316 | u32 level; | |
317 | }; | |
0f3fa48a | 318 | |
148f9bb8 | 319 | static const struct cpuid_dependent_feature |
b38b0665 PA |
320 | cpuid_dependent_features[] = { |
321 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
322 | { X86_FEATURE_DCA, 0x00000009 }, | |
323 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
324 | { 0, 0 } | |
325 | }; | |
326 | ||
148f9bb8 | 327 | static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) |
b38b0665 PA |
328 | { |
329 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 330 | |
b38b0665 | 331 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
332 | |
333 | if (!cpu_has(c, df->feature)) | |
334 | continue; | |
b38b0665 PA |
335 | /* |
336 | * Note: cpuid_level is set to -1 if unavailable, but | |
337 | * extended_extended_level is set to 0 if unavailable | |
338 | * and the legitimate extended levels are all negative | |
339 | * when signed; hence the weird messing around with | |
340 | * signs here... | |
341 | */ | |
0f3fa48a | 342 | if (!((s32)df->level < 0 ? |
f6db44df | 343 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
344 | (s32)df->level > (s32)c->cpuid_level)) |
345 | continue; | |
346 | ||
347 | clear_cpu_cap(c, df->feature); | |
348 | if (!warn) | |
349 | continue; | |
350 | ||
351 | printk(KERN_WARNING | |
9def39be JT |
352 | "CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", |
353 | x86_cap_flag(df->feature), df->level); | |
b38b0665 | 354 | } |
f6db44df | 355 | } |
b38b0665 | 356 | |
102bbe3a YL |
357 | /* |
358 | * Naming convention should be: <Name> [(<Codename>)] | |
359 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
360 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
361 | * isn't used | |
102bbe3a YL |
362 | */ |
363 | ||
364 | /* Look up CPU names by table lookup. */ | |
148f9bb8 | 365 | static const char *table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 366 | { |
09dc68d9 JB |
367 | #ifdef CONFIG_X86_32 |
368 | const struct legacy_cpu_model_info *info; | |
102bbe3a YL |
369 | |
370 | if (c->x86_model >= 16) | |
371 | return NULL; /* Range check */ | |
372 | ||
373 | if (!this_cpu) | |
374 | return NULL; | |
375 | ||
09dc68d9 | 376 | info = this_cpu->legacy_models; |
102bbe3a | 377 | |
09dc68d9 | 378 | while (info->family) { |
102bbe3a YL |
379 | if (info->family == c->x86) |
380 | return info->model_names[c->x86_model]; | |
381 | info++; | |
382 | } | |
09dc68d9 | 383 | #endif |
102bbe3a YL |
384 | return NULL; /* Not found */ |
385 | } | |
386 | ||
148f9bb8 PG |
387 | __u32 cpu_caps_cleared[NCAPINTS]; |
388 | __u32 cpu_caps_set[NCAPINTS]; | |
7d851c8d | 389 | |
11e3a840 JF |
390 | void load_percpu_segment(int cpu) |
391 | { | |
392 | #ifdef CONFIG_X86_32 | |
393 | loadsegment(fs, __KERNEL_PERCPU); | |
394 | #else | |
395 | loadsegment(gs, 0); | |
396 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
397 | #endif | |
60a5317f | 398 | load_stack_canary_segment(); |
11e3a840 JF |
399 | } |
400 | ||
0f3fa48a IM |
401 | /* |
402 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
403 | * it's on the real one. | |
404 | */ | |
552be871 | 405 | void switch_to_new_gdt(int cpu) |
9d31d35b YL |
406 | { |
407 | struct desc_ptr gdt_descr; | |
408 | ||
2697fbd5 | 409 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
410 | gdt_descr.size = GDT_SIZE - 1; |
411 | load_gdt(&gdt_descr); | |
2697fbd5 | 412 | /* Reload the per-cpu base */ |
11e3a840 JF |
413 | |
414 | load_percpu_segment(cpu); | |
9d31d35b YL |
415 | } |
416 | ||
148f9bb8 | 417 | static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 418 | |
148f9bb8 | 419 | static void get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
420 | { |
421 | unsigned int *v; | |
422 | char *p, *q; | |
423 | ||
3da99c97 | 424 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 425 | return; |
1da177e4 | 426 | |
0f3fa48a | 427 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
428 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
429 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
430 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
431 | c->x86_model_id[48] = 0; | |
432 | ||
0f3fa48a IM |
433 | /* |
434 | * Intel chips right-justify this string for some dumb reason; | |
435 | * undo that brain damage: | |
436 | */ | |
1da177e4 | 437 | p = q = &c->x86_model_id[0]; |
34048c9e | 438 | while (*p == ' ') |
9766cdbc | 439 | p++; |
34048c9e | 440 | if (p != q) { |
9766cdbc JSR |
441 | while (*p) |
442 | *q++ = *p++; | |
443 | while (q <= &c->x86_model_id[48]) | |
444 | *q++ = '\0'; /* Zero-pad the rest */ | |
1da177e4 | 445 | } |
1da177e4 LT |
446 | } |
447 | ||
148f9bb8 | 448 | void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 449 | { |
9d31d35b | 450 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 451 | |
3da99c97 | 452 | n = c->extended_cpuid_level; |
1da177e4 LT |
453 | |
454 | if (n >= 0x80000005) { | |
9d31d35b | 455 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 456 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
457 | #ifdef CONFIG_X86_64 |
458 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
459 | c->x86_tlbsize = 0; | |
460 | #endif | |
1da177e4 LT |
461 | } |
462 | ||
463 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
464 | return; | |
465 | ||
0a488a53 | 466 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 467 | l2size = ecx >> 16; |
34048c9e | 468 | |
140fc727 YL |
469 | #ifdef CONFIG_X86_64 |
470 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
471 | #else | |
1da177e4 | 472 | /* do processor-specific cache resizing */ |
09dc68d9 JB |
473 | if (this_cpu->legacy_cache_size) |
474 | l2size = this_cpu->legacy_cache_size(c, l2size); | |
1da177e4 LT |
475 | |
476 | /* Allow user to override all this if necessary. */ | |
477 | if (cachesize_override != -1) | |
478 | l2size = cachesize_override; | |
479 | ||
34048c9e | 480 | if (l2size == 0) |
1da177e4 | 481 | return; /* Again, no L2 cache is possible */ |
140fc727 | 482 | #endif |
1da177e4 LT |
483 | |
484 | c->x86_cache_size = l2size; | |
1da177e4 LT |
485 | } |
486 | ||
e0ba94f1 AS |
487 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
488 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
489 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
490 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
491 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
492 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
dd360393 | 493 | u16 __read_mostly tlb_lld_1g[NR_INFO]; |
e0ba94f1 | 494 | |
f94fe119 | 495 | static void cpu_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
496 | { |
497 | if (this_cpu->c_detect_tlb) | |
498 | this_cpu->c_detect_tlb(c); | |
499 | ||
f94fe119 | 500 | pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", |
e0ba94f1 | 501 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
f94fe119 SH |
502 | tlb_lli_4m[ENTRIES]); |
503 | ||
504 | pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", | |
505 | tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], | |
506 | tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); | |
e0ba94f1 AS |
507 | } |
508 | ||
148f9bb8 | 509 | void detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 510 | { |
97e4db7c | 511 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
512 | u32 eax, ebx, ecx, edx; |
513 | int index_msb, core_bits; | |
2eaad1fd | 514 | static bool printed; |
1da177e4 | 515 | |
0a488a53 | 516 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 517 | return; |
1da177e4 | 518 | |
0a488a53 YL |
519 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
520 | goto out; | |
1da177e4 | 521 | |
1cd78776 YL |
522 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
523 | return; | |
1da177e4 | 524 | |
0a488a53 | 525 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 526 | |
9d31d35b YL |
527 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
528 | ||
529 | if (smp_num_siblings == 1) { | |
2eaad1fd | 530 | printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); |
0f3fa48a IM |
531 | goto out; |
532 | } | |
9d31d35b | 533 | |
0f3fa48a IM |
534 | if (smp_num_siblings <= 1) |
535 | goto out; | |
9d31d35b | 536 | |
0f3fa48a IM |
537 | index_msb = get_count_order(smp_num_siblings); |
538 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 539 | |
0f3fa48a | 540 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 541 | |
0f3fa48a | 542 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 543 | |
0f3fa48a | 544 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 545 | |
0f3fa48a IM |
546 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
547 | ((1 << core_bits) - 1); | |
1da177e4 | 548 | |
0a488a53 | 549 | out: |
2eaad1fd | 550 | if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { |
0a488a53 YL |
551 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", |
552 | c->phys_proc_id); | |
553 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
554 | c->cpu_core_id); | |
2eaad1fd | 555 | printed = 1; |
9d31d35b | 556 | } |
9d31d35b | 557 | #endif |
97e4db7c | 558 | } |
1da177e4 | 559 | |
148f9bb8 | 560 | static void get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
561 | { |
562 | char *v = c->x86_vendor_id; | |
0f3fa48a | 563 | int i; |
1da177e4 LT |
564 | |
565 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
566 | if (!cpu_devs[i]) |
567 | break; | |
568 | ||
569 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
570 | (cpu_devs[i]->c_ident[1] && | |
571 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 572 | |
10a434fc YL |
573 | this_cpu = cpu_devs[i]; |
574 | c->x86_vendor = this_cpu->c_x86_vendor; | |
575 | return; | |
1da177e4 LT |
576 | } |
577 | } | |
10a434fc | 578 | |
a9c56953 MK |
579 | printk_once(KERN_ERR |
580 | "CPU: vendor_id '%s' unknown, using generic init.\n" \ | |
581 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 582 | |
fe38d855 CE |
583 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
584 | this_cpu = &default_cpu; | |
1da177e4 LT |
585 | } |
586 | ||
148f9bb8 | 587 | void cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 588 | { |
1da177e4 | 589 | /* Get vendor name */ |
4a148513 HH |
590 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
591 | (unsigned int *)&c->x86_vendor_id[0], | |
592 | (unsigned int *)&c->x86_vendor_id[8], | |
593 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 594 | |
1da177e4 | 595 | c->x86 = 4; |
9d31d35b | 596 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
597 | if (c->cpuid_level >= 0x00000001) { |
598 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 599 | |
1da177e4 | 600 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
9d31d35b YL |
601 | c->x86 = (tfms >> 8) & 0xf; |
602 | c->x86_model = (tfms >> 4) & 0xf; | |
603 | c->x86_mask = tfms & 0xf; | |
0f3fa48a | 604 | |
f5f786d0 | 605 | if (c->x86 == 0xf) |
1da177e4 | 606 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 607 | if (c->x86 >= 0x6) |
9d31d35b | 608 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
0f3fa48a | 609 | |
d4387bd3 | 610 | if (cap0 & (1<<19)) { |
d4387bd3 | 611 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 612 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 613 | } |
1da177e4 | 614 | } |
1da177e4 | 615 | } |
3da99c97 | 616 | |
148f9bb8 | 617 | void get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 YL |
618 | { |
619 | u32 tfms, xlvl; | |
3da99c97 | 620 | u32 ebx; |
093af8d7 | 621 | |
3da99c97 YL |
622 | /* Intel-defined flags: level 0x00000001 */ |
623 | if (c->cpuid_level >= 0x00000001) { | |
624 | u32 capability, excap; | |
0f3fa48a | 625 | |
3da99c97 YL |
626 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); |
627 | c->x86_capability[0] = capability; | |
628 | c->x86_capability[4] = excap; | |
629 | } | |
093af8d7 | 630 | |
bdc802dc PA |
631 | /* Additional Intel-defined flags: level 0x00000007 */ |
632 | if (c->cpuid_level >= 0x00000007) { | |
633 | u32 eax, ebx, ecx, edx; | |
634 | ||
635 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); | |
636 | ||
2494b030 | 637 | c->x86_capability[9] = ebx; |
bdc802dc PA |
638 | } |
639 | ||
6229ad27 FY |
640 | /* Extended state features: level 0x0000000d */ |
641 | if (c->cpuid_level >= 0x0000000d) { | |
642 | u32 eax, ebx, ecx, edx; | |
643 | ||
644 | cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); | |
645 | ||
646 | c->x86_capability[10] = eax; | |
647 | } | |
648 | ||
cbc82b17 PWJ |
649 | /* Additional Intel-defined flags: level 0x0000000F */ |
650 | if (c->cpuid_level >= 0x0000000F) { | |
651 | u32 eax, ebx, ecx, edx; | |
652 | ||
653 | /* QoS sub-leaf, EAX=0Fh, ECX=0 */ | |
654 | cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); | |
655 | c->x86_capability[11] = edx; | |
656 | if (cpu_has(c, X86_FEATURE_CQM_LLC)) { | |
657 | /* will be overridden if occupancy monitoring exists */ | |
658 | c->x86_cache_max_rmid = ebx; | |
659 | ||
660 | /* QoS sub-leaf, EAX=0Fh, ECX=1 */ | |
661 | cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); | |
662 | c->x86_capability[12] = edx; | |
663 | if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) { | |
664 | c->x86_cache_max_rmid = ecx; | |
665 | c->x86_cache_occ_scale = ebx; | |
666 | } | |
667 | } else { | |
668 | c->x86_cache_max_rmid = -1; | |
669 | c->x86_cache_occ_scale = -1; | |
670 | } | |
671 | } | |
672 | ||
3da99c97 YL |
673 | /* AMD-defined flags: level 0x80000001 */ |
674 | xlvl = cpuid_eax(0x80000000); | |
675 | c->extended_cpuid_level = xlvl; | |
0f3fa48a | 676 | |
3da99c97 YL |
677 | if ((xlvl & 0xffff0000) == 0x80000000) { |
678 | if (xlvl >= 0x80000001) { | |
679 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
680 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 681 | } |
093af8d7 | 682 | } |
093af8d7 | 683 | |
5122c890 YL |
684 | if (c->extended_cpuid_level >= 0x80000008) { |
685 | u32 eax = cpuid_eax(0x80000008); | |
686 | ||
687 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
688 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 689 | } |
13c6c532 JB |
690 | #ifdef CONFIG_X86_32 |
691 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
692 | c->x86_phys_bits = 36; | |
5122c890 | 693 | #endif |
e3224234 YL |
694 | |
695 | if (c->extended_cpuid_level >= 0x80000007) | |
696 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 | 697 | |
1dedefd1 | 698 | init_scattered_cpuid_features(c); |
093af8d7 | 699 | } |
1da177e4 | 700 | |
148f9bb8 | 701 | static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
aef93c8b YL |
702 | { |
703 | #ifdef CONFIG_X86_32 | |
704 | int i; | |
705 | ||
706 | /* | |
707 | * First of all, decide if this is a 486 or higher | |
708 | * It's a 486 if we can modify the AC flag | |
709 | */ | |
710 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
711 | c->x86 = 4; | |
712 | else | |
713 | c->x86 = 3; | |
714 | ||
715 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
716 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
717 | c->x86_vendor_id[0] = 0; | |
718 | cpu_devs[i]->c_identify(c); | |
719 | if (c->x86_vendor_id[0]) { | |
720 | get_cpu_vendor(c); | |
721 | break; | |
722 | } | |
723 | } | |
724 | #endif | |
725 | } | |
726 | ||
34048c9e PC |
727 | /* |
728 | * Do minimum CPU detection early. | |
729 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
730 | * cache alignment. | |
731 | * The others are not touched to avoid unwanted side effects. | |
732 | * | |
733 | * WARNING: this function is only called on the BP. Don't add code here | |
734 | * that is supposed to run on all CPUs. | |
735 | */ | |
3da99c97 | 736 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 737 | { |
6627d242 YL |
738 | #ifdef CONFIG_X86_64 |
739 | c->x86_clflush_size = 64; | |
13c6c532 JB |
740 | c->x86_phys_bits = 36; |
741 | c->x86_virt_bits = 48; | |
6627d242 | 742 | #else |
d4387bd3 | 743 | c->x86_clflush_size = 32; |
13c6c532 JB |
744 | c->x86_phys_bits = 32; |
745 | c->x86_virt_bits = 32; | |
6627d242 | 746 | #endif |
0a488a53 | 747 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 748 | |
3da99c97 | 749 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 750 | c->extended_cpuid_level = 0; |
d7cd5611 | 751 | |
aef93c8b YL |
752 | if (!have_cpuid_p()) |
753 | identify_cpu_without_cpuid(c); | |
754 | ||
755 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
756 | if (!have_cpuid_p()) |
757 | return; | |
758 | ||
759 | cpu_detect(c); | |
3da99c97 | 760 | get_cpu_vendor(c); |
3da99c97 | 761 | get_cpu_cap(c); |
60e019eb | 762 | fpu_detect(c); |
12cf105c | 763 | |
10a434fc YL |
764 | if (this_cpu->c_early_init) |
765 | this_cpu->c_early_init(c); | |
093af8d7 | 766 | |
f6e9456c | 767 | c->cpu_index = 0; |
b38b0665 | 768 | filter_cpuid_features(c, false); |
de5397ad | 769 | |
a110b5ec BP |
770 | if (this_cpu->c_bsp_init) |
771 | this_cpu->c_bsp_init(c); | |
c3b83598 BP |
772 | |
773 | setup_force_cpu_cap(X86_FEATURE_ALWAYS); | |
d7cd5611 RR |
774 | } |
775 | ||
9d31d35b YL |
776 | void __init early_cpu_init(void) |
777 | { | |
02dde8b4 | 778 | const struct cpu_dev *const *cdev; |
10a434fc YL |
779 | int count = 0; |
780 | ||
ac23f253 | 781 | #ifdef CONFIG_PROCESSOR_SELECT |
9766cdbc | 782 | printk(KERN_INFO "KERNEL supported cpus:\n"); |
31c997ca IM |
783 | #endif |
784 | ||
10a434fc | 785 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 786 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 787 | |
10a434fc YL |
788 | if (count >= X86_VENDOR_NUM) |
789 | break; | |
790 | cpu_devs[count] = cpudev; | |
791 | count++; | |
792 | ||
ac23f253 | 793 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
794 | { |
795 | unsigned int j; | |
796 | ||
797 | for (j = 0; j < 2; j++) { | |
798 | if (!cpudev->c_ident[j]) | |
799 | continue; | |
800 | printk(KERN_INFO " %s %s\n", cpudev->c_vendor, | |
801 | cpudev->c_ident[j]); | |
802 | } | |
10a434fc | 803 | } |
0388423d | 804 | #endif |
10a434fc | 805 | } |
9d31d35b | 806 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 807 | } |
093af8d7 | 808 | |
b6734c35 | 809 | /* |
366d4a43 BP |
810 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; |
811 | * unfortunately, that's not true in practice because of early VIA | |
812 | * chips and (more importantly) broken virtualizers that are not easy | |
813 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
814 | * probing for it doesn't even work. Disable it completely on 32-bit | |
ba0593bf | 815 | * unless we can find a reliable way to detect all the broken cases. |
366d4a43 | 816 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). |
b6734c35 | 817 | */ |
148f9bb8 | 818 | static void detect_nopl(struct cpuinfo_x86 *c) |
b6734c35 | 819 | { |
366d4a43 | 820 | #ifdef CONFIG_X86_32 |
b6734c35 | 821 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
366d4a43 BP |
822 | #else |
823 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
824 | #endif | |
d7cd5611 RR |
825 | } |
826 | ||
148f9bb8 | 827 | static void generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 828 | { |
aef93c8b | 829 | c->extended_cpuid_level = 0; |
1da177e4 | 830 | |
3da99c97 | 831 | if (!have_cpuid_p()) |
aef93c8b | 832 | identify_cpu_without_cpuid(c); |
1d67953f | 833 | |
aef93c8b | 834 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 835 | if (!have_cpuid_p()) |
aef93c8b | 836 | return; |
1da177e4 | 837 | |
3da99c97 | 838 | cpu_detect(c); |
1da177e4 | 839 | |
3da99c97 | 840 | get_cpu_vendor(c); |
1da177e4 | 841 | |
3da99c97 | 842 | get_cpu_cap(c); |
1da177e4 | 843 | |
3da99c97 YL |
844 | if (c->cpuid_level >= 0x00000001) { |
845 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
846 | #ifdef CONFIG_X86_32 |
847 | # ifdef CONFIG_X86_HT | |
cb8cc442 | 848 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 849 | # else |
3da99c97 | 850 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
851 | # endif |
852 | #endif | |
b89d3b3e | 853 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 854 | } |
1da177e4 | 855 | |
1b05d60d | 856 | get_model_name(c); /* Default name */ |
1da177e4 | 857 | |
3da99c97 | 858 | detect_nopl(c); |
1da177e4 | 859 | } |
1da177e4 | 860 | |
cbc82b17 PWJ |
861 | static void x86_init_cache_qos(struct cpuinfo_x86 *c) |
862 | { | |
863 | /* | |
864 | * The heavy lifting of max_rmid and cache_occ_scale are handled | |
865 | * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu | |
866 | * in case CQM bits really aren't there in this CPU. | |
867 | */ | |
868 | if (c != &boot_cpu_data) { | |
869 | boot_cpu_data.x86_cache_max_rmid = | |
870 | min(boot_cpu_data.x86_cache_max_rmid, | |
871 | c->x86_cache_max_rmid); | |
872 | } | |
873 | } | |
874 | ||
1da177e4 LT |
875 | /* |
876 | * This does the hard work of actually picking apart the CPU stuff... | |
877 | */ | |
148f9bb8 | 878 | static void identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
879 | { |
880 | int i; | |
881 | ||
882 | c->loops_per_jiffy = loops_per_jiffy; | |
883 | c->x86_cache_size = -1; | |
884 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
885 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
886 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
887 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 888 | c->x86_max_cores = 1; |
102bbe3a | 889 | c->x86_coreid_bits = 0; |
11fdd252 | 890 | #ifdef CONFIG_X86_64 |
102bbe3a | 891 | c->x86_clflush_size = 64; |
13c6c532 JB |
892 | c->x86_phys_bits = 36; |
893 | c->x86_virt_bits = 48; | |
102bbe3a YL |
894 | #else |
895 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 896 | c->x86_clflush_size = 32; |
13c6c532 JB |
897 | c->x86_phys_bits = 32; |
898 | c->x86_virt_bits = 32; | |
102bbe3a YL |
899 | #endif |
900 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
901 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
902 | ||
1da177e4 LT |
903 | generic_identify(c); |
904 | ||
3898534d | 905 | if (this_cpu->c_identify) |
1da177e4 LT |
906 | this_cpu->c_identify(c); |
907 | ||
2759c328 YL |
908 | /* Clear/Set all flags overriden by options, after probe */ |
909 | for (i = 0; i < NCAPINTS; i++) { | |
910 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
911 | c->x86_capability[i] |= cpu_caps_set[i]; | |
912 | } | |
913 | ||
102bbe3a | 914 | #ifdef CONFIG_X86_64 |
cb8cc442 | 915 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
916 | #endif |
917 | ||
1da177e4 LT |
918 | /* |
919 | * Vendor-specific initialization. In this section we | |
920 | * canonicalize the feature flags, meaning if there are | |
921 | * features a certain CPU supports which CPUID doesn't | |
922 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
923 | * we handle them here. | |
924 | * | |
925 | * At the end of this section, c->x86_capability better | |
926 | * indicate the features this CPU genuinely supports! | |
927 | */ | |
928 | if (this_cpu->c_init) | |
929 | this_cpu->c_init(c); | |
930 | ||
931 | /* Disable the PN if appropriate */ | |
932 | squash_the_stupid_serial_number(c); | |
933 | ||
b2cc2a07 PA |
934 | /* Set up SMEP/SMAP */ |
935 | setup_smep(c); | |
936 | setup_smap(c); | |
937 | ||
1da177e4 | 938 | /* |
0f3fa48a IM |
939 | * The vendor-specific functions might have changed features. |
940 | * Now we do "generic changes." | |
1da177e4 LT |
941 | */ |
942 | ||
b38b0665 PA |
943 | /* Filter out anything that depends on CPUID levels we don't have */ |
944 | filter_cpuid_features(c, true); | |
945 | ||
1da177e4 | 946 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 947 | if (!c->x86_model_id[0]) { |
02dde8b4 | 948 | const char *p; |
1da177e4 | 949 | p = table_lookup_model(c); |
34048c9e | 950 | if (p) |
1da177e4 LT |
951 | strcpy(c->x86_model_id, p); |
952 | else | |
953 | /* Last resort... */ | |
954 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 955 | c->x86, c->x86_model); |
1da177e4 LT |
956 | } |
957 | ||
102bbe3a YL |
958 | #ifdef CONFIG_X86_64 |
959 | detect_ht(c); | |
960 | #endif | |
961 | ||
88b094fb | 962 | init_hypervisor(c); |
49d859d7 | 963 | x86_init_rdrand(c); |
cbc82b17 | 964 | x86_init_cache_qos(c); |
3e0c3737 YL |
965 | |
966 | /* | |
967 | * Clear/Set all flags overriden by options, need do it | |
968 | * before following smp all cpus cap AND. | |
969 | */ | |
970 | for (i = 0; i < NCAPINTS; i++) { | |
971 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
972 | c->x86_capability[i] |= cpu_caps_set[i]; | |
973 | } | |
974 | ||
1da177e4 LT |
975 | /* |
976 | * On SMP, boot_cpu_data holds the common feature set between | |
977 | * all CPUs; so make sure that we indicate which features are | |
978 | * common between the CPUs. The first time this routine gets | |
979 | * executed, c == &boot_cpu_data. | |
980 | */ | |
34048c9e | 981 | if (c != &boot_cpu_data) { |
1da177e4 | 982 | /* AND the already accumulated flags with these */ |
9d31d35b | 983 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 | 984 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
65fc985b BP |
985 | |
986 | /* OR, i.e. replicate the bug flags */ | |
987 | for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) | |
988 | c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; | |
1da177e4 LT |
989 | } |
990 | ||
991 | /* Init Machine Check Exception if available. */ | |
5e09954a | 992 | mcheck_cpu_init(c); |
30d432df AK |
993 | |
994 | select_idle_routine(c); | |
102bbe3a | 995 | |
de2d9445 | 996 | #ifdef CONFIG_NUMA |
102bbe3a YL |
997 | numa_add_cpu(smp_processor_id()); |
998 | #endif | |
a6c4e076 | 999 | } |
31ab269a | 1000 | |
8b6c0ab1 IM |
1001 | /* |
1002 | * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions | |
1003 | * on 32-bit kernels: | |
1004 | */ | |
cfda7bb9 AL |
1005 | #ifdef CONFIG_X86_32 |
1006 | void enable_sep_cpu(void) | |
1007 | { | |
8b6c0ab1 IM |
1008 | struct tss_struct *tss; |
1009 | int cpu; | |
cfda7bb9 | 1010 | |
8b6c0ab1 IM |
1011 | cpu = get_cpu(); |
1012 | tss = &per_cpu(cpu_tss, cpu); | |
1013 | ||
1014 | if (!boot_cpu_has(X86_FEATURE_SEP)) | |
1015 | goto out; | |
1016 | ||
1017 | /* | |
cf9328cc AL |
1018 | * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- |
1019 | * see the big comment in struct x86_hw_tss's definition. | |
8b6c0ab1 | 1020 | */ |
cfda7bb9 AL |
1021 | |
1022 | tss->x86_tss.ss1 = __KERNEL_CS; | |
8b6c0ab1 IM |
1023 | wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); |
1024 | ||
cf9328cc AL |
1025 | wrmsr(MSR_IA32_SYSENTER_ESP, |
1026 | (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack), | |
1027 | 0); | |
8b6c0ab1 IM |
1028 | |
1029 | wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)ia32_sysenter_target, 0); | |
1030 | ||
1031 | out: | |
cfda7bb9 AL |
1032 | put_cpu(); |
1033 | } | |
e04d645f GC |
1034 | #endif |
1035 | ||
a6c4e076 JF |
1036 | void __init identify_boot_cpu(void) |
1037 | { | |
1038 | identify_cpu(&boot_cpu_data); | |
02c68a02 | 1039 | init_amd_e400_c1e_mask(); |
102bbe3a | 1040 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1041 | sysenter_setup(); |
6fe940d6 | 1042 | enable_sep_cpu(); |
102bbe3a | 1043 | #endif |
5b556332 | 1044 | cpu_detect_tlb(&boot_cpu_data); |
a6c4e076 | 1045 | } |
3b520b23 | 1046 | |
148f9bb8 | 1047 | void identify_secondary_cpu(struct cpuinfo_x86 *c) |
a6c4e076 JF |
1048 | { |
1049 | BUG_ON(c == &boot_cpu_data); | |
1050 | identify_cpu(c); | |
102bbe3a | 1051 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1052 | enable_sep_cpu(); |
102bbe3a | 1053 | #endif |
a6c4e076 | 1054 | mtrr_ap_init(); |
1da177e4 LT |
1055 | } |
1056 | ||
a0854a46 | 1057 | struct msr_range { |
0f3fa48a IM |
1058 | unsigned min; |
1059 | unsigned max; | |
a0854a46 | 1060 | }; |
1da177e4 | 1061 | |
148f9bb8 | 1062 | static const struct msr_range msr_range_array[] = { |
a0854a46 YL |
1063 | { 0x00000000, 0x00000418}, |
1064 | { 0xc0000000, 0xc000040b}, | |
1065 | { 0xc0010000, 0xc0010142}, | |
1066 | { 0xc0011000, 0xc001103b}, | |
1067 | }; | |
1da177e4 | 1068 | |
148f9bb8 | 1069 | static void __print_cpu_msr(void) |
a0854a46 | 1070 | { |
0f3fa48a | 1071 | unsigned index_min, index_max; |
a0854a46 YL |
1072 | unsigned index; |
1073 | u64 val; | |
1074 | int i; | |
a0854a46 YL |
1075 | |
1076 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
1077 | index_min = msr_range_array[i].min; | |
1078 | index_max = msr_range_array[i].max; | |
0f3fa48a | 1079 | |
a0854a46 | 1080 | for (index = index_min; index < index_max; index++) { |
ecd431d9 | 1081 | if (rdmsrl_safe(index, &val)) |
a0854a46 YL |
1082 | continue; |
1083 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 1084 | } |
a0854a46 YL |
1085 | } |
1086 | } | |
94605eff | 1087 | |
148f9bb8 | 1088 | static int show_msr; |
0f3fa48a | 1089 | |
a0854a46 YL |
1090 | static __init int setup_show_msr(char *arg) |
1091 | { | |
1092 | int num; | |
3dd9d514 | 1093 | |
a0854a46 | 1094 | get_option(&arg, &num); |
3dd9d514 | 1095 | |
a0854a46 YL |
1096 | if (num > 0) |
1097 | show_msr = num; | |
1098 | return 1; | |
1da177e4 | 1099 | } |
a0854a46 | 1100 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 1101 | |
191679fd AK |
1102 | static __init int setup_noclflush(char *arg) |
1103 | { | |
840d2830 | 1104 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); |
da4aaa7d | 1105 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); |
191679fd AK |
1106 | return 1; |
1107 | } | |
1108 | __setup("noclflush", setup_noclflush); | |
1109 | ||
148f9bb8 | 1110 | void print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1111 | { |
02dde8b4 | 1112 | const char *vendor = NULL; |
1da177e4 | 1113 | |
0f3fa48a | 1114 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1115 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1116 | } else { |
1117 | if (c->cpuid_level >= 0) | |
1118 | vendor = c->x86_vendor_id; | |
1119 | } | |
1da177e4 | 1120 | |
bd32a8cf | 1121 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 1122 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 1123 | |
9d31d35b | 1124 | if (c->x86_model_id[0]) |
924e101a | 1125 | printk(KERN_CONT "%s", strim(c->x86_model_id)); |
1da177e4 | 1126 | else |
9d31d35b | 1127 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 1128 | |
924e101a BP |
1129 | printk(KERN_CONT " (fam: %02x, model: %02x", c->x86, c->x86_model); |
1130 | ||
34048c9e | 1131 | if (c->x86_mask || c->cpuid_level >= 0) |
924e101a | 1132 | printk(KERN_CONT ", stepping: %02x)\n", c->x86_mask); |
1da177e4 | 1133 | else |
924e101a | 1134 | printk(KERN_CONT ")\n"); |
a0854a46 | 1135 | |
0b8b8078 | 1136 | print_cpu_msr(c); |
21c3fcf3 YL |
1137 | } |
1138 | ||
148f9bb8 | 1139 | void print_cpu_msr(struct cpuinfo_x86 *c) |
21c3fcf3 | 1140 | { |
a0854a46 | 1141 | if (c->cpu_index < show_msr) |
21c3fcf3 | 1142 | __print_cpu_msr(); |
1da177e4 LT |
1143 | } |
1144 | ||
ac72e788 AK |
1145 | static __init int setup_disablecpuid(char *arg) |
1146 | { | |
1147 | int bit; | |
0f3fa48a | 1148 | |
ac72e788 AK |
1149 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) |
1150 | setup_clear_cpu_cap(bit); | |
1151 | else | |
1152 | return 0; | |
0f3fa48a | 1153 | |
ac72e788 AK |
1154 | return 1; |
1155 | } | |
1156 | __setup("clearcpuid=", setup_disablecpuid); | |
1157 | ||
d5494d4f | 1158 | #ifdef CONFIG_X86_64 |
9ff80942 | 1159 | struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; |
629f4f9d SA |
1160 | struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1, |
1161 | (unsigned long) debug_idt_table }; | |
d5494d4f | 1162 | |
947e76cd | 1163 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
277d5b40 | 1164 | irq_stack_union) __aligned(PAGE_SIZE) __visible; |
0f3fa48a | 1165 | |
bdf977b3 | 1166 | /* |
a7fcf28d AL |
1167 | * The following percpu variables are hot. Align current_task to |
1168 | * cacheline size such that they fall in the same cacheline. | |
bdf977b3 TH |
1169 | */ |
1170 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1171 | &init_task; | |
1172 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1173 | |
bdf977b3 TH |
1174 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
1175 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; | |
1176 | ||
277d5b40 | 1177 | DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; |
d5494d4f | 1178 | |
c2daa3be PZ |
1179 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1180 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
1181 | ||
7e16838d LT |
1182 | DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); |
1183 | ||
0f3fa48a IM |
1184 | /* |
1185 | * Special IST stacks which the CPU switches to when it calls | |
1186 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
1187 | * limit), all of them are 4K, except the debug stack which | |
1188 | * is 8K. | |
1189 | */ | |
1190 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
1191 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1192 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1193 | }; | |
1194 | ||
92d65b23 | 1195 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
3e352aa8 | 1196 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); |
d5494d4f | 1197 | |
d5494d4f YL |
1198 | /* May not be marked __init: used by software suspend */ |
1199 | void syscall_init(void) | |
1da177e4 | 1200 | { |
d5494d4f YL |
1201 | /* |
1202 | * LSTAR and STAR live in a bit strange symbiosis. | |
1203 | * They both write to the same internal register. STAR allows to | |
1204 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
1205 | */ | |
1206 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
1207 | wrmsrl(MSR_LSTAR, system_call); | |
d56fe4bf IM |
1208 | |
1209 | #ifdef CONFIG_IA32_EMULATION | |
a76c7f46 DV |
1210 | wrmsrl(MSR_CSTAR, ia32_cstar_target); |
1211 | /* | |
487d1edb DV |
1212 | * This only works on Intel CPUs. |
1213 | * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. | |
1214 | * This does not cause SYSENTER to jump to the wrong location, because | |
1215 | * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). | |
a76c7f46 DV |
1216 | */ |
1217 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); | |
1218 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); | |
1219 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)ia32_sysenter_target); | |
d56fe4bf IM |
1220 | #else |
1221 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
6b51311c | 1222 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); |
d56fe4bf IM |
1223 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); |
1224 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); | |
d5494d4f | 1225 | #endif |
03ae5768 | 1226 | |
d5494d4f YL |
1227 | /* Flags to clear on syscall */ |
1228 | wrmsrl(MSR_SYSCALL_MASK, | |
63bcff2a | 1229 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| |
8c7aa698 | 1230 | X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); |
1da177e4 | 1231 | } |
62111195 | 1232 | |
d5494d4f YL |
1233 | /* |
1234 | * Copies of the original ist values from the tss are only accessed during | |
1235 | * debugging, no special alignment required. | |
1236 | */ | |
1237 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1238 | ||
228bdaa9 | 1239 | static DEFINE_PER_CPU(unsigned long, debug_stack_addr); |
42181186 | 1240 | DEFINE_PER_CPU(int, debug_stack_usage); |
228bdaa9 SR |
1241 | |
1242 | int is_debug_stack(unsigned long addr) | |
1243 | { | |
89cbc767 CL |
1244 | return __this_cpu_read(debug_stack_usage) || |
1245 | (addr <= __this_cpu_read(debug_stack_addr) && | |
1246 | addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); | |
228bdaa9 | 1247 | } |
0f46efeb | 1248 | NOKPROBE_SYMBOL(is_debug_stack); |
228bdaa9 | 1249 | |
629f4f9d | 1250 | DEFINE_PER_CPU(u32, debug_idt_ctr); |
f8988175 | 1251 | |
228bdaa9 SR |
1252 | void debug_stack_set_zero(void) |
1253 | { | |
629f4f9d SA |
1254 | this_cpu_inc(debug_idt_ctr); |
1255 | load_current_idt(); | |
228bdaa9 | 1256 | } |
0f46efeb | 1257 | NOKPROBE_SYMBOL(debug_stack_set_zero); |
228bdaa9 SR |
1258 | |
1259 | void debug_stack_reset(void) | |
1260 | { | |
629f4f9d | 1261 | if (WARN_ON(!this_cpu_read(debug_idt_ctr))) |
f8988175 | 1262 | return; |
629f4f9d SA |
1263 | if (this_cpu_dec_return(debug_idt_ctr) == 0) |
1264 | load_current_idt(); | |
228bdaa9 | 1265 | } |
0f46efeb | 1266 | NOKPROBE_SYMBOL(debug_stack_reset); |
228bdaa9 | 1267 | |
0f3fa48a | 1268 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1269 | |
bdf977b3 TH |
1270 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1271 | EXPORT_PER_CPU_SYMBOL(current_task); | |
c2daa3be PZ |
1272 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1273 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
27e74da9 | 1274 | DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); |
bdf977b3 | 1275 | |
a7fcf28d AL |
1276 | /* |
1277 | * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find | |
1278 | * the top of the kernel stack. Use an extra percpu variable to track the | |
1279 | * top of the kernel stack directly. | |
1280 | */ | |
1281 | DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = | |
1282 | (unsigned long)&init_thread_union + THREAD_SIZE; | |
1283 | EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); | |
1284 | ||
60a5317f | 1285 | #ifdef CONFIG_CC_STACKPROTECTOR |
53f82452 | 1286 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1287 | #endif |
d5494d4f | 1288 | |
0f3fa48a | 1289 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1290 | |
9766cdbc JSR |
1291 | /* |
1292 | * Clear all 6 debug registers: | |
1293 | */ | |
1294 | static void clear_all_debug_regs(void) | |
1295 | { | |
1296 | int i; | |
1297 | ||
1298 | for (i = 0; i < 8; i++) { | |
1299 | /* Ignore db4, db5 */ | |
1300 | if ((i == 4) || (i == 5)) | |
1301 | continue; | |
1302 | ||
1303 | set_debugreg(0, i); | |
1304 | } | |
1305 | } | |
c5413fbe | 1306 | |
0bb9fef9 JW |
1307 | #ifdef CONFIG_KGDB |
1308 | /* | |
1309 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1310 | * connection established. | |
1311 | */ | |
1312 | static void dbg_restore_debug_regs(void) | |
1313 | { | |
1314 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1315 | arch_kgdb_ops.correct_hw_break(); | |
1316 | } | |
1317 | #else /* ! CONFIG_KGDB */ | |
1318 | #define dbg_restore_debug_regs() | |
1319 | #endif /* ! CONFIG_KGDB */ | |
1320 | ||
ce4b1b16 IM |
1321 | static void wait_for_master_cpu(int cpu) |
1322 | { | |
1323 | #ifdef CONFIG_SMP | |
1324 | /* | |
1325 | * wait for ACK from master CPU before continuing | |
1326 | * with AP initialization | |
1327 | */ | |
1328 | WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); | |
1329 | while (!cpumask_test_cpu(cpu, cpu_callout_mask)) | |
1330 | cpu_relax(); | |
1331 | #endif | |
1332 | } | |
1333 | ||
d2cbcc49 RR |
1334 | /* |
1335 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1336 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1337 | * and IDT. We reload them nevertheless, this function acts as a | |
1338 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1339 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1340 | */ |
1ba76586 | 1341 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1342 | |
148f9bb8 | 1343 | void cpu_init(void) |
1ba76586 | 1344 | { |
0fe1e009 | 1345 | struct orig_ist *oist; |
1ba76586 | 1346 | struct task_struct *me; |
0f3fa48a IM |
1347 | struct tss_struct *t; |
1348 | unsigned long v; | |
ce4b1b16 | 1349 | int cpu = stack_smp_processor_id(); |
1ba76586 YL |
1350 | int i; |
1351 | ||
ce4b1b16 IM |
1352 | wait_for_master_cpu(cpu); |
1353 | ||
1e02ce4c AL |
1354 | /* |
1355 | * Initialize the CR4 shadow before doing anything that could | |
1356 | * try to read it. | |
1357 | */ | |
1358 | cr4_init_shadow(); | |
1359 | ||
e6ebf5de FY |
1360 | /* |
1361 | * Load microcode on this cpu if a valid microcode is available. | |
1362 | * This is early microcode loading procedure. | |
1363 | */ | |
1364 | load_ucode_ap(); | |
1365 | ||
24933b82 | 1366 | t = &per_cpu(cpu_tss, cpu); |
0fe1e009 | 1367 | oist = &per_cpu(orig_ist, cpu); |
0f3fa48a | 1368 | |
e7a22c1e | 1369 | #ifdef CONFIG_NUMA |
27fd185f | 1370 | if (this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
1371 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
1372 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1373 | #endif |
1ba76586 YL |
1374 | |
1375 | me = current; | |
1376 | ||
2eaad1fd | 1377 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 | 1378 | |
375074cc | 1379 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
1ba76586 YL |
1380 | |
1381 | /* | |
1382 | * Initialize the per-CPU GDT with the boot GDT, | |
1383 | * and set up the GDT descriptor: | |
1384 | */ | |
1385 | ||
552be871 | 1386 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1387 | loadsegment(fs, 0); |
1388 | ||
cf910e83 | 1389 | load_current_idt(); |
1ba76586 YL |
1390 | |
1391 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1392 | syscall_init(); | |
1393 | ||
1394 | wrmsrl(MSR_FS_BASE, 0); | |
1395 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1396 | barrier(); | |
1397 | ||
4763ed4d | 1398 | x86_configure_nx(); |
659006bf | 1399 | x2apic_setup(); |
1ba76586 YL |
1400 | |
1401 | /* | |
1402 | * set up and load the per-CPU TSS | |
1403 | */ | |
0fe1e009 | 1404 | if (!oist->ist[0]) { |
92d65b23 | 1405 | char *estacks = per_cpu(exception_stacks, cpu); |
0f3fa48a | 1406 | |
1ba76586 | 1407 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
0f3fa48a | 1408 | estacks += exception_stack_sizes[v]; |
0fe1e009 | 1409 | oist->ist[v] = t->x86_tss.ist[v] = |
1ba76586 | 1410 | (unsigned long)estacks; |
228bdaa9 SR |
1411 | if (v == DEBUG_STACK-1) |
1412 | per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; | |
1ba76586 YL |
1413 | } |
1414 | } | |
1415 | ||
1416 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
0f3fa48a | 1417 | |
1ba76586 YL |
1418 | /* |
1419 | * <= is required because the CPU will access up to | |
1420 | * 8 bits beyond the end of the IO permission bitmap. | |
1421 | */ | |
1422 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1423 | t->io_bitmap[i] = ~0UL; | |
1424 | ||
1425 | atomic_inc(&init_mm.mm_count); | |
1426 | me->active_mm = &init_mm; | |
8c5dfd25 | 1427 | BUG_ON(me->mm); |
1ba76586 YL |
1428 | enter_lazy_tlb(&init_mm, me); |
1429 | ||
1430 | load_sp0(t, ¤t->thread); | |
1431 | set_tss_desc(cpu, t); | |
1432 | load_TR_desc(); | |
1433 | load_LDT(&init_mm.context); | |
1434 | ||
0bb9fef9 JW |
1435 | clear_all_debug_regs(); |
1436 | dbg_restore_debug_regs(); | |
1ba76586 YL |
1437 | |
1438 | fpu_init(); | |
1439 | ||
1ba76586 YL |
1440 | if (is_uv_system()) |
1441 | uv_cpu_init(); | |
1442 | } | |
1443 | ||
1444 | #else | |
1445 | ||
148f9bb8 | 1446 | void cpu_init(void) |
9ee79a3d | 1447 | { |
d2cbcc49 RR |
1448 | int cpu = smp_processor_id(); |
1449 | struct task_struct *curr = current; | |
24933b82 | 1450 | struct tss_struct *t = &per_cpu(cpu_tss, cpu); |
9ee79a3d | 1451 | struct thread_struct *thread = &curr->thread; |
62111195 | 1452 | |
ce4b1b16 | 1453 | wait_for_master_cpu(cpu); |
e6ebf5de | 1454 | |
5b2bdbc8 SR |
1455 | /* |
1456 | * Initialize the CR4 shadow before doing anything that could | |
1457 | * try to read it. | |
1458 | */ | |
1459 | cr4_init_shadow(); | |
1460 | ||
ce4b1b16 | 1461 | show_ucode_info_early(); |
62111195 JF |
1462 | |
1463 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1464 | ||
9298b815 | 1465 | if (cpu_feature_enabled(X86_FEATURE_VME) || cpu_has_tsc || cpu_has_de) |
375074cc | 1466 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
62111195 | 1467 | |
cf910e83 | 1468 | load_current_idt(); |
552be871 | 1469 | switch_to_new_gdt(cpu); |
1da177e4 | 1470 | |
1da177e4 LT |
1471 | /* |
1472 | * Set up and load the per-CPU TSS and LDT | |
1473 | */ | |
1474 | atomic_inc(&init_mm.mm_count); | |
62111195 | 1475 | curr->active_mm = &init_mm; |
8c5dfd25 | 1476 | BUG_ON(curr->mm); |
62111195 | 1477 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1478 | |
faca6227 | 1479 | load_sp0(t, thread); |
34048c9e | 1480 | set_tss_desc(cpu, t); |
1da177e4 LT |
1481 | load_TR_desc(); |
1482 | load_LDT(&init_mm.context); | |
1483 | ||
f9a196b8 TG |
1484 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); |
1485 | ||
22c4e308 | 1486 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1487 | /* Set up doublefault TSS pointer in the GDT */ |
1488 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1489 | #endif |
1da177e4 | 1490 | |
9766cdbc | 1491 | clear_all_debug_regs(); |
0bb9fef9 | 1492 | dbg_restore_debug_regs(); |
1da177e4 | 1493 | |
0e49bf66 | 1494 | fpu_init(); |
1da177e4 | 1495 | } |
1ba76586 | 1496 | #endif |
5700f743 BP |
1497 | |
1498 | #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS | |
1499 | void warn_pre_alternatives(void) | |
1500 | { | |
1501 | WARN(1, "You're using static_cpu_has before alternatives have run!\n"); | |
1502 | } | |
1503 | EXPORT_SYMBOL_GPL(warn_pre_alternatives); | |
1504 | #endif | |
4a90a99c BP |
1505 | |
1506 | inline bool __static_cpu_has_safe(u16 bit) | |
1507 | { | |
1508 | return boot_cpu_has(bit); | |
1509 | } | |
1510 | EXPORT_SYMBOL_GPL(__static_cpu_has_safe); |