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1da177e4 | 1 | #include <linux/init.h> |
f0fc4aff YL |
2 | #include <linux/kernel.h> |
3 | #include <linux/sched.h> | |
1da177e4 | 4 | #include <linux/string.h> |
f0fc4aff YL |
5 | #include <linux/bootmem.h> |
6 | #include <linux/bitops.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/kgdb.h> | |
9 | #include <linux/topology.h> | |
1da177e4 LT |
10 | #include <linux/delay.h> |
11 | #include <linux/smp.h> | |
1da177e4 | 12 | #include <linux/percpu.h> |
1da177e4 LT |
13 | #include <asm/i387.h> |
14 | #include <asm/msr.h> | |
15 | #include <asm/io.h> | |
f0fc4aff | 16 | #include <asm/linkage.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
27b07da7 | 18 | #include <asm/mtrr.h> |
a03a3e28 | 19 | #include <asm/mce.h> |
8d4a4300 | 20 | #include <asm/pat.h> |
b6734c35 | 21 | #include <asm/asm.h> |
f0fc4aff | 22 | #include <asm/numa.h> |
b342797c | 23 | #include <asm/smp.h> |
1da177e4 LT |
24 | #ifdef CONFIG_X86_LOCAL_APIC |
25 | #include <asm/mpspec.h> | |
26 | #include <asm/apic.h> | |
27 | #include <mach_apic.h> | |
f0fc4aff | 28 | #include <asm/genapic.h> |
1da177e4 LT |
29 | #endif |
30 | ||
f0fc4aff YL |
31 | #include <asm/pda.h> |
32 | #include <asm/pgtable.h> | |
33 | #include <asm/processor.h> | |
34 | #include <asm/desc.h> | |
35 | #include <asm/atomic.h> | |
36 | #include <asm/proto.h> | |
37 | #include <asm/sections.h> | |
38 | #include <asm/setup.h> | |
88b094fb | 39 | #include <asm/hypervisor.h> |
f0fc4aff | 40 | |
1da177e4 LT |
41 | #include "cpu.h" |
42 | ||
0a488a53 YL |
43 | static struct cpu_dev *this_cpu __cpuinitdata; |
44 | ||
950ad7ff YL |
45 | #ifdef CONFIG_X86_64 |
46 | /* We need valid kernel segments for data and code in long mode too | |
47 | * IRET will check the segment types kkeil 2000/10/28 | |
48 | * Also sysret mandates a special GDT layout | |
49 | */ | |
50 | /* The TLS descriptors are currently at a different place compared to i386. | |
51 | Hopefully nobody expects them at a fixed place (Wine?) */ | |
7a61d35d | 52 | DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff YL |
53 | [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, |
54 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, | |
55 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, | |
56 | [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, | |
57 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, | |
58 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, | |
59 | } }; | |
60 | #else | |
63cc8c75 | 61 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
6842ef0e GOC |
62 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
63 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
64 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
65 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
66 | /* |
67 | * Segments used for calling PnP BIOS have byte granularity. | |
68 | * They code segments and data segments have fixed 64k limits, | |
69 | * the transfer segment sizes are set at run time. | |
70 | */ | |
6842ef0e GOC |
71 | /* 32-bit code */ |
72 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
73 | /* 16-bit code */ | |
74 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
75 | /* 16-bit data */ | |
76 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
77 | /* 16-bit data */ | |
78 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
79 | /* 16-bit data */ | |
80 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
bf504672 RR |
81 | /* |
82 | * The APM segments have byte granularity and their bases | |
83 | * are set at run time. All have 64k limits. | |
84 | */ | |
6842ef0e GOC |
85 | /* 32-bit code */ |
86 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
bf504672 | 87 | /* 16-bit code */ |
6842ef0e GOC |
88 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
89 | /* data */ | |
90 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
bf504672 | 91 | |
6842ef0e GOC |
92 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
93 | [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } }, | |
7a61d35d | 94 | } }; |
950ad7ff | 95 | #endif |
7a61d35d | 96 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 97 | |
ba51dced | 98 | #ifdef CONFIG_X86_32 |
3bc9b76b | 99 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 100 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 101 | |
0a488a53 YL |
102 | static int __init cachesize_setup(char *str) |
103 | { | |
104 | get_option(&str, &cachesize_override); | |
105 | return 1; | |
106 | } | |
107 | __setup("cachesize=", cachesize_setup); | |
108 | ||
0a488a53 YL |
109 | static int __init x86_fxsr_setup(char *s) |
110 | { | |
111 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
112 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
113 | return 1; | |
114 | } | |
115 | __setup("nofxsr", x86_fxsr_setup); | |
116 | ||
117 | static int __init x86_sep_setup(char *s) | |
118 | { | |
119 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
120 | return 1; | |
121 | } | |
122 | __setup("nosep", x86_sep_setup); | |
123 | ||
124 | /* Standard macro to see if a specific flag is changeable */ | |
125 | static inline int flag_is_changeable_p(u32 flag) | |
126 | { | |
127 | u32 f1, f2; | |
128 | ||
94f6bac1 KH |
129 | /* |
130 | * Cyrix and IDT cpus allow disabling of CPUID | |
131 | * so the code below may return different results | |
132 | * when it is executed before and after enabling | |
133 | * the CPUID. Add "volatile" to not allow gcc to | |
134 | * optimize the subsequent calls to this function. | |
135 | */ | |
136 | asm volatile ("pushfl\n\t" | |
137 | "pushfl\n\t" | |
138 | "popl %0\n\t" | |
139 | "movl %0,%1\n\t" | |
140 | "xorl %2,%0\n\t" | |
141 | "pushl %0\n\t" | |
142 | "popfl\n\t" | |
143 | "pushfl\n\t" | |
144 | "popl %0\n\t" | |
145 | "popfl\n\t" | |
146 | : "=&r" (f1), "=&r" (f2) | |
147 | : "ir" (flag)); | |
0a488a53 YL |
148 | |
149 | return ((f1^f2) & flag) != 0; | |
150 | } | |
151 | ||
152 | /* Probe for the CPUID instruction */ | |
153 | static int __cpuinit have_cpuid_p(void) | |
154 | { | |
155 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
156 | } | |
157 | ||
158 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
159 | { | |
160 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { | |
161 | /* Disable processor serial number */ | |
162 | unsigned long lo, hi; | |
163 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
164 | lo |= 0x200000; | |
165 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
166 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
167 | clear_cpu_cap(c, X86_FEATURE_PN); | |
168 | ||
169 | /* Disabling the serial number may affect the cpuid level */ | |
170 | c->cpuid_level = cpuid_eax(0); | |
171 | } | |
172 | } | |
173 | ||
174 | static int __init x86_serial_nr_setup(char *s) | |
175 | { | |
176 | disable_x86_serial_nr = 0; | |
177 | return 1; | |
178 | } | |
179 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 180 | #else |
102bbe3a YL |
181 | static inline int flag_is_changeable_p(u32 flag) |
182 | { | |
183 | return 1; | |
184 | } | |
ba51dced YL |
185 | /* Probe for the CPUID instruction */ |
186 | static inline int have_cpuid_p(void) | |
187 | { | |
188 | return 1; | |
189 | } | |
102bbe3a YL |
190 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
191 | { | |
192 | } | |
ba51dced | 193 | #endif |
0a488a53 | 194 | |
102bbe3a YL |
195 | /* |
196 | * Naming convention should be: <Name> [(<Codename>)] | |
197 | * This table only is used unless init_<vendor>() below doesn't set it; | |
198 | * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used | |
199 | * | |
200 | */ | |
201 | ||
202 | /* Look up CPU names by table lookup. */ | |
203 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) | |
204 | { | |
205 | struct cpu_model_info *info; | |
206 | ||
207 | if (c->x86_model >= 16) | |
208 | return NULL; /* Range check */ | |
209 | ||
210 | if (!this_cpu) | |
211 | return NULL; | |
212 | ||
213 | info = this_cpu->c_models; | |
214 | ||
215 | while (info && info->family) { | |
216 | if (info->family == c->x86) | |
217 | return info->model_names[c->x86_model]; | |
218 | info++; | |
219 | } | |
220 | return NULL; /* Not found */ | |
221 | } | |
222 | ||
7d851c8d AK |
223 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
224 | ||
9d31d35b YL |
225 | /* Current gdt points %fs at the "master" per-cpu area: after this, |
226 | * it's on the real one. */ | |
227 | void switch_to_new_gdt(void) | |
228 | { | |
229 | struct desc_ptr gdt_descr; | |
230 | ||
231 | gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id()); | |
232 | gdt_descr.size = GDT_SIZE - 1; | |
233 | load_gdt(&gdt_descr); | |
fab334c1 | 234 | #ifdef CONFIG_X86_32 |
9d31d35b | 235 | asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory"); |
fab334c1 | 236 | #endif |
9d31d35b YL |
237 | } |
238 | ||
10a434fc | 239 | static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 240 | |
34048c9e | 241 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
1da177e4 | 242 | { |
b9e67f00 YL |
243 | #ifdef CONFIG_X86_64 |
244 | display_cacheinfo(c); | |
245 | #else | |
1da177e4 LT |
246 | /* Not much we can do here... */ |
247 | /* Check if at least it has cpuid */ | |
248 | if (c->cpuid_level == -1) { | |
249 | /* No cpuid. It must be an ancient CPU */ | |
250 | if (c->x86 == 4) | |
251 | strcpy(c->x86_model_id, "486"); | |
252 | else if (c->x86 == 3) | |
253 | strcpy(c->x86_model_id, "386"); | |
254 | } | |
b9e67f00 | 255 | #endif |
1da177e4 LT |
256 | } |
257 | ||
95414930 | 258 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 259 | .c_init = default_init, |
fe38d855 | 260 | .c_vendor = "Unknown", |
10a434fc | 261 | .c_x86_vendor = X86_VENDOR_UNKNOWN, |
1da177e4 | 262 | }; |
1da177e4 | 263 | |
1b05d60d | 264 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
265 | { |
266 | unsigned int *v; | |
267 | char *p, *q; | |
268 | ||
3da99c97 | 269 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 270 | return; |
1da177e4 LT |
271 | |
272 | v = (unsigned int *) c->x86_model_id; | |
273 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
274 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
275 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
276 | c->x86_model_id[48] = 0; | |
277 | ||
278 | /* Intel chips right-justify this string for some dumb reason; | |
279 | undo that brain damage */ | |
280 | p = q = &c->x86_model_id[0]; | |
34048c9e | 281 | while (*p == ' ') |
1da177e4 | 282 | p++; |
34048c9e PC |
283 | if (p != q) { |
284 | while (*p) | |
1da177e4 | 285 | *q++ = *p++; |
34048c9e | 286 | while (q <= &c->x86_model_id[48]) |
1da177e4 LT |
287 | *q++ = '\0'; /* Zero-pad the rest */ |
288 | } | |
1da177e4 LT |
289 | } |
290 | ||
3bc9b76b | 291 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 | 292 | { |
9d31d35b | 293 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 294 | |
3da99c97 | 295 | n = c->extended_cpuid_level; |
1da177e4 LT |
296 | |
297 | if (n >= 0x80000005) { | |
9d31d35b | 298 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 299 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
9d31d35b YL |
300 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); |
301 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
140fc727 YL |
302 | #ifdef CONFIG_X86_64 |
303 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
304 | c->x86_tlbsize = 0; | |
305 | #endif | |
1da177e4 LT |
306 | } |
307 | ||
308 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
309 | return; | |
310 | ||
0a488a53 | 311 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 312 | l2size = ecx >> 16; |
34048c9e | 313 | |
140fc727 YL |
314 | #ifdef CONFIG_X86_64 |
315 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
316 | #else | |
1da177e4 LT |
317 | /* do processor-specific cache resizing */ |
318 | if (this_cpu->c_size_cache) | |
34048c9e | 319 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
320 | |
321 | /* Allow user to override all this if necessary. */ | |
322 | if (cachesize_override != -1) | |
323 | l2size = cachesize_override; | |
324 | ||
34048c9e | 325 | if (l2size == 0) |
1da177e4 | 326 | return; /* Again, no L2 cache is possible */ |
140fc727 | 327 | #endif |
1da177e4 LT |
328 | |
329 | c->x86_cache_size = l2size; | |
330 | ||
331 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
0a488a53 | 332 | l2size, ecx & 0xFF); |
1da177e4 LT |
333 | } |
334 | ||
9d31d35b | 335 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 336 | { |
97e4db7c | 337 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
338 | u32 eax, ebx, ecx, edx; |
339 | int index_msb, core_bits; | |
1da177e4 | 340 | |
0a488a53 | 341 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 342 | return; |
1da177e4 | 343 | |
0a488a53 YL |
344 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
345 | goto out; | |
1da177e4 | 346 | |
1cd78776 YL |
347 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
348 | return; | |
1da177e4 | 349 | |
0a488a53 | 350 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 351 | |
9d31d35b YL |
352 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
353 | ||
354 | if (smp_num_siblings == 1) { | |
355 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
356 | } else if (smp_num_siblings > 1) { | |
357 | ||
358 | if (smp_num_siblings > NR_CPUS) { | |
359 | printk(KERN_WARNING "CPU: Unsupported number of siblings %d", | |
360 | smp_num_siblings); | |
361 | smp_num_siblings = 1; | |
362 | return; | |
363 | } | |
364 | ||
365 | index_msb = get_count_order(smp_num_siblings); | |
1cd78776 YL |
366 | #ifdef CONFIG_X86_64 |
367 | c->phys_proc_id = phys_pkg_id(index_msb); | |
368 | #else | |
9d31d35b | 369 | c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb); |
1cd78776 | 370 | #endif |
9d31d35b YL |
371 | |
372 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
373 | ||
374 | index_msb = get_count_order(smp_num_siblings); | |
375 | ||
376 | core_bits = get_count_order(c->x86_max_cores); | |
377 | ||
1cd78776 YL |
378 | #ifdef CONFIG_X86_64 |
379 | c->cpu_core_id = phys_pkg_id(index_msb) & | |
380 | ((1 << core_bits) - 1); | |
381 | #else | |
9d31d35b YL |
382 | c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) & |
383 | ((1 << core_bits) - 1); | |
1cd78776 | 384 | #endif |
1da177e4 | 385 | } |
1da177e4 | 386 | |
0a488a53 YL |
387 | out: |
388 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
389 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
390 | c->phys_proc_id); | |
391 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
392 | c->cpu_core_id); | |
9d31d35b | 393 | } |
9d31d35b | 394 | #endif |
97e4db7c | 395 | } |
1da177e4 | 396 | |
3da99c97 | 397 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
398 | { |
399 | char *v = c->x86_vendor_id; | |
400 | int i; | |
fe38d855 | 401 | static int printed; |
1da177e4 LT |
402 | |
403 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
404 | if (!cpu_devs[i]) |
405 | break; | |
406 | ||
407 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
408 | (cpu_devs[i]->c_ident[1] && | |
409 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
410 | this_cpu = cpu_devs[i]; | |
411 | c->x86_vendor = this_cpu->c_x86_vendor; | |
412 | return; | |
1da177e4 LT |
413 | } |
414 | } | |
10a434fc | 415 | |
fe38d855 CE |
416 | if (!printed) { |
417 | printed++; | |
43603c8d | 418 | printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v); |
fe38d855 CE |
419 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); |
420 | } | |
10a434fc | 421 | |
fe38d855 CE |
422 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
423 | this_cpu = &default_cpu; | |
1da177e4 LT |
424 | } |
425 | ||
9d31d35b | 426 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 427 | { |
1da177e4 | 428 | /* Get vendor name */ |
4a148513 HH |
429 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
430 | (unsigned int *)&c->x86_vendor_id[0], | |
431 | (unsigned int *)&c->x86_vendor_id[8], | |
432 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 433 | |
1da177e4 | 434 | c->x86 = 4; |
9d31d35b | 435 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
436 | if (c->cpuid_level >= 0x00000001) { |
437 | u32 junk, tfms, cap0, misc; | |
438 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
9d31d35b YL |
439 | c->x86 = (tfms >> 8) & 0xf; |
440 | c->x86_model = (tfms >> 4) & 0xf; | |
441 | c->x86_mask = tfms & 0xf; | |
f5f786d0 | 442 | if (c->x86 == 0xf) |
1da177e4 | 443 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 444 | if (c->x86 >= 0x6) |
9d31d35b | 445 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
d4387bd3 | 446 | if (cap0 & (1<<19)) { |
d4387bd3 | 447 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 448 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 449 | } |
1da177e4 | 450 | } |
1da177e4 | 451 | } |
3da99c97 YL |
452 | |
453 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
093af8d7 YL |
454 | { |
455 | u32 tfms, xlvl; | |
3da99c97 | 456 | u32 ebx; |
093af8d7 | 457 | |
3da99c97 YL |
458 | /* Intel-defined flags: level 0x00000001 */ |
459 | if (c->cpuid_level >= 0x00000001) { | |
460 | u32 capability, excap; | |
461 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
462 | c->x86_capability[0] = capability; | |
463 | c->x86_capability[4] = excap; | |
464 | } | |
093af8d7 | 465 | |
3da99c97 YL |
466 | /* AMD-defined flags: level 0x80000001 */ |
467 | xlvl = cpuid_eax(0x80000000); | |
468 | c->extended_cpuid_level = xlvl; | |
469 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
470 | if (xlvl >= 0x80000001) { | |
471 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
472 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 473 | } |
093af8d7 | 474 | } |
093af8d7 | 475 | |
5122c890 | 476 | #ifdef CONFIG_X86_64 |
5122c890 YL |
477 | if (c->extended_cpuid_level >= 0x80000008) { |
478 | u32 eax = cpuid_eax(0x80000008); | |
479 | ||
480 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
481 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 482 | } |
5122c890 | 483 | #endif |
e3224234 YL |
484 | |
485 | if (c->extended_cpuid_level >= 0x80000007) | |
486 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 YL |
487 | |
488 | } | |
1da177e4 | 489 | |
aef93c8b YL |
490 | static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
491 | { | |
492 | #ifdef CONFIG_X86_32 | |
493 | int i; | |
494 | ||
495 | /* | |
496 | * First of all, decide if this is a 486 or higher | |
497 | * It's a 486 if we can modify the AC flag | |
498 | */ | |
499 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
500 | c->x86 = 4; | |
501 | else | |
502 | c->x86 = 3; | |
503 | ||
504 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
505 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
506 | c->x86_vendor_id[0] = 0; | |
507 | cpu_devs[i]->c_identify(c); | |
508 | if (c->x86_vendor_id[0]) { | |
509 | get_cpu_vendor(c); | |
510 | break; | |
511 | } | |
512 | } | |
513 | #endif | |
514 | } | |
515 | ||
34048c9e PC |
516 | /* |
517 | * Do minimum CPU detection early. | |
518 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
519 | * cache alignment. | |
520 | * The others are not touched to avoid unwanted side effects. | |
521 | * | |
522 | * WARNING: this function is only called on the BP. Don't add code here | |
523 | * that is supposed to run on all CPUs. | |
524 | */ | |
3da99c97 | 525 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 526 | { |
6627d242 YL |
527 | #ifdef CONFIG_X86_64 |
528 | c->x86_clflush_size = 64; | |
529 | #else | |
d4387bd3 | 530 | c->x86_clflush_size = 32; |
6627d242 | 531 | #endif |
0a488a53 | 532 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 533 | |
3da99c97 | 534 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 535 | c->extended_cpuid_level = 0; |
d7cd5611 | 536 | |
aef93c8b YL |
537 | if (!have_cpuid_p()) |
538 | identify_cpu_without_cpuid(c); | |
539 | ||
540 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
541 | if (!have_cpuid_p()) |
542 | return; | |
543 | ||
544 | cpu_detect(c); | |
545 | ||
3da99c97 | 546 | get_cpu_vendor(c); |
2b16a235 | 547 | |
3da99c97 | 548 | get_cpu_cap(c); |
12cf105c | 549 | |
10a434fc YL |
550 | if (this_cpu->c_early_init) |
551 | this_cpu->c_early_init(c); | |
093af8d7 | 552 | |
3da99c97 | 553 | validate_pat_support(c); |
bfcb4c1b | 554 | |
1c4acdb4 | 555 | #ifdef CONFIG_SMP |
bfcb4c1b | 556 | c->cpu_index = boot_cpu_id; |
1c4acdb4 | 557 | #endif |
d7cd5611 RR |
558 | } |
559 | ||
9d31d35b YL |
560 | void __init early_cpu_init(void) |
561 | { | |
10a434fc YL |
562 | struct cpu_dev **cdev; |
563 | int count = 0; | |
564 | ||
565 | printk("KERNEL supported cpus:\n"); | |
566 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { | |
567 | struct cpu_dev *cpudev = *cdev; | |
568 | unsigned int j; | |
9d31d35b | 569 | |
10a434fc YL |
570 | if (count >= X86_VENDOR_NUM) |
571 | break; | |
572 | cpu_devs[count] = cpudev; | |
573 | count++; | |
574 | ||
575 | for (j = 0; j < 2; j++) { | |
576 | if (!cpudev->c_ident[j]) | |
577 | continue; | |
578 | printk(" %s %s\n", cpudev->c_vendor, | |
579 | cpudev->c_ident[j]); | |
580 | } | |
581 | } | |
9d31d35b | 582 | |
9d31d35b | 583 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 584 | } |
093af8d7 | 585 | |
b6734c35 PA |
586 | /* |
587 | * The NOPL instruction is supposed to exist on all CPUs with | |
ba0593bf | 588 | * family >= 6; unfortunately, that's not true in practice because |
b6734c35 | 589 | * of early VIA chips and (more importantly) broken virtualizers that |
ba0593bf PA |
590 | * are not easy to detect. In the latter case it doesn't even *fail* |
591 | * reliably, so probing for it doesn't even work. Disable it completely | |
592 | * unless we can find a reliable way to detect all the broken cases. | |
b6734c35 PA |
593 | */ |
594 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
595 | { | |
b6734c35 | 596 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
d7cd5611 RR |
597 | } |
598 | ||
34048c9e | 599 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 600 | { |
aef93c8b | 601 | c->extended_cpuid_level = 0; |
1da177e4 | 602 | |
3da99c97 | 603 | if (!have_cpuid_p()) |
aef93c8b | 604 | identify_cpu_without_cpuid(c); |
1d67953f | 605 | |
aef93c8b | 606 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 607 | if (!have_cpuid_p()) |
aef93c8b | 608 | return; |
1da177e4 | 609 | |
3da99c97 | 610 | cpu_detect(c); |
1da177e4 | 611 | |
3da99c97 | 612 | get_cpu_vendor(c); |
1da177e4 | 613 | |
3da99c97 | 614 | get_cpu_cap(c); |
1da177e4 | 615 | |
3da99c97 YL |
616 | if (c->cpuid_level >= 0x00000001) { |
617 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
618 | #ifdef CONFIG_X86_32 |
619 | # ifdef CONFIG_X86_HT | |
3da99c97 | 620 | c->apicid = phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 621 | # else |
3da99c97 | 622 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
623 | # endif |
624 | #endif | |
1da177e4 | 625 | |
b89d3b3e YL |
626 | #ifdef CONFIG_X86_HT |
627 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 628 | #endif |
3da99c97 | 629 | } |
1da177e4 | 630 | |
1b05d60d | 631 | get_model_name(c); /* Default name */ |
1da177e4 | 632 | |
3da99c97 YL |
633 | init_scattered_cpuid_features(c); |
634 | detect_nopl(c); | |
1da177e4 | 635 | } |
1da177e4 LT |
636 | |
637 | /* | |
638 | * This does the hard work of actually picking apart the CPU stuff... | |
639 | */ | |
9a250347 | 640 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
641 | { |
642 | int i; | |
643 | ||
644 | c->loops_per_jiffy = loops_per_jiffy; | |
645 | c->x86_cache_size = -1; | |
646 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
647 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
648 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
649 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 650 | c->x86_max_cores = 1; |
102bbe3a | 651 | c->x86_coreid_bits = 0; |
11fdd252 | 652 | #ifdef CONFIG_X86_64 |
102bbe3a YL |
653 | c->x86_clflush_size = 64; |
654 | #else | |
655 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 656 | c->x86_clflush_size = 32; |
102bbe3a YL |
657 | #endif |
658 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
659 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
660 | ||
1da177e4 LT |
661 | generic_identify(c); |
662 | ||
3898534d | 663 | if (this_cpu->c_identify) |
1da177e4 LT |
664 | this_cpu->c_identify(c); |
665 | ||
102bbe3a YL |
666 | #ifdef CONFIG_X86_64 |
667 | c->apicid = phys_pkg_id(0); | |
668 | #endif | |
669 | ||
1da177e4 LT |
670 | /* |
671 | * Vendor-specific initialization. In this section we | |
672 | * canonicalize the feature flags, meaning if there are | |
673 | * features a certain CPU supports which CPUID doesn't | |
674 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
675 | * we handle them here. | |
676 | * | |
677 | * At the end of this section, c->x86_capability better | |
678 | * indicate the features this CPU genuinely supports! | |
679 | */ | |
680 | if (this_cpu->c_init) | |
681 | this_cpu->c_init(c); | |
682 | ||
683 | /* Disable the PN if appropriate */ | |
684 | squash_the_stupid_serial_number(c); | |
685 | ||
686 | /* | |
687 | * The vendor-specific functions might have changed features. Now | |
688 | * we do "generic changes." | |
689 | */ | |
690 | ||
1da177e4 | 691 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 692 | if (!c->x86_model_id[0]) { |
1da177e4 LT |
693 | char *p; |
694 | p = table_lookup_model(c); | |
34048c9e | 695 | if (p) |
1da177e4 LT |
696 | strcpy(c->x86_model_id, p); |
697 | else | |
698 | /* Last resort... */ | |
699 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 700 | c->x86, c->x86_model); |
1da177e4 LT |
701 | } |
702 | ||
102bbe3a YL |
703 | #ifdef CONFIG_X86_64 |
704 | detect_ht(c); | |
705 | #endif | |
706 | ||
88b094fb | 707 | init_hypervisor(c); |
1da177e4 LT |
708 | /* |
709 | * On SMP, boot_cpu_data holds the common feature set between | |
710 | * all CPUs; so make sure that we indicate which features are | |
711 | * common between the CPUs. The first time this routine gets | |
712 | * executed, c == &boot_cpu_data. | |
713 | */ | |
34048c9e | 714 | if (c != &boot_cpu_data) { |
1da177e4 | 715 | /* AND the already accumulated flags with these */ |
9d31d35b | 716 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
717 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
718 | } | |
719 | ||
7d851c8d AK |
720 | /* Clear all flags overriden by options */ |
721 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 722 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 723 | |
102bbe3a | 724 | #ifdef CONFIG_X86_MCE |
1da177e4 | 725 | /* Init Machine Check Exception if available. */ |
1da177e4 | 726 | mcheck_init(c); |
102bbe3a | 727 | #endif |
30d432df AK |
728 | |
729 | select_idle_routine(c); | |
102bbe3a YL |
730 | |
731 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
732 | numa_add_cpu(smp_processor_id()); | |
733 | #endif | |
a6c4e076 | 734 | } |
31ab269a | 735 | |
e04d645f GC |
736 | #ifdef CONFIG_X86_64 |
737 | static void vgetcpu_set_mode(void) | |
738 | { | |
739 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
740 | vgetcpu_mode = VGETCPU_RDTSCP; | |
741 | else | |
742 | vgetcpu_mode = VGETCPU_LSL; | |
743 | } | |
744 | #endif | |
745 | ||
a6c4e076 JF |
746 | void __init identify_boot_cpu(void) |
747 | { | |
748 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 749 | #ifdef CONFIG_X86_32 |
a6c4e076 | 750 | sysenter_setup(); |
6fe940d6 | 751 | enable_sep_cpu(); |
e04d645f GC |
752 | #else |
753 | vgetcpu_set_mode(); | |
102bbe3a | 754 | #endif |
a6c4e076 | 755 | } |
3b520b23 | 756 | |
a6c4e076 JF |
757 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
758 | { | |
759 | BUG_ON(c == &boot_cpu_data); | |
760 | identify_cpu(c); | |
102bbe3a | 761 | #ifdef CONFIG_X86_32 |
a6c4e076 | 762 | enable_sep_cpu(); |
102bbe3a | 763 | #endif |
a6c4e076 | 764 | mtrr_ap_init(); |
1da177e4 LT |
765 | } |
766 | ||
a0854a46 YL |
767 | struct msr_range { |
768 | unsigned min; | |
769 | unsigned max; | |
770 | }; | |
1da177e4 | 771 | |
a0854a46 YL |
772 | static struct msr_range msr_range_array[] __cpuinitdata = { |
773 | { 0x00000000, 0x00000418}, | |
774 | { 0xc0000000, 0xc000040b}, | |
775 | { 0xc0010000, 0xc0010142}, | |
776 | { 0xc0011000, 0xc001103b}, | |
777 | }; | |
1da177e4 | 778 | |
a0854a46 YL |
779 | static void __cpuinit print_cpu_msr(void) |
780 | { | |
781 | unsigned index; | |
782 | u64 val; | |
783 | int i; | |
784 | unsigned index_min, index_max; | |
785 | ||
786 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
787 | index_min = msr_range_array[i].min; | |
788 | index_max = msr_range_array[i].max; | |
789 | for (index = index_min; index < index_max; index++) { | |
790 | if (rdmsrl_amd_safe(index, &val)) | |
791 | continue; | |
792 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 793 | } |
a0854a46 YL |
794 | } |
795 | } | |
94605eff | 796 | |
a0854a46 YL |
797 | static int show_msr __cpuinitdata; |
798 | static __init int setup_show_msr(char *arg) | |
799 | { | |
800 | int num; | |
3dd9d514 | 801 | |
a0854a46 | 802 | get_option(&arg, &num); |
3dd9d514 | 803 | |
a0854a46 YL |
804 | if (num > 0) |
805 | show_msr = num; | |
806 | return 1; | |
1da177e4 | 807 | } |
a0854a46 | 808 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 809 | |
191679fd AK |
810 | static __init int setup_noclflush(char *arg) |
811 | { | |
812 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
813 | return 1; | |
814 | } | |
815 | __setup("noclflush", setup_noclflush); | |
816 | ||
3bc9b76b | 817 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
818 | { |
819 | char *vendor = NULL; | |
820 | ||
821 | if (c->x86_vendor < X86_VENDOR_NUM) | |
822 | vendor = this_cpu->c_vendor; | |
823 | else if (c->cpuid_level >= 0) | |
824 | vendor = c->x86_vendor_id; | |
825 | ||
bd32a8cf | 826 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 827 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 828 | |
9d31d35b YL |
829 | if (c->x86_model_id[0]) |
830 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 831 | else |
9d31d35b | 832 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 833 | |
34048c9e | 834 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 835 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 836 | else |
9d31d35b | 837 | printk(KERN_CONT "\n"); |
a0854a46 YL |
838 | |
839 | #ifdef CONFIG_SMP | |
840 | if (c->cpu_index < show_msr) | |
841 | print_cpu_msr(); | |
842 | #else | |
843 | if (show_msr) | |
844 | print_cpu_msr(); | |
845 | #endif | |
1da177e4 LT |
846 | } |
847 | ||
ac72e788 AK |
848 | static __init int setup_disablecpuid(char *arg) |
849 | { | |
850 | int bit; | |
851 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
852 | setup_clear_cpu_cap(bit); | |
853 | else | |
854 | return 0; | |
855 | return 1; | |
856 | } | |
857 | __setup("clearcpuid=", setup_disablecpuid); | |
858 | ||
3bc9b76b | 859 | cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; |
1da177e4 | 860 | |
d5494d4f YL |
861 | #ifdef CONFIG_X86_64 |
862 | struct x8664_pda **_cpu_pda __read_mostly; | |
863 | EXPORT_SYMBOL(_cpu_pda); | |
864 | ||
865 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; | |
866 | ||
34945ede | 867 | static char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss; |
d5494d4f | 868 | |
2d9cd6c2 | 869 | void __cpuinit pda_init(int cpu) |
d5494d4f YL |
870 | { |
871 | struct x8664_pda *pda = cpu_pda(cpu); | |
872 | ||
873 | /* Setup up data that may be needed in __get_free_pages early */ | |
874 | loadsegment(fs, 0); | |
875 | loadsegment(gs, 0); | |
876 | /* Memory clobbers used to order PDA accessed */ | |
877 | mb(); | |
878 | wrmsrl(MSR_GS_BASE, pda); | |
879 | mb(); | |
880 | ||
881 | pda->cpunumber = cpu; | |
882 | pda->irqcount = -1; | |
883 | pda->kernelstack = (unsigned long)stack_thread_info() - | |
884 | PDA_STACKOFFSET + THREAD_SIZE; | |
885 | pda->active_mm = &init_mm; | |
886 | pda->mmu_state = 0; | |
887 | ||
888 | if (cpu == 0) { | |
889 | /* others are initialized in smpboot.c */ | |
890 | pda->pcurrent = &init_task; | |
891 | pda->irqstackptr = boot_cpu_stack; | |
892 | pda->irqstackptr += IRQSTACKSIZE - 64; | |
893 | } else { | |
894 | if (!pda->irqstackptr) { | |
895 | pda->irqstackptr = (char *) | |
896 | __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER); | |
897 | if (!pda->irqstackptr) | |
898 | panic("cannot allocate irqstack for cpu %d", | |
899 | cpu); | |
900 | pda->irqstackptr += IRQSTACKSIZE - 64; | |
901 | } | |
902 | ||
903 | if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE) | |
904 | pda->nodenumber = cpu_to_node(cpu); | |
905 | } | |
906 | } | |
907 | ||
34945ede JS |
908 | static char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + |
909 | DEBUG_STKSZ] __page_aligned_bss; | |
d5494d4f YL |
910 | |
911 | extern asmlinkage void ignore_sysret(void); | |
912 | ||
913 | /* May not be marked __init: used by software suspend */ | |
914 | void syscall_init(void) | |
1da177e4 | 915 | { |
d5494d4f YL |
916 | /* |
917 | * LSTAR and STAR live in a bit strange symbiosis. | |
918 | * They both write to the same internal register. STAR allows to | |
919 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
920 | */ | |
921 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
922 | wrmsrl(MSR_LSTAR, system_call); | |
923 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 924 | |
d5494d4f YL |
925 | #ifdef CONFIG_IA32_EMULATION |
926 | syscall32_cpu_init(); | |
927 | #endif | |
03ae5768 | 928 | |
d5494d4f YL |
929 | /* Flags to clear on syscall */ |
930 | wrmsrl(MSR_SYSCALL_MASK, | |
931 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
1da177e4 | 932 | } |
62111195 | 933 | |
d5494d4f YL |
934 | unsigned long kernel_eflags; |
935 | ||
936 | /* | |
937 | * Copies of the original ist values from the tss are only accessed during | |
938 | * debugging, no special alignment required. | |
939 | */ | |
940 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
941 | ||
942 | #else | |
943 | ||
7c3576d2 | 944 | /* Make sure %fs is initialized properly in idle threads */ |
6b2fb3c6 | 945 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
946 | { |
947 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 948 | regs->fs = __KERNEL_PERCPU; |
f95d47ca JF |
949 | return regs; |
950 | } | |
d5494d4f | 951 | #endif |
c5413fbe | 952 | |
d2cbcc49 RR |
953 | /* |
954 | * cpu_init() initializes state that is per-CPU. Some data is already | |
955 | * initialized (naturally) in the bootstrap process, such as the GDT | |
956 | * and IDT. We reload them nevertheless, this function acts as a | |
957 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 958 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 959 | */ |
1ba76586 YL |
960 | #ifdef CONFIG_X86_64 |
961 | void __cpuinit cpu_init(void) | |
962 | { | |
963 | int cpu = stack_smp_processor_id(); | |
964 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
965 | struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); | |
966 | unsigned long v; | |
967 | char *estacks = NULL; | |
968 | struct task_struct *me; | |
969 | int i; | |
970 | ||
971 | /* CPU 0 is initialised in head64.c */ | |
972 | if (cpu != 0) | |
973 | pda_init(cpu); | |
974 | else | |
975 | estacks = boot_exception_stacks; | |
976 | ||
977 | me = current; | |
978 | ||
979 | if (cpu_test_and_set(cpu, cpu_initialized)) | |
980 | panic("CPU#%d already initialized!\n", cpu); | |
981 | ||
982 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
983 | ||
984 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
985 | ||
986 | /* | |
987 | * Initialize the per-CPU GDT with the boot GDT, | |
988 | * and set up the GDT descriptor: | |
989 | */ | |
990 | ||
991 | switch_to_new_gdt(); | |
992 | load_idt((const struct desc_ptr *)&idt_descr); | |
993 | ||
994 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
995 | syscall_init(); | |
996 | ||
997 | wrmsrl(MSR_FS_BASE, 0); | |
998 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
999 | barrier(); | |
1000 | ||
1001 | check_efer(); | |
1002 | if (cpu != 0 && x2apic) | |
1003 | enable_x2apic(); | |
1004 | ||
1005 | /* | |
1006 | * set up and load the per-CPU TSS | |
1007 | */ | |
1008 | if (!orig_ist->ist[0]) { | |
1009 | static const unsigned int order[N_EXCEPTION_STACKS] = { | |
1010 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER, | |
1011 | [DEBUG_STACK - 1] = DEBUG_STACK_ORDER | |
1012 | }; | |
1013 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { | |
1014 | if (cpu) { | |
1015 | estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]); | |
1016 | if (!estacks) | |
1017 | panic("Cannot allocate exception " | |
1018 | "stack %ld %d\n", v, cpu); | |
1019 | } | |
1020 | estacks += PAGE_SIZE << order[v]; | |
1021 | orig_ist->ist[v] = t->x86_tss.ist[v] = | |
1022 | (unsigned long)estacks; | |
1023 | } | |
1024 | } | |
1025 | ||
1026 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
1027 | /* | |
1028 | * <= is required because the CPU will access up to | |
1029 | * 8 bits beyond the end of the IO permission bitmap. | |
1030 | */ | |
1031 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1032 | t->io_bitmap[i] = ~0UL; | |
1033 | ||
1034 | atomic_inc(&init_mm.mm_count); | |
1035 | me->active_mm = &init_mm; | |
1036 | if (me->mm) | |
1037 | BUG(); | |
1038 | enter_lazy_tlb(&init_mm, me); | |
1039 | ||
1040 | load_sp0(t, ¤t->thread); | |
1041 | set_tss_desc(cpu, t); | |
1042 | load_TR_desc(); | |
1043 | load_LDT(&init_mm.context); | |
1044 | ||
1045 | #ifdef CONFIG_KGDB | |
1046 | /* | |
1047 | * If the kgdb is connected no debug regs should be altered. This | |
1048 | * is only applicable when KGDB and a KGDB I/O module are built | |
1049 | * into the kernel and you are using early debugging with | |
1050 | * kgdbwait. KGDB will control the kernel HW breakpoint registers. | |
1051 | */ | |
1052 | if (kgdb_connected && arch_kgdb_ops.correct_hw_break) | |
1053 | arch_kgdb_ops.correct_hw_break(); | |
1054 | else { | |
1055 | #endif | |
1056 | /* | |
1057 | * Clear all 6 debug registers: | |
1058 | */ | |
1059 | ||
1060 | set_debugreg(0UL, 0); | |
1061 | set_debugreg(0UL, 1); | |
1062 | set_debugreg(0UL, 2); | |
1063 | set_debugreg(0UL, 3); | |
1064 | set_debugreg(0UL, 6); | |
1065 | set_debugreg(0UL, 7); | |
1066 | #ifdef CONFIG_KGDB | |
1067 | /* If the kgdb is connected no debug regs should be altered. */ | |
1068 | } | |
1069 | #endif | |
1070 | ||
1071 | fpu_init(); | |
1072 | ||
1073 | raw_local_save_flags(kernel_eflags); | |
1074 | ||
1075 | if (is_uv_system()) | |
1076 | uv_cpu_init(); | |
1077 | } | |
1078 | ||
1079 | #else | |
1080 | ||
d2cbcc49 | 1081 | void __cpuinit cpu_init(void) |
9ee79a3d | 1082 | { |
d2cbcc49 RR |
1083 | int cpu = smp_processor_id(); |
1084 | struct task_struct *curr = current; | |
34048c9e | 1085 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1086 | struct thread_struct *thread = &curr->thread; |
62111195 JF |
1087 | |
1088 | if (cpu_test_and_set(cpu, cpu_initialized)) { | |
1089 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); | |
1090 | for (;;) local_irq_enable(); | |
1091 | } | |
1092 | ||
1093 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1094 | ||
1095 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1096 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1097 | |
4d37e7e3 | 1098 | load_idt(&idt_descr); |
c5413fbe | 1099 | switch_to_new_gdt(); |
1da177e4 | 1100 | |
1da177e4 LT |
1101 | /* |
1102 | * Set up and load the per-CPU TSS and LDT | |
1103 | */ | |
1104 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
1105 | curr->active_mm = &init_mm; |
1106 | if (curr->mm) | |
1107 | BUG(); | |
1108 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 | 1109 | |
faca6227 | 1110 | load_sp0(t, thread); |
34048c9e | 1111 | set_tss_desc(cpu, t); |
1da177e4 LT |
1112 | load_TR_desc(); |
1113 | load_LDT(&init_mm.context); | |
1114 | ||
22c4e308 | 1115 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1116 | /* Set up doublefault TSS pointer in the GDT */ |
1117 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1118 | #endif |
1da177e4 | 1119 | |
464d1a78 JF |
1120 | /* Clear %gs. */ |
1121 | asm volatile ("mov %0, %%gs" : : "r" (0)); | |
1da177e4 LT |
1122 | |
1123 | /* Clear all 6 debug registers: */ | |
4bb0d3ec ZA |
1124 | set_debugreg(0, 0); |
1125 | set_debugreg(0, 1); | |
1126 | set_debugreg(0, 2); | |
1127 | set_debugreg(0, 3); | |
1128 | set_debugreg(0, 6); | |
1129 | set_debugreg(0, 7); | |
1da177e4 LT |
1130 | |
1131 | /* | |
1132 | * Force FPU initialization: | |
1133 | */ | |
b359e8a4 SS |
1134 | if (cpu_has_xsave) |
1135 | current_thread_info()->status = TS_XSAVE; | |
1136 | else | |
1137 | current_thread_info()->status = 0; | |
1da177e4 LT |
1138 | clear_used_math(); |
1139 | mxcsr_feature_mask_init(); | |
dc1e35c6 SS |
1140 | |
1141 | /* | |
1142 | * Boot processor to setup the FP and extended state context info. | |
1143 | */ | |
b3572e36 | 1144 | if (smp_processor_id() == boot_cpu_id) |
dc1e35c6 SS |
1145 | init_thread_xstate(); |
1146 | ||
1147 | xsave_init(); | |
1da177e4 | 1148 | } |
e1367daf | 1149 | |
1ba76586 YL |
1150 | |
1151 | #endif |