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1da177e4 | 1 | #include <linux/init.h> |
f0fc4aff YL |
2 | #include <linux/kernel.h> |
3 | #include <linux/sched.h> | |
1da177e4 | 4 | #include <linux/string.h> |
f0fc4aff YL |
5 | #include <linux/bootmem.h> |
6 | #include <linux/bitops.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/kgdb.h> | |
9 | #include <linux/topology.h> | |
1da177e4 LT |
10 | #include <linux/delay.h> |
11 | #include <linux/smp.h> | |
1da177e4 | 12 | #include <linux/percpu.h> |
1da177e4 LT |
13 | #include <asm/i387.h> |
14 | #include <asm/msr.h> | |
15 | #include <asm/io.h> | |
f0fc4aff | 16 | #include <asm/linkage.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
27b07da7 | 18 | #include <asm/mtrr.h> |
a03a3e28 | 19 | #include <asm/mce.h> |
8d4a4300 | 20 | #include <asm/pat.h> |
b6734c35 | 21 | #include <asm/asm.h> |
f0fc4aff | 22 | #include <asm/numa.h> |
b342797c | 23 | #include <asm/smp.h> |
1da177e4 LT |
24 | #ifdef CONFIG_X86_LOCAL_APIC |
25 | #include <asm/mpspec.h> | |
26 | #include <asm/apic.h> | |
27 | #include <mach_apic.h> | |
f0fc4aff | 28 | #include <asm/genapic.h> |
1da177e4 LT |
29 | #endif |
30 | ||
f0fc4aff YL |
31 | #include <asm/pda.h> |
32 | #include <asm/pgtable.h> | |
33 | #include <asm/processor.h> | |
34 | #include <asm/desc.h> | |
35 | #include <asm/atomic.h> | |
36 | #include <asm/proto.h> | |
37 | #include <asm/sections.h> | |
38 | #include <asm/setup.h> | |
88b094fb | 39 | #include <asm/hypervisor.h> |
f0fc4aff | 40 | |
1da177e4 LT |
41 | #include "cpu.h" |
42 | ||
c2d1cec1 MT |
43 | #ifdef CONFIG_X86_64 |
44 | ||
45 | /* all of these masks are initialized in setup_cpu_local_masks() */ | |
46 | cpumask_var_t cpu_callin_mask; | |
47 | cpumask_var_t cpu_callout_mask; | |
48 | cpumask_var_t cpu_initialized_mask; | |
49 | ||
50 | /* representing cpus for which sibling maps can be computed */ | |
51 | cpumask_var_t cpu_sibling_setup_mask; | |
52 | ||
53 | #else /* CONFIG_X86_32 */ | |
54 | ||
55 | cpumask_t cpu_callin_map; | |
56 | cpumask_t cpu_callout_map; | |
57 | cpumask_t cpu_initialized; | |
58 | cpumask_t cpu_sibling_setup_map; | |
59 | ||
60 | #endif /* CONFIG_X86_32 */ | |
61 | ||
62 | ||
0a488a53 YL |
63 | static struct cpu_dev *this_cpu __cpuinitdata; |
64 | ||
950ad7ff YL |
65 | #ifdef CONFIG_X86_64 |
66 | /* We need valid kernel segments for data and code in long mode too | |
67 | * IRET will check the segment types kkeil 2000/10/28 | |
68 | * Also sysret mandates a special GDT layout | |
69 | */ | |
70 | /* The TLS descriptors are currently at a different place compared to i386. | |
71 | Hopefully nobody expects them at a fixed place (Wine?) */ | |
7a61d35d | 72 | DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff YL |
73 | [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, |
74 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, | |
75 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, | |
76 | [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, | |
77 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, | |
78 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, | |
79 | } }; | |
80 | #else | |
63cc8c75 | 81 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
6842ef0e GOC |
82 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
83 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
84 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
85 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
86 | /* |
87 | * Segments used for calling PnP BIOS have byte granularity. | |
88 | * They code segments and data segments have fixed 64k limits, | |
89 | * the transfer segment sizes are set at run time. | |
90 | */ | |
6842ef0e GOC |
91 | /* 32-bit code */ |
92 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
93 | /* 16-bit code */ | |
94 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
95 | /* 16-bit data */ | |
96 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
97 | /* 16-bit data */ | |
98 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
99 | /* 16-bit data */ | |
100 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
bf504672 RR |
101 | /* |
102 | * The APM segments have byte granularity and their bases | |
103 | * are set at run time. All have 64k limits. | |
104 | */ | |
6842ef0e GOC |
105 | /* 32-bit code */ |
106 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
bf504672 | 107 | /* 16-bit code */ |
6842ef0e GOC |
108 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
109 | /* data */ | |
110 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
bf504672 | 111 | |
6842ef0e GOC |
112 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
113 | [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } }, | |
7a61d35d | 114 | } }; |
950ad7ff | 115 | #endif |
7a61d35d | 116 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 117 | |
ba51dced | 118 | #ifdef CONFIG_X86_32 |
3bc9b76b | 119 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 120 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 121 | |
0a488a53 YL |
122 | static int __init cachesize_setup(char *str) |
123 | { | |
124 | get_option(&str, &cachesize_override); | |
125 | return 1; | |
126 | } | |
127 | __setup("cachesize=", cachesize_setup); | |
128 | ||
0a488a53 YL |
129 | static int __init x86_fxsr_setup(char *s) |
130 | { | |
131 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
132 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
133 | return 1; | |
134 | } | |
135 | __setup("nofxsr", x86_fxsr_setup); | |
136 | ||
137 | static int __init x86_sep_setup(char *s) | |
138 | { | |
139 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
140 | return 1; | |
141 | } | |
142 | __setup("nosep", x86_sep_setup); | |
143 | ||
144 | /* Standard macro to see if a specific flag is changeable */ | |
145 | static inline int flag_is_changeable_p(u32 flag) | |
146 | { | |
147 | u32 f1, f2; | |
148 | ||
94f6bac1 KH |
149 | /* |
150 | * Cyrix and IDT cpus allow disabling of CPUID | |
151 | * so the code below may return different results | |
152 | * when it is executed before and after enabling | |
153 | * the CPUID. Add "volatile" to not allow gcc to | |
154 | * optimize the subsequent calls to this function. | |
155 | */ | |
156 | asm volatile ("pushfl\n\t" | |
157 | "pushfl\n\t" | |
158 | "popl %0\n\t" | |
159 | "movl %0,%1\n\t" | |
160 | "xorl %2,%0\n\t" | |
161 | "pushl %0\n\t" | |
162 | "popfl\n\t" | |
163 | "pushfl\n\t" | |
164 | "popl %0\n\t" | |
165 | "popfl\n\t" | |
166 | : "=&r" (f1), "=&r" (f2) | |
167 | : "ir" (flag)); | |
0a488a53 YL |
168 | |
169 | return ((f1^f2) & flag) != 0; | |
170 | } | |
171 | ||
172 | /* Probe for the CPUID instruction */ | |
173 | static int __cpuinit have_cpuid_p(void) | |
174 | { | |
175 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
176 | } | |
177 | ||
178 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
179 | { | |
180 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { | |
181 | /* Disable processor serial number */ | |
182 | unsigned long lo, hi; | |
183 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
184 | lo |= 0x200000; | |
185 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
186 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
187 | clear_cpu_cap(c, X86_FEATURE_PN); | |
188 | ||
189 | /* Disabling the serial number may affect the cpuid level */ | |
190 | c->cpuid_level = cpuid_eax(0); | |
191 | } | |
192 | } | |
193 | ||
194 | static int __init x86_serial_nr_setup(char *s) | |
195 | { | |
196 | disable_x86_serial_nr = 0; | |
197 | return 1; | |
198 | } | |
199 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 200 | #else |
102bbe3a YL |
201 | static inline int flag_is_changeable_p(u32 flag) |
202 | { | |
203 | return 1; | |
204 | } | |
ba51dced YL |
205 | /* Probe for the CPUID instruction */ |
206 | static inline int have_cpuid_p(void) | |
207 | { | |
208 | return 1; | |
209 | } | |
102bbe3a YL |
210 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
211 | { | |
212 | } | |
ba51dced | 213 | #endif |
0a488a53 | 214 | |
102bbe3a YL |
215 | /* |
216 | * Naming convention should be: <Name> [(<Codename>)] | |
217 | * This table only is used unless init_<vendor>() below doesn't set it; | |
218 | * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used | |
219 | * | |
220 | */ | |
221 | ||
222 | /* Look up CPU names by table lookup. */ | |
223 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) | |
224 | { | |
225 | struct cpu_model_info *info; | |
226 | ||
227 | if (c->x86_model >= 16) | |
228 | return NULL; /* Range check */ | |
229 | ||
230 | if (!this_cpu) | |
231 | return NULL; | |
232 | ||
233 | info = this_cpu->c_models; | |
234 | ||
235 | while (info && info->family) { | |
236 | if (info->family == c->x86) | |
237 | return info->model_names[c->x86_model]; | |
238 | info++; | |
239 | } | |
240 | return NULL; /* Not found */ | |
241 | } | |
242 | ||
7d851c8d AK |
243 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
244 | ||
9d31d35b YL |
245 | /* Current gdt points %fs at the "master" per-cpu area: after this, |
246 | * it's on the real one. */ | |
247 | void switch_to_new_gdt(void) | |
248 | { | |
249 | struct desc_ptr gdt_descr; | |
250 | ||
251 | gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id()); | |
252 | gdt_descr.size = GDT_SIZE - 1; | |
253 | load_gdt(&gdt_descr); | |
fab334c1 | 254 | #ifdef CONFIG_X86_32 |
9d31d35b | 255 | asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory"); |
fab334c1 | 256 | #endif |
9d31d35b YL |
257 | } |
258 | ||
10a434fc | 259 | static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 260 | |
34048c9e | 261 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
1da177e4 | 262 | { |
b9e67f00 YL |
263 | #ifdef CONFIG_X86_64 |
264 | display_cacheinfo(c); | |
265 | #else | |
1da177e4 LT |
266 | /* Not much we can do here... */ |
267 | /* Check if at least it has cpuid */ | |
268 | if (c->cpuid_level == -1) { | |
269 | /* No cpuid. It must be an ancient CPU */ | |
270 | if (c->x86 == 4) | |
271 | strcpy(c->x86_model_id, "486"); | |
272 | else if (c->x86 == 3) | |
273 | strcpy(c->x86_model_id, "386"); | |
274 | } | |
b9e67f00 | 275 | #endif |
1da177e4 LT |
276 | } |
277 | ||
95414930 | 278 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 279 | .c_init = default_init, |
fe38d855 | 280 | .c_vendor = "Unknown", |
10a434fc | 281 | .c_x86_vendor = X86_VENDOR_UNKNOWN, |
1da177e4 | 282 | }; |
1da177e4 | 283 | |
1b05d60d | 284 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
285 | { |
286 | unsigned int *v; | |
287 | char *p, *q; | |
288 | ||
3da99c97 | 289 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 290 | return; |
1da177e4 LT |
291 | |
292 | v = (unsigned int *) c->x86_model_id; | |
293 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
294 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
295 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
296 | c->x86_model_id[48] = 0; | |
297 | ||
298 | /* Intel chips right-justify this string for some dumb reason; | |
299 | undo that brain damage */ | |
300 | p = q = &c->x86_model_id[0]; | |
34048c9e | 301 | while (*p == ' ') |
1da177e4 | 302 | p++; |
34048c9e PC |
303 | if (p != q) { |
304 | while (*p) | |
1da177e4 | 305 | *q++ = *p++; |
34048c9e | 306 | while (q <= &c->x86_model_id[48]) |
1da177e4 LT |
307 | *q++ = '\0'; /* Zero-pad the rest */ |
308 | } | |
1da177e4 LT |
309 | } |
310 | ||
3bc9b76b | 311 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 | 312 | { |
9d31d35b | 313 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 314 | |
3da99c97 | 315 | n = c->extended_cpuid_level; |
1da177e4 LT |
316 | |
317 | if (n >= 0x80000005) { | |
9d31d35b | 318 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 319 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
9d31d35b YL |
320 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); |
321 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
140fc727 YL |
322 | #ifdef CONFIG_X86_64 |
323 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
324 | c->x86_tlbsize = 0; | |
325 | #endif | |
1da177e4 LT |
326 | } |
327 | ||
328 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
329 | return; | |
330 | ||
0a488a53 | 331 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 332 | l2size = ecx >> 16; |
34048c9e | 333 | |
140fc727 YL |
334 | #ifdef CONFIG_X86_64 |
335 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
336 | #else | |
1da177e4 LT |
337 | /* do processor-specific cache resizing */ |
338 | if (this_cpu->c_size_cache) | |
34048c9e | 339 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
340 | |
341 | /* Allow user to override all this if necessary. */ | |
342 | if (cachesize_override != -1) | |
343 | l2size = cachesize_override; | |
344 | ||
34048c9e | 345 | if (l2size == 0) |
1da177e4 | 346 | return; /* Again, no L2 cache is possible */ |
140fc727 | 347 | #endif |
1da177e4 LT |
348 | |
349 | c->x86_cache_size = l2size; | |
350 | ||
351 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
0a488a53 | 352 | l2size, ecx & 0xFF); |
1da177e4 LT |
353 | } |
354 | ||
9d31d35b | 355 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 356 | { |
97e4db7c | 357 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
358 | u32 eax, ebx, ecx, edx; |
359 | int index_msb, core_bits; | |
1da177e4 | 360 | |
0a488a53 | 361 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 362 | return; |
1da177e4 | 363 | |
0a488a53 YL |
364 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
365 | goto out; | |
1da177e4 | 366 | |
1cd78776 YL |
367 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
368 | return; | |
1da177e4 | 369 | |
0a488a53 | 370 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 371 | |
9d31d35b YL |
372 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
373 | ||
374 | if (smp_num_siblings == 1) { | |
375 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
376 | } else if (smp_num_siblings > 1) { | |
377 | ||
9628937d | 378 | if (smp_num_siblings > nr_cpu_ids) { |
9d31d35b YL |
379 | printk(KERN_WARNING "CPU: Unsupported number of siblings %d", |
380 | smp_num_siblings); | |
381 | smp_num_siblings = 1; | |
382 | return; | |
383 | } | |
384 | ||
385 | index_msb = get_count_order(smp_num_siblings); | |
1cd78776 YL |
386 | #ifdef CONFIG_X86_64 |
387 | c->phys_proc_id = phys_pkg_id(index_msb); | |
388 | #else | |
9d31d35b | 389 | c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb); |
1cd78776 | 390 | #endif |
9d31d35b YL |
391 | |
392 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
393 | ||
394 | index_msb = get_count_order(smp_num_siblings); | |
395 | ||
396 | core_bits = get_count_order(c->x86_max_cores); | |
397 | ||
1cd78776 YL |
398 | #ifdef CONFIG_X86_64 |
399 | c->cpu_core_id = phys_pkg_id(index_msb) & | |
400 | ((1 << core_bits) - 1); | |
401 | #else | |
9d31d35b YL |
402 | c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) & |
403 | ((1 << core_bits) - 1); | |
1cd78776 | 404 | #endif |
1da177e4 | 405 | } |
1da177e4 | 406 | |
0a488a53 YL |
407 | out: |
408 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
409 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
410 | c->phys_proc_id); | |
411 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
412 | c->cpu_core_id); | |
9d31d35b | 413 | } |
9d31d35b | 414 | #endif |
97e4db7c | 415 | } |
1da177e4 | 416 | |
3da99c97 | 417 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
418 | { |
419 | char *v = c->x86_vendor_id; | |
420 | int i; | |
fe38d855 | 421 | static int printed; |
1da177e4 LT |
422 | |
423 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
424 | if (!cpu_devs[i]) |
425 | break; | |
426 | ||
427 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
428 | (cpu_devs[i]->c_ident[1] && | |
429 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
430 | this_cpu = cpu_devs[i]; | |
431 | c->x86_vendor = this_cpu->c_x86_vendor; | |
432 | return; | |
1da177e4 LT |
433 | } |
434 | } | |
10a434fc | 435 | |
fe38d855 CE |
436 | if (!printed) { |
437 | printed++; | |
43603c8d | 438 | printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v); |
fe38d855 CE |
439 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); |
440 | } | |
10a434fc | 441 | |
fe38d855 CE |
442 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
443 | this_cpu = &default_cpu; | |
1da177e4 LT |
444 | } |
445 | ||
9d31d35b | 446 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 447 | { |
1da177e4 | 448 | /* Get vendor name */ |
4a148513 HH |
449 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
450 | (unsigned int *)&c->x86_vendor_id[0], | |
451 | (unsigned int *)&c->x86_vendor_id[8], | |
452 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 453 | |
1da177e4 | 454 | c->x86 = 4; |
9d31d35b | 455 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
456 | if (c->cpuid_level >= 0x00000001) { |
457 | u32 junk, tfms, cap0, misc; | |
458 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
9d31d35b YL |
459 | c->x86 = (tfms >> 8) & 0xf; |
460 | c->x86_model = (tfms >> 4) & 0xf; | |
461 | c->x86_mask = tfms & 0xf; | |
f5f786d0 | 462 | if (c->x86 == 0xf) |
1da177e4 | 463 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 464 | if (c->x86 >= 0x6) |
9d31d35b | 465 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
d4387bd3 | 466 | if (cap0 & (1<<19)) { |
d4387bd3 | 467 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 468 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 469 | } |
1da177e4 | 470 | } |
1da177e4 | 471 | } |
3da99c97 YL |
472 | |
473 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
093af8d7 YL |
474 | { |
475 | u32 tfms, xlvl; | |
3da99c97 | 476 | u32 ebx; |
093af8d7 | 477 | |
3da99c97 YL |
478 | /* Intel-defined flags: level 0x00000001 */ |
479 | if (c->cpuid_level >= 0x00000001) { | |
480 | u32 capability, excap; | |
481 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
482 | c->x86_capability[0] = capability; | |
483 | c->x86_capability[4] = excap; | |
484 | } | |
093af8d7 | 485 | |
3da99c97 YL |
486 | /* AMD-defined flags: level 0x80000001 */ |
487 | xlvl = cpuid_eax(0x80000000); | |
488 | c->extended_cpuid_level = xlvl; | |
489 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
490 | if (xlvl >= 0x80000001) { | |
491 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
492 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 493 | } |
093af8d7 | 494 | } |
093af8d7 | 495 | |
5122c890 | 496 | #ifdef CONFIG_X86_64 |
5122c890 YL |
497 | if (c->extended_cpuid_level >= 0x80000008) { |
498 | u32 eax = cpuid_eax(0x80000008); | |
499 | ||
500 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
501 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 502 | } |
5122c890 | 503 | #endif |
e3224234 YL |
504 | |
505 | if (c->extended_cpuid_level >= 0x80000007) | |
506 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 YL |
507 | |
508 | } | |
1da177e4 | 509 | |
aef93c8b YL |
510 | static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
511 | { | |
512 | #ifdef CONFIG_X86_32 | |
513 | int i; | |
514 | ||
515 | /* | |
516 | * First of all, decide if this is a 486 or higher | |
517 | * It's a 486 if we can modify the AC flag | |
518 | */ | |
519 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
520 | c->x86 = 4; | |
521 | else | |
522 | c->x86 = 3; | |
523 | ||
524 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
525 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
526 | c->x86_vendor_id[0] = 0; | |
527 | cpu_devs[i]->c_identify(c); | |
528 | if (c->x86_vendor_id[0]) { | |
529 | get_cpu_vendor(c); | |
530 | break; | |
531 | } | |
532 | } | |
533 | #endif | |
534 | } | |
535 | ||
34048c9e PC |
536 | /* |
537 | * Do minimum CPU detection early. | |
538 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
539 | * cache alignment. | |
540 | * The others are not touched to avoid unwanted side effects. | |
541 | * | |
542 | * WARNING: this function is only called on the BP. Don't add code here | |
543 | * that is supposed to run on all CPUs. | |
544 | */ | |
3da99c97 | 545 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 546 | { |
6627d242 YL |
547 | #ifdef CONFIG_X86_64 |
548 | c->x86_clflush_size = 64; | |
549 | #else | |
d4387bd3 | 550 | c->x86_clflush_size = 32; |
6627d242 | 551 | #endif |
0a488a53 | 552 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 553 | |
3da99c97 | 554 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 555 | c->extended_cpuid_level = 0; |
d7cd5611 | 556 | |
aef93c8b YL |
557 | if (!have_cpuid_p()) |
558 | identify_cpu_without_cpuid(c); | |
559 | ||
560 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
561 | if (!have_cpuid_p()) |
562 | return; | |
563 | ||
564 | cpu_detect(c); | |
565 | ||
3da99c97 | 566 | get_cpu_vendor(c); |
2b16a235 | 567 | |
3da99c97 | 568 | get_cpu_cap(c); |
12cf105c | 569 | |
10a434fc YL |
570 | if (this_cpu->c_early_init) |
571 | this_cpu->c_early_init(c); | |
093af8d7 | 572 | |
1c4acdb4 | 573 | #ifdef CONFIG_SMP |
bfcb4c1b | 574 | c->cpu_index = boot_cpu_id; |
1c4acdb4 | 575 | #endif |
d7cd5611 RR |
576 | } |
577 | ||
9d31d35b YL |
578 | void __init early_cpu_init(void) |
579 | { | |
10a434fc YL |
580 | struct cpu_dev **cdev; |
581 | int count = 0; | |
582 | ||
583 | printk("KERNEL supported cpus:\n"); | |
584 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { | |
585 | struct cpu_dev *cpudev = *cdev; | |
586 | unsigned int j; | |
9d31d35b | 587 | |
10a434fc YL |
588 | if (count >= X86_VENDOR_NUM) |
589 | break; | |
590 | cpu_devs[count] = cpudev; | |
591 | count++; | |
592 | ||
593 | for (j = 0; j < 2; j++) { | |
594 | if (!cpudev->c_ident[j]) | |
595 | continue; | |
596 | printk(" %s %s\n", cpudev->c_vendor, | |
597 | cpudev->c_ident[j]); | |
598 | } | |
599 | } | |
9d31d35b | 600 | |
9d31d35b | 601 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 602 | } |
093af8d7 | 603 | |
b6734c35 PA |
604 | /* |
605 | * The NOPL instruction is supposed to exist on all CPUs with | |
ba0593bf | 606 | * family >= 6; unfortunately, that's not true in practice because |
b6734c35 | 607 | * of early VIA chips and (more importantly) broken virtualizers that |
ba0593bf PA |
608 | * are not easy to detect. In the latter case it doesn't even *fail* |
609 | * reliably, so probing for it doesn't even work. Disable it completely | |
610 | * unless we can find a reliable way to detect all the broken cases. | |
b6734c35 PA |
611 | */ |
612 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
613 | { | |
b6734c35 | 614 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
d7cd5611 RR |
615 | } |
616 | ||
34048c9e | 617 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 618 | { |
aef93c8b | 619 | c->extended_cpuid_level = 0; |
1da177e4 | 620 | |
3da99c97 | 621 | if (!have_cpuid_p()) |
aef93c8b | 622 | identify_cpu_without_cpuid(c); |
1d67953f | 623 | |
aef93c8b | 624 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 625 | if (!have_cpuid_p()) |
aef93c8b | 626 | return; |
1da177e4 | 627 | |
3da99c97 | 628 | cpu_detect(c); |
1da177e4 | 629 | |
3da99c97 | 630 | get_cpu_vendor(c); |
1da177e4 | 631 | |
3da99c97 | 632 | get_cpu_cap(c); |
1da177e4 | 633 | |
3da99c97 YL |
634 | if (c->cpuid_level >= 0x00000001) { |
635 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
636 | #ifdef CONFIG_X86_32 |
637 | # ifdef CONFIG_X86_HT | |
3da99c97 | 638 | c->apicid = phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 639 | # else |
3da99c97 | 640 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
641 | # endif |
642 | #endif | |
1da177e4 | 643 | |
b89d3b3e YL |
644 | #ifdef CONFIG_X86_HT |
645 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 646 | #endif |
3da99c97 | 647 | } |
1da177e4 | 648 | |
1b05d60d | 649 | get_model_name(c); /* Default name */ |
1da177e4 | 650 | |
3da99c97 YL |
651 | init_scattered_cpuid_features(c); |
652 | detect_nopl(c); | |
1da177e4 | 653 | } |
1da177e4 LT |
654 | |
655 | /* | |
656 | * This does the hard work of actually picking apart the CPU stuff... | |
657 | */ | |
9a250347 | 658 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
659 | { |
660 | int i; | |
661 | ||
662 | c->loops_per_jiffy = loops_per_jiffy; | |
663 | c->x86_cache_size = -1; | |
664 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
665 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
666 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
667 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 668 | c->x86_max_cores = 1; |
102bbe3a | 669 | c->x86_coreid_bits = 0; |
11fdd252 | 670 | #ifdef CONFIG_X86_64 |
102bbe3a YL |
671 | c->x86_clflush_size = 64; |
672 | #else | |
673 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 674 | c->x86_clflush_size = 32; |
102bbe3a YL |
675 | #endif |
676 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
677 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
678 | ||
1da177e4 LT |
679 | generic_identify(c); |
680 | ||
3898534d | 681 | if (this_cpu->c_identify) |
1da177e4 LT |
682 | this_cpu->c_identify(c); |
683 | ||
102bbe3a YL |
684 | #ifdef CONFIG_X86_64 |
685 | c->apicid = phys_pkg_id(0); | |
686 | #endif | |
687 | ||
1da177e4 LT |
688 | /* |
689 | * Vendor-specific initialization. In this section we | |
690 | * canonicalize the feature flags, meaning if there are | |
691 | * features a certain CPU supports which CPUID doesn't | |
692 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
693 | * we handle them here. | |
694 | * | |
695 | * At the end of this section, c->x86_capability better | |
696 | * indicate the features this CPU genuinely supports! | |
697 | */ | |
698 | if (this_cpu->c_init) | |
699 | this_cpu->c_init(c); | |
700 | ||
701 | /* Disable the PN if appropriate */ | |
702 | squash_the_stupid_serial_number(c); | |
703 | ||
704 | /* | |
705 | * The vendor-specific functions might have changed features. Now | |
706 | * we do "generic changes." | |
707 | */ | |
708 | ||
1da177e4 | 709 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 710 | if (!c->x86_model_id[0]) { |
1da177e4 LT |
711 | char *p; |
712 | p = table_lookup_model(c); | |
34048c9e | 713 | if (p) |
1da177e4 LT |
714 | strcpy(c->x86_model_id, p); |
715 | else | |
716 | /* Last resort... */ | |
717 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 718 | c->x86, c->x86_model); |
1da177e4 LT |
719 | } |
720 | ||
102bbe3a YL |
721 | #ifdef CONFIG_X86_64 |
722 | detect_ht(c); | |
723 | #endif | |
724 | ||
88b094fb | 725 | init_hypervisor(c); |
1da177e4 LT |
726 | /* |
727 | * On SMP, boot_cpu_data holds the common feature set between | |
728 | * all CPUs; so make sure that we indicate which features are | |
729 | * common between the CPUs. The first time this routine gets | |
730 | * executed, c == &boot_cpu_data. | |
731 | */ | |
34048c9e | 732 | if (c != &boot_cpu_data) { |
1da177e4 | 733 | /* AND the already accumulated flags with these */ |
9d31d35b | 734 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
735 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
736 | } | |
737 | ||
7d851c8d AK |
738 | /* Clear all flags overriden by options */ |
739 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 740 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 741 | |
102bbe3a | 742 | #ifdef CONFIG_X86_MCE |
1da177e4 | 743 | /* Init Machine Check Exception if available. */ |
1da177e4 | 744 | mcheck_init(c); |
102bbe3a | 745 | #endif |
30d432df AK |
746 | |
747 | select_idle_routine(c); | |
102bbe3a YL |
748 | |
749 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
750 | numa_add_cpu(smp_processor_id()); | |
751 | #endif | |
a6c4e076 | 752 | } |
31ab269a | 753 | |
e04d645f GC |
754 | #ifdef CONFIG_X86_64 |
755 | static void vgetcpu_set_mode(void) | |
756 | { | |
757 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
758 | vgetcpu_mode = VGETCPU_RDTSCP; | |
759 | else | |
760 | vgetcpu_mode = VGETCPU_LSL; | |
761 | } | |
762 | #endif | |
763 | ||
a6c4e076 JF |
764 | void __init identify_boot_cpu(void) |
765 | { | |
766 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 767 | #ifdef CONFIG_X86_32 |
a6c4e076 | 768 | sysenter_setup(); |
6fe940d6 | 769 | enable_sep_cpu(); |
e04d645f GC |
770 | #else |
771 | vgetcpu_set_mode(); | |
102bbe3a | 772 | #endif |
a6c4e076 | 773 | } |
3b520b23 | 774 | |
a6c4e076 JF |
775 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
776 | { | |
777 | BUG_ON(c == &boot_cpu_data); | |
778 | identify_cpu(c); | |
102bbe3a | 779 | #ifdef CONFIG_X86_32 |
a6c4e076 | 780 | enable_sep_cpu(); |
102bbe3a | 781 | #endif |
a6c4e076 | 782 | mtrr_ap_init(); |
1da177e4 LT |
783 | } |
784 | ||
a0854a46 YL |
785 | struct msr_range { |
786 | unsigned min; | |
787 | unsigned max; | |
788 | }; | |
1da177e4 | 789 | |
a0854a46 YL |
790 | static struct msr_range msr_range_array[] __cpuinitdata = { |
791 | { 0x00000000, 0x00000418}, | |
792 | { 0xc0000000, 0xc000040b}, | |
793 | { 0xc0010000, 0xc0010142}, | |
794 | { 0xc0011000, 0xc001103b}, | |
795 | }; | |
1da177e4 | 796 | |
a0854a46 YL |
797 | static void __cpuinit print_cpu_msr(void) |
798 | { | |
799 | unsigned index; | |
800 | u64 val; | |
801 | int i; | |
802 | unsigned index_min, index_max; | |
803 | ||
804 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
805 | index_min = msr_range_array[i].min; | |
806 | index_max = msr_range_array[i].max; | |
807 | for (index = index_min; index < index_max; index++) { | |
808 | if (rdmsrl_amd_safe(index, &val)) | |
809 | continue; | |
810 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 811 | } |
a0854a46 YL |
812 | } |
813 | } | |
94605eff | 814 | |
a0854a46 YL |
815 | static int show_msr __cpuinitdata; |
816 | static __init int setup_show_msr(char *arg) | |
817 | { | |
818 | int num; | |
3dd9d514 | 819 | |
a0854a46 | 820 | get_option(&arg, &num); |
3dd9d514 | 821 | |
a0854a46 YL |
822 | if (num > 0) |
823 | show_msr = num; | |
824 | return 1; | |
1da177e4 | 825 | } |
a0854a46 | 826 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 827 | |
191679fd AK |
828 | static __init int setup_noclflush(char *arg) |
829 | { | |
830 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
831 | return 1; | |
832 | } | |
833 | __setup("noclflush", setup_noclflush); | |
834 | ||
3bc9b76b | 835 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
836 | { |
837 | char *vendor = NULL; | |
838 | ||
839 | if (c->x86_vendor < X86_VENDOR_NUM) | |
840 | vendor = this_cpu->c_vendor; | |
841 | else if (c->cpuid_level >= 0) | |
842 | vendor = c->x86_vendor_id; | |
843 | ||
bd32a8cf | 844 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 845 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 846 | |
9d31d35b YL |
847 | if (c->x86_model_id[0]) |
848 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 849 | else |
9d31d35b | 850 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 851 | |
34048c9e | 852 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 853 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 854 | else |
9d31d35b | 855 | printk(KERN_CONT "\n"); |
a0854a46 YL |
856 | |
857 | #ifdef CONFIG_SMP | |
858 | if (c->cpu_index < show_msr) | |
859 | print_cpu_msr(); | |
860 | #else | |
861 | if (show_msr) | |
862 | print_cpu_msr(); | |
863 | #endif | |
1da177e4 LT |
864 | } |
865 | ||
ac72e788 AK |
866 | static __init int setup_disablecpuid(char *arg) |
867 | { | |
868 | int bit; | |
869 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
870 | setup_clear_cpu_cap(bit); | |
871 | else | |
872 | return 0; | |
873 | return 1; | |
874 | } | |
875 | __setup("clearcpuid=", setup_disablecpuid); | |
876 | ||
d5494d4f YL |
877 | #ifdef CONFIG_X86_64 |
878 | struct x8664_pda **_cpu_pda __read_mostly; | |
879 | EXPORT_SYMBOL(_cpu_pda); | |
880 | ||
881 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; | |
882 | ||
34945ede | 883 | static char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss; |
d5494d4f | 884 | |
2d9cd6c2 | 885 | void __cpuinit pda_init(int cpu) |
d5494d4f YL |
886 | { |
887 | struct x8664_pda *pda = cpu_pda(cpu); | |
888 | ||
889 | /* Setup up data that may be needed in __get_free_pages early */ | |
890 | loadsegment(fs, 0); | |
891 | loadsegment(gs, 0); | |
892 | /* Memory clobbers used to order PDA accessed */ | |
893 | mb(); | |
894 | wrmsrl(MSR_GS_BASE, pda); | |
895 | mb(); | |
896 | ||
897 | pda->cpunumber = cpu; | |
898 | pda->irqcount = -1; | |
899 | pda->kernelstack = (unsigned long)stack_thread_info() - | |
900 | PDA_STACKOFFSET + THREAD_SIZE; | |
901 | pda->active_mm = &init_mm; | |
902 | pda->mmu_state = 0; | |
903 | ||
904 | if (cpu == 0) { | |
905 | /* others are initialized in smpboot.c */ | |
906 | pda->pcurrent = &init_task; | |
907 | pda->irqstackptr = boot_cpu_stack; | |
908 | pda->irqstackptr += IRQSTACKSIZE - 64; | |
909 | } else { | |
910 | if (!pda->irqstackptr) { | |
911 | pda->irqstackptr = (char *) | |
912 | __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER); | |
913 | if (!pda->irqstackptr) | |
914 | panic("cannot allocate irqstack for cpu %d", | |
915 | cpu); | |
916 | pda->irqstackptr += IRQSTACKSIZE - 64; | |
917 | } | |
918 | ||
919 | if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE) | |
920 | pda->nodenumber = cpu_to_node(cpu); | |
921 | } | |
922 | } | |
923 | ||
34945ede JS |
924 | static char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + |
925 | DEBUG_STKSZ] __page_aligned_bss; | |
d5494d4f YL |
926 | |
927 | extern asmlinkage void ignore_sysret(void); | |
928 | ||
929 | /* May not be marked __init: used by software suspend */ | |
930 | void syscall_init(void) | |
1da177e4 | 931 | { |
d5494d4f YL |
932 | /* |
933 | * LSTAR and STAR live in a bit strange symbiosis. | |
934 | * They both write to the same internal register. STAR allows to | |
935 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
936 | */ | |
937 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
938 | wrmsrl(MSR_LSTAR, system_call); | |
939 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 940 | |
d5494d4f YL |
941 | #ifdef CONFIG_IA32_EMULATION |
942 | syscall32_cpu_init(); | |
943 | #endif | |
03ae5768 | 944 | |
d5494d4f YL |
945 | /* Flags to clear on syscall */ |
946 | wrmsrl(MSR_SYSCALL_MASK, | |
947 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
1da177e4 | 948 | } |
62111195 | 949 | |
d5494d4f YL |
950 | unsigned long kernel_eflags; |
951 | ||
952 | /* | |
953 | * Copies of the original ist values from the tss are only accessed during | |
954 | * debugging, no special alignment required. | |
955 | */ | |
956 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
957 | ||
958 | #else | |
959 | ||
7c3576d2 | 960 | /* Make sure %fs is initialized properly in idle threads */ |
6b2fb3c6 | 961 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
962 | { |
963 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 964 | regs->fs = __KERNEL_PERCPU; |
f95d47ca JF |
965 | return regs; |
966 | } | |
d5494d4f | 967 | #endif |
c5413fbe | 968 | |
d2cbcc49 RR |
969 | /* |
970 | * cpu_init() initializes state that is per-CPU. Some data is already | |
971 | * initialized (naturally) in the bootstrap process, such as the GDT | |
972 | * and IDT. We reload them nevertheless, this function acts as a | |
973 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 974 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 975 | */ |
1ba76586 YL |
976 | #ifdef CONFIG_X86_64 |
977 | void __cpuinit cpu_init(void) | |
978 | { | |
979 | int cpu = stack_smp_processor_id(); | |
980 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
981 | struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); | |
982 | unsigned long v; | |
983 | char *estacks = NULL; | |
984 | struct task_struct *me; | |
985 | int i; | |
986 | ||
987 | /* CPU 0 is initialised in head64.c */ | |
988 | if (cpu != 0) | |
989 | pda_init(cpu); | |
990 | else | |
991 | estacks = boot_exception_stacks; | |
992 | ||
993 | me = current; | |
994 | ||
c2d1cec1 | 995 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) |
1ba76586 YL |
996 | panic("CPU#%d already initialized!\n", cpu); |
997 | ||
998 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
999 | ||
1000 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1001 | ||
1002 | /* | |
1003 | * Initialize the per-CPU GDT with the boot GDT, | |
1004 | * and set up the GDT descriptor: | |
1005 | */ | |
1006 | ||
1007 | switch_to_new_gdt(); | |
1008 | load_idt((const struct desc_ptr *)&idt_descr); | |
1009 | ||
1010 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1011 | syscall_init(); | |
1012 | ||
1013 | wrmsrl(MSR_FS_BASE, 0); | |
1014 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1015 | barrier(); | |
1016 | ||
1017 | check_efer(); | |
1018 | if (cpu != 0 && x2apic) | |
1019 | enable_x2apic(); | |
1020 | ||
1021 | /* | |
1022 | * set up and load the per-CPU TSS | |
1023 | */ | |
1024 | if (!orig_ist->ist[0]) { | |
1025 | static const unsigned int order[N_EXCEPTION_STACKS] = { | |
1026 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER, | |
1027 | [DEBUG_STACK - 1] = DEBUG_STACK_ORDER | |
1028 | }; | |
1029 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { | |
1030 | if (cpu) { | |
1031 | estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]); | |
1032 | if (!estacks) | |
1033 | panic("Cannot allocate exception " | |
1034 | "stack %ld %d\n", v, cpu); | |
1035 | } | |
1036 | estacks += PAGE_SIZE << order[v]; | |
1037 | orig_ist->ist[v] = t->x86_tss.ist[v] = | |
1038 | (unsigned long)estacks; | |
1039 | } | |
1040 | } | |
1041 | ||
1042 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
1043 | /* | |
1044 | * <= is required because the CPU will access up to | |
1045 | * 8 bits beyond the end of the IO permission bitmap. | |
1046 | */ | |
1047 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1048 | t->io_bitmap[i] = ~0UL; | |
1049 | ||
1050 | atomic_inc(&init_mm.mm_count); | |
1051 | me->active_mm = &init_mm; | |
1052 | if (me->mm) | |
1053 | BUG(); | |
1054 | enter_lazy_tlb(&init_mm, me); | |
1055 | ||
1056 | load_sp0(t, ¤t->thread); | |
1057 | set_tss_desc(cpu, t); | |
1058 | load_TR_desc(); | |
1059 | load_LDT(&init_mm.context); | |
1060 | ||
1061 | #ifdef CONFIG_KGDB | |
1062 | /* | |
1063 | * If the kgdb is connected no debug regs should be altered. This | |
1064 | * is only applicable when KGDB and a KGDB I/O module are built | |
1065 | * into the kernel and you are using early debugging with | |
1066 | * kgdbwait. KGDB will control the kernel HW breakpoint registers. | |
1067 | */ | |
1068 | if (kgdb_connected && arch_kgdb_ops.correct_hw_break) | |
1069 | arch_kgdb_ops.correct_hw_break(); | |
1070 | else { | |
1071 | #endif | |
1072 | /* | |
1073 | * Clear all 6 debug registers: | |
1074 | */ | |
1075 | ||
1076 | set_debugreg(0UL, 0); | |
1077 | set_debugreg(0UL, 1); | |
1078 | set_debugreg(0UL, 2); | |
1079 | set_debugreg(0UL, 3); | |
1080 | set_debugreg(0UL, 6); | |
1081 | set_debugreg(0UL, 7); | |
1082 | #ifdef CONFIG_KGDB | |
1083 | /* If the kgdb is connected no debug regs should be altered. */ | |
1084 | } | |
1085 | #endif | |
1086 | ||
1087 | fpu_init(); | |
1088 | ||
1089 | raw_local_save_flags(kernel_eflags); | |
1090 | ||
1091 | if (is_uv_system()) | |
1092 | uv_cpu_init(); | |
1093 | } | |
1094 | ||
1095 | #else | |
1096 | ||
d2cbcc49 | 1097 | void __cpuinit cpu_init(void) |
9ee79a3d | 1098 | { |
d2cbcc49 RR |
1099 | int cpu = smp_processor_id(); |
1100 | struct task_struct *curr = current; | |
34048c9e | 1101 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1102 | struct thread_struct *thread = &curr->thread; |
62111195 | 1103 | |
c2d1cec1 | 1104 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { |
62111195 JF |
1105 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); |
1106 | for (;;) local_irq_enable(); | |
1107 | } | |
1108 | ||
1109 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1110 | ||
1111 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1112 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1113 | |
4d37e7e3 | 1114 | load_idt(&idt_descr); |
c5413fbe | 1115 | switch_to_new_gdt(); |
1da177e4 | 1116 | |
1da177e4 LT |
1117 | /* |
1118 | * Set up and load the per-CPU TSS and LDT | |
1119 | */ | |
1120 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
1121 | curr->active_mm = &init_mm; |
1122 | if (curr->mm) | |
1123 | BUG(); | |
1124 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 | 1125 | |
faca6227 | 1126 | load_sp0(t, thread); |
34048c9e | 1127 | set_tss_desc(cpu, t); |
1da177e4 LT |
1128 | load_TR_desc(); |
1129 | load_LDT(&init_mm.context); | |
1130 | ||
22c4e308 | 1131 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1132 | /* Set up doublefault TSS pointer in the GDT */ |
1133 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1134 | #endif |
1da177e4 | 1135 | |
464d1a78 JF |
1136 | /* Clear %gs. */ |
1137 | asm volatile ("mov %0, %%gs" : : "r" (0)); | |
1da177e4 LT |
1138 | |
1139 | /* Clear all 6 debug registers: */ | |
4bb0d3ec ZA |
1140 | set_debugreg(0, 0); |
1141 | set_debugreg(0, 1); | |
1142 | set_debugreg(0, 2); | |
1143 | set_debugreg(0, 3); | |
1144 | set_debugreg(0, 6); | |
1145 | set_debugreg(0, 7); | |
1da177e4 LT |
1146 | |
1147 | /* | |
1148 | * Force FPU initialization: | |
1149 | */ | |
b359e8a4 SS |
1150 | if (cpu_has_xsave) |
1151 | current_thread_info()->status = TS_XSAVE; | |
1152 | else | |
1153 | current_thread_info()->status = 0; | |
1da177e4 LT |
1154 | clear_used_math(); |
1155 | mxcsr_feature_mask_init(); | |
dc1e35c6 SS |
1156 | |
1157 | /* | |
1158 | * Boot processor to setup the FP and extended state context info. | |
1159 | */ | |
b3572e36 | 1160 | if (smp_processor_id() == boot_cpu_id) |
dc1e35c6 SS |
1161 | init_thread_xstate(); |
1162 | ||
1163 | xsave_init(); | |
1da177e4 | 1164 | } |
e1367daf | 1165 | |
1ba76586 YL |
1166 | |
1167 | #endif |