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Commit | Line | Data |
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f0fc4aff | 1 | #include <linux/bootmem.h> |
9766cdbc | 2 | #include <linux/linkage.h> |
f0fc4aff | 3 | #include <linux/bitops.h> |
9766cdbc | 4 | #include <linux/kernel.h> |
f0fc4aff | 5 | #include <linux/module.h> |
9766cdbc JSR |
6 | #include <linux/percpu.h> |
7 | #include <linux/string.h> | |
1da177e4 | 8 | #include <linux/delay.h> |
9766cdbc JSR |
9 | #include <linux/sched.h> |
10 | #include <linux/init.h> | |
11 | #include <linux/kgdb.h> | |
1da177e4 | 12 | #include <linux/smp.h> |
9766cdbc JSR |
13 | #include <linux/io.h> |
14 | ||
15 | #include <asm/stackprotector.h> | |
cdd6c482 | 16 | #include <asm/perf_event.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
9766cdbc JSR |
18 | #include <asm/hypervisor.h> |
19 | #include <asm/processor.h> | |
20 | #include <asm/sections.h> | |
8bdbd962 AC |
21 | #include <linux/topology.h> |
22 | #include <linux/cpumask.h> | |
9766cdbc JSR |
23 | #include <asm/pgtable.h> |
24 | #include <asm/atomic.h> | |
25 | #include <asm/proto.h> | |
26 | #include <asm/setup.h> | |
27 | #include <asm/apic.h> | |
28 | #include <asm/desc.h> | |
29 | #include <asm/i387.h> | |
27b07da7 | 30 | #include <asm/mtrr.h> |
8bdbd962 | 31 | #include <linux/numa.h> |
9766cdbc JSR |
32 | #include <asm/asm.h> |
33 | #include <asm/cpu.h> | |
a03a3e28 | 34 | #include <asm/mce.h> |
9766cdbc | 35 | #include <asm/msr.h> |
8d4a4300 | 36 | #include <asm/pat.h> |
e641f5f5 IM |
37 | |
38 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 39 | #include <asm/uv/uv.h> |
1da177e4 LT |
40 | #endif |
41 | ||
42 | #include "cpu.h" | |
43 | ||
c2d1cec1 | 44 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 45 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
46 | cpumask_var_t cpu_callout_mask; |
47 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
48 | |
49 | /* representing cpus for which sibling maps can be computed */ | |
50 | cpumask_var_t cpu_sibling_setup_mask; | |
51 | ||
2f2f52ba | 52 | /* correctly size the local cpu masks */ |
4369f1fb | 53 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
54 | { |
55 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
56 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
57 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
58 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
59 | } | |
60 | ||
e8055139 OZ |
61 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
62 | { | |
63 | #ifdef CONFIG_X86_64 | |
27c13ece | 64 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
65 | #else |
66 | /* Not much we can do here... */ | |
67 | /* Check if at least it has cpuid */ | |
68 | if (c->cpuid_level == -1) { | |
69 | /* No cpuid. It must be an ancient CPU */ | |
70 | if (c->x86 == 4) | |
71 | strcpy(c->x86_model_id, "486"); | |
72 | else if (c->x86 == 3) | |
73 | strcpy(c->x86_model_id, "386"); | |
74 | } | |
75 | #endif | |
76 | } | |
77 | ||
78 | static const struct cpu_dev __cpuinitconst default_cpu = { | |
79 | .c_init = default_init, | |
80 | .c_vendor = "Unknown", | |
81 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
82 | }; | |
83 | ||
84 | static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu; | |
0a488a53 | 85 | |
06deef89 | 86 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 87 | #ifdef CONFIG_X86_64 |
06deef89 BG |
88 | /* |
89 | * We need valid kernel segments for data and code in long mode too | |
90 | * IRET will check the segment types kkeil 2000/10/28 | |
91 | * Also sysret mandates a special GDT layout | |
92 | * | |
9766cdbc | 93 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
94 | * Hopefully nobody expects them at a fixed place (Wine?) |
95 | */ | |
1e5de182 AM |
96 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
97 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
98 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
99 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
100 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
101 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 102 | #else |
1e5de182 AM |
103 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
104 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
105 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
106 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
107 | /* |
108 | * Segments used for calling PnP BIOS have byte granularity. | |
109 | * They code segments and data segments have fixed 64k limits, | |
110 | * the transfer segment sizes are set at run time. | |
111 | */ | |
6842ef0e | 112 | /* 32-bit code */ |
1e5de182 | 113 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 114 | /* 16-bit code */ |
1e5de182 | 115 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 116 | /* 16-bit data */ |
1e5de182 | 117 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 118 | /* 16-bit data */ |
1e5de182 | 119 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 120 | /* 16-bit data */ |
1e5de182 | 121 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
122 | /* |
123 | * The APM segments have byte granularity and their bases | |
124 | * are set at run time. All have 64k limits. | |
125 | */ | |
6842ef0e | 126 | /* 32-bit code */ |
1e5de182 | 127 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 128 | /* 16-bit code */ |
1e5de182 | 129 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 130 | /* data */ |
72c4d853 | 131 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 132 | |
1e5de182 AM |
133 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
134 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 135 | GDT_STACK_CANARY_INIT |
950ad7ff | 136 | #endif |
06deef89 | 137 | } }; |
7a61d35d | 138 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 139 | |
0c752a93 SS |
140 | static int __init x86_xsave_setup(char *s) |
141 | { | |
142 | setup_clear_cpu_cap(X86_FEATURE_XSAVE); | |
6bad06b7 | 143 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); |
0c752a93 SS |
144 | return 1; |
145 | } | |
146 | __setup("noxsave", x86_xsave_setup); | |
147 | ||
6bad06b7 SS |
148 | static int __init x86_xsaveopt_setup(char *s) |
149 | { | |
150 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); | |
151 | return 1; | |
152 | } | |
153 | __setup("noxsaveopt", x86_xsaveopt_setup); | |
154 | ||
ba51dced | 155 | #ifdef CONFIG_X86_32 |
3bc9b76b | 156 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 157 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 158 | |
0a488a53 YL |
159 | static int __init cachesize_setup(char *str) |
160 | { | |
161 | get_option(&str, &cachesize_override); | |
162 | return 1; | |
163 | } | |
164 | __setup("cachesize=", cachesize_setup); | |
165 | ||
0a488a53 YL |
166 | static int __init x86_fxsr_setup(char *s) |
167 | { | |
168 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
169 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
170 | return 1; | |
171 | } | |
172 | __setup("nofxsr", x86_fxsr_setup); | |
173 | ||
174 | static int __init x86_sep_setup(char *s) | |
175 | { | |
176 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
177 | return 1; | |
178 | } | |
179 | __setup("nosep", x86_sep_setup); | |
180 | ||
181 | /* Standard macro to see if a specific flag is changeable */ | |
182 | static inline int flag_is_changeable_p(u32 flag) | |
183 | { | |
184 | u32 f1, f2; | |
185 | ||
94f6bac1 KH |
186 | /* |
187 | * Cyrix and IDT cpus allow disabling of CPUID | |
188 | * so the code below may return different results | |
189 | * when it is executed before and after enabling | |
190 | * the CPUID. Add "volatile" to not allow gcc to | |
191 | * optimize the subsequent calls to this function. | |
192 | */ | |
0f3fa48a IM |
193 | asm volatile ("pushfl \n\t" |
194 | "pushfl \n\t" | |
195 | "popl %0 \n\t" | |
196 | "movl %0, %1 \n\t" | |
197 | "xorl %2, %0 \n\t" | |
198 | "pushl %0 \n\t" | |
199 | "popfl \n\t" | |
200 | "pushfl \n\t" | |
201 | "popl %0 \n\t" | |
202 | "popfl \n\t" | |
203 | ||
94f6bac1 KH |
204 | : "=&r" (f1), "=&r" (f2) |
205 | : "ir" (flag)); | |
0a488a53 YL |
206 | |
207 | return ((f1^f2) & flag) != 0; | |
208 | } | |
209 | ||
210 | /* Probe for the CPUID instruction */ | |
211 | static int __cpuinit have_cpuid_p(void) | |
212 | { | |
213 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
214 | } | |
215 | ||
216 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
217 | { | |
0f3fa48a IM |
218 | unsigned long lo, hi; |
219 | ||
220 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
221 | return; | |
222 | ||
223 | /* Disable processor serial number: */ | |
224 | ||
225 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
226 | lo |= 0x200000; | |
227 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
228 | ||
229 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
230 | clear_cpu_cap(c, X86_FEATURE_PN); | |
231 | ||
232 | /* Disabling the serial number may affect the cpuid level */ | |
233 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
234 | } |
235 | ||
236 | static int __init x86_serial_nr_setup(char *s) | |
237 | { | |
238 | disable_x86_serial_nr = 0; | |
239 | return 1; | |
240 | } | |
241 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 242 | #else |
102bbe3a YL |
243 | static inline int flag_is_changeable_p(u32 flag) |
244 | { | |
245 | return 1; | |
246 | } | |
ba51dced YL |
247 | /* Probe for the CPUID instruction */ |
248 | static inline int have_cpuid_p(void) | |
249 | { | |
250 | return 1; | |
251 | } | |
102bbe3a YL |
252 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
253 | { | |
254 | } | |
ba51dced | 255 | #endif |
0a488a53 | 256 | |
de5397ad FY |
257 | static int disable_smep __initdata; |
258 | static __init int setup_disable_smep(char *arg) | |
259 | { | |
260 | disable_smep = 1; | |
261 | return 1; | |
262 | } | |
263 | __setup("nosmep", setup_disable_smep); | |
264 | ||
265 | static __init void setup_smep(struct cpuinfo_x86 *c) | |
266 | { | |
267 | if (cpu_has(c, X86_FEATURE_SMEP)) { | |
268 | if (unlikely(disable_smep)) { | |
269 | setup_clear_cpu_cap(X86_FEATURE_SMEP); | |
270 | clear_in_cr4(X86_CR4_SMEP); | |
271 | } else | |
272 | set_in_cr4(X86_CR4_SMEP); | |
273 | } | |
274 | } | |
275 | ||
b38b0665 PA |
276 | /* |
277 | * Some CPU features depend on higher CPUID levels, which may not always | |
278 | * be available due to CPUID level capping or broken virtualization | |
279 | * software. Add those features to this table to auto-disable them. | |
280 | */ | |
281 | struct cpuid_dependent_feature { | |
282 | u32 feature; | |
283 | u32 level; | |
284 | }; | |
0f3fa48a | 285 | |
b38b0665 PA |
286 | static const struct cpuid_dependent_feature __cpuinitconst |
287 | cpuid_dependent_features[] = { | |
288 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
289 | { X86_FEATURE_DCA, 0x00000009 }, | |
290 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
291 | { 0, 0 } | |
292 | }; | |
293 | ||
294 | static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) | |
295 | { | |
296 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 297 | |
b38b0665 | 298 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
299 | |
300 | if (!cpu_has(c, df->feature)) | |
301 | continue; | |
b38b0665 PA |
302 | /* |
303 | * Note: cpuid_level is set to -1 if unavailable, but | |
304 | * extended_extended_level is set to 0 if unavailable | |
305 | * and the legitimate extended levels are all negative | |
306 | * when signed; hence the weird messing around with | |
307 | * signs here... | |
308 | */ | |
0f3fa48a | 309 | if (!((s32)df->level < 0 ? |
f6db44df | 310 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
311 | (s32)df->level > (s32)c->cpuid_level)) |
312 | continue; | |
313 | ||
314 | clear_cpu_cap(c, df->feature); | |
315 | if (!warn) | |
316 | continue; | |
317 | ||
318 | printk(KERN_WARNING | |
319 | "CPU: CPU feature %s disabled, no CPUID level 0x%x\n", | |
320 | x86_cap_flags[df->feature], df->level); | |
b38b0665 | 321 | } |
f6db44df | 322 | } |
b38b0665 | 323 | |
102bbe3a YL |
324 | /* |
325 | * Naming convention should be: <Name> [(<Codename>)] | |
326 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
327 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
328 | * isn't used | |
102bbe3a YL |
329 | */ |
330 | ||
331 | /* Look up CPU names by table lookup. */ | |
02dde8b4 | 332 | static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 333 | { |
02dde8b4 | 334 | const struct cpu_model_info *info; |
102bbe3a YL |
335 | |
336 | if (c->x86_model >= 16) | |
337 | return NULL; /* Range check */ | |
338 | ||
339 | if (!this_cpu) | |
340 | return NULL; | |
341 | ||
342 | info = this_cpu->c_models; | |
343 | ||
344 | while (info && info->family) { | |
345 | if (info->family == c->x86) | |
346 | return info->model_names[c->x86_model]; | |
347 | info++; | |
348 | } | |
349 | return NULL; /* Not found */ | |
350 | } | |
351 | ||
3e0c3737 YL |
352 | __u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata; |
353 | __u32 cpu_caps_set[NCAPINTS] __cpuinitdata; | |
7d851c8d | 354 | |
11e3a840 JF |
355 | void load_percpu_segment(int cpu) |
356 | { | |
357 | #ifdef CONFIG_X86_32 | |
358 | loadsegment(fs, __KERNEL_PERCPU); | |
359 | #else | |
360 | loadsegment(gs, 0); | |
361 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
362 | #endif | |
60a5317f | 363 | load_stack_canary_segment(); |
11e3a840 JF |
364 | } |
365 | ||
0f3fa48a IM |
366 | /* |
367 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
368 | * it's on the real one. | |
369 | */ | |
552be871 | 370 | void switch_to_new_gdt(int cpu) |
9d31d35b YL |
371 | { |
372 | struct desc_ptr gdt_descr; | |
373 | ||
2697fbd5 | 374 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
375 | gdt_descr.size = GDT_SIZE - 1; |
376 | load_gdt(&gdt_descr); | |
2697fbd5 | 377 | /* Reload the per-cpu base */ |
11e3a840 JF |
378 | |
379 | load_percpu_segment(cpu); | |
9d31d35b YL |
380 | } |
381 | ||
02dde8b4 | 382 | static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 383 | |
1b05d60d | 384 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
385 | { |
386 | unsigned int *v; | |
387 | char *p, *q; | |
388 | ||
3da99c97 | 389 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 390 | return; |
1da177e4 | 391 | |
0f3fa48a | 392 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
393 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
394 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
395 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
396 | c->x86_model_id[48] = 0; | |
397 | ||
0f3fa48a IM |
398 | /* |
399 | * Intel chips right-justify this string for some dumb reason; | |
400 | * undo that brain damage: | |
401 | */ | |
1da177e4 | 402 | p = q = &c->x86_model_id[0]; |
34048c9e | 403 | while (*p == ' ') |
9766cdbc | 404 | p++; |
34048c9e | 405 | if (p != q) { |
9766cdbc JSR |
406 | while (*p) |
407 | *q++ = *p++; | |
408 | while (q <= &c->x86_model_id[48]) | |
409 | *q++ = '\0'; /* Zero-pad the rest */ | |
1da177e4 | 410 | } |
1da177e4 LT |
411 | } |
412 | ||
27c13ece | 413 | void __cpuinit cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 414 | { |
9d31d35b | 415 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 416 | |
3da99c97 | 417 | n = c->extended_cpuid_level; |
1da177e4 LT |
418 | |
419 | if (n >= 0x80000005) { | |
9d31d35b | 420 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 421 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
422 | #ifdef CONFIG_X86_64 |
423 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
424 | c->x86_tlbsize = 0; | |
425 | #endif | |
1da177e4 LT |
426 | } |
427 | ||
428 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
429 | return; | |
430 | ||
0a488a53 | 431 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 432 | l2size = ecx >> 16; |
34048c9e | 433 | |
140fc727 YL |
434 | #ifdef CONFIG_X86_64 |
435 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
436 | #else | |
1da177e4 LT |
437 | /* do processor-specific cache resizing */ |
438 | if (this_cpu->c_size_cache) | |
34048c9e | 439 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
440 | |
441 | /* Allow user to override all this if necessary. */ | |
442 | if (cachesize_override != -1) | |
443 | l2size = cachesize_override; | |
444 | ||
34048c9e | 445 | if (l2size == 0) |
1da177e4 | 446 | return; /* Again, no L2 cache is possible */ |
140fc727 | 447 | #endif |
1da177e4 LT |
448 | |
449 | c->x86_cache_size = l2size; | |
1da177e4 LT |
450 | } |
451 | ||
9d31d35b | 452 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 453 | { |
97e4db7c | 454 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
455 | u32 eax, ebx, ecx, edx; |
456 | int index_msb, core_bits; | |
2eaad1fd | 457 | static bool printed; |
1da177e4 | 458 | |
0a488a53 | 459 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 460 | return; |
1da177e4 | 461 | |
0a488a53 YL |
462 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
463 | goto out; | |
1da177e4 | 464 | |
1cd78776 YL |
465 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
466 | return; | |
1da177e4 | 467 | |
0a488a53 | 468 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 469 | |
9d31d35b YL |
470 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
471 | ||
472 | if (smp_num_siblings == 1) { | |
2eaad1fd | 473 | printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); |
0f3fa48a IM |
474 | goto out; |
475 | } | |
9d31d35b | 476 | |
0f3fa48a IM |
477 | if (smp_num_siblings <= 1) |
478 | goto out; | |
9d31d35b | 479 | |
0f3fa48a IM |
480 | if (smp_num_siblings > nr_cpu_ids) { |
481 | pr_warning("CPU: Unsupported number of siblings %d", | |
482 | smp_num_siblings); | |
483 | smp_num_siblings = 1; | |
484 | return; | |
485 | } | |
9d31d35b | 486 | |
0f3fa48a IM |
487 | index_msb = get_count_order(smp_num_siblings); |
488 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 489 | |
0f3fa48a | 490 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 491 | |
0f3fa48a | 492 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 493 | |
0f3fa48a | 494 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 495 | |
0f3fa48a IM |
496 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
497 | ((1 << core_bits) - 1); | |
1da177e4 | 498 | |
0a488a53 | 499 | out: |
2eaad1fd | 500 | if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { |
0a488a53 YL |
501 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", |
502 | c->phys_proc_id); | |
503 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
504 | c->cpu_core_id); | |
2eaad1fd | 505 | printed = 1; |
9d31d35b | 506 | } |
9d31d35b | 507 | #endif |
97e4db7c | 508 | } |
1da177e4 | 509 | |
3da99c97 | 510 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
511 | { |
512 | char *v = c->x86_vendor_id; | |
0f3fa48a | 513 | int i; |
1da177e4 LT |
514 | |
515 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
516 | if (!cpu_devs[i]) |
517 | break; | |
518 | ||
519 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
520 | (cpu_devs[i]->c_ident[1] && | |
521 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 522 | |
10a434fc YL |
523 | this_cpu = cpu_devs[i]; |
524 | c->x86_vendor = this_cpu->c_x86_vendor; | |
525 | return; | |
1da177e4 LT |
526 | } |
527 | } | |
10a434fc | 528 | |
a9c56953 MK |
529 | printk_once(KERN_ERR |
530 | "CPU: vendor_id '%s' unknown, using generic init.\n" \ | |
531 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 532 | |
fe38d855 CE |
533 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
534 | this_cpu = &default_cpu; | |
1da177e4 LT |
535 | } |
536 | ||
9d31d35b | 537 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 538 | { |
1da177e4 | 539 | /* Get vendor name */ |
4a148513 HH |
540 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
541 | (unsigned int *)&c->x86_vendor_id[0], | |
542 | (unsigned int *)&c->x86_vendor_id[8], | |
543 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 544 | |
1da177e4 | 545 | c->x86 = 4; |
9d31d35b | 546 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
547 | if (c->cpuid_level >= 0x00000001) { |
548 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 549 | |
1da177e4 | 550 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
9d31d35b YL |
551 | c->x86 = (tfms >> 8) & 0xf; |
552 | c->x86_model = (tfms >> 4) & 0xf; | |
553 | c->x86_mask = tfms & 0xf; | |
0f3fa48a | 554 | |
f5f786d0 | 555 | if (c->x86 == 0xf) |
1da177e4 | 556 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 557 | if (c->x86 >= 0x6) |
9d31d35b | 558 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
0f3fa48a | 559 | |
d4387bd3 | 560 | if (cap0 & (1<<19)) { |
d4387bd3 | 561 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 562 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 563 | } |
1da177e4 | 564 | } |
1da177e4 | 565 | } |
3da99c97 | 566 | |
d900329e | 567 | void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 YL |
568 | { |
569 | u32 tfms, xlvl; | |
3da99c97 | 570 | u32 ebx; |
093af8d7 | 571 | |
3da99c97 YL |
572 | /* Intel-defined flags: level 0x00000001 */ |
573 | if (c->cpuid_level >= 0x00000001) { | |
574 | u32 capability, excap; | |
0f3fa48a | 575 | |
3da99c97 YL |
576 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); |
577 | c->x86_capability[0] = capability; | |
578 | c->x86_capability[4] = excap; | |
579 | } | |
093af8d7 | 580 | |
bdc802dc PA |
581 | /* Additional Intel-defined flags: level 0x00000007 */ |
582 | if (c->cpuid_level >= 0x00000007) { | |
583 | u32 eax, ebx, ecx, edx; | |
584 | ||
585 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); | |
586 | ||
2494b030 | 587 | c->x86_capability[9] = ebx; |
bdc802dc PA |
588 | } |
589 | ||
3da99c97 YL |
590 | /* AMD-defined flags: level 0x80000001 */ |
591 | xlvl = cpuid_eax(0x80000000); | |
592 | c->extended_cpuid_level = xlvl; | |
0f3fa48a | 593 | |
3da99c97 YL |
594 | if ((xlvl & 0xffff0000) == 0x80000000) { |
595 | if (xlvl >= 0x80000001) { | |
596 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
597 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 598 | } |
093af8d7 | 599 | } |
093af8d7 | 600 | |
5122c890 YL |
601 | if (c->extended_cpuid_level >= 0x80000008) { |
602 | u32 eax = cpuid_eax(0x80000008); | |
603 | ||
604 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
605 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 606 | } |
13c6c532 JB |
607 | #ifdef CONFIG_X86_32 |
608 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
609 | c->x86_phys_bits = 36; | |
5122c890 | 610 | #endif |
e3224234 YL |
611 | |
612 | if (c->extended_cpuid_level >= 0x80000007) | |
613 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 | 614 | |
1dedefd1 | 615 | init_scattered_cpuid_features(c); |
093af8d7 | 616 | } |
1da177e4 | 617 | |
aef93c8b YL |
618 | static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
619 | { | |
620 | #ifdef CONFIG_X86_32 | |
621 | int i; | |
622 | ||
623 | /* | |
624 | * First of all, decide if this is a 486 or higher | |
625 | * It's a 486 if we can modify the AC flag | |
626 | */ | |
627 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
628 | c->x86 = 4; | |
629 | else | |
630 | c->x86 = 3; | |
631 | ||
632 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
633 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
634 | c->x86_vendor_id[0] = 0; | |
635 | cpu_devs[i]->c_identify(c); | |
636 | if (c->x86_vendor_id[0]) { | |
637 | get_cpu_vendor(c); | |
638 | break; | |
639 | } | |
640 | } | |
641 | #endif | |
642 | } | |
643 | ||
34048c9e PC |
644 | /* |
645 | * Do minimum CPU detection early. | |
646 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
647 | * cache alignment. | |
648 | * The others are not touched to avoid unwanted side effects. | |
649 | * | |
650 | * WARNING: this function is only called on the BP. Don't add code here | |
651 | * that is supposed to run on all CPUs. | |
652 | */ | |
3da99c97 | 653 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 654 | { |
6627d242 YL |
655 | #ifdef CONFIG_X86_64 |
656 | c->x86_clflush_size = 64; | |
13c6c532 JB |
657 | c->x86_phys_bits = 36; |
658 | c->x86_virt_bits = 48; | |
6627d242 | 659 | #else |
d4387bd3 | 660 | c->x86_clflush_size = 32; |
13c6c532 JB |
661 | c->x86_phys_bits = 32; |
662 | c->x86_virt_bits = 32; | |
6627d242 | 663 | #endif |
0a488a53 | 664 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 665 | |
3da99c97 | 666 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 667 | c->extended_cpuid_level = 0; |
d7cd5611 | 668 | |
aef93c8b YL |
669 | if (!have_cpuid_p()) |
670 | identify_cpu_without_cpuid(c); | |
671 | ||
672 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
673 | if (!have_cpuid_p()) |
674 | return; | |
675 | ||
676 | cpu_detect(c); | |
677 | ||
3da99c97 | 678 | get_cpu_vendor(c); |
2b16a235 | 679 | |
3da99c97 | 680 | get_cpu_cap(c); |
12cf105c | 681 | |
10a434fc YL |
682 | if (this_cpu->c_early_init) |
683 | this_cpu->c_early_init(c); | |
093af8d7 | 684 | |
1c4acdb4 | 685 | #ifdef CONFIG_SMP |
f6e9456c | 686 | c->cpu_index = 0; |
1c4acdb4 | 687 | #endif |
b38b0665 | 688 | filter_cpuid_features(c, false); |
de5397ad FY |
689 | |
690 | setup_smep(c); | |
d7cd5611 RR |
691 | } |
692 | ||
9d31d35b YL |
693 | void __init early_cpu_init(void) |
694 | { | |
02dde8b4 | 695 | const struct cpu_dev *const *cdev; |
10a434fc YL |
696 | int count = 0; |
697 | ||
ac23f253 | 698 | #ifdef CONFIG_PROCESSOR_SELECT |
9766cdbc | 699 | printk(KERN_INFO "KERNEL supported cpus:\n"); |
31c997ca IM |
700 | #endif |
701 | ||
10a434fc | 702 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 703 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 704 | |
10a434fc YL |
705 | if (count >= X86_VENDOR_NUM) |
706 | break; | |
707 | cpu_devs[count] = cpudev; | |
708 | count++; | |
709 | ||
ac23f253 | 710 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
711 | { |
712 | unsigned int j; | |
713 | ||
714 | for (j = 0; j < 2; j++) { | |
715 | if (!cpudev->c_ident[j]) | |
716 | continue; | |
717 | printk(KERN_INFO " %s %s\n", cpudev->c_vendor, | |
718 | cpudev->c_ident[j]); | |
719 | } | |
10a434fc | 720 | } |
0388423d | 721 | #endif |
10a434fc | 722 | } |
9d31d35b | 723 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 724 | } |
093af8d7 | 725 | |
b6734c35 | 726 | /* |
366d4a43 BP |
727 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; |
728 | * unfortunately, that's not true in practice because of early VIA | |
729 | * chips and (more importantly) broken virtualizers that are not easy | |
730 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
731 | * probing for it doesn't even work. Disable it completely on 32-bit | |
ba0593bf | 732 | * unless we can find a reliable way to detect all the broken cases. |
366d4a43 | 733 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). |
b6734c35 PA |
734 | */ |
735 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
736 | { | |
366d4a43 | 737 | #ifdef CONFIG_X86_32 |
b6734c35 | 738 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
366d4a43 BP |
739 | #else |
740 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
741 | #endif | |
d7cd5611 RR |
742 | } |
743 | ||
34048c9e | 744 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 745 | { |
aef93c8b | 746 | c->extended_cpuid_level = 0; |
1da177e4 | 747 | |
3da99c97 | 748 | if (!have_cpuid_p()) |
aef93c8b | 749 | identify_cpu_without_cpuid(c); |
1d67953f | 750 | |
aef93c8b | 751 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 752 | if (!have_cpuid_p()) |
aef93c8b | 753 | return; |
1da177e4 | 754 | |
3da99c97 | 755 | cpu_detect(c); |
1da177e4 | 756 | |
3da99c97 | 757 | get_cpu_vendor(c); |
1da177e4 | 758 | |
3da99c97 | 759 | get_cpu_cap(c); |
1da177e4 | 760 | |
3da99c97 YL |
761 | if (c->cpuid_level >= 0x00000001) { |
762 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
763 | #ifdef CONFIG_X86_32 |
764 | # ifdef CONFIG_X86_HT | |
cb8cc442 | 765 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 766 | # else |
3da99c97 | 767 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
768 | # endif |
769 | #endif | |
1da177e4 | 770 | |
b89d3b3e YL |
771 | #ifdef CONFIG_X86_HT |
772 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 773 | #endif |
3da99c97 | 774 | } |
1da177e4 | 775 | |
de5397ad FY |
776 | setup_smep(c); |
777 | ||
1b05d60d | 778 | get_model_name(c); /* Default name */ |
1da177e4 | 779 | |
3da99c97 | 780 | detect_nopl(c); |
1da177e4 | 781 | } |
1da177e4 LT |
782 | |
783 | /* | |
784 | * This does the hard work of actually picking apart the CPU stuff... | |
785 | */ | |
9a250347 | 786 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
787 | { |
788 | int i; | |
789 | ||
790 | c->loops_per_jiffy = loops_per_jiffy; | |
791 | c->x86_cache_size = -1; | |
792 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
793 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
794 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
795 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 796 | c->x86_max_cores = 1; |
102bbe3a | 797 | c->x86_coreid_bits = 0; |
11fdd252 | 798 | #ifdef CONFIG_X86_64 |
102bbe3a | 799 | c->x86_clflush_size = 64; |
13c6c532 JB |
800 | c->x86_phys_bits = 36; |
801 | c->x86_virt_bits = 48; | |
102bbe3a YL |
802 | #else |
803 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 804 | c->x86_clflush_size = 32; |
13c6c532 JB |
805 | c->x86_phys_bits = 32; |
806 | c->x86_virt_bits = 32; | |
102bbe3a YL |
807 | #endif |
808 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
809 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
810 | ||
1da177e4 LT |
811 | generic_identify(c); |
812 | ||
3898534d | 813 | if (this_cpu->c_identify) |
1da177e4 LT |
814 | this_cpu->c_identify(c); |
815 | ||
2759c328 YL |
816 | /* Clear/Set all flags overriden by options, after probe */ |
817 | for (i = 0; i < NCAPINTS; i++) { | |
818 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
819 | c->x86_capability[i] |= cpu_caps_set[i]; | |
820 | } | |
821 | ||
102bbe3a | 822 | #ifdef CONFIG_X86_64 |
cb8cc442 | 823 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
824 | #endif |
825 | ||
1da177e4 LT |
826 | /* |
827 | * Vendor-specific initialization. In this section we | |
828 | * canonicalize the feature flags, meaning if there are | |
829 | * features a certain CPU supports which CPUID doesn't | |
830 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
831 | * we handle them here. | |
832 | * | |
833 | * At the end of this section, c->x86_capability better | |
834 | * indicate the features this CPU genuinely supports! | |
835 | */ | |
836 | if (this_cpu->c_init) | |
837 | this_cpu->c_init(c); | |
838 | ||
839 | /* Disable the PN if appropriate */ | |
840 | squash_the_stupid_serial_number(c); | |
841 | ||
842 | /* | |
0f3fa48a IM |
843 | * The vendor-specific functions might have changed features. |
844 | * Now we do "generic changes." | |
1da177e4 LT |
845 | */ |
846 | ||
b38b0665 PA |
847 | /* Filter out anything that depends on CPUID levels we don't have */ |
848 | filter_cpuid_features(c, true); | |
849 | ||
1da177e4 | 850 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 851 | if (!c->x86_model_id[0]) { |
02dde8b4 | 852 | const char *p; |
1da177e4 | 853 | p = table_lookup_model(c); |
34048c9e | 854 | if (p) |
1da177e4 LT |
855 | strcpy(c->x86_model_id, p); |
856 | else | |
857 | /* Last resort... */ | |
858 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 859 | c->x86, c->x86_model); |
1da177e4 LT |
860 | } |
861 | ||
102bbe3a YL |
862 | #ifdef CONFIG_X86_64 |
863 | detect_ht(c); | |
864 | #endif | |
865 | ||
88b094fb | 866 | init_hypervisor(c); |
3e0c3737 YL |
867 | |
868 | /* | |
869 | * Clear/Set all flags overriden by options, need do it | |
870 | * before following smp all cpus cap AND. | |
871 | */ | |
872 | for (i = 0; i < NCAPINTS; i++) { | |
873 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
874 | c->x86_capability[i] |= cpu_caps_set[i]; | |
875 | } | |
876 | ||
1da177e4 LT |
877 | /* |
878 | * On SMP, boot_cpu_data holds the common feature set between | |
879 | * all CPUs; so make sure that we indicate which features are | |
880 | * common between the CPUs. The first time this routine gets | |
881 | * executed, c == &boot_cpu_data. | |
882 | */ | |
34048c9e | 883 | if (c != &boot_cpu_data) { |
1da177e4 | 884 | /* AND the already accumulated flags with these */ |
9d31d35b | 885 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
886 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
887 | } | |
888 | ||
889 | /* Init Machine Check Exception if available. */ | |
5e09954a | 890 | mcheck_cpu_init(c); |
30d432df AK |
891 | |
892 | select_idle_routine(c); | |
102bbe3a | 893 | |
de2d9445 | 894 | #ifdef CONFIG_NUMA |
102bbe3a YL |
895 | numa_add_cpu(smp_processor_id()); |
896 | #endif | |
a6c4e076 | 897 | } |
31ab269a | 898 | |
e04d645f GC |
899 | #ifdef CONFIG_X86_64 |
900 | static void vgetcpu_set_mode(void) | |
901 | { | |
902 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
903 | vgetcpu_mode = VGETCPU_RDTSCP; | |
904 | else | |
905 | vgetcpu_mode = VGETCPU_LSL; | |
906 | } | |
907 | #endif | |
908 | ||
a6c4e076 JF |
909 | void __init identify_boot_cpu(void) |
910 | { | |
911 | identify_cpu(&boot_cpu_data); | |
30e1e6d1 | 912 | init_c1e_mask(); |
102bbe3a | 913 | #ifdef CONFIG_X86_32 |
a6c4e076 | 914 | sysenter_setup(); |
6fe940d6 | 915 | enable_sep_cpu(); |
e04d645f GC |
916 | #else |
917 | vgetcpu_set_mode(); | |
102bbe3a | 918 | #endif |
a6c4e076 | 919 | } |
3b520b23 | 920 | |
a6c4e076 JF |
921 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
922 | { | |
923 | BUG_ON(c == &boot_cpu_data); | |
924 | identify_cpu(c); | |
102bbe3a | 925 | #ifdef CONFIG_X86_32 |
a6c4e076 | 926 | enable_sep_cpu(); |
102bbe3a | 927 | #endif |
a6c4e076 | 928 | mtrr_ap_init(); |
1da177e4 LT |
929 | } |
930 | ||
a0854a46 | 931 | struct msr_range { |
0f3fa48a IM |
932 | unsigned min; |
933 | unsigned max; | |
a0854a46 | 934 | }; |
1da177e4 | 935 | |
02dde8b4 | 936 | static const struct msr_range msr_range_array[] __cpuinitconst = { |
a0854a46 YL |
937 | { 0x00000000, 0x00000418}, |
938 | { 0xc0000000, 0xc000040b}, | |
939 | { 0xc0010000, 0xc0010142}, | |
940 | { 0xc0011000, 0xc001103b}, | |
941 | }; | |
1da177e4 | 942 | |
a0854a46 YL |
943 | static void __cpuinit print_cpu_msr(void) |
944 | { | |
0f3fa48a | 945 | unsigned index_min, index_max; |
a0854a46 YL |
946 | unsigned index; |
947 | u64 val; | |
948 | int i; | |
a0854a46 YL |
949 | |
950 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
951 | index_min = msr_range_array[i].min; | |
952 | index_max = msr_range_array[i].max; | |
0f3fa48a | 953 | |
a0854a46 YL |
954 | for (index = index_min; index < index_max; index++) { |
955 | if (rdmsrl_amd_safe(index, &val)) | |
956 | continue; | |
957 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 958 | } |
a0854a46 YL |
959 | } |
960 | } | |
94605eff | 961 | |
a0854a46 | 962 | static int show_msr __cpuinitdata; |
0f3fa48a | 963 | |
a0854a46 YL |
964 | static __init int setup_show_msr(char *arg) |
965 | { | |
966 | int num; | |
3dd9d514 | 967 | |
a0854a46 | 968 | get_option(&arg, &num); |
3dd9d514 | 969 | |
a0854a46 YL |
970 | if (num > 0) |
971 | show_msr = num; | |
972 | return 1; | |
1da177e4 | 973 | } |
a0854a46 | 974 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 975 | |
191679fd AK |
976 | static __init int setup_noclflush(char *arg) |
977 | { | |
978 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
979 | return 1; | |
980 | } | |
981 | __setup("noclflush", setup_noclflush); | |
982 | ||
3bc9b76b | 983 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 984 | { |
02dde8b4 | 985 | const char *vendor = NULL; |
1da177e4 | 986 | |
0f3fa48a | 987 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 988 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
989 | } else { |
990 | if (c->cpuid_level >= 0) | |
991 | vendor = c->x86_vendor_id; | |
992 | } | |
1da177e4 | 993 | |
bd32a8cf | 994 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 995 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 996 | |
9d31d35b YL |
997 | if (c->x86_model_id[0]) |
998 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 999 | else |
9d31d35b | 1000 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 1001 | |
34048c9e | 1002 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 1003 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 1004 | else |
9d31d35b | 1005 | printk(KERN_CONT "\n"); |
a0854a46 YL |
1006 | |
1007 | #ifdef CONFIG_SMP | |
1008 | if (c->cpu_index < show_msr) | |
1009 | print_cpu_msr(); | |
1010 | #else | |
1011 | if (show_msr) | |
1012 | print_cpu_msr(); | |
1013 | #endif | |
1da177e4 LT |
1014 | } |
1015 | ||
ac72e788 AK |
1016 | static __init int setup_disablecpuid(char *arg) |
1017 | { | |
1018 | int bit; | |
0f3fa48a | 1019 | |
ac72e788 AK |
1020 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) |
1021 | setup_clear_cpu_cap(bit); | |
1022 | else | |
1023 | return 0; | |
0f3fa48a | 1024 | |
ac72e788 AK |
1025 | return 1; |
1026 | } | |
1027 | __setup("clearcpuid=", setup_disablecpuid); | |
1028 | ||
d5494d4f | 1029 | #ifdef CONFIG_X86_64 |
9ff80942 | 1030 | struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; |
d5494d4f | 1031 | |
947e76cd BG |
1032 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
1033 | irq_stack_union) __aligned(PAGE_SIZE); | |
0f3fa48a | 1034 | |
bdf977b3 TH |
1035 | /* |
1036 | * The following four percpu variables are hot. Align current_task to | |
1037 | * cacheline size such that all four fall in the same cacheline. | |
1038 | */ | |
1039 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1040 | &init_task; | |
1041 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1042 | |
9af45651 BG |
1043 | DEFINE_PER_CPU(unsigned long, kernel_stack) = |
1044 | (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; | |
1045 | EXPORT_PER_CPU_SYMBOL(kernel_stack); | |
1046 | ||
bdf977b3 TH |
1047 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
1048 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; | |
1049 | ||
56895530 | 1050 | DEFINE_PER_CPU(unsigned int, irq_count) = -1; |
d5494d4f | 1051 | |
0f3fa48a IM |
1052 | /* |
1053 | * Special IST stacks which the CPU switches to when it calls | |
1054 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
1055 | * limit), all of them are 4K, except the debug stack which | |
1056 | * is 8K. | |
1057 | */ | |
1058 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
1059 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1060 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1061 | }; | |
1062 | ||
92d65b23 | 1063 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
3e352aa8 | 1064 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); |
d5494d4f | 1065 | |
d5494d4f YL |
1066 | /* May not be marked __init: used by software suspend */ |
1067 | void syscall_init(void) | |
1da177e4 | 1068 | { |
d5494d4f YL |
1069 | /* |
1070 | * LSTAR and STAR live in a bit strange symbiosis. | |
1071 | * They both write to the same internal register. STAR allows to | |
1072 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
1073 | */ | |
1074 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
1075 | wrmsrl(MSR_LSTAR, system_call); | |
1076 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 1077 | |
d5494d4f YL |
1078 | #ifdef CONFIG_IA32_EMULATION |
1079 | syscall32_cpu_init(); | |
1080 | #endif | |
03ae5768 | 1081 | |
d5494d4f YL |
1082 | /* Flags to clear on syscall */ |
1083 | wrmsrl(MSR_SYSCALL_MASK, | |
1084 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
1da177e4 | 1085 | } |
62111195 | 1086 | |
d5494d4f YL |
1087 | unsigned long kernel_eflags; |
1088 | ||
1089 | /* | |
1090 | * Copies of the original ist values from the tss are only accessed during | |
1091 | * debugging, no special alignment required. | |
1092 | */ | |
1093 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1094 | ||
0f3fa48a | 1095 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1096 | |
bdf977b3 TH |
1097 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1098 | EXPORT_PER_CPU_SYMBOL(current_task); | |
1099 | ||
60a5317f | 1100 | #ifdef CONFIG_CC_STACKPROTECTOR |
53f82452 | 1101 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1102 | #endif |
d5494d4f | 1103 | |
60a5317f | 1104 | /* Make sure %fs and %gs are initialized properly in idle threads */ |
6b2fb3c6 | 1105 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
1106 | { |
1107 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 1108 | regs->fs = __KERNEL_PERCPU; |
60a5317f | 1109 | regs->gs = __KERNEL_STACK_CANARY; |
0f3fa48a | 1110 | |
f95d47ca JF |
1111 | return regs; |
1112 | } | |
0f3fa48a | 1113 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1114 | |
9766cdbc JSR |
1115 | /* |
1116 | * Clear all 6 debug registers: | |
1117 | */ | |
1118 | static void clear_all_debug_regs(void) | |
1119 | { | |
1120 | int i; | |
1121 | ||
1122 | for (i = 0; i < 8; i++) { | |
1123 | /* Ignore db4, db5 */ | |
1124 | if ((i == 4) || (i == 5)) | |
1125 | continue; | |
1126 | ||
1127 | set_debugreg(0, i); | |
1128 | } | |
1129 | } | |
c5413fbe | 1130 | |
0bb9fef9 JW |
1131 | #ifdef CONFIG_KGDB |
1132 | /* | |
1133 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1134 | * connection established. | |
1135 | */ | |
1136 | static void dbg_restore_debug_regs(void) | |
1137 | { | |
1138 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1139 | arch_kgdb_ops.correct_hw_break(); | |
1140 | } | |
1141 | #else /* ! CONFIG_KGDB */ | |
1142 | #define dbg_restore_debug_regs() | |
1143 | #endif /* ! CONFIG_KGDB */ | |
1144 | ||
d2cbcc49 RR |
1145 | /* |
1146 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1147 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1148 | * and IDT. We reload them nevertheless, this function acts as a | |
1149 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1150 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1151 | */ |
1ba76586 | 1152 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1153 | |
1ba76586 YL |
1154 | void __cpuinit cpu_init(void) |
1155 | { | |
0fe1e009 | 1156 | struct orig_ist *oist; |
1ba76586 | 1157 | struct task_struct *me; |
0f3fa48a IM |
1158 | struct tss_struct *t; |
1159 | unsigned long v; | |
1160 | int cpu; | |
1ba76586 YL |
1161 | int i; |
1162 | ||
0f3fa48a IM |
1163 | cpu = stack_smp_processor_id(); |
1164 | t = &per_cpu(init_tss, cpu); | |
0fe1e009 | 1165 | oist = &per_cpu(orig_ist, cpu); |
0f3fa48a | 1166 | |
e7a22c1e | 1167 | #ifdef CONFIG_NUMA |
e534c7c5 LS |
1168 | if (cpu != 0 && percpu_read(numa_node) == 0 && |
1169 | early_cpu_to_node(cpu) != NUMA_NO_NODE) | |
1170 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1171 | #endif |
1ba76586 YL |
1172 | |
1173 | me = current; | |
1174 | ||
c2d1cec1 | 1175 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) |
1ba76586 YL |
1176 | panic("CPU#%d already initialized!\n", cpu); |
1177 | ||
2eaad1fd | 1178 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 YL |
1179 | |
1180 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1181 | ||
1182 | /* | |
1183 | * Initialize the per-CPU GDT with the boot GDT, | |
1184 | * and set up the GDT descriptor: | |
1185 | */ | |
1186 | ||
552be871 | 1187 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1188 | loadsegment(fs, 0); |
1189 | ||
1ba76586 YL |
1190 | load_idt((const struct desc_ptr *)&idt_descr); |
1191 | ||
1192 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1193 | syscall_init(); | |
1194 | ||
1195 | wrmsrl(MSR_FS_BASE, 0); | |
1196 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1197 | barrier(); | |
1198 | ||
4763ed4d | 1199 | x86_configure_nx(); |
06cd9a7d | 1200 | if (cpu != 0) |
1ba76586 YL |
1201 | enable_x2apic(); |
1202 | ||
1203 | /* | |
1204 | * set up and load the per-CPU TSS | |
1205 | */ | |
0fe1e009 | 1206 | if (!oist->ist[0]) { |
92d65b23 | 1207 | char *estacks = per_cpu(exception_stacks, cpu); |
0f3fa48a | 1208 | |
1ba76586 | 1209 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
0f3fa48a | 1210 | estacks += exception_stack_sizes[v]; |
0fe1e009 | 1211 | oist->ist[v] = t->x86_tss.ist[v] = |
1ba76586 YL |
1212 | (unsigned long)estacks; |
1213 | } | |
1214 | } | |
1215 | ||
1216 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
0f3fa48a | 1217 | |
1ba76586 YL |
1218 | /* |
1219 | * <= is required because the CPU will access up to | |
1220 | * 8 bits beyond the end of the IO permission bitmap. | |
1221 | */ | |
1222 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1223 | t->io_bitmap[i] = ~0UL; | |
1224 | ||
1225 | atomic_inc(&init_mm.mm_count); | |
1226 | me->active_mm = &init_mm; | |
8c5dfd25 | 1227 | BUG_ON(me->mm); |
1ba76586 YL |
1228 | enter_lazy_tlb(&init_mm, me); |
1229 | ||
1230 | load_sp0(t, ¤t->thread); | |
1231 | set_tss_desc(cpu, t); | |
1232 | load_TR_desc(); | |
1233 | load_LDT(&init_mm.context); | |
1234 | ||
0bb9fef9 JW |
1235 | clear_all_debug_regs(); |
1236 | dbg_restore_debug_regs(); | |
1ba76586 YL |
1237 | |
1238 | fpu_init(); | |
0e49bf66 | 1239 | xsave_init(); |
1ba76586 YL |
1240 | |
1241 | raw_local_save_flags(kernel_eflags); | |
1242 | ||
1243 | if (is_uv_system()) | |
1244 | uv_cpu_init(); | |
1245 | } | |
1246 | ||
1247 | #else | |
1248 | ||
d2cbcc49 | 1249 | void __cpuinit cpu_init(void) |
9ee79a3d | 1250 | { |
d2cbcc49 RR |
1251 | int cpu = smp_processor_id(); |
1252 | struct task_struct *curr = current; | |
34048c9e | 1253 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1254 | struct thread_struct *thread = &curr->thread; |
62111195 | 1255 | |
c2d1cec1 | 1256 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { |
62111195 | 1257 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); |
9766cdbc JSR |
1258 | for (;;) |
1259 | local_irq_enable(); | |
62111195 JF |
1260 | } |
1261 | ||
1262 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1263 | ||
1264 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1265 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1266 | |
4d37e7e3 | 1267 | load_idt(&idt_descr); |
552be871 | 1268 | switch_to_new_gdt(cpu); |
1da177e4 | 1269 | |
1da177e4 LT |
1270 | /* |
1271 | * Set up and load the per-CPU TSS and LDT | |
1272 | */ | |
1273 | atomic_inc(&init_mm.mm_count); | |
62111195 | 1274 | curr->active_mm = &init_mm; |
8c5dfd25 | 1275 | BUG_ON(curr->mm); |
62111195 | 1276 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1277 | |
faca6227 | 1278 | load_sp0(t, thread); |
34048c9e | 1279 | set_tss_desc(cpu, t); |
1da177e4 LT |
1280 | load_TR_desc(); |
1281 | load_LDT(&init_mm.context); | |
1282 | ||
f9a196b8 TG |
1283 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); |
1284 | ||
22c4e308 | 1285 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1286 | /* Set up doublefault TSS pointer in the GDT */ |
1287 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1288 | #endif |
1da177e4 | 1289 | |
9766cdbc | 1290 | clear_all_debug_regs(); |
0bb9fef9 | 1291 | dbg_restore_debug_regs(); |
1da177e4 | 1292 | |
0e49bf66 | 1293 | fpu_init(); |
dc1e35c6 | 1294 | xsave_init(); |
1da177e4 | 1295 | } |
1ba76586 | 1296 | #endif |