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Commit | Line | Data |
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f0fc4aff | 1 | #include <linux/bootmem.h> |
9766cdbc | 2 | #include <linux/linkage.h> |
f0fc4aff | 3 | #include <linux/bitops.h> |
9766cdbc | 4 | #include <linux/kernel.h> |
f0fc4aff | 5 | #include <linux/module.h> |
9766cdbc JSR |
6 | #include <linux/percpu.h> |
7 | #include <linux/string.h> | |
1da177e4 | 8 | #include <linux/delay.h> |
9766cdbc JSR |
9 | #include <linux/sched.h> |
10 | #include <linux/init.h> | |
0f46efeb | 11 | #include <linux/kprobes.h> |
9766cdbc | 12 | #include <linux/kgdb.h> |
1da177e4 | 13 | #include <linux/smp.h> |
9766cdbc JSR |
14 | #include <linux/io.h> |
15 | ||
16 | #include <asm/stackprotector.h> | |
cdd6c482 | 17 | #include <asm/perf_event.h> |
1da177e4 | 18 | #include <asm/mmu_context.h> |
49d859d7 | 19 | #include <asm/archrandom.h> |
9766cdbc JSR |
20 | #include <asm/hypervisor.h> |
21 | #include <asm/processor.h> | |
f649e938 | 22 | #include <asm/debugreg.h> |
9766cdbc | 23 | #include <asm/sections.h> |
f40c3300 | 24 | #include <asm/vsyscall.h> |
8bdbd962 AC |
25 | #include <linux/topology.h> |
26 | #include <linux/cpumask.h> | |
9766cdbc | 27 | #include <asm/pgtable.h> |
60063497 | 28 | #include <linux/atomic.h> |
9766cdbc JSR |
29 | #include <asm/proto.h> |
30 | #include <asm/setup.h> | |
31 | #include <asm/apic.h> | |
32 | #include <asm/desc.h> | |
33 | #include <asm/i387.h> | |
1361b83a | 34 | #include <asm/fpu-internal.h> |
27b07da7 | 35 | #include <asm/mtrr.h> |
8bdbd962 | 36 | #include <linux/numa.h> |
9766cdbc JSR |
37 | #include <asm/asm.h> |
38 | #include <asm/cpu.h> | |
a03a3e28 | 39 | #include <asm/mce.h> |
9766cdbc | 40 | #include <asm/msr.h> |
8d4a4300 | 41 | #include <asm/pat.h> |
d288e1cf FY |
42 | #include <asm/microcode.h> |
43 | #include <asm/microcode_intel.h> | |
e641f5f5 IM |
44 | |
45 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 46 | #include <asm/uv/uv.h> |
1da177e4 LT |
47 | #endif |
48 | ||
49 | #include "cpu.h" | |
50 | ||
c2d1cec1 | 51 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 52 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
53 | cpumask_var_t cpu_callout_mask; |
54 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
55 | |
56 | /* representing cpus for which sibling maps can be computed */ | |
57 | cpumask_var_t cpu_sibling_setup_mask; | |
58 | ||
2f2f52ba | 59 | /* correctly size the local cpu masks */ |
4369f1fb | 60 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
61 | { |
62 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
63 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
64 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
65 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
66 | } | |
67 | ||
148f9bb8 | 68 | static void default_init(struct cpuinfo_x86 *c) |
e8055139 OZ |
69 | { |
70 | #ifdef CONFIG_X86_64 | |
27c13ece | 71 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
72 | #else |
73 | /* Not much we can do here... */ | |
74 | /* Check if at least it has cpuid */ | |
75 | if (c->cpuid_level == -1) { | |
76 | /* No cpuid. It must be an ancient CPU */ | |
77 | if (c->x86 == 4) | |
78 | strcpy(c->x86_model_id, "486"); | |
79 | else if (c->x86 == 3) | |
80 | strcpy(c->x86_model_id, "386"); | |
81 | } | |
82 | #endif | |
83 | } | |
84 | ||
148f9bb8 | 85 | static const struct cpu_dev default_cpu = { |
e8055139 OZ |
86 | .c_init = default_init, |
87 | .c_vendor = "Unknown", | |
88 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
89 | }; | |
90 | ||
148f9bb8 | 91 | static const struct cpu_dev *this_cpu = &default_cpu; |
0a488a53 | 92 | |
06deef89 | 93 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 94 | #ifdef CONFIG_X86_64 |
06deef89 BG |
95 | /* |
96 | * We need valid kernel segments for data and code in long mode too | |
97 | * IRET will check the segment types kkeil 2000/10/28 | |
98 | * Also sysret mandates a special GDT layout | |
99 | * | |
9766cdbc | 100 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
101 | * Hopefully nobody expects them at a fixed place (Wine?) |
102 | */ | |
1e5de182 AM |
103 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
104 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
105 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
106 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
107 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
108 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 109 | #else |
1e5de182 AM |
110 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
111 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
112 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
113 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
114 | /* |
115 | * Segments used for calling PnP BIOS have byte granularity. | |
116 | * They code segments and data segments have fixed 64k limits, | |
117 | * the transfer segment sizes are set at run time. | |
118 | */ | |
6842ef0e | 119 | /* 32-bit code */ |
1e5de182 | 120 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 121 | /* 16-bit code */ |
1e5de182 | 122 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 123 | /* 16-bit data */ |
1e5de182 | 124 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 125 | /* 16-bit data */ |
1e5de182 | 126 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 127 | /* 16-bit data */ |
1e5de182 | 128 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
129 | /* |
130 | * The APM segments have byte granularity and their bases | |
131 | * are set at run time. All have 64k limits. | |
132 | */ | |
6842ef0e | 133 | /* 32-bit code */ |
1e5de182 | 134 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 135 | /* 16-bit code */ |
1e5de182 | 136 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 137 | /* data */ |
72c4d853 | 138 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 139 | |
1e5de182 AM |
140 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
141 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 142 | GDT_STACK_CANARY_INIT |
950ad7ff | 143 | #endif |
06deef89 | 144 | } }; |
7a61d35d | 145 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 146 | |
0c752a93 SS |
147 | static int __init x86_xsave_setup(char *s) |
148 | { | |
2cd3949f DH |
149 | if (strlen(s)) |
150 | return 0; | |
0c752a93 | 151 | setup_clear_cpu_cap(X86_FEATURE_XSAVE); |
6bad06b7 | 152 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); |
b6f42a4a | 153 | setup_clear_cpu_cap(X86_FEATURE_XSAVES); |
c6fd893d SS |
154 | setup_clear_cpu_cap(X86_FEATURE_AVX); |
155 | setup_clear_cpu_cap(X86_FEATURE_AVX2); | |
0c752a93 SS |
156 | return 1; |
157 | } | |
158 | __setup("noxsave", x86_xsave_setup); | |
159 | ||
6bad06b7 SS |
160 | static int __init x86_xsaveopt_setup(char *s) |
161 | { | |
162 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); | |
163 | return 1; | |
164 | } | |
165 | __setup("noxsaveopt", x86_xsaveopt_setup); | |
166 | ||
b6f42a4a FY |
167 | static int __init x86_xsaves_setup(char *s) |
168 | { | |
169 | setup_clear_cpu_cap(X86_FEATURE_XSAVES); | |
170 | return 1; | |
171 | } | |
172 | __setup("noxsaves", x86_xsaves_setup); | |
173 | ||
ba51dced | 174 | #ifdef CONFIG_X86_32 |
148f9bb8 PG |
175 | static int cachesize_override = -1; |
176 | static int disable_x86_serial_nr = 1; | |
1da177e4 | 177 | |
0a488a53 YL |
178 | static int __init cachesize_setup(char *str) |
179 | { | |
180 | get_option(&str, &cachesize_override); | |
181 | return 1; | |
182 | } | |
183 | __setup("cachesize=", cachesize_setup); | |
184 | ||
0a488a53 YL |
185 | static int __init x86_fxsr_setup(char *s) |
186 | { | |
187 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
188 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
189 | return 1; | |
190 | } | |
191 | __setup("nofxsr", x86_fxsr_setup); | |
192 | ||
193 | static int __init x86_sep_setup(char *s) | |
194 | { | |
195 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
196 | return 1; | |
197 | } | |
198 | __setup("nosep", x86_sep_setup); | |
199 | ||
200 | /* Standard macro to see if a specific flag is changeable */ | |
201 | static inline int flag_is_changeable_p(u32 flag) | |
202 | { | |
203 | u32 f1, f2; | |
204 | ||
94f6bac1 KH |
205 | /* |
206 | * Cyrix and IDT cpus allow disabling of CPUID | |
207 | * so the code below may return different results | |
208 | * when it is executed before and after enabling | |
209 | * the CPUID. Add "volatile" to not allow gcc to | |
210 | * optimize the subsequent calls to this function. | |
211 | */ | |
0f3fa48a IM |
212 | asm volatile ("pushfl \n\t" |
213 | "pushfl \n\t" | |
214 | "popl %0 \n\t" | |
215 | "movl %0, %1 \n\t" | |
216 | "xorl %2, %0 \n\t" | |
217 | "pushl %0 \n\t" | |
218 | "popfl \n\t" | |
219 | "pushfl \n\t" | |
220 | "popl %0 \n\t" | |
221 | "popfl \n\t" | |
222 | ||
94f6bac1 KH |
223 | : "=&r" (f1), "=&r" (f2) |
224 | : "ir" (flag)); | |
0a488a53 YL |
225 | |
226 | return ((f1^f2) & flag) != 0; | |
227 | } | |
228 | ||
229 | /* Probe for the CPUID instruction */ | |
148f9bb8 | 230 | int have_cpuid_p(void) |
0a488a53 YL |
231 | { |
232 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
233 | } | |
234 | ||
148f9bb8 | 235 | static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
0a488a53 | 236 | { |
0f3fa48a IM |
237 | unsigned long lo, hi; |
238 | ||
239 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
240 | return; | |
241 | ||
242 | /* Disable processor serial number: */ | |
243 | ||
244 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
245 | lo |= 0x200000; | |
246 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
247 | ||
248 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
249 | clear_cpu_cap(c, X86_FEATURE_PN); | |
250 | ||
251 | /* Disabling the serial number may affect the cpuid level */ | |
252 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
253 | } |
254 | ||
255 | static int __init x86_serial_nr_setup(char *s) | |
256 | { | |
257 | disable_x86_serial_nr = 0; | |
258 | return 1; | |
259 | } | |
260 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 261 | #else |
102bbe3a YL |
262 | static inline int flag_is_changeable_p(u32 flag) |
263 | { | |
264 | return 1; | |
265 | } | |
102bbe3a YL |
266 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
267 | { | |
268 | } | |
ba51dced | 269 | #endif |
0a488a53 | 270 | |
de5397ad FY |
271 | static __init int setup_disable_smep(char *arg) |
272 | { | |
b2cc2a07 | 273 | setup_clear_cpu_cap(X86_FEATURE_SMEP); |
de5397ad FY |
274 | return 1; |
275 | } | |
276 | __setup("nosmep", setup_disable_smep); | |
277 | ||
b2cc2a07 | 278 | static __always_inline void setup_smep(struct cpuinfo_x86 *c) |
de5397ad | 279 | { |
b2cc2a07 PA |
280 | if (cpu_has(c, X86_FEATURE_SMEP)) |
281 | set_in_cr4(X86_CR4_SMEP); | |
de5397ad FY |
282 | } |
283 | ||
52b6179a PA |
284 | static __init int setup_disable_smap(char *arg) |
285 | { | |
b2cc2a07 | 286 | setup_clear_cpu_cap(X86_FEATURE_SMAP); |
52b6179a PA |
287 | return 1; |
288 | } | |
289 | __setup("nosmap", setup_disable_smap); | |
290 | ||
b2cc2a07 PA |
291 | static __always_inline void setup_smap(struct cpuinfo_x86 *c) |
292 | { | |
293 | unsigned long eflags; | |
294 | ||
295 | /* This should have been cleared long ago */ | |
296 | raw_local_save_flags(eflags); | |
297 | BUG_ON(eflags & X86_EFLAGS_AC); | |
298 | ||
03bbd596 PA |
299 | if (cpu_has(c, X86_FEATURE_SMAP)) { |
300 | #ifdef CONFIG_X86_SMAP | |
b2cc2a07 | 301 | set_in_cr4(X86_CR4_SMAP); |
03bbd596 PA |
302 | #else |
303 | clear_in_cr4(X86_CR4_SMAP); | |
304 | #endif | |
305 | } | |
de5397ad FY |
306 | } |
307 | ||
b38b0665 PA |
308 | /* |
309 | * Some CPU features depend on higher CPUID levels, which may not always | |
310 | * be available due to CPUID level capping or broken virtualization | |
311 | * software. Add those features to this table to auto-disable them. | |
312 | */ | |
313 | struct cpuid_dependent_feature { | |
314 | u32 feature; | |
315 | u32 level; | |
316 | }; | |
0f3fa48a | 317 | |
148f9bb8 | 318 | static const struct cpuid_dependent_feature |
b38b0665 PA |
319 | cpuid_dependent_features[] = { |
320 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
321 | { X86_FEATURE_DCA, 0x00000009 }, | |
322 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
323 | { 0, 0 } | |
324 | }; | |
325 | ||
148f9bb8 | 326 | static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) |
b38b0665 PA |
327 | { |
328 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 329 | |
b38b0665 | 330 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
331 | |
332 | if (!cpu_has(c, df->feature)) | |
333 | continue; | |
b38b0665 PA |
334 | /* |
335 | * Note: cpuid_level is set to -1 if unavailable, but | |
336 | * extended_extended_level is set to 0 if unavailable | |
337 | * and the legitimate extended levels are all negative | |
338 | * when signed; hence the weird messing around with | |
339 | * signs here... | |
340 | */ | |
0f3fa48a | 341 | if (!((s32)df->level < 0 ? |
f6db44df | 342 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
343 | (s32)df->level > (s32)c->cpuid_level)) |
344 | continue; | |
345 | ||
346 | clear_cpu_cap(c, df->feature); | |
347 | if (!warn) | |
348 | continue; | |
349 | ||
350 | printk(KERN_WARNING | |
9def39be JT |
351 | "CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", |
352 | x86_cap_flag(df->feature), df->level); | |
b38b0665 | 353 | } |
f6db44df | 354 | } |
b38b0665 | 355 | |
102bbe3a YL |
356 | /* |
357 | * Naming convention should be: <Name> [(<Codename>)] | |
358 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
359 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
360 | * isn't used | |
102bbe3a YL |
361 | */ |
362 | ||
363 | /* Look up CPU names by table lookup. */ | |
148f9bb8 | 364 | static const char *table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 365 | { |
09dc68d9 JB |
366 | #ifdef CONFIG_X86_32 |
367 | const struct legacy_cpu_model_info *info; | |
102bbe3a YL |
368 | |
369 | if (c->x86_model >= 16) | |
370 | return NULL; /* Range check */ | |
371 | ||
372 | if (!this_cpu) | |
373 | return NULL; | |
374 | ||
09dc68d9 | 375 | info = this_cpu->legacy_models; |
102bbe3a | 376 | |
09dc68d9 | 377 | while (info->family) { |
102bbe3a YL |
378 | if (info->family == c->x86) |
379 | return info->model_names[c->x86_model]; | |
380 | info++; | |
381 | } | |
09dc68d9 | 382 | #endif |
102bbe3a YL |
383 | return NULL; /* Not found */ |
384 | } | |
385 | ||
148f9bb8 PG |
386 | __u32 cpu_caps_cleared[NCAPINTS]; |
387 | __u32 cpu_caps_set[NCAPINTS]; | |
7d851c8d | 388 | |
11e3a840 JF |
389 | void load_percpu_segment(int cpu) |
390 | { | |
391 | #ifdef CONFIG_X86_32 | |
392 | loadsegment(fs, __KERNEL_PERCPU); | |
393 | #else | |
394 | loadsegment(gs, 0); | |
395 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
396 | #endif | |
60a5317f | 397 | load_stack_canary_segment(); |
11e3a840 JF |
398 | } |
399 | ||
0f3fa48a IM |
400 | /* |
401 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
402 | * it's on the real one. | |
403 | */ | |
552be871 | 404 | void switch_to_new_gdt(int cpu) |
9d31d35b YL |
405 | { |
406 | struct desc_ptr gdt_descr; | |
407 | ||
2697fbd5 | 408 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
409 | gdt_descr.size = GDT_SIZE - 1; |
410 | load_gdt(&gdt_descr); | |
2697fbd5 | 411 | /* Reload the per-cpu base */ |
11e3a840 JF |
412 | |
413 | load_percpu_segment(cpu); | |
9d31d35b YL |
414 | } |
415 | ||
148f9bb8 | 416 | static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 417 | |
148f9bb8 | 418 | static void get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
419 | { |
420 | unsigned int *v; | |
421 | char *p, *q; | |
422 | ||
3da99c97 | 423 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 424 | return; |
1da177e4 | 425 | |
0f3fa48a | 426 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
427 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
428 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
429 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
430 | c->x86_model_id[48] = 0; | |
431 | ||
0f3fa48a IM |
432 | /* |
433 | * Intel chips right-justify this string for some dumb reason; | |
434 | * undo that brain damage: | |
435 | */ | |
1da177e4 | 436 | p = q = &c->x86_model_id[0]; |
34048c9e | 437 | while (*p == ' ') |
9766cdbc | 438 | p++; |
34048c9e | 439 | if (p != q) { |
9766cdbc JSR |
440 | while (*p) |
441 | *q++ = *p++; | |
442 | while (q <= &c->x86_model_id[48]) | |
443 | *q++ = '\0'; /* Zero-pad the rest */ | |
1da177e4 | 444 | } |
1da177e4 LT |
445 | } |
446 | ||
148f9bb8 | 447 | void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 448 | { |
9d31d35b | 449 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 450 | |
3da99c97 | 451 | n = c->extended_cpuid_level; |
1da177e4 LT |
452 | |
453 | if (n >= 0x80000005) { | |
9d31d35b | 454 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 455 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
456 | #ifdef CONFIG_X86_64 |
457 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
458 | c->x86_tlbsize = 0; | |
459 | #endif | |
1da177e4 LT |
460 | } |
461 | ||
462 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
463 | return; | |
464 | ||
0a488a53 | 465 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 466 | l2size = ecx >> 16; |
34048c9e | 467 | |
140fc727 YL |
468 | #ifdef CONFIG_X86_64 |
469 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
470 | #else | |
1da177e4 | 471 | /* do processor-specific cache resizing */ |
09dc68d9 JB |
472 | if (this_cpu->legacy_cache_size) |
473 | l2size = this_cpu->legacy_cache_size(c, l2size); | |
1da177e4 LT |
474 | |
475 | /* Allow user to override all this if necessary. */ | |
476 | if (cachesize_override != -1) | |
477 | l2size = cachesize_override; | |
478 | ||
34048c9e | 479 | if (l2size == 0) |
1da177e4 | 480 | return; /* Again, no L2 cache is possible */ |
140fc727 | 481 | #endif |
1da177e4 LT |
482 | |
483 | c->x86_cache_size = l2size; | |
1da177e4 LT |
484 | } |
485 | ||
e0ba94f1 AS |
486 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
487 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
488 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
489 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
490 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
491 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
dd360393 | 492 | u16 __read_mostly tlb_lld_1g[NR_INFO]; |
e0ba94f1 | 493 | |
148f9bb8 | 494 | void cpu_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
495 | { |
496 | if (this_cpu->c_detect_tlb) | |
497 | this_cpu->c_detect_tlb(c); | |
498 | ||
dd360393 | 499 | printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" |
e9f4e0a9 | 500 | "Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", |
e0ba94f1 AS |
501 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
502 | tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES], | |
c4211f42 | 503 | tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES], |
e9f4e0a9 | 504 | tlb_lld_1g[ENTRIES]); |
e0ba94f1 AS |
505 | } |
506 | ||
148f9bb8 | 507 | void detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 508 | { |
97e4db7c | 509 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
510 | u32 eax, ebx, ecx, edx; |
511 | int index_msb, core_bits; | |
2eaad1fd | 512 | static bool printed; |
1da177e4 | 513 | |
0a488a53 | 514 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 515 | return; |
1da177e4 | 516 | |
0a488a53 YL |
517 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
518 | goto out; | |
1da177e4 | 519 | |
1cd78776 YL |
520 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
521 | return; | |
1da177e4 | 522 | |
0a488a53 | 523 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 524 | |
9d31d35b YL |
525 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
526 | ||
527 | if (smp_num_siblings == 1) { | |
2eaad1fd | 528 | printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); |
0f3fa48a IM |
529 | goto out; |
530 | } | |
9d31d35b | 531 | |
0f3fa48a IM |
532 | if (smp_num_siblings <= 1) |
533 | goto out; | |
9d31d35b | 534 | |
0f3fa48a IM |
535 | index_msb = get_count_order(smp_num_siblings); |
536 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 537 | |
0f3fa48a | 538 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 539 | |
0f3fa48a | 540 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 541 | |
0f3fa48a | 542 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 543 | |
0f3fa48a IM |
544 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
545 | ((1 << core_bits) - 1); | |
1da177e4 | 546 | |
0a488a53 | 547 | out: |
2eaad1fd | 548 | if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { |
0a488a53 YL |
549 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", |
550 | c->phys_proc_id); | |
551 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
552 | c->cpu_core_id); | |
2eaad1fd | 553 | printed = 1; |
9d31d35b | 554 | } |
9d31d35b | 555 | #endif |
97e4db7c | 556 | } |
1da177e4 | 557 | |
148f9bb8 | 558 | static void get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
559 | { |
560 | char *v = c->x86_vendor_id; | |
0f3fa48a | 561 | int i; |
1da177e4 LT |
562 | |
563 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
564 | if (!cpu_devs[i]) |
565 | break; | |
566 | ||
567 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
568 | (cpu_devs[i]->c_ident[1] && | |
569 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 570 | |
10a434fc YL |
571 | this_cpu = cpu_devs[i]; |
572 | c->x86_vendor = this_cpu->c_x86_vendor; | |
573 | return; | |
1da177e4 LT |
574 | } |
575 | } | |
10a434fc | 576 | |
a9c56953 MK |
577 | printk_once(KERN_ERR |
578 | "CPU: vendor_id '%s' unknown, using generic init.\n" \ | |
579 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 580 | |
fe38d855 CE |
581 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
582 | this_cpu = &default_cpu; | |
1da177e4 LT |
583 | } |
584 | ||
148f9bb8 | 585 | void cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 586 | { |
1da177e4 | 587 | /* Get vendor name */ |
4a148513 HH |
588 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
589 | (unsigned int *)&c->x86_vendor_id[0], | |
590 | (unsigned int *)&c->x86_vendor_id[8], | |
591 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 592 | |
1da177e4 | 593 | c->x86 = 4; |
9d31d35b | 594 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
595 | if (c->cpuid_level >= 0x00000001) { |
596 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 597 | |
1da177e4 | 598 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
9d31d35b YL |
599 | c->x86 = (tfms >> 8) & 0xf; |
600 | c->x86_model = (tfms >> 4) & 0xf; | |
601 | c->x86_mask = tfms & 0xf; | |
0f3fa48a | 602 | |
f5f786d0 | 603 | if (c->x86 == 0xf) |
1da177e4 | 604 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 605 | if (c->x86 >= 0x6) |
9d31d35b | 606 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
0f3fa48a | 607 | |
d4387bd3 | 608 | if (cap0 & (1<<19)) { |
d4387bd3 | 609 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 610 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 611 | } |
1da177e4 | 612 | } |
1da177e4 | 613 | } |
3da99c97 | 614 | |
148f9bb8 | 615 | void get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 YL |
616 | { |
617 | u32 tfms, xlvl; | |
3da99c97 | 618 | u32 ebx; |
093af8d7 | 619 | |
3da99c97 YL |
620 | /* Intel-defined flags: level 0x00000001 */ |
621 | if (c->cpuid_level >= 0x00000001) { | |
622 | u32 capability, excap; | |
0f3fa48a | 623 | |
3da99c97 YL |
624 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); |
625 | c->x86_capability[0] = capability; | |
626 | c->x86_capability[4] = excap; | |
627 | } | |
093af8d7 | 628 | |
bdc802dc PA |
629 | /* Additional Intel-defined flags: level 0x00000007 */ |
630 | if (c->cpuid_level >= 0x00000007) { | |
631 | u32 eax, ebx, ecx, edx; | |
632 | ||
633 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); | |
634 | ||
2494b030 | 635 | c->x86_capability[9] = ebx; |
bdc802dc PA |
636 | } |
637 | ||
6229ad27 FY |
638 | /* Extended state features: level 0x0000000d */ |
639 | if (c->cpuid_level >= 0x0000000d) { | |
640 | u32 eax, ebx, ecx, edx; | |
641 | ||
642 | cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); | |
643 | ||
644 | c->x86_capability[10] = eax; | |
645 | } | |
646 | ||
3da99c97 YL |
647 | /* AMD-defined flags: level 0x80000001 */ |
648 | xlvl = cpuid_eax(0x80000000); | |
649 | c->extended_cpuid_level = xlvl; | |
0f3fa48a | 650 | |
3da99c97 YL |
651 | if ((xlvl & 0xffff0000) == 0x80000000) { |
652 | if (xlvl >= 0x80000001) { | |
653 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
654 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 655 | } |
093af8d7 | 656 | } |
093af8d7 | 657 | |
5122c890 YL |
658 | if (c->extended_cpuid_level >= 0x80000008) { |
659 | u32 eax = cpuid_eax(0x80000008); | |
660 | ||
661 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
662 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 663 | } |
13c6c532 JB |
664 | #ifdef CONFIG_X86_32 |
665 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
666 | c->x86_phys_bits = 36; | |
5122c890 | 667 | #endif |
e3224234 YL |
668 | |
669 | if (c->extended_cpuid_level >= 0x80000007) | |
670 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 | 671 | |
1dedefd1 | 672 | init_scattered_cpuid_features(c); |
093af8d7 | 673 | } |
1da177e4 | 674 | |
148f9bb8 | 675 | static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
aef93c8b YL |
676 | { |
677 | #ifdef CONFIG_X86_32 | |
678 | int i; | |
679 | ||
680 | /* | |
681 | * First of all, decide if this is a 486 or higher | |
682 | * It's a 486 if we can modify the AC flag | |
683 | */ | |
684 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
685 | c->x86 = 4; | |
686 | else | |
687 | c->x86 = 3; | |
688 | ||
689 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
690 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
691 | c->x86_vendor_id[0] = 0; | |
692 | cpu_devs[i]->c_identify(c); | |
693 | if (c->x86_vendor_id[0]) { | |
694 | get_cpu_vendor(c); | |
695 | break; | |
696 | } | |
697 | } | |
698 | #endif | |
699 | } | |
700 | ||
34048c9e PC |
701 | /* |
702 | * Do minimum CPU detection early. | |
703 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
704 | * cache alignment. | |
705 | * The others are not touched to avoid unwanted side effects. | |
706 | * | |
707 | * WARNING: this function is only called on the BP. Don't add code here | |
708 | * that is supposed to run on all CPUs. | |
709 | */ | |
3da99c97 | 710 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 711 | { |
6627d242 YL |
712 | #ifdef CONFIG_X86_64 |
713 | c->x86_clflush_size = 64; | |
13c6c532 JB |
714 | c->x86_phys_bits = 36; |
715 | c->x86_virt_bits = 48; | |
6627d242 | 716 | #else |
d4387bd3 | 717 | c->x86_clflush_size = 32; |
13c6c532 JB |
718 | c->x86_phys_bits = 32; |
719 | c->x86_virt_bits = 32; | |
6627d242 | 720 | #endif |
0a488a53 | 721 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 722 | |
3da99c97 | 723 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 724 | c->extended_cpuid_level = 0; |
d7cd5611 | 725 | |
aef93c8b YL |
726 | if (!have_cpuid_p()) |
727 | identify_cpu_without_cpuid(c); | |
728 | ||
729 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
730 | if (!have_cpuid_p()) |
731 | return; | |
732 | ||
733 | cpu_detect(c); | |
3da99c97 | 734 | get_cpu_vendor(c); |
3da99c97 | 735 | get_cpu_cap(c); |
60e019eb | 736 | fpu_detect(c); |
12cf105c | 737 | |
10a434fc YL |
738 | if (this_cpu->c_early_init) |
739 | this_cpu->c_early_init(c); | |
093af8d7 | 740 | |
f6e9456c | 741 | c->cpu_index = 0; |
b38b0665 | 742 | filter_cpuid_features(c, false); |
de5397ad | 743 | |
a110b5ec BP |
744 | if (this_cpu->c_bsp_init) |
745 | this_cpu->c_bsp_init(c); | |
c3b83598 BP |
746 | |
747 | setup_force_cpu_cap(X86_FEATURE_ALWAYS); | |
d7cd5611 RR |
748 | } |
749 | ||
9d31d35b YL |
750 | void __init early_cpu_init(void) |
751 | { | |
02dde8b4 | 752 | const struct cpu_dev *const *cdev; |
10a434fc YL |
753 | int count = 0; |
754 | ||
ac23f253 | 755 | #ifdef CONFIG_PROCESSOR_SELECT |
9766cdbc | 756 | printk(KERN_INFO "KERNEL supported cpus:\n"); |
31c997ca IM |
757 | #endif |
758 | ||
10a434fc | 759 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 760 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 761 | |
10a434fc YL |
762 | if (count >= X86_VENDOR_NUM) |
763 | break; | |
764 | cpu_devs[count] = cpudev; | |
765 | count++; | |
766 | ||
ac23f253 | 767 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
768 | { |
769 | unsigned int j; | |
770 | ||
771 | for (j = 0; j < 2; j++) { | |
772 | if (!cpudev->c_ident[j]) | |
773 | continue; | |
774 | printk(KERN_INFO " %s %s\n", cpudev->c_vendor, | |
775 | cpudev->c_ident[j]); | |
776 | } | |
10a434fc | 777 | } |
0388423d | 778 | #endif |
10a434fc | 779 | } |
9d31d35b | 780 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 781 | } |
093af8d7 | 782 | |
b6734c35 | 783 | /* |
366d4a43 BP |
784 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; |
785 | * unfortunately, that's not true in practice because of early VIA | |
786 | * chips and (more importantly) broken virtualizers that are not easy | |
787 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
788 | * probing for it doesn't even work. Disable it completely on 32-bit | |
ba0593bf | 789 | * unless we can find a reliable way to detect all the broken cases. |
366d4a43 | 790 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). |
b6734c35 | 791 | */ |
148f9bb8 | 792 | static void detect_nopl(struct cpuinfo_x86 *c) |
b6734c35 | 793 | { |
366d4a43 | 794 | #ifdef CONFIG_X86_32 |
b6734c35 | 795 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
366d4a43 BP |
796 | #else |
797 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
798 | #endif | |
d7cd5611 RR |
799 | } |
800 | ||
148f9bb8 | 801 | static void generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 802 | { |
aef93c8b | 803 | c->extended_cpuid_level = 0; |
1da177e4 | 804 | |
3da99c97 | 805 | if (!have_cpuid_p()) |
aef93c8b | 806 | identify_cpu_without_cpuid(c); |
1d67953f | 807 | |
aef93c8b | 808 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 809 | if (!have_cpuid_p()) |
aef93c8b | 810 | return; |
1da177e4 | 811 | |
3da99c97 | 812 | cpu_detect(c); |
1da177e4 | 813 | |
3da99c97 | 814 | get_cpu_vendor(c); |
1da177e4 | 815 | |
3da99c97 | 816 | get_cpu_cap(c); |
1da177e4 | 817 | |
3da99c97 YL |
818 | if (c->cpuid_level >= 0x00000001) { |
819 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
820 | #ifdef CONFIG_X86_32 |
821 | # ifdef CONFIG_X86_HT | |
cb8cc442 | 822 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 823 | # else |
3da99c97 | 824 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
825 | # endif |
826 | #endif | |
b89d3b3e | 827 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 828 | } |
1da177e4 | 829 | |
1b05d60d | 830 | get_model_name(c); /* Default name */ |
1da177e4 | 831 | |
3da99c97 | 832 | detect_nopl(c); |
1da177e4 | 833 | } |
1da177e4 LT |
834 | |
835 | /* | |
836 | * This does the hard work of actually picking apart the CPU stuff... | |
837 | */ | |
148f9bb8 | 838 | static void identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
839 | { |
840 | int i; | |
841 | ||
842 | c->loops_per_jiffy = loops_per_jiffy; | |
843 | c->x86_cache_size = -1; | |
844 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
845 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
846 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
847 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 848 | c->x86_max_cores = 1; |
102bbe3a | 849 | c->x86_coreid_bits = 0; |
11fdd252 | 850 | #ifdef CONFIG_X86_64 |
102bbe3a | 851 | c->x86_clflush_size = 64; |
13c6c532 JB |
852 | c->x86_phys_bits = 36; |
853 | c->x86_virt_bits = 48; | |
102bbe3a YL |
854 | #else |
855 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 856 | c->x86_clflush_size = 32; |
13c6c532 JB |
857 | c->x86_phys_bits = 32; |
858 | c->x86_virt_bits = 32; | |
102bbe3a YL |
859 | #endif |
860 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
861 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
862 | ||
1da177e4 LT |
863 | generic_identify(c); |
864 | ||
3898534d | 865 | if (this_cpu->c_identify) |
1da177e4 LT |
866 | this_cpu->c_identify(c); |
867 | ||
2759c328 YL |
868 | /* Clear/Set all flags overriden by options, after probe */ |
869 | for (i = 0; i < NCAPINTS; i++) { | |
870 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
871 | c->x86_capability[i] |= cpu_caps_set[i]; | |
872 | } | |
873 | ||
102bbe3a | 874 | #ifdef CONFIG_X86_64 |
cb8cc442 | 875 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
876 | #endif |
877 | ||
1da177e4 LT |
878 | /* |
879 | * Vendor-specific initialization. In this section we | |
880 | * canonicalize the feature flags, meaning if there are | |
881 | * features a certain CPU supports which CPUID doesn't | |
882 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
883 | * we handle them here. | |
884 | * | |
885 | * At the end of this section, c->x86_capability better | |
886 | * indicate the features this CPU genuinely supports! | |
887 | */ | |
888 | if (this_cpu->c_init) | |
889 | this_cpu->c_init(c); | |
890 | ||
891 | /* Disable the PN if appropriate */ | |
892 | squash_the_stupid_serial_number(c); | |
893 | ||
b2cc2a07 PA |
894 | /* Set up SMEP/SMAP */ |
895 | setup_smep(c); | |
896 | setup_smap(c); | |
897 | ||
1da177e4 | 898 | /* |
0f3fa48a IM |
899 | * The vendor-specific functions might have changed features. |
900 | * Now we do "generic changes." | |
1da177e4 LT |
901 | */ |
902 | ||
b38b0665 PA |
903 | /* Filter out anything that depends on CPUID levels we don't have */ |
904 | filter_cpuid_features(c, true); | |
905 | ||
1da177e4 | 906 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 907 | if (!c->x86_model_id[0]) { |
02dde8b4 | 908 | const char *p; |
1da177e4 | 909 | p = table_lookup_model(c); |
34048c9e | 910 | if (p) |
1da177e4 LT |
911 | strcpy(c->x86_model_id, p); |
912 | else | |
913 | /* Last resort... */ | |
914 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 915 | c->x86, c->x86_model); |
1da177e4 LT |
916 | } |
917 | ||
102bbe3a YL |
918 | #ifdef CONFIG_X86_64 |
919 | detect_ht(c); | |
920 | #endif | |
921 | ||
88b094fb | 922 | init_hypervisor(c); |
49d859d7 | 923 | x86_init_rdrand(c); |
3e0c3737 YL |
924 | |
925 | /* | |
926 | * Clear/Set all flags overriden by options, need do it | |
927 | * before following smp all cpus cap AND. | |
928 | */ | |
929 | for (i = 0; i < NCAPINTS; i++) { | |
930 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
931 | c->x86_capability[i] |= cpu_caps_set[i]; | |
932 | } | |
933 | ||
1da177e4 LT |
934 | /* |
935 | * On SMP, boot_cpu_data holds the common feature set between | |
936 | * all CPUs; so make sure that we indicate which features are | |
937 | * common between the CPUs. The first time this routine gets | |
938 | * executed, c == &boot_cpu_data. | |
939 | */ | |
34048c9e | 940 | if (c != &boot_cpu_data) { |
1da177e4 | 941 | /* AND the already accumulated flags with these */ |
9d31d35b | 942 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 | 943 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
65fc985b BP |
944 | |
945 | /* OR, i.e. replicate the bug flags */ | |
946 | for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) | |
947 | c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; | |
1da177e4 LT |
948 | } |
949 | ||
950 | /* Init Machine Check Exception if available. */ | |
5e09954a | 951 | mcheck_cpu_init(c); |
30d432df AK |
952 | |
953 | select_idle_routine(c); | |
102bbe3a | 954 | |
de2d9445 | 955 | #ifdef CONFIG_NUMA |
102bbe3a YL |
956 | numa_add_cpu(smp_processor_id()); |
957 | #endif | |
a6c4e076 | 958 | } |
31ab269a | 959 | |
e04d645f | 960 | #ifdef CONFIG_X86_64 |
e48510f4 | 961 | #ifdef CONFIG_IA32_EMULATION |
cfda7bb9 AL |
962 | /* May not be __init: called during resume */ |
963 | static void syscall32_cpu_init(void) | |
964 | { | |
965 | /* Load these always in case some future AMD CPU supports | |
966 | SYSENTER from compat mode too. */ | |
967 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); | |
968 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); | |
969 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)ia32_sysenter_target); | |
970 | ||
971 | wrmsrl(MSR_CSTAR, ia32_cstar_target); | |
972 | } | |
e48510f4 AM |
973 | #endif /* CONFIG_IA32_EMULATION */ |
974 | #endif /* CONFIG_X86_64 */ | |
cfda7bb9 AL |
975 | |
976 | #ifdef CONFIG_X86_32 | |
977 | void enable_sep_cpu(void) | |
978 | { | |
979 | int cpu = get_cpu(); | |
980 | struct tss_struct *tss = &per_cpu(init_tss, cpu); | |
981 | ||
982 | if (!boot_cpu_has(X86_FEATURE_SEP)) { | |
983 | put_cpu(); | |
984 | return; | |
985 | } | |
986 | ||
987 | tss->x86_tss.ss1 = __KERNEL_CS; | |
988 | tss->x86_tss.sp1 = sizeof(struct tss_struct) + (unsigned long) tss; | |
989 | wrmsr(MSR_IA32_SYSENTER_CS, __KERNEL_CS, 0); | |
990 | wrmsr(MSR_IA32_SYSENTER_ESP, tss->x86_tss.sp1, 0); | |
991 | wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long) ia32_sysenter_target, 0); | |
992 | put_cpu(); | |
993 | } | |
e04d645f GC |
994 | #endif |
995 | ||
a6c4e076 JF |
996 | void __init identify_boot_cpu(void) |
997 | { | |
998 | identify_cpu(&boot_cpu_data); | |
02c68a02 | 999 | init_amd_e400_c1e_mask(); |
102bbe3a | 1000 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1001 | sysenter_setup(); |
6fe940d6 | 1002 | enable_sep_cpu(); |
102bbe3a | 1003 | #endif |
5b556332 | 1004 | cpu_detect_tlb(&boot_cpu_data); |
a6c4e076 | 1005 | } |
3b520b23 | 1006 | |
148f9bb8 | 1007 | void identify_secondary_cpu(struct cpuinfo_x86 *c) |
a6c4e076 JF |
1008 | { |
1009 | BUG_ON(c == &boot_cpu_data); | |
1010 | identify_cpu(c); | |
102bbe3a | 1011 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1012 | enable_sep_cpu(); |
102bbe3a | 1013 | #endif |
a6c4e076 | 1014 | mtrr_ap_init(); |
1da177e4 LT |
1015 | } |
1016 | ||
a0854a46 | 1017 | struct msr_range { |
0f3fa48a IM |
1018 | unsigned min; |
1019 | unsigned max; | |
a0854a46 | 1020 | }; |
1da177e4 | 1021 | |
148f9bb8 | 1022 | static const struct msr_range msr_range_array[] = { |
a0854a46 YL |
1023 | { 0x00000000, 0x00000418}, |
1024 | { 0xc0000000, 0xc000040b}, | |
1025 | { 0xc0010000, 0xc0010142}, | |
1026 | { 0xc0011000, 0xc001103b}, | |
1027 | }; | |
1da177e4 | 1028 | |
148f9bb8 | 1029 | static void __print_cpu_msr(void) |
a0854a46 | 1030 | { |
0f3fa48a | 1031 | unsigned index_min, index_max; |
a0854a46 YL |
1032 | unsigned index; |
1033 | u64 val; | |
1034 | int i; | |
a0854a46 YL |
1035 | |
1036 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
1037 | index_min = msr_range_array[i].min; | |
1038 | index_max = msr_range_array[i].max; | |
0f3fa48a | 1039 | |
a0854a46 | 1040 | for (index = index_min; index < index_max; index++) { |
ecd431d9 | 1041 | if (rdmsrl_safe(index, &val)) |
a0854a46 YL |
1042 | continue; |
1043 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 1044 | } |
a0854a46 YL |
1045 | } |
1046 | } | |
94605eff | 1047 | |
148f9bb8 | 1048 | static int show_msr; |
0f3fa48a | 1049 | |
a0854a46 YL |
1050 | static __init int setup_show_msr(char *arg) |
1051 | { | |
1052 | int num; | |
3dd9d514 | 1053 | |
a0854a46 | 1054 | get_option(&arg, &num); |
3dd9d514 | 1055 | |
a0854a46 YL |
1056 | if (num > 0) |
1057 | show_msr = num; | |
1058 | return 1; | |
1da177e4 | 1059 | } |
a0854a46 | 1060 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 1061 | |
191679fd AK |
1062 | static __init int setup_noclflush(char *arg) |
1063 | { | |
840d2830 | 1064 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); |
da4aaa7d | 1065 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); |
191679fd AK |
1066 | return 1; |
1067 | } | |
1068 | __setup("noclflush", setup_noclflush); | |
1069 | ||
148f9bb8 | 1070 | void print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1071 | { |
02dde8b4 | 1072 | const char *vendor = NULL; |
1da177e4 | 1073 | |
0f3fa48a | 1074 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1075 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1076 | } else { |
1077 | if (c->cpuid_level >= 0) | |
1078 | vendor = c->x86_vendor_id; | |
1079 | } | |
1da177e4 | 1080 | |
bd32a8cf | 1081 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 1082 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 1083 | |
9d31d35b | 1084 | if (c->x86_model_id[0]) |
924e101a | 1085 | printk(KERN_CONT "%s", strim(c->x86_model_id)); |
1da177e4 | 1086 | else |
9d31d35b | 1087 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 1088 | |
924e101a BP |
1089 | printk(KERN_CONT " (fam: %02x, model: %02x", c->x86, c->x86_model); |
1090 | ||
34048c9e | 1091 | if (c->x86_mask || c->cpuid_level >= 0) |
924e101a | 1092 | printk(KERN_CONT ", stepping: %02x)\n", c->x86_mask); |
1da177e4 | 1093 | else |
924e101a | 1094 | printk(KERN_CONT ")\n"); |
a0854a46 | 1095 | |
0b8b8078 | 1096 | print_cpu_msr(c); |
21c3fcf3 YL |
1097 | } |
1098 | ||
148f9bb8 | 1099 | void print_cpu_msr(struct cpuinfo_x86 *c) |
21c3fcf3 | 1100 | { |
a0854a46 | 1101 | if (c->cpu_index < show_msr) |
21c3fcf3 | 1102 | __print_cpu_msr(); |
1da177e4 LT |
1103 | } |
1104 | ||
ac72e788 AK |
1105 | static __init int setup_disablecpuid(char *arg) |
1106 | { | |
1107 | int bit; | |
0f3fa48a | 1108 | |
ac72e788 AK |
1109 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) |
1110 | setup_clear_cpu_cap(bit); | |
1111 | else | |
1112 | return 0; | |
0f3fa48a | 1113 | |
ac72e788 AK |
1114 | return 1; |
1115 | } | |
1116 | __setup("clearcpuid=", setup_disablecpuid); | |
1117 | ||
198d208d SR |
1118 | DEFINE_PER_CPU(unsigned long, kernel_stack) = |
1119 | (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; | |
1120 | EXPORT_PER_CPU_SYMBOL(kernel_stack); | |
1121 | ||
d5494d4f | 1122 | #ifdef CONFIG_X86_64 |
9ff80942 | 1123 | struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; |
629f4f9d SA |
1124 | struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1, |
1125 | (unsigned long) debug_idt_table }; | |
d5494d4f | 1126 | |
947e76cd | 1127 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
277d5b40 | 1128 | irq_stack_union) __aligned(PAGE_SIZE) __visible; |
0f3fa48a | 1129 | |
bdf977b3 TH |
1130 | /* |
1131 | * The following four percpu variables are hot. Align current_task to | |
1132 | * cacheline size such that all four fall in the same cacheline. | |
1133 | */ | |
1134 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1135 | &init_task; | |
1136 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1137 | |
bdf977b3 TH |
1138 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
1139 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; | |
1140 | ||
277d5b40 | 1141 | DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; |
d5494d4f | 1142 | |
c2daa3be PZ |
1143 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1144 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
1145 | ||
7e16838d LT |
1146 | DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); |
1147 | ||
0f3fa48a IM |
1148 | /* |
1149 | * Special IST stacks which the CPU switches to when it calls | |
1150 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
1151 | * limit), all of them are 4K, except the debug stack which | |
1152 | * is 8K. | |
1153 | */ | |
1154 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
1155 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1156 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1157 | }; | |
1158 | ||
92d65b23 | 1159 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
3e352aa8 | 1160 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); |
d5494d4f | 1161 | |
d5494d4f YL |
1162 | /* May not be marked __init: used by software suspend */ |
1163 | void syscall_init(void) | |
1da177e4 | 1164 | { |
d5494d4f YL |
1165 | /* |
1166 | * LSTAR and STAR live in a bit strange symbiosis. | |
1167 | * They both write to the same internal register. STAR allows to | |
1168 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
1169 | */ | |
1170 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
1171 | wrmsrl(MSR_LSTAR, system_call); | |
1172 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 1173 | |
d5494d4f YL |
1174 | #ifdef CONFIG_IA32_EMULATION |
1175 | syscall32_cpu_init(); | |
1176 | #endif | |
03ae5768 | 1177 | |
d5494d4f YL |
1178 | /* Flags to clear on syscall */ |
1179 | wrmsrl(MSR_SYSCALL_MASK, | |
63bcff2a | 1180 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| |
8c7aa698 | 1181 | X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); |
1da177e4 | 1182 | } |
62111195 | 1183 | |
d5494d4f YL |
1184 | /* |
1185 | * Copies of the original ist values from the tss are only accessed during | |
1186 | * debugging, no special alignment required. | |
1187 | */ | |
1188 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1189 | ||
228bdaa9 | 1190 | static DEFINE_PER_CPU(unsigned long, debug_stack_addr); |
42181186 | 1191 | DEFINE_PER_CPU(int, debug_stack_usage); |
228bdaa9 SR |
1192 | |
1193 | int is_debug_stack(unsigned long addr) | |
1194 | { | |
89cbc767 CL |
1195 | return __this_cpu_read(debug_stack_usage) || |
1196 | (addr <= __this_cpu_read(debug_stack_addr) && | |
1197 | addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); | |
228bdaa9 | 1198 | } |
0f46efeb | 1199 | NOKPROBE_SYMBOL(is_debug_stack); |
228bdaa9 | 1200 | |
629f4f9d | 1201 | DEFINE_PER_CPU(u32, debug_idt_ctr); |
f8988175 | 1202 | |
228bdaa9 SR |
1203 | void debug_stack_set_zero(void) |
1204 | { | |
629f4f9d SA |
1205 | this_cpu_inc(debug_idt_ctr); |
1206 | load_current_idt(); | |
228bdaa9 | 1207 | } |
0f46efeb | 1208 | NOKPROBE_SYMBOL(debug_stack_set_zero); |
228bdaa9 SR |
1209 | |
1210 | void debug_stack_reset(void) | |
1211 | { | |
629f4f9d | 1212 | if (WARN_ON(!this_cpu_read(debug_idt_ctr))) |
f8988175 | 1213 | return; |
629f4f9d SA |
1214 | if (this_cpu_dec_return(debug_idt_ctr) == 0) |
1215 | load_current_idt(); | |
228bdaa9 | 1216 | } |
0f46efeb | 1217 | NOKPROBE_SYMBOL(debug_stack_reset); |
228bdaa9 | 1218 | |
0f3fa48a | 1219 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1220 | |
bdf977b3 TH |
1221 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1222 | EXPORT_PER_CPU_SYMBOL(current_task); | |
c2daa3be PZ |
1223 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1224 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
27e74da9 | 1225 | DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); |
bdf977b3 | 1226 | |
60a5317f | 1227 | #ifdef CONFIG_CC_STACKPROTECTOR |
53f82452 | 1228 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1229 | #endif |
d5494d4f | 1230 | |
0f3fa48a | 1231 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1232 | |
9766cdbc JSR |
1233 | /* |
1234 | * Clear all 6 debug registers: | |
1235 | */ | |
1236 | static void clear_all_debug_regs(void) | |
1237 | { | |
1238 | int i; | |
1239 | ||
1240 | for (i = 0; i < 8; i++) { | |
1241 | /* Ignore db4, db5 */ | |
1242 | if ((i == 4) || (i == 5)) | |
1243 | continue; | |
1244 | ||
1245 | set_debugreg(0, i); | |
1246 | } | |
1247 | } | |
c5413fbe | 1248 | |
0bb9fef9 JW |
1249 | #ifdef CONFIG_KGDB |
1250 | /* | |
1251 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1252 | * connection established. | |
1253 | */ | |
1254 | static void dbg_restore_debug_regs(void) | |
1255 | { | |
1256 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1257 | arch_kgdb_ops.correct_hw_break(); | |
1258 | } | |
1259 | #else /* ! CONFIG_KGDB */ | |
1260 | #define dbg_restore_debug_regs() | |
1261 | #endif /* ! CONFIG_KGDB */ | |
1262 | ||
ce4b1b16 IM |
1263 | static void wait_for_master_cpu(int cpu) |
1264 | { | |
1265 | #ifdef CONFIG_SMP | |
1266 | /* | |
1267 | * wait for ACK from master CPU before continuing | |
1268 | * with AP initialization | |
1269 | */ | |
1270 | WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); | |
1271 | while (!cpumask_test_cpu(cpu, cpu_callout_mask)) | |
1272 | cpu_relax(); | |
1273 | #endif | |
1274 | } | |
1275 | ||
d2cbcc49 RR |
1276 | /* |
1277 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1278 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1279 | * and IDT. We reload them nevertheless, this function acts as a | |
1280 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1281 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1282 | */ |
1ba76586 | 1283 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1284 | |
148f9bb8 | 1285 | void cpu_init(void) |
1ba76586 | 1286 | { |
0fe1e009 | 1287 | struct orig_ist *oist; |
1ba76586 | 1288 | struct task_struct *me; |
0f3fa48a IM |
1289 | struct tss_struct *t; |
1290 | unsigned long v; | |
ce4b1b16 | 1291 | int cpu = stack_smp_processor_id(); |
1ba76586 YL |
1292 | int i; |
1293 | ||
ce4b1b16 IM |
1294 | wait_for_master_cpu(cpu); |
1295 | ||
e6ebf5de FY |
1296 | /* |
1297 | * Load microcode on this cpu if a valid microcode is available. | |
1298 | * This is early microcode loading procedure. | |
1299 | */ | |
1300 | load_ucode_ap(); | |
1301 | ||
0f3fa48a | 1302 | t = &per_cpu(init_tss, cpu); |
0fe1e009 | 1303 | oist = &per_cpu(orig_ist, cpu); |
0f3fa48a | 1304 | |
e7a22c1e | 1305 | #ifdef CONFIG_NUMA |
27fd185f | 1306 | if (this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
1307 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
1308 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1309 | #endif |
1ba76586 YL |
1310 | |
1311 | me = current; | |
1312 | ||
2eaad1fd | 1313 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 YL |
1314 | |
1315 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1316 | ||
1317 | /* | |
1318 | * Initialize the per-CPU GDT with the boot GDT, | |
1319 | * and set up the GDT descriptor: | |
1320 | */ | |
1321 | ||
552be871 | 1322 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1323 | loadsegment(fs, 0); |
1324 | ||
cf910e83 | 1325 | load_current_idt(); |
1ba76586 YL |
1326 | |
1327 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1328 | syscall_init(); | |
1329 | ||
1330 | wrmsrl(MSR_FS_BASE, 0); | |
1331 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1332 | barrier(); | |
1333 | ||
4763ed4d | 1334 | x86_configure_nx(); |
27fd185f | 1335 | enable_x2apic(); |
1ba76586 YL |
1336 | |
1337 | /* | |
1338 | * set up and load the per-CPU TSS | |
1339 | */ | |
0fe1e009 | 1340 | if (!oist->ist[0]) { |
92d65b23 | 1341 | char *estacks = per_cpu(exception_stacks, cpu); |
0f3fa48a | 1342 | |
1ba76586 | 1343 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
0f3fa48a | 1344 | estacks += exception_stack_sizes[v]; |
0fe1e009 | 1345 | oist->ist[v] = t->x86_tss.ist[v] = |
1ba76586 | 1346 | (unsigned long)estacks; |
228bdaa9 SR |
1347 | if (v == DEBUG_STACK-1) |
1348 | per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; | |
1ba76586 YL |
1349 | } |
1350 | } | |
1351 | ||
1352 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
0f3fa48a | 1353 | |
1ba76586 YL |
1354 | /* |
1355 | * <= is required because the CPU will access up to | |
1356 | * 8 bits beyond the end of the IO permission bitmap. | |
1357 | */ | |
1358 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1359 | t->io_bitmap[i] = ~0UL; | |
1360 | ||
1361 | atomic_inc(&init_mm.mm_count); | |
1362 | me->active_mm = &init_mm; | |
8c5dfd25 | 1363 | BUG_ON(me->mm); |
1ba76586 YL |
1364 | enter_lazy_tlb(&init_mm, me); |
1365 | ||
1366 | load_sp0(t, ¤t->thread); | |
1367 | set_tss_desc(cpu, t); | |
1368 | load_TR_desc(); | |
1369 | load_LDT(&init_mm.context); | |
1370 | ||
0bb9fef9 JW |
1371 | clear_all_debug_regs(); |
1372 | dbg_restore_debug_regs(); | |
1ba76586 YL |
1373 | |
1374 | fpu_init(); | |
1375 | ||
1ba76586 YL |
1376 | if (is_uv_system()) |
1377 | uv_cpu_init(); | |
1378 | } | |
1379 | ||
1380 | #else | |
1381 | ||
148f9bb8 | 1382 | void cpu_init(void) |
9ee79a3d | 1383 | { |
d2cbcc49 RR |
1384 | int cpu = smp_processor_id(); |
1385 | struct task_struct *curr = current; | |
34048c9e | 1386 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1387 | struct thread_struct *thread = &curr->thread; |
62111195 | 1388 | |
ce4b1b16 | 1389 | wait_for_master_cpu(cpu); |
e6ebf5de | 1390 | |
ce4b1b16 | 1391 | show_ucode_info_early(); |
62111195 JF |
1392 | |
1393 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1394 | ||
9298b815 | 1395 | if (cpu_feature_enabled(X86_FEATURE_VME) || cpu_has_tsc || cpu_has_de) |
62111195 | 1396 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
62111195 | 1397 | |
cf910e83 | 1398 | load_current_idt(); |
552be871 | 1399 | switch_to_new_gdt(cpu); |
1da177e4 | 1400 | |
1da177e4 LT |
1401 | /* |
1402 | * Set up and load the per-CPU TSS and LDT | |
1403 | */ | |
1404 | atomic_inc(&init_mm.mm_count); | |
62111195 | 1405 | curr->active_mm = &init_mm; |
8c5dfd25 | 1406 | BUG_ON(curr->mm); |
62111195 | 1407 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1408 | |
faca6227 | 1409 | load_sp0(t, thread); |
34048c9e | 1410 | set_tss_desc(cpu, t); |
1da177e4 LT |
1411 | load_TR_desc(); |
1412 | load_LDT(&init_mm.context); | |
1413 | ||
f9a196b8 TG |
1414 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); |
1415 | ||
22c4e308 | 1416 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1417 | /* Set up doublefault TSS pointer in the GDT */ |
1418 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1419 | #endif |
1da177e4 | 1420 | |
9766cdbc | 1421 | clear_all_debug_regs(); |
0bb9fef9 | 1422 | dbg_restore_debug_regs(); |
1da177e4 | 1423 | |
0e49bf66 | 1424 | fpu_init(); |
1da177e4 | 1425 | } |
1ba76586 | 1426 | #endif |
5700f743 BP |
1427 | |
1428 | #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS | |
1429 | void warn_pre_alternatives(void) | |
1430 | { | |
1431 | WARN(1, "You're using static_cpu_has before alternatives have run!\n"); | |
1432 | } | |
1433 | EXPORT_SYMBOL_GPL(warn_pre_alternatives); | |
1434 | #endif | |
4a90a99c BP |
1435 | |
1436 | inline bool __static_cpu_has_safe(u16 bit) | |
1437 | { | |
1438 | return boot_cpu_has(bit); | |
1439 | } | |
1440 | EXPORT_SYMBOL_GPL(__static_cpu_has_safe); |