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Commit | Line | Data |
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1da177e4 | 1 | #include <linux/init.h> |
f0fc4aff YL |
2 | #include <linux/kernel.h> |
3 | #include <linux/sched.h> | |
1da177e4 | 4 | #include <linux/string.h> |
f0fc4aff YL |
5 | #include <linux/bootmem.h> |
6 | #include <linux/bitops.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/kgdb.h> | |
9 | #include <linux/topology.h> | |
1da177e4 LT |
10 | #include <linux/delay.h> |
11 | #include <linux/smp.h> | |
1da177e4 | 12 | #include <linux/percpu.h> |
1da177e4 LT |
13 | #include <asm/i387.h> |
14 | #include <asm/msr.h> | |
15 | #include <asm/io.h> | |
f0fc4aff | 16 | #include <asm/linkage.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
27b07da7 | 18 | #include <asm/mtrr.h> |
a03a3e28 | 19 | #include <asm/mce.h> |
8d4a4300 | 20 | #include <asm/pat.h> |
b6734c35 | 21 | #include <asm/asm.h> |
f0fc4aff | 22 | #include <asm/numa.h> |
b342797c | 23 | #include <asm/smp.h> |
f472cdba | 24 | #include <asm/cpu.h> |
06879033 | 25 | #include <asm/cpumask.h> |
1da177e4 LT |
26 | #ifdef CONFIG_X86_LOCAL_APIC |
27 | #include <asm/mpspec.h> | |
28 | #include <asm/apic.h> | |
29 | #include <mach_apic.h> | |
f0fc4aff | 30 | #include <asm/genapic.h> |
bdbcdd48 | 31 | #include <asm/uv/uv.h> |
1da177e4 LT |
32 | #endif |
33 | ||
f0fc4aff YL |
34 | #include <asm/pgtable.h> |
35 | #include <asm/processor.h> | |
36 | #include <asm/desc.h> | |
37 | #include <asm/atomic.h> | |
38 | #include <asm/proto.h> | |
39 | #include <asm/sections.h> | |
40 | #include <asm/setup.h> | |
88b094fb | 41 | #include <asm/hypervisor.h> |
f0fc4aff | 42 | |
1da177e4 LT |
43 | #include "cpu.h" |
44 | ||
c2d1cec1 MT |
45 | #ifdef CONFIG_X86_64 |
46 | ||
47 | /* all of these masks are initialized in setup_cpu_local_masks() */ | |
48 | cpumask_var_t cpu_callin_mask; | |
49 | cpumask_var_t cpu_callout_mask; | |
50 | cpumask_var_t cpu_initialized_mask; | |
51 | ||
52 | /* representing cpus for which sibling maps can be computed */ | |
53 | cpumask_var_t cpu_sibling_setup_mask; | |
54 | ||
2f2f52ba | 55 | /* correctly size the local cpu masks */ |
4369f1fb | 56 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
57 | { |
58 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
59 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
60 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
61 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
62 | } | |
63 | ||
c2d1cec1 MT |
64 | #else /* CONFIG_X86_32 */ |
65 | ||
66 | cpumask_t cpu_callin_map; | |
67 | cpumask_t cpu_callout_map; | |
68 | cpumask_t cpu_initialized; | |
69 | cpumask_t cpu_sibling_setup_map; | |
70 | ||
71 | #endif /* CONFIG_X86_32 */ | |
72 | ||
73 | ||
0a488a53 YL |
74 | static struct cpu_dev *this_cpu __cpuinitdata; |
75 | ||
06deef89 | 76 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 77 | #ifdef CONFIG_X86_64 |
06deef89 BG |
78 | /* |
79 | * We need valid kernel segments for data and code in long mode too | |
80 | * IRET will check the segment types kkeil 2000/10/28 | |
81 | * Also sysret mandates a special GDT layout | |
82 | * | |
83 | * The TLS descriptors are currently at a different place compared to i386. | |
84 | * Hopefully nobody expects them at a fixed place (Wine?) | |
85 | */ | |
950ad7ff YL |
86 | [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, |
87 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, | |
88 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, | |
89 | [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, | |
90 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, | |
91 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, | |
950ad7ff | 92 | #else |
6842ef0e GOC |
93 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
94 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
95 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
96 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
97 | /* |
98 | * Segments used for calling PnP BIOS have byte granularity. | |
99 | * They code segments and data segments have fixed 64k limits, | |
100 | * the transfer segment sizes are set at run time. | |
101 | */ | |
6842ef0e GOC |
102 | /* 32-bit code */ |
103 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
104 | /* 16-bit code */ | |
105 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
106 | /* 16-bit data */ | |
107 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
108 | /* 16-bit data */ | |
109 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
110 | /* 16-bit data */ | |
111 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
bf504672 RR |
112 | /* |
113 | * The APM segments have byte granularity and their bases | |
114 | * are set at run time. All have 64k limits. | |
115 | */ | |
6842ef0e GOC |
116 | /* 32-bit code */ |
117 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
bf504672 | 118 | /* 16-bit code */ |
6842ef0e GOC |
119 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
120 | /* data */ | |
121 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
bf504672 | 122 | |
6842ef0e | 123 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
0dd76d73 | 124 | [GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } }, |
950ad7ff | 125 | #endif |
06deef89 | 126 | } }; |
7a61d35d | 127 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 128 | |
ba51dced | 129 | #ifdef CONFIG_X86_32 |
3bc9b76b | 130 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 131 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 132 | |
0a488a53 YL |
133 | static int __init cachesize_setup(char *str) |
134 | { | |
135 | get_option(&str, &cachesize_override); | |
136 | return 1; | |
137 | } | |
138 | __setup("cachesize=", cachesize_setup); | |
139 | ||
0a488a53 YL |
140 | static int __init x86_fxsr_setup(char *s) |
141 | { | |
142 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
143 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
144 | return 1; | |
145 | } | |
146 | __setup("nofxsr", x86_fxsr_setup); | |
147 | ||
148 | static int __init x86_sep_setup(char *s) | |
149 | { | |
150 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
151 | return 1; | |
152 | } | |
153 | __setup("nosep", x86_sep_setup); | |
154 | ||
155 | /* Standard macro to see if a specific flag is changeable */ | |
156 | static inline int flag_is_changeable_p(u32 flag) | |
157 | { | |
158 | u32 f1, f2; | |
159 | ||
94f6bac1 KH |
160 | /* |
161 | * Cyrix and IDT cpus allow disabling of CPUID | |
162 | * so the code below may return different results | |
163 | * when it is executed before and after enabling | |
164 | * the CPUID. Add "volatile" to not allow gcc to | |
165 | * optimize the subsequent calls to this function. | |
166 | */ | |
167 | asm volatile ("pushfl\n\t" | |
168 | "pushfl\n\t" | |
169 | "popl %0\n\t" | |
170 | "movl %0,%1\n\t" | |
171 | "xorl %2,%0\n\t" | |
172 | "pushl %0\n\t" | |
173 | "popfl\n\t" | |
174 | "pushfl\n\t" | |
175 | "popl %0\n\t" | |
176 | "popfl\n\t" | |
177 | : "=&r" (f1), "=&r" (f2) | |
178 | : "ir" (flag)); | |
0a488a53 YL |
179 | |
180 | return ((f1^f2) & flag) != 0; | |
181 | } | |
182 | ||
183 | /* Probe for the CPUID instruction */ | |
184 | static int __cpuinit have_cpuid_p(void) | |
185 | { | |
186 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
187 | } | |
188 | ||
189 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
190 | { | |
191 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { | |
192 | /* Disable processor serial number */ | |
193 | unsigned long lo, hi; | |
194 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
195 | lo |= 0x200000; | |
196 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
197 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
198 | clear_cpu_cap(c, X86_FEATURE_PN); | |
199 | ||
200 | /* Disabling the serial number may affect the cpuid level */ | |
201 | c->cpuid_level = cpuid_eax(0); | |
202 | } | |
203 | } | |
204 | ||
205 | static int __init x86_serial_nr_setup(char *s) | |
206 | { | |
207 | disable_x86_serial_nr = 0; | |
208 | return 1; | |
209 | } | |
210 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 211 | #else |
102bbe3a YL |
212 | static inline int flag_is_changeable_p(u32 flag) |
213 | { | |
214 | return 1; | |
215 | } | |
ba51dced YL |
216 | /* Probe for the CPUID instruction */ |
217 | static inline int have_cpuid_p(void) | |
218 | { | |
219 | return 1; | |
220 | } | |
102bbe3a YL |
221 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
222 | { | |
223 | } | |
ba51dced | 224 | #endif |
0a488a53 | 225 | |
b38b0665 PA |
226 | /* |
227 | * Some CPU features depend on higher CPUID levels, which may not always | |
228 | * be available due to CPUID level capping or broken virtualization | |
229 | * software. Add those features to this table to auto-disable them. | |
230 | */ | |
231 | struct cpuid_dependent_feature { | |
232 | u32 feature; | |
233 | u32 level; | |
234 | }; | |
235 | static const struct cpuid_dependent_feature __cpuinitconst | |
236 | cpuid_dependent_features[] = { | |
237 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
238 | { X86_FEATURE_DCA, 0x00000009 }, | |
239 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
240 | { 0, 0 } | |
241 | }; | |
242 | ||
243 | static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) | |
244 | { | |
245 | const struct cpuid_dependent_feature *df; | |
246 | for (df = cpuid_dependent_features; df->feature; df++) { | |
247 | /* | |
248 | * Note: cpuid_level is set to -1 if unavailable, but | |
249 | * extended_extended_level is set to 0 if unavailable | |
250 | * and the legitimate extended levels are all negative | |
251 | * when signed; hence the weird messing around with | |
252 | * signs here... | |
253 | */ | |
254 | if (cpu_has(c, df->feature) && | |
255 | ((s32)df->feature < 0 ? | |
256 | (u32)df->feature > (u32)c->extended_cpuid_level : | |
257 | (s32)df->feature > (s32)c->cpuid_level)) { | |
258 | clear_cpu_cap(c, df->feature); | |
259 | if (warn) | |
260 | printk(KERN_WARNING | |
261 | "CPU: CPU feature %s disabled " | |
262 | "due to lack of CPUID level 0x%x\n", | |
263 | x86_cap_flags[df->feature], | |
264 | df->level); | |
265 | } | |
266 | } | |
267 | } | |
268 | ||
102bbe3a YL |
269 | /* |
270 | * Naming convention should be: <Name> [(<Codename>)] | |
271 | * This table only is used unless init_<vendor>() below doesn't set it; | |
272 | * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used | |
273 | * | |
274 | */ | |
275 | ||
276 | /* Look up CPU names by table lookup. */ | |
277 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) | |
278 | { | |
279 | struct cpu_model_info *info; | |
280 | ||
281 | if (c->x86_model >= 16) | |
282 | return NULL; /* Range check */ | |
283 | ||
284 | if (!this_cpu) | |
285 | return NULL; | |
286 | ||
287 | info = this_cpu->c_models; | |
288 | ||
289 | while (info && info->family) { | |
290 | if (info->family == c->x86) | |
291 | return info->model_names[c->x86_model]; | |
292 | info++; | |
293 | } | |
294 | return NULL; /* Not found */ | |
295 | } | |
296 | ||
7d851c8d AK |
297 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
298 | ||
9d31d35b YL |
299 | /* Current gdt points %fs at the "master" per-cpu area: after this, |
300 | * it's on the real one. */ | |
301 | void switch_to_new_gdt(void) | |
302 | { | |
303 | struct desc_ptr gdt_descr; | |
2697fbd5 | 304 | int cpu = smp_processor_id(); |
9d31d35b | 305 | |
2697fbd5 | 306 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
307 | gdt_descr.size = GDT_SIZE - 1; |
308 | load_gdt(&gdt_descr); | |
2697fbd5 | 309 | /* Reload the per-cpu base */ |
fab334c1 | 310 | #ifdef CONFIG_X86_32 |
2697fbd5 BG |
311 | loadsegment(fs, __KERNEL_PERCPU); |
312 | #else | |
313 | loadsegment(gs, 0); | |
314 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
fab334c1 | 315 | #endif |
9d31d35b YL |
316 | } |
317 | ||
10a434fc | 318 | static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 319 | |
34048c9e | 320 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
1da177e4 | 321 | { |
b9e67f00 YL |
322 | #ifdef CONFIG_X86_64 |
323 | display_cacheinfo(c); | |
324 | #else | |
1da177e4 LT |
325 | /* Not much we can do here... */ |
326 | /* Check if at least it has cpuid */ | |
327 | if (c->cpuid_level == -1) { | |
328 | /* No cpuid. It must be an ancient CPU */ | |
329 | if (c->x86 == 4) | |
330 | strcpy(c->x86_model_id, "486"); | |
331 | else if (c->x86 == 3) | |
332 | strcpy(c->x86_model_id, "386"); | |
333 | } | |
b9e67f00 | 334 | #endif |
1da177e4 LT |
335 | } |
336 | ||
95414930 | 337 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 338 | .c_init = default_init, |
fe38d855 | 339 | .c_vendor = "Unknown", |
10a434fc | 340 | .c_x86_vendor = X86_VENDOR_UNKNOWN, |
1da177e4 | 341 | }; |
1da177e4 | 342 | |
1b05d60d | 343 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
344 | { |
345 | unsigned int *v; | |
346 | char *p, *q; | |
347 | ||
3da99c97 | 348 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 349 | return; |
1da177e4 LT |
350 | |
351 | v = (unsigned int *) c->x86_model_id; | |
352 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
353 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
354 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
355 | c->x86_model_id[48] = 0; | |
356 | ||
357 | /* Intel chips right-justify this string for some dumb reason; | |
358 | undo that brain damage */ | |
359 | p = q = &c->x86_model_id[0]; | |
34048c9e | 360 | while (*p == ' ') |
1da177e4 | 361 | p++; |
34048c9e PC |
362 | if (p != q) { |
363 | while (*p) | |
1da177e4 | 364 | *q++ = *p++; |
34048c9e | 365 | while (q <= &c->x86_model_id[48]) |
1da177e4 LT |
366 | *q++ = '\0'; /* Zero-pad the rest */ |
367 | } | |
1da177e4 LT |
368 | } |
369 | ||
3bc9b76b | 370 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 | 371 | { |
9d31d35b | 372 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 373 | |
3da99c97 | 374 | n = c->extended_cpuid_level; |
1da177e4 LT |
375 | |
376 | if (n >= 0x80000005) { | |
9d31d35b | 377 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 378 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
9d31d35b YL |
379 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); |
380 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
140fc727 YL |
381 | #ifdef CONFIG_X86_64 |
382 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
383 | c->x86_tlbsize = 0; | |
384 | #endif | |
1da177e4 LT |
385 | } |
386 | ||
387 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
388 | return; | |
389 | ||
0a488a53 | 390 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 391 | l2size = ecx >> 16; |
34048c9e | 392 | |
140fc727 YL |
393 | #ifdef CONFIG_X86_64 |
394 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
395 | #else | |
1da177e4 LT |
396 | /* do processor-specific cache resizing */ |
397 | if (this_cpu->c_size_cache) | |
34048c9e | 398 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
399 | |
400 | /* Allow user to override all this if necessary. */ | |
401 | if (cachesize_override != -1) | |
402 | l2size = cachesize_override; | |
403 | ||
34048c9e | 404 | if (l2size == 0) |
1da177e4 | 405 | return; /* Again, no L2 cache is possible */ |
140fc727 | 406 | #endif |
1da177e4 LT |
407 | |
408 | c->x86_cache_size = l2size; | |
409 | ||
410 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
0a488a53 | 411 | l2size, ecx & 0xFF); |
1da177e4 LT |
412 | } |
413 | ||
9d31d35b | 414 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 415 | { |
97e4db7c | 416 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
417 | u32 eax, ebx, ecx, edx; |
418 | int index_msb, core_bits; | |
1da177e4 | 419 | |
0a488a53 | 420 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 421 | return; |
1da177e4 | 422 | |
0a488a53 YL |
423 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
424 | goto out; | |
1da177e4 | 425 | |
1cd78776 YL |
426 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
427 | return; | |
1da177e4 | 428 | |
0a488a53 | 429 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 430 | |
9d31d35b YL |
431 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
432 | ||
433 | if (smp_num_siblings == 1) { | |
434 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
435 | } else if (smp_num_siblings > 1) { | |
436 | ||
9628937d | 437 | if (smp_num_siblings > nr_cpu_ids) { |
9d31d35b YL |
438 | printk(KERN_WARNING "CPU: Unsupported number of siblings %d", |
439 | smp_num_siblings); | |
440 | smp_num_siblings = 1; | |
441 | return; | |
442 | } | |
443 | ||
444 | index_msb = get_count_order(smp_num_siblings); | |
445 | c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b YL |
446 | |
447 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
448 | ||
449 | index_msb = get_count_order(smp_num_siblings); | |
450 | ||
451 | core_bits = get_count_order(c->x86_max_cores); | |
452 | ||
453 | c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) & | |
454 | ((1 << core_bits) - 1); | |
1da177e4 | 455 | } |
1da177e4 | 456 | |
0a488a53 YL |
457 | out: |
458 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
459 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
460 | c->phys_proc_id); | |
461 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
462 | c->cpu_core_id); | |
9d31d35b | 463 | } |
9d31d35b | 464 | #endif |
97e4db7c | 465 | } |
1da177e4 | 466 | |
3da99c97 | 467 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
468 | { |
469 | char *v = c->x86_vendor_id; | |
470 | int i; | |
fe38d855 | 471 | static int printed; |
1da177e4 LT |
472 | |
473 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
474 | if (!cpu_devs[i]) |
475 | break; | |
476 | ||
477 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
478 | (cpu_devs[i]->c_ident[1] && | |
479 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
480 | this_cpu = cpu_devs[i]; | |
481 | c->x86_vendor = this_cpu->c_x86_vendor; | |
482 | return; | |
1da177e4 LT |
483 | } |
484 | } | |
10a434fc | 485 | |
fe38d855 CE |
486 | if (!printed) { |
487 | printed++; | |
43603c8d | 488 | printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v); |
fe38d855 CE |
489 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); |
490 | } | |
10a434fc | 491 | |
fe38d855 CE |
492 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
493 | this_cpu = &default_cpu; | |
1da177e4 LT |
494 | } |
495 | ||
9d31d35b | 496 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 497 | { |
1da177e4 | 498 | /* Get vendor name */ |
4a148513 HH |
499 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
500 | (unsigned int *)&c->x86_vendor_id[0], | |
501 | (unsigned int *)&c->x86_vendor_id[8], | |
502 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 503 | |
1da177e4 | 504 | c->x86 = 4; |
9d31d35b | 505 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
506 | if (c->cpuid_level >= 0x00000001) { |
507 | u32 junk, tfms, cap0, misc; | |
508 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
9d31d35b YL |
509 | c->x86 = (tfms >> 8) & 0xf; |
510 | c->x86_model = (tfms >> 4) & 0xf; | |
511 | c->x86_mask = tfms & 0xf; | |
f5f786d0 | 512 | if (c->x86 == 0xf) |
1da177e4 | 513 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 514 | if (c->x86 >= 0x6) |
9d31d35b | 515 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
d4387bd3 | 516 | if (cap0 & (1<<19)) { |
d4387bd3 | 517 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 518 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 519 | } |
1da177e4 | 520 | } |
1da177e4 | 521 | } |
3da99c97 YL |
522 | |
523 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
093af8d7 YL |
524 | { |
525 | u32 tfms, xlvl; | |
3da99c97 | 526 | u32 ebx; |
093af8d7 | 527 | |
3da99c97 YL |
528 | /* Intel-defined flags: level 0x00000001 */ |
529 | if (c->cpuid_level >= 0x00000001) { | |
530 | u32 capability, excap; | |
531 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
532 | c->x86_capability[0] = capability; | |
533 | c->x86_capability[4] = excap; | |
534 | } | |
093af8d7 | 535 | |
3da99c97 YL |
536 | /* AMD-defined flags: level 0x80000001 */ |
537 | xlvl = cpuid_eax(0x80000000); | |
538 | c->extended_cpuid_level = xlvl; | |
539 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
540 | if (xlvl >= 0x80000001) { | |
541 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
542 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 543 | } |
093af8d7 | 544 | } |
093af8d7 | 545 | |
5122c890 | 546 | #ifdef CONFIG_X86_64 |
5122c890 YL |
547 | if (c->extended_cpuid_level >= 0x80000008) { |
548 | u32 eax = cpuid_eax(0x80000008); | |
549 | ||
550 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
551 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 552 | } |
5122c890 | 553 | #endif |
e3224234 YL |
554 | |
555 | if (c->extended_cpuid_level >= 0x80000007) | |
556 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 YL |
557 | |
558 | } | |
1da177e4 | 559 | |
aef93c8b YL |
560 | static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
561 | { | |
562 | #ifdef CONFIG_X86_32 | |
563 | int i; | |
564 | ||
565 | /* | |
566 | * First of all, decide if this is a 486 or higher | |
567 | * It's a 486 if we can modify the AC flag | |
568 | */ | |
569 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
570 | c->x86 = 4; | |
571 | else | |
572 | c->x86 = 3; | |
573 | ||
574 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
575 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
576 | c->x86_vendor_id[0] = 0; | |
577 | cpu_devs[i]->c_identify(c); | |
578 | if (c->x86_vendor_id[0]) { | |
579 | get_cpu_vendor(c); | |
580 | break; | |
581 | } | |
582 | } | |
583 | #endif | |
584 | } | |
585 | ||
34048c9e PC |
586 | /* |
587 | * Do minimum CPU detection early. | |
588 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
589 | * cache alignment. | |
590 | * The others are not touched to avoid unwanted side effects. | |
591 | * | |
592 | * WARNING: this function is only called on the BP. Don't add code here | |
593 | * that is supposed to run on all CPUs. | |
594 | */ | |
3da99c97 | 595 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 596 | { |
6627d242 YL |
597 | #ifdef CONFIG_X86_64 |
598 | c->x86_clflush_size = 64; | |
599 | #else | |
d4387bd3 | 600 | c->x86_clflush_size = 32; |
6627d242 | 601 | #endif |
0a488a53 | 602 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 603 | |
3da99c97 | 604 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 605 | c->extended_cpuid_level = 0; |
d7cd5611 | 606 | |
aef93c8b YL |
607 | if (!have_cpuid_p()) |
608 | identify_cpu_without_cpuid(c); | |
609 | ||
610 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
611 | if (!have_cpuid_p()) |
612 | return; | |
613 | ||
614 | cpu_detect(c); | |
615 | ||
3da99c97 | 616 | get_cpu_vendor(c); |
2b16a235 | 617 | |
3da99c97 | 618 | get_cpu_cap(c); |
12cf105c | 619 | |
10a434fc YL |
620 | if (this_cpu->c_early_init) |
621 | this_cpu->c_early_init(c); | |
093af8d7 | 622 | |
1c4acdb4 | 623 | #ifdef CONFIG_SMP |
bfcb4c1b | 624 | c->cpu_index = boot_cpu_id; |
1c4acdb4 | 625 | #endif |
b38b0665 | 626 | filter_cpuid_features(c, false); |
d7cd5611 RR |
627 | } |
628 | ||
9d31d35b YL |
629 | void __init early_cpu_init(void) |
630 | { | |
10a434fc YL |
631 | struct cpu_dev **cdev; |
632 | int count = 0; | |
633 | ||
634 | printk("KERNEL supported cpus:\n"); | |
635 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { | |
636 | struct cpu_dev *cpudev = *cdev; | |
637 | unsigned int j; | |
9d31d35b | 638 | |
10a434fc YL |
639 | if (count >= X86_VENDOR_NUM) |
640 | break; | |
641 | cpu_devs[count] = cpudev; | |
642 | count++; | |
643 | ||
644 | for (j = 0; j < 2; j++) { | |
645 | if (!cpudev->c_ident[j]) | |
646 | continue; | |
647 | printk(" %s %s\n", cpudev->c_vendor, | |
648 | cpudev->c_ident[j]); | |
649 | } | |
650 | } | |
9d31d35b | 651 | |
9d31d35b | 652 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 653 | } |
093af8d7 | 654 | |
b6734c35 PA |
655 | /* |
656 | * The NOPL instruction is supposed to exist on all CPUs with | |
ba0593bf | 657 | * family >= 6; unfortunately, that's not true in practice because |
b6734c35 | 658 | * of early VIA chips and (more importantly) broken virtualizers that |
ba0593bf PA |
659 | * are not easy to detect. In the latter case it doesn't even *fail* |
660 | * reliably, so probing for it doesn't even work. Disable it completely | |
661 | * unless we can find a reliable way to detect all the broken cases. | |
b6734c35 PA |
662 | */ |
663 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
664 | { | |
b6734c35 | 665 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
d7cd5611 RR |
666 | } |
667 | ||
34048c9e | 668 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 669 | { |
aef93c8b | 670 | c->extended_cpuid_level = 0; |
1da177e4 | 671 | |
3da99c97 | 672 | if (!have_cpuid_p()) |
aef93c8b | 673 | identify_cpu_without_cpuid(c); |
1d67953f | 674 | |
aef93c8b | 675 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 676 | if (!have_cpuid_p()) |
aef93c8b | 677 | return; |
1da177e4 | 678 | |
3da99c97 | 679 | cpu_detect(c); |
1da177e4 | 680 | |
3da99c97 | 681 | get_cpu_vendor(c); |
1da177e4 | 682 | |
3da99c97 | 683 | get_cpu_cap(c); |
1da177e4 | 684 | |
3da99c97 YL |
685 | if (c->cpuid_level >= 0x00000001) { |
686 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
687 | #ifdef CONFIG_X86_32 |
688 | # ifdef CONFIG_X86_HT | |
3da99c97 | 689 | c->apicid = phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 690 | # else |
3da99c97 | 691 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
692 | # endif |
693 | #endif | |
1da177e4 | 694 | |
b89d3b3e YL |
695 | #ifdef CONFIG_X86_HT |
696 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 697 | #endif |
3da99c97 | 698 | } |
1da177e4 | 699 | |
1b05d60d | 700 | get_model_name(c); /* Default name */ |
1da177e4 | 701 | |
3da99c97 YL |
702 | init_scattered_cpuid_features(c); |
703 | detect_nopl(c); | |
1da177e4 | 704 | } |
1da177e4 LT |
705 | |
706 | /* | |
707 | * This does the hard work of actually picking apart the CPU stuff... | |
708 | */ | |
9a250347 | 709 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
710 | { |
711 | int i; | |
712 | ||
713 | c->loops_per_jiffy = loops_per_jiffy; | |
714 | c->x86_cache_size = -1; | |
715 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
716 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
717 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
718 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 719 | c->x86_max_cores = 1; |
102bbe3a | 720 | c->x86_coreid_bits = 0; |
11fdd252 | 721 | #ifdef CONFIG_X86_64 |
102bbe3a YL |
722 | c->x86_clflush_size = 64; |
723 | #else | |
724 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 725 | c->x86_clflush_size = 32; |
102bbe3a YL |
726 | #endif |
727 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
728 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
729 | ||
1da177e4 LT |
730 | generic_identify(c); |
731 | ||
3898534d | 732 | if (this_cpu->c_identify) |
1da177e4 LT |
733 | this_cpu->c_identify(c); |
734 | ||
102bbe3a | 735 | #ifdef CONFIG_X86_64 |
d4c9a9f3 | 736 | c->apicid = phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
737 | #endif |
738 | ||
1da177e4 LT |
739 | /* |
740 | * Vendor-specific initialization. In this section we | |
741 | * canonicalize the feature flags, meaning if there are | |
742 | * features a certain CPU supports which CPUID doesn't | |
743 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
744 | * we handle them here. | |
745 | * | |
746 | * At the end of this section, c->x86_capability better | |
747 | * indicate the features this CPU genuinely supports! | |
748 | */ | |
749 | if (this_cpu->c_init) | |
750 | this_cpu->c_init(c); | |
751 | ||
752 | /* Disable the PN if appropriate */ | |
753 | squash_the_stupid_serial_number(c); | |
754 | ||
755 | /* | |
756 | * The vendor-specific functions might have changed features. Now | |
757 | * we do "generic changes." | |
758 | */ | |
759 | ||
b38b0665 PA |
760 | /* Filter out anything that depends on CPUID levels we don't have */ |
761 | filter_cpuid_features(c, true); | |
762 | ||
1da177e4 | 763 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 764 | if (!c->x86_model_id[0]) { |
1da177e4 LT |
765 | char *p; |
766 | p = table_lookup_model(c); | |
34048c9e | 767 | if (p) |
1da177e4 LT |
768 | strcpy(c->x86_model_id, p); |
769 | else | |
770 | /* Last resort... */ | |
771 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 772 | c->x86, c->x86_model); |
1da177e4 LT |
773 | } |
774 | ||
102bbe3a YL |
775 | #ifdef CONFIG_X86_64 |
776 | detect_ht(c); | |
777 | #endif | |
778 | ||
88b094fb | 779 | init_hypervisor(c); |
1da177e4 LT |
780 | /* |
781 | * On SMP, boot_cpu_data holds the common feature set between | |
782 | * all CPUs; so make sure that we indicate which features are | |
783 | * common between the CPUs. The first time this routine gets | |
784 | * executed, c == &boot_cpu_data. | |
785 | */ | |
34048c9e | 786 | if (c != &boot_cpu_data) { |
1da177e4 | 787 | /* AND the already accumulated flags with these */ |
9d31d35b | 788 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
789 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
790 | } | |
791 | ||
7d851c8d AK |
792 | /* Clear all flags overriden by options */ |
793 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 794 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 795 | |
102bbe3a | 796 | #ifdef CONFIG_X86_MCE |
1da177e4 | 797 | /* Init Machine Check Exception if available. */ |
1da177e4 | 798 | mcheck_init(c); |
102bbe3a | 799 | #endif |
30d432df AK |
800 | |
801 | select_idle_routine(c); | |
102bbe3a YL |
802 | |
803 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
804 | numa_add_cpu(smp_processor_id()); | |
805 | #endif | |
a6c4e076 | 806 | } |
31ab269a | 807 | |
e04d645f GC |
808 | #ifdef CONFIG_X86_64 |
809 | static void vgetcpu_set_mode(void) | |
810 | { | |
811 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
812 | vgetcpu_mode = VGETCPU_RDTSCP; | |
813 | else | |
814 | vgetcpu_mode = VGETCPU_LSL; | |
815 | } | |
816 | #endif | |
817 | ||
a6c4e076 JF |
818 | void __init identify_boot_cpu(void) |
819 | { | |
820 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 821 | #ifdef CONFIG_X86_32 |
a6c4e076 | 822 | sysenter_setup(); |
6fe940d6 | 823 | enable_sep_cpu(); |
e04d645f GC |
824 | #else |
825 | vgetcpu_set_mode(); | |
102bbe3a | 826 | #endif |
a6c4e076 | 827 | } |
3b520b23 | 828 | |
a6c4e076 JF |
829 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
830 | { | |
831 | BUG_ON(c == &boot_cpu_data); | |
832 | identify_cpu(c); | |
102bbe3a | 833 | #ifdef CONFIG_X86_32 |
a6c4e076 | 834 | enable_sep_cpu(); |
102bbe3a | 835 | #endif |
a6c4e076 | 836 | mtrr_ap_init(); |
1da177e4 LT |
837 | } |
838 | ||
a0854a46 YL |
839 | struct msr_range { |
840 | unsigned min; | |
841 | unsigned max; | |
842 | }; | |
1da177e4 | 843 | |
a0854a46 YL |
844 | static struct msr_range msr_range_array[] __cpuinitdata = { |
845 | { 0x00000000, 0x00000418}, | |
846 | { 0xc0000000, 0xc000040b}, | |
847 | { 0xc0010000, 0xc0010142}, | |
848 | { 0xc0011000, 0xc001103b}, | |
849 | }; | |
1da177e4 | 850 | |
a0854a46 YL |
851 | static void __cpuinit print_cpu_msr(void) |
852 | { | |
853 | unsigned index; | |
854 | u64 val; | |
855 | int i; | |
856 | unsigned index_min, index_max; | |
857 | ||
858 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
859 | index_min = msr_range_array[i].min; | |
860 | index_max = msr_range_array[i].max; | |
861 | for (index = index_min; index < index_max; index++) { | |
862 | if (rdmsrl_amd_safe(index, &val)) | |
863 | continue; | |
864 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 865 | } |
a0854a46 YL |
866 | } |
867 | } | |
94605eff | 868 | |
a0854a46 YL |
869 | static int show_msr __cpuinitdata; |
870 | static __init int setup_show_msr(char *arg) | |
871 | { | |
872 | int num; | |
3dd9d514 | 873 | |
a0854a46 | 874 | get_option(&arg, &num); |
3dd9d514 | 875 | |
a0854a46 YL |
876 | if (num > 0) |
877 | show_msr = num; | |
878 | return 1; | |
1da177e4 | 879 | } |
a0854a46 | 880 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 881 | |
191679fd AK |
882 | static __init int setup_noclflush(char *arg) |
883 | { | |
884 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
885 | return 1; | |
886 | } | |
887 | __setup("noclflush", setup_noclflush); | |
888 | ||
3bc9b76b | 889 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
890 | { |
891 | char *vendor = NULL; | |
892 | ||
893 | if (c->x86_vendor < X86_VENDOR_NUM) | |
894 | vendor = this_cpu->c_vendor; | |
895 | else if (c->cpuid_level >= 0) | |
896 | vendor = c->x86_vendor_id; | |
897 | ||
bd32a8cf | 898 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 899 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 900 | |
9d31d35b YL |
901 | if (c->x86_model_id[0]) |
902 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 903 | else |
9d31d35b | 904 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 905 | |
34048c9e | 906 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 907 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 908 | else |
9d31d35b | 909 | printk(KERN_CONT "\n"); |
a0854a46 YL |
910 | |
911 | #ifdef CONFIG_SMP | |
912 | if (c->cpu_index < show_msr) | |
913 | print_cpu_msr(); | |
914 | #else | |
915 | if (show_msr) | |
916 | print_cpu_msr(); | |
917 | #endif | |
1da177e4 LT |
918 | } |
919 | ||
ac72e788 AK |
920 | static __init int setup_disablecpuid(char *arg) |
921 | { | |
922 | int bit; | |
923 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
924 | setup_clear_cpu_cap(bit); | |
925 | else | |
926 | return 0; | |
927 | return 1; | |
928 | } | |
929 | __setup("clearcpuid=", setup_disablecpuid); | |
930 | ||
d5494d4f | 931 | #ifdef CONFIG_X86_64 |
d5494d4f YL |
932 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; |
933 | ||
947e76cd BG |
934 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
935 | irq_stack_union) __aligned(PAGE_SIZE); | |
26f80bd6 BG |
936 | #ifdef CONFIG_SMP |
937 | DEFINE_PER_CPU(char *, irq_stack_ptr); /* will be set during per cpu init */ | |
938 | #else | |
939 | DEFINE_PER_CPU(char *, irq_stack_ptr) = | |
947e76cd | 940 | per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; |
26f80bd6 | 941 | #endif |
d5494d4f | 942 | |
9af45651 BG |
943 | DEFINE_PER_CPU(unsigned long, kernel_stack) = |
944 | (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; | |
945 | EXPORT_PER_CPU_SYMBOL(kernel_stack); | |
946 | ||
56895530 BG |
947 | DEFINE_PER_CPU(unsigned int, irq_count) = -1; |
948 | ||
92d65b23 BG |
949 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
950 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]) | |
951 | __aligned(PAGE_SIZE); | |
d5494d4f YL |
952 | |
953 | extern asmlinkage void ignore_sysret(void); | |
954 | ||
955 | /* May not be marked __init: used by software suspend */ | |
956 | void syscall_init(void) | |
1da177e4 | 957 | { |
d5494d4f YL |
958 | /* |
959 | * LSTAR and STAR live in a bit strange symbiosis. | |
960 | * They both write to the same internal register. STAR allows to | |
961 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
962 | */ | |
963 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
964 | wrmsrl(MSR_LSTAR, system_call); | |
965 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 966 | |
d5494d4f YL |
967 | #ifdef CONFIG_IA32_EMULATION |
968 | syscall32_cpu_init(); | |
969 | #endif | |
03ae5768 | 970 | |
d5494d4f YL |
971 | /* Flags to clear on syscall */ |
972 | wrmsrl(MSR_SYSCALL_MASK, | |
973 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
1da177e4 | 974 | } |
62111195 | 975 | |
d5494d4f YL |
976 | unsigned long kernel_eflags; |
977 | ||
978 | /* | |
979 | * Copies of the original ist values from the tss are only accessed during | |
980 | * debugging, no special alignment required. | |
981 | */ | |
982 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
983 | ||
984 | #else | |
985 | ||
7c3576d2 | 986 | /* Make sure %fs is initialized properly in idle threads */ |
6b2fb3c6 | 987 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
988 | { |
989 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 990 | regs->fs = __KERNEL_PERCPU; |
f95d47ca JF |
991 | return regs; |
992 | } | |
d5494d4f | 993 | #endif |
c5413fbe | 994 | |
d2cbcc49 RR |
995 | /* |
996 | * cpu_init() initializes state that is per-CPU. Some data is already | |
997 | * initialized (naturally) in the bootstrap process, such as the GDT | |
998 | * and IDT. We reload them nevertheless, this function acts as a | |
999 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1000 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1001 | */ |
1ba76586 YL |
1002 | #ifdef CONFIG_X86_64 |
1003 | void __cpuinit cpu_init(void) | |
1004 | { | |
1005 | int cpu = stack_smp_processor_id(); | |
1006 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
1007 | struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); | |
1008 | unsigned long v; | |
1ba76586 YL |
1009 | struct task_struct *me; |
1010 | int i; | |
1011 | ||
e7a22c1e BG |
1012 | #ifdef CONFIG_NUMA |
1013 | if (cpu != 0 && percpu_read(node_number) == 0 && | |
1014 | cpu_to_node(cpu) != NUMA_NO_NODE) | |
1015 | percpu_write(node_number, cpu_to_node(cpu)); | |
1016 | #endif | |
1017 | ||
1ba76586 YL |
1018 | me = current; |
1019 | ||
c2d1cec1 | 1020 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) |
1ba76586 YL |
1021 | panic("CPU#%d already initialized!\n", cpu); |
1022 | ||
1023 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1024 | ||
1025 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1026 | ||
1027 | /* | |
1028 | * Initialize the per-CPU GDT with the boot GDT, | |
1029 | * and set up the GDT descriptor: | |
1030 | */ | |
1031 | ||
1032 | switch_to_new_gdt(); | |
2697fbd5 BG |
1033 | loadsegment(fs, 0); |
1034 | ||
1ba76586 YL |
1035 | load_idt((const struct desc_ptr *)&idt_descr); |
1036 | ||
1037 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1038 | syscall_init(); | |
1039 | ||
1040 | wrmsrl(MSR_FS_BASE, 0); | |
1041 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1042 | barrier(); | |
1043 | ||
1044 | check_efer(); | |
1045 | if (cpu != 0 && x2apic) | |
1046 | enable_x2apic(); | |
1047 | ||
1048 | /* | |
1049 | * set up and load the per-CPU TSS | |
1050 | */ | |
1051 | if (!orig_ist->ist[0]) { | |
92d65b23 BG |
1052 | static const unsigned int sizes[N_EXCEPTION_STACKS] = { |
1053 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1054 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1ba76586 | 1055 | }; |
92d65b23 | 1056 | char *estacks = per_cpu(exception_stacks, cpu); |
1ba76586 | 1057 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
92d65b23 | 1058 | estacks += sizes[v]; |
1ba76586 YL |
1059 | orig_ist->ist[v] = t->x86_tss.ist[v] = |
1060 | (unsigned long)estacks; | |
1061 | } | |
1062 | } | |
1063 | ||
1064 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
1065 | /* | |
1066 | * <= is required because the CPU will access up to | |
1067 | * 8 bits beyond the end of the IO permission bitmap. | |
1068 | */ | |
1069 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1070 | t->io_bitmap[i] = ~0UL; | |
1071 | ||
1072 | atomic_inc(&init_mm.mm_count); | |
1073 | me->active_mm = &init_mm; | |
1074 | if (me->mm) | |
1075 | BUG(); | |
1076 | enter_lazy_tlb(&init_mm, me); | |
1077 | ||
1078 | load_sp0(t, ¤t->thread); | |
1079 | set_tss_desc(cpu, t); | |
1080 | load_TR_desc(); | |
1081 | load_LDT(&init_mm.context); | |
1082 | ||
1083 | #ifdef CONFIG_KGDB | |
1084 | /* | |
1085 | * If the kgdb is connected no debug regs should be altered. This | |
1086 | * is only applicable when KGDB and a KGDB I/O module are built | |
1087 | * into the kernel and you are using early debugging with | |
1088 | * kgdbwait. KGDB will control the kernel HW breakpoint registers. | |
1089 | */ | |
1090 | if (kgdb_connected && arch_kgdb_ops.correct_hw_break) | |
1091 | arch_kgdb_ops.correct_hw_break(); | |
8f6d86dc | 1092 | else |
1ba76586 | 1093 | #endif |
8f6d86dc PZ |
1094 | { |
1095 | /* | |
1096 | * Clear all 6 debug registers: | |
1097 | */ | |
1098 | set_debugreg(0UL, 0); | |
1099 | set_debugreg(0UL, 1); | |
1100 | set_debugreg(0UL, 2); | |
1101 | set_debugreg(0UL, 3); | |
1102 | set_debugreg(0UL, 6); | |
1103 | set_debugreg(0UL, 7); | |
1ba76586 | 1104 | } |
1ba76586 YL |
1105 | |
1106 | fpu_init(); | |
1107 | ||
1108 | raw_local_save_flags(kernel_eflags); | |
1109 | ||
1110 | if (is_uv_system()) | |
1111 | uv_cpu_init(); | |
1112 | } | |
1113 | ||
1114 | #else | |
1115 | ||
d2cbcc49 | 1116 | void __cpuinit cpu_init(void) |
9ee79a3d | 1117 | { |
d2cbcc49 RR |
1118 | int cpu = smp_processor_id(); |
1119 | struct task_struct *curr = current; | |
34048c9e | 1120 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1121 | struct thread_struct *thread = &curr->thread; |
62111195 | 1122 | |
c2d1cec1 | 1123 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { |
62111195 JF |
1124 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); |
1125 | for (;;) local_irq_enable(); | |
1126 | } | |
1127 | ||
1128 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1129 | ||
1130 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1131 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1132 | |
4d37e7e3 | 1133 | load_idt(&idt_descr); |
c5413fbe | 1134 | switch_to_new_gdt(); |
1da177e4 | 1135 | |
1da177e4 LT |
1136 | /* |
1137 | * Set up and load the per-CPU TSS and LDT | |
1138 | */ | |
1139 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
1140 | curr->active_mm = &init_mm; |
1141 | if (curr->mm) | |
1142 | BUG(); | |
1143 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 | 1144 | |
faca6227 | 1145 | load_sp0(t, thread); |
34048c9e | 1146 | set_tss_desc(cpu, t); |
1da177e4 LT |
1147 | load_TR_desc(); |
1148 | load_LDT(&init_mm.context); | |
1149 | ||
22c4e308 | 1150 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1151 | /* Set up doublefault TSS pointer in the GDT */ |
1152 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1153 | #endif |
1da177e4 | 1154 | |
464d1a78 JF |
1155 | /* Clear %gs. */ |
1156 | asm volatile ("mov %0, %%gs" : : "r" (0)); | |
1da177e4 LT |
1157 | |
1158 | /* Clear all 6 debug registers: */ | |
4bb0d3ec ZA |
1159 | set_debugreg(0, 0); |
1160 | set_debugreg(0, 1); | |
1161 | set_debugreg(0, 2); | |
1162 | set_debugreg(0, 3); | |
1163 | set_debugreg(0, 6); | |
1164 | set_debugreg(0, 7); | |
1da177e4 LT |
1165 | |
1166 | /* | |
1167 | * Force FPU initialization: | |
1168 | */ | |
b359e8a4 SS |
1169 | if (cpu_has_xsave) |
1170 | current_thread_info()->status = TS_XSAVE; | |
1171 | else | |
1172 | current_thread_info()->status = 0; | |
1da177e4 LT |
1173 | clear_used_math(); |
1174 | mxcsr_feature_mask_init(); | |
dc1e35c6 SS |
1175 | |
1176 | /* | |
1177 | * Boot processor to setup the FP and extended state context info. | |
1178 | */ | |
b3572e36 | 1179 | if (smp_processor_id() == boot_cpu_id) |
dc1e35c6 SS |
1180 | init_thread_xstate(); |
1181 | ||
1182 | xsave_init(); | |
1da177e4 | 1183 | } |
e1367daf | 1184 | |
1ba76586 YL |
1185 | |
1186 | #endif |