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1da177e4 | 1 | #include <linux/init.h> |
f0fc4aff YL |
2 | #include <linux/kernel.h> |
3 | #include <linux/sched.h> | |
1da177e4 | 4 | #include <linux/string.h> |
f0fc4aff YL |
5 | #include <linux/bootmem.h> |
6 | #include <linux/bitops.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/kgdb.h> | |
9 | #include <linux/topology.h> | |
1da177e4 LT |
10 | #include <linux/delay.h> |
11 | #include <linux/smp.h> | |
1da177e4 | 12 | #include <linux/percpu.h> |
1da177e4 LT |
13 | #include <asm/i387.h> |
14 | #include <asm/msr.h> | |
15 | #include <asm/io.h> | |
f0fc4aff | 16 | #include <asm/linkage.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
27b07da7 | 18 | #include <asm/mtrr.h> |
a03a3e28 | 19 | #include <asm/mce.h> |
8d4a4300 | 20 | #include <asm/pat.h> |
7e00df58 | 21 | #include <asm/asm.h> |
f0fc4aff | 22 | #include <asm/numa.h> |
1da177e4 LT |
23 | #ifdef CONFIG_X86_LOCAL_APIC |
24 | #include <asm/mpspec.h> | |
25 | #include <asm/apic.h> | |
26 | #include <mach_apic.h> | |
f0fc4aff | 27 | #include <asm/genapic.h> |
1da177e4 LT |
28 | #endif |
29 | ||
f0fc4aff YL |
30 | #include <asm/pda.h> |
31 | #include <asm/pgtable.h> | |
32 | #include <asm/processor.h> | |
33 | #include <asm/desc.h> | |
34 | #include <asm/atomic.h> | |
35 | #include <asm/proto.h> | |
36 | #include <asm/sections.h> | |
37 | #include <asm/setup.h> | |
38 | ||
1da177e4 LT |
39 | #include "cpu.h" |
40 | ||
0a488a53 YL |
41 | static struct cpu_dev *this_cpu __cpuinitdata; |
42 | ||
950ad7ff YL |
43 | #ifdef CONFIG_X86_64 |
44 | /* We need valid kernel segments for data and code in long mode too | |
45 | * IRET will check the segment types kkeil 2000/10/28 | |
46 | * Also sysret mandates a special GDT layout | |
47 | */ | |
48 | /* The TLS descriptors are currently at a different place compared to i386. | |
49 | Hopefully nobody expects them at a fixed place (Wine?) */ | |
50 | DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = { | |
51 | [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, | |
52 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, | |
53 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, | |
54 | [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, | |
55 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, | |
56 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, | |
57 | } }; | |
58 | #else | |
63cc8c75 | 59 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
6842ef0e GOC |
60 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
61 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
62 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
63 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
64 | /* |
65 | * Segments used for calling PnP BIOS have byte granularity. | |
66 | * They code segments and data segments have fixed 64k limits, | |
67 | * the transfer segment sizes are set at run time. | |
68 | */ | |
6842ef0e GOC |
69 | /* 32-bit code */ |
70 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
71 | /* 16-bit code */ | |
72 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
73 | /* 16-bit data */ | |
74 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
75 | /* 16-bit data */ | |
76 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
77 | /* 16-bit data */ | |
78 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
bf504672 RR |
79 | /* |
80 | * The APM segments have byte granularity and their bases | |
81 | * are set at run time. All have 64k limits. | |
82 | */ | |
6842ef0e GOC |
83 | /* 32-bit code */ |
84 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
bf504672 | 85 | /* 16-bit code */ |
6842ef0e GOC |
86 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
87 | /* data */ | |
88 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
bf504672 | 89 | |
6842ef0e GOC |
90 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
91 | [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } }, | |
7a61d35d | 92 | } }; |
950ad7ff | 93 | #endif |
7a61d35d | 94 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 95 | |
ba51dced | 96 | #ifdef CONFIG_X86_32 |
3bc9b76b | 97 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 98 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 99 | |
0a488a53 YL |
100 | static int __init cachesize_setup(char *str) |
101 | { | |
102 | get_option(&str, &cachesize_override); | |
103 | return 1; | |
104 | } | |
105 | __setup("cachesize=", cachesize_setup); | |
106 | ||
107 | /* | |
108 | * Naming convention should be: <Name> [(<Codename>)] | |
109 | * This table only is used unless init_<vendor>() below doesn't set it; | |
110 | * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used | |
111 | * | |
112 | */ | |
113 | ||
114 | /* Look up CPU names by table lookup. */ | |
115 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) | |
116 | { | |
117 | struct cpu_model_info *info; | |
118 | ||
119 | if (c->x86_model >= 16) | |
120 | return NULL; /* Range check */ | |
121 | ||
122 | if (!this_cpu) | |
123 | return NULL; | |
124 | ||
125 | info = this_cpu->c_models; | |
126 | ||
127 | while (info && info->family) { | |
128 | if (info->family == c->x86) | |
129 | return info->model_names[c->x86_model]; | |
130 | info++; | |
131 | } | |
132 | return NULL; /* Not found */ | |
133 | } | |
134 | ||
135 | static int __init x86_fxsr_setup(char *s) | |
136 | { | |
137 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
138 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
139 | return 1; | |
140 | } | |
141 | __setup("nofxsr", x86_fxsr_setup); | |
142 | ||
143 | static int __init x86_sep_setup(char *s) | |
144 | { | |
145 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
146 | return 1; | |
147 | } | |
148 | __setup("nosep", x86_sep_setup); | |
149 | ||
150 | /* Standard macro to see if a specific flag is changeable */ | |
151 | static inline int flag_is_changeable_p(u32 flag) | |
152 | { | |
153 | u32 f1, f2; | |
154 | ||
155 | asm("pushfl\n\t" | |
156 | "pushfl\n\t" | |
157 | "popl %0\n\t" | |
158 | "movl %0,%1\n\t" | |
159 | "xorl %2,%0\n\t" | |
160 | "pushl %0\n\t" | |
161 | "popfl\n\t" | |
162 | "pushfl\n\t" | |
163 | "popl %0\n\t" | |
164 | "popfl\n\t" | |
165 | : "=&r" (f1), "=&r" (f2) | |
166 | : "ir" (flag)); | |
167 | ||
168 | return ((f1^f2) & flag) != 0; | |
169 | } | |
170 | ||
171 | /* Probe for the CPUID instruction */ | |
172 | static int __cpuinit have_cpuid_p(void) | |
173 | { | |
174 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
175 | } | |
176 | ||
177 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
178 | { | |
179 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { | |
180 | /* Disable processor serial number */ | |
181 | unsigned long lo, hi; | |
182 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
183 | lo |= 0x200000; | |
184 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
185 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
186 | clear_cpu_cap(c, X86_FEATURE_PN); | |
187 | ||
188 | /* Disabling the serial number may affect the cpuid level */ | |
189 | c->cpuid_level = cpuid_eax(0); | |
190 | } | |
191 | } | |
192 | ||
193 | static int __init x86_serial_nr_setup(char *s) | |
194 | { | |
195 | disable_x86_serial_nr = 0; | |
196 | return 1; | |
197 | } | |
198 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced YL |
199 | #else |
200 | /* Probe for the CPUID instruction */ | |
201 | static inline int have_cpuid_p(void) | |
202 | { | |
203 | return 1; | |
204 | } | |
205 | #endif | |
0a488a53 | 206 | |
7d851c8d AK |
207 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
208 | ||
9d31d35b YL |
209 | /* Current gdt points %fs at the "master" per-cpu area: after this, |
210 | * it's on the real one. */ | |
211 | void switch_to_new_gdt(void) | |
212 | { | |
213 | struct desc_ptr gdt_descr; | |
214 | ||
215 | gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id()); | |
216 | gdt_descr.size = GDT_SIZE - 1; | |
217 | load_gdt(&gdt_descr); | |
218 | asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory"); | |
219 | } | |
220 | ||
10a434fc | 221 | static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 222 | |
34048c9e | 223 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
1da177e4 LT |
224 | { |
225 | /* Not much we can do here... */ | |
226 | /* Check if at least it has cpuid */ | |
227 | if (c->cpuid_level == -1) { | |
228 | /* No cpuid. It must be an ancient CPU */ | |
229 | if (c->x86 == 4) | |
230 | strcpy(c->x86_model_id, "486"); | |
231 | else if (c->x86 == 3) | |
232 | strcpy(c->x86_model_id, "386"); | |
233 | } | |
234 | } | |
235 | ||
95414930 | 236 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 237 | .c_init = default_init, |
fe38d855 | 238 | .c_vendor = "Unknown", |
10a434fc | 239 | .c_x86_vendor = X86_VENDOR_UNKNOWN, |
1da177e4 | 240 | }; |
1da177e4 | 241 | |
3bc9b76b | 242 | int __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
243 | { |
244 | unsigned int *v; | |
245 | char *p, *q; | |
246 | ||
3da99c97 | 247 | if (c->extended_cpuid_level < 0x80000004) |
1da177e4 LT |
248 | return 0; |
249 | ||
250 | v = (unsigned int *) c->x86_model_id; | |
251 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
252 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
253 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
254 | c->x86_model_id[48] = 0; | |
255 | ||
256 | /* Intel chips right-justify this string for some dumb reason; | |
257 | undo that brain damage */ | |
258 | p = q = &c->x86_model_id[0]; | |
34048c9e | 259 | while (*p == ' ') |
1da177e4 | 260 | p++; |
34048c9e PC |
261 | if (p != q) { |
262 | while (*p) | |
1da177e4 | 263 | *q++ = *p++; |
34048c9e | 264 | while (q <= &c->x86_model_id[48]) |
1da177e4 LT |
265 | *q++ = '\0'; /* Zero-pad the rest */ |
266 | } | |
267 | ||
268 | return 1; | |
269 | } | |
270 | ||
3bc9b76b | 271 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 | 272 | { |
9d31d35b | 273 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 274 | |
3da99c97 | 275 | n = c->extended_cpuid_level; |
1da177e4 LT |
276 | |
277 | if (n >= 0x80000005) { | |
9d31d35b | 278 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 279 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
9d31d35b YL |
280 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); |
281 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
1da177e4 LT |
282 | } |
283 | ||
284 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
285 | return; | |
286 | ||
0a488a53 | 287 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 288 | l2size = ecx >> 16; |
34048c9e | 289 | |
1da177e4 LT |
290 | /* do processor-specific cache resizing */ |
291 | if (this_cpu->c_size_cache) | |
34048c9e | 292 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
293 | |
294 | /* Allow user to override all this if necessary. */ | |
295 | if (cachesize_override != -1) | |
296 | l2size = cachesize_override; | |
297 | ||
34048c9e | 298 | if (l2size == 0) |
1da177e4 LT |
299 | return; /* Again, no L2 cache is possible */ |
300 | ||
301 | c->x86_cache_size = l2size; | |
302 | ||
303 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
0a488a53 | 304 | l2size, ecx & 0xFF); |
1da177e4 LT |
305 | } |
306 | ||
9d31d35b | 307 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 308 | { |
97e4db7c | 309 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
310 | u32 eax, ebx, ecx, edx; |
311 | int index_msb, core_bits; | |
1da177e4 | 312 | |
0a488a53 | 313 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 314 | return; |
1da177e4 | 315 | |
0a488a53 YL |
316 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
317 | goto out; | |
1da177e4 | 318 | |
0a488a53 | 319 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 320 | |
9d31d35b YL |
321 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
322 | ||
323 | if (smp_num_siblings == 1) { | |
324 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
325 | } else if (smp_num_siblings > 1) { | |
326 | ||
327 | if (smp_num_siblings > NR_CPUS) { | |
328 | printk(KERN_WARNING "CPU: Unsupported number of siblings %d", | |
329 | smp_num_siblings); | |
330 | smp_num_siblings = 1; | |
331 | return; | |
332 | } | |
333 | ||
334 | index_msb = get_count_order(smp_num_siblings); | |
335 | c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb); | |
336 | ||
9d31d35b YL |
337 | |
338 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
339 | ||
340 | index_msb = get_count_order(smp_num_siblings); | |
341 | ||
342 | core_bits = get_count_order(c->x86_max_cores); | |
343 | ||
344 | c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) & | |
345 | ((1 << core_bits) - 1); | |
1da177e4 | 346 | } |
1da177e4 | 347 | |
0a488a53 YL |
348 | out: |
349 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
350 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
351 | c->phys_proc_id); | |
352 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
353 | c->cpu_core_id); | |
9d31d35b | 354 | } |
9d31d35b | 355 | #endif |
97e4db7c | 356 | } |
1da177e4 | 357 | |
3da99c97 | 358 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
359 | { |
360 | char *v = c->x86_vendor_id; | |
361 | int i; | |
fe38d855 | 362 | static int printed; |
1da177e4 LT |
363 | |
364 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
365 | if (!cpu_devs[i]) |
366 | break; | |
367 | ||
368 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
369 | (cpu_devs[i]->c_ident[1] && | |
370 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
371 | this_cpu = cpu_devs[i]; | |
372 | c->x86_vendor = this_cpu->c_x86_vendor; | |
373 | return; | |
1da177e4 LT |
374 | } |
375 | } | |
10a434fc | 376 | |
fe38d855 CE |
377 | if (!printed) { |
378 | printed++; | |
379 | printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n"); | |
380 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); | |
381 | } | |
10a434fc | 382 | |
fe38d855 CE |
383 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
384 | this_cpu = &default_cpu; | |
1da177e4 LT |
385 | } |
386 | ||
9d31d35b | 387 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 388 | { |
1da177e4 | 389 | /* Get vendor name */ |
4a148513 HH |
390 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
391 | (unsigned int *)&c->x86_vendor_id[0], | |
392 | (unsigned int *)&c->x86_vendor_id[8], | |
393 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 394 | |
1da177e4 | 395 | c->x86 = 4; |
9d31d35b | 396 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
397 | if (c->cpuid_level >= 0x00000001) { |
398 | u32 junk, tfms, cap0, misc; | |
399 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
9d31d35b YL |
400 | c->x86 = (tfms >> 8) & 0xf; |
401 | c->x86_model = (tfms >> 4) & 0xf; | |
402 | c->x86_mask = tfms & 0xf; | |
f5f786d0 | 403 | if (c->x86 == 0xf) |
1da177e4 | 404 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 405 | if (c->x86 >= 0x6) |
9d31d35b | 406 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
d4387bd3 | 407 | if (cap0 & (1<<19)) { |
d4387bd3 | 408 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 409 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 410 | } |
1da177e4 | 411 | } |
1da177e4 | 412 | } |
3da99c97 YL |
413 | |
414 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
093af8d7 YL |
415 | { |
416 | u32 tfms, xlvl; | |
3da99c97 | 417 | u32 ebx; |
093af8d7 | 418 | |
3da99c97 YL |
419 | /* Intel-defined flags: level 0x00000001 */ |
420 | if (c->cpuid_level >= 0x00000001) { | |
421 | u32 capability, excap; | |
422 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
423 | c->x86_capability[0] = capability; | |
424 | c->x86_capability[4] = excap; | |
425 | } | |
093af8d7 | 426 | |
3da99c97 YL |
427 | /* AMD-defined flags: level 0x80000001 */ |
428 | xlvl = cpuid_eax(0x80000000); | |
429 | c->extended_cpuid_level = xlvl; | |
430 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
431 | if (xlvl >= 0x80000001) { | |
432 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
433 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 434 | } |
093af8d7 | 435 | } |
093af8d7 | 436 | } |
34048c9e PC |
437 | /* |
438 | * Do minimum CPU detection early. | |
439 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
440 | * cache alignment. | |
441 | * The others are not touched to avoid unwanted side effects. | |
442 | * | |
443 | * WARNING: this function is only called on the BP. Don't add code here | |
444 | * that is supposed to run on all CPUs. | |
445 | */ | |
3da99c97 | 446 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 447 | { |
d4387bd3 | 448 | c->x86_clflush_size = 32; |
0a488a53 | 449 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 RR |
450 | |
451 | if (!have_cpuid_p()) | |
452 | return; | |
453 | ||
3da99c97 YL |
454 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
455 | ||
0a488a53 YL |
456 | c->extended_cpuid_level = 0; |
457 | ||
d7cd5611 RR |
458 | cpu_detect(c); |
459 | ||
3da99c97 | 460 | get_cpu_vendor(c); |
2b16a235 | 461 | |
3da99c97 | 462 | get_cpu_cap(c); |
2b16a235 | 463 | |
10a434fc YL |
464 | if (this_cpu->c_early_init) |
465 | this_cpu->c_early_init(c); | |
093af8d7 | 466 | |
3da99c97 | 467 | validate_pat_support(c); |
d7cd5611 RR |
468 | } |
469 | ||
9d31d35b YL |
470 | void __init early_cpu_init(void) |
471 | { | |
10a434fc YL |
472 | struct cpu_dev **cdev; |
473 | int count = 0; | |
474 | ||
475 | printk("KERNEL supported cpus:\n"); | |
476 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { | |
477 | struct cpu_dev *cpudev = *cdev; | |
478 | unsigned int j; | |
9d31d35b | 479 | |
10a434fc YL |
480 | if (count >= X86_VENDOR_NUM) |
481 | break; | |
482 | cpu_devs[count] = cpudev; | |
483 | count++; | |
484 | ||
485 | for (j = 0; j < 2; j++) { | |
486 | if (!cpudev->c_ident[j]) | |
487 | continue; | |
488 | printk(" %s %s\n", cpudev->c_vendor, | |
489 | cpudev->c_ident[j]); | |
490 | } | |
491 | } | |
9d31d35b | 492 | |
9d31d35b | 493 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 RR |
494 | } |
495 | ||
7e00df58 PA |
496 | /* |
497 | * The NOPL instruction is supposed to exist on all CPUs with | |
498 | * family >= 6, unfortunately, that's not true in practice because | |
499 | * of early VIA chips and (more importantly) broken virtualizers that | |
500 | * are not easy to detect. Hence, probe for it based on first | |
501 | * principles. | |
502 | */ | |
503 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
504 | { | |
505 | const u32 nopl_signature = 0x888c53b1; /* Random number */ | |
506 | u32 has_nopl = nopl_signature; | |
507 | ||
508 | clear_cpu_cap(c, X86_FEATURE_NOPL); | |
509 | if (c->x86 >= 6) { | |
510 | asm volatile("\n" | |
511 | "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */ | |
512 | "2:\n" | |
513 | " .section .fixup,\"ax\"\n" | |
514 | "3: xor %0,%0\n" | |
515 | " jmp 2b\n" | |
516 | " .previous\n" | |
517 | _ASM_EXTABLE(1b,3b) | |
518 | : "+a" (has_nopl)); | |
519 | ||
520 | if (has_nopl == nopl_signature) | |
521 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
522 | } | |
523 | } | |
524 | ||
34048c9e | 525 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 526 | { |
3da99c97 YL |
527 | if (!have_cpuid_p()) |
528 | return; | |
1da177e4 | 529 | |
3da99c97 | 530 | c->extended_cpuid_level = 0; |
1d67953f | 531 | |
3da99c97 | 532 | cpu_detect(c); |
1da177e4 | 533 | |
3da99c97 | 534 | get_cpu_vendor(c); |
1da177e4 | 535 | |
3da99c97 | 536 | get_cpu_cap(c); |
1da177e4 | 537 | |
3da99c97 YL |
538 | if (c->cpuid_level >= 0x00000001) { |
539 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
96c52749 | 540 | #ifdef CONFIG_X86_HT |
3da99c97 YL |
541 | c->apicid = phys_pkg_id(c->initial_apicid, 0); |
542 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 543 | #else |
3da99c97 | 544 | c->apicid = c->initial_apicid; |
1e9f28fa | 545 | #endif |
3da99c97 | 546 | } |
1da177e4 | 547 | |
3da99c97 YL |
548 | if (c->extended_cpuid_level >= 0x80000004) |
549 | get_model_name(c); /* Default name */ | |
1da177e4 | 550 | |
3da99c97 YL |
551 | init_scattered_cpuid_features(c); |
552 | detect_nopl(c); | |
1da177e4 | 553 | } |
1da177e4 LT |
554 | |
555 | /* | |
556 | * This does the hard work of actually picking apart the CPU stuff... | |
557 | */ | |
9a250347 | 558 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
559 | { |
560 | int i; | |
561 | ||
562 | c->loops_per_jiffy = loops_per_jiffy; | |
563 | c->x86_cache_size = -1; | |
564 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
565 | c->cpuid_level = -1; /* CPUID not detected */ | |
566 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ | |
567 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
568 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 569 | c->x86_max_cores = 1; |
770d132f | 570 | c->x86_clflush_size = 32; |
1da177e4 LT |
571 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
572 | ||
573 | if (!have_cpuid_p()) { | |
34048c9e PC |
574 | /* |
575 | * First of all, decide if this is a 486 or higher | |
576 | * It's a 486 if we can modify the AC flag | |
577 | */ | |
578 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
1da177e4 LT |
579 | c->x86 = 4; |
580 | else | |
581 | c->x86 = 3; | |
582 | } | |
583 | ||
584 | generic_identify(c); | |
585 | ||
3898534d | 586 | if (this_cpu->c_identify) |
1da177e4 LT |
587 | this_cpu->c_identify(c); |
588 | ||
1da177e4 LT |
589 | /* |
590 | * Vendor-specific initialization. In this section we | |
591 | * canonicalize the feature flags, meaning if there are | |
592 | * features a certain CPU supports which CPUID doesn't | |
593 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
594 | * we handle them here. | |
595 | * | |
596 | * At the end of this section, c->x86_capability better | |
597 | * indicate the features this CPU genuinely supports! | |
598 | */ | |
599 | if (this_cpu->c_init) | |
600 | this_cpu->c_init(c); | |
601 | ||
602 | /* Disable the PN if appropriate */ | |
603 | squash_the_stupid_serial_number(c); | |
604 | ||
605 | /* | |
606 | * The vendor-specific functions might have changed features. Now | |
607 | * we do "generic changes." | |
608 | */ | |
609 | ||
1da177e4 | 610 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 611 | if (!c->x86_model_id[0]) { |
1da177e4 LT |
612 | char *p; |
613 | p = table_lookup_model(c); | |
34048c9e | 614 | if (p) |
1da177e4 LT |
615 | strcpy(c->x86_model_id, p); |
616 | else | |
617 | /* Last resort... */ | |
618 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 619 | c->x86, c->x86_model); |
1da177e4 LT |
620 | } |
621 | ||
1da177e4 LT |
622 | /* |
623 | * On SMP, boot_cpu_data holds the common feature set between | |
624 | * all CPUs; so make sure that we indicate which features are | |
625 | * common between the CPUs. The first time this routine gets | |
626 | * executed, c == &boot_cpu_data. | |
627 | */ | |
34048c9e | 628 | if (c != &boot_cpu_data) { |
1da177e4 | 629 | /* AND the already accumulated flags with these */ |
9d31d35b | 630 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
631 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
632 | } | |
633 | ||
7d851c8d AK |
634 | /* Clear all flags overriden by options */ |
635 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 636 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 637 | |
1da177e4 | 638 | /* Init Machine Check Exception if available. */ |
1da177e4 | 639 | mcheck_init(c); |
30d432df AK |
640 | |
641 | select_idle_routine(c); | |
a6c4e076 | 642 | } |
31ab269a | 643 | |
a6c4e076 JF |
644 | void __init identify_boot_cpu(void) |
645 | { | |
646 | identify_cpu(&boot_cpu_data); | |
647 | sysenter_setup(); | |
6fe940d6 | 648 | enable_sep_cpu(); |
a6c4e076 | 649 | } |
3b520b23 | 650 | |
a6c4e076 JF |
651 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
652 | { | |
653 | BUG_ON(c == &boot_cpu_data); | |
654 | identify_cpu(c); | |
655 | enable_sep_cpu(); | |
656 | mtrr_ap_init(); | |
1da177e4 LT |
657 | } |
658 | ||
a0854a46 YL |
659 | struct msr_range { |
660 | unsigned min; | |
661 | unsigned max; | |
662 | }; | |
1da177e4 | 663 | |
a0854a46 YL |
664 | static struct msr_range msr_range_array[] __cpuinitdata = { |
665 | { 0x00000000, 0x00000418}, | |
666 | { 0xc0000000, 0xc000040b}, | |
667 | { 0xc0010000, 0xc0010142}, | |
668 | { 0xc0011000, 0xc001103b}, | |
669 | }; | |
1da177e4 | 670 | |
a0854a46 YL |
671 | static void __cpuinit print_cpu_msr(void) |
672 | { | |
673 | unsigned index; | |
674 | u64 val; | |
675 | int i; | |
676 | unsigned index_min, index_max; | |
677 | ||
678 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
679 | index_min = msr_range_array[i].min; | |
680 | index_max = msr_range_array[i].max; | |
681 | for (index = index_min; index < index_max; index++) { | |
682 | if (rdmsrl_amd_safe(index, &val)) | |
683 | continue; | |
684 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 685 | } |
a0854a46 YL |
686 | } |
687 | } | |
94605eff | 688 | |
a0854a46 YL |
689 | static int show_msr __cpuinitdata; |
690 | static __init int setup_show_msr(char *arg) | |
691 | { | |
692 | int num; | |
3dd9d514 | 693 | |
a0854a46 | 694 | get_option(&arg, &num); |
3dd9d514 | 695 | |
a0854a46 YL |
696 | if (num > 0) |
697 | show_msr = num; | |
698 | return 1; | |
1da177e4 | 699 | } |
a0854a46 | 700 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 701 | |
191679fd AK |
702 | static __init int setup_noclflush(char *arg) |
703 | { | |
704 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
705 | return 1; | |
706 | } | |
707 | __setup("noclflush", setup_noclflush); | |
708 | ||
3bc9b76b | 709 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
710 | { |
711 | char *vendor = NULL; | |
712 | ||
713 | if (c->x86_vendor < X86_VENDOR_NUM) | |
714 | vendor = this_cpu->c_vendor; | |
715 | else if (c->cpuid_level >= 0) | |
716 | vendor = c->x86_vendor_id; | |
717 | ||
718 | if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor))) | |
9d31d35b | 719 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 720 | |
9d31d35b YL |
721 | if (c->x86_model_id[0]) |
722 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 723 | else |
9d31d35b | 724 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 725 | |
34048c9e | 726 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 727 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 728 | else |
9d31d35b | 729 | printk(KERN_CONT "\n"); |
a0854a46 YL |
730 | |
731 | #ifdef CONFIG_SMP | |
732 | if (c->cpu_index < show_msr) | |
733 | print_cpu_msr(); | |
734 | #else | |
735 | if (show_msr) | |
736 | print_cpu_msr(); | |
737 | #endif | |
1da177e4 LT |
738 | } |
739 | ||
ac72e788 AK |
740 | static __init int setup_disablecpuid(char *arg) |
741 | { | |
742 | int bit; | |
743 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
744 | setup_clear_cpu_cap(bit); | |
745 | else | |
746 | return 0; | |
747 | return 1; | |
748 | } | |
749 | __setup("clearcpuid=", setup_disablecpuid); | |
750 | ||
3bc9b76b | 751 | cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; |
1da177e4 | 752 | |
d5494d4f YL |
753 | #ifdef CONFIG_X86_64 |
754 | struct x8664_pda **_cpu_pda __read_mostly; | |
755 | EXPORT_SYMBOL(_cpu_pda); | |
756 | ||
757 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; | |
758 | ||
759 | char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss; | |
760 | ||
761 | unsigned long __supported_pte_mask __read_mostly = ~0UL; | |
762 | EXPORT_SYMBOL_GPL(__supported_pte_mask); | |
763 | ||
764 | static int do_not_nx __cpuinitdata; | |
765 | ||
766 | /* noexec=on|off | |
767 | Control non executable mappings for 64bit processes. | |
768 | ||
769 | on Enable(default) | |
770 | off Disable | |
771 | */ | |
772 | static int __init nonx_setup(char *str) | |
773 | { | |
774 | if (!str) | |
775 | return -EINVAL; | |
776 | if (!strncmp(str, "on", 2)) { | |
777 | __supported_pte_mask |= _PAGE_NX; | |
778 | do_not_nx = 0; | |
779 | } else if (!strncmp(str, "off", 3)) { | |
780 | do_not_nx = 1; | |
781 | __supported_pte_mask &= ~_PAGE_NX; | |
782 | } | |
783 | return 0; | |
784 | } | |
785 | early_param("noexec", nonx_setup); | |
786 | ||
787 | int force_personality32; | |
788 | ||
789 | /* noexec32=on|off | |
790 | Control non executable heap for 32bit processes. | |
791 | To control the stack too use noexec=off | |
792 | ||
793 | on PROT_READ does not imply PROT_EXEC for 32bit processes (default) | |
794 | off PROT_READ implies PROT_EXEC | |
795 | */ | |
796 | static int __init nonx32_setup(char *str) | |
797 | { | |
798 | if (!strcmp(str, "on")) | |
799 | force_personality32 &= ~READ_IMPLIES_EXEC; | |
800 | else if (!strcmp(str, "off")) | |
801 | force_personality32 |= READ_IMPLIES_EXEC; | |
802 | return 1; | |
803 | } | |
804 | __setup("noexec32=", nonx32_setup); | |
805 | ||
806 | void pda_init(int cpu) | |
807 | { | |
808 | struct x8664_pda *pda = cpu_pda(cpu); | |
809 | ||
810 | /* Setup up data that may be needed in __get_free_pages early */ | |
811 | loadsegment(fs, 0); | |
812 | loadsegment(gs, 0); | |
813 | /* Memory clobbers used to order PDA accessed */ | |
814 | mb(); | |
815 | wrmsrl(MSR_GS_BASE, pda); | |
816 | mb(); | |
817 | ||
818 | pda->cpunumber = cpu; | |
819 | pda->irqcount = -1; | |
820 | pda->kernelstack = (unsigned long)stack_thread_info() - | |
821 | PDA_STACKOFFSET + THREAD_SIZE; | |
822 | pda->active_mm = &init_mm; | |
823 | pda->mmu_state = 0; | |
824 | ||
825 | if (cpu == 0) { | |
826 | /* others are initialized in smpboot.c */ | |
827 | pda->pcurrent = &init_task; | |
828 | pda->irqstackptr = boot_cpu_stack; | |
829 | pda->irqstackptr += IRQSTACKSIZE - 64; | |
830 | } else { | |
831 | if (!pda->irqstackptr) { | |
832 | pda->irqstackptr = (char *) | |
833 | __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER); | |
834 | if (!pda->irqstackptr) | |
835 | panic("cannot allocate irqstack for cpu %d", | |
836 | cpu); | |
837 | pda->irqstackptr += IRQSTACKSIZE - 64; | |
838 | } | |
839 | ||
840 | if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE) | |
841 | pda->nodenumber = cpu_to_node(cpu); | |
842 | } | |
843 | } | |
844 | ||
845 | char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + | |
846 | DEBUG_STKSZ] __page_aligned_bss; | |
847 | ||
848 | extern asmlinkage void ignore_sysret(void); | |
849 | ||
850 | /* May not be marked __init: used by software suspend */ | |
851 | void syscall_init(void) | |
852 | { | |
853 | /* | |
854 | * LSTAR and STAR live in a bit strange symbiosis. | |
855 | * They both write to the same internal register. STAR allows to | |
856 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
857 | */ | |
858 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
859 | wrmsrl(MSR_LSTAR, system_call); | |
860 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
861 | ||
862 | #ifdef CONFIG_IA32_EMULATION | |
863 | syscall32_cpu_init(); | |
864 | #endif | |
865 | ||
866 | /* Flags to clear on syscall */ | |
867 | wrmsrl(MSR_SYSCALL_MASK, | |
868 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
869 | } | |
870 | ||
871 | void __cpuinit check_efer(void) | |
872 | { | |
873 | unsigned long efer; | |
874 | ||
875 | rdmsrl(MSR_EFER, efer); | |
876 | if (!(efer & EFER_NX) || do_not_nx) | |
877 | __supported_pte_mask &= ~_PAGE_NX; | |
878 | } | |
879 | ||
880 | unsigned long kernel_eflags; | |
881 | ||
882 | /* | |
883 | * Copies of the original ist values from the tss are only accessed during | |
884 | * debugging, no special alignment required. | |
885 | */ | |
886 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
887 | ||
888 | #else | |
889 | ||
7c3576d2 | 890 | /* Make sure %fs is initialized properly in idle threads */ |
6b2fb3c6 | 891 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
892 | { |
893 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 894 | regs->fs = __KERNEL_PERCPU; |
f95d47ca JF |
895 | return regs; |
896 | } | |
d5494d4f | 897 | #endif |
f95d47ca | 898 | |
d2cbcc49 RR |
899 | /* |
900 | * cpu_init() initializes state that is per-CPU. Some data is already | |
901 | * initialized (naturally) in the bootstrap process, such as the GDT | |
902 | * and IDT. We reload them nevertheless, this function acts as a | |
903 | * 'CPU state barrier', nothing should get across. | |
904 | */ | |
905 | void __cpuinit cpu_init(void) | |
9ee79a3d | 906 | { |
d2cbcc49 RR |
907 | int cpu = smp_processor_id(); |
908 | struct task_struct *curr = current; | |
34048c9e | 909 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 910 | struct thread_struct *thread = &curr->thread; |
62111195 JF |
911 | |
912 | if (cpu_test_and_set(cpu, cpu_initialized)) { | |
913 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); | |
914 | for (;;) local_irq_enable(); | |
915 | } | |
916 | ||
917 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
918 | ||
919 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
920 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 921 | |
4d37e7e3 | 922 | load_idt(&idt_descr); |
c5413fbe | 923 | switch_to_new_gdt(); |
1da177e4 | 924 | |
1da177e4 LT |
925 | /* |
926 | * Set up and load the per-CPU TSS and LDT | |
927 | */ | |
928 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
929 | curr->active_mm = &init_mm; |
930 | if (curr->mm) | |
931 | BUG(); | |
932 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 | 933 | |
faca6227 | 934 | load_sp0(t, thread); |
34048c9e | 935 | set_tss_desc(cpu, t); |
1da177e4 LT |
936 | load_TR_desc(); |
937 | load_LDT(&init_mm.context); | |
938 | ||
22c4e308 | 939 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
940 | /* Set up doublefault TSS pointer in the GDT */ |
941 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 942 | #endif |
1da177e4 | 943 | |
464d1a78 JF |
944 | /* Clear %gs. */ |
945 | asm volatile ("mov %0, %%gs" : : "r" (0)); | |
1da177e4 LT |
946 | |
947 | /* Clear all 6 debug registers: */ | |
4bb0d3ec ZA |
948 | set_debugreg(0, 0); |
949 | set_debugreg(0, 1); | |
950 | set_debugreg(0, 2); | |
951 | set_debugreg(0, 3); | |
952 | set_debugreg(0, 6); | |
953 | set_debugreg(0, 7); | |
1da177e4 LT |
954 | |
955 | /* | |
956 | * Force FPU initialization: | |
957 | */ | |
b359e8a4 SS |
958 | if (cpu_has_xsave) |
959 | current_thread_info()->status = TS_XSAVE; | |
960 | else | |
961 | current_thread_info()->status = 0; | |
1da177e4 LT |
962 | clear_used_math(); |
963 | mxcsr_feature_mask_init(); | |
dc1e35c6 SS |
964 | |
965 | /* | |
966 | * Boot processor to setup the FP and extended state context info. | |
967 | */ | |
968 | if (!smp_processor_id()) | |
969 | init_thread_xstate(); | |
970 | ||
971 | xsave_init(); | |
1da177e4 | 972 | } |
e1367daf LS |
973 | |
974 | #ifdef CONFIG_HOTPLUG_CPU | |
3bc9b76b | 975 | void __cpuinit cpu_uninit(void) |
e1367daf LS |
976 | { |
977 | int cpu = raw_smp_processor_id(); | |
978 | cpu_clear(cpu, cpu_initialized); | |
979 | ||
980 | /* lazy TLB state */ | |
981 | per_cpu(cpu_tlbstate, cpu).state = 0; | |
982 | per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm; | |
983 | } | |
984 | #endif |