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Commit | Line | Data |
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f0fc4aff | 1 | #include <linux/bootmem.h> |
9766cdbc | 2 | #include <linux/linkage.h> |
f0fc4aff | 3 | #include <linux/bitops.h> |
9766cdbc | 4 | #include <linux/kernel.h> |
f0fc4aff | 5 | #include <linux/module.h> |
9766cdbc JSR |
6 | #include <linux/percpu.h> |
7 | #include <linux/string.h> | |
1da177e4 | 8 | #include <linux/delay.h> |
9766cdbc JSR |
9 | #include <linux/sched.h> |
10 | #include <linux/init.h> | |
11 | #include <linux/kgdb.h> | |
1da177e4 | 12 | #include <linux/smp.h> |
9766cdbc JSR |
13 | #include <linux/io.h> |
14 | ||
15 | #include <asm/stackprotector.h> | |
1da177e4 | 16 | #include <asm/mmu_context.h> |
9766cdbc JSR |
17 | #include <asm/hypervisor.h> |
18 | #include <asm/processor.h> | |
19 | #include <asm/sections.h> | |
0f3fa48a | 20 | #include <asm/topology.h> |
9766cdbc JSR |
21 | #include <asm/cpumask.h> |
22 | #include <asm/pgtable.h> | |
23 | #include <asm/atomic.h> | |
24 | #include <asm/proto.h> | |
25 | #include <asm/setup.h> | |
26 | #include <asm/apic.h> | |
27 | #include <asm/desc.h> | |
28 | #include <asm/i387.h> | |
27b07da7 | 29 | #include <asm/mtrr.h> |
9766cdbc JSR |
30 | #include <asm/numa.h> |
31 | #include <asm/asm.h> | |
32 | #include <asm/cpu.h> | |
a03a3e28 | 33 | #include <asm/mce.h> |
9766cdbc | 34 | #include <asm/msr.h> |
8d4a4300 | 35 | #include <asm/pat.h> |
b342797c | 36 | #include <asm/smp.h> |
e641f5f5 IM |
37 | |
38 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 39 | #include <asm/uv/uv.h> |
1da177e4 LT |
40 | #endif |
41 | ||
42 | #include "cpu.h" | |
43 | ||
c2d1cec1 | 44 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 45 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
46 | cpumask_var_t cpu_callout_mask; |
47 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
48 | |
49 | /* representing cpus for which sibling maps can be computed */ | |
50 | cpumask_var_t cpu_sibling_setup_mask; | |
51 | ||
2f2f52ba | 52 | /* correctly size the local cpu masks */ |
4369f1fb | 53 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
54 | { |
55 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
56 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
57 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
58 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
59 | } | |
60 | ||
02dde8b4 | 61 | static const struct cpu_dev *this_cpu __cpuinitdata; |
0a488a53 | 62 | |
06deef89 | 63 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 64 | #ifdef CONFIG_X86_64 |
06deef89 BG |
65 | /* |
66 | * We need valid kernel segments for data and code in long mode too | |
67 | * IRET will check the segment types kkeil 2000/10/28 | |
68 | * Also sysret mandates a special GDT layout | |
69 | * | |
9766cdbc | 70 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
71 | * Hopefully nobody expects them at a fixed place (Wine?) |
72 | */ | |
0f3fa48a IM |
73 | [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, |
74 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, | |
75 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, | |
76 | [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, | |
77 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, | |
78 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, | |
950ad7ff | 79 | #else |
0f3fa48a IM |
80 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
81 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
82 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
83 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
84 | /* |
85 | * Segments used for calling PnP BIOS have byte granularity. | |
86 | * They code segments and data segments have fixed 64k limits, | |
87 | * the transfer segment sizes are set at run time. | |
88 | */ | |
6842ef0e | 89 | /* 32-bit code */ |
0f3fa48a | 90 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, |
6842ef0e | 91 | /* 16-bit code */ |
0f3fa48a | 92 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, |
6842ef0e | 93 | /* 16-bit data */ |
0f3fa48a | 94 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, |
6842ef0e | 95 | /* 16-bit data */ |
0f3fa48a | 96 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, |
6842ef0e | 97 | /* 16-bit data */ |
0f3fa48a | 98 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, |
bf504672 RR |
99 | /* |
100 | * The APM segments have byte granularity and their bases | |
101 | * are set at run time. All have 64k limits. | |
102 | */ | |
6842ef0e | 103 | /* 32-bit code */ |
0f3fa48a | 104 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, |
bf504672 | 105 | /* 16-bit code */ |
0f3fa48a | 106 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
6842ef0e | 107 | /* data */ |
0f3fa48a | 108 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, |
bf504672 | 109 | |
0f3fa48a IM |
110 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
111 | [GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
60a5317f | 112 | GDT_STACK_CANARY_INIT |
950ad7ff | 113 | #endif |
06deef89 | 114 | } }; |
7a61d35d | 115 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 116 | |
ba51dced | 117 | #ifdef CONFIG_X86_32 |
3bc9b76b | 118 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 119 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 120 | |
0a488a53 YL |
121 | static int __init cachesize_setup(char *str) |
122 | { | |
123 | get_option(&str, &cachesize_override); | |
124 | return 1; | |
125 | } | |
126 | __setup("cachesize=", cachesize_setup); | |
127 | ||
0a488a53 YL |
128 | static int __init x86_fxsr_setup(char *s) |
129 | { | |
130 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
131 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
132 | return 1; | |
133 | } | |
134 | __setup("nofxsr", x86_fxsr_setup); | |
135 | ||
136 | static int __init x86_sep_setup(char *s) | |
137 | { | |
138 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
139 | return 1; | |
140 | } | |
141 | __setup("nosep", x86_sep_setup); | |
142 | ||
143 | /* Standard macro to see if a specific flag is changeable */ | |
144 | static inline int flag_is_changeable_p(u32 flag) | |
145 | { | |
146 | u32 f1, f2; | |
147 | ||
94f6bac1 KH |
148 | /* |
149 | * Cyrix and IDT cpus allow disabling of CPUID | |
150 | * so the code below may return different results | |
151 | * when it is executed before and after enabling | |
152 | * the CPUID. Add "volatile" to not allow gcc to | |
153 | * optimize the subsequent calls to this function. | |
154 | */ | |
0f3fa48a IM |
155 | asm volatile ("pushfl \n\t" |
156 | "pushfl \n\t" | |
157 | "popl %0 \n\t" | |
158 | "movl %0, %1 \n\t" | |
159 | "xorl %2, %0 \n\t" | |
160 | "pushl %0 \n\t" | |
161 | "popfl \n\t" | |
162 | "pushfl \n\t" | |
163 | "popl %0 \n\t" | |
164 | "popfl \n\t" | |
165 | ||
94f6bac1 KH |
166 | : "=&r" (f1), "=&r" (f2) |
167 | : "ir" (flag)); | |
0a488a53 YL |
168 | |
169 | return ((f1^f2) & flag) != 0; | |
170 | } | |
171 | ||
172 | /* Probe for the CPUID instruction */ | |
173 | static int __cpuinit have_cpuid_p(void) | |
174 | { | |
175 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
176 | } | |
177 | ||
178 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
179 | { | |
0f3fa48a IM |
180 | unsigned long lo, hi; |
181 | ||
182 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
183 | return; | |
184 | ||
185 | /* Disable processor serial number: */ | |
186 | ||
187 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
188 | lo |= 0x200000; | |
189 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
190 | ||
191 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
192 | clear_cpu_cap(c, X86_FEATURE_PN); | |
193 | ||
194 | /* Disabling the serial number may affect the cpuid level */ | |
195 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
196 | } |
197 | ||
198 | static int __init x86_serial_nr_setup(char *s) | |
199 | { | |
200 | disable_x86_serial_nr = 0; | |
201 | return 1; | |
202 | } | |
203 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 204 | #else |
102bbe3a YL |
205 | static inline int flag_is_changeable_p(u32 flag) |
206 | { | |
207 | return 1; | |
208 | } | |
ba51dced YL |
209 | /* Probe for the CPUID instruction */ |
210 | static inline int have_cpuid_p(void) | |
211 | { | |
212 | return 1; | |
213 | } | |
102bbe3a YL |
214 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
215 | { | |
216 | } | |
ba51dced | 217 | #endif |
0a488a53 | 218 | |
b38b0665 PA |
219 | /* |
220 | * Some CPU features depend on higher CPUID levels, which may not always | |
221 | * be available due to CPUID level capping or broken virtualization | |
222 | * software. Add those features to this table to auto-disable them. | |
223 | */ | |
224 | struct cpuid_dependent_feature { | |
225 | u32 feature; | |
226 | u32 level; | |
227 | }; | |
0f3fa48a | 228 | |
b38b0665 PA |
229 | static const struct cpuid_dependent_feature __cpuinitconst |
230 | cpuid_dependent_features[] = { | |
231 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
232 | { X86_FEATURE_DCA, 0x00000009 }, | |
233 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
234 | { 0, 0 } | |
235 | }; | |
236 | ||
237 | static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) | |
238 | { | |
239 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 240 | |
b38b0665 | 241 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
242 | |
243 | if (!cpu_has(c, df->feature)) | |
244 | continue; | |
b38b0665 PA |
245 | /* |
246 | * Note: cpuid_level is set to -1 if unavailable, but | |
247 | * extended_extended_level is set to 0 if unavailable | |
248 | * and the legitimate extended levels are all negative | |
249 | * when signed; hence the weird messing around with | |
250 | * signs here... | |
251 | */ | |
0f3fa48a | 252 | if (!((s32)df->level < 0 ? |
f6db44df | 253 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
254 | (s32)df->level > (s32)c->cpuid_level)) |
255 | continue; | |
256 | ||
257 | clear_cpu_cap(c, df->feature); | |
258 | if (!warn) | |
259 | continue; | |
260 | ||
261 | printk(KERN_WARNING | |
262 | "CPU: CPU feature %s disabled, no CPUID level 0x%x\n", | |
263 | x86_cap_flags[df->feature], df->level); | |
b38b0665 | 264 | } |
f6db44df | 265 | } |
b38b0665 | 266 | |
102bbe3a YL |
267 | /* |
268 | * Naming convention should be: <Name> [(<Codename>)] | |
269 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
270 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
271 | * isn't used | |
102bbe3a YL |
272 | */ |
273 | ||
274 | /* Look up CPU names by table lookup. */ | |
02dde8b4 | 275 | static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 276 | { |
02dde8b4 | 277 | const struct cpu_model_info *info; |
102bbe3a YL |
278 | |
279 | if (c->x86_model >= 16) | |
280 | return NULL; /* Range check */ | |
281 | ||
282 | if (!this_cpu) | |
283 | return NULL; | |
284 | ||
285 | info = this_cpu->c_models; | |
286 | ||
287 | while (info && info->family) { | |
288 | if (info->family == c->x86) | |
289 | return info->model_names[c->x86_model]; | |
290 | info++; | |
291 | } | |
292 | return NULL; /* Not found */ | |
293 | } | |
294 | ||
7d851c8d AK |
295 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
296 | ||
11e3a840 JF |
297 | void load_percpu_segment(int cpu) |
298 | { | |
299 | #ifdef CONFIG_X86_32 | |
300 | loadsegment(fs, __KERNEL_PERCPU); | |
301 | #else | |
302 | loadsegment(gs, 0); | |
303 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
304 | #endif | |
60a5317f | 305 | load_stack_canary_segment(); |
11e3a840 JF |
306 | } |
307 | ||
0f3fa48a IM |
308 | /* |
309 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
310 | * it's on the real one. | |
311 | */ | |
552be871 | 312 | void switch_to_new_gdt(int cpu) |
9d31d35b YL |
313 | { |
314 | struct desc_ptr gdt_descr; | |
315 | ||
2697fbd5 | 316 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
317 | gdt_descr.size = GDT_SIZE - 1; |
318 | load_gdt(&gdt_descr); | |
2697fbd5 | 319 | /* Reload the per-cpu base */ |
11e3a840 JF |
320 | |
321 | load_percpu_segment(cpu); | |
9d31d35b YL |
322 | } |
323 | ||
02dde8b4 | 324 | static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 325 | |
34048c9e | 326 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
1da177e4 | 327 | { |
b9e67f00 YL |
328 | #ifdef CONFIG_X86_64 |
329 | display_cacheinfo(c); | |
330 | #else | |
1da177e4 LT |
331 | /* Not much we can do here... */ |
332 | /* Check if at least it has cpuid */ | |
333 | if (c->cpuid_level == -1) { | |
334 | /* No cpuid. It must be an ancient CPU */ | |
335 | if (c->x86 == 4) | |
336 | strcpy(c->x86_model_id, "486"); | |
337 | else if (c->x86 == 3) | |
338 | strcpy(c->x86_model_id, "386"); | |
339 | } | |
b9e67f00 | 340 | #endif |
1da177e4 LT |
341 | } |
342 | ||
02dde8b4 | 343 | static const struct cpu_dev __cpuinitconst default_cpu = { |
1da177e4 | 344 | .c_init = default_init, |
fe38d855 | 345 | .c_vendor = "Unknown", |
10a434fc | 346 | .c_x86_vendor = X86_VENDOR_UNKNOWN, |
1da177e4 | 347 | }; |
1da177e4 | 348 | |
1b05d60d | 349 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
350 | { |
351 | unsigned int *v; | |
352 | char *p, *q; | |
353 | ||
3da99c97 | 354 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 355 | return; |
1da177e4 | 356 | |
0f3fa48a | 357 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
358 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
359 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
360 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
361 | c->x86_model_id[48] = 0; | |
362 | ||
0f3fa48a IM |
363 | /* |
364 | * Intel chips right-justify this string for some dumb reason; | |
365 | * undo that brain damage: | |
366 | */ | |
1da177e4 | 367 | p = q = &c->x86_model_id[0]; |
34048c9e | 368 | while (*p == ' ') |
9766cdbc | 369 | p++; |
34048c9e | 370 | if (p != q) { |
9766cdbc JSR |
371 | while (*p) |
372 | *q++ = *p++; | |
373 | while (q <= &c->x86_model_id[48]) | |
374 | *q++ = '\0'; /* Zero-pad the rest */ | |
1da177e4 | 375 | } |
1da177e4 LT |
376 | } |
377 | ||
3bc9b76b | 378 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 | 379 | { |
9d31d35b | 380 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 381 | |
3da99c97 | 382 | n = c->extended_cpuid_level; |
1da177e4 LT |
383 | |
384 | if (n >= 0x80000005) { | |
9d31d35b | 385 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 386 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
9d31d35b YL |
387 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); |
388 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
140fc727 YL |
389 | #ifdef CONFIG_X86_64 |
390 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
391 | c->x86_tlbsize = 0; | |
392 | #endif | |
1da177e4 LT |
393 | } |
394 | ||
395 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
396 | return; | |
397 | ||
0a488a53 | 398 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 399 | l2size = ecx >> 16; |
34048c9e | 400 | |
140fc727 YL |
401 | #ifdef CONFIG_X86_64 |
402 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
403 | #else | |
1da177e4 LT |
404 | /* do processor-specific cache resizing */ |
405 | if (this_cpu->c_size_cache) | |
34048c9e | 406 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
407 | |
408 | /* Allow user to override all this if necessary. */ | |
409 | if (cachesize_override != -1) | |
410 | l2size = cachesize_override; | |
411 | ||
34048c9e | 412 | if (l2size == 0) |
1da177e4 | 413 | return; /* Again, no L2 cache is possible */ |
140fc727 | 414 | #endif |
1da177e4 LT |
415 | |
416 | c->x86_cache_size = l2size; | |
417 | ||
418 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
0a488a53 | 419 | l2size, ecx & 0xFF); |
1da177e4 LT |
420 | } |
421 | ||
9d31d35b | 422 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 423 | { |
97e4db7c | 424 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
425 | u32 eax, ebx, ecx, edx; |
426 | int index_msb, core_bits; | |
1da177e4 | 427 | |
0a488a53 | 428 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 429 | return; |
1da177e4 | 430 | |
0a488a53 YL |
431 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
432 | goto out; | |
1da177e4 | 433 | |
1cd78776 YL |
434 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
435 | return; | |
1da177e4 | 436 | |
0a488a53 | 437 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 438 | |
9d31d35b YL |
439 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
440 | ||
441 | if (smp_num_siblings == 1) { | |
442 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
0f3fa48a IM |
443 | goto out; |
444 | } | |
9d31d35b | 445 | |
0f3fa48a IM |
446 | if (smp_num_siblings <= 1) |
447 | goto out; | |
9d31d35b | 448 | |
0f3fa48a IM |
449 | if (smp_num_siblings > nr_cpu_ids) { |
450 | pr_warning("CPU: Unsupported number of siblings %d", | |
451 | smp_num_siblings); | |
452 | smp_num_siblings = 1; | |
453 | return; | |
454 | } | |
9d31d35b | 455 | |
0f3fa48a IM |
456 | index_msb = get_count_order(smp_num_siblings); |
457 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 458 | |
0f3fa48a | 459 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 460 | |
0f3fa48a | 461 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 462 | |
0f3fa48a | 463 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 464 | |
0f3fa48a IM |
465 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
466 | ((1 << core_bits) - 1); | |
1da177e4 | 467 | |
0a488a53 YL |
468 | out: |
469 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
470 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
471 | c->phys_proc_id); | |
472 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
473 | c->cpu_core_id); | |
9d31d35b | 474 | } |
9d31d35b | 475 | #endif |
97e4db7c | 476 | } |
1da177e4 | 477 | |
3da99c97 | 478 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
479 | { |
480 | char *v = c->x86_vendor_id; | |
fe38d855 | 481 | static int printed; |
0f3fa48a | 482 | int i; |
1da177e4 LT |
483 | |
484 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
485 | if (!cpu_devs[i]) |
486 | break; | |
487 | ||
488 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
489 | (cpu_devs[i]->c_ident[1] && | |
490 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 491 | |
10a434fc YL |
492 | this_cpu = cpu_devs[i]; |
493 | c->x86_vendor = this_cpu->c_x86_vendor; | |
494 | return; | |
1da177e4 LT |
495 | } |
496 | } | |
10a434fc | 497 | |
fe38d855 CE |
498 | if (!printed) { |
499 | printed++; | |
0f3fa48a IM |
500 | printk(KERN_ERR |
501 | "CPU: vendor_id '%s' unknown, using generic init.\n", v); | |
502 | ||
fe38d855 CE |
503 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); |
504 | } | |
10a434fc | 505 | |
fe38d855 CE |
506 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
507 | this_cpu = &default_cpu; | |
1da177e4 LT |
508 | } |
509 | ||
9d31d35b | 510 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 511 | { |
1da177e4 | 512 | /* Get vendor name */ |
4a148513 HH |
513 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
514 | (unsigned int *)&c->x86_vendor_id[0], | |
515 | (unsigned int *)&c->x86_vendor_id[8], | |
516 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 517 | |
1da177e4 | 518 | c->x86 = 4; |
9d31d35b | 519 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
520 | if (c->cpuid_level >= 0x00000001) { |
521 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 522 | |
1da177e4 | 523 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
9d31d35b YL |
524 | c->x86 = (tfms >> 8) & 0xf; |
525 | c->x86_model = (tfms >> 4) & 0xf; | |
526 | c->x86_mask = tfms & 0xf; | |
0f3fa48a | 527 | |
f5f786d0 | 528 | if (c->x86 == 0xf) |
1da177e4 | 529 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 530 | if (c->x86 >= 0x6) |
9d31d35b | 531 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
0f3fa48a | 532 | |
d4387bd3 | 533 | if (cap0 & (1<<19)) { |
d4387bd3 | 534 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 535 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 536 | } |
1da177e4 | 537 | } |
1da177e4 | 538 | } |
3da99c97 YL |
539 | |
540 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
093af8d7 YL |
541 | { |
542 | u32 tfms, xlvl; | |
3da99c97 | 543 | u32 ebx; |
093af8d7 | 544 | |
3da99c97 YL |
545 | /* Intel-defined flags: level 0x00000001 */ |
546 | if (c->cpuid_level >= 0x00000001) { | |
547 | u32 capability, excap; | |
0f3fa48a | 548 | |
3da99c97 YL |
549 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); |
550 | c->x86_capability[0] = capability; | |
551 | c->x86_capability[4] = excap; | |
552 | } | |
093af8d7 | 553 | |
3da99c97 YL |
554 | /* AMD-defined flags: level 0x80000001 */ |
555 | xlvl = cpuid_eax(0x80000000); | |
556 | c->extended_cpuid_level = xlvl; | |
0f3fa48a | 557 | |
3da99c97 YL |
558 | if ((xlvl & 0xffff0000) == 0x80000000) { |
559 | if (xlvl >= 0x80000001) { | |
560 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
561 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 562 | } |
093af8d7 | 563 | } |
093af8d7 | 564 | |
5122c890 YL |
565 | if (c->extended_cpuid_level >= 0x80000008) { |
566 | u32 eax = cpuid_eax(0x80000008); | |
567 | ||
568 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
569 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 570 | } |
13c6c532 JB |
571 | #ifdef CONFIG_X86_32 |
572 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
573 | c->x86_phys_bits = 36; | |
5122c890 | 574 | #endif |
e3224234 YL |
575 | |
576 | if (c->extended_cpuid_level >= 0x80000007) | |
577 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 YL |
578 | |
579 | } | |
1da177e4 | 580 | |
aef93c8b YL |
581 | static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
582 | { | |
583 | #ifdef CONFIG_X86_32 | |
584 | int i; | |
585 | ||
586 | /* | |
587 | * First of all, decide if this is a 486 or higher | |
588 | * It's a 486 if we can modify the AC flag | |
589 | */ | |
590 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
591 | c->x86 = 4; | |
592 | else | |
593 | c->x86 = 3; | |
594 | ||
595 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
596 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
597 | c->x86_vendor_id[0] = 0; | |
598 | cpu_devs[i]->c_identify(c); | |
599 | if (c->x86_vendor_id[0]) { | |
600 | get_cpu_vendor(c); | |
601 | break; | |
602 | } | |
603 | } | |
604 | #endif | |
605 | } | |
606 | ||
34048c9e PC |
607 | /* |
608 | * Do minimum CPU detection early. | |
609 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
610 | * cache alignment. | |
611 | * The others are not touched to avoid unwanted side effects. | |
612 | * | |
613 | * WARNING: this function is only called on the BP. Don't add code here | |
614 | * that is supposed to run on all CPUs. | |
615 | */ | |
3da99c97 | 616 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 617 | { |
6627d242 YL |
618 | #ifdef CONFIG_X86_64 |
619 | c->x86_clflush_size = 64; | |
13c6c532 JB |
620 | c->x86_phys_bits = 36; |
621 | c->x86_virt_bits = 48; | |
6627d242 | 622 | #else |
d4387bd3 | 623 | c->x86_clflush_size = 32; |
13c6c532 JB |
624 | c->x86_phys_bits = 32; |
625 | c->x86_virt_bits = 32; | |
6627d242 | 626 | #endif |
0a488a53 | 627 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 628 | |
3da99c97 | 629 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 630 | c->extended_cpuid_level = 0; |
d7cd5611 | 631 | |
aef93c8b YL |
632 | if (!have_cpuid_p()) |
633 | identify_cpu_without_cpuid(c); | |
634 | ||
635 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
636 | if (!have_cpuid_p()) |
637 | return; | |
638 | ||
639 | cpu_detect(c); | |
640 | ||
3da99c97 | 641 | get_cpu_vendor(c); |
2b16a235 | 642 | |
3da99c97 | 643 | get_cpu_cap(c); |
12cf105c | 644 | |
10a434fc YL |
645 | if (this_cpu->c_early_init) |
646 | this_cpu->c_early_init(c); | |
093af8d7 | 647 | |
1c4acdb4 | 648 | #ifdef CONFIG_SMP |
bfcb4c1b | 649 | c->cpu_index = boot_cpu_id; |
1c4acdb4 | 650 | #endif |
b38b0665 | 651 | filter_cpuid_features(c, false); |
d7cd5611 RR |
652 | } |
653 | ||
9d31d35b YL |
654 | void __init early_cpu_init(void) |
655 | { | |
02dde8b4 | 656 | const struct cpu_dev *const *cdev; |
10a434fc YL |
657 | int count = 0; |
658 | ||
9766cdbc | 659 | printk(KERN_INFO "KERNEL supported cpus:\n"); |
10a434fc | 660 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 661 | const struct cpu_dev *cpudev = *cdev; |
10a434fc | 662 | unsigned int j; |
9d31d35b | 663 | |
10a434fc YL |
664 | if (count >= X86_VENDOR_NUM) |
665 | break; | |
666 | cpu_devs[count] = cpudev; | |
667 | count++; | |
668 | ||
669 | for (j = 0; j < 2; j++) { | |
670 | if (!cpudev->c_ident[j]) | |
671 | continue; | |
9766cdbc | 672 | printk(KERN_INFO " %s %s\n", cpudev->c_vendor, |
10a434fc YL |
673 | cpudev->c_ident[j]); |
674 | } | |
675 | } | |
9d31d35b | 676 | |
9d31d35b | 677 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 678 | } |
093af8d7 | 679 | |
b6734c35 PA |
680 | /* |
681 | * The NOPL instruction is supposed to exist on all CPUs with | |
ba0593bf | 682 | * family >= 6; unfortunately, that's not true in practice because |
b6734c35 | 683 | * of early VIA chips and (more importantly) broken virtualizers that |
ba0593bf PA |
684 | * are not easy to detect. In the latter case it doesn't even *fail* |
685 | * reliably, so probing for it doesn't even work. Disable it completely | |
686 | * unless we can find a reliable way to detect all the broken cases. | |
b6734c35 PA |
687 | */ |
688 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
689 | { | |
b6734c35 | 690 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
d7cd5611 RR |
691 | } |
692 | ||
34048c9e | 693 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 694 | { |
aef93c8b | 695 | c->extended_cpuid_level = 0; |
1da177e4 | 696 | |
3da99c97 | 697 | if (!have_cpuid_p()) |
aef93c8b | 698 | identify_cpu_without_cpuid(c); |
1d67953f | 699 | |
aef93c8b | 700 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 701 | if (!have_cpuid_p()) |
aef93c8b | 702 | return; |
1da177e4 | 703 | |
3da99c97 | 704 | cpu_detect(c); |
1da177e4 | 705 | |
3da99c97 | 706 | get_cpu_vendor(c); |
1da177e4 | 707 | |
3da99c97 | 708 | get_cpu_cap(c); |
1da177e4 | 709 | |
3da99c97 YL |
710 | if (c->cpuid_level >= 0x00000001) { |
711 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
712 | #ifdef CONFIG_X86_32 |
713 | # ifdef CONFIG_X86_HT | |
cb8cc442 | 714 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 715 | # else |
3da99c97 | 716 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
717 | # endif |
718 | #endif | |
1da177e4 | 719 | |
b89d3b3e YL |
720 | #ifdef CONFIG_X86_HT |
721 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 722 | #endif |
3da99c97 | 723 | } |
1da177e4 | 724 | |
1b05d60d | 725 | get_model_name(c); /* Default name */ |
1da177e4 | 726 | |
3da99c97 YL |
727 | init_scattered_cpuid_features(c); |
728 | detect_nopl(c); | |
1da177e4 | 729 | } |
1da177e4 LT |
730 | |
731 | /* | |
732 | * This does the hard work of actually picking apart the CPU stuff... | |
733 | */ | |
9a250347 | 734 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
735 | { |
736 | int i; | |
737 | ||
738 | c->loops_per_jiffy = loops_per_jiffy; | |
739 | c->x86_cache_size = -1; | |
740 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
741 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
742 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
743 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 744 | c->x86_max_cores = 1; |
102bbe3a | 745 | c->x86_coreid_bits = 0; |
11fdd252 | 746 | #ifdef CONFIG_X86_64 |
102bbe3a | 747 | c->x86_clflush_size = 64; |
13c6c532 JB |
748 | c->x86_phys_bits = 36; |
749 | c->x86_virt_bits = 48; | |
102bbe3a YL |
750 | #else |
751 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 752 | c->x86_clflush_size = 32; |
13c6c532 JB |
753 | c->x86_phys_bits = 32; |
754 | c->x86_virt_bits = 32; | |
102bbe3a YL |
755 | #endif |
756 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
757 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
758 | ||
1da177e4 LT |
759 | generic_identify(c); |
760 | ||
3898534d | 761 | if (this_cpu->c_identify) |
1da177e4 LT |
762 | this_cpu->c_identify(c); |
763 | ||
102bbe3a | 764 | #ifdef CONFIG_X86_64 |
cb8cc442 | 765 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
766 | #endif |
767 | ||
1da177e4 LT |
768 | /* |
769 | * Vendor-specific initialization. In this section we | |
770 | * canonicalize the feature flags, meaning if there are | |
771 | * features a certain CPU supports which CPUID doesn't | |
772 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
773 | * we handle them here. | |
774 | * | |
775 | * At the end of this section, c->x86_capability better | |
776 | * indicate the features this CPU genuinely supports! | |
777 | */ | |
778 | if (this_cpu->c_init) | |
779 | this_cpu->c_init(c); | |
780 | ||
781 | /* Disable the PN if appropriate */ | |
782 | squash_the_stupid_serial_number(c); | |
783 | ||
784 | /* | |
0f3fa48a IM |
785 | * The vendor-specific functions might have changed features. |
786 | * Now we do "generic changes." | |
1da177e4 LT |
787 | */ |
788 | ||
b38b0665 PA |
789 | /* Filter out anything that depends on CPUID levels we don't have */ |
790 | filter_cpuid_features(c, true); | |
791 | ||
1da177e4 | 792 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 793 | if (!c->x86_model_id[0]) { |
02dde8b4 | 794 | const char *p; |
1da177e4 | 795 | p = table_lookup_model(c); |
34048c9e | 796 | if (p) |
1da177e4 LT |
797 | strcpy(c->x86_model_id, p); |
798 | else | |
799 | /* Last resort... */ | |
800 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 801 | c->x86, c->x86_model); |
1da177e4 LT |
802 | } |
803 | ||
102bbe3a YL |
804 | #ifdef CONFIG_X86_64 |
805 | detect_ht(c); | |
806 | #endif | |
807 | ||
88b094fb | 808 | init_hypervisor(c); |
1da177e4 LT |
809 | /* |
810 | * On SMP, boot_cpu_data holds the common feature set between | |
811 | * all CPUs; so make sure that we indicate which features are | |
812 | * common between the CPUs. The first time this routine gets | |
813 | * executed, c == &boot_cpu_data. | |
814 | */ | |
34048c9e | 815 | if (c != &boot_cpu_data) { |
1da177e4 | 816 | /* AND the already accumulated flags with these */ |
9d31d35b | 817 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
818 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
819 | } | |
820 | ||
7d851c8d AK |
821 | /* Clear all flags overriden by options */ |
822 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 823 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 824 | |
102bbe3a | 825 | #ifdef CONFIG_X86_MCE |
1da177e4 | 826 | /* Init Machine Check Exception if available. */ |
1da177e4 | 827 | mcheck_init(c); |
102bbe3a | 828 | #endif |
30d432df AK |
829 | |
830 | select_idle_routine(c); | |
102bbe3a YL |
831 | |
832 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
833 | numa_add_cpu(smp_processor_id()); | |
834 | #endif | |
a6c4e076 | 835 | } |
31ab269a | 836 | |
e04d645f GC |
837 | #ifdef CONFIG_X86_64 |
838 | static void vgetcpu_set_mode(void) | |
839 | { | |
840 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
841 | vgetcpu_mode = VGETCPU_RDTSCP; | |
842 | else | |
843 | vgetcpu_mode = VGETCPU_LSL; | |
844 | } | |
845 | #endif | |
846 | ||
a6c4e076 JF |
847 | void __init identify_boot_cpu(void) |
848 | { | |
849 | identify_cpu(&boot_cpu_data); | |
30e1e6d1 | 850 | init_c1e_mask(); |
102bbe3a | 851 | #ifdef CONFIG_X86_32 |
a6c4e076 | 852 | sysenter_setup(); |
6fe940d6 | 853 | enable_sep_cpu(); |
e04d645f GC |
854 | #else |
855 | vgetcpu_set_mode(); | |
102bbe3a | 856 | #endif |
a6c4e076 | 857 | } |
3b520b23 | 858 | |
a6c4e076 JF |
859 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
860 | { | |
861 | BUG_ON(c == &boot_cpu_data); | |
862 | identify_cpu(c); | |
102bbe3a | 863 | #ifdef CONFIG_X86_32 |
a6c4e076 | 864 | enable_sep_cpu(); |
102bbe3a | 865 | #endif |
a6c4e076 | 866 | mtrr_ap_init(); |
1da177e4 LT |
867 | } |
868 | ||
a0854a46 | 869 | struct msr_range { |
0f3fa48a IM |
870 | unsigned min; |
871 | unsigned max; | |
a0854a46 | 872 | }; |
1da177e4 | 873 | |
02dde8b4 | 874 | static const struct msr_range msr_range_array[] __cpuinitconst = { |
a0854a46 YL |
875 | { 0x00000000, 0x00000418}, |
876 | { 0xc0000000, 0xc000040b}, | |
877 | { 0xc0010000, 0xc0010142}, | |
878 | { 0xc0011000, 0xc001103b}, | |
879 | }; | |
1da177e4 | 880 | |
a0854a46 YL |
881 | static void __cpuinit print_cpu_msr(void) |
882 | { | |
0f3fa48a | 883 | unsigned index_min, index_max; |
a0854a46 YL |
884 | unsigned index; |
885 | u64 val; | |
886 | int i; | |
a0854a46 YL |
887 | |
888 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
889 | index_min = msr_range_array[i].min; | |
890 | index_max = msr_range_array[i].max; | |
0f3fa48a | 891 | |
a0854a46 YL |
892 | for (index = index_min; index < index_max; index++) { |
893 | if (rdmsrl_amd_safe(index, &val)) | |
894 | continue; | |
895 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 896 | } |
a0854a46 YL |
897 | } |
898 | } | |
94605eff | 899 | |
a0854a46 | 900 | static int show_msr __cpuinitdata; |
0f3fa48a | 901 | |
a0854a46 YL |
902 | static __init int setup_show_msr(char *arg) |
903 | { | |
904 | int num; | |
3dd9d514 | 905 | |
a0854a46 | 906 | get_option(&arg, &num); |
3dd9d514 | 907 | |
a0854a46 YL |
908 | if (num > 0) |
909 | show_msr = num; | |
910 | return 1; | |
1da177e4 | 911 | } |
a0854a46 | 912 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 913 | |
191679fd AK |
914 | static __init int setup_noclflush(char *arg) |
915 | { | |
916 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
917 | return 1; | |
918 | } | |
919 | __setup("noclflush", setup_noclflush); | |
920 | ||
3bc9b76b | 921 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 922 | { |
02dde8b4 | 923 | const char *vendor = NULL; |
1da177e4 | 924 | |
0f3fa48a | 925 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 926 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
927 | } else { |
928 | if (c->cpuid_level >= 0) | |
929 | vendor = c->x86_vendor_id; | |
930 | } | |
1da177e4 | 931 | |
bd32a8cf | 932 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 933 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 934 | |
9d31d35b YL |
935 | if (c->x86_model_id[0]) |
936 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 937 | else |
9d31d35b | 938 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 939 | |
34048c9e | 940 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 941 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 942 | else |
9d31d35b | 943 | printk(KERN_CONT "\n"); |
a0854a46 YL |
944 | |
945 | #ifdef CONFIG_SMP | |
946 | if (c->cpu_index < show_msr) | |
947 | print_cpu_msr(); | |
948 | #else | |
949 | if (show_msr) | |
950 | print_cpu_msr(); | |
951 | #endif | |
1da177e4 LT |
952 | } |
953 | ||
ac72e788 AK |
954 | static __init int setup_disablecpuid(char *arg) |
955 | { | |
956 | int bit; | |
0f3fa48a | 957 | |
ac72e788 AK |
958 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) |
959 | setup_clear_cpu_cap(bit); | |
960 | else | |
961 | return 0; | |
0f3fa48a | 962 | |
ac72e788 AK |
963 | return 1; |
964 | } | |
965 | __setup("clearcpuid=", setup_disablecpuid); | |
966 | ||
d5494d4f | 967 | #ifdef CONFIG_X86_64 |
d5494d4f YL |
968 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; |
969 | ||
947e76cd BG |
970 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
971 | irq_stack_union) __aligned(PAGE_SIZE); | |
0f3fa48a | 972 | |
26f80bd6 | 973 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
2add8e23 | 974 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; |
d5494d4f | 975 | |
9af45651 BG |
976 | DEFINE_PER_CPU(unsigned long, kernel_stack) = |
977 | (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; | |
978 | EXPORT_PER_CPU_SYMBOL(kernel_stack); | |
d5494d4f | 979 | |
56895530 | 980 | DEFINE_PER_CPU(unsigned int, irq_count) = -1; |
d5494d4f | 981 | |
0f3fa48a IM |
982 | /* |
983 | * Special IST stacks which the CPU switches to when it calls | |
984 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
985 | * limit), all of them are 4K, except the debug stack which | |
986 | * is 8K. | |
987 | */ | |
988 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
989 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
990 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
991 | }; | |
992 | ||
92d65b23 BG |
993 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
994 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]) | |
995 | __aligned(PAGE_SIZE); | |
d5494d4f | 996 | |
d5494d4f YL |
997 | /* May not be marked __init: used by software suspend */ |
998 | void syscall_init(void) | |
1da177e4 | 999 | { |
d5494d4f YL |
1000 | /* |
1001 | * LSTAR and STAR live in a bit strange symbiosis. | |
1002 | * They both write to the same internal register. STAR allows to | |
1003 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
1004 | */ | |
1005 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
1006 | wrmsrl(MSR_LSTAR, system_call); | |
1007 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 1008 | |
d5494d4f YL |
1009 | #ifdef CONFIG_IA32_EMULATION |
1010 | syscall32_cpu_init(); | |
1011 | #endif | |
03ae5768 | 1012 | |
d5494d4f YL |
1013 | /* Flags to clear on syscall */ |
1014 | wrmsrl(MSR_SYSCALL_MASK, | |
1015 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
1da177e4 | 1016 | } |
62111195 | 1017 | |
d5494d4f YL |
1018 | unsigned long kernel_eflags; |
1019 | ||
1020 | /* | |
1021 | * Copies of the original ist values from the tss are only accessed during | |
1022 | * debugging, no special alignment required. | |
1023 | */ | |
1024 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1025 | ||
0f3fa48a | 1026 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1027 | |
60a5317f TH |
1028 | #ifdef CONFIG_CC_STACKPROTECTOR |
1029 | DEFINE_PER_CPU(unsigned long, stack_canary); | |
1030 | #endif | |
d5494d4f | 1031 | |
60a5317f | 1032 | /* Make sure %fs and %gs are initialized properly in idle threads */ |
6b2fb3c6 | 1033 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
1034 | { |
1035 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 1036 | regs->fs = __KERNEL_PERCPU; |
60a5317f | 1037 | regs->gs = __KERNEL_STACK_CANARY; |
0f3fa48a | 1038 | |
f95d47ca JF |
1039 | return regs; |
1040 | } | |
0f3fa48a | 1041 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1042 | |
9766cdbc JSR |
1043 | /* |
1044 | * Clear all 6 debug registers: | |
1045 | */ | |
1046 | static void clear_all_debug_regs(void) | |
1047 | { | |
1048 | int i; | |
1049 | ||
1050 | for (i = 0; i < 8; i++) { | |
1051 | /* Ignore db4, db5 */ | |
1052 | if ((i == 4) || (i == 5)) | |
1053 | continue; | |
1054 | ||
1055 | set_debugreg(0, i); | |
1056 | } | |
1057 | } | |
c5413fbe | 1058 | |
d2cbcc49 RR |
1059 | /* |
1060 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1061 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1062 | * and IDT. We reload them nevertheless, this function acts as a | |
1063 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1064 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1065 | */ |
1ba76586 | 1066 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1067 | |
1ba76586 YL |
1068 | void __cpuinit cpu_init(void) |
1069 | { | |
0f3fa48a | 1070 | struct orig_ist *orig_ist; |
1ba76586 | 1071 | struct task_struct *me; |
0f3fa48a IM |
1072 | struct tss_struct *t; |
1073 | unsigned long v; | |
1074 | int cpu; | |
1ba76586 YL |
1075 | int i; |
1076 | ||
0f3fa48a IM |
1077 | cpu = stack_smp_processor_id(); |
1078 | t = &per_cpu(init_tss, cpu); | |
1079 | orig_ist = &per_cpu(orig_ist, cpu); | |
1080 | ||
e7a22c1e BG |
1081 | #ifdef CONFIG_NUMA |
1082 | if (cpu != 0 && percpu_read(node_number) == 0 && | |
1083 | cpu_to_node(cpu) != NUMA_NO_NODE) | |
1084 | percpu_write(node_number, cpu_to_node(cpu)); | |
1085 | #endif | |
1ba76586 YL |
1086 | |
1087 | me = current; | |
1088 | ||
c2d1cec1 | 1089 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) |
1ba76586 YL |
1090 | panic("CPU#%d already initialized!\n", cpu); |
1091 | ||
1092 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1093 | ||
1094 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1095 | ||
1096 | /* | |
1097 | * Initialize the per-CPU GDT with the boot GDT, | |
1098 | * and set up the GDT descriptor: | |
1099 | */ | |
1100 | ||
552be871 | 1101 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1102 | loadsegment(fs, 0); |
1103 | ||
1ba76586 YL |
1104 | load_idt((const struct desc_ptr *)&idt_descr); |
1105 | ||
1106 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1107 | syscall_init(); | |
1108 | ||
1109 | wrmsrl(MSR_FS_BASE, 0); | |
1110 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1111 | barrier(); | |
1112 | ||
1113 | check_efer(); | |
06cd9a7d | 1114 | if (cpu != 0) |
1ba76586 YL |
1115 | enable_x2apic(); |
1116 | ||
1117 | /* | |
1118 | * set up and load the per-CPU TSS | |
1119 | */ | |
1120 | if (!orig_ist->ist[0]) { | |
92d65b23 | 1121 | char *estacks = per_cpu(exception_stacks, cpu); |
0f3fa48a | 1122 | |
1ba76586 | 1123 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
0f3fa48a | 1124 | estacks += exception_stack_sizes[v]; |
1ba76586 YL |
1125 | orig_ist->ist[v] = t->x86_tss.ist[v] = |
1126 | (unsigned long)estacks; | |
1127 | } | |
1128 | } | |
1129 | ||
1130 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
0f3fa48a | 1131 | |
1ba76586 YL |
1132 | /* |
1133 | * <= is required because the CPU will access up to | |
1134 | * 8 bits beyond the end of the IO permission bitmap. | |
1135 | */ | |
1136 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1137 | t->io_bitmap[i] = ~0UL; | |
1138 | ||
1139 | atomic_inc(&init_mm.mm_count); | |
1140 | me->active_mm = &init_mm; | |
8c5dfd25 | 1141 | BUG_ON(me->mm); |
1ba76586 YL |
1142 | enter_lazy_tlb(&init_mm, me); |
1143 | ||
1144 | load_sp0(t, ¤t->thread); | |
1145 | set_tss_desc(cpu, t); | |
1146 | load_TR_desc(); | |
1147 | load_LDT(&init_mm.context); | |
1148 | ||
1149 | #ifdef CONFIG_KGDB | |
1150 | /* | |
1151 | * If the kgdb is connected no debug regs should be altered. This | |
1152 | * is only applicable when KGDB and a KGDB I/O module are built | |
1153 | * into the kernel and you are using early debugging with | |
1154 | * kgdbwait. KGDB will control the kernel HW breakpoint registers. | |
1155 | */ | |
1156 | if (kgdb_connected && arch_kgdb_ops.correct_hw_break) | |
1157 | arch_kgdb_ops.correct_hw_break(); | |
8f6d86dc | 1158 | else |
1ba76586 | 1159 | #endif |
9766cdbc | 1160 | clear_all_debug_regs(); |
1ba76586 YL |
1161 | |
1162 | fpu_init(); | |
1163 | ||
1164 | raw_local_save_flags(kernel_eflags); | |
1165 | ||
1166 | if (is_uv_system()) | |
1167 | uv_cpu_init(); | |
1168 | } | |
1169 | ||
1170 | #else | |
1171 | ||
d2cbcc49 | 1172 | void __cpuinit cpu_init(void) |
9ee79a3d | 1173 | { |
d2cbcc49 RR |
1174 | int cpu = smp_processor_id(); |
1175 | struct task_struct *curr = current; | |
34048c9e | 1176 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1177 | struct thread_struct *thread = &curr->thread; |
62111195 | 1178 | |
c2d1cec1 | 1179 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { |
62111195 | 1180 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); |
9766cdbc JSR |
1181 | for (;;) |
1182 | local_irq_enable(); | |
62111195 JF |
1183 | } |
1184 | ||
1185 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1186 | ||
1187 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1188 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1189 | |
4d37e7e3 | 1190 | load_idt(&idt_descr); |
552be871 | 1191 | switch_to_new_gdt(cpu); |
1da177e4 | 1192 | |
1da177e4 LT |
1193 | /* |
1194 | * Set up and load the per-CPU TSS and LDT | |
1195 | */ | |
1196 | atomic_inc(&init_mm.mm_count); | |
62111195 | 1197 | curr->active_mm = &init_mm; |
8c5dfd25 | 1198 | BUG_ON(curr->mm); |
62111195 | 1199 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1200 | |
faca6227 | 1201 | load_sp0(t, thread); |
34048c9e | 1202 | set_tss_desc(cpu, t); |
1da177e4 LT |
1203 | load_TR_desc(); |
1204 | load_LDT(&init_mm.context); | |
1205 | ||
f9a196b8 TG |
1206 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); |
1207 | ||
22c4e308 | 1208 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1209 | /* Set up doublefault TSS pointer in the GDT */ |
1210 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1211 | #endif |
1da177e4 | 1212 | |
9766cdbc | 1213 | clear_all_debug_regs(); |
1da177e4 LT |
1214 | |
1215 | /* | |
1216 | * Force FPU initialization: | |
1217 | */ | |
b359e8a4 SS |
1218 | if (cpu_has_xsave) |
1219 | current_thread_info()->status = TS_XSAVE; | |
1220 | else | |
1221 | current_thread_info()->status = 0; | |
1da177e4 LT |
1222 | clear_used_math(); |
1223 | mxcsr_feature_mask_init(); | |
dc1e35c6 SS |
1224 | |
1225 | /* | |
1226 | * Boot processor to setup the FP and extended state context info. | |
1227 | */ | |
b3572e36 | 1228 | if (smp_processor_id() == boot_cpu_id) |
dc1e35c6 SS |
1229 | init_thread_xstate(); |
1230 | ||
1231 | xsave_init(); | |
1da177e4 | 1232 | } |
1ba76586 | 1233 | #endif |