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1da177e4 | 1 | #include <linux/init.h> |
f0fc4aff YL |
2 | #include <linux/kernel.h> |
3 | #include <linux/sched.h> | |
1da177e4 | 4 | #include <linux/string.h> |
f0fc4aff YL |
5 | #include <linux/bootmem.h> |
6 | #include <linux/bitops.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/kgdb.h> | |
9 | #include <linux/topology.h> | |
1da177e4 LT |
10 | #include <linux/delay.h> |
11 | #include <linux/smp.h> | |
1da177e4 | 12 | #include <linux/percpu.h> |
1da177e4 LT |
13 | #include <asm/i387.h> |
14 | #include <asm/msr.h> | |
15 | #include <asm/io.h> | |
f0fc4aff | 16 | #include <asm/linkage.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
27b07da7 | 18 | #include <asm/mtrr.h> |
a03a3e28 | 19 | #include <asm/mce.h> |
8d4a4300 | 20 | #include <asm/pat.h> |
b6734c35 | 21 | #include <asm/asm.h> |
f0fc4aff | 22 | #include <asm/numa.h> |
b342797c | 23 | #include <asm/smp.h> |
1da177e4 LT |
24 | #ifdef CONFIG_X86_LOCAL_APIC |
25 | #include <asm/mpspec.h> | |
26 | #include <asm/apic.h> | |
27 | #include <mach_apic.h> | |
f0fc4aff | 28 | #include <asm/genapic.h> |
1da177e4 LT |
29 | #endif |
30 | ||
f0fc4aff YL |
31 | #include <asm/pda.h> |
32 | #include <asm/pgtable.h> | |
33 | #include <asm/processor.h> | |
34 | #include <asm/desc.h> | |
35 | #include <asm/atomic.h> | |
36 | #include <asm/proto.h> | |
37 | #include <asm/sections.h> | |
38 | #include <asm/setup.h> | |
39 | ||
1da177e4 LT |
40 | #include "cpu.h" |
41 | ||
0a488a53 YL |
42 | static struct cpu_dev *this_cpu __cpuinitdata; |
43 | ||
950ad7ff YL |
44 | #ifdef CONFIG_X86_64 |
45 | /* We need valid kernel segments for data and code in long mode too | |
46 | * IRET will check the segment types kkeil 2000/10/28 | |
47 | * Also sysret mandates a special GDT layout | |
48 | */ | |
49 | /* The TLS descriptors are currently at a different place compared to i386. | |
50 | Hopefully nobody expects them at a fixed place (Wine?) */ | |
7a61d35d | 51 | DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff YL |
52 | [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, |
53 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, | |
54 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, | |
55 | [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, | |
56 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, | |
57 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, | |
58 | } }; | |
59 | #else | |
63cc8c75 | 60 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
6842ef0e GOC |
61 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
62 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
63 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
64 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
65 | /* |
66 | * Segments used for calling PnP BIOS have byte granularity. | |
67 | * They code segments and data segments have fixed 64k limits, | |
68 | * the transfer segment sizes are set at run time. | |
69 | */ | |
6842ef0e GOC |
70 | /* 32-bit code */ |
71 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
72 | /* 16-bit code */ | |
73 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
74 | /* 16-bit data */ | |
75 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
76 | /* 16-bit data */ | |
77 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
78 | /* 16-bit data */ | |
79 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
bf504672 RR |
80 | /* |
81 | * The APM segments have byte granularity and their bases | |
82 | * are set at run time. All have 64k limits. | |
83 | */ | |
6842ef0e GOC |
84 | /* 32-bit code */ |
85 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
bf504672 | 86 | /* 16-bit code */ |
6842ef0e GOC |
87 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
88 | /* data */ | |
89 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
bf504672 | 90 | |
6842ef0e GOC |
91 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
92 | [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } }, | |
7a61d35d | 93 | } }; |
950ad7ff | 94 | #endif |
7a61d35d | 95 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 96 | |
ba51dced | 97 | #ifdef CONFIG_X86_32 |
3bc9b76b | 98 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 99 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 100 | |
0a488a53 YL |
101 | static int __init cachesize_setup(char *str) |
102 | { | |
103 | get_option(&str, &cachesize_override); | |
104 | return 1; | |
105 | } | |
106 | __setup("cachesize=", cachesize_setup); | |
107 | ||
0a488a53 YL |
108 | static int __init x86_fxsr_setup(char *s) |
109 | { | |
110 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
111 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
112 | return 1; | |
113 | } | |
114 | __setup("nofxsr", x86_fxsr_setup); | |
115 | ||
116 | static int __init x86_sep_setup(char *s) | |
117 | { | |
118 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
119 | return 1; | |
120 | } | |
121 | __setup("nosep", x86_sep_setup); | |
122 | ||
123 | /* Standard macro to see if a specific flag is changeable */ | |
124 | static inline int flag_is_changeable_p(u32 flag) | |
125 | { | |
126 | u32 f1, f2; | |
127 | ||
94f6bac1 KH |
128 | /* |
129 | * Cyrix and IDT cpus allow disabling of CPUID | |
130 | * so the code below may return different results | |
131 | * when it is executed before and after enabling | |
132 | * the CPUID. Add "volatile" to not allow gcc to | |
133 | * optimize the subsequent calls to this function. | |
134 | */ | |
135 | asm volatile ("pushfl\n\t" | |
136 | "pushfl\n\t" | |
137 | "popl %0\n\t" | |
138 | "movl %0,%1\n\t" | |
139 | "xorl %2,%0\n\t" | |
140 | "pushl %0\n\t" | |
141 | "popfl\n\t" | |
142 | "pushfl\n\t" | |
143 | "popl %0\n\t" | |
144 | "popfl\n\t" | |
145 | : "=&r" (f1), "=&r" (f2) | |
146 | : "ir" (flag)); | |
0a488a53 YL |
147 | |
148 | return ((f1^f2) & flag) != 0; | |
149 | } | |
150 | ||
151 | /* Probe for the CPUID instruction */ | |
152 | static int __cpuinit have_cpuid_p(void) | |
153 | { | |
154 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
155 | } | |
156 | ||
157 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
158 | { | |
159 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { | |
160 | /* Disable processor serial number */ | |
161 | unsigned long lo, hi; | |
162 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
163 | lo |= 0x200000; | |
164 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
165 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
166 | clear_cpu_cap(c, X86_FEATURE_PN); | |
167 | ||
168 | /* Disabling the serial number may affect the cpuid level */ | |
169 | c->cpuid_level = cpuid_eax(0); | |
170 | } | |
171 | } | |
172 | ||
173 | static int __init x86_serial_nr_setup(char *s) | |
174 | { | |
175 | disable_x86_serial_nr = 0; | |
176 | return 1; | |
177 | } | |
178 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 179 | #else |
102bbe3a YL |
180 | static inline int flag_is_changeable_p(u32 flag) |
181 | { | |
182 | return 1; | |
183 | } | |
ba51dced YL |
184 | /* Probe for the CPUID instruction */ |
185 | static inline int have_cpuid_p(void) | |
186 | { | |
187 | return 1; | |
188 | } | |
102bbe3a YL |
189 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
190 | { | |
191 | } | |
ba51dced | 192 | #endif |
0a488a53 | 193 | |
102bbe3a YL |
194 | /* |
195 | * Naming convention should be: <Name> [(<Codename>)] | |
196 | * This table only is used unless init_<vendor>() below doesn't set it; | |
197 | * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used | |
198 | * | |
199 | */ | |
200 | ||
201 | /* Look up CPU names by table lookup. */ | |
202 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) | |
203 | { | |
204 | struct cpu_model_info *info; | |
205 | ||
206 | if (c->x86_model >= 16) | |
207 | return NULL; /* Range check */ | |
208 | ||
209 | if (!this_cpu) | |
210 | return NULL; | |
211 | ||
212 | info = this_cpu->c_models; | |
213 | ||
214 | while (info && info->family) { | |
215 | if (info->family == c->x86) | |
216 | return info->model_names[c->x86_model]; | |
217 | info++; | |
218 | } | |
219 | return NULL; /* Not found */ | |
220 | } | |
221 | ||
7d851c8d AK |
222 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
223 | ||
9d31d35b YL |
224 | /* Current gdt points %fs at the "master" per-cpu area: after this, |
225 | * it's on the real one. */ | |
226 | void switch_to_new_gdt(void) | |
227 | { | |
228 | struct desc_ptr gdt_descr; | |
229 | ||
230 | gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id()); | |
231 | gdt_descr.size = GDT_SIZE - 1; | |
232 | load_gdt(&gdt_descr); | |
fab334c1 | 233 | #ifdef CONFIG_X86_32 |
9d31d35b | 234 | asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory"); |
fab334c1 | 235 | #endif |
9d31d35b YL |
236 | } |
237 | ||
10a434fc | 238 | static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 239 | |
34048c9e | 240 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
1da177e4 | 241 | { |
b9e67f00 YL |
242 | #ifdef CONFIG_X86_64 |
243 | display_cacheinfo(c); | |
244 | #else | |
1da177e4 LT |
245 | /* Not much we can do here... */ |
246 | /* Check if at least it has cpuid */ | |
247 | if (c->cpuid_level == -1) { | |
248 | /* No cpuid. It must be an ancient CPU */ | |
249 | if (c->x86 == 4) | |
250 | strcpy(c->x86_model_id, "486"); | |
251 | else if (c->x86 == 3) | |
252 | strcpy(c->x86_model_id, "386"); | |
253 | } | |
b9e67f00 | 254 | #endif |
1da177e4 LT |
255 | } |
256 | ||
95414930 | 257 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 258 | .c_init = default_init, |
fe38d855 | 259 | .c_vendor = "Unknown", |
10a434fc | 260 | .c_x86_vendor = X86_VENDOR_UNKNOWN, |
1da177e4 | 261 | }; |
1da177e4 | 262 | |
1b05d60d | 263 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
264 | { |
265 | unsigned int *v; | |
266 | char *p, *q; | |
267 | ||
3da99c97 | 268 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 269 | return; |
1da177e4 LT |
270 | |
271 | v = (unsigned int *) c->x86_model_id; | |
272 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
273 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
274 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
275 | c->x86_model_id[48] = 0; | |
276 | ||
277 | /* Intel chips right-justify this string for some dumb reason; | |
278 | undo that brain damage */ | |
279 | p = q = &c->x86_model_id[0]; | |
34048c9e | 280 | while (*p == ' ') |
1da177e4 | 281 | p++; |
34048c9e PC |
282 | if (p != q) { |
283 | while (*p) | |
1da177e4 | 284 | *q++ = *p++; |
34048c9e | 285 | while (q <= &c->x86_model_id[48]) |
1da177e4 LT |
286 | *q++ = '\0'; /* Zero-pad the rest */ |
287 | } | |
1da177e4 LT |
288 | } |
289 | ||
3bc9b76b | 290 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 | 291 | { |
9d31d35b | 292 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 293 | |
3da99c97 | 294 | n = c->extended_cpuid_level; |
1da177e4 LT |
295 | |
296 | if (n >= 0x80000005) { | |
9d31d35b | 297 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 298 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
9d31d35b YL |
299 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); |
300 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
140fc727 YL |
301 | #ifdef CONFIG_X86_64 |
302 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
303 | c->x86_tlbsize = 0; | |
304 | #endif | |
1da177e4 LT |
305 | } |
306 | ||
307 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
308 | return; | |
309 | ||
0a488a53 | 310 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 311 | l2size = ecx >> 16; |
34048c9e | 312 | |
140fc727 YL |
313 | #ifdef CONFIG_X86_64 |
314 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
315 | #else | |
1da177e4 LT |
316 | /* do processor-specific cache resizing */ |
317 | if (this_cpu->c_size_cache) | |
34048c9e | 318 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
319 | |
320 | /* Allow user to override all this if necessary. */ | |
321 | if (cachesize_override != -1) | |
322 | l2size = cachesize_override; | |
323 | ||
34048c9e | 324 | if (l2size == 0) |
1da177e4 | 325 | return; /* Again, no L2 cache is possible */ |
140fc727 | 326 | #endif |
1da177e4 LT |
327 | |
328 | c->x86_cache_size = l2size; | |
329 | ||
330 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
0a488a53 | 331 | l2size, ecx & 0xFF); |
1da177e4 LT |
332 | } |
333 | ||
9d31d35b | 334 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 335 | { |
97e4db7c | 336 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
337 | u32 eax, ebx, ecx, edx; |
338 | int index_msb, core_bits; | |
1da177e4 | 339 | |
0a488a53 | 340 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 341 | return; |
1da177e4 | 342 | |
0a488a53 YL |
343 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
344 | goto out; | |
1da177e4 | 345 | |
1cd78776 YL |
346 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
347 | return; | |
1da177e4 | 348 | |
0a488a53 | 349 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 350 | |
9d31d35b YL |
351 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
352 | ||
353 | if (smp_num_siblings == 1) { | |
354 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
355 | } else if (smp_num_siblings > 1) { | |
356 | ||
357 | if (smp_num_siblings > NR_CPUS) { | |
358 | printk(KERN_WARNING "CPU: Unsupported number of siblings %d", | |
359 | smp_num_siblings); | |
360 | smp_num_siblings = 1; | |
361 | return; | |
362 | } | |
363 | ||
364 | index_msb = get_count_order(smp_num_siblings); | |
1cd78776 YL |
365 | #ifdef CONFIG_X86_64 |
366 | c->phys_proc_id = phys_pkg_id(index_msb); | |
367 | #else | |
9d31d35b | 368 | c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb); |
1cd78776 | 369 | #endif |
9d31d35b YL |
370 | |
371 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
372 | ||
373 | index_msb = get_count_order(smp_num_siblings); | |
374 | ||
375 | core_bits = get_count_order(c->x86_max_cores); | |
376 | ||
1cd78776 YL |
377 | #ifdef CONFIG_X86_64 |
378 | c->cpu_core_id = phys_pkg_id(index_msb) & | |
379 | ((1 << core_bits) - 1); | |
380 | #else | |
9d31d35b YL |
381 | c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) & |
382 | ((1 << core_bits) - 1); | |
1cd78776 | 383 | #endif |
1da177e4 | 384 | } |
1da177e4 | 385 | |
0a488a53 YL |
386 | out: |
387 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
388 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
389 | c->phys_proc_id); | |
390 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
391 | c->cpu_core_id); | |
9d31d35b | 392 | } |
9d31d35b | 393 | #endif |
97e4db7c | 394 | } |
1da177e4 | 395 | |
3da99c97 | 396 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
397 | { |
398 | char *v = c->x86_vendor_id; | |
399 | int i; | |
fe38d855 | 400 | static int printed; |
1da177e4 LT |
401 | |
402 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
403 | if (!cpu_devs[i]) |
404 | break; | |
405 | ||
406 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
407 | (cpu_devs[i]->c_ident[1] && | |
408 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
409 | this_cpu = cpu_devs[i]; | |
410 | c->x86_vendor = this_cpu->c_x86_vendor; | |
411 | return; | |
1da177e4 LT |
412 | } |
413 | } | |
10a434fc | 414 | |
fe38d855 CE |
415 | if (!printed) { |
416 | printed++; | |
43603c8d | 417 | printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v); |
fe38d855 CE |
418 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); |
419 | } | |
10a434fc | 420 | |
fe38d855 CE |
421 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
422 | this_cpu = &default_cpu; | |
1da177e4 LT |
423 | } |
424 | ||
9d31d35b | 425 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 426 | { |
1da177e4 | 427 | /* Get vendor name */ |
4a148513 HH |
428 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
429 | (unsigned int *)&c->x86_vendor_id[0], | |
430 | (unsigned int *)&c->x86_vendor_id[8], | |
431 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 432 | |
1da177e4 | 433 | c->x86 = 4; |
9d31d35b | 434 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
435 | if (c->cpuid_level >= 0x00000001) { |
436 | u32 junk, tfms, cap0, misc; | |
437 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
9d31d35b YL |
438 | c->x86 = (tfms >> 8) & 0xf; |
439 | c->x86_model = (tfms >> 4) & 0xf; | |
440 | c->x86_mask = tfms & 0xf; | |
f5f786d0 | 441 | if (c->x86 == 0xf) |
1da177e4 | 442 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 443 | if (c->x86 >= 0x6) |
9d31d35b | 444 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
d4387bd3 | 445 | if (cap0 & (1<<19)) { |
d4387bd3 | 446 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 447 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 448 | } |
1da177e4 | 449 | } |
1da177e4 | 450 | } |
3da99c97 YL |
451 | |
452 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
093af8d7 YL |
453 | { |
454 | u32 tfms, xlvl; | |
3da99c97 | 455 | u32 ebx; |
093af8d7 | 456 | |
3da99c97 YL |
457 | /* Intel-defined flags: level 0x00000001 */ |
458 | if (c->cpuid_level >= 0x00000001) { | |
459 | u32 capability, excap; | |
460 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
461 | c->x86_capability[0] = capability; | |
462 | c->x86_capability[4] = excap; | |
463 | } | |
093af8d7 | 464 | |
3da99c97 YL |
465 | /* AMD-defined flags: level 0x80000001 */ |
466 | xlvl = cpuid_eax(0x80000000); | |
467 | c->extended_cpuid_level = xlvl; | |
468 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
469 | if (xlvl >= 0x80000001) { | |
470 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
471 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 472 | } |
093af8d7 | 473 | } |
093af8d7 | 474 | |
5122c890 | 475 | #ifdef CONFIG_X86_64 |
5122c890 YL |
476 | if (c->extended_cpuid_level >= 0x80000008) { |
477 | u32 eax = cpuid_eax(0x80000008); | |
478 | ||
479 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
480 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 481 | } |
5122c890 | 482 | #endif |
e3224234 YL |
483 | |
484 | if (c->extended_cpuid_level >= 0x80000007) | |
485 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 YL |
486 | |
487 | } | |
1da177e4 | 488 | |
aef93c8b YL |
489 | static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
490 | { | |
491 | #ifdef CONFIG_X86_32 | |
492 | int i; | |
493 | ||
494 | /* | |
495 | * First of all, decide if this is a 486 or higher | |
496 | * It's a 486 if we can modify the AC flag | |
497 | */ | |
498 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
499 | c->x86 = 4; | |
500 | else | |
501 | c->x86 = 3; | |
502 | ||
503 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
504 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
505 | c->x86_vendor_id[0] = 0; | |
506 | cpu_devs[i]->c_identify(c); | |
507 | if (c->x86_vendor_id[0]) { | |
508 | get_cpu_vendor(c); | |
509 | break; | |
510 | } | |
511 | } | |
512 | #endif | |
513 | } | |
514 | ||
34048c9e PC |
515 | /* |
516 | * Do minimum CPU detection early. | |
517 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
518 | * cache alignment. | |
519 | * The others are not touched to avoid unwanted side effects. | |
520 | * | |
521 | * WARNING: this function is only called on the BP. Don't add code here | |
522 | * that is supposed to run on all CPUs. | |
523 | */ | |
3da99c97 | 524 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 525 | { |
6627d242 YL |
526 | #ifdef CONFIG_X86_64 |
527 | c->x86_clflush_size = 64; | |
528 | #else | |
d4387bd3 | 529 | c->x86_clflush_size = 32; |
6627d242 | 530 | #endif |
0a488a53 | 531 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 532 | |
3da99c97 | 533 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 534 | c->extended_cpuid_level = 0; |
d7cd5611 | 535 | |
aef93c8b YL |
536 | if (!have_cpuid_p()) |
537 | identify_cpu_without_cpuid(c); | |
538 | ||
539 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
540 | if (!have_cpuid_p()) |
541 | return; | |
542 | ||
543 | cpu_detect(c); | |
544 | ||
3da99c97 | 545 | get_cpu_vendor(c); |
2b16a235 | 546 | |
3da99c97 | 547 | get_cpu_cap(c); |
12cf105c | 548 | |
10a434fc YL |
549 | if (this_cpu->c_early_init) |
550 | this_cpu->c_early_init(c); | |
093af8d7 | 551 | |
3da99c97 | 552 | validate_pat_support(c); |
bfcb4c1b | 553 | |
1c4acdb4 | 554 | #ifdef CONFIG_SMP |
bfcb4c1b | 555 | c->cpu_index = boot_cpu_id; |
1c4acdb4 | 556 | #endif |
d7cd5611 RR |
557 | } |
558 | ||
9d31d35b YL |
559 | void __init early_cpu_init(void) |
560 | { | |
10a434fc YL |
561 | struct cpu_dev **cdev; |
562 | int count = 0; | |
563 | ||
564 | printk("KERNEL supported cpus:\n"); | |
565 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { | |
566 | struct cpu_dev *cpudev = *cdev; | |
567 | unsigned int j; | |
9d31d35b | 568 | |
10a434fc YL |
569 | if (count >= X86_VENDOR_NUM) |
570 | break; | |
571 | cpu_devs[count] = cpudev; | |
572 | count++; | |
573 | ||
574 | for (j = 0; j < 2; j++) { | |
575 | if (!cpudev->c_ident[j]) | |
576 | continue; | |
577 | printk(" %s %s\n", cpudev->c_vendor, | |
578 | cpudev->c_ident[j]); | |
579 | } | |
580 | } | |
9d31d35b | 581 | |
9d31d35b | 582 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 583 | } |
093af8d7 | 584 | |
b6734c35 PA |
585 | /* |
586 | * The NOPL instruction is supposed to exist on all CPUs with | |
ba0593bf | 587 | * family >= 6; unfortunately, that's not true in practice because |
b6734c35 | 588 | * of early VIA chips and (more importantly) broken virtualizers that |
ba0593bf PA |
589 | * are not easy to detect. In the latter case it doesn't even *fail* |
590 | * reliably, so probing for it doesn't even work. Disable it completely | |
591 | * unless we can find a reliable way to detect all the broken cases. | |
b6734c35 PA |
592 | */ |
593 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
594 | { | |
b6734c35 | 595 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
d7cd5611 RR |
596 | } |
597 | ||
34048c9e | 598 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 599 | { |
aef93c8b | 600 | c->extended_cpuid_level = 0; |
1da177e4 | 601 | |
3da99c97 | 602 | if (!have_cpuid_p()) |
aef93c8b | 603 | identify_cpu_without_cpuid(c); |
1d67953f | 604 | |
aef93c8b | 605 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 606 | if (!have_cpuid_p()) |
aef93c8b | 607 | return; |
1da177e4 | 608 | |
3da99c97 | 609 | cpu_detect(c); |
1da177e4 | 610 | |
3da99c97 | 611 | get_cpu_vendor(c); |
1da177e4 | 612 | |
3da99c97 | 613 | get_cpu_cap(c); |
1da177e4 | 614 | |
3da99c97 YL |
615 | if (c->cpuid_level >= 0x00000001) { |
616 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
617 | #ifdef CONFIG_X86_32 |
618 | # ifdef CONFIG_X86_HT | |
3da99c97 | 619 | c->apicid = phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 620 | # else |
3da99c97 | 621 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
622 | # endif |
623 | #endif | |
1da177e4 | 624 | |
b89d3b3e YL |
625 | #ifdef CONFIG_X86_HT |
626 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 627 | #endif |
3da99c97 | 628 | } |
1da177e4 | 629 | |
1b05d60d | 630 | get_model_name(c); /* Default name */ |
1da177e4 | 631 | |
3da99c97 YL |
632 | init_scattered_cpuid_features(c); |
633 | detect_nopl(c); | |
1da177e4 | 634 | } |
1da177e4 LT |
635 | |
636 | /* | |
637 | * This does the hard work of actually picking apart the CPU stuff... | |
638 | */ | |
9a250347 | 639 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
640 | { |
641 | int i; | |
642 | ||
643 | c->loops_per_jiffy = loops_per_jiffy; | |
644 | c->x86_cache_size = -1; | |
645 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
646 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
647 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
648 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 649 | c->x86_max_cores = 1; |
102bbe3a | 650 | c->x86_coreid_bits = 0; |
11fdd252 | 651 | #ifdef CONFIG_X86_64 |
102bbe3a YL |
652 | c->x86_clflush_size = 64; |
653 | #else | |
654 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 655 | c->x86_clflush_size = 32; |
102bbe3a YL |
656 | #endif |
657 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
658 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
659 | ||
1da177e4 LT |
660 | generic_identify(c); |
661 | ||
3898534d | 662 | if (this_cpu->c_identify) |
1da177e4 LT |
663 | this_cpu->c_identify(c); |
664 | ||
102bbe3a YL |
665 | #ifdef CONFIG_X86_64 |
666 | c->apicid = phys_pkg_id(0); | |
667 | #endif | |
668 | ||
1da177e4 LT |
669 | /* |
670 | * Vendor-specific initialization. In this section we | |
671 | * canonicalize the feature flags, meaning if there are | |
672 | * features a certain CPU supports which CPUID doesn't | |
673 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
674 | * we handle them here. | |
675 | * | |
676 | * At the end of this section, c->x86_capability better | |
677 | * indicate the features this CPU genuinely supports! | |
678 | */ | |
679 | if (this_cpu->c_init) | |
680 | this_cpu->c_init(c); | |
681 | ||
682 | /* Disable the PN if appropriate */ | |
683 | squash_the_stupid_serial_number(c); | |
684 | ||
685 | /* | |
686 | * The vendor-specific functions might have changed features. Now | |
687 | * we do "generic changes." | |
688 | */ | |
689 | ||
1da177e4 | 690 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 691 | if (!c->x86_model_id[0]) { |
1da177e4 LT |
692 | char *p; |
693 | p = table_lookup_model(c); | |
34048c9e | 694 | if (p) |
1da177e4 LT |
695 | strcpy(c->x86_model_id, p); |
696 | else | |
697 | /* Last resort... */ | |
698 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 699 | c->x86, c->x86_model); |
1da177e4 LT |
700 | } |
701 | ||
102bbe3a YL |
702 | #ifdef CONFIG_X86_64 |
703 | detect_ht(c); | |
704 | #endif | |
705 | ||
1da177e4 LT |
706 | /* |
707 | * On SMP, boot_cpu_data holds the common feature set between | |
708 | * all CPUs; so make sure that we indicate which features are | |
709 | * common between the CPUs. The first time this routine gets | |
710 | * executed, c == &boot_cpu_data. | |
711 | */ | |
34048c9e | 712 | if (c != &boot_cpu_data) { |
1da177e4 | 713 | /* AND the already accumulated flags with these */ |
9d31d35b | 714 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
715 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
716 | } | |
717 | ||
7d851c8d AK |
718 | /* Clear all flags overriden by options */ |
719 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 720 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 721 | |
102bbe3a | 722 | #ifdef CONFIG_X86_MCE |
1da177e4 | 723 | /* Init Machine Check Exception if available. */ |
1da177e4 | 724 | mcheck_init(c); |
102bbe3a | 725 | #endif |
30d432df AK |
726 | |
727 | select_idle_routine(c); | |
102bbe3a YL |
728 | |
729 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
730 | numa_add_cpu(smp_processor_id()); | |
731 | #endif | |
a6c4e076 | 732 | } |
31ab269a | 733 | |
e04d645f GC |
734 | #ifdef CONFIG_X86_64 |
735 | static void vgetcpu_set_mode(void) | |
736 | { | |
737 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
738 | vgetcpu_mode = VGETCPU_RDTSCP; | |
739 | else | |
740 | vgetcpu_mode = VGETCPU_LSL; | |
741 | } | |
742 | #endif | |
743 | ||
a6c4e076 JF |
744 | void __init identify_boot_cpu(void) |
745 | { | |
746 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 747 | #ifdef CONFIG_X86_32 |
a6c4e076 | 748 | sysenter_setup(); |
6fe940d6 | 749 | enable_sep_cpu(); |
e04d645f GC |
750 | #else |
751 | vgetcpu_set_mode(); | |
102bbe3a | 752 | #endif |
a6c4e076 | 753 | } |
3b520b23 | 754 | |
a6c4e076 JF |
755 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
756 | { | |
757 | BUG_ON(c == &boot_cpu_data); | |
758 | identify_cpu(c); | |
102bbe3a | 759 | #ifdef CONFIG_X86_32 |
a6c4e076 | 760 | enable_sep_cpu(); |
102bbe3a | 761 | #endif |
a6c4e076 | 762 | mtrr_ap_init(); |
1da177e4 LT |
763 | } |
764 | ||
a0854a46 YL |
765 | struct msr_range { |
766 | unsigned min; | |
767 | unsigned max; | |
768 | }; | |
1da177e4 | 769 | |
a0854a46 YL |
770 | static struct msr_range msr_range_array[] __cpuinitdata = { |
771 | { 0x00000000, 0x00000418}, | |
772 | { 0xc0000000, 0xc000040b}, | |
773 | { 0xc0010000, 0xc0010142}, | |
774 | { 0xc0011000, 0xc001103b}, | |
775 | }; | |
1da177e4 | 776 | |
a0854a46 YL |
777 | static void __cpuinit print_cpu_msr(void) |
778 | { | |
779 | unsigned index; | |
780 | u64 val; | |
781 | int i; | |
782 | unsigned index_min, index_max; | |
783 | ||
784 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
785 | index_min = msr_range_array[i].min; | |
786 | index_max = msr_range_array[i].max; | |
787 | for (index = index_min; index < index_max; index++) { | |
788 | if (rdmsrl_amd_safe(index, &val)) | |
789 | continue; | |
790 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 791 | } |
a0854a46 YL |
792 | } |
793 | } | |
94605eff | 794 | |
a0854a46 YL |
795 | static int show_msr __cpuinitdata; |
796 | static __init int setup_show_msr(char *arg) | |
797 | { | |
798 | int num; | |
3dd9d514 | 799 | |
a0854a46 | 800 | get_option(&arg, &num); |
3dd9d514 | 801 | |
a0854a46 YL |
802 | if (num > 0) |
803 | show_msr = num; | |
804 | return 1; | |
1da177e4 | 805 | } |
a0854a46 | 806 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 807 | |
191679fd AK |
808 | static __init int setup_noclflush(char *arg) |
809 | { | |
810 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
811 | return 1; | |
812 | } | |
813 | __setup("noclflush", setup_noclflush); | |
814 | ||
3bc9b76b | 815 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
816 | { |
817 | char *vendor = NULL; | |
818 | ||
819 | if (c->x86_vendor < X86_VENDOR_NUM) | |
820 | vendor = this_cpu->c_vendor; | |
821 | else if (c->cpuid_level >= 0) | |
822 | vendor = c->x86_vendor_id; | |
823 | ||
bd32a8cf | 824 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 825 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 826 | |
9d31d35b YL |
827 | if (c->x86_model_id[0]) |
828 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 829 | else |
9d31d35b | 830 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 831 | |
34048c9e | 832 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 833 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 834 | else |
9d31d35b | 835 | printk(KERN_CONT "\n"); |
a0854a46 YL |
836 | |
837 | #ifdef CONFIG_SMP | |
838 | if (c->cpu_index < show_msr) | |
839 | print_cpu_msr(); | |
840 | #else | |
841 | if (show_msr) | |
842 | print_cpu_msr(); | |
843 | #endif | |
1da177e4 LT |
844 | } |
845 | ||
ac72e788 AK |
846 | static __init int setup_disablecpuid(char *arg) |
847 | { | |
848 | int bit; | |
849 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
850 | setup_clear_cpu_cap(bit); | |
851 | else | |
852 | return 0; | |
853 | return 1; | |
854 | } | |
855 | __setup("clearcpuid=", setup_disablecpuid); | |
856 | ||
3bc9b76b | 857 | cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; |
1da177e4 | 858 | |
d5494d4f YL |
859 | #ifdef CONFIG_X86_64 |
860 | struct x8664_pda **_cpu_pda __read_mostly; | |
861 | EXPORT_SYMBOL(_cpu_pda); | |
862 | ||
863 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; | |
864 | ||
865 | char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss; | |
866 | ||
2d9cd6c2 | 867 | void __cpuinit pda_init(int cpu) |
d5494d4f YL |
868 | { |
869 | struct x8664_pda *pda = cpu_pda(cpu); | |
870 | ||
871 | /* Setup up data that may be needed in __get_free_pages early */ | |
872 | loadsegment(fs, 0); | |
873 | loadsegment(gs, 0); | |
874 | /* Memory clobbers used to order PDA accessed */ | |
875 | mb(); | |
876 | wrmsrl(MSR_GS_BASE, pda); | |
877 | mb(); | |
878 | ||
879 | pda->cpunumber = cpu; | |
880 | pda->irqcount = -1; | |
881 | pda->kernelstack = (unsigned long)stack_thread_info() - | |
882 | PDA_STACKOFFSET + THREAD_SIZE; | |
883 | pda->active_mm = &init_mm; | |
884 | pda->mmu_state = 0; | |
885 | ||
886 | if (cpu == 0) { | |
887 | /* others are initialized in smpboot.c */ | |
888 | pda->pcurrent = &init_task; | |
889 | pda->irqstackptr = boot_cpu_stack; | |
890 | pda->irqstackptr += IRQSTACKSIZE - 64; | |
891 | } else { | |
892 | if (!pda->irqstackptr) { | |
893 | pda->irqstackptr = (char *) | |
894 | __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER); | |
895 | if (!pda->irqstackptr) | |
896 | panic("cannot allocate irqstack for cpu %d", | |
897 | cpu); | |
898 | pda->irqstackptr += IRQSTACKSIZE - 64; | |
899 | } | |
900 | ||
901 | if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE) | |
902 | pda->nodenumber = cpu_to_node(cpu); | |
903 | } | |
904 | } | |
905 | ||
906 | char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + | |
907 | DEBUG_STKSZ] __page_aligned_bss; | |
908 | ||
909 | extern asmlinkage void ignore_sysret(void); | |
910 | ||
911 | /* May not be marked __init: used by software suspend */ | |
912 | void syscall_init(void) | |
1da177e4 | 913 | { |
d5494d4f YL |
914 | /* |
915 | * LSTAR and STAR live in a bit strange symbiosis. | |
916 | * They both write to the same internal register. STAR allows to | |
917 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
918 | */ | |
919 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
920 | wrmsrl(MSR_LSTAR, system_call); | |
921 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 922 | |
d5494d4f YL |
923 | #ifdef CONFIG_IA32_EMULATION |
924 | syscall32_cpu_init(); | |
925 | #endif | |
03ae5768 | 926 | |
d5494d4f YL |
927 | /* Flags to clear on syscall */ |
928 | wrmsrl(MSR_SYSCALL_MASK, | |
929 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
1da177e4 | 930 | } |
62111195 | 931 | |
d5494d4f YL |
932 | unsigned long kernel_eflags; |
933 | ||
934 | /* | |
935 | * Copies of the original ist values from the tss are only accessed during | |
936 | * debugging, no special alignment required. | |
937 | */ | |
938 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
939 | ||
940 | #else | |
941 | ||
7c3576d2 | 942 | /* Make sure %fs is initialized properly in idle threads */ |
6b2fb3c6 | 943 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
944 | { |
945 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 946 | regs->fs = __KERNEL_PERCPU; |
f95d47ca JF |
947 | return regs; |
948 | } | |
d5494d4f | 949 | #endif |
c5413fbe | 950 | |
d2cbcc49 RR |
951 | /* |
952 | * cpu_init() initializes state that is per-CPU. Some data is already | |
953 | * initialized (naturally) in the bootstrap process, such as the GDT | |
954 | * and IDT. We reload them nevertheless, this function acts as a | |
955 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 956 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 957 | */ |
1ba76586 YL |
958 | #ifdef CONFIG_X86_64 |
959 | void __cpuinit cpu_init(void) | |
960 | { | |
961 | int cpu = stack_smp_processor_id(); | |
962 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
963 | struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); | |
964 | unsigned long v; | |
965 | char *estacks = NULL; | |
966 | struct task_struct *me; | |
967 | int i; | |
968 | ||
969 | /* CPU 0 is initialised in head64.c */ | |
970 | if (cpu != 0) | |
971 | pda_init(cpu); | |
972 | else | |
973 | estacks = boot_exception_stacks; | |
974 | ||
975 | me = current; | |
976 | ||
977 | if (cpu_test_and_set(cpu, cpu_initialized)) | |
978 | panic("CPU#%d already initialized!\n", cpu); | |
979 | ||
980 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
981 | ||
982 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
983 | ||
984 | /* | |
985 | * Initialize the per-CPU GDT with the boot GDT, | |
986 | * and set up the GDT descriptor: | |
987 | */ | |
988 | ||
989 | switch_to_new_gdt(); | |
990 | load_idt((const struct desc_ptr *)&idt_descr); | |
991 | ||
992 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
993 | syscall_init(); | |
994 | ||
995 | wrmsrl(MSR_FS_BASE, 0); | |
996 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
997 | barrier(); | |
998 | ||
999 | check_efer(); | |
1000 | if (cpu != 0 && x2apic) | |
1001 | enable_x2apic(); | |
1002 | ||
1003 | /* | |
1004 | * set up and load the per-CPU TSS | |
1005 | */ | |
1006 | if (!orig_ist->ist[0]) { | |
1007 | static const unsigned int order[N_EXCEPTION_STACKS] = { | |
1008 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER, | |
1009 | [DEBUG_STACK - 1] = DEBUG_STACK_ORDER | |
1010 | }; | |
1011 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { | |
1012 | if (cpu) { | |
1013 | estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]); | |
1014 | if (!estacks) | |
1015 | panic("Cannot allocate exception " | |
1016 | "stack %ld %d\n", v, cpu); | |
1017 | } | |
1018 | estacks += PAGE_SIZE << order[v]; | |
1019 | orig_ist->ist[v] = t->x86_tss.ist[v] = | |
1020 | (unsigned long)estacks; | |
1021 | } | |
1022 | } | |
1023 | ||
1024 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
1025 | /* | |
1026 | * <= is required because the CPU will access up to | |
1027 | * 8 bits beyond the end of the IO permission bitmap. | |
1028 | */ | |
1029 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1030 | t->io_bitmap[i] = ~0UL; | |
1031 | ||
1032 | atomic_inc(&init_mm.mm_count); | |
1033 | me->active_mm = &init_mm; | |
1034 | if (me->mm) | |
1035 | BUG(); | |
1036 | enter_lazy_tlb(&init_mm, me); | |
1037 | ||
1038 | load_sp0(t, ¤t->thread); | |
1039 | set_tss_desc(cpu, t); | |
1040 | load_TR_desc(); | |
1041 | load_LDT(&init_mm.context); | |
1042 | ||
1043 | #ifdef CONFIG_KGDB | |
1044 | /* | |
1045 | * If the kgdb is connected no debug regs should be altered. This | |
1046 | * is only applicable when KGDB and a KGDB I/O module are built | |
1047 | * into the kernel and you are using early debugging with | |
1048 | * kgdbwait. KGDB will control the kernel HW breakpoint registers. | |
1049 | */ | |
1050 | if (kgdb_connected && arch_kgdb_ops.correct_hw_break) | |
1051 | arch_kgdb_ops.correct_hw_break(); | |
1052 | else { | |
1053 | #endif | |
1054 | /* | |
1055 | * Clear all 6 debug registers: | |
1056 | */ | |
1057 | ||
1058 | set_debugreg(0UL, 0); | |
1059 | set_debugreg(0UL, 1); | |
1060 | set_debugreg(0UL, 2); | |
1061 | set_debugreg(0UL, 3); | |
1062 | set_debugreg(0UL, 6); | |
1063 | set_debugreg(0UL, 7); | |
1064 | #ifdef CONFIG_KGDB | |
1065 | /* If the kgdb is connected no debug regs should be altered. */ | |
1066 | } | |
1067 | #endif | |
1068 | ||
1069 | fpu_init(); | |
1070 | ||
1071 | raw_local_save_flags(kernel_eflags); | |
1072 | ||
1073 | if (is_uv_system()) | |
1074 | uv_cpu_init(); | |
1075 | } | |
1076 | ||
1077 | #else | |
1078 | ||
d2cbcc49 | 1079 | void __cpuinit cpu_init(void) |
9ee79a3d | 1080 | { |
d2cbcc49 RR |
1081 | int cpu = smp_processor_id(); |
1082 | struct task_struct *curr = current; | |
34048c9e | 1083 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1084 | struct thread_struct *thread = &curr->thread; |
62111195 JF |
1085 | |
1086 | if (cpu_test_and_set(cpu, cpu_initialized)) { | |
1087 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); | |
1088 | for (;;) local_irq_enable(); | |
1089 | } | |
1090 | ||
1091 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1092 | ||
1093 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1094 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1095 | |
4d37e7e3 | 1096 | load_idt(&idt_descr); |
c5413fbe | 1097 | switch_to_new_gdt(); |
1da177e4 | 1098 | |
1da177e4 LT |
1099 | /* |
1100 | * Set up and load the per-CPU TSS and LDT | |
1101 | */ | |
1102 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
1103 | curr->active_mm = &init_mm; |
1104 | if (curr->mm) | |
1105 | BUG(); | |
1106 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 | 1107 | |
faca6227 | 1108 | load_sp0(t, thread); |
34048c9e | 1109 | set_tss_desc(cpu, t); |
1da177e4 LT |
1110 | load_TR_desc(); |
1111 | load_LDT(&init_mm.context); | |
1112 | ||
22c4e308 | 1113 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1114 | /* Set up doublefault TSS pointer in the GDT */ |
1115 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1116 | #endif |
1da177e4 | 1117 | |
464d1a78 JF |
1118 | /* Clear %gs. */ |
1119 | asm volatile ("mov %0, %%gs" : : "r" (0)); | |
1da177e4 LT |
1120 | |
1121 | /* Clear all 6 debug registers: */ | |
4bb0d3ec ZA |
1122 | set_debugreg(0, 0); |
1123 | set_debugreg(0, 1); | |
1124 | set_debugreg(0, 2); | |
1125 | set_debugreg(0, 3); | |
1126 | set_debugreg(0, 6); | |
1127 | set_debugreg(0, 7); | |
1da177e4 LT |
1128 | |
1129 | /* | |
1130 | * Force FPU initialization: | |
1131 | */ | |
b359e8a4 SS |
1132 | if (cpu_has_xsave) |
1133 | current_thread_info()->status = TS_XSAVE; | |
1134 | else | |
1135 | current_thread_info()->status = 0; | |
1da177e4 LT |
1136 | clear_used_math(); |
1137 | mxcsr_feature_mask_init(); | |
dc1e35c6 SS |
1138 | |
1139 | /* | |
1140 | * Boot processor to setup the FP and extended state context info. | |
1141 | */ | |
b3572e36 | 1142 | if (smp_processor_id() == boot_cpu_id) |
dc1e35c6 SS |
1143 | init_thread_xstate(); |
1144 | ||
1145 | xsave_init(); | |
1da177e4 | 1146 | } |
e1367daf | 1147 | |
1ba76586 YL |
1148 | |
1149 | #endif |