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1da177e4 LT |
1 | #include <linux/kernel.h> |
2 | ||
3 | #include <linux/string.h> | |
4 | #include <linux/bitops.h> | |
5 | #include <linux/smp.h> | |
83ce4009 | 6 | #include <linux/sched.h> |
1da177e4 | 7 | #include <linux/thread_info.h> |
53e86b91 | 8 | #include <linux/module.h> |
8bdbd962 | 9 | #include <linux/uaccess.h> |
1da177e4 LT |
10 | |
11 | #include <asm/processor.h> | |
d72b1b4f | 12 | #include <asm/pgtable.h> |
1da177e4 | 13 | #include <asm/msr.h> |
73bdb73f | 14 | #include <asm/bugs.h> |
1f442d70 | 15 | #include <asm/cpu.h> |
1da177e4 | 16 | |
185f3b9d | 17 | #ifdef CONFIG_X86_64 |
8bdbd962 | 18 | #include <linux/topology.h> |
185f3b9d YL |
19 | #endif |
20 | ||
1da177e4 LT |
21 | #include "cpu.h" |
22 | ||
23 | #ifdef CONFIG_X86_LOCAL_APIC | |
24 | #include <asm/mpspec.h> | |
25 | #include <asm/apic.h> | |
1da177e4 LT |
26 | #endif |
27 | ||
148f9bb8 | 28 | static void early_init_intel(struct cpuinfo_x86 *c) |
1da177e4 | 29 | { |
161ec53c FY |
30 | u64 misc_enable; |
31 | ||
99fb4d34 | 32 | /* Unmask CPUID levels if masked: */ |
30a0fb94 | 33 | if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { |
0b131be8 PA |
34 | if (msr_clear_bit(MSR_IA32_MISC_ENABLE, |
35 | MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) { | |
99fb4d34 | 36 | c->cpuid_level = cpuid_eax(0); |
d900329e | 37 | get_cpu_cap(c); |
99fb4d34 | 38 | } |
066941bd PA |
39 | } |
40 | ||
2b16a235 AK |
41 | if ((c->x86 == 0xf && c->x86_model >= 0x03) || |
42 | (c->x86 == 0x6 && c->x86_model >= 0x0e)) | |
43 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | |
185f3b9d | 44 | |
506ed6b5 AK |
45 | if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) { |
46 | unsigned lower_word; | |
47 | ||
48 | wrmsr(MSR_IA32_UCODE_REV, 0, 0); | |
49 | /* Required by the SDM */ | |
50 | sync_core(); | |
51 | rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode); | |
52 | } | |
53 | ||
7a0fc404 PA |
54 | /* |
55 | * Atom erratum AAE44/AAF40/AAG38/AAH41: | |
56 | * | |
57 | * A race condition between speculative fetches and invalidating | |
58 | * a large page. This is worked around in microcode, but we | |
59 | * need the microcode to have already been loaded... so if it is | |
60 | * not, recommend a BIOS update and disable large pages. | |
61 | */ | |
30963c0a AK |
62 | if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 && |
63 | c->microcode < 0x20e) { | |
64 | printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n"); | |
65 | clear_cpu_cap(c, X86_FEATURE_PSE); | |
7a0fc404 PA |
66 | } |
67 | ||
185f3b9d YL |
68 | #ifdef CONFIG_X86_64 |
69 | set_cpu_cap(c, X86_FEATURE_SYSENTER32); | |
70 | #else | |
71 | /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ | |
72 | if (c->x86 == 15 && c->x86_cache_alignment == 64) | |
73 | c->x86_cache_alignment = 128; | |
74 | #endif | |
40fb1715 | 75 | |
13c6c532 JB |
76 | /* CPUID workaround for 0F33/0F34 CPU */ |
77 | if (c->x86 == 0xF && c->x86_model == 0x3 | |
78 | && (c->x86_mask == 0x3 || c->x86_mask == 0x4)) | |
79 | c->x86_phys_bits = 36; | |
80 | ||
40fb1715 VP |
81 | /* |
82 | * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate | |
83ce4009 IM |
83 | * with P/T states and does not stop in deep C-states. |
84 | * | |
85 | * It is also reliable across cores and sockets. (but not across | |
86 | * cabinets - we turn it off in that case explicitly.) | |
40fb1715 VP |
87 | */ |
88 | if (c->x86_power & (1 << 8)) { | |
89 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | |
90 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); | |
14be1f74 | 91 | if (!check_tsc_unstable()) |
35af99e6 | 92 | set_sched_clock_stable(); |
40fb1715 VP |
93 | } |
94 | ||
c54fdbb2 FT |
95 | /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ |
96 | if (c->x86 == 6) { | |
97 | switch (c->x86_model) { | |
98 | case 0x27: /* Penwell */ | |
99 | case 0x35: /* Cloverview */ | |
100 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); | |
101 | break; | |
102 | default: | |
103 | break; | |
104 | } | |
105 | } | |
106 | ||
75a04811 PA |
107 | /* |
108 | * There is a known erratum on Pentium III and Core Solo | |
109 | * and Core Duo CPUs. | |
110 | * " Page with PAT set to WC while associated MTRR is UC | |
111 | * may consolidate to UC " | |
112 | * Because of this erratum, it is better to stick with | |
113 | * setting WC in MTRR rather than using PAT on these CPUs. | |
114 | * | |
115 | * Enable PAT WC only on P4, Core 2 or later CPUs. | |
116 | */ | |
117 | if (c->x86 == 6 && c->x86_model < 15) | |
118 | clear_cpu_cap(c, X86_FEATURE_PAT); | |
f8561296 VN |
119 | |
120 | #ifdef CONFIG_KMEMCHECK | |
121 | /* | |
122 | * P4s have a "fast strings" feature which causes single- | |
123 | * stepping REP instructions to only generate a #DB on | |
124 | * cache-line boundaries. | |
125 | * | |
126 | * Ingo Molnar reported a Pentium D (model 6) and a Xeon | |
127 | * (model 2) with the same problem. | |
128 | */ | |
c0a639ad | 129 | if (c->x86 == 15) |
0b131be8 PA |
130 | if (msr_clear_bit(MSR_IA32_MISC_ENABLE, |
131 | MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) > 0) | |
c0a639ad | 132 | pr_info("kmemcheck: Disabling fast string operations\n"); |
f8561296 | 133 | #endif |
161ec53c FY |
134 | |
135 | /* | |
136 | * If fast string is not enabled in IA32_MISC_ENABLE for any reason, | |
137 | * clear the fast string and enhanced fast string CPU capabilities. | |
138 | */ | |
139 | if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { | |
140 | rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); | |
141 | if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) { | |
142 | printk(KERN_INFO "Disabled fast string operations\n"); | |
143 | setup_clear_cpu_cap(X86_FEATURE_REP_GOOD); | |
144 | setup_clear_cpu_cap(X86_FEATURE_ERMS); | |
145 | } | |
146 | } | |
ee1b5b16 BD |
147 | |
148 | /* | |
149 | * Intel Quark Core DevMan_001.pdf section 6.4.11 | |
150 | * "The operating system also is required to invalidate (i.e., flush) | |
151 | * the TLB when any changes are made to any of the page table entries. | |
152 | * The operating system must reload CR3 to cause the TLB to be flushed" | |
153 | * | |
154 | * As a result cpu_has_pge() in arch/x86/include/asm/tlbflush.h should | |
155 | * be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE | |
156 | * to be modified | |
157 | */ | |
158 | if (c->x86 == 5 && c->x86_model == 9) { | |
159 | pr_info("Disabling PGE capability bit\n"); | |
160 | setup_clear_cpu_cap(X86_FEATURE_PGE); | |
161 | } | |
1da177e4 LT |
162 | } |
163 | ||
185f3b9d | 164 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
165 | /* |
166 | * Early probe support logic for ppro memory erratum #50 | |
167 | * | |
168 | * This is called before we do cpu ident work | |
169 | */ | |
65eb6b43 | 170 | |
148f9bb8 | 171 | int ppro_with_ram_bug(void) |
1da177e4 LT |
172 | { |
173 | /* Uses data from early_cpu_detect now */ | |
174 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
175 | boot_cpu_data.x86 == 6 && | |
176 | boot_cpu_data.x86_model == 1 && | |
177 | boot_cpu_data.x86_mask < 8) { | |
178 | printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n"); | |
179 | return 1; | |
180 | } | |
181 | return 0; | |
182 | } | |
65eb6b43 | 183 | |
148f9bb8 | 184 | static void intel_smp_check(struct cpuinfo_x86 *c) |
1f442d70 | 185 | { |
1f442d70 | 186 | /* calling is from identify_secondary_cpu() ? */ |
f6e9456c | 187 | if (!c->cpu_index) |
1f442d70 YL |
188 | return; |
189 | ||
190 | /* | |
191 | * Mask B, Pentium, but not Pentium MMX | |
192 | */ | |
193 | if (c->x86 == 5 && | |
194 | c->x86_mask >= 1 && c->x86_mask <= 4 && | |
195 | c->x86_model <= 3) { | |
196 | /* | |
197 | * Remember we have B step Pentia with bugs | |
198 | */ | |
199 | WARN_ONCE(1, "WARNING: SMP operation may be unreliable" | |
200 | "with B stepping processors.\n"); | |
201 | } | |
1f442d70 YL |
202 | } |
203 | ||
69f2366c CB |
204 | static int forcepae; |
205 | static int __init forcepae_setup(char *__unused) | |
206 | { | |
207 | forcepae = 1; | |
208 | return 1; | |
209 | } | |
210 | __setup("forcepae", forcepae_setup); | |
211 | ||
148f9bb8 | 212 | static void intel_workarounds(struct cpuinfo_x86 *c) |
1da177e4 | 213 | { |
4052704d YL |
214 | #ifdef CONFIG_X86_F00F_BUG |
215 | /* | |
216 | * All current models of Pentium and Pentium with MMX technology CPUs | |
8bdbd962 | 217 | * have the F0 0F bug, which lets nonprivileged users lock up the |
4eefbe79 | 218 | * system. Announce that the fault handler will be checking for it. |
4052704d | 219 | */ |
e2604b49 | 220 | clear_cpu_bug(c, X86_BUG_F00F); |
4052704d YL |
221 | if (!paravirt_enabled() && c->x86 == 5) { |
222 | static int f00f_workaround_enabled; | |
223 | ||
e2604b49 | 224 | set_cpu_bug(c, X86_BUG_F00F); |
4052704d | 225 | if (!f00f_workaround_enabled) { |
4052704d YL |
226 | printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n"); |
227 | f00f_workaround_enabled = 1; | |
228 | } | |
229 | } | |
230 | #endif | |
231 | ||
232 | /* | |
233 | * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until | |
234 | * model 3 mask 3 | |
235 | */ | |
236 | if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633) | |
237 | clear_cpu_cap(c, X86_FEATURE_SEP); | |
238 | ||
69f2366c CB |
239 | /* |
240 | * PAE CPUID issue: many Pentium M report no PAE but may have a | |
241 | * functionally usable PAE implementation. | |
242 | * Forcefully enable PAE if kernel parameter "forcepae" is present. | |
243 | */ | |
244 | if (forcepae) { | |
245 | printk(KERN_WARNING "PAE forced!\n"); | |
246 | set_cpu_cap(c, X86_FEATURE_PAE); | |
247 | add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); | |
248 | } | |
249 | ||
4052704d YL |
250 | /* |
251 | * P4 Xeon errata 037 workaround. | |
252 | * Hardware prefetcher may cause stale data to be loaded into the cache. | |
253 | */ | |
1da177e4 | 254 | if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) { |
0b131be8 PA |
255 | if (msr_set_bit(MSR_IA32_MISC_ENABLE, |
256 | MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) | |
257 | > 0) { | |
c0a639ad BP |
258 | pr_info("CPU: C0 stepping P4 Xeon detected.\n"); |
259 | pr_info("CPU: Disabling hardware prefetching (Errata 037)\n"); | |
1da177e4 LT |
260 | } |
261 | } | |
1da177e4 | 262 | |
4052704d YL |
263 | /* |
264 | * See if we have a good local APIC by checking for buggy Pentia, | |
265 | * i.e. all B steppings and the C2 stepping of P54C when using their | |
266 | * integrated APIC (see 11AP erratum in "Pentium Processor | |
267 | * Specification Update"). | |
268 | */ | |
269 | if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 && | |
270 | (c->x86_mask < 0x6 || c->x86_mask == 0xb)) | |
9b13a93d | 271 | set_cpu_bug(c, X86_BUG_11AP); |
185f3b9d | 272 | |
185f3b9d | 273 | |
4052704d | 274 | #ifdef CONFIG_X86_INTEL_USERCOPY |
185f3b9d | 275 | /* |
4052704d | 276 | * Set up the preferred alignment for movsl bulk memory moves |
185f3b9d | 277 | */ |
4052704d YL |
278 | switch (c->x86) { |
279 | case 4: /* 486: untested */ | |
280 | break; | |
281 | case 5: /* Old Pentia: untested */ | |
282 | break; | |
283 | case 6: /* PII/PIII only like movsl with 8-byte alignment */ | |
284 | movsl_mask.mask = 7; | |
285 | break; | |
286 | case 15: /* P4 is OK down to 8-byte alignment */ | |
287 | movsl_mask.mask = 7; | |
288 | break; | |
289 | } | |
185f3b9d | 290 | #endif |
4052704d | 291 | |
1f442d70 | 292 | intel_smp_check(c); |
4052704d YL |
293 | } |
294 | #else | |
148f9bb8 | 295 | static void intel_workarounds(struct cpuinfo_x86 *c) |
4052704d YL |
296 | { |
297 | } | |
185f3b9d YL |
298 | #endif |
299 | ||
148f9bb8 | 300 | static void srat_detect_node(struct cpuinfo_x86 *c) |
185f3b9d | 301 | { |
645a7919 | 302 | #ifdef CONFIG_NUMA |
185f3b9d YL |
303 | unsigned node; |
304 | int cpu = smp_processor_id(); | |
185f3b9d YL |
305 | |
306 | /* Don't do the funky fallback heuristics the AMD version employs | |
307 | for now. */ | |
bbc9e2f4 | 308 | node = numa_cpu_node(cpu); |
50f2d7f6 | 309 | if (node == NUMA_NO_NODE || !node_online(node)) { |
d9c2d5ac YL |
310 | /* reuse the value from init_cpu_to_node() */ |
311 | node = cpu_to_node(cpu); | |
312 | } | |
185f3b9d | 313 | numa_set_node(cpu, node); |
185f3b9d YL |
314 | #endif |
315 | } | |
316 | ||
3dd9d514 AK |
317 | /* |
318 | * find out the number of processor cores on the die | |
319 | */ | |
148f9bb8 | 320 | static int intel_num_cpu_cores(struct cpuinfo_x86 *c) |
3dd9d514 | 321 | { |
f2ab4461 | 322 | unsigned int eax, ebx, ecx, edx; |
3dd9d514 AK |
323 | |
324 | if (c->cpuid_level < 4) | |
325 | return 1; | |
326 | ||
f2ab4461 ZA |
327 | /* Intel has a non-standard dependency on %ecx for this CPUID level. */ |
328 | cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); | |
3dd9d514 | 329 | if (eax & 0x1f) |
8bdbd962 | 330 | return (eax >> 26) + 1; |
3dd9d514 AK |
331 | else |
332 | return 1; | |
333 | } | |
334 | ||
148f9bb8 | 335 | static void detect_vmx_virtcap(struct cpuinfo_x86 *c) |
e38e05a8 SY |
336 | { |
337 | /* Intel VMX MSR indicated features */ | |
338 | #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000 | |
339 | #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000 | |
340 | #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000 | |
341 | #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001 | |
342 | #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002 | |
343 | #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020 | |
344 | ||
345 | u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2; | |
346 | ||
347 | clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW); | |
348 | clear_cpu_cap(c, X86_FEATURE_VNMI); | |
349 | clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); | |
350 | clear_cpu_cap(c, X86_FEATURE_EPT); | |
351 | clear_cpu_cap(c, X86_FEATURE_VPID); | |
352 | ||
353 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high); | |
354 | msr_ctl = vmx_msr_high | vmx_msr_low; | |
355 | if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW) | |
356 | set_cpu_cap(c, X86_FEATURE_TPR_SHADOW); | |
357 | if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI) | |
358 | set_cpu_cap(c, X86_FEATURE_VNMI); | |
359 | if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) { | |
360 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, | |
361 | vmx_msr_low, vmx_msr_high); | |
362 | msr_ctl2 = vmx_msr_high | vmx_msr_low; | |
363 | if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) && | |
364 | (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)) | |
365 | set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); | |
366 | if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT) | |
367 | set_cpu_cap(c, X86_FEATURE_EPT); | |
368 | if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID) | |
369 | set_cpu_cap(c, X86_FEATURE_VPID); | |
370 | } | |
371 | } | |
372 | ||
148f9bb8 | 373 | static void init_intel(struct cpuinfo_x86 *c) |
1da177e4 LT |
374 | { |
375 | unsigned int l2 = 0; | |
1da177e4 | 376 | |
2b16a235 AK |
377 | early_init_intel(c); |
378 | ||
4052704d | 379 | intel_workarounds(c); |
1da177e4 | 380 | |
345077cd SS |
381 | /* |
382 | * Detect the extended topology information if available. This | |
383 | * will reinitialise the initial_apicid which will be used | |
384 | * in init_intel_cacheinfo() | |
385 | */ | |
386 | detect_extended_topology(c); | |
387 | ||
2a226155 PZ |
388 | if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { |
389 | /* | |
390 | * let's use the legacy cpuid vector 0x1 and 0x4 for topology | |
391 | * detection. | |
392 | */ | |
393 | c->x86_max_cores = intel_num_cpu_cores(c); | |
394 | #ifdef CONFIG_X86_32 | |
395 | detect_ht(c); | |
396 | #endif | |
397 | } | |
398 | ||
1da177e4 | 399 | l2 = init_intel_cacheinfo(c); |
aece118e BD |
400 | |
401 | /* Detect legacy cache sizes if init_intel_cacheinfo did not */ | |
402 | if (l2 == 0) { | |
403 | cpu_detect_cache_sizes(c); | |
404 | l2 = c->x86_cache_size; | |
405 | } | |
406 | ||
65eb6b43 | 407 | if (c->cpuid_level > 9) { |
0080e667 VP |
408 | unsigned eax = cpuid_eax(10); |
409 | /* Check for version and the number of counters */ | |
410 | if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) | |
d0e95ebd | 411 | set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); |
0080e667 | 412 | } |
1da177e4 | 413 | |
4052704d YL |
414 | if (cpu_has_xmm2) |
415 | set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); | |
416 | if (cpu_has_ds) { | |
417 | unsigned int l1; | |
418 | rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); | |
419 | if (!(l1 & (1<<11))) | |
420 | set_cpu_cap(c, X86_FEATURE_BTS); | |
421 | if (!(l1 & (1<<12))) | |
422 | set_cpu_cap(c, X86_FEATURE_PEBS); | |
4052704d | 423 | } |
1da177e4 | 424 | |
40e2d7f9 LB |
425 | if (c->x86 == 6 && cpu_has_clflush && |
426 | (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47)) | |
9b13a93d | 427 | set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); |
e736ad54 | 428 | |
4052704d YL |
429 | #ifdef CONFIG_X86_64 |
430 | if (c->x86 == 15) | |
431 | c->x86_cache_alignment = c->x86_clflush_size * 2; | |
432 | if (c->x86 == 6) | |
433 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | |
434 | #else | |
65eb6b43 PC |
435 | /* |
436 | * Names for the Pentium II/Celeron processors | |
437 | * detectable only by also checking the cache size. | |
438 | * Dixon is NOT a Celeron. | |
439 | */ | |
1da177e4 | 440 | if (c->x86 == 6) { |
4052704d YL |
441 | char *p = NULL; |
442 | ||
1da177e4 LT |
443 | switch (c->x86_model) { |
444 | case 5: | |
865be7a8 OZ |
445 | if (l2 == 0) |
446 | p = "Celeron (Covington)"; | |
447 | else if (l2 == 256) | |
448 | p = "Mobile Pentium II (Dixon)"; | |
1da177e4 | 449 | break; |
65eb6b43 | 450 | |
1da177e4 LT |
451 | case 6: |
452 | if (l2 == 128) | |
453 | p = "Celeron (Mendocino)"; | |
454 | else if (c->x86_mask == 0 || c->x86_mask == 5) | |
455 | p = "Celeron-A"; | |
456 | break; | |
65eb6b43 | 457 | |
1da177e4 LT |
458 | case 8: |
459 | if (l2 == 128) | |
460 | p = "Celeron (Coppermine)"; | |
461 | break; | |
462 | } | |
1da177e4 | 463 | |
4052704d YL |
464 | if (p) |
465 | strcpy(c->x86_model_id, p); | |
1da177e4 | 466 | } |
1da177e4 | 467 | |
185f3b9d YL |
468 | if (c->x86 == 15) |
469 | set_cpu_cap(c, X86_FEATURE_P4); | |
470 | if (c->x86 == 6) | |
471 | set_cpu_cap(c, X86_FEATURE_P3); | |
f4166c54 | 472 | #endif |
185f3b9d | 473 | |
185f3b9d | 474 | /* Work around errata */ |
2759c328 | 475 | srat_detect_node(c); |
e38e05a8 SY |
476 | |
477 | if (cpu_has(c, X86_FEATURE_VMX)) | |
478 | detect_vmx_virtcap(c); | |
abe48b10 LB |
479 | |
480 | /* | |
481 | * Initialize MSR_IA32_ENERGY_PERF_BIAS if BIOS did not. | |
482 | * x86_energy_perf_policy(8) is available to change it at run-time | |
483 | */ | |
484 | if (cpu_has(c, X86_FEATURE_EPB)) { | |
485 | u64 epb; | |
486 | ||
487 | rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); | |
17edf2d7 LB |
488 | if ((epb & 0xF) == ENERGY_PERF_BIAS_PERFORMANCE) { |
489 | printk_once(KERN_WARNING "ENERGY_PERF_BIAS:" | |
490 | " Set to 'normal', was 'performance'\n" | |
491 | "ENERGY_PERF_BIAS: View and update with" | |
492 | " x86_energy_perf_policy(8)\n"); | |
abe48b10 LB |
493 | epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL; |
494 | wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); | |
495 | } | |
496 | } | |
42ed458a | 497 | } |
1da177e4 | 498 | |
185f3b9d | 499 | #ifdef CONFIG_X86_32 |
148f9bb8 | 500 | static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) |
1da177e4 | 501 | { |
65eb6b43 PC |
502 | /* |
503 | * Intel PIII Tualatin. This comes in two flavours. | |
1da177e4 LT |
504 | * One has 256kb of cache, the other 512. We have no way |
505 | * to determine which, so we use a boottime override | |
506 | * for the 512kb model, and assume 256 otherwise. | |
507 | */ | |
508 | if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) | |
509 | size = 256; | |
aece118e BD |
510 | |
511 | /* | |
512 | * Intel Quark SoC X1000 contains a 4-way set associative | |
513 | * 16K cache with a 16 byte cache line and 256 lines per tag | |
514 | */ | |
515 | if ((c->x86 == 5) && (c->x86_model == 9)) | |
516 | size = 16; | |
1da177e4 LT |
517 | return size; |
518 | } | |
185f3b9d | 519 | #endif |
1da177e4 | 520 | |
e0ba94f1 AS |
521 | #define TLB_INST_4K 0x01 |
522 | #define TLB_INST_4M 0x02 | |
523 | #define TLB_INST_2M_4M 0x03 | |
524 | ||
525 | #define TLB_INST_ALL 0x05 | |
526 | #define TLB_INST_1G 0x06 | |
527 | ||
528 | #define TLB_DATA_4K 0x11 | |
529 | #define TLB_DATA_4M 0x12 | |
530 | #define TLB_DATA_2M_4M 0x13 | |
531 | #define TLB_DATA_4K_4M 0x14 | |
532 | ||
533 | #define TLB_DATA_1G 0x16 | |
534 | ||
535 | #define TLB_DATA0_4K 0x21 | |
536 | #define TLB_DATA0_4M 0x22 | |
537 | #define TLB_DATA0_2M_4M 0x23 | |
538 | ||
539 | #define STLB_4K 0x41 | |
dd360393 | 540 | #define STLB_4K_2M 0x42 |
e0ba94f1 | 541 | |
148f9bb8 | 542 | static const struct _tlb_table intel_tlb_table[] = { |
e0ba94f1 AS |
543 | { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" }, |
544 | { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" }, | |
545 | { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" }, | |
546 | { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" }, | |
547 | { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" }, | |
548 | { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" }, | |
549 | { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" }, | |
550 | { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, | |
551 | { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, | |
552 | { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, | |
553 | { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, | |
554 | { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" }, | |
555 | { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" }, | |
556 | { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" }, | |
557 | { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" }, | |
558 | { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" }, | |
559 | { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" }, | |
560 | { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" }, | |
dd360393 KS |
561 | { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" }, |
562 | { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" }, | |
563 | { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, | |
e0ba94f1 AS |
564 | { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" }, |
565 | { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" }, | |
566 | { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" }, | |
567 | { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" }, | |
568 | { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" }, | |
dd360393 KS |
569 | { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set ssociative" }, |
570 | { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set ssociative" }, | |
e0ba94f1 AS |
571 | { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" }, |
572 | { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" }, | |
dd360393 KS |
573 | { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" }, |
574 | { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" }, | |
e0ba94f1 AS |
575 | { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" }, |
576 | { 0x00, 0, 0 } | |
577 | }; | |
578 | ||
148f9bb8 | 579 | static void intel_tlb_lookup(const unsigned char desc) |
e0ba94f1 AS |
580 | { |
581 | unsigned char k; | |
582 | if (desc == 0) | |
583 | return; | |
584 | ||
585 | /* look up this descriptor in the table */ | |
586 | for (k = 0; intel_tlb_table[k].descriptor != desc && \ | |
587 | intel_tlb_table[k].descriptor != 0; k++) | |
588 | ; | |
589 | ||
590 | if (intel_tlb_table[k].tlb_type == 0) | |
591 | return; | |
592 | ||
593 | switch (intel_tlb_table[k].tlb_type) { | |
594 | case STLB_4K: | |
595 | if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) | |
596 | tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; | |
597 | if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) | |
598 | tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; | |
599 | break; | |
dd360393 KS |
600 | case STLB_4K_2M: |
601 | if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) | |
602 | tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; | |
603 | if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) | |
604 | tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; | |
605 | if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) | |
606 | tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; | |
607 | if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) | |
608 | tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; | |
609 | if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) | |
610 | tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; | |
611 | if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) | |
612 | tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; | |
613 | break; | |
e0ba94f1 AS |
614 | case TLB_INST_ALL: |
615 | if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) | |
616 | tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; | |
617 | if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) | |
618 | tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; | |
619 | if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) | |
620 | tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; | |
621 | break; | |
622 | case TLB_INST_4K: | |
623 | if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) | |
624 | tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; | |
625 | break; | |
626 | case TLB_INST_4M: | |
627 | if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) | |
628 | tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; | |
629 | break; | |
630 | case TLB_INST_2M_4M: | |
631 | if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) | |
632 | tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; | |
633 | if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) | |
634 | tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; | |
635 | break; | |
636 | case TLB_DATA_4K: | |
637 | case TLB_DATA0_4K: | |
638 | if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) | |
639 | tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; | |
640 | break; | |
641 | case TLB_DATA_4M: | |
642 | case TLB_DATA0_4M: | |
643 | if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) | |
644 | tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; | |
645 | break; | |
646 | case TLB_DATA_2M_4M: | |
647 | case TLB_DATA0_2M_4M: | |
648 | if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) | |
649 | tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; | |
650 | if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) | |
651 | tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; | |
652 | break; | |
653 | case TLB_DATA_4K_4M: | |
654 | if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) | |
655 | tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; | |
656 | if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) | |
657 | tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; | |
658 | break; | |
dd360393 KS |
659 | case TLB_DATA_1G: |
660 | if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries) | |
661 | tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries; | |
e0ba94f1 AS |
662 | break; |
663 | } | |
664 | } | |
665 | ||
148f9bb8 | 666 | static void intel_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
667 | { |
668 | int i, j, n; | |
669 | unsigned int regs[4]; | |
670 | unsigned char *desc = (unsigned char *)regs; | |
5b556332 BP |
671 | |
672 | if (c->cpuid_level < 2) | |
673 | return; | |
674 | ||
e0ba94f1 AS |
675 | /* Number of times to iterate */ |
676 | n = cpuid_eax(2) & 0xFF; | |
677 | ||
678 | for (i = 0 ; i < n ; i++) { | |
679 | cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]); | |
680 | ||
681 | /* If bit 31 is set, this is an unknown format */ | |
682 | for (j = 0 ; j < 3 ; j++) | |
683 | if (regs[j] & (1 << 31)) | |
684 | regs[j] = 0; | |
685 | ||
686 | /* Byte 0 is level count, not a descriptor */ | |
687 | for (j = 1 ; j < 16 ; j++) | |
688 | intel_tlb_lookup(desc[j]); | |
689 | } | |
690 | } | |
691 | ||
148f9bb8 | 692 | static const struct cpu_dev intel_cpu_dev = { |
1da177e4 | 693 | .c_vendor = "Intel", |
65eb6b43 | 694 | .c_ident = { "GenuineIntel" }, |
185f3b9d | 695 | #ifdef CONFIG_X86_32 |
09dc68d9 JB |
696 | .legacy_models = { |
697 | { .family = 4, .model_names = | |
65eb6b43 PC |
698 | { |
699 | [0] = "486 DX-25/33", | |
700 | [1] = "486 DX-50", | |
701 | [2] = "486 SX", | |
702 | [3] = "486 DX/2", | |
703 | [4] = "486 SL", | |
704 | [5] = "486 SX/2", | |
705 | [7] = "486 DX/2-WB", | |
706 | [8] = "486 DX/4", | |
1da177e4 LT |
707 | [9] = "486 DX/4-WB" |
708 | } | |
709 | }, | |
09dc68d9 | 710 | { .family = 5, .model_names = |
65eb6b43 PC |
711 | { |
712 | [0] = "Pentium 60/66 A-step", | |
713 | [1] = "Pentium 60/66", | |
1da177e4 | 714 | [2] = "Pentium 75 - 200", |
65eb6b43 | 715 | [3] = "OverDrive PODP5V83", |
1da177e4 | 716 | [4] = "Pentium MMX", |
65eb6b43 | 717 | [7] = "Mobile Pentium 75 - 200", |
aece118e BD |
718 | [8] = "Mobile Pentium MMX", |
719 | [9] = "Quark SoC X1000", | |
1da177e4 LT |
720 | } |
721 | }, | |
09dc68d9 | 722 | { .family = 6, .model_names = |
65eb6b43 | 723 | { |
1da177e4 | 724 | [0] = "Pentium Pro A-step", |
65eb6b43 PC |
725 | [1] = "Pentium Pro", |
726 | [3] = "Pentium II (Klamath)", | |
727 | [4] = "Pentium II (Deschutes)", | |
728 | [5] = "Pentium II (Deschutes)", | |
1da177e4 | 729 | [6] = "Mobile Pentium II", |
65eb6b43 PC |
730 | [7] = "Pentium III (Katmai)", |
731 | [8] = "Pentium III (Coppermine)", | |
1da177e4 LT |
732 | [10] = "Pentium III (Cascades)", |
733 | [11] = "Pentium III (Tualatin)", | |
734 | } | |
735 | }, | |
09dc68d9 | 736 | { .family = 15, .model_names = |
1da177e4 LT |
737 | { |
738 | [0] = "Pentium 4 (Unknown)", | |
739 | [1] = "Pentium 4 (Willamette)", | |
740 | [2] = "Pentium 4 (Northwood)", | |
741 | [4] = "Pentium 4 (Foster)", | |
742 | [5] = "Pentium 4 (Foster)", | |
743 | } | |
744 | }, | |
745 | }, | |
09dc68d9 | 746 | .legacy_cache_size = intel_size_cache, |
185f3b9d | 747 | #endif |
e0ba94f1 | 748 | .c_detect_tlb = intel_detect_tlb, |
03ae5768 | 749 | .c_early_init = early_init_intel, |
1da177e4 | 750 | .c_init = init_intel, |
10a434fc | 751 | .c_x86_vendor = X86_VENDOR_INTEL, |
1da177e4 LT |
752 | }; |
753 | ||
10a434fc | 754 | cpu_dev_register(intel_cpu_dev); |
1da177e4 | 755 |