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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/x86_64/entry.S | |
3 | * | |
4 | * Copyright (C) 1991, 1992 Linus Torvalds | |
5 | * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs | |
6 | * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> | |
1da177e4 LT |
7 | */ |
8 | ||
9 | /* | |
10 | * entry.S contains the system-call and fault low-level handling routines. | |
11 | * | |
8b4777a4 AL |
12 | * Some of this is documented in Documentation/x86/entry_64.txt |
13 | * | |
1da177e4 LT |
14 | * NOTE: This code handles signal-recognition, which happens every time |
15 | * after an interrupt and after each system call. | |
0bd7b798 | 16 | * |
0bd7b798 | 17 | * A note on terminology: |
7fcb3bc3 | 18 | * - iret frame: Architecture defined interrupt frame from SS to RIP |
0bd7b798 | 19 | * at the top of the kernel process stack. |
2e91a17b AK |
20 | * |
21 | * Some macro usage: | |
22 | * - CFI macros are used to generate dwarf2 unwind information for better | |
23 | * backtraces. They don't change any code. | |
2e91a17b | 24 | * - ENTRY/END Define functions in the symbol table. |
2e91a17b | 25 | * - TRACE_IRQ_* - Trace hard interrupt state for lock debugging. |
cb5dd2c5 | 26 | * - idtentry - Define exception entry points. |
1da177e4 LT |
27 | */ |
28 | ||
1da177e4 LT |
29 | #include <linux/linkage.h> |
30 | #include <asm/segment.h> | |
1da177e4 LT |
31 | #include <asm/cache.h> |
32 | #include <asm/errno.h> | |
33 | #include <asm/dwarf2.h> | |
34 | #include <asm/calling.h> | |
e2d5df93 | 35 | #include <asm/asm-offsets.h> |
1da177e4 LT |
36 | #include <asm/msr.h> |
37 | #include <asm/unistd.h> | |
38 | #include <asm/thread_info.h> | |
39 | #include <asm/hw_irq.h> | |
0341c14d | 40 | #include <asm/page_types.h> |
2601e64d | 41 | #include <asm/irqflags.h> |
72fe4858 | 42 | #include <asm/paravirt.h> |
9939ddaf | 43 | #include <asm/percpu.h> |
d7abc0fa | 44 | #include <asm/asm.h> |
91d1aa43 | 45 | #include <asm/context_tracking.h> |
63bcff2a | 46 | #include <asm/smap.h> |
3891a04a | 47 | #include <asm/pgtable_types.h> |
d7e7528b | 48 | #include <linux/err.h> |
1da177e4 | 49 | |
86a1c34a RM |
50 | /* Avoid __ASSEMBLER__'ifying <linux/audit.h> just for this. */ |
51 | #include <linux/elf-em.h> | |
52 | #define AUDIT_ARCH_X86_64 (EM_X86_64|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE) | |
53 | #define __AUDIT_ARCH_64BIT 0x80000000 | |
54 | #define __AUDIT_ARCH_LE 0x40000000 | |
55 | ||
1da177e4 | 56 | .code64 |
ea714547 JO |
57 | .section .entry.text, "ax" |
58 | ||
16444a8a | 59 | |
dc37db4d | 60 | #ifndef CONFIG_PREEMPT |
1da177e4 | 61 | #define retint_kernel retint_restore_args |
0bd7b798 | 62 | #endif |
2601e64d | 63 | |
72fe4858 | 64 | #ifdef CONFIG_PARAVIRT |
2be29982 | 65 | ENTRY(native_usergs_sysret64) |
72fe4858 GOC |
66 | swapgs |
67 | sysretq | |
b3baaa13 | 68 | ENDPROC(native_usergs_sysret64) |
72fe4858 GOC |
69 | #endif /* CONFIG_PARAVIRT */ |
70 | ||
2601e64d | 71 | |
f2db9382 | 72 | .macro TRACE_IRQS_IRETQ |
2601e64d | 73 | #ifdef CONFIG_TRACE_IRQFLAGS |
f2db9382 | 74 | bt $9,EFLAGS(%rsp) /* interrupts off? */ |
2601e64d IM |
75 | jnc 1f |
76 | TRACE_IRQS_ON | |
77 | 1: | |
78 | #endif | |
79 | .endm | |
80 | ||
5963e317 SR |
81 | /* |
82 | * When dynamic function tracer is enabled it will add a breakpoint | |
83 | * to all locations that it is about to modify, sync CPUs, update | |
84 | * all the code, sync CPUs, then remove the breakpoints. In this time | |
85 | * if lockdep is enabled, it might jump back into the debug handler | |
86 | * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF). | |
87 | * | |
88 | * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to | |
89 | * make sure the stack pointer does not get reset back to the top | |
90 | * of the debug stack, and instead just reuses the current stack. | |
91 | */ | |
92 | #if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS) | |
93 | ||
94 | .macro TRACE_IRQS_OFF_DEBUG | |
95 | call debug_stack_set_zero | |
96 | TRACE_IRQS_OFF | |
97 | call debug_stack_reset | |
98 | .endm | |
99 | ||
100 | .macro TRACE_IRQS_ON_DEBUG | |
101 | call debug_stack_set_zero | |
102 | TRACE_IRQS_ON | |
103 | call debug_stack_reset | |
104 | .endm | |
105 | ||
f2db9382 DV |
106 | .macro TRACE_IRQS_IRETQ_DEBUG |
107 | bt $9,EFLAGS(%rsp) /* interrupts off? */ | |
5963e317 SR |
108 | jnc 1f |
109 | TRACE_IRQS_ON_DEBUG | |
110 | 1: | |
111 | .endm | |
112 | ||
113 | #else | |
114 | # define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF | |
115 | # define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON | |
116 | # define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ | |
117 | #endif | |
118 | ||
dcd072e2 | 119 | /* |
e90e147c | 120 | * empty frame |
dcd072e2 AH |
121 | */ |
122 | .macro EMPTY_FRAME start=1 offset=0 | |
7effaa88 | 123 | .if \start |
dcd072e2 | 124 | CFI_STARTPROC simple |
adf14236 | 125 | CFI_SIGNAL_FRAME |
dcd072e2 | 126 | CFI_DEF_CFA rsp,8+\offset |
7effaa88 | 127 | .else |
dcd072e2 | 128 | CFI_DEF_CFA_OFFSET 8+\offset |
7effaa88 | 129 | .endif |
1da177e4 | 130 | .endm |
d99015b1 AH |
131 | |
132 | /* | |
dcd072e2 | 133 | * initial frame state for interrupts (and exceptions without error code) |
d99015b1 | 134 | */ |
dcd072e2 | 135 | .macro INTR_FRAME start=1 offset=0 |
911d2bb5 DV |
136 | EMPTY_FRAME \start, 5*8+\offset |
137 | /*CFI_REL_OFFSET ss, 4*8+\offset*/ | |
138 | CFI_REL_OFFSET rsp, 3*8+\offset | |
139 | /*CFI_REL_OFFSET rflags, 2*8+\offset*/ | |
140 | /*CFI_REL_OFFSET cs, 1*8+\offset*/ | |
141 | CFI_REL_OFFSET rip, 0*8+\offset | |
d99015b1 AH |
142 | .endm |
143 | ||
d99015b1 AH |
144 | /* |
145 | * initial frame state for exceptions with error code (and interrupts | |
146 | * with vector already pushed) | |
147 | */ | |
dcd072e2 | 148 | .macro XCPT_FRAME start=1 offset=0 |
911d2bb5 | 149 | INTR_FRAME \start, 1*8+\offset |
dcd072e2 AH |
150 | .endm |
151 | ||
152 | /* | |
76f5df43 | 153 | * frame that enables passing a complete pt_regs to a C function. |
dcd072e2 | 154 | */ |
76f5df43 | 155 | .macro DEFAULT_FRAME start=1 offset=0 |
f2db9382 DV |
156 | XCPT_FRAME \start, ORIG_RAX+\offset |
157 | CFI_REL_OFFSET rdi, RDI+\offset | |
158 | CFI_REL_OFFSET rsi, RSI+\offset | |
159 | CFI_REL_OFFSET rdx, RDX+\offset | |
160 | CFI_REL_OFFSET rcx, RCX+\offset | |
161 | CFI_REL_OFFSET rax, RAX+\offset | |
162 | CFI_REL_OFFSET r8, R8+\offset | |
163 | CFI_REL_OFFSET r9, R9+\offset | |
164 | CFI_REL_OFFSET r10, R10+\offset | |
165 | CFI_REL_OFFSET r11, R11+\offset | |
dcd072e2 AH |
166 | CFI_REL_OFFSET rbx, RBX+\offset |
167 | CFI_REL_OFFSET rbp, RBP+\offset | |
168 | CFI_REL_OFFSET r12, R12+\offset | |
169 | CFI_REL_OFFSET r13, R13+\offset | |
170 | CFI_REL_OFFSET r14, R14+\offset | |
171 | CFI_REL_OFFSET r15, R15+\offset | |
172 | .endm | |
d99015b1 | 173 | |
1da177e4 | 174 | /* |
b87cf63e | 175 | * 64bit SYSCALL instruction entry. Up to 6 arguments in registers. |
1da177e4 | 176 | * |
b87cf63e DV |
177 | * 64bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11, |
178 | * then loads new ss, cs, and rip from previously programmed MSRs. | |
179 | * rflags gets masked by a value from another MSR (so CLD and CLAC | |
180 | * are not needed). SYSCALL does not save anything on the stack | |
181 | * and does not change rsp. | |
182 | * | |
183 | * Registers on entry: | |
1da177e4 | 184 | * rax system call number |
b87cf63e DV |
185 | * rcx return address |
186 | * r11 saved rflags (note: r11 is callee-clobbered register in C ABI) | |
1da177e4 | 187 | * rdi arg0 |
1da177e4 | 188 | * rsi arg1 |
0bd7b798 | 189 | * rdx arg2 |
b87cf63e | 190 | * r10 arg3 (needs to be moved to rcx to conform to C ABI) |
1da177e4 LT |
191 | * r8 arg4 |
192 | * r9 arg5 | |
b87cf63e | 193 | * (note: r12-r15,rbp,rbx are callee-preserved in C ABI) |
0bd7b798 | 194 | * |
1da177e4 LT |
195 | * Only called from user space. |
196 | * | |
7fcb3bc3 | 197 | * When user can change pt_regs->foo always force IRET. That is because |
7bf36bbc AK |
198 | * it deals with uncanonical addresses better. SYSRET has trouble |
199 | * with them due to bugs in both AMD and Intel CPUs. | |
0bd7b798 | 200 | */ |
1da177e4 LT |
201 | |
202 | ENTRY(system_call) | |
7effaa88 | 203 | CFI_STARTPROC simple |
adf14236 | 204 | CFI_SIGNAL_FRAME |
ef593260 | 205 | CFI_DEF_CFA rsp,0 |
7effaa88 JB |
206 | CFI_REGISTER rip,rcx |
207 | /*CFI_REGISTER rflags,r11*/ | |
9ed8e7d8 DV |
208 | |
209 | /* | |
210 | * Interrupts are off on entry. | |
211 | * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, | |
212 | * it is too small to ever cause noticeable irq latency. | |
213 | */ | |
72fe4858 GOC |
214 | SWAPGS_UNSAFE_STACK |
215 | /* | |
216 | * A hypervisor implementation might want to use a label | |
217 | * after the swapgs, so that it can do the swapgs | |
218 | * for the guest and jump here on syscall. | |
219 | */ | |
f6b2bc84 | 220 | GLOBAL(system_call_after_swapgs) |
72fe4858 | 221 | |
c38e5038 | 222 | movq %rsp,PER_CPU_VAR(rsp_scratch) |
9af45651 | 223 | movq PER_CPU_VAR(kernel_stack),%rsp |
9ed8e7d8 DV |
224 | |
225 | /* Construct struct pt_regs on stack */ | |
226 | pushq_cfi $__USER_DS /* pt_regs->ss */ | |
227 | pushq_cfi PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */ | |
33db1fd4 | 228 | /* |
9ed8e7d8 DV |
229 | * Re-enable interrupts. |
230 | * We use 'rsp_scratch' as a scratch space, hence irq-off block above | |
231 | * must execute atomically in the face of possible interrupt-driven | |
232 | * task preemption. We must enable interrupts only after we're done | |
233 | * with using rsp_scratch: | |
33db1fd4 DV |
234 | */ |
235 | ENABLE_INTERRUPTS(CLBR_NONE) | |
9ed8e7d8 DV |
236 | pushq_cfi %r11 /* pt_regs->flags */ |
237 | pushq_cfi $__USER_CS /* pt_regs->cs */ | |
238 | pushq_cfi %rcx /* pt_regs->ip */ | |
239 | CFI_REL_OFFSET rip,0 | |
240 | pushq_cfi_reg rax /* pt_regs->orig_ax */ | |
241 | pushq_cfi_reg rdi /* pt_regs->di */ | |
242 | pushq_cfi_reg rsi /* pt_regs->si */ | |
243 | pushq_cfi_reg rdx /* pt_regs->dx */ | |
244 | pushq_cfi_reg rcx /* pt_regs->cx */ | |
245 | pushq_cfi $-ENOSYS /* pt_regs->ax */ | |
246 | pushq_cfi_reg r8 /* pt_regs->r8 */ | |
247 | pushq_cfi_reg r9 /* pt_regs->r9 */ | |
248 | pushq_cfi_reg r10 /* pt_regs->r10 */ | |
a71ffdd7 DV |
249 | pushq_cfi_reg r11 /* pt_regs->r11 */ |
250 | sub $(6*8),%rsp /* pt_regs->bp,bx,r12-15 not saved */ | |
27be87c5 | 251 | CFI_ADJUST_CFA_OFFSET 6*8 |
9ed8e7d8 | 252 | |
dca5b52a | 253 | testl $_TIF_WORK_SYSCALL_ENTRY, ASM_THREAD_INFO(TI_flags, %rsp, SIZEOF_PTREGS) |
1da177e4 | 254 | jnz tracesys |
86a1c34a | 255 | system_call_fastpath: |
fca460f9 | 256 | #if __SYSCALL_MASK == ~0 |
1da177e4 | 257 | cmpq $__NR_syscall_max,%rax |
fca460f9 PA |
258 | #else |
259 | andl $__SYSCALL_MASK,%eax | |
260 | cmpl $__NR_syscall_max,%eax | |
261 | #endif | |
146b2b09 | 262 | ja 1f /* return -ENOSYS (already in pt_regs->ax) */ |
1da177e4 | 263 | movq %r10,%rcx |
146b2b09 | 264 | call *sys_call_table(,%rax,8) |
f2db9382 | 265 | movq %rax,RAX(%rsp) |
146b2b09 | 266 | 1: |
1da177e4 | 267 | /* |
146b2b09 DV |
268 | * Syscall return path ending with SYSRET (fast path). |
269 | * Has incompletely filled pt_regs. | |
0bd7b798 | 270 | */ |
10cd706d | 271 | LOCKDEP_SYS_EXIT |
72fe4858 | 272 | DISABLE_INTERRUPTS(CLBR_NONE) |
2601e64d | 273 | TRACE_IRQS_OFF |
b3494a4a AL |
274 | |
275 | /* | |
276 | * We must check ti flags with interrupts (or at least preemption) | |
277 | * off because we must *never* return to userspace without | |
278 | * processing exit work that is enqueued if we're preempted here. | |
279 | * In particular, returning to userspace with any of the one-shot | |
280 | * flags (TIF_NOTIFY_RESUME, TIF_USER_RETURN_NOTIFY, etc) set is | |
281 | * very bad. | |
282 | */ | |
06ab9c1b IM |
283 | testl $_TIF_ALLWORK_MASK, ASM_THREAD_INFO(TI_flags, %rsp, SIZEOF_PTREGS) |
284 | jnz int_ret_from_sys_call_irqs_off /* Go to the slow path */ | |
b3494a4a | 285 | |
bcddc015 | 286 | CFI_REMEMBER_STATE |
2601e64d IM |
287 | /* |
288 | * sysretq will re-enable interrupts: | |
289 | */ | |
290 | TRACE_IRQS_ON | |
29722cd4 DV |
291 | RESTORE_C_REGS_EXCEPT_RCX_R11 |
292 | movq RIP(%rsp),%rcx | |
7effaa88 | 293 | CFI_REGISTER rip,rcx |
29722cd4 | 294 | movq EFLAGS(%rsp),%r11 |
7effaa88 | 295 | /*CFI_REGISTER rflags,r11*/ |
263042e4 | 296 | movq RSP(%rsp),%rsp |
b87cf63e DV |
297 | /* |
298 | * 64bit SYSRET restores rip from rcx, | |
299 | * rflags from r11 (but RF and VM bits are forced to 0), | |
300 | * cs and ss are loaded from MSRs. | |
301 | */ | |
2be29982 | 302 | USERGS_SYSRET64 |
1da177e4 | 303 | |
bcddc015 | 304 | CFI_RESTORE_STATE |
1da177e4 | 305 | |
7fcb3bc3 | 306 | /* Do syscall entry tracing */ |
0bd7b798 | 307 | tracesys: |
76f5df43 | 308 | movq %rsp, %rdi |
47eb582e | 309 | movl $AUDIT_ARCH_X86_64, %esi |
1dcf74f6 AL |
310 | call syscall_trace_enter_phase1 |
311 | test %rax, %rax | |
312 | jnz tracesys_phase2 /* if needed, run the slow path */ | |
76f5df43 | 313 | RESTORE_C_REGS_EXCEPT_RAX /* else restore clobbered regs */ |
f2db9382 | 314 | movq ORIG_RAX(%rsp), %rax |
1dcf74f6 AL |
315 | jmp system_call_fastpath /* and return to the fast path */ |
316 | ||
317 | tracesys_phase2: | |
76f5df43 | 318 | SAVE_EXTRA_REGS |
1dcf74f6 | 319 | movq %rsp, %rdi |
47eb582e | 320 | movl $AUDIT_ARCH_X86_64, %esi |
1dcf74f6 AL |
321 | movq %rax,%rdx |
322 | call syscall_trace_enter_phase2 | |
323 | ||
d4d67150 | 324 | /* |
e90e147c | 325 | * Reload registers from stack in case ptrace changed them. |
1dcf74f6 | 326 | * We don't reload %rax because syscall_trace_entry_phase2() returned |
d4d67150 RM |
327 | * the value it wants us to use in the table lookup. |
328 | */ | |
76f5df43 DV |
329 | RESTORE_C_REGS_EXCEPT_RAX |
330 | RESTORE_EXTRA_REGS | |
fca460f9 | 331 | #if __SYSCALL_MASK == ~0 |
1da177e4 | 332 | cmpq $__NR_syscall_max,%rax |
fca460f9 PA |
333 | #else |
334 | andl $__SYSCALL_MASK,%eax | |
335 | cmpl $__NR_syscall_max,%eax | |
336 | #endif | |
54eea995 | 337 | ja int_ret_from_sys_call /* RAX(%rsp) is already set */ |
1da177e4 LT |
338 | movq %r10,%rcx /* fixup for C */ |
339 | call *sys_call_table(,%rax,8) | |
f2db9382 | 340 | movq %rax,RAX(%rsp) |
7fcb3bc3 | 341 | /* Use IRET because user could have changed pt_regs->foo */ |
0bd7b798 AH |
342 | |
343 | /* | |
1da177e4 | 344 | * Syscall return path ending with IRET. |
7fcb3bc3 | 345 | * Has correct iret frame. |
bcddc015 | 346 | */ |
bc8b2b92 | 347 | GLOBAL(int_ret_from_sys_call) |
72fe4858 | 348 | DISABLE_INTERRUPTS(CLBR_NONE) |
2601e64d | 349 | TRACE_IRQS_OFF |
b3494a4a | 350 | int_ret_from_sys_call_irqs_off: |
1da177e4 LT |
351 | movl $_TIF_ALLWORK_MASK,%edi |
352 | /* edi: mask to check */ | |
bc8b2b92 | 353 | GLOBAL(int_with_check) |
10cd706d | 354 | LOCKDEP_SYS_EXIT_IRQ |
1da177e4 | 355 | GET_THREAD_INFO(%rcx) |
26ccb8a7 | 356 | movl TI_flags(%rcx),%edx |
1da177e4 LT |
357 | andl %edi,%edx |
358 | jnz int_careful | |
26ccb8a7 | 359 | andl $~TS_COMPAT,TI_status(%rcx) |
1da177e4 LT |
360 | jmp retint_swapgs |
361 | ||
362 | /* Either reschedule or signal or syscall exit tracking needed. */ | |
363 | /* First do a reschedule test. */ | |
364 | /* edx: work, edi: workmask */ | |
365 | int_careful: | |
366 | bt $TIF_NEED_RESCHED,%edx | |
367 | jnc int_very_careful | |
2601e64d | 368 | TRACE_IRQS_ON |
72fe4858 | 369 | ENABLE_INTERRUPTS(CLBR_NONE) |
df5d1874 | 370 | pushq_cfi %rdi |
0430499c | 371 | SCHEDULE_USER |
df5d1874 | 372 | popq_cfi %rdi |
72fe4858 | 373 | DISABLE_INTERRUPTS(CLBR_NONE) |
2601e64d | 374 | TRACE_IRQS_OFF |
1da177e4 LT |
375 | jmp int_with_check |
376 | ||
7fcb3bc3 | 377 | /* handle signals and tracing -- both require a full pt_regs */ |
1da177e4 | 378 | int_very_careful: |
2601e64d | 379 | TRACE_IRQS_ON |
72fe4858 | 380 | ENABLE_INTERRUPTS(CLBR_NONE) |
76f5df43 | 381 | SAVE_EXTRA_REGS |
0bd7b798 | 382 | /* Check for syscall exit trace */ |
d4d67150 | 383 | testl $_TIF_WORK_SYSCALL_EXIT,%edx |
1da177e4 | 384 | jz int_signal |
df5d1874 | 385 | pushq_cfi %rdi |
0bd7b798 | 386 | leaq 8(%rsp),%rdi # &ptregs -> arg1 |
1da177e4 | 387 | call syscall_trace_leave |
df5d1874 | 388 | popq_cfi %rdi |
d4d67150 | 389 | andl $~(_TIF_WORK_SYSCALL_EXIT|_TIF_SYSCALL_EMU),%edi |
1da177e4 | 390 | jmp int_restore_rest |
0bd7b798 | 391 | |
1da177e4 | 392 | int_signal: |
8f4d37ec | 393 | testl $_TIF_DO_NOTIFY_MASK,%edx |
1da177e4 LT |
394 | jz 1f |
395 | movq %rsp,%rdi # &ptregs -> arg1 | |
396 | xorl %esi,%esi # oldset -> arg2 | |
397 | call do_notify_resume | |
eca91e78 | 398 | 1: movl $_TIF_WORK_MASK,%edi |
1da177e4 | 399 | int_restore_rest: |
76f5df43 | 400 | RESTORE_EXTRA_REGS |
72fe4858 | 401 | DISABLE_INTERRUPTS(CLBR_NONE) |
2601e64d | 402 | TRACE_IRQS_OFF |
1da177e4 LT |
403 | jmp int_with_check |
404 | CFI_ENDPROC | |
bcddc015 | 405 | END(system_call) |
0bd7b798 | 406 | |
1d4b4b29 AV |
407 | .macro FORK_LIKE func |
408 | ENTRY(stub_\func) | |
409 | CFI_STARTPROC | |
76f5df43 DV |
410 | DEFAULT_FRAME 0, 8 /* offset 8: return address */ |
411 | SAVE_EXTRA_REGS 8 | |
1d4b4b29 | 412 | call sys_\func |
76f5df43 | 413 | ret |
1d4b4b29 AV |
414 | CFI_ENDPROC |
415 | END(stub_\func) | |
416 | .endm | |
417 | ||
418 | FORK_LIKE clone | |
419 | FORK_LIKE fork | |
420 | FORK_LIKE vfork | |
1da177e4 | 421 | |
1da177e4 LT |
422 | ENTRY(stub_execve) |
423 | CFI_STARTPROC | |
e6b04b6b | 424 | addq $8, %rsp |
76f5df43 DV |
425 | DEFAULT_FRAME 0 |
426 | SAVE_EXTRA_REGS | |
1da177e4 | 427 | call sys_execve |
1da177e4 | 428 | movq %rax,RAX(%rsp) |
76f5df43 | 429 | RESTORE_EXTRA_REGS |
1da177e4 LT |
430 | jmp int_ret_from_sys_call |
431 | CFI_ENDPROC | |
4b787e0b | 432 | END(stub_execve) |
0bd7b798 | 433 | |
27d6ec7a DD |
434 | ENTRY(stub_execveat) |
435 | CFI_STARTPROC | |
436 | addq $8, %rsp | |
76f5df43 DV |
437 | DEFAULT_FRAME 0 |
438 | SAVE_EXTRA_REGS | |
27d6ec7a | 439 | call sys_execveat |
27d6ec7a | 440 | movq %rax,RAX(%rsp) |
76f5df43 | 441 | RESTORE_EXTRA_REGS |
27d6ec7a DD |
442 | jmp int_ret_from_sys_call |
443 | CFI_ENDPROC | |
444 | END(stub_execveat) | |
445 | ||
1da177e4 LT |
446 | /* |
447 | * sigreturn is special because it needs to restore all registers on return. | |
448 | * This cannot be done with SYSRET, so use the IRET return path instead. | |
0bd7b798 | 449 | */ |
1da177e4 LT |
450 | ENTRY(stub_rt_sigreturn) |
451 | CFI_STARTPROC | |
7effaa88 | 452 | addq $8, %rsp |
76f5df43 DV |
453 | DEFAULT_FRAME 0 |
454 | SAVE_EXTRA_REGS | |
1da177e4 LT |
455 | call sys_rt_sigreturn |
456 | movq %rax,RAX(%rsp) # fixme, this could be done at the higher layer | |
76f5df43 | 457 | RESTORE_EXTRA_REGS |
1da177e4 LT |
458 | jmp int_ret_from_sys_call |
459 | CFI_ENDPROC | |
4b787e0b | 460 | END(stub_rt_sigreturn) |
1da177e4 | 461 | |
c5a37394 | 462 | #ifdef CONFIG_X86_X32_ABI |
c5a37394 PA |
463 | ENTRY(stub_x32_rt_sigreturn) |
464 | CFI_STARTPROC | |
465 | addq $8, %rsp | |
76f5df43 DV |
466 | DEFAULT_FRAME 0 |
467 | SAVE_EXTRA_REGS | |
c5a37394 PA |
468 | call sys32_x32_rt_sigreturn |
469 | movq %rax,RAX(%rsp) # fixme, this could be done at the higher layer | |
76f5df43 | 470 | RESTORE_EXTRA_REGS |
c5a37394 PA |
471 | jmp int_ret_from_sys_call |
472 | CFI_ENDPROC | |
473 | END(stub_x32_rt_sigreturn) | |
474 | ||
d1a797f3 PA |
475 | ENTRY(stub_x32_execve) |
476 | CFI_STARTPROC | |
477 | addq $8, %rsp | |
76f5df43 DV |
478 | DEFAULT_FRAME 0 |
479 | SAVE_EXTRA_REGS | |
6783eaa2 | 480 | call compat_sys_execve |
d1a797f3 | 481 | movq %rax,RAX(%rsp) |
76f5df43 | 482 | RESTORE_EXTRA_REGS |
d1a797f3 PA |
483 | jmp int_ret_from_sys_call |
484 | CFI_ENDPROC | |
485 | END(stub_x32_execve) | |
486 | ||
27d6ec7a DD |
487 | ENTRY(stub_x32_execveat) |
488 | CFI_STARTPROC | |
489 | addq $8, %rsp | |
76f5df43 DV |
490 | DEFAULT_FRAME 0 |
491 | SAVE_EXTRA_REGS | |
27d6ec7a | 492 | call compat_sys_execveat |
27d6ec7a | 493 | movq %rax,RAX(%rsp) |
76f5df43 | 494 | RESTORE_EXTRA_REGS |
27d6ec7a DD |
495 | jmp int_ret_from_sys_call |
496 | CFI_ENDPROC | |
497 | END(stub_x32_execveat) | |
498 | ||
c5a37394 PA |
499 | #endif |
500 | ||
1eeb207f DV |
501 | /* |
502 | * A newly forked process directly context switches into this address. | |
503 | * | |
504 | * rdi: prev task we switched from | |
505 | */ | |
506 | ENTRY(ret_from_fork) | |
507 | DEFAULT_FRAME | |
508 | ||
509 | LOCK ; btr $TIF_FORK,TI_flags(%r8) | |
510 | ||
511 | pushq_cfi $0x0002 | |
512 | popfq_cfi # reset kernel eflags | |
513 | ||
514 | call schedule_tail # rdi: 'prev' task parameter | |
515 | ||
516 | GET_THREAD_INFO(%rcx) | |
517 | ||
518 | RESTORE_EXTRA_REGS | |
519 | ||
520 | testl $3,CS(%rsp) # from kernel_thread? | |
521 | jz 1f | |
522 | ||
1e3fbb8a AL |
523 | /* |
524 | * By the time we get here, we have no idea whether our pt_regs, | |
525 | * ti flags, and ti status came from the 64-bit SYSCALL fast path, | |
526 | * the slow path, or one of the ia32entry paths. | |
527 | * Use int_ret_from_sys_call to return, since it can safely handle | |
528 | * all of the above. | |
529 | */ | |
530 | jmp int_ret_from_sys_call | |
1eeb207f DV |
531 | |
532 | 1: | |
533 | movq %rbp, %rdi | |
534 | call *%rbx | |
535 | movl $0, RAX(%rsp) | |
536 | RESTORE_EXTRA_REGS | |
537 | jmp int_ret_from_sys_call | |
538 | CFI_ENDPROC | |
539 | END(ret_from_fork) | |
540 | ||
939b7871 PA |
541 | /* |
542 | * Build the entry stubs and pointer table with some assembler magic. | |
543 | * We pack 7 stubs into a single 32-byte chunk, which will fit in a | |
544 | * single cache line on all modern x86 implementations. | |
545 | */ | |
546 | .section .init.rodata,"a" | |
547 | ENTRY(interrupt) | |
ea714547 | 548 | .section .entry.text |
939b7871 PA |
549 | .p2align 5 |
550 | .p2align CONFIG_X86_L1_CACHE_SHIFT | |
551 | ENTRY(irq_entries_start) | |
552 | INTR_FRAME | |
553 | vector=FIRST_EXTERNAL_VECTOR | |
2414e021 | 554 | .rept (FIRST_SYSTEM_VECTOR-FIRST_EXTERNAL_VECTOR+6)/7 |
939b7871 PA |
555 | .balign 32 |
556 | .rept 7 | |
2414e021 | 557 | .if vector < FIRST_SYSTEM_VECTOR |
8665596e | 558 | .if vector <> FIRST_EXTERNAL_VECTOR |
939b7871 PA |
559 | CFI_ADJUST_CFA_OFFSET -8 |
560 | .endif | |
df5d1874 | 561 | 1: pushq_cfi $(~vector+0x80) /* Note: always in signed byte range */ |
8665596e | 562 | .if ((vector-FIRST_EXTERNAL_VECTOR)%7) <> 6 |
939b7871 PA |
563 | jmp 2f |
564 | .endif | |
565 | .previous | |
566 | .quad 1b | |
ea714547 | 567 | .section .entry.text |
939b7871 PA |
568 | vector=vector+1 |
569 | .endif | |
570 | .endr | |
571 | 2: jmp common_interrupt | |
572 | .endr | |
573 | CFI_ENDPROC | |
574 | END(irq_entries_start) | |
575 | ||
576 | .previous | |
577 | END(interrupt) | |
578 | .previous | |
579 | ||
d99015b1 | 580 | /* |
1da177e4 LT |
581 | * Interrupt entry/exit. |
582 | * | |
583 | * Interrupt entry points save only callee clobbered registers in fast path. | |
d99015b1 AH |
584 | * |
585 | * Entry runs with interrupts off. | |
586 | */ | |
1da177e4 | 587 | |
722024db | 588 | /* 0(%rsp): ~(interrupt number) */ |
1da177e4 | 589 | .macro interrupt func |
f6f64681 | 590 | cld |
e90e147c DV |
591 | /* |
592 | * Since nothing in interrupt handling code touches r12...r15 members | |
593 | * of "struct pt_regs", and since interrupts can nest, we can save | |
594 | * four stack slots and simultaneously provide | |
595 | * an unwind-friendly stack layout by saving "truncated" pt_regs | |
596 | * exactly up to rbp slot, without these members. | |
597 | */ | |
76f5df43 DV |
598 | ALLOC_PT_GPREGS_ON_STACK -RBP |
599 | SAVE_C_REGS -RBP | |
600 | /* this goes to 0(%rsp) for unwinder, not for saving the value: */ | |
601 | SAVE_EXTRA_REGS_RBP -RBP | |
602 | ||
603 | leaq -RBP(%rsp),%rdi /* arg1 for \func (pointer to pt_regs) */ | |
f6f64681 | 604 | |
76f5df43 | 605 | testl $3, CS-RBP(%rsp) |
f6f64681 DV |
606 | je 1f |
607 | SWAPGS | |
76f5df43 | 608 | 1: |
f6f64681 | 609 | /* |
e90e147c | 610 | * Save previous stack pointer, optionally switch to interrupt stack. |
f6f64681 DV |
611 | * irq_count is used to check if a CPU is already on an interrupt stack |
612 | * or not. While this is essentially redundant with preempt_count it is | |
613 | * a little cheaper to use a separate counter in the PDA (short of | |
614 | * moving irq_enter into assembly, which would be too much work) | |
615 | */ | |
76f5df43 DV |
616 | movq %rsp, %rsi |
617 | incl PER_CPU_VAR(irq_count) | |
f6f64681 DV |
618 | cmovzq PER_CPU_VAR(irq_stack_ptr),%rsp |
619 | CFI_DEF_CFA_REGISTER rsi | |
f6f64681 | 620 | pushq %rsi |
911d2bb5 DV |
621 | /* |
622 | * For debugger: | |
623 | * "CFA (Current Frame Address) is the value on stack + offset" | |
624 | */ | |
f6f64681 | 625 | CFI_ESCAPE 0x0f /* DW_CFA_def_cfa_expression */, 6, \ |
911d2bb5 | 626 | 0x77 /* DW_OP_breg7 (rsp) */, 0, \ |
f6f64681 | 627 | 0x06 /* DW_OP_deref */, \ |
911d2bb5 | 628 | 0x08 /* DW_OP_const1u */, SIZEOF_PTREGS-RBP, \ |
f6f64681 DV |
629 | 0x22 /* DW_OP_plus */ |
630 | /* We entered an interrupt context - irqs are off: */ | |
631 | TRACE_IRQS_OFF | |
632 | ||
1da177e4 LT |
633 | call \func |
634 | .endm | |
635 | ||
722024db AH |
636 | /* |
637 | * The interrupt stubs push (~vector+0x80) onto the stack and | |
638 | * then jump to common_interrupt. | |
639 | */ | |
939b7871 PA |
640 | .p2align CONFIG_X86_L1_CACHE_SHIFT |
641 | common_interrupt: | |
7effaa88 | 642 | XCPT_FRAME |
ee4eb87b | 643 | ASM_CLAC |
722024db | 644 | addq $-0x80,(%rsp) /* Adjust vector to [-256,-1] range */ |
1da177e4 | 645 | interrupt do_IRQ |
34061f13 | 646 | /* 0(%rsp): old RSP */ |
7effaa88 | 647 | ret_from_intr: |
72fe4858 | 648 | DISABLE_INTERRUPTS(CLBR_NONE) |
2601e64d | 649 | TRACE_IRQS_OFF |
56895530 | 650 | decl PER_CPU_VAR(irq_count) |
625dbc3b | 651 | |
a2bbe750 FW |
652 | /* Restore saved previous stack */ |
653 | popq %rsi | |
911d2bb5 | 654 | CFI_DEF_CFA rsi,SIZEOF_PTREGS-RBP /* reg/off reset after def_cfa_expr */ |
e90e147c | 655 | /* return code expects complete pt_regs - adjust rsp accordingly: */ |
f2db9382 | 656 | leaq -RBP(%rsi),%rsp |
7effaa88 | 657 | CFI_DEF_CFA_REGISTER rsp |
f2db9382 | 658 | CFI_ADJUST_CFA_OFFSET RBP |
625dbc3b | 659 | |
7effaa88 | 660 | exit_intr: |
1da177e4 | 661 | GET_THREAD_INFO(%rcx) |
f2db9382 | 662 | testl $3,CS(%rsp) |
1da177e4 | 663 | je retint_kernel |
0bd7b798 | 664 | |
1da177e4 LT |
665 | /* Interrupt came from user space */ |
666 | /* | |
e90e147c | 667 | * Has a correct top of stack. |
1da177e4 | 668 | * %rcx: thread info. Interrupts off. |
0bd7b798 | 669 | */ |
1da177e4 LT |
670 | retint_with_reschedule: |
671 | movl $_TIF_WORK_MASK,%edi | |
7effaa88 | 672 | retint_check: |
10cd706d | 673 | LOCKDEP_SYS_EXIT_IRQ |
26ccb8a7 | 674 | movl TI_flags(%rcx),%edx |
1da177e4 | 675 | andl %edi,%edx |
7effaa88 | 676 | CFI_REMEMBER_STATE |
1da177e4 | 677 | jnz retint_careful |
10cd706d PZ |
678 | |
679 | retint_swapgs: /* return to user-space */ | |
2601e64d IM |
680 | /* |
681 | * The iretq could re-enable interrupts: | |
682 | */ | |
72fe4858 | 683 | DISABLE_INTERRUPTS(CLBR_ANY) |
2601e64d | 684 | TRACE_IRQS_IRETQ |
2a23c6b8 AL |
685 | |
686 | /* | |
687 | * Try to use SYSRET instead of IRET if we're returning to | |
688 | * a completely clean 64-bit userspace context. | |
689 | */ | |
f2db9382 DV |
690 | movq RCX(%rsp),%rcx |
691 | cmpq %rcx,RIP(%rsp) /* RCX == RIP */ | |
2a23c6b8 AL |
692 | jne opportunistic_sysret_failed |
693 | ||
694 | /* | |
695 | * On Intel CPUs, sysret with non-canonical RCX/RIP will #GP | |
696 | * in kernel space. This essentially lets the user take over | |
697 | * the kernel, since userspace controls RSP. It's not worth | |
698 | * testing for canonicalness exactly -- this check detects any | |
699 | * of the 17 high bits set, which is true for non-canonical | |
700 | * or kernel addresses. (This will pessimize vsyscall=native. | |
701 | * Big deal.) | |
702 | * | |
703 | * If virtual addresses ever become wider, this will need | |
704 | * to be updated to remain correct on both old and new CPUs. | |
705 | */ | |
706 | .ifne __VIRTUAL_MASK_SHIFT - 47 | |
707 | .error "virtual address width changed -- sysret checks need update" | |
708 | .endif | |
709 | shr $__VIRTUAL_MASK_SHIFT, %rcx | |
710 | jnz opportunistic_sysret_failed | |
711 | ||
f2db9382 | 712 | cmpq $__USER_CS,CS(%rsp) /* CS must match SYSRET */ |
2a23c6b8 AL |
713 | jne opportunistic_sysret_failed |
714 | ||
f2db9382 DV |
715 | movq R11(%rsp),%r11 |
716 | cmpq %r11,EFLAGS(%rsp) /* R11 == RFLAGS */ | |
2a23c6b8 AL |
717 | jne opportunistic_sysret_failed |
718 | ||
f2db9382 | 719 | testq $X86_EFLAGS_RF,%r11 /* sysret can't restore RF */ |
2a23c6b8 AL |
720 | jnz opportunistic_sysret_failed |
721 | ||
722 | /* nothing to check for RSP */ | |
723 | ||
f2db9382 | 724 | cmpq $__USER_DS,SS(%rsp) /* SS must match SYSRET */ |
2a23c6b8 AL |
725 | jne opportunistic_sysret_failed |
726 | ||
727 | /* | |
728 | * We win! This label is here just for ease of understanding | |
729 | * perf profiles. Nothing jumps here. | |
730 | */ | |
731 | irq_return_via_sysret: | |
732 | CFI_REMEMBER_STATE | |
d441c1f2 DV |
733 | /* r11 is already restored (see code above) */ |
734 | RESTORE_C_REGS_EXCEPT_R11 | |
735 | movq RSP(%rsp),%rsp | |
2a23c6b8 AL |
736 | USERGS_SYSRET64 |
737 | CFI_RESTORE_STATE | |
738 | ||
739 | opportunistic_sysret_failed: | |
72fe4858 | 740 | SWAPGS |
2601e64d IM |
741 | jmp restore_args |
742 | ||
10cd706d | 743 | retint_restore_args: /* return to kernel space */ |
72fe4858 | 744 | DISABLE_INTERRUPTS(CLBR_ANY) |
2601e64d IM |
745 | /* |
746 | * The iretq could re-enable interrupts: | |
747 | */ | |
748 | TRACE_IRQS_IRETQ | |
749 | restore_args: | |
76f5df43 DV |
750 | RESTORE_C_REGS |
751 | REMOVE_PT_GPREGS_FROM_STACK 8 | |
3701d863 | 752 | |
f7f3d791 | 753 | irq_return: |
7209a75d AL |
754 | INTERRUPT_RETURN |
755 | ||
756 | ENTRY(native_iret) | |
3891a04a PA |
757 | /* |
758 | * Are we returning to a stack segment from the LDT? Note: in | |
759 | * 64-bit mode SS:RSP on the exception stack is always valid. | |
760 | */ | |
34273f41 | 761 | #ifdef CONFIG_X86_ESPFIX64 |
3891a04a | 762 | testb $4,(SS-RIP)(%rsp) |
7209a75d | 763 | jnz native_irq_return_ldt |
34273f41 | 764 | #endif |
3891a04a | 765 | |
af726f21 | 766 | .global native_irq_return_iret |
7209a75d | 767 | native_irq_return_iret: |
b645af2d AL |
768 | /* |
769 | * This may fault. Non-paranoid faults on return to userspace are | |
770 | * handled by fixup_bad_iret. These include #SS, #GP, and #NP. | |
771 | * Double-faults due to espfix64 are handled in do_double_fault. | |
772 | * Other faults here are fatal. | |
773 | */ | |
1da177e4 | 774 | iretq |
3701d863 | 775 | |
34273f41 | 776 | #ifdef CONFIG_X86_ESPFIX64 |
7209a75d | 777 | native_irq_return_ldt: |
3891a04a PA |
778 | pushq_cfi %rax |
779 | pushq_cfi %rdi | |
780 | SWAPGS | |
781 | movq PER_CPU_VAR(espfix_waddr),%rdi | |
782 | movq %rax,(0*8)(%rdi) /* RAX */ | |
783 | movq (2*8)(%rsp),%rax /* RIP */ | |
784 | movq %rax,(1*8)(%rdi) | |
785 | movq (3*8)(%rsp),%rax /* CS */ | |
786 | movq %rax,(2*8)(%rdi) | |
787 | movq (4*8)(%rsp),%rax /* RFLAGS */ | |
788 | movq %rax,(3*8)(%rdi) | |
789 | movq (6*8)(%rsp),%rax /* SS */ | |
790 | movq %rax,(5*8)(%rdi) | |
791 | movq (5*8)(%rsp),%rax /* RSP */ | |
792 | movq %rax,(4*8)(%rdi) | |
793 | andl $0xffff0000,%eax | |
794 | popq_cfi %rdi | |
795 | orq PER_CPU_VAR(espfix_stack),%rax | |
796 | SWAPGS | |
797 | movq %rax,%rsp | |
798 | popq_cfi %rax | |
7209a75d | 799 | jmp native_irq_return_iret |
34273f41 | 800 | #endif |
3891a04a | 801 | |
7effaa88 | 802 | /* edi: workmask, edx: work */ |
1da177e4 | 803 | retint_careful: |
7effaa88 | 804 | CFI_RESTORE_STATE |
1da177e4 LT |
805 | bt $TIF_NEED_RESCHED,%edx |
806 | jnc retint_signal | |
2601e64d | 807 | TRACE_IRQS_ON |
72fe4858 | 808 | ENABLE_INTERRUPTS(CLBR_NONE) |
df5d1874 | 809 | pushq_cfi %rdi |
0430499c | 810 | SCHEDULE_USER |
df5d1874 | 811 | popq_cfi %rdi |
1da177e4 | 812 | GET_THREAD_INFO(%rcx) |
72fe4858 | 813 | DISABLE_INTERRUPTS(CLBR_NONE) |
2601e64d | 814 | TRACE_IRQS_OFF |
1da177e4 | 815 | jmp retint_check |
0bd7b798 | 816 | |
1da177e4 | 817 | retint_signal: |
8f4d37ec | 818 | testl $_TIF_DO_NOTIFY_MASK,%edx |
10ffdbb8 | 819 | jz retint_swapgs |
2601e64d | 820 | TRACE_IRQS_ON |
72fe4858 | 821 | ENABLE_INTERRUPTS(CLBR_NONE) |
76f5df43 | 822 | SAVE_EXTRA_REGS |
0bd7b798 | 823 | movq $-1,ORIG_RAX(%rsp) |
3829ee6b | 824 | xorl %esi,%esi # oldset |
1da177e4 LT |
825 | movq %rsp,%rdi # &pt_regs |
826 | call do_notify_resume | |
76f5df43 | 827 | RESTORE_EXTRA_REGS |
72fe4858 | 828 | DISABLE_INTERRUPTS(CLBR_NONE) |
2601e64d | 829 | TRACE_IRQS_OFF |
be9e6870 | 830 | GET_THREAD_INFO(%rcx) |
eca91e78 | 831 | jmp retint_with_reschedule |
1da177e4 LT |
832 | |
833 | #ifdef CONFIG_PREEMPT | |
834 | /* Returning to kernel space. Check if we need preemption */ | |
835 | /* rcx: threadinfo. interrupts off. */ | |
b06babac | 836 | ENTRY(retint_kernel) |
c2daa3be | 837 | cmpl $0,PER_CPU_VAR(__preempt_count) |
1da177e4 | 838 | jnz retint_restore_args |
f2db9382 | 839 | bt $9,EFLAGS(%rsp) /* interrupts off? */ |
1da177e4 LT |
840 | jnc retint_restore_args |
841 | call preempt_schedule_irq | |
842 | jmp exit_intr | |
0bd7b798 | 843 | #endif |
1da177e4 | 844 | CFI_ENDPROC |
4b787e0b | 845 | END(common_interrupt) |
3891a04a | 846 | |
1da177e4 LT |
847 | /* |
848 | * APIC interrupts. | |
0bd7b798 | 849 | */ |
cf910e83 | 850 | .macro apicinterrupt3 num sym do_sym |
322648d1 | 851 | ENTRY(\sym) |
7effaa88 | 852 | INTR_FRAME |
ee4eb87b | 853 | ASM_CLAC |
df5d1874 | 854 | pushq_cfi $~(\num) |
39e95433 | 855 | .Lcommon_\sym: |
322648d1 | 856 | interrupt \do_sym |
1da177e4 LT |
857 | jmp ret_from_intr |
858 | CFI_ENDPROC | |
322648d1 AH |
859 | END(\sym) |
860 | .endm | |
1da177e4 | 861 | |
cf910e83 SA |
862 | #ifdef CONFIG_TRACING |
863 | #define trace(sym) trace_##sym | |
864 | #define smp_trace(sym) smp_trace_##sym | |
865 | ||
866 | .macro trace_apicinterrupt num sym | |
867 | apicinterrupt3 \num trace(\sym) smp_trace(\sym) | |
868 | .endm | |
869 | #else | |
870 | .macro trace_apicinterrupt num sym do_sym | |
871 | .endm | |
872 | #endif | |
873 | ||
874 | .macro apicinterrupt num sym do_sym | |
875 | apicinterrupt3 \num \sym \do_sym | |
876 | trace_apicinterrupt \num \sym | |
877 | .endm | |
878 | ||
322648d1 | 879 | #ifdef CONFIG_SMP |
cf910e83 | 880 | apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR \ |
322648d1 | 881 | irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt |
cf910e83 | 882 | apicinterrupt3 REBOOT_VECTOR \ |
4ef702c1 | 883 | reboot_interrupt smp_reboot_interrupt |
322648d1 | 884 | #endif |
1da177e4 | 885 | |
03b48632 | 886 | #ifdef CONFIG_X86_UV |
cf910e83 | 887 | apicinterrupt3 UV_BAU_MESSAGE \ |
322648d1 | 888 | uv_bau_message_intr1 uv_bau_message_interrupt |
03b48632 | 889 | #endif |
322648d1 AH |
890 | apicinterrupt LOCAL_TIMER_VECTOR \ |
891 | apic_timer_interrupt smp_apic_timer_interrupt | |
4a4de9c7 DS |
892 | apicinterrupt X86_PLATFORM_IPI_VECTOR \ |
893 | x86_platform_ipi smp_x86_platform_ipi | |
89b831ef | 894 | |
d78f2664 | 895 | #ifdef CONFIG_HAVE_KVM |
cf910e83 | 896 | apicinterrupt3 POSTED_INTR_VECTOR \ |
d78f2664 YZ |
897 | kvm_posted_intr_ipi smp_kvm_posted_intr_ipi |
898 | #endif | |
899 | ||
33e5ff63 | 900 | #ifdef CONFIG_X86_MCE_THRESHOLD |
322648d1 | 901 | apicinterrupt THRESHOLD_APIC_VECTOR \ |
7856f6cc | 902 | threshold_interrupt smp_threshold_interrupt |
33e5ff63 SA |
903 | #endif |
904 | ||
905 | #ifdef CONFIG_X86_THERMAL_VECTOR | |
322648d1 AH |
906 | apicinterrupt THERMAL_APIC_VECTOR \ |
907 | thermal_interrupt smp_thermal_interrupt | |
33e5ff63 | 908 | #endif |
1812924b | 909 | |
322648d1 AH |
910 | #ifdef CONFIG_SMP |
911 | apicinterrupt CALL_FUNCTION_SINGLE_VECTOR \ | |
912 | call_function_single_interrupt smp_call_function_single_interrupt | |
913 | apicinterrupt CALL_FUNCTION_VECTOR \ | |
914 | call_function_interrupt smp_call_function_interrupt | |
915 | apicinterrupt RESCHEDULE_VECTOR \ | |
916 | reschedule_interrupt smp_reschedule_interrupt | |
917 | #endif | |
1da177e4 | 918 | |
322648d1 AH |
919 | apicinterrupt ERROR_APIC_VECTOR \ |
920 | error_interrupt smp_error_interrupt | |
921 | apicinterrupt SPURIOUS_APIC_VECTOR \ | |
922 | spurious_interrupt smp_spurious_interrupt | |
0bd7b798 | 923 | |
e360adbe PZ |
924 | #ifdef CONFIG_IRQ_WORK |
925 | apicinterrupt IRQ_WORK_VECTOR \ | |
926 | irq_work_interrupt smp_irq_work_interrupt | |
241771ef IM |
927 | #endif |
928 | ||
1da177e4 LT |
929 | /* |
930 | * Exception entry points. | |
0bd7b798 | 931 | */ |
9b476688 | 932 | #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss) + (TSS_ist + ((x) - 1) * 8) |
577ed45e AL |
933 | |
934 | .macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 | |
322648d1 | 935 | ENTRY(\sym) |
577ed45e AL |
936 | /* Sanity check */ |
937 | .if \shift_ist != -1 && \paranoid == 0 | |
938 | .error "using shift_ist requires paranoid=1" | |
939 | .endif | |
940 | ||
cb5dd2c5 AL |
941 | .if \has_error_code |
942 | XCPT_FRAME | |
943 | .else | |
7effaa88 | 944 | INTR_FRAME |
cb5dd2c5 | 945 | .endif |
1da177e4 | 946 | |
ee4eb87b | 947 | ASM_CLAC |
b8b1d08b | 948 | PARAVIRT_ADJUST_EXCEPTION_FRAME |
cb5dd2c5 AL |
949 | |
950 | .ifeq \has_error_code | |
951 | pushq_cfi $-1 /* ORIG_RAX: no syscall to restart */ | |
952 | .endif | |
953 | ||
76f5df43 | 954 | ALLOC_PT_GPREGS_ON_STACK |
cb5dd2c5 AL |
955 | |
956 | .if \paranoid | |
48e08d0f AL |
957 | .if \paranoid == 1 |
958 | CFI_REMEMBER_STATE | |
959 | testl $3, CS(%rsp) /* If coming from userspace, switch */ | |
960 | jnz 1f /* stacks. */ | |
961 | .endif | |
ebfc453e | 962 | call paranoid_entry |
cb5dd2c5 AL |
963 | .else |
964 | call error_entry | |
965 | .endif | |
ebfc453e | 966 | /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */ |
cb5dd2c5 | 967 | |
1bd24efc | 968 | DEFAULT_FRAME 0 |
cb5dd2c5 AL |
969 | |
970 | .if \paranoid | |
577ed45e AL |
971 | .if \shift_ist != -1 |
972 | TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */ | |
973 | .else | |
b8b1d08b | 974 | TRACE_IRQS_OFF |
cb5dd2c5 | 975 | .endif |
577ed45e | 976 | .endif |
cb5dd2c5 AL |
977 | |
978 | movq %rsp,%rdi /* pt_regs pointer */ | |
979 | ||
980 | .if \has_error_code | |
981 | movq ORIG_RAX(%rsp),%rsi /* get error code */ | |
982 | movq $-1,ORIG_RAX(%rsp) /* no syscall to restart */ | |
983 | .else | |
984 | xorl %esi,%esi /* no error code */ | |
985 | .endif | |
986 | ||
577ed45e | 987 | .if \shift_ist != -1 |
9b476688 | 988 | subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) |
577ed45e AL |
989 | .endif |
990 | ||
322648d1 | 991 | call \do_sym |
cb5dd2c5 | 992 | |
577ed45e | 993 | .if \shift_ist != -1 |
9b476688 | 994 | addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) |
577ed45e AL |
995 | .endif |
996 | ||
ebfc453e | 997 | /* these procedures expect "no swapgs" flag in ebx */ |
cb5dd2c5 | 998 | .if \paranoid |
ebfc453e | 999 | jmp paranoid_exit |
cb5dd2c5 | 1000 | .else |
ebfc453e | 1001 | jmp error_exit |
cb5dd2c5 AL |
1002 | .endif |
1003 | ||
48e08d0f AL |
1004 | .if \paranoid == 1 |
1005 | CFI_RESTORE_STATE | |
1006 | /* | |
1007 | * Paranoid entry from userspace. Switch stacks and treat it | |
1008 | * as a normal entry. This means that paranoid handlers | |
1009 | * run in real process context if user_mode(regs). | |
1010 | */ | |
1011 | 1: | |
1012 | call error_entry | |
1013 | ||
1014 | DEFAULT_FRAME 0 | |
1015 | ||
1016 | movq %rsp,%rdi /* pt_regs pointer */ | |
1017 | call sync_regs | |
1018 | movq %rax,%rsp /* switch stack */ | |
1019 | ||
1020 | movq %rsp,%rdi /* pt_regs pointer */ | |
1021 | ||
1022 | .if \has_error_code | |
1023 | movq ORIG_RAX(%rsp),%rsi /* get error code */ | |
1024 | movq $-1,ORIG_RAX(%rsp) /* no syscall to restart */ | |
1025 | .else | |
1026 | xorl %esi,%esi /* no error code */ | |
1027 | .endif | |
1028 | ||
1029 | call \do_sym | |
1030 | ||
1031 | jmp error_exit /* %ebx: no swapgs flag */ | |
1032 | .endif | |
1033 | ||
b8b1d08b | 1034 | CFI_ENDPROC |
ddeb8f21 | 1035 | END(\sym) |
322648d1 | 1036 | .endm |
b8b1d08b | 1037 | |
25c74b10 | 1038 | #ifdef CONFIG_TRACING |
cb5dd2c5 AL |
1039 | .macro trace_idtentry sym do_sym has_error_code:req |
1040 | idtentry trace(\sym) trace(\do_sym) has_error_code=\has_error_code | |
1041 | idtentry \sym \do_sym has_error_code=\has_error_code | |
25c74b10 SA |
1042 | .endm |
1043 | #else | |
cb5dd2c5 AL |
1044 | .macro trace_idtentry sym do_sym has_error_code:req |
1045 | idtentry \sym \do_sym has_error_code=\has_error_code | |
25c74b10 SA |
1046 | .endm |
1047 | #endif | |
1048 | ||
cb5dd2c5 AL |
1049 | idtentry divide_error do_divide_error has_error_code=0 |
1050 | idtentry overflow do_overflow has_error_code=0 | |
1051 | idtentry bounds do_bounds has_error_code=0 | |
1052 | idtentry invalid_op do_invalid_op has_error_code=0 | |
1053 | idtentry device_not_available do_device_not_available has_error_code=0 | |
48e08d0f | 1054 | idtentry double_fault do_double_fault has_error_code=1 paranoid=2 |
cb5dd2c5 AL |
1055 | idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0 |
1056 | idtentry invalid_TSS do_invalid_TSS has_error_code=1 | |
1057 | idtentry segment_not_present do_segment_not_present has_error_code=1 | |
1058 | idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0 | |
1059 | idtentry coprocessor_error do_coprocessor_error has_error_code=0 | |
1060 | idtentry alignment_check do_alignment_check has_error_code=1 | |
1061 | idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0 | |
5cec93c2 | 1062 | |
2601e64d | 1063 | |
9f1e87ea CG |
1064 | /* Reload gs selector with exception handling */ |
1065 | /* edi: new selector */ | |
9f9d489a | 1066 | ENTRY(native_load_gs_index) |
7effaa88 | 1067 | CFI_STARTPROC |
df5d1874 | 1068 | pushfq_cfi |
b8aa287f | 1069 | DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI) |
9f1e87ea | 1070 | SWAPGS |
0bd7b798 | 1071 | gs_change: |
9f1e87ea | 1072 | movl %edi,%gs |
1da177e4 | 1073 | 2: mfence /* workaround */ |
72fe4858 | 1074 | SWAPGS |
df5d1874 | 1075 | popfq_cfi |
9f1e87ea | 1076 | ret |
7effaa88 | 1077 | CFI_ENDPROC |
6efdcfaf | 1078 | END(native_load_gs_index) |
0bd7b798 | 1079 | |
d7abc0fa | 1080 | _ASM_EXTABLE(gs_change,bad_gs) |
9f1e87ea | 1081 | .section .fixup,"ax" |
1da177e4 | 1082 | /* running with kernelgs */ |
0bd7b798 | 1083 | bad_gs: |
72fe4858 | 1084 | SWAPGS /* switch back to user gs */ |
1da177e4 | 1085 | xorl %eax,%eax |
9f1e87ea CG |
1086 | movl %eax,%gs |
1087 | jmp 2b | |
1088 | .previous | |
0bd7b798 | 1089 | |
2699500b | 1090 | /* Call softirq on interrupt stack. Interrupts are off. */ |
7d65f4a6 | 1091 | ENTRY(do_softirq_own_stack) |
7effaa88 | 1092 | CFI_STARTPROC |
df5d1874 | 1093 | pushq_cfi %rbp |
2699500b AK |
1094 | CFI_REL_OFFSET rbp,0 |
1095 | mov %rsp,%rbp | |
1096 | CFI_DEF_CFA_REGISTER rbp | |
56895530 | 1097 | incl PER_CPU_VAR(irq_count) |
26f80bd6 | 1098 | cmove PER_CPU_VAR(irq_stack_ptr),%rsp |
2699500b | 1099 | push %rbp # backlink for old unwinder |
ed6b676c | 1100 | call __do_softirq |
2699500b | 1101 | leaveq |
df5d1874 | 1102 | CFI_RESTORE rbp |
7effaa88 | 1103 | CFI_DEF_CFA_REGISTER rsp |
2699500b | 1104 | CFI_ADJUST_CFA_OFFSET -8 |
56895530 | 1105 | decl PER_CPU_VAR(irq_count) |
ed6b676c | 1106 | ret |
7effaa88 | 1107 | CFI_ENDPROC |
7d65f4a6 | 1108 | END(do_softirq_own_stack) |
75154f40 | 1109 | |
3d75e1b8 | 1110 | #ifdef CONFIG_XEN |
cb5dd2c5 | 1111 | idtentry xen_hypervisor_callback xen_do_hypervisor_callback has_error_code=0 |
3d75e1b8 JF |
1112 | |
1113 | /* | |
9f1e87ea CG |
1114 | * A note on the "critical region" in our callback handler. |
1115 | * We want to avoid stacking callback handlers due to events occurring | |
1116 | * during handling of the last event. To do this, we keep events disabled | |
1117 | * until we've done all processing. HOWEVER, we must enable events before | |
1118 | * popping the stack frame (can't be done atomically) and so it would still | |
1119 | * be possible to get enough handler activations to overflow the stack. | |
1120 | * Although unlikely, bugs of that kind are hard to track down, so we'd | |
1121 | * like to avoid the possibility. | |
1122 | * So, on entry to the handler we detect whether we interrupted an | |
1123 | * existing activation in its critical region -- if so, we pop the current | |
1124 | * activation and restart the handler using the previous one. | |
1125 | */ | |
3d75e1b8 JF |
1126 | ENTRY(xen_do_hypervisor_callback) # do_hypervisor_callback(struct *pt_regs) |
1127 | CFI_STARTPROC | |
9f1e87ea CG |
1128 | /* |
1129 | * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will | |
1130 | * see the correct pointer to the pt_regs | |
1131 | */ | |
3d75e1b8 JF |
1132 | movq %rdi, %rsp # we don't return, adjust the stack frame |
1133 | CFI_ENDPROC | |
dcd072e2 | 1134 | DEFAULT_FRAME |
56895530 | 1135 | 11: incl PER_CPU_VAR(irq_count) |
3d75e1b8 JF |
1136 | movq %rsp,%rbp |
1137 | CFI_DEF_CFA_REGISTER rbp | |
26f80bd6 | 1138 | cmovzq PER_CPU_VAR(irq_stack_ptr),%rsp |
3d75e1b8 JF |
1139 | pushq %rbp # backlink for old unwinder |
1140 | call xen_evtchn_do_upcall | |
1141 | popq %rsp | |
1142 | CFI_DEF_CFA_REGISTER rsp | |
56895530 | 1143 | decl PER_CPU_VAR(irq_count) |
fdfd811d DV |
1144 | #ifndef CONFIG_PREEMPT |
1145 | call xen_maybe_preempt_hcall | |
1146 | #endif | |
3d75e1b8 JF |
1147 | jmp error_exit |
1148 | CFI_ENDPROC | |
371c394a | 1149 | END(xen_do_hypervisor_callback) |
3d75e1b8 JF |
1150 | |
1151 | /* | |
9f1e87ea CG |
1152 | * Hypervisor uses this for application faults while it executes. |
1153 | * We get here for two reasons: | |
1154 | * 1. Fault while reloading DS, ES, FS or GS | |
1155 | * 2. Fault while executing IRET | |
1156 | * Category 1 we do not need to fix up as Xen has already reloaded all segment | |
1157 | * registers that could be reloaded and zeroed the others. | |
1158 | * Category 2 we fix up by killing the current process. We cannot use the | |
1159 | * normal Linux return path in this case because if we use the IRET hypercall | |
1160 | * to pop the stack frame we end up in an infinite loop of failsafe callbacks. | |
1161 | * We distinguish between categories by comparing each saved segment register | |
1162 | * with its current contents: any discrepancy means we in category 1. | |
1163 | */ | |
3d75e1b8 | 1164 | ENTRY(xen_failsafe_callback) |
dcd072e2 AH |
1165 | INTR_FRAME 1 (6*8) |
1166 | /*CFI_REL_OFFSET gs,GS*/ | |
1167 | /*CFI_REL_OFFSET fs,FS*/ | |
1168 | /*CFI_REL_OFFSET es,ES*/ | |
1169 | /*CFI_REL_OFFSET ds,DS*/ | |
1170 | CFI_REL_OFFSET r11,8 | |
1171 | CFI_REL_OFFSET rcx,0 | |
3d75e1b8 JF |
1172 | movw %ds,%cx |
1173 | cmpw %cx,0x10(%rsp) | |
1174 | CFI_REMEMBER_STATE | |
1175 | jne 1f | |
1176 | movw %es,%cx | |
1177 | cmpw %cx,0x18(%rsp) | |
1178 | jne 1f | |
1179 | movw %fs,%cx | |
1180 | cmpw %cx,0x20(%rsp) | |
1181 | jne 1f | |
1182 | movw %gs,%cx | |
1183 | cmpw %cx,0x28(%rsp) | |
1184 | jne 1f | |
1185 | /* All segments match their saved values => Category 2 (Bad IRET). */ | |
1186 | movq (%rsp),%rcx | |
1187 | CFI_RESTORE rcx | |
1188 | movq 8(%rsp),%r11 | |
1189 | CFI_RESTORE r11 | |
1190 | addq $0x30,%rsp | |
1191 | CFI_ADJUST_CFA_OFFSET -0x30 | |
14ae22ba IM |
1192 | pushq_cfi $0 /* RIP */ |
1193 | pushq_cfi %r11 | |
1194 | pushq_cfi %rcx | |
4a5c3e77 | 1195 | jmp general_protection |
3d75e1b8 JF |
1196 | CFI_RESTORE_STATE |
1197 | 1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */ | |
1198 | movq (%rsp),%rcx | |
1199 | CFI_RESTORE rcx | |
1200 | movq 8(%rsp),%r11 | |
1201 | CFI_RESTORE r11 | |
1202 | addq $0x30,%rsp | |
1203 | CFI_ADJUST_CFA_OFFSET -0x30 | |
a349e23d | 1204 | pushq_cfi $-1 /* orig_ax = -1 => not a system call */ |
76f5df43 DV |
1205 | ALLOC_PT_GPREGS_ON_STACK |
1206 | SAVE_C_REGS | |
1207 | SAVE_EXTRA_REGS | |
3d75e1b8 JF |
1208 | jmp error_exit |
1209 | CFI_ENDPROC | |
3d75e1b8 JF |
1210 | END(xen_failsafe_callback) |
1211 | ||
cf910e83 | 1212 | apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ |
38e20b07 SY |
1213 | xen_hvm_callback_vector xen_evtchn_do_upcall |
1214 | ||
3d75e1b8 | 1215 | #endif /* CONFIG_XEN */ |
ddeb8f21 | 1216 | |
bc2b0331 | 1217 | #if IS_ENABLED(CONFIG_HYPERV) |
cf910e83 | 1218 | apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ |
bc2b0331 S |
1219 | hyperv_callback_vector hyperv_vector_handler |
1220 | #endif /* CONFIG_HYPERV */ | |
1221 | ||
577ed45e AL |
1222 | idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK |
1223 | idtentry int3 do_int3 has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK | |
6f442be2 | 1224 | idtentry stack_segment do_stack_segment has_error_code=1 |
6cac5a92 | 1225 | #ifdef CONFIG_XEN |
cb5dd2c5 AL |
1226 | idtentry xen_debug do_debug has_error_code=0 |
1227 | idtentry xen_int3 do_int3 has_error_code=0 | |
1228 | idtentry xen_stack_segment do_stack_segment has_error_code=1 | |
6cac5a92 | 1229 | #endif |
cb5dd2c5 AL |
1230 | idtentry general_protection do_general_protection has_error_code=1 |
1231 | trace_idtentry page_fault do_page_fault has_error_code=1 | |
631bc487 | 1232 | #ifdef CONFIG_KVM_GUEST |
cb5dd2c5 | 1233 | idtentry async_page_fault do_async_page_fault has_error_code=1 |
631bc487 | 1234 | #endif |
ddeb8f21 | 1235 | #ifdef CONFIG_X86_MCE |
cb5dd2c5 | 1236 | idtentry machine_check has_error_code=0 paranoid=1 do_sym=*machine_check_vector(%rip) |
ddeb8f21 AH |
1237 | #endif |
1238 | ||
ebfc453e DV |
1239 | /* |
1240 | * Save all registers in pt_regs, and switch gs if needed. | |
1241 | * Use slow, but surefire "are we in kernel?" check. | |
1242 | * Return: ebx=0: need swapgs on exit, ebx=1: otherwise | |
1243 | */ | |
1244 | ENTRY(paranoid_entry) | |
1245 | XCPT_FRAME 1 15*8 | |
1eeb207f DV |
1246 | cld |
1247 | SAVE_C_REGS 8 | |
1248 | SAVE_EXTRA_REGS 8 | |
1249 | movl $1,%ebx | |
1250 | movl $MSR_GS_BASE,%ecx | |
1251 | rdmsr | |
1252 | testl %edx,%edx | |
1253 | js 1f /* negative -> in kernel */ | |
1254 | SWAPGS | |
1255 | xorl %ebx,%ebx | |
1256 | 1: ret | |
1257 | CFI_ENDPROC | |
ebfc453e | 1258 | END(paranoid_entry) |
ddeb8f21 | 1259 | |
ebfc453e DV |
1260 | /* |
1261 | * "Paranoid" exit path from exception stack. This is invoked | |
1262 | * only on return from non-NMI IST interrupts that came | |
1263 | * from kernel space. | |
1264 | * | |
1265 | * We may be returning to very strange contexts (e.g. very early | |
1266 | * in syscall entry), so checking for preemption here would | |
1267 | * be complicated. Fortunately, we there's no good reason | |
1268 | * to try to handle preemption here. | |
1269 | */ | |
1270 | /* On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it) */ | |
ddeb8f21 | 1271 | ENTRY(paranoid_exit) |
1f130a78 | 1272 | DEFAULT_FRAME |
ddeb8f21 | 1273 | DISABLE_INTERRUPTS(CLBR_NONE) |
5963e317 | 1274 | TRACE_IRQS_OFF_DEBUG |
ddeb8f21 | 1275 | testl %ebx,%ebx /* swapgs needed? */ |
0d550836 | 1276 | jnz paranoid_exit_no_swapgs |
f2db9382 | 1277 | TRACE_IRQS_IRETQ |
ddeb8f21 | 1278 | SWAPGS_UNSAFE_STACK |
0d550836 DV |
1279 | jmp paranoid_exit_restore |
1280 | paranoid_exit_no_swapgs: | |
f2db9382 | 1281 | TRACE_IRQS_IRETQ_DEBUG |
0d550836 | 1282 | paranoid_exit_restore: |
76f5df43 DV |
1283 | RESTORE_EXTRA_REGS |
1284 | RESTORE_C_REGS | |
1285 | REMOVE_PT_GPREGS_FROM_STACK 8 | |
48e08d0f | 1286 | INTERRUPT_RETURN |
ddeb8f21 AH |
1287 | CFI_ENDPROC |
1288 | END(paranoid_exit) | |
1289 | ||
1290 | /* | |
ebfc453e DV |
1291 | * Save all registers in pt_regs, and switch gs if needed. |
1292 | * Return: ebx=0: need swapgs on exit, ebx=1: otherwise | |
ddeb8f21 AH |
1293 | */ |
1294 | ENTRY(error_entry) | |
ebfc453e | 1295 | XCPT_FRAME 1 15*8 |
ddeb8f21 | 1296 | cld |
76f5df43 DV |
1297 | SAVE_C_REGS 8 |
1298 | SAVE_EXTRA_REGS 8 | |
ddeb8f21 AH |
1299 | xorl %ebx,%ebx |
1300 | testl $3,CS+8(%rsp) | |
1301 | je error_kernelspace | |
1302 | error_swapgs: | |
1303 | SWAPGS | |
1304 | error_sti: | |
1305 | TRACE_IRQS_OFF | |
1306 | ret | |
ddeb8f21 | 1307 | |
ebfc453e DV |
1308 | /* |
1309 | * There are two places in the kernel that can potentially fault with | |
1310 | * usergs. Handle them here. B stepping K8s sometimes report a | |
1311 | * truncated RIP for IRET exceptions returning to compat mode. Check | |
1312 | * for these here too. | |
1313 | */ | |
ddeb8f21 | 1314 | error_kernelspace: |
3bab13b0 | 1315 | CFI_REL_OFFSET rcx, RCX+8 |
ddeb8f21 | 1316 | incl %ebx |
7209a75d | 1317 | leaq native_irq_return_iret(%rip),%rcx |
ddeb8f21 | 1318 | cmpq %rcx,RIP+8(%rsp) |
b645af2d | 1319 | je error_bad_iret |
ae24ffe5 BG |
1320 | movl %ecx,%eax /* zero extend */ |
1321 | cmpq %rax,RIP+8(%rsp) | |
1322 | je bstep_iret | |
ddeb8f21 | 1323 | cmpq $gs_change,RIP+8(%rsp) |
9f1e87ea | 1324 | je error_swapgs |
ddeb8f21 | 1325 | jmp error_sti |
ae24ffe5 BG |
1326 | |
1327 | bstep_iret: | |
1328 | /* Fix truncated RIP */ | |
1329 | movq %rcx,RIP+8(%rsp) | |
b645af2d AL |
1330 | /* fall through */ |
1331 | ||
1332 | error_bad_iret: | |
1333 | SWAPGS | |
1334 | mov %rsp,%rdi | |
1335 | call fixup_bad_iret | |
1336 | mov %rax,%rsp | |
1337 | decl %ebx /* Return to usergs */ | |
1338 | jmp error_sti | |
e6b04b6b | 1339 | CFI_ENDPROC |
ddeb8f21 AH |
1340 | END(error_entry) |
1341 | ||
1342 | ||
ebfc453e | 1343 | /* On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it) */ |
ddeb8f21 AH |
1344 | ENTRY(error_exit) |
1345 | DEFAULT_FRAME | |
1346 | movl %ebx,%eax | |
76f5df43 | 1347 | RESTORE_EXTRA_REGS |
ddeb8f21 AH |
1348 | DISABLE_INTERRUPTS(CLBR_NONE) |
1349 | TRACE_IRQS_OFF | |
1350 | GET_THREAD_INFO(%rcx) | |
1351 | testl %eax,%eax | |
1352 | jne retint_kernel | |
1353 | LOCKDEP_SYS_EXIT_IRQ | |
1354 | movl TI_flags(%rcx),%edx | |
1355 | movl $_TIF_WORK_MASK,%edi | |
1356 | andl %edi,%edx | |
1357 | jnz retint_careful | |
1358 | jmp retint_swapgs | |
1359 | CFI_ENDPROC | |
1360 | END(error_exit) | |
1361 | ||
3f3c8b8c SR |
1362 | /* |
1363 | * Test if a given stack is an NMI stack or not. | |
1364 | */ | |
1365 | .macro test_in_nmi reg stack nmi_ret normal_ret | |
1366 | cmpq %\reg, \stack | |
1367 | ja \normal_ret | |
1368 | subq $EXCEPTION_STKSZ, %\reg | |
1369 | cmpq %\reg, \stack | |
1370 | jb \normal_ret | |
1371 | jmp \nmi_ret | |
1372 | .endm | |
ddeb8f21 AH |
1373 | |
1374 | /* runs on exception stack */ | |
1375 | ENTRY(nmi) | |
1376 | INTR_FRAME | |
1377 | PARAVIRT_ADJUST_EXCEPTION_FRAME | |
3f3c8b8c SR |
1378 | /* |
1379 | * We allow breakpoints in NMIs. If a breakpoint occurs, then | |
1380 | * the iretq it performs will take us out of NMI context. | |
1381 | * This means that we can have nested NMIs where the next | |
1382 | * NMI is using the top of the stack of the previous NMI. We | |
1383 | * can't let it execute because the nested NMI will corrupt the | |
1384 | * stack of the previous NMI. NMI handlers are not re-entrant | |
1385 | * anyway. | |
1386 | * | |
1387 | * To handle this case we do the following: | |
1388 | * Check the a special location on the stack that contains | |
1389 | * a variable that is set when NMIs are executing. | |
1390 | * The interrupted task's stack is also checked to see if it | |
1391 | * is an NMI stack. | |
1392 | * If the variable is not set and the stack is not the NMI | |
1393 | * stack then: | |
1394 | * o Set the special variable on the stack | |
1395 | * o Copy the interrupt frame into a "saved" location on the stack | |
1396 | * o Copy the interrupt frame into a "copy" location on the stack | |
1397 | * o Continue processing the NMI | |
1398 | * If the variable is set or the previous stack is the NMI stack: | |
1399 | * o Modify the "copy" location to jump to the repeate_nmi | |
1400 | * o return back to the first NMI | |
1401 | * | |
1402 | * Now on exit of the first NMI, we first clear the stack variable | |
1403 | * The NMI stack will tell any nested NMIs at that point that it is | |
1404 | * nested. Then we pop the stack normally with iret, and if there was | |
1405 | * a nested NMI that updated the copy interrupt stack frame, a | |
1406 | * jump will be made to the repeat_nmi code that will handle the second | |
1407 | * NMI. | |
1408 | */ | |
1409 | ||
146b2b09 | 1410 | /* Use %rdx as our temp variable throughout */ |
3f3c8b8c | 1411 | pushq_cfi %rdx |
62610913 | 1412 | CFI_REL_OFFSET rdx, 0 |
3f3c8b8c | 1413 | |
45d5a168 SR |
1414 | /* |
1415 | * If %cs was not the kernel segment, then the NMI triggered in user | |
1416 | * space, which means it is definitely not nested. | |
1417 | */ | |
a38449ef | 1418 | cmpl $__KERNEL_CS, 16(%rsp) |
45d5a168 SR |
1419 | jne first_nmi |
1420 | ||
3f3c8b8c SR |
1421 | /* |
1422 | * Check the special variable on the stack to see if NMIs are | |
1423 | * executing. | |
1424 | */ | |
a38449ef | 1425 | cmpl $1, -8(%rsp) |
3f3c8b8c SR |
1426 | je nested_nmi |
1427 | ||
1428 | /* | |
1429 | * Now test if the previous stack was an NMI stack. | |
1430 | * We need the double check. We check the NMI stack to satisfy the | |
1431 | * race when the first NMI clears the variable before returning. | |
1432 | * We check the variable because the first NMI could be in a | |
1433 | * breakpoint routine using a breakpoint stack. | |
1434 | */ | |
1435 | lea 6*8(%rsp), %rdx | |
1436 | test_in_nmi rdx, 4*8(%rsp), nested_nmi, first_nmi | |
62610913 | 1437 | CFI_REMEMBER_STATE |
3f3c8b8c SR |
1438 | |
1439 | nested_nmi: | |
1440 | /* | |
1441 | * Do nothing if we interrupted the fixup in repeat_nmi. | |
1442 | * It's about to repeat the NMI handler, so we are fine | |
1443 | * with ignoring this one. | |
1444 | */ | |
1445 | movq $repeat_nmi, %rdx | |
1446 | cmpq 8(%rsp), %rdx | |
1447 | ja 1f | |
1448 | movq $end_repeat_nmi, %rdx | |
1449 | cmpq 8(%rsp), %rdx | |
1450 | ja nested_nmi_out | |
1451 | ||
1452 | 1: | |
1453 | /* Set up the interrupted NMIs stack to jump to repeat_nmi */ | |
28696f43 | 1454 | leaq -1*8(%rsp), %rdx |
3f3c8b8c | 1455 | movq %rdx, %rsp |
28696f43 SQ |
1456 | CFI_ADJUST_CFA_OFFSET 1*8 |
1457 | leaq -10*8(%rsp), %rdx | |
3f3c8b8c SR |
1458 | pushq_cfi $__KERNEL_DS |
1459 | pushq_cfi %rdx | |
1460 | pushfq_cfi | |
1461 | pushq_cfi $__KERNEL_CS | |
1462 | pushq_cfi $repeat_nmi | |
1463 | ||
1464 | /* Put stack back */ | |
28696f43 SQ |
1465 | addq $(6*8), %rsp |
1466 | CFI_ADJUST_CFA_OFFSET -6*8 | |
3f3c8b8c SR |
1467 | |
1468 | nested_nmi_out: | |
1469 | popq_cfi %rdx | |
62610913 | 1470 | CFI_RESTORE rdx |
3f3c8b8c SR |
1471 | |
1472 | /* No need to check faults here */ | |
1473 | INTERRUPT_RETURN | |
1474 | ||
62610913 | 1475 | CFI_RESTORE_STATE |
3f3c8b8c SR |
1476 | first_nmi: |
1477 | /* | |
1478 | * Because nested NMIs will use the pushed location that we | |
1479 | * stored in rdx, we must keep that space available. | |
1480 | * Here's what our stack frame will look like: | |
1481 | * +-------------------------+ | |
1482 | * | original SS | | |
1483 | * | original Return RSP | | |
1484 | * | original RFLAGS | | |
1485 | * | original CS | | |
1486 | * | original RIP | | |
1487 | * +-------------------------+ | |
1488 | * | temp storage for rdx | | |
1489 | * +-------------------------+ | |
1490 | * | NMI executing variable | | |
1491 | * +-------------------------+ | |
3f3c8b8c SR |
1492 | * | copied SS | |
1493 | * | copied Return RSP | | |
1494 | * | copied RFLAGS | | |
1495 | * | copied CS | | |
1496 | * | copied RIP | | |
1497 | * +-------------------------+ | |
28696f43 SQ |
1498 | * | Saved SS | |
1499 | * | Saved Return RSP | | |
1500 | * | Saved RFLAGS | | |
1501 | * | Saved CS | | |
1502 | * | Saved RIP | | |
1503 | * +-------------------------+ | |
3f3c8b8c SR |
1504 | * | pt_regs | |
1505 | * +-------------------------+ | |
1506 | * | |
79fb4ad6 SR |
1507 | * The saved stack frame is used to fix up the copied stack frame |
1508 | * that a nested NMI may change to make the interrupted NMI iret jump | |
1509 | * to the repeat_nmi. The original stack frame and the temp storage | |
3f3c8b8c SR |
1510 | * is also used by nested NMIs and can not be trusted on exit. |
1511 | */ | |
79fb4ad6 | 1512 | /* Do not pop rdx, nested NMIs will corrupt that part of the stack */ |
62610913 JB |
1513 | movq (%rsp), %rdx |
1514 | CFI_RESTORE rdx | |
1515 | ||
3f3c8b8c SR |
1516 | /* Set the NMI executing variable on the stack. */ |
1517 | pushq_cfi $1 | |
1518 | ||
28696f43 SQ |
1519 | /* |
1520 | * Leave room for the "copied" frame | |
1521 | */ | |
1522 | subq $(5*8), %rsp | |
444723dc | 1523 | CFI_ADJUST_CFA_OFFSET 5*8 |
28696f43 | 1524 | |
3f3c8b8c SR |
1525 | /* Copy the stack frame to the Saved frame */ |
1526 | .rept 5 | |
28696f43 | 1527 | pushq_cfi 11*8(%rsp) |
3f3c8b8c | 1528 | .endr |
911d2bb5 | 1529 | CFI_DEF_CFA_OFFSET 5*8 |
62610913 | 1530 | |
79fb4ad6 SR |
1531 | /* Everything up to here is safe from nested NMIs */ |
1532 | ||
62610913 JB |
1533 | /* |
1534 | * If there was a nested NMI, the first NMI's iret will return | |
1535 | * here. But NMIs are still enabled and we can take another | |
1536 | * nested NMI. The nested NMI checks the interrupted RIP to see | |
1537 | * if it is between repeat_nmi and end_repeat_nmi, and if so | |
1538 | * it will just return, as we are about to repeat an NMI anyway. | |
1539 | * This makes it safe to copy to the stack frame that a nested | |
1540 | * NMI will update. | |
1541 | */ | |
1542 | repeat_nmi: | |
1543 | /* | |
1544 | * Update the stack variable to say we are still in NMI (the update | |
1545 | * is benign for the non-repeat case, where 1 was pushed just above | |
1546 | * to this very stack slot). | |
1547 | */ | |
28696f43 | 1548 | movq $1, 10*8(%rsp) |
3f3c8b8c SR |
1549 | |
1550 | /* Make another copy, this one may be modified by nested NMIs */ | |
28696f43 SQ |
1551 | addq $(10*8), %rsp |
1552 | CFI_ADJUST_CFA_OFFSET -10*8 | |
3f3c8b8c | 1553 | .rept 5 |
28696f43 | 1554 | pushq_cfi -6*8(%rsp) |
3f3c8b8c | 1555 | .endr |
28696f43 | 1556 | subq $(5*8), %rsp |
911d2bb5 | 1557 | CFI_DEF_CFA_OFFSET 5*8 |
62610913 | 1558 | end_repeat_nmi: |
3f3c8b8c SR |
1559 | |
1560 | /* | |
1561 | * Everything below this point can be preempted by a nested | |
79fb4ad6 SR |
1562 | * NMI if the first NMI took an exception and reset our iret stack |
1563 | * so that we repeat another NMI. | |
3f3c8b8c | 1564 | */ |
1fd466ef | 1565 | pushq_cfi $-1 /* ORIG_RAX: no syscall to restart */ |
76f5df43 DV |
1566 | ALLOC_PT_GPREGS_ON_STACK |
1567 | ||
1fd466ef | 1568 | /* |
ebfc453e | 1569 | * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit |
1fd466ef SR |
1570 | * as we should not be calling schedule in NMI context. |
1571 | * Even with normal interrupts enabled. An NMI should not be | |
1572 | * setting NEED_RESCHED or anything that normal interrupts and | |
1573 | * exceptions might do. | |
1574 | */ | |
ebfc453e | 1575 | call paranoid_entry |
ddeb8f21 | 1576 | DEFAULT_FRAME 0 |
7fbb98c5 SR |
1577 | |
1578 | /* | |
1579 | * Save off the CR2 register. If we take a page fault in the NMI then | |
1580 | * it could corrupt the CR2 value. If the NMI preempts a page fault | |
1581 | * handler before it was able to read the CR2 register, and then the | |
1582 | * NMI itself takes a page fault, the page fault that was preempted | |
1583 | * will read the information from the NMI page fault and not the | |
1584 | * origin fault. Save it off and restore it if it changes. | |
1585 | * Use the r12 callee-saved register. | |
1586 | */ | |
1587 | movq %cr2, %r12 | |
1588 | ||
ddeb8f21 AH |
1589 | /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */ |
1590 | movq %rsp,%rdi | |
1591 | movq $-1,%rsi | |
1592 | call do_nmi | |
7fbb98c5 SR |
1593 | |
1594 | /* Did the NMI take a page fault? Restore cr2 if it did */ | |
1595 | movq %cr2, %rcx | |
1596 | cmpq %rcx, %r12 | |
1597 | je 1f | |
1598 | movq %r12, %cr2 | |
1599 | 1: | |
1600 | ||
ddeb8f21 AH |
1601 | testl %ebx,%ebx /* swapgs needed? */ |
1602 | jnz nmi_restore | |
ddeb8f21 AH |
1603 | nmi_swapgs: |
1604 | SWAPGS_UNSAFE_STACK | |
1605 | nmi_restore: | |
76f5df43 DV |
1606 | RESTORE_EXTRA_REGS |
1607 | RESTORE_C_REGS | |
444723dc | 1608 | /* Pop the extra iret frame at once */ |
76f5df43 | 1609 | REMOVE_PT_GPREGS_FROM_STACK 6*8 |
28696f43 | 1610 | |
3f3c8b8c | 1611 | /* Clear the NMI executing stack variable */ |
28696f43 | 1612 | movq $0, 5*8(%rsp) |
ddeb8f21 | 1613 | jmp irq_return |
9f1e87ea | 1614 | CFI_ENDPROC |
ddeb8f21 AH |
1615 | END(nmi) |
1616 | ||
1617 | ENTRY(ignore_sysret) | |
1618 | CFI_STARTPROC | |
1619 | mov $-ENOSYS,%eax | |
1620 | sysret | |
1621 | CFI_ENDPROC | |
1622 | END(ignore_sysret) | |
1623 |