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x86: Call fixup_exception() before notify_die() in math_error()
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1da177e4 1/*
1da177e4 2 * Copyright (C) 1991, 1992 Linus Torvalds
a8c1be9d 3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
1da177e4
LT
4 *
5 * Pentium III FXSR, SSE support
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 */
8
9/*
c1d518c8 10 * Handle hardware traps and faults.
1da177e4 11 */
c767a54b
JP
12
13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
56dd9470 15#include <linux/context_tracking.h>
b5964405
IM
16#include <linux/interrupt.h>
17#include <linux/kallsyms.h>
18#include <linux/spinlock.h>
b5964405
IM
19#include <linux/kprobes.h>
20#include <linux/uaccess.h>
b5964405 21#include <linux/kdebug.h>
f503b5ae 22#include <linux/kgdb.h>
1da177e4 23#include <linux/kernel.h>
186f4360 24#include <linux/export.h>
b5964405 25#include <linux/ptrace.h>
b02ef20a 26#include <linux/uprobes.h>
1da177e4 27#include <linux/string.h>
b5964405 28#include <linux/delay.h>
1da177e4 29#include <linux/errno.h>
b5964405
IM
30#include <linux/kexec.h>
31#include <linux/sched.h>
68db0cf1 32#include <linux/sched/task_stack.h>
1da177e4 33#include <linux/timer.h>
1da177e4 34#include <linux/init.h>
91768d6c 35#include <linux/bug.h>
b5964405
IM
36#include <linux/nmi.h>
37#include <linux/mm.h>
c1d518c8
AH
38#include <linux/smp.h>
39#include <linux/io.h>
1da177e4 40
c0d12172
DJ
41#if defined(CONFIG_EDAC)
42#include <linux/edac.h>
43#endif
44
b5964405 45#include <asm/stacktrace.h>
1da177e4 46#include <asm/processor.h>
1da177e4 47#include <asm/debugreg.h>
60063497 48#include <linux/atomic.h>
35de5b06 49#include <asm/text-patching.h>
08d636b6 50#include <asm/ftrace.h>
c1d518c8 51#include <asm/traps.h>
1da177e4 52#include <asm/desc.h>
78f7f1e5 53#include <asm/fpu/internal.h>
ed1bbc40 54#include <asm/cpu_entry_area.h>
9e55e44e 55#include <asm/mce.h>
4eefbe79 56#include <asm/fixmap.h>
1164dd00 57#include <asm/mach_traps.h>
17f41571 58#include <asm/alternative.h>
a84eeaa9 59#include <asm/fpu/xstate.h>
e7126cf5 60#include <asm/trace/mpx.h>
fe3d197f 61#include <asm/mpx.h>
ba3e127e 62#include <asm/vm86.h>
6fc9dc81 63#include <asm/umip.h>
c1d518c8 64
081f75bb 65#ifdef CONFIG_X86_64
428cf902 66#include <asm/x86_init.h>
081f75bb
AH
67#include <asm/pgalloc.h>
68#include <asm/proto.h>
081f75bb 69#else
c1d518c8 70#include <asm/processor-flags.h>
8e6dafd6 71#include <asm/setup.h>
b2502b41 72#include <asm/proto.h>
081f75bb 73#endif
1da177e4 74
7854f822 75DECLARE_BITMAP(system_vectors, NR_VECTORS);
b77b881f 76
d99e1bd1 77static inline void cond_local_irq_enable(struct pt_regs *regs)
762db434
AH
78{
79 if (regs->flags & X86_EFLAGS_IF)
80 local_irq_enable();
81}
82
d99e1bd1 83static inline void cond_local_irq_disable(struct pt_regs *regs)
3d2a71a5
AH
84{
85 if (regs->flags & X86_EFLAGS_IF)
86 local_irq_disable();
3d2a71a5
AH
87}
88
aaee8c3c
AL
89/*
90 * In IST context, we explicitly disable preemption. This serves two
91 * purposes: it makes it much less likely that we would accidentally
92 * schedule in IST context and it will force a warning if we somehow
93 * manage to schedule by accident.
94 */
8c84014f 95void ist_enter(struct pt_regs *regs)
95927475 96{
f39b6f0e 97 if (user_mode(regs)) {
5778077d 98 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
95927475
AL
99 } else {
100 /*
101 * We might have interrupted pretty much anything. In
102 * fact, if we're a machine check, we can even interrupt
103 * NMI processing. We don't want in_nmi() to return true,
104 * but we need to notify RCU.
105 */
106 rcu_nmi_enter();
95927475 107 }
b926e6f6 108
aaee8c3c 109 preempt_disable();
b926e6f6
AL
110
111 /* This code is a bit fragile. Test it. */
f78f5b90 112 RCU_LOCKDEP_WARN(!rcu_is_watching(), "ist_enter didn't work");
95927475
AL
113}
114
8c84014f 115void ist_exit(struct pt_regs *regs)
95927475 116{
aaee8c3c 117 preempt_enable_no_resched();
95927475 118
8c84014f 119 if (!user_mode(regs))
95927475
AL
120 rcu_nmi_exit();
121}
122
bced35b6
AL
123/**
124 * ist_begin_non_atomic() - begin a non-atomic section in an IST exception
125 * @regs: regs passed to the IST exception handler
126 *
127 * IST exception handlers normally cannot schedule. As a special
128 * exception, if the exception interrupted userspace code (i.e.
f39b6f0e 129 * user_mode(regs) would return true) and the exception was not
bced35b6
AL
130 * a double fault, it can be safe to schedule. ist_begin_non_atomic()
131 * begins a non-atomic section within an ist_enter()/ist_exit() region.
132 * Callers are responsible for enabling interrupts themselves inside
8c84014f 133 * the non-atomic section, and callers must call ist_end_non_atomic()
bced35b6
AL
134 * before ist_exit().
135 */
136void ist_begin_non_atomic(struct pt_regs *regs)
137{
f39b6f0e 138 BUG_ON(!user_mode(regs));
bced35b6
AL
139
140 /*
141 * Sanity check: we need to be on the normal thread stack. This
142 * will catch asm bugs and any attempt to use ist_preempt_enable
143 * from double_fault.
144 */
3383642c 145 BUG_ON(!on_thread_stack());
bced35b6 146
aaee8c3c 147 preempt_enable_no_resched();
bced35b6
AL
148}
149
150/**
151 * ist_end_non_atomic() - begin a non-atomic section in an IST exception
152 *
153 * Ends a non-atomic section started with ist_begin_non_atomic().
154 */
155void ist_end_non_atomic(void)
156{
aaee8c3c 157 preempt_disable();
bced35b6
AL
158}
159
9a93848f
PZ
160int is_valid_bugaddr(unsigned long addr)
161{
162 unsigned short ud;
163
164 if (addr < TASK_SIZE_MAX)
165 return 0;
166
167 if (probe_kernel_address((unsigned short *)addr, ud))
168 return 0;
169
170 return ud == INSN_UD0 || ud == INSN_UD2;
171}
172
8a524f80 173int fixup_bug(struct pt_regs *regs, int trapnr)
9a93848f
PZ
174{
175 if (trapnr != X86_TRAP_UD)
176 return 0;
177
178 switch (report_bug(regs->ip, regs)) {
179 case BUG_TRAP_TYPE_NONE:
180 case BUG_TRAP_TYPE_BUG:
181 break;
182
183 case BUG_TRAP_TYPE_WARN:
f5b10c36 184 regs->ip += LEN_UD2;
9a93848f
PZ
185 return 1;
186 }
187
188 return 0;
189}
190
9326638c 191static nokprobe_inline int
c416ddf5
FW
192do_trap_no_signal(struct task_struct *tsk, int trapnr, char *str,
193 struct pt_regs *regs, long error_code)
1da177e4 194{
d74ef111 195 if (v8086_mode(regs)) {
3c1326f8 196 /*
c416ddf5 197 * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86.
3c1326f8
AH
198 * On nmi (interrupt 2), do_trap should not be called.
199 */
c416ddf5
FW
200 if (trapnr < X86_TRAP_UD) {
201 if (!handle_vm86_trap((struct kernel_vm86_regs *) regs,
202 error_code, trapnr))
203 return 0;
204 }
205 return -1;
1da177e4 206 }
d74ef111 207
55474c48 208 if (!user_mode(regs)) {
9a93848f
PZ
209 if (fixup_exception(regs, trapnr))
210 return 0;
211
9a93848f
PZ
212 tsk->thread.error_code = error_code;
213 tsk->thread.trap_nr = trapnr;
214 die(str, regs, error_code);
c416ddf5 215 }
1da177e4 216
c416ddf5
FW
217 return -1;
218}
1da177e4 219
1c326c4d
ON
220static siginfo_t *fill_trap_info(struct pt_regs *regs, int signr, int trapnr,
221 siginfo_t *info)
958d3d72
ON
222{
223 unsigned long siaddr;
224 int sicode;
225
226 switch (trapnr) {
1c326c4d
ON
227 default:
228 return SEND_SIG_PRIV;
229
958d3d72
ON
230 case X86_TRAP_DE:
231 sicode = FPE_INTDIV;
b02ef20a 232 siaddr = uprobe_get_trap_addr(regs);
958d3d72
ON
233 break;
234 case X86_TRAP_UD:
235 sicode = ILL_ILLOPN;
b02ef20a 236 siaddr = uprobe_get_trap_addr(regs);
958d3d72
ON
237 break;
238 case X86_TRAP_AC:
239 sicode = BUS_ADRALN;
240 siaddr = 0;
241 break;
242 }
243
244 info->si_signo = signr;
245 info->si_errno = 0;
246 info->si_code = sicode;
247 info->si_addr = (void __user *)siaddr;
1c326c4d 248 return info;
958d3d72
ON
249}
250
9326638c 251static void
c416ddf5
FW
252do_trap(int trapnr, int signr, char *str, struct pt_regs *regs,
253 long error_code, siginfo_t *info)
254{
255 struct task_struct *tsk = current;
256
257
258 if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code))
259 return;
b5964405 260 /*
51e7dc70 261 * We want error_code and trap_nr set for userspace faults and
b5964405
IM
262 * kernelspace faults which result in die(), but not
263 * kernelspace faults which are fixed up. die() gives the
264 * process no chance to handle the signal and notice the
265 * kernel fault information, so that won't result in polluting
266 * the information about previously queued, but not yet
267 * delivered, faults. See also do_general_protection below.
268 */
269 tsk->thread.error_code = error_code;
51e7dc70 270 tsk->thread.trap_nr = trapnr;
d1895183 271
081f75bb
AH
272 if (show_unhandled_signals && unhandled_signal(tsk, signr) &&
273 printk_ratelimit()) {
c767a54b
JP
274 pr_info("%s[%d] trap %s ip:%lx sp:%lx error:%lx",
275 tsk->comm, tsk->pid, str,
276 regs->ip, regs->sp, error_code);
1c99a687 277 print_vma_addr(KERN_CONT " in ", regs->ip);
c767a54b 278 pr_cont("\n");
081f75bb 279 }
081f75bb 280
38cad57b 281 force_sig_info(signr, info ?: SEND_SIG_PRIV, tsk);
1da177e4 282}
9326638c 283NOKPROBE_SYMBOL(do_trap);
1da177e4 284
dff0796e 285static void do_error_trap(struct pt_regs *regs, long error_code, char *str,
1c326c4d 286 unsigned long trapnr, int signr)
dff0796e 287{
1c326c4d 288 siginfo_t info;
dff0796e 289
5778077d 290 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
02fdcd5e 291
b8347c21
AS
292 /*
293 * WARN*()s end up here; fix them up before we call the
294 * notifier chain.
295 */
296 if (!user_mode(regs) && fixup_bug(regs, trapnr))
297 return;
298
dff0796e
ON
299 if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) !=
300 NOTIFY_STOP) {
d99e1bd1 301 cond_local_irq_enable(regs);
1c326c4d
ON
302 do_trap(trapnr, signr, str, regs, error_code,
303 fill_trap_info(regs, signr, trapnr, &info));
dff0796e 304 }
dff0796e
ON
305}
306
b5964405 307#define DO_ERROR(trapnr, signr, str, name) \
e407d620 308dotraplinkage void do_##name(struct pt_regs *regs, long error_code) \
b5964405 309{ \
1c326c4d 310 do_error_trap(regs, error_code, str, trapnr, signr); \
1da177e4
LT
311}
312
0eb14833
ON
313DO_ERROR(X86_TRAP_DE, SIGFPE, "divide error", divide_error)
314DO_ERROR(X86_TRAP_OF, SIGSEGV, "overflow", overflow)
0eb14833
ON
315DO_ERROR(X86_TRAP_UD, SIGILL, "invalid opcode", invalid_op)
316DO_ERROR(X86_TRAP_OLD_MF, SIGFPE, "coprocessor segment overrun",coprocessor_segment_overrun)
317DO_ERROR(X86_TRAP_TS, SIGSEGV, "invalid TSS", invalid_TSS)
318DO_ERROR(X86_TRAP_NP, SIGBUS, "segment not present", segment_not_present)
0eb14833 319DO_ERROR(X86_TRAP_SS, SIGBUS, "stack segment", stack_segment)
0eb14833 320DO_ERROR(X86_TRAP_AC, SIGBUS, "alignment check", alignment_check)
1da177e4 321
e37e43a4 322#ifdef CONFIG_VMAP_STACK
6271cfdf
AL
323__visible void __noreturn handle_stack_overflow(const char *message,
324 struct pt_regs *regs,
325 unsigned long fault_address)
e37e43a4
AL
326{
327 printk(KERN_EMERG "BUG: stack guard page was hit at %p (stack is %p..%p)\n",
328 (void *)fault_address, current->stack,
329 (char *)current->stack + THREAD_SIZE - 1);
330 die(message, regs, 0);
331
332 /* Be absolutely certain we don't return. */
333 panic(message);
334}
335#endif
336
081f75bb
AH
337#ifdef CONFIG_X86_64
338/* Runs on IST stack */
081f75bb
AH
339dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code)
340{
341 static const char str[] = "double fault";
342 struct task_struct *tsk = current;
e37e43a4
AL
343#ifdef CONFIG_VMAP_STACK
344 unsigned long cr2;
345#endif
081f75bb 346
af726f21
AL
347#ifdef CONFIG_X86_ESPFIX64
348 extern unsigned char native_irq_return_iret[];
349
350 /*
351 * If IRET takes a non-IST fault on the espfix64 stack, then we
6d9256f0
AL
352 * end up promoting it to a doublefault. In that case, take
353 * advantage of the fact that we're not using the normal (TSS.sp0)
354 * stack right now. We can write a fake #GP(0) frame at TSS.sp0
355 * and then modify our own IRET frame so that, when we return,
356 * we land directly at the #GP(0) vector with the stack already
357 * set up according to its expectations.
358 *
359 * The net result is that our #GP handler will think that we
360 * entered from usermode with the bad user context.
95927475
AL
361 *
362 * No need for ist_enter here because we don't use RCU.
af726f21 363 */
c739f930 364 if (((long)regs->sp >> P4D_SHIFT) == ESPFIX_PGD_ENTRY &&
af726f21
AL
365 regs->cs == __KERNEL_CS &&
366 regs->ip == (unsigned long)native_irq_return_iret)
367 {
c482feef 368 struct pt_regs *gpregs = (struct pt_regs *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1;
af726f21 369
6d9256f0
AL
370 /*
371 * regs->sp points to the failing IRET frame on the
372 * ESPFIX64 stack. Copy it to the entry stack. This fills
373 * in gpregs->ss through gpregs->ip.
374 *
375 */
376 memmove(&gpregs->ip, (void *)regs->sp, 5*8);
377 gpregs->orig_ax = 0; /* Missing (lost) #GP error code */
af726f21 378
6d9256f0
AL
379 /*
380 * Adjust our frame so that we return straight to the #GP
381 * vector with the expected RSP value. This is safe because
382 * we won't enable interupts or schedule before we invoke
383 * general_protection, so nothing will clobber the stack
384 * frame we just set up.
385 */
af726f21 386 regs->ip = (unsigned long)general_protection;
6d9256f0 387 regs->sp = (unsigned long)&gpregs->orig_ax;
95927475 388
af726f21
AL
389 return;
390 }
391#endif
392
8c84014f 393 ist_enter(regs);
c9408265 394 notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV);
081f75bb
AH
395
396 tsk->thread.error_code = error_code;
51e7dc70 397 tsk->thread.trap_nr = X86_TRAP_DF;
081f75bb 398
e37e43a4
AL
399#ifdef CONFIG_VMAP_STACK
400 /*
401 * If we overflow the stack into a guard page, the CPU will fail
402 * to deliver #PF and will send #DF instead. Similarly, if we
403 * take any non-IST exception while too close to the bottom of
404 * the stack, the processor will get a page fault while
405 * delivering the exception and will generate a double fault.
406 *
407 * According to the SDM (footnote in 6.15 under "Interrupt 14 -
408 * Page-Fault Exception (#PF):
409 *
410 * Processors update CR2 whenever a page fault is detected. If a
411 * second page fault occurs while an earlier page fault is being
6d9256f0 412 * delivered, the faulting linear address of the second fault will
e37e43a4
AL
413 * overwrite the contents of CR2 (replacing the previous
414 * address). These updates to CR2 occur even if the page fault
415 * results in a double fault or occurs during the delivery of a
416 * double fault.
417 *
418 * The logic below has a small possibility of incorrectly diagnosing
419 * some errors as stack overflows. For example, if the IDT or GDT
420 * gets corrupted such that #GP delivery fails due to a bad descriptor
421 * causing #GP and we hit this condition while CR2 coincidentally
422 * points to the stack guard page, we'll think we overflowed the
423 * stack. Given that we're going to panic one way or another
424 * if this happens, this isn't necessarily worth fixing.
425 *
426 * If necessary, we could improve the test by only diagnosing
427 * a stack overflow if the saved RSP points within 47 bytes of
428 * the bottom of the stack: if RSP == tsk_stack + 48 and we
429 * take an exception, the stack is already aligned and there
430 * will be enough room SS, RSP, RFLAGS, CS, RIP, and a
431 * possible error code, so a stack overflow would *not* double
432 * fault. With any less space left, exception delivery could
433 * fail, and, as a practical matter, we've overflowed the
434 * stack even if the actual trigger for the double fault was
435 * something else.
436 */
437 cr2 = read_cr2();
438 if ((unsigned long)task_stack_page(tsk) - 1 - cr2 < PAGE_SIZE)
439 handle_stack_overflow("kernel stack overflow (double-fault)", regs, cr2);
440#endif
441
4d067d8e
BP
442#ifdef CONFIG_DOUBLEFAULT
443 df_debug(regs, error_code);
444#endif
bd8b96df
IM
445 /*
446 * This is always a kernel trap and never fixable (and thus must
447 * never return).
448 */
081f75bb
AH
449 for (;;)
450 die(str, regs, error_code);
451}
452#endif
453
fe3d197f
DH
454dotraplinkage void do_bounds(struct pt_regs *regs, long error_code)
455{
1126cb45 456 const struct mpx_bndcsr *bndcsr;
fe3d197f
DH
457 siginfo_t *info;
458
5778077d 459 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
fe3d197f
DH
460 if (notify_die(DIE_TRAP, "bounds", regs, error_code,
461 X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP)
8c84014f 462 return;
d99e1bd1 463 cond_local_irq_enable(regs);
fe3d197f 464
f39b6f0e 465 if (!user_mode(regs))
fe3d197f
DH
466 die("bounds", regs, error_code);
467
468 if (!cpu_feature_enabled(X86_FEATURE_MPX)) {
469 /* The exception is not from Intel MPX */
470 goto exit_trap;
471 }
472
473 /*
474 * We need to look at BNDSTATUS to resolve this exception.
a84eeaa9
DH
475 * A NULL here might mean that it is in its 'init state',
476 * which is all zeros which indicates MPX was not
477 * responsible for the exception.
fe3d197f 478 */
d91cab78 479 bndcsr = get_xsave_field_ptr(XFEATURE_MASK_BNDCSR);
fe3d197f
DH
480 if (!bndcsr)
481 goto exit_trap;
482
e7126cf5 483 trace_bounds_exception_mpx(bndcsr);
fe3d197f
DH
484 /*
485 * The error code field of the BNDSTATUS register communicates status
486 * information of a bound range exception #BR or operation involving
487 * bound directory.
488 */
489 switch (bndcsr->bndstatus & MPX_BNDSTA_ERROR_CODE) {
490 case 2: /* Bound directory has invalid entry. */
46a6e0cf 491 if (mpx_handle_bd_fault())
fe3d197f
DH
492 goto exit_trap;
493 break; /* Success, it was handled */
494 case 1: /* Bound violation. */
46a6e0cf 495 info = mpx_generate_siginfo(regs);
e10abb2f 496 if (IS_ERR(info)) {
fe3d197f
DH
497 /*
498 * We failed to decode the MPX instruction. Act as if
499 * the exception was not caused by MPX.
500 */
501 goto exit_trap;
502 }
503 /*
504 * Success, we decoded the instruction and retrieved
505 * an 'info' containing the address being accessed
506 * which caused the exception. This information
507 * allows and application to possibly handle the
508 * #BR exception itself.
509 */
510 do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, info);
511 kfree(info);
512 break;
513 case 0: /* No exception caused by Intel MPX operations. */
514 goto exit_trap;
515 default:
516 die("bounds", regs, error_code);
517 }
518
fe3d197f 519 return;
8c84014f 520
fe3d197f
DH
521exit_trap:
522 /*
523 * This path out is for all the cases where we could not
524 * handle the exception in some way (like allocating a
525 * table or telling userspace about it. We will also end
526 * up here if the kernel has MPX turned off at compile
527 * time..
528 */
529 do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, NULL);
fe3d197f
DH
530}
531
9326638c 532dotraplinkage void
13485ab5 533do_general_protection(struct pt_regs *regs, long error_code)
1da177e4 534{
13485ab5 535 struct task_struct *tsk;
b5964405 536
5778077d 537 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
d99e1bd1 538 cond_local_irq_enable(regs);
c6df0d71 539
6fc9dc81
RN
540 if (static_cpu_has(X86_FEATURE_UMIP)) {
541 if (user_mode(regs) && fixup_umip_exception(regs))
542 return;
543 }
544
d74ef111 545 if (v8086_mode(regs)) {
ef3f6288
FW
546 local_irq_enable();
547 handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code);
8c84014f 548 return;
ef3f6288 549 }
1da177e4 550
13485ab5 551 tsk = current;
55474c48 552 if (!user_mode(regs)) {
548acf19 553 if (fixup_exception(regs, X86_TRAP_GP))
8c84014f 554 return;
ef3f6288
FW
555
556 tsk->thread.error_code = error_code;
557 tsk->thread.trap_nr = X86_TRAP_GP;
6ba3c97a
FW
558 if (notify_die(DIE_GPF, "general protection fault", regs, error_code,
559 X86_TRAP_GP, SIGSEGV) != NOTIFY_STOP)
ef3f6288 560 die("general protection fault", regs, error_code);
8c84014f 561 return;
ef3f6288 562 }
1da177e4 563
13485ab5 564 tsk->thread.error_code = error_code;
51e7dc70 565 tsk->thread.trap_nr = X86_TRAP_GP;
b5964405 566
13485ab5
AH
567 if (show_unhandled_signals && unhandled_signal(tsk, SIGSEGV) &&
568 printk_ratelimit()) {
c767a54b 569 pr_info("%s[%d] general protection ip:%lx sp:%lx error:%lx",
13485ab5
AH
570 tsk->comm, task_pid_nr(tsk),
571 regs->ip, regs->sp, error_code);
1c99a687 572 print_vma_addr(KERN_CONT " in ", regs->ip);
c767a54b 573 pr_cont("\n");
03252919 574 }
abd4f750 575
38cad57b 576 force_sig_info(SIGSEGV, SEND_SIG_PRIV, tsk);
1da177e4 577}
9326638c 578NOKPROBE_SYMBOL(do_general_protection);
1da177e4 579
9326638c 580dotraplinkage void notrace do_int3(struct pt_regs *regs, long error_code)
1da177e4 581{
08d636b6 582#ifdef CONFIG_DYNAMIC_FTRACE
a192cd04
SR
583 /*
584 * ftrace must be first, everything else may cause a recursive crash.
585 * See note by declaration of modifying_ftrace_code in ftrace.c
586 */
587 if (unlikely(atomic_read(&modifying_ftrace_code)) &&
588 ftrace_int3_handler(regs))
08d636b6
SR
589 return;
590#endif
17f41571
JK
591 if (poke_int3_handler(regs))
592 return;
593
9cf982d9
AL
594 /*
595 * Use ist_enter despite the fact that we don't use an IST stack.
596 * We can be called from a kprobe in non-CONTEXT_KERNEL kernel
597 * mode or even during context tracking state changes.
598 *
599 * This means that we can't schedule. That's okay.
600 */
8c84014f 601 ist_enter(regs);
5778077d 602 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
f503b5ae 603#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
c9408265
KC
604 if (kgdb_ll_trap(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP,
605 SIGTRAP) == NOTIFY_STOP)
6ba3c97a 606 goto exit;
f503b5ae 607#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
cc3a1bf5 608
6f6343f5
MH
609#ifdef CONFIG_KPROBES
610 if (kprobe_int3_handler(regs))
4cdf77a8 611 goto exit;
6f6343f5
MH
612#endif
613
c9408265
KC
614 if (notify_die(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP,
615 SIGTRAP) == NOTIFY_STOP)
6ba3c97a 616 goto exit;
b5964405 617
d99e1bd1 618 cond_local_irq_enable(regs);
c9408265 619 do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, error_code, NULL);
d99e1bd1 620 cond_local_irq_disable(regs);
9cf982d9 621
6ba3c97a 622exit:
8c84014f 623 ist_exit(regs);
1da177e4 624}
9326638c 625NOKPROBE_SYMBOL(do_int3);
1da177e4 626
081f75bb 627#ifdef CONFIG_X86_64
bd8b96df 628/*
7f2590a1
AL
629 * Help handler running on a per-cpu (IST or entry trampoline) stack
630 * to switch to the normal thread stack if the interrupted code was in
631 * user mode. The actual stack switch is done in entry_64.S
bd8b96df 632 */
7ddc6a21 633asmlinkage __visible notrace struct pt_regs *sync_regs(struct pt_regs *eregs)
081f75bb 634{
7f2590a1
AL
635 struct pt_regs *regs = (struct pt_regs *)this_cpu_read(cpu_current_top_of_stack) - 1;
636 if (regs != eregs)
637 *regs = *eregs;
081f75bb
AH
638 return regs;
639}
9326638c 640NOKPROBE_SYMBOL(sync_regs);
b645af2d
AL
641
642struct bad_iret_stack {
643 void *error_entry_ret;
644 struct pt_regs regs;
645};
646
7ddc6a21 647asmlinkage __visible notrace
b645af2d
AL
648struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s)
649{
650 /*
651 * This is called from entry_64.S early in handling a fault
652 * caused by a bad iret to user mode. To handle the fault
7f2590a1
AL
653 * correctly, we want to move our stack frame to where it would
654 * be had we entered directly on the entry stack (rather than
655 * just below the IRET frame) and we want to pretend that the
656 * exception came from the IRET target.
b645af2d
AL
657 */
658 struct bad_iret_stack *new_stack =
c482feef 659 (struct bad_iret_stack *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1;
b645af2d
AL
660
661 /* Copy the IRET target to the new stack. */
662 memmove(&new_stack->regs.ip, (void *)s->regs.sp, 5*8);
663
664 /* Copy the remainder of the stack from the current stack. */
665 memmove(new_stack, s, offsetof(struct bad_iret_stack, regs.ip));
666
f39b6f0e 667 BUG_ON(!user_mode(&new_stack->regs));
b645af2d
AL
668 return new_stack;
669}
7ddc6a21 670NOKPROBE_SYMBOL(fixup_bad_iret);
081f75bb
AH
671#endif
672
f2b37575
AL
673static bool is_sysenter_singlestep(struct pt_regs *regs)
674{
675 /*
676 * We don't try for precision here. If we're anywhere in the region of
677 * code that can be single-stepped in the SYSENTER entry path, then
678 * assume that this is a useless single-step trap due to SYSENTER
679 * being invoked with TF set. (We don't know in advance exactly
680 * which instructions will be hit because BTF could plausibly
681 * be set.)
682 */
683#ifdef CONFIG_X86_32
684 return (regs->ip - (unsigned long)__begin_SYSENTER_singlestep_region) <
685 (unsigned long)__end_SYSENTER_singlestep_region -
686 (unsigned long)__begin_SYSENTER_singlestep_region;
687#elif defined(CONFIG_IA32_EMULATION)
688 return (regs->ip - (unsigned long)entry_SYSENTER_compat) <
689 (unsigned long)__end_entry_SYSENTER_compat -
690 (unsigned long)entry_SYSENTER_compat;
691#else
692 return false;
693#endif
694}
695
1da177e4
LT
696/*
697 * Our handling of the processor debug registers is non-trivial.
698 * We do not clear them on entry and exit from the kernel. Therefore
699 * it is possible to get a watchpoint trap here from inside the kernel.
700 * However, the code in ./ptrace.c has ensured that the user can
701 * only set watchpoints on userspace addresses. Therefore the in-kernel
702 * watchpoint trap can only occur in code which is reading/writing
703 * from user space. Such code must not hold kernel locks (since it
704 * can equally take a page fault), therefore it is safe to call
705 * force_sig_info even though that claims and releases locks.
b5964405 706 *
1da177e4
LT
707 * Code in ./signal.c ensures that the debug control register
708 * is restored before we deliver any signal, and therefore that
709 * user code runs with the correct debug control register even though
710 * we clear it here.
711 *
712 * Being careful here means that we don't have to be as careful in a
713 * lot of more complicated places (task switching can be a bit lazy
714 * about restoring all the debug state, and ptrace doesn't have to
715 * find every occurrence of the TF bit that could be saved away even
716 * by user code)
c1d518c8
AH
717 *
718 * May run on IST stack.
1da177e4 719 */
9326638c 720dotraplinkage void do_debug(struct pt_regs *regs, long error_code)
1da177e4 721{
1da177e4 722 struct task_struct *tsk = current;
a1e80faf 723 int user_icebp = 0;
08d68323 724 unsigned long dr6;
da654b74 725 int si_code;
1da177e4 726
8c84014f 727 ist_enter(regs);
4cdf77a8 728
08d68323 729 get_debugreg(dr6, 6);
8bb56436
AL
730 /*
731 * The Intel SDM says:
732 *
733 * Certain debug exceptions may clear bits 0-3. The remaining
734 * contents of the DR6 register are never cleared by the
735 * processor. To avoid confusion in identifying debug
736 * exceptions, debug handlers should clear the register before
737 * returning to the interrupted task.
738 *
739 * Keep it simple: clear DR6 immediately.
740 */
741 set_debugreg(0, 6);
1da177e4 742
40f9249a
P
743 /* Filter out all the reserved bits which are preset to 1 */
744 dr6 &= ~DR6_RESERVED;
745
81edd9f6
AL
746 /*
747 * The SDM says "The processor clears the BTF flag when it
748 * generates a debug exception." Clear TIF_BLOCKSTEP to keep
749 * TIF_BLOCKSTEP in sync with the hardware BTF flag.
750 */
751 clear_tsk_thread_flag(tsk, TIF_BLOCKSTEP);
752
f2b37575
AL
753 if (unlikely(!user_mode(regs) && (dr6 & DR_STEP) &&
754 is_sysenter_singlestep(regs))) {
755 dr6 &= ~DR_STEP;
756 if (!dr6)
757 goto exit;
758 /*
759 * else we might have gotten a single-step trap and hit a
760 * watchpoint at the same time, in which case we should fall
761 * through and handle the watchpoint.
762 */
763 }
764
a1e80faf
FW
765 /*
766 * If dr6 has no reason to give us about the origin of this trap,
767 * then it's very likely the result of an icebp/int01 trap.
768 * User wants a sigtrap for that.
769 */
f39b6f0e 770 if (!dr6 && user_mode(regs))
a1e80faf
FW
771 user_icebp = 1;
772
08d68323
P
773 /* Store the virtualized DR6 value */
774 tsk->thread.debugreg6 = dr6;
775
6f6343f5
MH
776#ifdef CONFIG_KPROBES
777 if (kprobe_debug_handler(regs))
778 goto exit;
779#endif
780
5a802e15 781 if (notify_die(DIE_DEBUG, "debug", regs, (long)&dr6, error_code,
62edab90 782 SIGTRAP) == NOTIFY_STOP)
6ba3c97a 783 goto exit;
3d2a71a5 784
42181186
SR
785 /*
786 * Let others (NMI) know that the debug stack is in use
787 * as we may switch to the interrupt stack.
788 */
789 debug_stack_usage_inc();
790
1da177e4 791 /* It's safe to allow irq's after DR6 has been saved */
d99e1bd1 792 cond_local_irq_enable(regs);
1da177e4 793
d74ef111 794 if (v8086_mode(regs)) {
c9408265
KC
795 handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code,
796 X86_TRAP_DB);
d99e1bd1 797 cond_local_irq_disable(regs);
42181186 798 debug_stack_usage_dec();
6ba3c97a 799 goto exit;
1da177e4
LT
800 }
801
f2b37575
AL
802 if (WARN_ON_ONCE((dr6 & DR_STEP) && !user_mode(regs))) {
803 /*
804 * Historical junk that used to handle SYSENTER single-stepping.
805 * This should be unreachable now. If we survive for a while
806 * without anyone hitting this warning, we'll turn this into
807 * an oops.
808 */
08d68323
P
809 tsk->thread.debugreg6 &= ~DR_STEP;
810 set_tsk_thread_flag(tsk, TIF_SINGLESTEP);
811 regs->flags &= ~X86_EFLAGS_TF;
1da177e4 812 }
08d68323 813 si_code = get_si_code(tsk->thread.debugreg6);
a1e80faf 814 if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS) || user_icebp)
08d68323 815 send_sigtrap(tsk, regs, error_code, si_code);
d99e1bd1 816 cond_local_irq_disable(regs);
42181186 817 debug_stack_usage_dec();
1da177e4 818
6ba3c97a 819exit:
8c84014f 820 ist_exit(regs);
1da177e4 821}
9326638c 822NOKPROBE_SYMBOL(do_debug);
1da177e4
LT
823
824/*
825 * Note that we play around with the 'TS' bit in an attempt to get
826 * the correct behaviour even in the presence of the asynchronous
827 * IRQ13 behaviour
828 */
5e1b05be 829static void math_error(struct pt_regs *regs, int error_code, int trapnr)
1da177e4 830{
e2e75c91 831 struct task_struct *task = current;
e1cebad4 832 struct fpu *fpu = &task->thread.fpu;
1da177e4 833 siginfo_t info;
c9408265
KC
834 char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" :
835 "simd exception";
e2e75c91 836
d99e1bd1 837 cond_local_irq_enable(regs);
e2e75c91 838
e1cebad4 839 if (!user_mode(regs)) {
69507fa7
SL
840 if (fixup_exception(regs, trapnr))
841 return;
842
843 task->thread.error_code = error_code;
844 task->thread.trap_nr = trapnr;
845
846 if (notify_die(DIE_TRAP, str, regs, error_code,
847 trapnr, SIGFPE) != NOTIFY_STOP)
e2e75c91 848 die(str, regs, error_code);
e2e75c91
BG
849 return;
850 }
1da177e4
LT
851
852 /*
853 * Save the info for the exception handler and clear the error.
854 */
e1cebad4
IM
855 fpu__save(fpu);
856
857 task->thread.trap_nr = trapnr;
9b6dba9e 858 task->thread.error_code = error_code;
e1cebad4
IM
859 info.si_signo = SIGFPE;
860 info.si_errno = 0;
861 info.si_addr = (void __user *)uprobe_get_trap_addr(regs);
adf77bac 862
e1cebad4 863 info.si_code = fpu__exception_code(fpu, trapnr);
adf77bac 864
e1cebad4
IM
865 /* Retry when we get spurious exceptions: */
866 if (!info.si_code)
c9408265 867 return;
e1cebad4 868
1da177e4
LT
869 force_sig_info(SIGFPE, &info, task);
870}
871
e407d620 872dotraplinkage void do_coprocessor_error(struct pt_regs *regs, long error_code)
1da177e4 873{
5778077d 874 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
c9408265 875 math_error(regs, error_code, X86_TRAP_MF);
1da177e4
LT
876}
877
e407d620
AH
878dotraplinkage void
879do_simd_coprocessor_error(struct pt_regs *regs, long error_code)
1da177e4 880{
5778077d 881 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
c9408265 882 math_error(regs, error_code, X86_TRAP_XF);
1da177e4
LT
883}
884
e407d620
AH
885dotraplinkage void
886do_spurious_interrupt_bug(struct pt_regs *regs, long error_code)
1da177e4 887{
d99e1bd1 888 cond_local_irq_enable(regs);
081f75bb
AH
889}
890
9326638c 891dotraplinkage void
aa78bcfa 892do_device_not_available(struct pt_regs *regs, long error_code)
7643e9b9 893{
bef8b6da
AL
894 unsigned long cr0;
895
5778077d 896 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
304bceda 897
a334fe43 898#ifdef CONFIG_MATH_EMULATION
c6ab109f 899 if (!boot_cpu_has(X86_FEATURE_FPU) && (read_cr0() & X86_CR0_EM)) {
d315760f
TH
900 struct math_emu_info info = { };
901
d99e1bd1 902 cond_local_irq_enable(regs);
d315760f 903
aa78bcfa 904 info.regs = regs;
d315760f 905 math_emulate(&info);
a334fe43 906 return;
7643e9b9 907 }
a334fe43 908#endif
bef8b6da
AL
909
910 /* This should not happen. */
911 cr0 = read_cr0();
912 if (WARN(cr0 & X86_CR0_TS, "CR0.TS was set")) {
913 /* Try to fix it up and carry on. */
914 write_cr0(cr0 & ~X86_CR0_TS);
915 } else {
916 /*
917 * Something terrible happened, and we're better off trying
918 * to kill the task than getting stuck in a never-ending
919 * loop of #NM faults.
920 */
921 die("unexpected #NM exception", regs, error_code);
922 }
7643e9b9 923}
9326638c 924NOKPROBE_SYMBOL(do_device_not_available);
7643e9b9 925
081f75bb 926#ifdef CONFIG_X86_32
e407d620 927dotraplinkage void do_iret_error(struct pt_regs *regs, long error_code)
f8e0870f
AH
928{
929 siginfo_t info;
6ba3c97a 930
5778077d 931 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
f8e0870f
AH
932 local_irq_enable();
933
934 info.si_signo = SIGILL;
935 info.si_errno = 0;
936 info.si_code = ILL_BADSTK;
fc6fcdfb 937 info.si_addr = NULL;
c9408265 938 if (notify_die(DIE_TRAP, "iret exception", regs, error_code,
6ba3c97a
FW
939 X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) {
940 do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, error_code,
941 &info);
942 }
f8e0870f 943}
081f75bb 944#endif
f8e0870f 945
1da177e4
LT
946void __init trap_init(void)
947{
40e7f949
AL
948 /* Init cpu_entry_area before IST entries are set up */
949 setup_cpu_entry_areas();
950
b70543a0 951 idt_setup_traps();
bb3f0b59 952
4eefbe79
KC
953 /*
954 * Set the IDT descriptor to a fixed read-only location, so that the
955 * "sidt" instruction will not leak the location of the kernel, and
956 * to defend the IDT against arbitrary memory write vulnerabilities.
957 * It will be reloaded in cpu_init() */
92a0f81d
TG
958 cea_set_pte(CPU_ENTRY_AREA_RO_IDT_VADDR, __pa_symbol(idt_table),
959 PAGE_KERNEL_RO);
960 idt_descr.address = CPU_ENTRY_AREA_RO_IDT;
4eefbe79 961
1da177e4 962 /*
b5964405 963 * Should be a barrier for any external CPU state:
1da177e4
LT
964 */
965 cpu_init();
966
90f6225f 967 idt_setup_ist_traps();
b4d83270 968
428cf902 969 x86_init.irqs.trap_init();
228bdaa9 970
0a30908b 971 idt_setup_debugidt_traps();
1da177e4 972}