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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 1991, 1992 Linus Torvalds |
a8c1be9d | 3 | * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs |
1da177e4 LT |
4 | * |
5 | * Pentium III FXSR, SSE support | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | */ | |
8 | ||
9 | /* | |
c1d518c8 | 10 | * Handle hardware traps and faults. |
1da177e4 | 11 | */ |
c767a54b JP |
12 | |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
14 | ||
56dd9470 | 15 | #include <linux/context_tracking.h> |
b5964405 IM |
16 | #include <linux/interrupt.h> |
17 | #include <linux/kallsyms.h> | |
18 | #include <linux/spinlock.h> | |
b5964405 IM |
19 | #include <linux/kprobes.h> |
20 | #include <linux/uaccess.h> | |
b5964405 | 21 | #include <linux/kdebug.h> |
f503b5ae | 22 | #include <linux/kgdb.h> |
1da177e4 | 23 | #include <linux/kernel.h> |
b5964405 IM |
24 | #include <linux/module.h> |
25 | #include <linux/ptrace.h> | |
b02ef20a | 26 | #include <linux/uprobes.h> |
1da177e4 | 27 | #include <linux/string.h> |
b5964405 | 28 | #include <linux/delay.h> |
1da177e4 | 29 | #include <linux/errno.h> |
b5964405 IM |
30 | #include <linux/kexec.h> |
31 | #include <linux/sched.h> | |
1da177e4 | 32 | #include <linux/timer.h> |
1da177e4 | 33 | #include <linux/init.h> |
91768d6c | 34 | #include <linux/bug.h> |
b5964405 IM |
35 | #include <linux/nmi.h> |
36 | #include <linux/mm.h> | |
c1d518c8 AH |
37 | #include <linux/smp.h> |
38 | #include <linux/io.h> | |
1da177e4 LT |
39 | |
40 | #ifdef CONFIG_EISA | |
41 | #include <linux/ioport.h> | |
42 | #include <linux/eisa.h> | |
43 | #endif | |
44 | ||
c0d12172 DJ |
45 | #if defined(CONFIG_EDAC) |
46 | #include <linux/edac.h> | |
47 | #endif | |
48 | ||
f8561296 | 49 | #include <asm/kmemcheck.h> |
b5964405 | 50 | #include <asm/stacktrace.h> |
1da177e4 | 51 | #include <asm/processor.h> |
1da177e4 | 52 | #include <asm/debugreg.h> |
60063497 | 53 | #include <linux/atomic.h> |
08d636b6 | 54 | #include <asm/ftrace.h> |
c1d518c8 | 55 | #include <asm/traps.h> |
1da177e4 LT |
56 | #include <asm/desc.h> |
57 | #include <asm/i387.h> | |
1361b83a | 58 | #include <asm/fpu-internal.h> |
9e55e44e | 59 | #include <asm/mce.h> |
4eefbe79 | 60 | #include <asm/fixmap.h> |
1164dd00 | 61 | #include <asm/mach_traps.h> |
17f41571 | 62 | #include <asm/alternative.h> |
fe3d197f | 63 | #include <asm/mpx.h> |
c1d518c8 | 64 | |
081f75bb | 65 | #ifdef CONFIG_X86_64 |
428cf902 | 66 | #include <asm/x86_init.h> |
081f75bb AH |
67 | #include <asm/pgalloc.h> |
68 | #include <asm/proto.h> | |
4df05f36 KC |
69 | |
70 | /* No need to be aligned, but done to keep all IDTs defined the same way. */ | |
71 | gate_desc debug_idt_table[NR_VECTORS] __page_aligned_bss; | |
081f75bb | 72 | #else |
c1d518c8 | 73 | #include <asm/processor-flags.h> |
8e6dafd6 | 74 | #include <asm/setup.h> |
1da177e4 | 75 | |
1da177e4 | 76 | asmlinkage int system_call(void); |
081f75bb | 77 | #endif |
1da177e4 | 78 | |
4df05f36 KC |
79 | /* Must be page-aligned because the real IDT is used in a fixmap. */ |
80 | gate_desc idt_table[NR_VECTORS] __page_aligned_bss; | |
81 | ||
b77b881f YL |
82 | DECLARE_BITMAP(used_vectors, NR_VECTORS); |
83 | EXPORT_SYMBOL_GPL(used_vectors); | |
84 | ||
762db434 AH |
85 | static inline void conditional_sti(struct pt_regs *regs) |
86 | { | |
87 | if (regs->flags & X86_EFLAGS_IF) | |
88 | local_irq_enable(); | |
89 | } | |
90 | ||
3d2a71a5 AH |
91 | static inline void preempt_conditional_sti(struct pt_regs *regs) |
92 | { | |
bdb43806 | 93 | preempt_count_inc(); |
3d2a71a5 AH |
94 | if (regs->flags & X86_EFLAGS_IF) |
95 | local_irq_enable(); | |
96 | } | |
97 | ||
be716615 TG |
98 | static inline void conditional_cli(struct pt_regs *regs) |
99 | { | |
100 | if (regs->flags & X86_EFLAGS_IF) | |
101 | local_irq_disable(); | |
102 | } | |
103 | ||
3d2a71a5 AH |
104 | static inline void preempt_conditional_cli(struct pt_regs *regs) |
105 | { | |
106 | if (regs->flags & X86_EFLAGS_IF) | |
107 | local_irq_disable(); | |
bdb43806 | 108 | preempt_count_dec(); |
3d2a71a5 AH |
109 | } |
110 | ||
95927475 AL |
111 | enum ctx_state ist_enter(struct pt_regs *regs) |
112 | { | |
b926e6f6 | 113 | enum ctx_state prev_state; |
95927475 | 114 | |
f39b6f0e | 115 | if (user_mode(regs)) { |
95927475 | 116 | /* Other than that, we're just an exception. */ |
b926e6f6 | 117 | prev_state = exception_enter(); |
95927475 AL |
118 | } else { |
119 | /* | |
120 | * We might have interrupted pretty much anything. In | |
121 | * fact, if we're a machine check, we can even interrupt | |
122 | * NMI processing. We don't want in_nmi() to return true, | |
123 | * but we need to notify RCU. | |
124 | */ | |
125 | rcu_nmi_enter(); | |
b926e6f6 | 126 | prev_state = IN_KERNEL; /* the value is irrelevant. */ |
95927475 | 127 | } |
b926e6f6 AL |
128 | |
129 | /* | |
130 | * We are atomic because we're on the IST stack (or we're on x86_32, | |
131 | * in which case we still shouldn't schedule). | |
132 | * | |
133 | * This must be after exception_enter(), because exception_enter() | |
134 | * won't do anything if in_interrupt() returns true. | |
135 | */ | |
136 | preempt_count_add(HARDIRQ_OFFSET); | |
137 | ||
138 | /* This code is a bit fragile. Test it. */ | |
139 | rcu_lockdep_assert(rcu_is_watching(), "ist_enter didn't work"); | |
140 | ||
141 | return prev_state; | |
95927475 AL |
142 | } |
143 | ||
144 | void ist_exit(struct pt_regs *regs, enum ctx_state prev_state) | |
145 | { | |
b926e6f6 | 146 | /* Must be before exception_exit. */ |
95927475 AL |
147 | preempt_count_sub(HARDIRQ_OFFSET); |
148 | ||
f39b6f0e | 149 | if (user_mode(regs)) |
95927475 AL |
150 | return exception_exit(prev_state); |
151 | else | |
152 | rcu_nmi_exit(); | |
153 | } | |
154 | ||
bced35b6 AL |
155 | /** |
156 | * ist_begin_non_atomic() - begin a non-atomic section in an IST exception | |
157 | * @regs: regs passed to the IST exception handler | |
158 | * | |
159 | * IST exception handlers normally cannot schedule. As a special | |
160 | * exception, if the exception interrupted userspace code (i.e. | |
f39b6f0e | 161 | * user_mode(regs) would return true) and the exception was not |
bced35b6 AL |
162 | * a double fault, it can be safe to schedule. ist_begin_non_atomic() |
163 | * begins a non-atomic section within an ist_enter()/ist_exit() region. | |
164 | * Callers are responsible for enabling interrupts themselves inside | |
165 | * the non-atomic section, and callers must call is_end_non_atomic() | |
166 | * before ist_exit(). | |
167 | */ | |
168 | void ist_begin_non_atomic(struct pt_regs *regs) | |
169 | { | |
f39b6f0e | 170 | BUG_ON(!user_mode(regs)); |
bced35b6 AL |
171 | |
172 | /* | |
173 | * Sanity check: we need to be on the normal thread stack. This | |
174 | * will catch asm bugs and any attempt to use ist_preempt_enable | |
175 | * from double_fault. | |
176 | */ | |
a7fcf28d AL |
177 | BUG_ON((unsigned long)(current_top_of_stack() - |
178 | current_stack_pointer()) >= THREAD_SIZE); | |
bced35b6 AL |
179 | |
180 | preempt_count_sub(HARDIRQ_OFFSET); | |
181 | } | |
182 | ||
183 | /** | |
184 | * ist_end_non_atomic() - begin a non-atomic section in an IST exception | |
185 | * | |
186 | * Ends a non-atomic section started with ist_begin_non_atomic(). | |
187 | */ | |
188 | void ist_end_non_atomic(void) | |
189 | { | |
190 | preempt_count_add(HARDIRQ_OFFSET); | |
191 | } | |
192 | ||
9326638c | 193 | static nokprobe_inline int |
c416ddf5 FW |
194 | do_trap_no_signal(struct task_struct *tsk, int trapnr, char *str, |
195 | struct pt_regs *regs, long error_code) | |
1da177e4 | 196 | { |
081f75bb | 197 | #ifdef CONFIG_X86_32 |
6b6891f9 | 198 | if (regs->flags & X86_VM_MASK) { |
3c1326f8 | 199 | /* |
c416ddf5 | 200 | * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86. |
3c1326f8 AH |
201 | * On nmi (interrupt 2), do_trap should not be called. |
202 | */ | |
c416ddf5 FW |
203 | if (trapnr < X86_TRAP_UD) { |
204 | if (!handle_vm86_trap((struct kernel_vm86_regs *) regs, | |
205 | error_code, trapnr)) | |
206 | return 0; | |
207 | } | |
208 | return -1; | |
1da177e4 | 209 | } |
081f75bb | 210 | #endif |
ae60f071 | 211 | if (!user_mode_ignore_vm86(regs)) { |
c416ddf5 FW |
212 | if (!fixup_exception(regs)) { |
213 | tsk->thread.error_code = error_code; | |
214 | tsk->thread.trap_nr = trapnr; | |
215 | die(str, regs, error_code); | |
216 | } | |
217 | return 0; | |
218 | } | |
1da177e4 | 219 | |
c416ddf5 FW |
220 | return -1; |
221 | } | |
1da177e4 | 222 | |
1c326c4d ON |
223 | static siginfo_t *fill_trap_info(struct pt_regs *regs, int signr, int trapnr, |
224 | siginfo_t *info) | |
958d3d72 ON |
225 | { |
226 | unsigned long siaddr; | |
227 | int sicode; | |
228 | ||
229 | switch (trapnr) { | |
1c326c4d ON |
230 | default: |
231 | return SEND_SIG_PRIV; | |
232 | ||
958d3d72 ON |
233 | case X86_TRAP_DE: |
234 | sicode = FPE_INTDIV; | |
b02ef20a | 235 | siaddr = uprobe_get_trap_addr(regs); |
958d3d72 ON |
236 | break; |
237 | case X86_TRAP_UD: | |
238 | sicode = ILL_ILLOPN; | |
b02ef20a | 239 | siaddr = uprobe_get_trap_addr(regs); |
958d3d72 ON |
240 | break; |
241 | case X86_TRAP_AC: | |
242 | sicode = BUS_ADRALN; | |
243 | siaddr = 0; | |
244 | break; | |
245 | } | |
246 | ||
247 | info->si_signo = signr; | |
248 | info->si_errno = 0; | |
249 | info->si_code = sicode; | |
250 | info->si_addr = (void __user *)siaddr; | |
1c326c4d | 251 | return info; |
958d3d72 ON |
252 | } |
253 | ||
9326638c | 254 | static void |
c416ddf5 FW |
255 | do_trap(int trapnr, int signr, char *str, struct pt_regs *regs, |
256 | long error_code, siginfo_t *info) | |
257 | { | |
258 | struct task_struct *tsk = current; | |
259 | ||
260 | ||
261 | if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code)) | |
262 | return; | |
b5964405 | 263 | /* |
51e7dc70 | 264 | * We want error_code and trap_nr set for userspace faults and |
b5964405 IM |
265 | * kernelspace faults which result in die(), but not |
266 | * kernelspace faults which are fixed up. die() gives the | |
267 | * process no chance to handle the signal and notice the | |
268 | * kernel fault information, so that won't result in polluting | |
269 | * the information about previously queued, but not yet | |
270 | * delivered, faults. See also do_general_protection below. | |
271 | */ | |
272 | tsk->thread.error_code = error_code; | |
51e7dc70 | 273 | tsk->thread.trap_nr = trapnr; |
d1895183 | 274 | |
081f75bb AH |
275 | #ifdef CONFIG_X86_64 |
276 | if (show_unhandled_signals && unhandled_signal(tsk, signr) && | |
277 | printk_ratelimit()) { | |
c767a54b JP |
278 | pr_info("%s[%d] trap %s ip:%lx sp:%lx error:%lx", |
279 | tsk->comm, tsk->pid, str, | |
280 | regs->ip, regs->sp, error_code); | |
081f75bb | 281 | print_vma_addr(" in ", regs->ip); |
c767a54b | 282 | pr_cont("\n"); |
081f75bb AH |
283 | } |
284 | #endif | |
285 | ||
38cad57b | 286 | force_sig_info(signr, info ?: SEND_SIG_PRIV, tsk); |
1da177e4 | 287 | } |
9326638c | 288 | NOKPROBE_SYMBOL(do_trap); |
1da177e4 | 289 | |
dff0796e | 290 | static void do_error_trap(struct pt_regs *regs, long error_code, char *str, |
1c326c4d | 291 | unsigned long trapnr, int signr) |
dff0796e ON |
292 | { |
293 | enum ctx_state prev_state = exception_enter(); | |
1c326c4d | 294 | siginfo_t info; |
dff0796e ON |
295 | |
296 | if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) != | |
297 | NOTIFY_STOP) { | |
298 | conditional_sti(regs); | |
1c326c4d ON |
299 | do_trap(trapnr, signr, str, regs, error_code, |
300 | fill_trap_info(regs, signr, trapnr, &info)); | |
dff0796e ON |
301 | } |
302 | ||
303 | exception_exit(prev_state); | |
304 | } | |
305 | ||
b5964405 | 306 | #define DO_ERROR(trapnr, signr, str, name) \ |
e407d620 | 307 | dotraplinkage void do_##name(struct pt_regs *regs, long error_code) \ |
b5964405 | 308 | { \ |
1c326c4d | 309 | do_error_trap(regs, error_code, str, trapnr, signr); \ |
1da177e4 LT |
310 | } |
311 | ||
0eb14833 ON |
312 | DO_ERROR(X86_TRAP_DE, SIGFPE, "divide error", divide_error) |
313 | DO_ERROR(X86_TRAP_OF, SIGSEGV, "overflow", overflow) | |
0eb14833 ON |
314 | DO_ERROR(X86_TRAP_UD, SIGILL, "invalid opcode", invalid_op) |
315 | DO_ERROR(X86_TRAP_OLD_MF, SIGFPE, "coprocessor segment overrun",coprocessor_segment_overrun) | |
316 | DO_ERROR(X86_TRAP_TS, SIGSEGV, "invalid TSS", invalid_TSS) | |
317 | DO_ERROR(X86_TRAP_NP, SIGBUS, "segment not present", segment_not_present) | |
0eb14833 | 318 | DO_ERROR(X86_TRAP_SS, SIGBUS, "stack segment", stack_segment) |
0eb14833 | 319 | DO_ERROR(X86_TRAP_AC, SIGBUS, "alignment check", alignment_check) |
1da177e4 | 320 | |
081f75bb AH |
321 | #ifdef CONFIG_X86_64 |
322 | /* Runs on IST stack */ | |
081f75bb AH |
323 | dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code) |
324 | { | |
325 | static const char str[] = "double fault"; | |
326 | struct task_struct *tsk = current; | |
327 | ||
af726f21 AL |
328 | #ifdef CONFIG_X86_ESPFIX64 |
329 | extern unsigned char native_irq_return_iret[]; | |
330 | ||
331 | /* | |
332 | * If IRET takes a non-IST fault on the espfix64 stack, then we | |
333 | * end up promoting it to a doublefault. In that case, modify | |
334 | * the stack to make it look like we just entered the #GP | |
335 | * handler from user space, similar to bad_iret. | |
95927475 AL |
336 | * |
337 | * No need for ist_enter here because we don't use RCU. | |
af726f21 AL |
338 | */ |
339 | if (((long)regs->sp >> PGDIR_SHIFT) == ESPFIX_PGD_ENTRY && | |
340 | regs->cs == __KERNEL_CS && | |
341 | regs->ip == (unsigned long)native_irq_return_iret) | |
342 | { | |
343 | struct pt_regs *normal_regs = task_pt_regs(current); | |
344 | ||
345 | /* Fake a #GP(0) from userspace. */ | |
346 | memmove(&normal_regs->ip, (void *)regs->sp, 5*8); | |
347 | normal_regs->orig_ax = 0; /* Missing (lost) #GP error code */ | |
348 | regs->ip = (unsigned long)general_protection; | |
349 | regs->sp = (unsigned long)&normal_regs->orig_ax; | |
95927475 | 350 | |
af726f21 AL |
351 | return; |
352 | } | |
353 | #endif | |
354 | ||
95927475 | 355 | ist_enter(regs); /* Discard prev_state because we won't return. */ |
c9408265 | 356 | notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV); |
081f75bb AH |
357 | |
358 | tsk->thread.error_code = error_code; | |
51e7dc70 | 359 | tsk->thread.trap_nr = X86_TRAP_DF; |
081f75bb | 360 | |
4d067d8e BP |
361 | #ifdef CONFIG_DOUBLEFAULT |
362 | df_debug(regs, error_code); | |
363 | #endif | |
bd8b96df IM |
364 | /* |
365 | * This is always a kernel trap and never fixable (and thus must | |
366 | * never return). | |
367 | */ | |
081f75bb AH |
368 | for (;;) |
369 | die(str, regs, error_code); | |
370 | } | |
371 | #endif | |
372 | ||
fe3d197f DH |
373 | dotraplinkage void do_bounds(struct pt_regs *regs, long error_code) |
374 | { | |
375 | struct task_struct *tsk = current; | |
376 | struct xsave_struct *xsave_buf; | |
377 | enum ctx_state prev_state; | |
378 | struct bndcsr *bndcsr; | |
379 | siginfo_t *info; | |
380 | ||
381 | prev_state = exception_enter(); | |
382 | if (notify_die(DIE_TRAP, "bounds", regs, error_code, | |
383 | X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP) | |
384 | goto exit; | |
385 | conditional_sti(regs); | |
386 | ||
f39b6f0e | 387 | if (!user_mode(regs)) |
fe3d197f DH |
388 | die("bounds", regs, error_code); |
389 | ||
390 | if (!cpu_feature_enabled(X86_FEATURE_MPX)) { | |
391 | /* The exception is not from Intel MPX */ | |
392 | goto exit_trap; | |
393 | } | |
394 | ||
395 | /* | |
396 | * We need to look at BNDSTATUS to resolve this exception. | |
397 | * It is not directly accessible, though, so we need to | |
398 | * do an xsave and then pull it out of the xsave buffer. | |
399 | */ | |
400 | fpu_save_init(&tsk->thread.fpu); | |
401 | xsave_buf = &(tsk->thread.fpu.state->xsave); | |
402 | bndcsr = get_xsave_addr(xsave_buf, XSTATE_BNDCSR); | |
403 | if (!bndcsr) | |
404 | goto exit_trap; | |
405 | ||
406 | /* | |
407 | * The error code field of the BNDSTATUS register communicates status | |
408 | * information of a bound range exception #BR or operation involving | |
409 | * bound directory. | |
410 | */ | |
411 | switch (bndcsr->bndstatus & MPX_BNDSTA_ERROR_CODE) { | |
412 | case 2: /* Bound directory has invalid entry. */ | |
413 | if (mpx_handle_bd_fault(xsave_buf)) | |
414 | goto exit_trap; | |
415 | break; /* Success, it was handled */ | |
416 | case 1: /* Bound violation. */ | |
417 | info = mpx_generate_siginfo(regs, xsave_buf); | |
e10abb2f | 418 | if (IS_ERR(info)) { |
fe3d197f DH |
419 | /* |
420 | * We failed to decode the MPX instruction. Act as if | |
421 | * the exception was not caused by MPX. | |
422 | */ | |
423 | goto exit_trap; | |
424 | } | |
425 | /* | |
426 | * Success, we decoded the instruction and retrieved | |
427 | * an 'info' containing the address being accessed | |
428 | * which caused the exception. This information | |
429 | * allows and application to possibly handle the | |
430 | * #BR exception itself. | |
431 | */ | |
432 | do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, info); | |
433 | kfree(info); | |
434 | break; | |
435 | case 0: /* No exception caused by Intel MPX operations. */ | |
436 | goto exit_trap; | |
437 | default: | |
438 | die("bounds", regs, error_code); | |
439 | } | |
440 | ||
441 | exit: | |
442 | exception_exit(prev_state); | |
443 | return; | |
444 | exit_trap: | |
445 | /* | |
446 | * This path out is for all the cases where we could not | |
447 | * handle the exception in some way (like allocating a | |
448 | * table or telling userspace about it. We will also end | |
449 | * up here if the kernel has MPX turned off at compile | |
450 | * time.. | |
451 | */ | |
452 | do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, NULL); | |
453 | exception_exit(prev_state); | |
454 | } | |
455 | ||
9326638c | 456 | dotraplinkage void |
13485ab5 | 457 | do_general_protection(struct pt_regs *regs, long error_code) |
1da177e4 | 458 | { |
13485ab5 | 459 | struct task_struct *tsk; |
6c1e0256 | 460 | enum ctx_state prev_state; |
b5964405 | 461 | |
6c1e0256 | 462 | prev_state = exception_enter(); |
c6df0d71 AH |
463 | conditional_sti(regs); |
464 | ||
081f75bb | 465 | #ifdef CONFIG_X86_32 |
ef3f6288 FW |
466 | if (regs->flags & X86_VM_MASK) { |
467 | local_irq_enable(); | |
468 | handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code); | |
6ba3c97a | 469 | goto exit; |
ef3f6288 | 470 | } |
081f75bb | 471 | #endif |
1da177e4 | 472 | |
13485ab5 | 473 | tsk = current; |
ae60f071 | 474 | if (!user_mode_ignore_vm86(regs)) { |
ef3f6288 | 475 | if (fixup_exception(regs)) |
6ba3c97a | 476 | goto exit; |
ef3f6288 FW |
477 | |
478 | tsk->thread.error_code = error_code; | |
479 | tsk->thread.trap_nr = X86_TRAP_GP; | |
6ba3c97a FW |
480 | if (notify_die(DIE_GPF, "general protection fault", regs, error_code, |
481 | X86_TRAP_GP, SIGSEGV) != NOTIFY_STOP) | |
ef3f6288 | 482 | die("general protection fault", regs, error_code); |
6ba3c97a | 483 | goto exit; |
ef3f6288 | 484 | } |
1da177e4 | 485 | |
13485ab5 | 486 | tsk->thread.error_code = error_code; |
51e7dc70 | 487 | tsk->thread.trap_nr = X86_TRAP_GP; |
b5964405 | 488 | |
13485ab5 AH |
489 | if (show_unhandled_signals && unhandled_signal(tsk, SIGSEGV) && |
490 | printk_ratelimit()) { | |
c767a54b | 491 | pr_info("%s[%d] general protection ip:%lx sp:%lx error:%lx", |
13485ab5 AH |
492 | tsk->comm, task_pid_nr(tsk), |
493 | regs->ip, regs->sp, error_code); | |
03252919 | 494 | print_vma_addr(" in ", regs->ip); |
c767a54b | 495 | pr_cont("\n"); |
03252919 | 496 | } |
abd4f750 | 497 | |
38cad57b | 498 | force_sig_info(SIGSEGV, SEND_SIG_PRIV, tsk); |
6ba3c97a | 499 | exit: |
6c1e0256 | 500 | exception_exit(prev_state); |
1da177e4 | 501 | } |
9326638c | 502 | NOKPROBE_SYMBOL(do_general_protection); |
1da177e4 | 503 | |
c1d518c8 | 504 | /* May run on IST stack. */ |
9326638c | 505 | dotraplinkage void notrace do_int3(struct pt_regs *regs, long error_code) |
1da177e4 | 506 | { |
6c1e0256 FW |
507 | enum ctx_state prev_state; |
508 | ||
08d636b6 | 509 | #ifdef CONFIG_DYNAMIC_FTRACE |
a192cd04 SR |
510 | /* |
511 | * ftrace must be first, everything else may cause a recursive crash. | |
512 | * See note by declaration of modifying_ftrace_code in ftrace.c | |
513 | */ | |
514 | if (unlikely(atomic_read(&modifying_ftrace_code)) && | |
515 | ftrace_int3_handler(regs)) | |
08d636b6 SR |
516 | return; |
517 | #endif | |
17f41571 JK |
518 | if (poke_int3_handler(regs)) |
519 | return; | |
520 | ||
95927475 | 521 | prev_state = ist_enter(regs); |
f503b5ae | 522 | #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP |
c9408265 KC |
523 | if (kgdb_ll_trap(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP, |
524 | SIGTRAP) == NOTIFY_STOP) | |
6ba3c97a | 525 | goto exit; |
f503b5ae | 526 | #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ |
cc3a1bf5 | 527 | |
6f6343f5 MH |
528 | #ifdef CONFIG_KPROBES |
529 | if (kprobe_int3_handler(regs)) | |
4cdf77a8 | 530 | goto exit; |
6f6343f5 MH |
531 | #endif |
532 | ||
c9408265 KC |
533 | if (notify_die(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP, |
534 | SIGTRAP) == NOTIFY_STOP) | |
6ba3c97a | 535 | goto exit; |
b5964405 | 536 | |
42181186 SR |
537 | /* |
538 | * Let others (NMI) know that the debug stack is in use | |
539 | * as we may switch to the interrupt stack. | |
540 | */ | |
541 | debug_stack_usage_inc(); | |
4915a35e | 542 | preempt_conditional_sti(regs); |
c9408265 | 543 | do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, error_code, NULL); |
4915a35e | 544 | preempt_conditional_cli(regs); |
42181186 | 545 | debug_stack_usage_dec(); |
6ba3c97a | 546 | exit: |
95927475 | 547 | ist_exit(regs, prev_state); |
1da177e4 | 548 | } |
9326638c | 549 | NOKPROBE_SYMBOL(do_int3); |
1da177e4 | 550 | |
081f75bb | 551 | #ifdef CONFIG_X86_64 |
bd8b96df | 552 | /* |
48e08d0f AL |
553 | * Help handler running on IST stack to switch off the IST stack if the |
554 | * interrupted code was in user mode. The actual stack switch is done in | |
555 | * entry_64.S | |
bd8b96df | 556 | */ |
7ddc6a21 | 557 | asmlinkage __visible notrace struct pt_regs *sync_regs(struct pt_regs *eregs) |
081f75bb | 558 | { |
48e08d0f AL |
559 | struct pt_regs *regs = task_pt_regs(current); |
560 | *regs = *eregs; | |
081f75bb AH |
561 | return regs; |
562 | } | |
9326638c | 563 | NOKPROBE_SYMBOL(sync_regs); |
b645af2d AL |
564 | |
565 | struct bad_iret_stack { | |
566 | void *error_entry_ret; | |
567 | struct pt_regs regs; | |
568 | }; | |
569 | ||
7ddc6a21 | 570 | asmlinkage __visible notrace |
b645af2d AL |
571 | struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s) |
572 | { | |
573 | /* | |
574 | * This is called from entry_64.S early in handling a fault | |
575 | * caused by a bad iret to user mode. To handle the fault | |
576 | * correctly, we want move our stack frame to task_pt_regs | |
577 | * and we want to pretend that the exception came from the | |
578 | * iret target. | |
579 | */ | |
580 | struct bad_iret_stack *new_stack = | |
581 | container_of(task_pt_regs(current), | |
582 | struct bad_iret_stack, regs); | |
583 | ||
584 | /* Copy the IRET target to the new stack. */ | |
585 | memmove(&new_stack->regs.ip, (void *)s->regs.sp, 5*8); | |
586 | ||
587 | /* Copy the remainder of the stack from the current stack. */ | |
588 | memmove(new_stack, s, offsetof(struct bad_iret_stack, regs.ip)); | |
589 | ||
f39b6f0e | 590 | BUG_ON(!user_mode(&new_stack->regs)); |
b645af2d AL |
591 | return new_stack; |
592 | } | |
7ddc6a21 | 593 | NOKPROBE_SYMBOL(fixup_bad_iret); |
081f75bb AH |
594 | #endif |
595 | ||
1da177e4 LT |
596 | /* |
597 | * Our handling of the processor debug registers is non-trivial. | |
598 | * We do not clear them on entry and exit from the kernel. Therefore | |
599 | * it is possible to get a watchpoint trap here from inside the kernel. | |
600 | * However, the code in ./ptrace.c has ensured that the user can | |
601 | * only set watchpoints on userspace addresses. Therefore the in-kernel | |
602 | * watchpoint trap can only occur in code which is reading/writing | |
603 | * from user space. Such code must not hold kernel locks (since it | |
604 | * can equally take a page fault), therefore it is safe to call | |
605 | * force_sig_info even though that claims and releases locks. | |
b5964405 | 606 | * |
1da177e4 LT |
607 | * Code in ./signal.c ensures that the debug control register |
608 | * is restored before we deliver any signal, and therefore that | |
609 | * user code runs with the correct debug control register even though | |
610 | * we clear it here. | |
611 | * | |
612 | * Being careful here means that we don't have to be as careful in a | |
613 | * lot of more complicated places (task switching can be a bit lazy | |
614 | * about restoring all the debug state, and ptrace doesn't have to | |
615 | * find every occurrence of the TF bit that could be saved away even | |
616 | * by user code) | |
c1d518c8 AH |
617 | * |
618 | * May run on IST stack. | |
1da177e4 | 619 | */ |
9326638c | 620 | dotraplinkage void do_debug(struct pt_regs *regs, long error_code) |
1da177e4 | 621 | { |
1da177e4 | 622 | struct task_struct *tsk = current; |
6c1e0256 | 623 | enum ctx_state prev_state; |
a1e80faf | 624 | int user_icebp = 0; |
08d68323 | 625 | unsigned long dr6; |
da654b74 | 626 | int si_code; |
1da177e4 | 627 | |
95927475 | 628 | prev_state = ist_enter(regs); |
4cdf77a8 | 629 | |
08d68323 | 630 | get_debugreg(dr6, 6); |
1da177e4 | 631 | |
40f9249a P |
632 | /* Filter out all the reserved bits which are preset to 1 */ |
633 | dr6 &= ~DR6_RESERVED; | |
634 | ||
a1e80faf FW |
635 | /* |
636 | * If dr6 has no reason to give us about the origin of this trap, | |
637 | * then it's very likely the result of an icebp/int01 trap. | |
638 | * User wants a sigtrap for that. | |
639 | */ | |
f39b6f0e | 640 | if (!dr6 && user_mode(regs)) |
a1e80faf FW |
641 | user_icebp = 1; |
642 | ||
f8561296 | 643 | /* Catch kmemcheck conditions first of all! */ |
eadb8a09 | 644 | if ((dr6 & DR_STEP) && kmemcheck_trap(regs)) |
6ba3c97a | 645 | goto exit; |
f8561296 | 646 | |
08d68323 P |
647 | /* DR6 may or may not be cleared by the CPU */ |
648 | set_debugreg(0, 6); | |
10faa81e | 649 | |
ea8e61b7 PZ |
650 | /* |
651 | * The processor cleared BTF, so don't mark that we need it set. | |
652 | */ | |
653 | clear_tsk_thread_flag(tsk, TIF_BLOCKSTEP); | |
654 | ||
08d68323 P |
655 | /* Store the virtualized DR6 value */ |
656 | tsk->thread.debugreg6 = dr6; | |
657 | ||
6f6343f5 MH |
658 | #ifdef CONFIG_KPROBES |
659 | if (kprobe_debug_handler(regs)) | |
660 | goto exit; | |
661 | #endif | |
662 | ||
5a802e15 | 663 | if (notify_die(DIE_DEBUG, "debug", regs, (long)&dr6, error_code, |
62edab90 | 664 | SIGTRAP) == NOTIFY_STOP) |
6ba3c97a | 665 | goto exit; |
3d2a71a5 | 666 | |
42181186 SR |
667 | /* |
668 | * Let others (NMI) know that the debug stack is in use | |
669 | * as we may switch to the interrupt stack. | |
670 | */ | |
671 | debug_stack_usage_inc(); | |
672 | ||
1da177e4 | 673 | /* It's safe to allow irq's after DR6 has been saved */ |
3d2a71a5 | 674 | preempt_conditional_sti(regs); |
1da177e4 | 675 | |
08d68323 | 676 | if (regs->flags & X86_VM_MASK) { |
c9408265 KC |
677 | handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code, |
678 | X86_TRAP_DB); | |
6554287b | 679 | preempt_conditional_cli(regs); |
42181186 | 680 | debug_stack_usage_dec(); |
6ba3c97a | 681 | goto exit; |
1da177e4 LT |
682 | } |
683 | ||
1da177e4 | 684 | /* |
08d68323 P |
685 | * Single-stepping through system calls: ignore any exceptions in |
686 | * kernel space, but re-enable TF when returning to user mode. | |
687 | * | |
688 | * We already checked v86 mode above, so we can check for kernel mode | |
689 | * by just checking the CPL of CS. | |
1da177e4 | 690 | */ |
ae60f071 | 691 | if ((dr6 & DR_STEP) && !user_mode_ignore_vm86(regs)) { |
08d68323 P |
692 | tsk->thread.debugreg6 &= ~DR_STEP; |
693 | set_tsk_thread_flag(tsk, TIF_SINGLESTEP); | |
694 | regs->flags &= ~X86_EFLAGS_TF; | |
1da177e4 | 695 | } |
08d68323 | 696 | si_code = get_si_code(tsk->thread.debugreg6); |
a1e80faf | 697 | if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS) || user_icebp) |
08d68323 | 698 | send_sigtrap(tsk, regs, error_code, si_code); |
3d2a71a5 | 699 | preempt_conditional_cli(regs); |
42181186 | 700 | debug_stack_usage_dec(); |
1da177e4 | 701 | |
6ba3c97a | 702 | exit: |
95927475 | 703 | ist_exit(regs, prev_state); |
1da177e4 | 704 | } |
9326638c | 705 | NOKPROBE_SYMBOL(do_debug); |
1da177e4 LT |
706 | |
707 | /* | |
708 | * Note that we play around with the 'TS' bit in an attempt to get | |
709 | * the correct behaviour even in the presence of the asynchronous | |
710 | * IRQ13 behaviour | |
711 | */ | |
5e1b05be | 712 | static void math_error(struct pt_regs *regs, int error_code, int trapnr) |
1da177e4 | 713 | { |
e2e75c91 | 714 | struct task_struct *task = current; |
1da177e4 | 715 | siginfo_t info; |
9b6dba9e | 716 | unsigned short err; |
c9408265 KC |
717 | char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" : |
718 | "simd exception"; | |
e2e75c91 BG |
719 | |
720 | if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, SIGFPE) == NOTIFY_STOP) | |
721 | return; | |
722 | conditional_sti(regs); | |
723 | ||
f39b6f0e | 724 | if (!user_mode(regs)) |
e2e75c91 BG |
725 | { |
726 | if (!fixup_exception(regs)) { | |
727 | task->thread.error_code = error_code; | |
51e7dc70 | 728 | task->thread.trap_nr = trapnr; |
e2e75c91 BG |
729 | die(str, regs, error_code); |
730 | } | |
731 | return; | |
732 | } | |
1da177e4 LT |
733 | |
734 | /* | |
735 | * Save the info for the exception handler and clear the error. | |
736 | */ | |
1da177e4 | 737 | save_init_fpu(task); |
51e7dc70 | 738 | task->thread.trap_nr = trapnr; |
9b6dba9e | 739 | task->thread.error_code = error_code; |
1da177e4 LT |
740 | info.si_signo = SIGFPE; |
741 | info.si_errno = 0; | |
b02ef20a | 742 | info.si_addr = (void __user *)uprobe_get_trap_addr(regs); |
c9408265 | 743 | if (trapnr == X86_TRAP_MF) { |
9b6dba9e BG |
744 | unsigned short cwd, swd; |
745 | /* | |
746 | * (~cwd & swd) will mask out exceptions that are not set to unmasked | |
747 | * status. 0x3f is the exception bits in these regs, 0x200 is the | |
748 | * C1 reg you need in case of a stack fault, 0x040 is the stack | |
749 | * fault bit. We should only be taking one exception at a time, | |
750 | * so if this combination doesn't produce any single exception, | |
751 | * then we have a bad program that isn't synchronizing its FPU usage | |
752 | * and it will suffer the consequences since we won't be able to | |
753 | * fully reproduce the context of the exception | |
754 | */ | |
755 | cwd = get_fpu_cwd(task); | |
756 | swd = get_fpu_swd(task); | |
adf77bac | 757 | |
9b6dba9e BG |
758 | err = swd & ~cwd; |
759 | } else { | |
760 | /* | |
761 | * The SIMD FPU exceptions are handled a little differently, as there | |
762 | * is only a single status/control register. Thus, to determine which | |
763 | * unmasked exception was caught we must mask the exception mask bits | |
764 | * at 0x1f80, and then use these to mask the exception bits at 0x3f. | |
765 | */ | |
766 | unsigned short mxcsr = get_fpu_mxcsr(task); | |
767 | err = ~(mxcsr >> 7) & mxcsr; | |
768 | } | |
adf77bac PA |
769 | |
770 | if (err & 0x001) { /* Invalid op */ | |
b5964405 IM |
771 | /* |
772 | * swd & 0x240 == 0x040: Stack Underflow | |
773 | * swd & 0x240 == 0x240: Stack Overflow | |
774 | * User must clear the SF bit (0x40) if set | |
775 | */ | |
776 | info.si_code = FPE_FLTINV; | |
adf77bac | 777 | } else if (err & 0x004) { /* Divide by Zero */ |
b5964405 | 778 | info.si_code = FPE_FLTDIV; |
adf77bac | 779 | } else if (err & 0x008) { /* Overflow */ |
b5964405 | 780 | info.si_code = FPE_FLTOVF; |
adf77bac PA |
781 | } else if (err & 0x012) { /* Denormal, Underflow */ |
782 | info.si_code = FPE_FLTUND; | |
783 | } else if (err & 0x020) { /* Precision */ | |
b5964405 | 784 | info.si_code = FPE_FLTRES; |
adf77bac | 785 | } else { |
bd8b96df | 786 | /* |
c9408265 KC |
787 | * If we're using IRQ 13, or supposedly even some trap |
788 | * X86_TRAP_MF implementations, it's possible | |
789 | * we get a spurious trap, which is not an error. | |
bd8b96df | 790 | */ |
c9408265 | 791 | return; |
1da177e4 LT |
792 | } |
793 | force_sig_info(SIGFPE, &info, task); | |
794 | } | |
795 | ||
e407d620 | 796 | dotraplinkage void do_coprocessor_error(struct pt_regs *regs, long error_code) |
1da177e4 | 797 | { |
6c1e0256 FW |
798 | enum ctx_state prev_state; |
799 | ||
800 | prev_state = exception_enter(); | |
c9408265 | 801 | math_error(regs, error_code, X86_TRAP_MF); |
6c1e0256 | 802 | exception_exit(prev_state); |
1da177e4 LT |
803 | } |
804 | ||
e407d620 AH |
805 | dotraplinkage void |
806 | do_simd_coprocessor_error(struct pt_regs *regs, long error_code) | |
1da177e4 | 807 | { |
6c1e0256 FW |
808 | enum ctx_state prev_state; |
809 | ||
810 | prev_state = exception_enter(); | |
c9408265 | 811 | math_error(regs, error_code, X86_TRAP_XF); |
6c1e0256 | 812 | exception_exit(prev_state); |
1da177e4 LT |
813 | } |
814 | ||
e407d620 AH |
815 | dotraplinkage void |
816 | do_spurious_interrupt_bug(struct pt_regs *regs, long error_code) | |
1da177e4 | 817 | { |
cf81978d | 818 | conditional_sti(regs); |
1da177e4 LT |
819 | #if 0 |
820 | /* No need to warn about this any longer. */ | |
c767a54b | 821 | pr_info("Ignoring P6 Local APIC Spurious Interrupt Bug...\n"); |
1da177e4 LT |
822 | #endif |
823 | } | |
824 | ||
2605fc21 | 825 | asmlinkage __visible void __attribute__((weak)) smp_thermal_interrupt(void) |
1da177e4 | 826 | { |
1da177e4 | 827 | } |
4efc0670 | 828 | |
2605fc21 | 829 | asmlinkage __visible void __attribute__((weak)) smp_threshold_interrupt(void) |
081f75bb AH |
830 | { |
831 | } | |
832 | ||
1da177e4 | 833 | /* |
b5964405 | 834 | * 'math_state_restore()' saves the current math information in the |
1da177e4 LT |
835 | * old math state array, and gets the new ones from the current task |
836 | * | |
837 | * Careful.. There are problems with IBM-designed IRQ13 behaviour. | |
838 | * Don't touch unless you *really* know how it works. | |
839 | * | |
be98c2cd LT |
840 | * Must be called with kernel preemption disabled (eg with local |
841 | * local interrupts as in the case of do_device_not_available). | |
1da177e4 | 842 | */ |
be98c2cd | 843 | void math_state_restore(void) |
1da177e4 | 844 | { |
f94edacf | 845 | struct task_struct *tsk = current; |
1da177e4 | 846 | |
aa283f49 SS |
847 | if (!tsk_used_math(tsk)) { |
848 | local_irq_enable(); | |
849 | /* | |
850 | * does a slab alloc which can sleep | |
851 | */ | |
852 | if (init_fpu(tsk)) { | |
853 | /* | |
854 | * ran out of memory! | |
855 | */ | |
856 | do_group_exit(SIGKILL); | |
857 | return; | |
858 | } | |
859 | local_irq_disable(); | |
860 | } | |
861 | ||
7575637a ON |
862 | /* Avoid __kernel_fpu_begin() right after __thread_fpu_begin() */ |
863 | kernel_fpu_disable(); | |
f94edacf | 864 | __thread_fpu_begin(tsk); |
80ab6f1e | 865 | if (unlikely(restore_fpu_checking(tsk))) { |
304bceda | 866 | drop_init_fpu(tsk); |
38cad57b | 867 | force_sig_info(SIGSEGV, SEND_SIG_PRIV, tsk); |
7575637a ON |
868 | } else { |
869 | tsk->thread.fpu_counter++; | |
80ab6f1e | 870 | } |
7575637a | 871 | kernel_fpu_enable(); |
1da177e4 | 872 | } |
5992b6da | 873 | EXPORT_SYMBOL_GPL(math_state_restore); |
1da177e4 | 874 | |
9326638c | 875 | dotraplinkage void |
aa78bcfa | 876 | do_device_not_available(struct pt_regs *regs, long error_code) |
7643e9b9 | 877 | { |
6c1e0256 FW |
878 | enum ctx_state prev_state; |
879 | ||
880 | prev_state = exception_enter(); | |
5d2bd700 | 881 | BUG_ON(use_eager_fpu()); |
304bceda | 882 | |
a334fe43 | 883 | #ifdef CONFIG_MATH_EMULATION |
7643e9b9 | 884 | if (read_cr0() & X86_CR0_EM) { |
d315760f TH |
885 | struct math_emu_info info = { }; |
886 | ||
7643e9b9 | 887 | conditional_sti(regs); |
d315760f | 888 | |
aa78bcfa | 889 | info.regs = regs; |
d315760f | 890 | math_emulate(&info); |
6c1e0256 | 891 | exception_exit(prev_state); |
a334fe43 | 892 | return; |
7643e9b9 | 893 | } |
a334fe43 BG |
894 | #endif |
895 | math_state_restore(); /* interrupts still off */ | |
896 | #ifdef CONFIG_X86_32 | |
897 | conditional_sti(regs); | |
081f75bb | 898 | #endif |
6c1e0256 | 899 | exception_exit(prev_state); |
7643e9b9 | 900 | } |
9326638c | 901 | NOKPROBE_SYMBOL(do_device_not_available); |
7643e9b9 | 902 | |
081f75bb | 903 | #ifdef CONFIG_X86_32 |
e407d620 | 904 | dotraplinkage void do_iret_error(struct pt_regs *regs, long error_code) |
f8e0870f AH |
905 | { |
906 | siginfo_t info; | |
6c1e0256 | 907 | enum ctx_state prev_state; |
6ba3c97a | 908 | |
6c1e0256 | 909 | prev_state = exception_enter(); |
f8e0870f AH |
910 | local_irq_enable(); |
911 | ||
912 | info.si_signo = SIGILL; | |
913 | info.si_errno = 0; | |
914 | info.si_code = ILL_BADSTK; | |
fc6fcdfb | 915 | info.si_addr = NULL; |
c9408265 | 916 | if (notify_die(DIE_TRAP, "iret exception", regs, error_code, |
6ba3c97a FW |
917 | X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) { |
918 | do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, error_code, | |
919 | &info); | |
920 | } | |
6c1e0256 | 921 | exception_exit(prev_state); |
f8e0870f | 922 | } |
081f75bb | 923 | #endif |
f8e0870f | 924 | |
29c84391 JK |
925 | /* Set of traps needed for early debugging. */ |
926 | void __init early_trap_init(void) | |
927 | { | |
b4d83270 | 928 | /* |
5eca7453 WN |
929 | * Don't use IST to set DEBUG_STACK as it doesn't work until TSS |
930 | * is ready in cpu_init() <-- trap_init(). Before trap_init(), | |
931 | * CPU runs at ring 0 so it is impossible to hit an invalid | |
932 | * stack. Using the original stack works well enough at this | |
933 | * early stage. DEBUG_STACK will be equipped after cpu_init() in | |
b4d83270 | 934 | * trap_init(). |
5eca7453 WN |
935 | * |
936 | * We don't need to set trace_idt_table like set_intr_gate(), | |
937 | * since we don't have trace_debug and it will be reset to | |
938 | * 'debug' in trap_init() by set_intr_gate_ist(). | |
b4d83270 | 939 | */ |
5eca7453 | 940 | set_intr_gate_notrace(X86_TRAP_DB, debug); |
29c84391 | 941 | /* int3 can be called from all */ |
5eca7453 | 942 | set_system_intr_gate(X86_TRAP_BP, &int3); |
8170e6be | 943 | #ifdef CONFIG_X86_32 |
25c74b10 | 944 | set_intr_gate(X86_TRAP_PF, page_fault); |
8170e6be | 945 | #endif |
29c84391 JK |
946 | load_idt(&idt_descr); |
947 | } | |
948 | ||
8170e6be PA |
949 | void __init early_trap_pf_init(void) |
950 | { | |
951 | #ifdef CONFIG_X86_64 | |
25c74b10 | 952 | set_intr_gate(X86_TRAP_PF, page_fault); |
8170e6be PA |
953 | #endif |
954 | } | |
955 | ||
1da177e4 LT |
956 | void __init trap_init(void) |
957 | { | |
dbeb2be2 RR |
958 | int i; |
959 | ||
1da177e4 | 960 | #ifdef CONFIG_EISA |
927222b1 | 961 | void __iomem *p = early_ioremap(0x0FFFD9, 4); |
b5964405 IM |
962 | |
963 | if (readl(p) == 'E' + ('I'<<8) + ('S'<<16) + ('A'<<24)) | |
1da177e4 | 964 | EISA_bus = 1; |
927222b1 | 965 | early_iounmap(p, 4); |
1da177e4 LT |
966 | #endif |
967 | ||
25c74b10 | 968 | set_intr_gate(X86_TRAP_DE, divide_error); |
c9408265 | 969 | set_intr_gate_ist(X86_TRAP_NMI, &nmi, NMI_STACK); |
699d2937 | 970 | /* int4 can be called from all */ |
c9408265 | 971 | set_system_intr_gate(X86_TRAP_OF, &overflow); |
25c74b10 SA |
972 | set_intr_gate(X86_TRAP_BR, bounds); |
973 | set_intr_gate(X86_TRAP_UD, invalid_op); | |
974 | set_intr_gate(X86_TRAP_NM, device_not_available); | |
081f75bb | 975 | #ifdef CONFIG_X86_32 |
c9408265 | 976 | set_task_gate(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS); |
081f75bb | 977 | #else |
c9408265 | 978 | set_intr_gate_ist(X86_TRAP_DF, &double_fault, DOUBLEFAULT_STACK); |
081f75bb | 979 | #endif |
25c74b10 SA |
980 | set_intr_gate(X86_TRAP_OLD_MF, coprocessor_segment_overrun); |
981 | set_intr_gate(X86_TRAP_TS, invalid_TSS); | |
982 | set_intr_gate(X86_TRAP_NP, segment_not_present); | |
6f442be2 | 983 | set_intr_gate(X86_TRAP_SS, stack_segment); |
25c74b10 SA |
984 | set_intr_gate(X86_TRAP_GP, general_protection); |
985 | set_intr_gate(X86_TRAP_SPURIOUS, spurious_interrupt_bug); | |
986 | set_intr_gate(X86_TRAP_MF, coprocessor_error); | |
987 | set_intr_gate(X86_TRAP_AC, alignment_check); | |
1da177e4 | 988 | #ifdef CONFIG_X86_MCE |
c9408265 | 989 | set_intr_gate_ist(X86_TRAP_MC, &machine_check, MCE_STACK); |
1da177e4 | 990 | #endif |
25c74b10 | 991 | set_intr_gate(X86_TRAP_XF, simd_coprocessor_error); |
1da177e4 | 992 | |
bb3f0b59 YL |
993 | /* Reserve all the builtin and the syscall vector: */ |
994 | for (i = 0; i < FIRST_EXTERNAL_VECTOR; i++) | |
995 | set_bit(i, used_vectors); | |
996 | ||
081f75bb AH |
997 | #ifdef CONFIG_IA32_EMULATION |
998 | set_system_intr_gate(IA32_SYSCALL_VECTOR, ia32_syscall); | |
bb3f0b59 | 999 | set_bit(IA32_SYSCALL_VECTOR, used_vectors); |
081f75bb AH |
1000 | #endif |
1001 | ||
1002 | #ifdef CONFIG_X86_32 | |
699d2937 | 1003 | set_system_trap_gate(SYSCALL_VECTOR, &system_call); |
dbeb2be2 | 1004 | set_bit(SYSCALL_VECTOR, used_vectors); |
081f75bb | 1005 | #endif |
bb3f0b59 | 1006 | |
4eefbe79 KC |
1007 | /* |
1008 | * Set the IDT descriptor to a fixed read-only location, so that the | |
1009 | * "sidt" instruction will not leak the location of the kernel, and | |
1010 | * to defend the IDT against arbitrary memory write vulnerabilities. | |
1011 | * It will be reloaded in cpu_init() */ | |
1012 | __set_fixmap(FIX_RO_IDT, __pa_symbol(idt_table), PAGE_KERNEL_RO); | |
1013 | idt_descr.address = fix_to_virt(FIX_RO_IDT); | |
1014 | ||
1da177e4 | 1015 | /* |
b5964405 | 1016 | * Should be a barrier for any external CPU state: |
1da177e4 LT |
1017 | */ |
1018 | cpu_init(); | |
1019 | ||
b4d83270 WN |
1020 | /* |
1021 | * X86_TRAP_DB and X86_TRAP_BP have been set | |
5eca7453 | 1022 | * in early_trap_init(). However, ITS works only after |
b4d83270 WN |
1023 | * cpu_init() loads TSS. See comments in early_trap_init(). |
1024 | */ | |
1025 | set_intr_gate_ist(X86_TRAP_DB, &debug, DEBUG_STACK); | |
1026 | /* int3 can be called from all */ | |
1027 | set_system_intr_gate_ist(X86_TRAP_BP, &int3, DEBUG_STACK); | |
1028 | ||
428cf902 | 1029 | x86_init.irqs.trap_init(); |
228bdaa9 SR |
1030 | |
1031 | #ifdef CONFIG_X86_64 | |
629f4f9d | 1032 | memcpy(&debug_idt_table, &idt_table, IDT_ENTRIES * 16); |
c9408265 KC |
1033 | set_nmi_gate(X86_TRAP_DB, &debug); |
1034 | set_nmi_gate(X86_TRAP_BP, &int3); | |
228bdaa9 | 1035 | #endif |
1da177e4 | 1036 | } |