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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 1991, 1992 Linus Torvalds |
a8c1be9d | 3 | * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs |
1da177e4 LT |
4 | * |
5 | * Pentium III FXSR, SSE support | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | */ | |
8 | ||
9 | /* | |
c1d518c8 | 10 | * Handle hardware traps and faults. |
1da177e4 | 11 | */ |
c767a54b JP |
12 | |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
14 | ||
56dd9470 | 15 | #include <linux/context_tracking.h> |
b5964405 IM |
16 | #include <linux/interrupt.h> |
17 | #include <linux/kallsyms.h> | |
18 | #include <linux/spinlock.h> | |
b5964405 IM |
19 | #include <linux/kprobes.h> |
20 | #include <linux/uaccess.h> | |
b5964405 | 21 | #include <linux/kdebug.h> |
f503b5ae | 22 | #include <linux/kgdb.h> |
1da177e4 | 23 | #include <linux/kernel.h> |
b5964405 IM |
24 | #include <linux/module.h> |
25 | #include <linux/ptrace.h> | |
b02ef20a | 26 | #include <linux/uprobes.h> |
1da177e4 | 27 | #include <linux/string.h> |
b5964405 | 28 | #include <linux/delay.h> |
1da177e4 | 29 | #include <linux/errno.h> |
b5964405 IM |
30 | #include <linux/kexec.h> |
31 | #include <linux/sched.h> | |
1da177e4 | 32 | #include <linux/timer.h> |
1da177e4 | 33 | #include <linux/init.h> |
91768d6c | 34 | #include <linux/bug.h> |
b5964405 IM |
35 | #include <linux/nmi.h> |
36 | #include <linux/mm.h> | |
c1d518c8 AH |
37 | #include <linux/smp.h> |
38 | #include <linux/io.h> | |
1da177e4 LT |
39 | |
40 | #ifdef CONFIG_EISA | |
41 | #include <linux/ioport.h> | |
42 | #include <linux/eisa.h> | |
43 | #endif | |
44 | ||
c0d12172 DJ |
45 | #if defined(CONFIG_EDAC) |
46 | #include <linux/edac.h> | |
47 | #endif | |
48 | ||
f8561296 | 49 | #include <asm/kmemcheck.h> |
b5964405 | 50 | #include <asm/stacktrace.h> |
1da177e4 | 51 | #include <asm/processor.h> |
1da177e4 | 52 | #include <asm/debugreg.h> |
60063497 | 53 | #include <linux/atomic.h> |
08d636b6 | 54 | #include <asm/ftrace.h> |
c1d518c8 | 55 | #include <asm/traps.h> |
1da177e4 | 56 | #include <asm/desc.h> |
78f7f1e5 | 57 | #include <asm/fpu/internal.h> |
9e55e44e | 58 | #include <asm/mce.h> |
4eefbe79 | 59 | #include <asm/fixmap.h> |
1164dd00 | 60 | #include <asm/mach_traps.h> |
17f41571 | 61 | #include <asm/alternative.h> |
fe3d197f | 62 | #include <asm/mpx.h> |
c1d518c8 | 63 | |
081f75bb | 64 | #ifdef CONFIG_X86_64 |
428cf902 | 65 | #include <asm/x86_init.h> |
081f75bb AH |
66 | #include <asm/pgalloc.h> |
67 | #include <asm/proto.h> | |
4df05f36 KC |
68 | |
69 | /* No need to be aligned, but done to keep all IDTs defined the same way. */ | |
70 | gate_desc debug_idt_table[NR_VECTORS] __page_aligned_bss; | |
081f75bb | 71 | #else |
c1d518c8 | 72 | #include <asm/processor-flags.h> |
8e6dafd6 | 73 | #include <asm/setup.h> |
1da177e4 | 74 | |
1da177e4 | 75 | asmlinkage int system_call(void); |
081f75bb | 76 | #endif |
1da177e4 | 77 | |
4df05f36 KC |
78 | /* Must be page-aligned because the real IDT is used in a fixmap. */ |
79 | gate_desc idt_table[NR_VECTORS] __page_aligned_bss; | |
80 | ||
b77b881f YL |
81 | DECLARE_BITMAP(used_vectors, NR_VECTORS); |
82 | EXPORT_SYMBOL_GPL(used_vectors); | |
83 | ||
762db434 AH |
84 | static inline void conditional_sti(struct pt_regs *regs) |
85 | { | |
86 | if (regs->flags & X86_EFLAGS_IF) | |
87 | local_irq_enable(); | |
88 | } | |
89 | ||
3d2a71a5 AH |
90 | static inline void preempt_conditional_sti(struct pt_regs *regs) |
91 | { | |
bdb43806 | 92 | preempt_count_inc(); |
3d2a71a5 AH |
93 | if (regs->flags & X86_EFLAGS_IF) |
94 | local_irq_enable(); | |
95 | } | |
96 | ||
be716615 TG |
97 | static inline void conditional_cli(struct pt_regs *regs) |
98 | { | |
99 | if (regs->flags & X86_EFLAGS_IF) | |
100 | local_irq_disable(); | |
101 | } | |
102 | ||
3d2a71a5 AH |
103 | static inline void preempt_conditional_cli(struct pt_regs *regs) |
104 | { | |
105 | if (regs->flags & X86_EFLAGS_IF) | |
106 | local_irq_disable(); | |
bdb43806 | 107 | preempt_count_dec(); |
3d2a71a5 AH |
108 | } |
109 | ||
95927475 AL |
110 | enum ctx_state ist_enter(struct pt_regs *regs) |
111 | { | |
b926e6f6 | 112 | enum ctx_state prev_state; |
95927475 | 113 | |
f39b6f0e | 114 | if (user_mode(regs)) { |
95927475 | 115 | /* Other than that, we're just an exception. */ |
b926e6f6 | 116 | prev_state = exception_enter(); |
95927475 AL |
117 | } else { |
118 | /* | |
119 | * We might have interrupted pretty much anything. In | |
120 | * fact, if we're a machine check, we can even interrupt | |
121 | * NMI processing. We don't want in_nmi() to return true, | |
122 | * but we need to notify RCU. | |
123 | */ | |
124 | rcu_nmi_enter(); | |
c467ea76 | 125 | prev_state = CONTEXT_KERNEL; /* the value is irrelevant. */ |
95927475 | 126 | } |
b926e6f6 AL |
127 | |
128 | /* | |
129 | * We are atomic because we're on the IST stack (or we're on x86_32, | |
130 | * in which case we still shouldn't schedule). | |
131 | * | |
132 | * This must be after exception_enter(), because exception_enter() | |
133 | * won't do anything if in_interrupt() returns true. | |
134 | */ | |
135 | preempt_count_add(HARDIRQ_OFFSET); | |
136 | ||
137 | /* This code is a bit fragile. Test it. */ | |
138 | rcu_lockdep_assert(rcu_is_watching(), "ist_enter didn't work"); | |
139 | ||
140 | return prev_state; | |
95927475 AL |
141 | } |
142 | ||
143 | void ist_exit(struct pt_regs *regs, enum ctx_state prev_state) | |
144 | { | |
b926e6f6 | 145 | /* Must be before exception_exit. */ |
95927475 AL |
146 | preempt_count_sub(HARDIRQ_OFFSET); |
147 | ||
f39b6f0e | 148 | if (user_mode(regs)) |
95927475 AL |
149 | return exception_exit(prev_state); |
150 | else | |
151 | rcu_nmi_exit(); | |
152 | } | |
153 | ||
bced35b6 AL |
154 | /** |
155 | * ist_begin_non_atomic() - begin a non-atomic section in an IST exception | |
156 | * @regs: regs passed to the IST exception handler | |
157 | * | |
158 | * IST exception handlers normally cannot schedule. As a special | |
159 | * exception, if the exception interrupted userspace code (i.e. | |
f39b6f0e | 160 | * user_mode(regs) would return true) and the exception was not |
bced35b6 AL |
161 | * a double fault, it can be safe to schedule. ist_begin_non_atomic() |
162 | * begins a non-atomic section within an ist_enter()/ist_exit() region. | |
163 | * Callers are responsible for enabling interrupts themselves inside | |
164 | * the non-atomic section, and callers must call is_end_non_atomic() | |
165 | * before ist_exit(). | |
166 | */ | |
167 | void ist_begin_non_atomic(struct pt_regs *regs) | |
168 | { | |
f39b6f0e | 169 | BUG_ON(!user_mode(regs)); |
bced35b6 AL |
170 | |
171 | /* | |
172 | * Sanity check: we need to be on the normal thread stack. This | |
173 | * will catch asm bugs and any attempt to use ist_preempt_enable | |
174 | * from double_fault. | |
175 | */ | |
a7fcf28d AL |
176 | BUG_ON((unsigned long)(current_top_of_stack() - |
177 | current_stack_pointer()) >= THREAD_SIZE); | |
bced35b6 AL |
178 | |
179 | preempt_count_sub(HARDIRQ_OFFSET); | |
180 | } | |
181 | ||
182 | /** | |
183 | * ist_end_non_atomic() - begin a non-atomic section in an IST exception | |
184 | * | |
185 | * Ends a non-atomic section started with ist_begin_non_atomic(). | |
186 | */ | |
187 | void ist_end_non_atomic(void) | |
188 | { | |
189 | preempt_count_add(HARDIRQ_OFFSET); | |
190 | } | |
191 | ||
9326638c | 192 | static nokprobe_inline int |
c416ddf5 FW |
193 | do_trap_no_signal(struct task_struct *tsk, int trapnr, char *str, |
194 | struct pt_regs *regs, long error_code) | |
1da177e4 | 195 | { |
d74ef111 | 196 | if (v8086_mode(regs)) { |
3c1326f8 | 197 | /* |
c416ddf5 | 198 | * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86. |
3c1326f8 AH |
199 | * On nmi (interrupt 2), do_trap should not be called. |
200 | */ | |
c416ddf5 FW |
201 | if (trapnr < X86_TRAP_UD) { |
202 | if (!handle_vm86_trap((struct kernel_vm86_regs *) regs, | |
203 | error_code, trapnr)) | |
204 | return 0; | |
205 | } | |
206 | return -1; | |
1da177e4 | 207 | } |
d74ef111 | 208 | |
55474c48 | 209 | if (!user_mode(regs)) { |
c416ddf5 FW |
210 | if (!fixup_exception(regs)) { |
211 | tsk->thread.error_code = error_code; | |
212 | tsk->thread.trap_nr = trapnr; | |
213 | die(str, regs, error_code); | |
214 | } | |
215 | return 0; | |
216 | } | |
1da177e4 | 217 | |
c416ddf5 FW |
218 | return -1; |
219 | } | |
1da177e4 | 220 | |
1c326c4d ON |
221 | static siginfo_t *fill_trap_info(struct pt_regs *regs, int signr, int trapnr, |
222 | siginfo_t *info) | |
958d3d72 ON |
223 | { |
224 | unsigned long siaddr; | |
225 | int sicode; | |
226 | ||
227 | switch (trapnr) { | |
1c326c4d ON |
228 | default: |
229 | return SEND_SIG_PRIV; | |
230 | ||
958d3d72 ON |
231 | case X86_TRAP_DE: |
232 | sicode = FPE_INTDIV; | |
b02ef20a | 233 | siaddr = uprobe_get_trap_addr(regs); |
958d3d72 ON |
234 | break; |
235 | case X86_TRAP_UD: | |
236 | sicode = ILL_ILLOPN; | |
b02ef20a | 237 | siaddr = uprobe_get_trap_addr(regs); |
958d3d72 ON |
238 | break; |
239 | case X86_TRAP_AC: | |
240 | sicode = BUS_ADRALN; | |
241 | siaddr = 0; | |
242 | break; | |
243 | } | |
244 | ||
245 | info->si_signo = signr; | |
246 | info->si_errno = 0; | |
247 | info->si_code = sicode; | |
248 | info->si_addr = (void __user *)siaddr; | |
1c326c4d | 249 | return info; |
958d3d72 ON |
250 | } |
251 | ||
9326638c | 252 | static void |
c416ddf5 FW |
253 | do_trap(int trapnr, int signr, char *str, struct pt_regs *regs, |
254 | long error_code, siginfo_t *info) | |
255 | { | |
256 | struct task_struct *tsk = current; | |
257 | ||
258 | ||
259 | if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code)) | |
260 | return; | |
b5964405 | 261 | /* |
51e7dc70 | 262 | * We want error_code and trap_nr set for userspace faults and |
b5964405 IM |
263 | * kernelspace faults which result in die(), but not |
264 | * kernelspace faults which are fixed up. die() gives the | |
265 | * process no chance to handle the signal and notice the | |
266 | * kernel fault information, so that won't result in polluting | |
267 | * the information about previously queued, but not yet | |
268 | * delivered, faults. See also do_general_protection below. | |
269 | */ | |
270 | tsk->thread.error_code = error_code; | |
51e7dc70 | 271 | tsk->thread.trap_nr = trapnr; |
d1895183 | 272 | |
081f75bb AH |
273 | #ifdef CONFIG_X86_64 |
274 | if (show_unhandled_signals && unhandled_signal(tsk, signr) && | |
275 | printk_ratelimit()) { | |
c767a54b JP |
276 | pr_info("%s[%d] trap %s ip:%lx sp:%lx error:%lx", |
277 | tsk->comm, tsk->pid, str, | |
278 | regs->ip, regs->sp, error_code); | |
081f75bb | 279 | print_vma_addr(" in ", regs->ip); |
c767a54b | 280 | pr_cont("\n"); |
081f75bb AH |
281 | } |
282 | #endif | |
283 | ||
38cad57b | 284 | force_sig_info(signr, info ?: SEND_SIG_PRIV, tsk); |
1da177e4 | 285 | } |
9326638c | 286 | NOKPROBE_SYMBOL(do_trap); |
1da177e4 | 287 | |
dff0796e | 288 | static void do_error_trap(struct pt_regs *regs, long error_code, char *str, |
1c326c4d | 289 | unsigned long trapnr, int signr) |
dff0796e ON |
290 | { |
291 | enum ctx_state prev_state = exception_enter(); | |
1c326c4d | 292 | siginfo_t info; |
dff0796e ON |
293 | |
294 | if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) != | |
295 | NOTIFY_STOP) { | |
296 | conditional_sti(regs); | |
1c326c4d ON |
297 | do_trap(trapnr, signr, str, regs, error_code, |
298 | fill_trap_info(regs, signr, trapnr, &info)); | |
dff0796e ON |
299 | } |
300 | ||
301 | exception_exit(prev_state); | |
302 | } | |
303 | ||
b5964405 | 304 | #define DO_ERROR(trapnr, signr, str, name) \ |
e407d620 | 305 | dotraplinkage void do_##name(struct pt_regs *regs, long error_code) \ |
b5964405 | 306 | { \ |
1c326c4d | 307 | do_error_trap(regs, error_code, str, trapnr, signr); \ |
1da177e4 LT |
308 | } |
309 | ||
0eb14833 ON |
310 | DO_ERROR(X86_TRAP_DE, SIGFPE, "divide error", divide_error) |
311 | DO_ERROR(X86_TRAP_OF, SIGSEGV, "overflow", overflow) | |
0eb14833 ON |
312 | DO_ERROR(X86_TRAP_UD, SIGILL, "invalid opcode", invalid_op) |
313 | DO_ERROR(X86_TRAP_OLD_MF, SIGFPE, "coprocessor segment overrun",coprocessor_segment_overrun) | |
314 | DO_ERROR(X86_TRAP_TS, SIGSEGV, "invalid TSS", invalid_TSS) | |
315 | DO_ERROR(X86_TRAP_NP, SIGBUS, "segment not present", segment_not_present) | |
0eb14833 | 316 | DO_ERROR(X86_TRAP_SS, SIGBUS, "stack segment", stack_segment) |
0eb14833 | 317 | DO_ERROR(X86_TRAP_AC, SIGBUS, "alignment check", alignment_check) |
1da177e4 | 318 | |
081f75bb AH |
319 | #ifdef CONFIG_X86_64 |
320 | /* Runs on IST stack */ | |
081f75bb AH |
321 | dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code) |
322 | { | |
323 | static const char str[] = "double fault"; | |
324 | struct task_struct *tsk = current; | |
325 | ||
af726f21 AL |
326 | #ifdef CONFIG_X86_ESPFIX64 |
327 | extern unsigned char native_irq_return_iret[]; | |
328 | ||
329 | /* | |
330 | * If IRET takes a non-IST fault on the espfix64 stack, then we | |
331 | * end up promoting it to a doublefault. In that case, modify | |
332 | * the stack to make it look like we just entered the #GP | |
333 | * handler from user space, similar to bad_iret. | |
95927475 AL |
334 | * |
335 | * No need for ist_enter here because we don't use RCU. | |
af726f21 AL |
336 | */ |
337 | if (((long)regs->sp >> PGDIR_SHIFT) == ESPFIX_PGD_ENTRY && | |
338 | regs->cs == __KERNEL_CS && | |
339 | regs->ip == (unsigned long)native_irq_return_iret) | |
340 | { | |
341 | struct pt_regs *normal_regs = task_pt_regs(current); | |
342 | ||
343 | /* Fake a #GP(0) from userspace. */ | |
344 | memmove(&normal_regs->ip, (void *)regs->sp, 5*8); | |
345 | normal_regs->orig_ax = 0; /* Missing (lost) #GP error code */ | |
346 | regs->ip = (unsigned long)general_protection; | |
347 | regs->sp = (unsigned long)&normal_regs->orig_ax; | |
95927475 | 348 | |
af726f21 AL |
349 | return; |
350 | } | |
351 | #endif | |
352 | ||
95927475 | 353 | ist_enter(regs); /* Discard prev_state because we won't return. */ |
c9408265 | 354 | notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV); |
081f75bb AH |
355 | |
356 | tsk->thread.error_code = error_code; | |
51e7dc70 | 357 | tsk->thread.trap_nr = X86_TRAP_DF; |
081f75bb | 358 | |
4d067d8e BP |
359 | #ifdef CONFIG_DOUBLEFAULT |
360 | df_debug(regs, error_code); | |
361 | #endif | |
bd8b96df IM |
362 | /* |
363 | * This is always a kernel trap and never fixable (and thus must | |
364 | * never return). | |
365 | */ | |
081f75bb AH |
366 | for (;;) |
367 | die(str, regs, error_code); | |
368 | } | |
369 | #endif | |
370 | ||
fe3d197f DH |
371 | dotraplinkage void do_bounds(struct pt_regs *regs, long error_code) |
372 | { | |
373 | struct task_struct *tsk = current; | |
374 | struct xsave_struct *xsave_buf; | |
375 | enum ctx_state prev_state; | |
376 | struct bndcsr *bndcsr; | |
377 | siginfo_t *info; | |
378 | ||
379 | prev_state = exception_enter(); | |
380 | if (notify_die(DIE_TRAP, "bounds", regs, error_code, | |
381 | X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP) | |
382 | goto exit; | |
383 | conditional_sti(regs); | |
384 | ||
f39b6f0e | 385 | if (!user_mode(regs)) |
fe3d197f DH |
386 | die("bounds", regs, error_code); |
387 | ||
388 | if (!cpu_feature_enabled(X86_FEATURE_MPX)) { | |
389 | /* The exception is not from Intel MPX */ | |
390 | goto exit_trap; | |
391 | } | |
392 | ||
393 | /* | |
394 | * We need to look at BNDSTATUS to resolve this exception. | |
395 | * It is not directly accessible, though, so we need to | |
396 | * do an xsave and then pull it out of the xsave buffer. | |
397 | */ | |
4f836347 | 398 | copy_fpregs_to_fpstate(&tsk->thread.fpu); |
7366ed77 | 399 | xsave_buf = &(tsk->thread.fpu.state.xsave); |
fe3d197f DH |
400 | bndcsr = get_xsave_addr(xsave_buf, XSTATE_BNDCSR); |
401 | if (!bndcsr) | |
402 | goto exit_trap; | |
403 | ||
404 | /* | |
405 | * The error code field of the BNDSTATUS register communicates status | |
406 | * information of a bound range exception #BR or operation involving | |
407 | * bound directory. | |
408 | */ | |
409 | switch (bndcsr->bndstatus & MPX_BNDSTA_ERROR_CODE) { | |
410 | case 2: /* Bound directory has invalid entry. */ | |
411 | if (mpx_handle_bd_fault(xsave_buf)) | |
412 | goto exit_trap; | |
413 | break; /* Success, it was handled */ | |
414 | case 1: /* Bound violation. */ | |
415 | info = mpx_generate_siginfo(regs, xsave_buf); | |
e10abb2f | 416 | if (IS_ERR(info)) { |
fe3d197f DH |
417 | /* |
418 | * We failed to decode the MPX instruction. Act as if | |
419 | * the exception was not caused by MPX. | |
420 | */ | |
421 | goto exit_trap; | |
422 | } | |
423 | /* | |
424 | * Success, we decoded the instruction and retrieved | |
425 | * an 'info' containing the address being accessed | |
426 | * which caused the exception. This information | |
427 | * allows and application to possibly handle the | |
428 | * #BR exception itself. | |
429 | */ | |
430 | do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, info); | |
431 | kfree(info); | |
432 | break; | |
433 | case 0: /* No exception caused by Intel MPX operations. */ | |
434 | goto exit_trap; | |
435 | default: | |
436 | die("bounds", regs, error_code); | |
437 | } | |
438 | ||
439 | exit: | |
440 | exception_exit(prev_state); | |
441 | return; | |
442 | exit_trap: | |
443 | /* | |
444 | * This path out is for all the cases where we could not | |
445 | * handle the exception in some way (like allocating a | |
446 | * table or telling userspace about it. We will also end | |
447 | * up here if the kernel has MPX turned off at compile | |
448 | * time.. | |
449 | */ | |
450 | do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, NULL); | |
451 | exception_exit(prev_state); | |
452 | } | |
453 | ||
9326638c | 454 | dotraplinkage void |
13485ab5 | 455 | do_general_protection(struct pt_regs *regs, long error_code) |
1da177e4 | 456 | { |
13485ab5 | 457 | struct task_struct *tsk; |
6c1e0256 | 458 | enum ctx_state prev_state; |
b5964405 | 459 | |
6c1e0256 | 460 | prev_state = exception_enter(); |
c6df0d71 AH |
461 | conditional_sti(regs); |
462 | ||
d74ef111 | 463 | if (v8086_mode(regs)) { |
ef3f6288 FW |
464 | local_irq_enable(); |
465 | handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code); | |
6ba3c97a | 466 | goto exit; |
ef3f6288 | 467 | } |
1da177e4 | 468 | |
13485ab5 | 469 | tsk = current; |
55474c48 | 470 | if (!user_mode(regs)) { |
ef3f6288 | 471 | if (fixup_exception(regs)) |
6ba3c97a | 472 | goto exit; |
ef3f6288 FW |
473 | |
474 | tsk->thread.error_code = error_code; | |
475 | tsk->thread.trap_nr = X86_TRAP_GP; | |
6ba3c97a FW |
476 | if (notify_die(DIE_GPF, "general protection fault", regs, error_code, |
477 | X86_TRAP_GP, SIGSEGV) != NOTIFY_STOP) | |
ef3f6288 | 478 | die("general protection fault", regs, error_code); |
6ba3c97a | 479 | goto exit; |
ef3f6288 | 480 | } |
1da177e4 | 481 | |
13485ab5 | 482 | tsk->thread.error_code = error_code; |
51e7dc70 | 483 | tsk->thread.trap_nr = X86_TRAP_GP; |
b5964405 | 484 | |
13485ab5 AH |
485 | if (show_unhandled_signals && unhandled_signal(tsk, SIGSEGV) && |
486 | printk_ratelimit()) { | |
c767a54b | 487 | pr_info("%s[%d] general protection ip:%lx sp:%lx error:%lx", |
13485ab5 AH |
488 | tsk->comm, task_pid_nr(tsk), |
489 | regs->ip, regs->sp, error_code); | |
03252919 | 490 | print_vma_addr(" in ", regs->ip); |
c767a54b | 491 | pr_cont("\n"); |
03252919 | 492 | } |
abd4f750 | 493 | |
38cad57b | 494 | force_sig_info(SIGSEGV, SEND_SIG_PRIV, tsk); |
6ba3c97a | 495 | exit: |
6c1e0256 | 496 | exception_exit(prev_state); |
1da177e4 | 497 | } |
9326638c | 498 | NOKPROBE_SYMBOL(do_general_protection); |
1da177e4 | 499 | |
c1d518c8 | 500 | /* May run on IST stack. */ |
9326638c | 501 | dotraplinkage void notrace do_int3(struct pt_regs *regs, long error_code) |
1da177e4 | 502 | { |
6c1e0256 FW |
503 | enum ctx_state prev_state; |
504 | ||
08d636b6 | 505 | #ifdef CONFIG_DYNAMIC_FTRACE |
a192cd04 SR |
506 | /* |
507 | * ftrace must be first, everything else may cause a recursive crash. | |
508 | * See note by declaration of modifying_ftrace_code in ftrace.c | |
509 | */ | |
510 | if (unlikely(atomic_read(&modifying_ftrace_code)) && | |
511 | ftrace_int3_handler(regs)) | |
08d636b6 SR |
512 | return; |
513 | #endif | |
17f41571 JK |
514 | if (poke_int3_handler(regs)) |
515 | return; | |
516 | ||
95927475 | 517 | prev_state = ist_enter(regs); |
f503b5ae | 518 | #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP |
c9408265 KC |
519 | if (kgdb_ll_trap(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP, |
520 | SIGTRAP) == NOTIFY_STOP) | |
6ba3c97a | 521 | goto exit; |
f503b5ae | 522 | #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ |
cc3a1bf5 | 523 | |
6f6343f5 MH |
524 | #ifdef CONFIG_KPROBES |
525 | if (kprobe_int3_handler(regs)) | |
4cdf77a8 | 526 | goto exit; |
6f6343f5 MH |
527 | #endif |
528 | ||
c9408265 KC |
529 | if (notify_die(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP, |
530 | SIGTRAP) == NOTIFY_STOP) | |
6ba3c97a | 531 | goto exit; |
b5964405 | 532 | |
42181186 SR |
533 | /* |
534 | * Let others (NMI) know that the debug stack is in use | |
535 | * as we may switch to the interrupt stack. | |
536 | */ | |
537 | debug_stack_usage_inc(); | |
4915a35e | 538 | preempt_conditional_sti(regs); |
c9408265 | 539 | do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, error_code, NULL); |
4915a35e | 540 | preempt_conditional_cli(regs); |
42181186 | 541 | debug_stack_usage_dec(); |
6ba3c97a | 542 | exit: |
95927475 | 543 | ist_exit(regs, prev_state); |
1da177e4 | 544 | } |
9326638c | 545 | NOKPROBE_SYMBOL(do_int3); |
1da177e4 | 546 | |
081f75bb | 547 | #ifdef CONFIG_X86_64 |
bd8b96df | 548 | /* |
48e08d0f AL |
549 | * Help handler running on IST stack to switch off the IST stack if the |
550 | * interrupted code was in user mode. The actual stack switch is done in | |
551 | * entry_64.S | |
bd8b96df | 552 | */ |
7ddc6a21 | 553 | asmlinkage __visible notrace struct pt_regs *sync_regs(struct pt_regs *eregs) |
081f75bb | 554 | { |
48e08d0f AL |
555 | struct pt_regs *regs = task_pt_regs(current); |
556 | *regs = *eregs; | |
081f75bb AH |
557 | return regs; |
558 | } | |
9326638c | 559 | NOKPROBE_SYMBOL(sync_regs); |
b645af2d AL |
560 | |
561 | struct bad_iret_stack { | |
562 | void *error_entry_ret; | |
563 | struct pt_regs regs; | |
564 | }; | |
565 | ||
7ddc6a21 | 566 | asmlinkage __visible notrace |
b645af2d AL |
567 | struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s) |
568 | { | |
569 | /* | |
570 | * This is called from entry_64.S early in handling a fault | |
571 | * caused by a bad iret to user mode. To handle the fault | |
572 | * correctly, we want move our stack frame to task_pt_regs | |
573 | * and we want to pretend that the exception came from the | |
574 | * iret target. | |
575 | */ | |
576 | struct bad_iret_stack *new_stack = | |
577 | container_of(task_pt_regs(current), | |
578 | struct bad_iret_stack, regs); | |
579 | ||
580 | /* Copy the IRET target to the new stack. */ | |
581 | memmove(&new_stack->regs.ip, (void *)s->regs.sp, 5*8); | |
582 | ||
583 | /* Copy the remainder of the stack from the current stack. */ | |
584 | memmove(new_stack, s, offsetof(struct bad_iret_stack, regs.ip)); | |
585 | ||
f39b6f0e | 586 | BUG_ON(!user_mode(&new_stack->regs)); |
b645af2d AL |
587 | return new_stack; |
588 | } | |
7ddc6a21 | 589 | NOKPROBE_SYMBOL(fixup_bad_iret); |
081f75bb AH |
590 | #endif |
591 | ||
1da177e4 LT |
592 | /* |
593 | * Our handling of the processor debug registers is non-trivial. | |
594 | * We do not clear them on entry and exit from the kernel. Therefore | |
595 | * it is possible to get a watchpoint trap here from inside the kernel. | |
596 | * However, the code in ./ptrace.c has ensured that the user can | |
597 | * only set watchpoints on userspace addresses. Therefore the in-kernel | |
598 | * watchpoint trap can only occur in code which is reading/writing | |
599 | * from user space. Such code must not hold kernel locks (since it | |
600 | * can equally take a page fault), therefore it is safe to call | |
601 | * force_sig_info even though that claims and releases locks. | |
b5964405 | 602 | * |
1da177e4 LT |
603 | * Code in ./signal.c ensures that the debug control register |
604 | * is restored before we deliver any signal, and therefore that | |
605 | * user code runs with the correct debug control register even though | |
606 | * we clear it here. | |
607 | * | |
608 | * Being careful here means that we don't have to be as careful in a | |
609 | * lot of more complicated places (task switching can be a bit lazy | |
610 | * about restoring all the debug state, and ptrace doesn't have to | |
611 | * find every occurrence of the TF bit that could be saved away even | |
612 | * by user code) | |
c1d518c8 AH |
613 | * |
614 | * May run on IST stack. | |
1da177e4 | 615 | */ |
9326638c | 616 | dotraplinkage void do_debug(struct pt_regs *regs, long error_code) |
1da177e4 | 617 | { |
1da177e4 | 618 | struct task_struct *tsk = current; |
6c1e0256 | 619 | enum ctx_state prev_state; |
a1e80faf | 620 | int user_icebp = 0; |
08d68323 | 621 | unsigned long dr6; |
da654b74 | 622 | int si_code; |
1da177e4 | 623 | |
95927475 | 624 | prev_state = ist_enter(regs); |
4cdf77a8 | 625 | |
08d68323 | 626 | get_debugreg(dr6, 6); |
1da177e4 | 627 | |
40f9249a P |
628 | /* Filter out all the reserved bits which are preset to 1 */ |
629 | dr6 &= ~DR6_RESERVED; | |
630 | ||
a1e80faf FW |
631 | /* |
632 | * If dr6 has no reason to give us about the origin of this trap, | |
633 | * then it's very likely the result of an icebp/int01 trap. | |
634 | * User wants a sigtrap for that. | |
635 | */ | |
f39b6f0e | 636 | if (!dr6 && user_mode(regs)) |
a1e80faf FW |
637 | user_icebp = 1; |
638 | ||
f8561296 | 639 | /* Catch kmemcheck conditions first of all! */ |
eadb8a09 | 640 | if ((dr6 & DR_STEP) && kmemcheck_trap(regs)) |
6ba3c97a | 641 | goto exit; |
f8561296 | 642 | |
08d68323 P |
643 | /* DR6 may or may not be cleared by the CPU */ |
644 | set_debugreg(0, 6); | |
10faa81e | 645 | |
ea8e61b7 PZ |
646 | /* |
647 | * The processor cleared BTF, so don't mark that we need it set. | |
648 | */ | |
649 | clear_tsk_thread_flag(tsk, TIF_BLOCKSTEP); | |
650 | ||
08d68323 P |
651 | /* Store the virtualized DR6 value */ |
652 | tsk->thread.debugreg6 = dr6; | |
653 | ||
6f6343f5 MH |
654 | #ifdef CONFIG_KPROBES |
655 | if (kprobe_debug_handler(regs)) | |
656 | goto exit; | |
657 | #endif | |
658 | ||
5a802e15 | 659 | if (notify_die(DIE_DEBUG, "debug", regs, (long)&dr6, error_code, |
62edab90 | 660 | SIGTRAP) == NOTIFY_STOP) |
6ba3c97a | 661 | goto exit; |
3d2a71a5 | 662 | |
42181186 SR |
663 | /* |
664 | * Let others (NMI) know that the debug stack is in use | |
665 | * as we may switch to the interrupt stack. | |
666 | */ | |
667 | debug_stack_usage_inc(); | |
668 | ||
1da177e4 | 669 | /* It's safe to allow irq's after DR6 has been saved */ |
3d2a71a5 | 670 | preempt_conditional_sti(regs); |
1da177e4 | 671 | |
d74ef111 | 672 | if (v8086_mode(regs)) { |
c9408265 KC |
673 | handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code, |
674 | X86_TRAP_DB); | |
6554287b | 675 | preempt_conditional_cli(regs); |
42181186 | 676 | debug_stack_usage_dec(); |
6ba3c97a | 677 | goto exit; |
1da177e4 LT |
678 | } |
679 | ||
1da177e4 | 680 | /* |
08d68323 P |
681 | * Single-stepping through system calls: ignore any exceptions in |
682 | * kernel space, but re-enable TF when returning to user mode. | |
683 | * | |
684 | * We already checked v86 mode above, so we can check for kernel mode | |
685 | * by just checking the CPL of CS. | |
1da177e4 | 686 | */ |
55474c48 | 687 | if ((dr6 & DR_STEP) && !user_mode(regs)) { |
08d68323 P |
688 | tsk->thread.debugreg6 &= ~DR_STEP; |
689 | set_tsk_thread_flag(tsk, TIF_SINGLESTEP); | |
690 | regs->flags &= ~X86_EFLAGS_TF; | |
1da177e4 | 691 | } |
08d68323 | 692 | si_code = get_si_code(tsk->thread.debugreg6); |
a1e80faf | 693 | if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS) || user_icebp) |
08d68323 | 694 | send_sigtrap(tsk, regs, error_code, si_code); |
3d2a71a5 | 695 | preempt_conditional_cli(regs); |
42181186 | 696 | debug_stack_usage_dec(); |
1da177e4 | 697 | |
6ba3c97a | 698 | exit: |
95927475 | 699 | ist_exit(regs, prev_state); |
1da177e4 | 700 | } |
9326638c | 701 | NOKPROBE_SYMBOL(do_debug); |
1da177e4 LT |
702 | |
703 | /* | |
704 | * Note that we play around with the 'TS' bit in an attempt to get | |
705 | * the correct behaviour even in the presence of the asynchronous | |
706 | * IRQ13 behaviour | |
707 | */ | |
5e1b05be | 708 | static void math_error(struct pt_regs *regs, int error_code, int trapnr) |
1da177e4 | 709 | { |
e2e75c91 | 710 | struct task_struct *task = current; |
1da177e4 | 711 | siginfo_t info; |
9b6dba9e | 712 | unsigned short err; |
c9408265 KC |
713 | char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" : |
714 | "simd exception"; | |
e2e75c91 BG |
715 | |
716 | if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, SIGFPE) == NOTIFY_STOP) | |
717 | return; | |
718 | conditional_sti(regs); | |
719 | ||
f39b6f0e | 720 | if (!user_mode(regs)) |
e2e75c91 BG |
721 | { |
722 | if (!fixup_exception(regs)) { | |
723 | task->thread.error_code = error_code; | |
51e7dc70 | 724 | task->thread.trap_nr = trapnr; |
e2e75c91 BG |
725 | die(str, regs, error_code); |
726 | } | |
727 | return; | |
728 | } | |
1da177e4 LT |
729 | |
730 | /* | |
731 | * Save the info for the exception handler and clear the error. | |
732 | */ | |
0c070595 | 733 | fpu__save(&task->thread.fpu); |
51e7dc70 | 734 | task->thread.trap_nr = trapnr; |
9b6dba9e | 735 | task->thread.error_code = error_code; |
1da177e4 LT |
736 | info.si_signo = SIGFPE; |
737 | info.si_errno = 0; | |
b02ef20a | 738 | info.si_addr = (void __user *)uprobe_get_trap_addr(regs); |
c9408265 | 739 | if (trapnr == X86_TRAP_MF) { |
9b6dba9e BG |
740 | unsigned short cwd, swd; |
741 | /* | |
742 | * (~cwd & swd) will mask out exceptions that are not set to unmasked | |
743 | * status. 0x3f is the exception bits in these regs, 0x200 is the | |
744 | * C1 reg you need in case of a stack fault, 0x040 is the stack | |
745 | * fault bit. We should only be taking one exception at a time, | |
746 | * so if this combination doesn't produce any single exception, | |
747 | * then we have a bad program that isn't synchronizing its FPU usage | |
748 | * and it will suffer the consequences since we won't be able to | |
749 | * fully reproduce the context of the exception | |
750 | */ | |
751 | cwd = get_fpu_cwd(task); | |
752 | swd = get_fpu_swd(task); | |
adf77bac | 753 | |
9b6dba9e BG |
754 | err = swd & ~cwd; |
755 | } else { | |
756 | /* | |
757 | * The SIMD FPU exceptions are handled a little differently, as there | |
758 | * is only a single status/control register. Thus, to determine which | |
759 | * unmasked exception was caught we must mask the exception mask bits | |
760 | * at 0x1f80, and then use these to mask the exception bits at 0x3f. | |
761 | */ | |
762 | unsigned short mxcsr = get_fpu_mxcsr(task); | |
763 | err = ~(mxcsr >> 7) & mxcsr; | |
764 | } | |
adf77bac PA |
765 | |
766 | if (err & 0x001) { /* Invalid op */ | |
b5964405 IM |
767 | /* |
768 | * swd & 0x240 == 0x040: Stack Underflow | |
769 | * swd & 0x240 == 0x240: Stack Overflow | |
770 | * User must clear the SF bit (0x40) if set | |
771 | */ | |
772 | info.si_code = FPE_FLTINV; | |
adf77bac | 773 | } else if (err & 0x004) { /* Divide by Zero */ |
b5964405 | 774 | info.si_code = FPE_FLTDIV; |
adf77bac | 775 | } else if (err & 0x008) { /* Overflow */ |
b5964405 | 776 | info.si_code = FPE_FLTOVF; |
adf77bac PA |
777 | } else if (err & 0x012) { /* Denormal, Underflow */ |
778 | info.si_code = FPE_FLTUND; | |
779 | } else if (err & 0x020) { /* Precision */ | |
b5964405 | 780 | info.si_code = FPE_FLTRES; |
adf77bac | 781 | } else { |
bd8b96df | 782 | /* |
c9408265 KC |
783 | * If we're using IRQ 13, or supposedly even some trap |
784 | * X86_TRAP_MF implementations, it's possible | |
785 | * we get a spurious trap, which is not an error. | |
bd8b96df | 786 | */ |
c9408265 | 787 | return; |
1da177e4 LT |
788 | } |
789 | force_sig_info(SIGFPE, &info, task); | |
790 | } | |
791 | ||
e407d620 | 792 | dotraplinkage void do_coprocessor_error(struct pt_regs *regs, long error_code) |
1da177e4 | 793 | { |
6c1e0256 FW |
794 | enum ctx_state prev_state; |
795 | ||
796 | prev_state = exception_enter(); | |
c9408265 | 797 | math_error(regs, error_code, X86_TRAP_MF); |
6c1e0256 | 798 | exception_exit(prev_state); |
1da177e4 LT |
799 | } |
800 | ||
e407d620 AH |
801 | dotraplinkage void |
802 | do_simd_coprocessor_error(struct pt_regs *regs, long error_code) | |
1da177e4 | 803 | { |
6c1e0256 FW |
804 | enum ctx_state prev_state; |
805 | ||
806 | prev_state = exception_enter(); | |
c9408265 | 807 | math_error(regs, error_code, X86_TRAP_XF); |
6c1e0256 | 808 | exception_exit(prev_state); |
1da177e4 LT |
809 | } |
810 | ||
e407d620 AH |
811 | dotraplinkage void |
812 | do_spurious_interrupt_bug(struct pt_regs *regs, long error_code) | |
1da177e4 | 813 | { |
cf81978d | 814 | conditional_sti(regs); |
1da177e4 LT |
815 | #if 0 |
816 | /* No need to warn about this any longer. */ | |
c767a54b | 817 | pr_info("Ignoring P6 Local APIC Spurious Interrupt Bug...\n"); |
1da177e4 LT |
818 | #endif |
819 | } | |
820 | ||
2605fc21 | 821 | asmlinkage __visible void __attribute__((weak)) smp_thermal_interrupt(void) |
1da177e4 | 822 | { |
1da177e4 | 823 | } |
4efc0670 | 824 | |
2605fc21 | 825 | asmlinkage __visible void __attribute__((weak)) smp_threshold_interrupt(void) |
081f75bb AH |
826 | { |
827 | } | |
828 | ||
9326638c | 829 | dotraplinkage void |
aa78bcfa | 830 | do_device_not_available(struct pt_regs *regs, long error_code) |
7643e9b9 | 831 | { |
6c1e0256 FW |
832 | enum ctx_state prev_state; |
833 | ||
834 | prev_state = exception_enter(); | |
5d2bd700 | 835 | BUG_ON(use_eager_fpu()); |
304bceda | 836 | |
a334fe43 | 837 | #ifdef CONFIG_MATH_EMULATION |
7643e9b9 | 838 | if (read_cr0() & X86_CR0_EM) { |
d315760f TH |
839 | struct math_emu_info info = { }; |
840 | ||
7643e9b9 | 841 | conditional_sti(regs); |
d315760f | 842 | |
aa78bcfa | 843 | info.regs = regs; |
d315760f | 844 | math_emulate(&info); |
6c1e0256 | 845 | exception_exit(prev_state); |
a334fe43 | 846 | return; |
7643e9b9 | 847 | } |
a334fe43 | 848 | #endif |
3a0aee48 | 849 | fpu__restore(); /* interrupts still off */ |
a334fe43 BG |
850 | #ifdef CONFIG_X86_32 |
851 | conditional_sti(regs); | |
081f75bb | 852 | #endif |
6c1e0256 | 853 | exception_exit(prev_state); |
7643e9b9 | 854 | } |
9326638c | 855 | NOKPROBE_SYMBOL(do_device_not_available); |
7643e9b9 | 856 | |
081f75bb | 857 | #ifdef CONFIG_X86_32 |
e407d620 | 858 | dotraplinkage void do_iret_error(struct pt_regs *regs, long error_code) |
f8e0870f AH |
859 | { |
860 | siginfo_t info; | |
6c1e0256 | 861 | enum ctx_state prev_state; |
6ba3c97a | 862 | |
6c1e0256 | 863 | prev_state = exception_enter(); |
f8e0870f AH |
864 | local_irq_enable(); |
865 | ||
866 | info.si_signo = SIGILL; | |
867 | info.si_errno = 0; | |
868 | info.si_code = ILL_BADSTK; | |
fc6fcdfb | 869 | info.si_addr = NULL; |
c9408265 | 870 | if (notify_die(DIE_TRAP, "iret exception", regs, error_code, |
6ba3c97a FW |
871 | X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) { |
872 | do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, error_code, | |
873 | &info); | |
874 | } | |
6c1e0256 | 875 | exception_exit(prev_state); |
f8e0870f | 876 | } |
081f75bb | 877 | #endif |
f8e0870f | 878 | |
29c84391 JK |
879 | /* Set of traps needed for early debugging. */ |
880 | void __init early_trap_init(void) | |
881 | { | |
b4d83270 | 882 | /* |
5eca7453 WN |
883 | * Don't use IST to set DEBUG_STACK as it doesn't work until TSS |
884 | * is ready in cpu_init() <-- trap_init(). Before trap_init(), | |
885 | * CPU runs at ring 0 so it is impossible to hit an invalid | |
886 | * stack. Using the original stack works well enough at this | |
887 | * early stage. DEBUG_STACK will be equipped after cpu_init() in | |
b4d83270 | 888 | * trap_init(). |
5eca7453 WN |
889 | * |
890 | * We don't need to set trace_idt_table like set_intr_gate(), | |
891 | * since we don't have trace_debug and it will be reset to | |
892 | * 'debug' in trap_init() by set_intr_gate_ist(). | |
b4d83270 | 893 | */ |
5eca7453 | 894 | set_intr_gate_notrace(X86_TRAP_DB, debug); |
29c84391 | 895 | /* int3 can be called from all */ |
5eca7453 | 896 | set_system_intr_gate(X86_TRAP_BP, &int3); |
8170e6be | 897 | #ifdef CONFIG_X86_32 |
25c74b10 | 898 | set_intr_gate(X86_TRAP_PF, page_fault); |
8170e6be | 899 | #endif |
29c84391 JK |
900 | load_idt(&idt_descr); |
901 | } | |
902 | ||
8170e6be PA |
903 | void __init early_trap_pf_init(void) |
904 | { | |
905 | #ifdef CONFIG_X86_64 | |
25c74b10 | 906 | set_intr_gate(X86_TRAP_PF, page_fault); |
8170e6be PA |
907 | #endif |
908 | } | |
909 | ||
1da177e4 LT |
910 | void __init trap_init(void) |
911 | { | |
dbeb2be2 RR |
912 | int i; |
913 | ||
1da177e4 | 914 | #ifdef CONFIG_EISA |
927222b1 | 915 | void __iomem *p = early_ioremap(0x0FFFD9, 4); |
b5964405 IM |
916 | |
917 | if (readl(p) == 'E' + ('I'<<8) + ('S'<<16) + ('A'<<24)) | |
1da177e4 | 918 | EISA_bus = 1; |
927222b1 | 919 | early_iounmap(p, 4); |
1da177e4 LT |
920 | #endif |
921 | ||
25c74b10 | 922 | set_intr_gate(X86_TRAP_DE, divide_error); |
c9408265 | 923 | set_intr_gate_ist(X86_TRAP_NMI, &nmi, NMI_STACK); |
699d2937 | 924 | /* int4 can be called from all */ |
c9408265 | 925 | set_system_intr_gate(X86_TRAP_OF, &overflow); |
25c74b10 SA |
926 | set_intr_gate(X86_TRAP_BR, bounds); |
927 | set_intr_gate(X86_TRAP_UD, invalid_op); | |
928 | set_intr_gate(X86_TRAP_NM, device_not_available); | |
081f75bb | 929 | #ifdef CONFIG_X86_32 |
c9408265 | 930 | set_task_gate(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS); |
081f75bb | 931 | #else |
c9408265 | 932 | set_intr_gate_ist(X86_TRAP_DF, &double_fault, DOUBLEFAULT_STACK); |
081f75bb | 933 | #endif |
25c74b10 SA |
934 | set_intr_gate(X86_TRAP_OLD_MF, coprocessor_segment_overrun); |
935 | set_intr_gate(X86_TRAP_TS, invalid_TSS); | |
936 | set_intr_gate(X86_TRAP_NP, segment_not_present); | |
6f442be2 | 937 | set_intr_gate(X86_TRAP_SS, stack_segment); |
25c74b10 SA |
938 | set_intr_gate(X86_TRAP_GP, general_protection); |
939 | set_intr_gate(X86_TRAP_SPURIOUS, spurious_interrupt_bug); | |
940 | set_intr_gate(X86_TRAP_MF, coprocessor_error); | |
941 | set_intr_gate(X86_TRAP_AC, alignment_check); | |
1da177e4 | 942 | #ifdef CONFIG_X86_MCE |
c9408265 | 943 | set_intr_gate_ist(X86_TRAP_MC, &machine_check, MCE_STACK); |
1da177e4 | 944 | #endif |
25c74b10 | 945 | set_intr_gate(X86_TRAP_XF, simd_coprocessor_error); |
1da177e4 | 946 | |
bb3f0b59 YL |
947 | /* Reserve all the builtin and the syscall vector: */ |
948 | for (i = 0; i < FIRST_EXTERNAL_VECTOR; i++) | |
949 | set_bit(i, used_vectors); | |
950 | ||
081f75bb AH |
951 | #ifdef CONFIG_IA32_EMULATION |
952 | set_system_intr_gate(IA32_SYSCALL_VECTOR, ia32_syscall); | |
bb3f0b59 | 953 | set_bit(IA32_SYSCALL_VECTOR, used_vectors); |
081f75bb AH |
954 | #endif |
955 | ||
956 | #ifdef CONFIG_X86_32 | |
699d2937 | 957 | set_system_trap_gate(SYSCALL_VECTOR, &system_call); |
dbeb2be2 | 958 | set_bit(SYSCALL_VECTOR, used_vectors); |
081f75bb | 959 | #endif |
bb3f0b59 | 960 | |
4eefbe79 KC |
961 | /* |
962 | * Set the IDT descriptor to a fixed read-only location, so that the | |
963 | * "sidt" instruction will not leak the location of the kernel, and | |
964 | * to defend the IDT against arbitrary memory write vulnerabilities. | |
965 | * It will be reloaded in cpu_init() */ | |
966 | __set_fixmap(FIX_RO_IDT, __pa_symbol(idt_table), PAGE_KERNEL_RO); | |
967 | idt_descr.address = fix_to_virt(FIX_RO_IDT); | |
968 | ||
1da177e4 | 969 | /* |
b5964405 | 970 | * Should be a barrier for any external CPU state: |
1da177e4 LT |
971 | */ |
972 | cpu_init(); | |
973 | ||
b4d83270 WN |
974 | /* |
975 | * X86_TRAP_DB and X86_TRAP_BP have been set | |
5eca7453 | 976 | * in early_trap_init(). However, ITS works only after |
b4d83270 WN |
977 | * cpu_init() loads TSS. See comments in early_trap_init(). |
978 | */ | |
979 | set_intr_gate_ist(X86_TRAP_DB, &debug, DEBUG_STACK); | |
980 | /* int3 can be called from all */ | |
981 | set_system_intr_gate_ist(X86_TRAP_BP, &int3, DEBUG_STACK); | |
982 | ||
428cf902 | 983 | x86_init.irqs.trap_init(); |
228bdaa9 SR |
984 | |
985 | #ifdef CONFIG_X86_64 | |
629f4f9d | 986 | memcpy(&debug_idt_table, &idt_table, IDT_ENTRIES * 16); |
c9408265 KC |
987 | set_nmi_gate(X86_TRAP_DB, &debug); |
988 | set_nmi_gate(X86_TRAP_BP, &int3); | |
228bdaa9 | 989 | #endif |
1da177e4 | 990 | } |