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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
26 | #if PTTYPE == 64 | |
27 | #define pt_element_t u64 | |
28 | #define guest_walker guest_walker64 | |
29 | #define FNAME(name) paging##64_##name | |
30 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
31 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
32 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 33 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
c7addb90 | 34 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
cea0f0e7 AK |
35 | #ifdef CONFIG_X86_64 |
36 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 37 | #define CMPXCHG cmpxchg |
cea0f0e7 | 38 | #else |
b3e4e63f | 39 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
40 | #define PT_MAX_FULL_LEVELS 2 |
41 | #endif | |
6aa8b732 AK |
42 | #elif PTTYPE == 32 |
43 | #define pt_element_t u32 | |
44 | #define guest_walker guest_walker32 | |
45 | #define FNAME(name) paging##32_##name | |
46 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
47 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
48 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 49 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
c7addb90 | 50 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 51 | #define PT_MAX_FULL_LEVELS 2 |
b3e4e63f | 52 | #define CMPXCHG cmpxchg |
6aa8b732 AK |
53 | #else |
54 | #error Invalid PTTYPE value | |
55 | #endif | |
56 | ||
e04da980 JR |
57 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
58 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 59 | |
6aa8b732 AK |
60 | /* |
61 | * The guest_walker structure emulates the behavior of the hardware page | |
62 | * table walker. | |
63 | */ | |
64 | struct guest_walker { | |
65 | int level; | |
8cbc7069 | 66 | unsigned max_level; |
cea0f0e7 | 67 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 68 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 69 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 70 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
8cbc7069 | 71 | pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
72 | unsigned pt_access; |
73 | unsigned pte_access; | |
815af8d4 | 74 | gfn_t gfn; |
8c28d031 | 75 | struct x86_exception fault; |
6aa8b732 AK |
76 | }; |
77 | ||
e04da980 | 78 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 79 | { |
e04da980 | 80 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
81 | } |
82 | ||
a78484c6 | 83 | static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
c8cfbb55 TY |
84 | pt_element_t __user *ptep_user, unsigned index, |
85 | pt_element_t orig_pte, pt_element_t new_pte) | |
b3e4e63f | 86 | { |
c8cfbb55 | 87 | int npages; |
b3e4e63f MT |
88 | pt_element_t ret; |
89 | pt_element_t *table; | |
90 | struct page *page; | |
91 | ||
c8cfbb55 TY |
92 | npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page); |
93 | /* Check if the user is doing something meaningless. */ | |
94 | if (unlikely(npages != 1)) | |
a78484c6 RJ |
95 | return -EFAULT; |
96 | ||
8fd75e12 | 97 | table = kmap_atomic(page); |
b3e4e63f | 98 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
8fd75e12 | 99 | kunmap_atomic(table); |
b3e4e63f MT |
100 | |
101 | kvm_release_page_dirty(page); | |
102 | ||
103 | return (ret != orig_pte); | |
104 | } | |
105 | ||
8cbc7069 AK |
106 | static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu, |
107 | struct kvm_mmu *mmu, | |
108 | struct guest_walker *walker, | |
109 | int write_fault) | |
110 | { | |
111 | unsigned level, index; | |
112 | pt_element_t pte, orig_pte; | |
113 | pt_element_t __user *ptep_user; | |
114 | gfn_t table_gfn; | |
115 | int ret; | |
116 | ||
117 | for (level = walker->max_level; level >= walker->level; --level) { | |
118 | pte = orig_pte = walker->ptes[level - 1]; | |
119 | table_gfn = walker->table_gfn[level - 1]; | |
120 | ptep_user = walker->ptep_user[level - 1]; | |
121 | index = offset_in_page(ptep_user) / sizeof(pt_element_t); | |
122 | if (!(pte & PT_ACCESSED_MASK)) { | |
123 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte)); | |
124 | pte |= PT_ACCESSED_MASK; | |
125 | } | |
126 | if (level == walker->level && write_fault && !is_dirty_gpte(pte)) { | |
127 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); | |
128 | pte |= PT_DIRTY_MASK; | |
129 | } | |
130 | if (pte == orig_pte) | |
131 | continue; | |
132 | ||
133 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte); | |
134 | if (ret) | |
135 | return ret; | |
136 | ||
137 | mark_page_dirty(vcpu->kvm, table_gfn); | |
138 | walker->ptes[level] = pte; | |
139 | } | |
140 | return 0; | |
141 | } | |
142 | ||
ac79c978 AK |
143 | /* |
144 | * Fetch a guest pte for a guest virtual address | |
145 | */ | |
1e301feb JR |
146 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
147 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
33770780 | 148 | gva_t addr, u32 access) |
6aa8b732 | 149 | { |
8cbc7069 | 150 | int ret; |
42bf3f0a | 151 | pt_element_t pte; |
b7233635 | 152 | pt_element_t __user *uninitialized_var(ptep_user); |
cea0f0e7 | 153 | gfn_t table_gfn; |
b0cfeb5d | 154 | unsigned index, pt_access, pte_access, accessed_dirty; |
42bf3f0a | 155 | gpa_t pte_gpa; |
134291bf TY |
156 | int offset; |
157 | const int write_fault = access & PFERR_WRITE_MASK; | |
158 | const int user_fault = access & PFERR_USER_MASK; | |
159 | const int fetch_fault = access & PFERR_FETCH_MASK; | |
160 | u16 errcode = 0; | |
13d22b6a AK |
161 | gpa_t real_gpa; |
162 | gfn_t gfn; | |
6aa8b732 | 163 | |
6fbc2770 | 164 | trace_kvm_mmu_pagetable_walk(addr, access); |
92c1c1e8 | 165 | retry_walk: |
1e301feb JR |
166 | walker->level = mmu->root_level; |
167 | pte = mmu->get_cr3(vcpu); | |
168 | ||
1b0973bd | 169 | #if PTTYPE == 64 |
1e301feb | 170 | if (walker->level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 171 | pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3); |
07420171 | 172 | trace_kvm_mmu_paging_element(pte, walker->level); |
134291bf | 173 | if (!is_present_gpte(pte)) |
f59c1d2d | 174 | goto error; |
1b0973bd AK |
175 | --walker->level; |
176 | } | |
177 | #endif | |
8cbc7069 | 178 | walker->max_level = walker->level; |
a9058ecd | 179 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
1e301feb | 180 | (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 181 | |
b514c30f | 182 | accessed_dirty = PT_ACCESSED_MASK; |
13d22b6a AK |
183 | pt_access = pte_access = ACC_ALL; |
184 | ++walker->level; | |
ac79c978 | 185 | |
13d22b6a | 186 | do { |
6e2ca7d1 TY |
187 | gfn_t real_gfn; |
188 | unsigned long host_addr; | |
189 | ||
13d22b6a AK |
190 | pt_access &= pte_access; |
191 | --walker->level; | |
192 | ||
42bf3f0a | 193 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 194 | |
5fb07ddb | 195 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
196 | offset = index * sizeof(pt_element_t); |
197 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
42bf3f0a | 198 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 199 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 200 | |
6e2ca7d1 TY |
201 | real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn), |
202 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
134291bf TY |
203 | if (unlikely(real_gfn == UNMAPPED_GVA)) |
204 | goto error; | |
6e2ca7d1 TY |
205 | real_gfn = gpa_to_gfn(real_gfn); |
206 | ||
207 | host_addr = gfn_to_hva(vcpu->kvm, real_gfn); | |
134291bf TY |
208 | if (unlikely(kvm_is_error_hva(host_addr))) |
209 | goto error; | |
6e2ca7d1 TY |
210 | |
211 | ptep_user = (pt_element_t __user *)((void *)host_addr + offset); | |
134291bf TY |
212 | if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte)))) |
213 | goto error; | |
8cbc7069 | 214 | walker->ptep_user[walker->level - 1] = ptep_user; |
a6085fba | 215 | |
07420171 | 216 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 217 | |
134291bf TY |
218 | if (unlikely(!is_present_gpte(pte))) |
219 | goto error; | |
7993ba43 | 220 | |
781e0743 AK |
221 | if (unlikely(is_rsvd_bits_set(&vcpu->arch.mmu, pte, |
222 | walker->level))) { | |
134291bf TY |
223 | errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK; |
224 | goto error; | |
f59c1d2d | 225 | } |
82725b20 | 226 | |
b514c30f | 227 | accessed_dirty &= pte; |
97d64b78 | 228 | pte_access = pt_access & gpte_access(vcpu, pte); |
73b1087e | 229 | |
7819026e | 230 | walker->ptes[walker->level - 1] = pte; |
6fd01b71 | 231 | } while (!is_last_gpte(mmu, walker->level, pte)); |
42bf3f0a | 232 | |
71331a1d | 233 | if (unlikely(permission_fault(mmu, pte_access, access))) { |
134291bf | 234 | errcode |= PFERR_PRESENT_MASK; |
f59c1d2d | 235 | goto error; |
134291bf | 236 | } |
f59c1d2d | 237 | |
13d22b6a AK |
238 | gfn = gpte_to_gfn_lvl(pte, walker->level); |
239 | gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT; | |
240 | ||
241 | if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36()) | |
242 | gfn += pse36_gfn_delta(pte); | |
243 | ||
c5421519 | 244 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access); |
13d22b6a AK |
245 | if (real_gpa == UNMAPPED_GVA) |
246 | return 0; | |
247 | ||
248 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
249 | ||
8ea667f2 AK |
250 | if (!write_fault) |
251 | protect_clean_gpte(&pte_access, pte); | |
908e7d79 GN |
252 | else |
253 | /* | |
254 | * On a write fault, fold the dirty bit into accessed_dirty by | |
255 | * shifting it one place right. | |
256 | */ | |
257 | accessed_dirty &= pte >> (PT_DIRTY_SHIFT - PT_ACCESSED_SHIFT); | |
b514c30f AK |
258 | |
259 | if (unlikely(!accessed_dirty)) { | |
260 | ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault); | |
261 | if (unlikely(ret < 0)) | |
262 | goto error; | |
263 | else if (ret) | |
264 | goto retry_walk; | |
265 | } | |
42bf3f0a | 266 | |
fe135d2c AK |
267 | walker->pt_access = pt_access; |
268 | walker->pte_access = pte_access; | |
269 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", | |
518c5a05 | 270 | __func__, (u64)pte, pte_access, pt_access); |
7993ba43 AK |
271 | return 1; |
272 | ||
f59c1d2d | 273 | error: |
134291bf | 274 | errcode |= write_fault | user_fault; |
e57d4a35 YW |
275 | if (fetch_fault && (mmu->nx || |
276 | kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))) | |
134291bf | 277 | errcode |= PFERR_FETCH_MASK; |
8df25a32 | 278 | |
134291bf TY |
279 | walker->fault.vector = PF_VECTOR; |
280 | walker->fault.error_code_valid = true; | |
281 | walker->fault.error_code = errcode; | |
6389ee94 AK |
282 | walker->fault.address = addr; |
283 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
8df25a32 | 284 | |
8c28d031 | 285 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 286 | return 0; |
6aa8b732 AK |
287 | } |
288 | ||
1e301feb | 289 | static int FNAME(walk_addr)(struct guest_walker *walker, |
33770780 | 290 | struct kvm_vcpu *vcpu, gva_t addr, u32 access) |
1e301feb JR |
291 | { |
292 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr, | |
33770780 | 293 | access); |
1e301feb JR |
294 | } |
295 | ||
6539e738 JR |
296 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
297 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 298 | u32 access) |
6539e738 JR |
299 | { |
300 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 301 | addr, access); |
6539e738 JR |
302 | } |
303 | ||
bd6360cc XG |
304 | static bool |
305 | FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
306 | u64 *spte, pt_element_t gpte, bool no_dirty_log) | |
0028425f | 307 | { |
41074d07 | 308 | unsigned pte_access; |
bd6360cc | 309 | gfn_t gfn; |
35149e21 | 310 | pfn_t pfn; |
0028425f | 311 | |
a052b42b | 312 | if (prefetch_invalid_gpte(vcpu, sp, spte, gpte)) |
bd6360cc | 313 | return false; |
407c61c6 | 314 | |
b8688d51 | 315 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
bd6360cc XG |
316 | |
317 | gfn = gpte_to_gfn(gpte); | |
3d34adec | 318 | pte_access = sp->role.access & gpte_access(vcpu, gpte); |
8ea667f2 | 319 | protect_clean_gpte(&pte_access, gpte); |
bd6360cc XG |
320 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, |
321 | no_dirty_log && (pte_access & ACC_WRITE_MASK)); | |
81c52c56 | 322 | if (is_error_pfn(pfn)) |
bd6360cc | 323 | return false; |
0f53b5b1 | 324 | |
1403283a | 325 | /* |
bd6360cc XG |
326 | * we call mmu_set_spte() with host_writable = true because |
327 | * pte_prefetch_gfn_to_pfn always gets a writable pfn. | |
1403283a | 328 | */ |
f7616203 XG |
329 | mmu_set_spte(vcpu, spte, pte_access, 0, NULL, PT_PAGE_TABLE_LEVEL, |
330 | gfn, pfn, true, true); | |
bd6360cc XG |
331 | |
332 | return true; | |
333 | } | |
334 | ||
335 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
336 | u64 *spte, const void *pte) | |
337 | { | |
338 | pt_element_t gpte = *(const pt_element_t *)pte; | |
339 | ||
340 | FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false); | |
0028425f AK |
341 | } |
342 | ||
39c8c672 AK |
343 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
344 | struct guest_walker *gw, int level) | |
345 | { | |
39c8c672 | 346 | pt_element_t curr_pte; |
189be38d XG |
347 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
348 | u64 mask; | |
349 | int r, index; | |
350 | ||
351 | if (level == PT_PAGE_TABLE_LEVEL) { | |
352 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
353 | base_gpa = pte_gpa & ~mask; | |
354 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
355 | ||
356 | r = kvm_read_guest_atomic(vcpu->kvm, base_gpa, | |
357 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); | |
358 | curr_pte = gw->prefetch_ptes[index]; | |
359 | } else | |
360 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, | |
39c8c672 | 361 | &curr_pte, sizeof(curr_pte)); |
189be38d | 362 | |
39c8c672 AK |
363 | return r || curr_pte != gw->ptes[level - 1]; |
364 | } | |
365 | ||
189be38d XG |
366 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
367 | u64 *sptep) | |
957ed9ef XG |
368 | { |
369 | struct kvm_mmu_page *sp; | |
189be38d | 370 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 371 | u64 *spte; |
189be38d | 372 | int i; |
957ed9ef XG |
373 | |
374 | sp = page_header(__pa(sptep)); | |
375 | ||
376 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
377 | return; | |
378 | ||
379 | if (sp->role.direct) | |
380 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
381 | ||
382 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
383 | spte = sp->spt + i; |
384 | ||
385 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
957ed9ef XG |
386 | if (spte == sptep) |
387 | continue; | |
388 | ||
c3707958 | 389 | if (is_shadow_present_pte(*spte)) |
957ed9ef XG |
390 | continue; |
391 | ||
bd6360cc | 392 | if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true)) |
957ed9ef | 393 | break; |
957ed9ef XG |
394 | } |
395 | } | |
396 | ||
6aa8b732 AK |
397 | /* |
398 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
d4878f24 XG |
399 | * If the guest tries to write a write-protected page, we need to |
400 | * emulate this operation, return 1 to indicate this case. | |
6aa8b732 | 401 | */ |
d4878f24 | 402 | static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
e7a04c99 | 403 | struct guest_walker *gw, |
c2288505 | 404 | int write_fault, int hlevel, |
d4878f24 | 405 | pfn_t pfn, bool map_writable, bool prefault) |
6aa8b732 | 406 | { |
5991b332 | 407 | struct kvm_mmu_page *sp = NULL; |
24157aaf | 408 | struct kvm_shadow_walk_iterator it; |
d4878f24 XG |
409 | unsigned direct_access, access = gw->pt_access; |
410 | int top_level, emulate = 0; | |
abb9e0b8 | 411 | |
b36c7a7c | 412 | direct_access = gw->pte_access; |
84754cd8 | 413 | |
5991b332 AK |
414 | top_level = vcpu->arch.mmu.root_level; |
415 | if (top_level == PT32E_ROOT_LEVEL) | |
416 | top_level = PT32_ROOT_LEVEL; | |
417 | /* | |
418 | * Verify that the top-level gpte is still there. Since the page | |
419 | * is a root page, it is either write protected (and cannot be | |
420 | * changed from now on) or it is invalid (in which case, we don't | |
421 | * really care if it changes underneath us after this point). | |
422 | */ | |
423 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
424 | goto out_gpte_changed; | |
425 | ||
24157aaf AK |
426 | for (shadow_walk_init(&it, vcpu, addr); |
427 | shadow_walk_okay(&it) && it.level > gw->level; | |
428 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
429 | gfn_t table_gfn; |
430 | ||
a30f47cb | 431 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 432 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 433 | |
5991b332 | 434 | sp = NULL; |
24157aaf AK |
435 | if (!is_shadow_present_pte(*it.sptep)) { |
436 | table_gfn = gw->table_gfn[it.level - 2]; | |
437 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
438 | false, access, it.sptep); | |
5991b332 | 439 | } |
0b3c9333 AK |
440 | |
441 | /* | |
442 | * Verify that the gpte in the page we've just write | |
443 | * protected is still there. | |
444 | */ | |
24157aaf | 445 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 446 | goto out_gpte_changed; |
abb9e0b8 | 447 | |
5991b332 | 448 | if (sp) |
24157aaf | 449 | link_shadow_page(it.sptep, sp); |
e7a04c99 | 450 | } |
050e6499 | 451 | |
0b3c9333 | 452 | for (; |
24157aaf AK |
453 | shadow_walk_okay(&it) && it.level > hlevel; |
454 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
455 | gfn_t direct_gfn; |
456 | ||
a30f47cb | 457 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 458 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 459 | |
24157aaf | 460 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 461 | |
24157aaf | 462 | if (is_shadow_present_pte(*it.sptep)) |
0b3c9333 AK |
463 | continue; |
464 | ||
24157aaf | 465 | direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
0b3c9333 | 466 | |
24157aaf AK |
467 | sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1, |
468 | true, direct_access, it.sptep); | |
469 | link_shadow_page(it.sptep, sp); | |
0b3c9333 AK |
470 | } |
471 | ||
a30f47cb | 472 | clear_sp_write_flooding_count(it.sptep); |
f7616203 XG |
473 | mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault, &emulate, |
474 | it.level, gw->gfn, pfn, prefault, map_writable); | |
189be38d | 475 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
0b3c9333 | 476 | |
d4878f24 | 477 | return emulate; |
0b3c9333 AK |
478 | |
479 | out_gpte_changed: | |
5991b332 | 480 | if (sp) |
24157aaf | 481 | kvm_mmu_put_page(sp, it.sptep); |
0b3c9333 | 482 | kvm_release_pfn_clean(pfn); |
d4878f24 | 483 | return 0; |
6aa8b732 AK |
484 | } |
485 | ||
7751babd XG |
486 | /* |
487 | * To see whether the mapped gfn can write its page table in the current | |
488 | * mapping. | |
489 | * | |
490 | * It is the helper function of FNAME(page_fault). When guest uses large page | |
491 | * size to map the writable gfn which is used as current page table, we should | |
492 | * force kvm to use small page size to map it because new shadow page will be | |
493 | * created when kvm establishes shadow page table that stop kvm using large | |
494 | * page size. Do it early can avoid unnecessary #PF and emulation. | |
495 | * | |
93c05d3e XG |
496 | * @write_fault_to_shadow_pgtable will return true if the fault gfn is |
497 | * currently used as its page table. | |
498 | * | |
7751babd XG |
499 | * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok |
500 | * since the PDPT is always shadowed, that means, we can not use large page | |
501 | * size to map the gfn which is used as PDPT. | |
502 | */ | |
503 | static bool | |
504 | FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu, | |
93c05d3e XG |
505 | struct guest_walker *walker, int user_fault, |
506 | bool *write_fault_to_shadow_pgtable) | |
7751babd XG |
507 | { |
508 | int level; | |
509 | gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1); | |
93c05d3e | 510 | bool self_changed = false; |
7751babd XG |
511 | |
512 | if (!(walker->pte_access & ACC_WRITE_MASK || | |
513 | (!is_write_protection(vcpu) && !user_fault))) | |
514 | return false; | |
515 | ||
93c05d3e XG |
516 | for (level = walker->level; level <= walker->max_level; level++) { |
517 | gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1]; | |
518 | ||
519 | self_changed |= !(gfn & mask); | |
520 | *write_fault_to_shadow_pgtable |= !gfn; | |
521 | } | |
7751babd | 522 | |
93c05d3e | 523 | return self_changed; |
7751babd XG |
524 | } |
525 | ||
6aa8b732 AK |
526 | /* |
527 | * Page fault handler. There are several causes for a page fault: | |
528 | * - there is no shadow pte for the guest pte | |
529 | * - write access through a shadow pte marked read only so that we can set | |
530 | * the dirty bit | |
531 | * - write access to a shadow pte marked read only so we can update the page | |
532 | * dirty bitmap, when userspace requests it | |
533 | * - mmio access; in this case we will never install a present shadow pte | |
534 | * - normal guest page fault due to the guest pte marked not present, not | |
535 | * writable, or not executable | |
536 | * | |
e2dec939 AK |
537 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
538 | * a negative value on error. | |
6aa8b732 | 539 | */ |
56028d08 | 540 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code, |
78b2c54a | 541 | bool prefault) |
6aa8b732 AK |
542 | { |
543 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 AK |
544 | int user_fault = error_code & PFERR_USER_MASK; |
545 | struct guest_walker walker; | |
e2dec939 | 546 | int r; |
35149e21 | 547 | pfn_t pfn; |
7e4e4056 | 548 | int level = PT_PAGE_TABLE_LEVEL; |
936a5fe6 | 549 | int force_pt_level; |
e930bffe | 550 | unsigned long mmu_seq; |
93c05d3e | 551 | bool map_writable, is_self_change_mapping; |
6aa8b732 | 552 | |
b8688d51 | 553 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 554 | |
f8f55942 XG |
555 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
556 | r = handle_mmio_page_fault(vcpu, addr, error_code, | |
ce88decf | 557 | mmu_is_nested(vcpu)); |
f8f55942 XG |
558 | if (likely(r != RET_MMIO_PF_INVALID)) |
559 | return r; | |
560 | }; | |
ce88decf | 561 | |
e2dec939 AK |
562 | r = mmu_topup_memory_caches(vcpu); |
563 | if (r) | |
564 | return r; | |
714b93da | 565 | |
6aa8b732 | 566 | /* |
a8b876b1 | 567 | * Look up the guest pte for the faulting address. |
6aa8b732 | 568 | */ |
33770780 | 569 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
570 | |
571 | /* | |
572 | * The page is not mapped by the guest. Let the guest handle it. | |
573 | */ | |
7993ba43 | 574 | if (!r) { |
b8688d51 | 575 | pgprintk("%s: guest page fault\n", __func__); |
a30f47cb | 576 | if (!prefault) |
fb67e14f | 577 | inject_page_fault(vcpu, &walker.fault); |
a30f47cb | 578 | |
6aa8b732 AK |
579 | return 0; |
580 | } | |
581 | ||
93c05d3e XG |
582 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
583 | ||
584 | is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu, | |
585 | &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable); | |
586 | ||
936a5fe6 | 587 | if (walker.level >= PT_DIRECTORY_LEVEL) |
7751babd | 588 | force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn) |
93c05d3e | 589 | || is_self_change_mapping; |
936a5fe6 AA |
590 | else |
591 | force_pt_level = 1; | |
592 | if (!force_pt_level) { | |
7e4e4056 JR |
593 | level = min(walker.level, mapping_level(vcpu, walker.gfn)); |
594 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 595 | } |
7e4e4056 | 596 | |
e930bffe | 597 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 598 | smp_rmb(); |
af585b92 | 599 | |
78b2c54a | 600 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault, |
612819c3 | 601 | &map_writable)) |
af585b92 | 602 | return 0; |
d7824fff | 603 | |
d7c55201 XG |
604 | if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr, |
605 | walker.gfn, pfn, walker.pte_access, &r)) | |
606 | return r; | |
607 | ||
c2288505 XG |
608 | /* |
609 | * Do not change pte_access if the pfn is a mmio page, otherwise | |
610 | * we will cache the incorrect access into mmio spte. | |
611 | */ | |
612 | if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) && | |
613 | !is_write_protection(vcpu) && !user_fault && | |
614 | !is_noslot_pfn(pfn)) { | |
615 | walker.pte_access |= ACC_WRITE_MASK; | |
616 | walker.pte_access &= ~ACC_USER_MASK; | |
617 | ||
618 | /* | |
619 | * If we converted a user page to a kernel page, | |
620 | * so that the kernel can write to it when cr0.wp=0, | |
621 | * then we should prevent the kernel from executing it | |
622 | * if SMEP is enabled. | |
623 | */ | |
624 | if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)) | |
625 | walker.pte_access &= ~ACC_EXEC_MASK; | |
626 | } | |
627 | ||
aaee2c94 | 628 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 629 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 630 | goto out_unlock; |
bc32ce21 | 631 | |
0375f7fa | 632 | kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
450e0b41 | 633 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
634 | if (!force_pt_level) |
635 | transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level); | |
c2288505 | 636 | r = FNAME(fetch)(vcpu, addr, &walker, write_fault, |
d4878f24 | 637 | level, pfn, map_writable, prefault); |
1165f5fe | 638 | ++vcpu->stat.pf_fixed; |
0375f7fa | 639 | kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
aaee2c94 | 640 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 641 | |
d4878f24 | 642 | return r; |
e930bffe AA |
643 | |
644 | out_unlock: | |
645 | spin_unlock(&vcpu->kvm->mmu_lock); | |
646 | kvm_release_pfn_clean(pfn); | |
647 | return 0; | |
6aa8b732 AK |
648 | } |
649 | ||
505aef8f XG |
650 | static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp) |
651 | { | |
652 | int offset = 0; | |
653 | ||
f71fa31f | 654 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
505aef8f XG |
655 | |
656 | if (PTTYPE == 32) | |
657 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
658 | ||
659 | return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); | |
660 | } | |
661 | ||
a461930b | 662 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) |
a7052897 | 663 | { |
a461930b | 664 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 665 | struct kvm_mmu_page *sp; |
a461930b AK |
666 | int level; |
667 | u64 *sptep; | |
668 | ||
bebb106a XG |
669 | vcpu_clear_mmio_info(vcpu, gva); |
670 | ||
f57f2ef5 XG |
671 | /* |
672 | * No need to check return value here, rmap_can_add() can | |
673 | * help us to skip pte prefetch later. | |
674 | */ | |
675 | mmu_topup_memory_caches(vcpu); | |
a7052897 | 676 | |
f57f2ef5 | 677 | spin_lock(&vcpu->kvm->mmu_lock); |
a461930b AK |
678 | for_each_shadow_entry(vcpu, gva, iterator) { |
679 | level = iterator.level; | |
680 | sptep = iterator.sptep; | |
ad218f85 | 681 | |
f78978aa | 682 | sp = page_header(__pa(sptep)); |
884a0ff0 | 683 | if (is_last_spte(*sptep, level)) { |
f57f2ef5 XG |
684 | pt_element_t gpte; |
685 | gpa_t pte_gpa; | |
686 | ||
f78978aa XG |
687 | if (!sp->unsync) |
688 | break; | |
689 | ||
505aef8f | 690 | pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
08e850c6 | 691 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b | 692 | |
505aef8f XG |
693 | if (mmu_page_zap_pte(vcpu->kvm, sp, sptep)) |
694 | kvm_flush_remote_tlbs(vcpu->kvm); | |
f57f2ef5 XG |
695 | |
696 | if (!rmap_can_add(vcpu)) | |
697 | break; | |
698 | ||
699 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
700 | sizeof(pt_element_t))) | |
701 | break; | |
702 | ||
703 | FNAME(update_pte)(vcpu, sp, sptep, &gpte); | |
87917239 | 704 | } |
a7052897 | 705 | |
f78978aa | 706 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
707 | break; |
708 | } | |
ad218f85 | 709 | spin_unlock(&vcpu->kvm->mmu_lock); |
a7052897 MT |
710 | } |
711 | ||
1871c602 | 712 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
ab9ae313 | 713 | struct x86_exception *exception) |
6aa8b732 AK |
714 | { |
715 | struct guest_walker walker; | |
e119d117 AK |
716 | gpa_t gpa = UNMAPPED_GVA; |
717 | int r; | |
6aa8b732 | 718 | |
33770780 | 719 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, access); |
6aa8b732 | 720 | |
e119d117 | 721 | if (r) { |
1755fbcc | 722 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 723 | gpa |= vaddr & ~PAGE_MASK; |
8c28d031 AK |
724 | } else if (exception) |
725 | *exception = walker.fault; | |
6aa8b732 AK |
726 | |
727 | return gpa; | |
728 | } | |
729 | ||
6539e738 | 730 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
731 | u32 access, |
732 | struct x86_exception *exception) | |
6539e738 JR |
733 | { |
734 | struct guest_walker walker; | |
735 | gpa_t gpa = UNMAPPED_GVA; | |
736 | int r; | |
737 | ||
33770780 | 738 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
739 | |
740 | if (r) { | |
741 | gpa = gfn_to_gpa(walker.gfn); | |
742 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
743 | } else if (exception) |
744 | *exception = walker.fault; | |
6539e738 JR |
745 | |
746 | return gpa; | |
747 | } | |
748 | ||
e8bc217a MT |
749 | /* |
750 | * Using the cached information from sp->gfns is safe because: | |
751 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
752 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
753 | * |
754 | * Note: | |
755 | * We should flush all tlbs if spte is dropped even though guest is | |
756 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
757 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
758 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
759 | * freed pages. | |
760 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. | |
e8bc217a | 761 | */ |
a4a8e6f7 | 762 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a | 763 | { |
505aef8f | 764 | int i, nr_present = 0; |
9bdbba13 | 765 | bool host_writable; |
51fb60d8 | 766 | gpa_t first_pte_gpa; |
e8bc217a | 767 | |
2032a93d LJ |
768 | /* direct kvm_mmu_page can not be unsync. */ |
769 | BUG_ON(sp->role.direct); | |
770 | ||
505aef8f | 771 | first_pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
51fb60d8 | 772 | |
e8bc217a MT |
773 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
774 | unsigned pte_access; | |
775 | pt_element_t gpte; | |
776 | gpa_t pte_gpa; | |
f55c3f41 | 777 | gfn_t gfn; |
e8bc217a | 778 | |
ce88decf | 779 | if (!sp->spt[i]) |
e8bc217a MT |
780 | continue; |
781 | ||
51fb60d8 | 782 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a MT |
783 | |
784 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
785 | sizeof(pt_element_t))) | |
786 | return -EINVAL; | |
787 | ||
a052b42b | 788 | if (prefetch_invalid_gpte(vcpu, sp, &sp->spt[i], gpte)) { |
a4ee1ca4 | 789 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
790 | continue; |
791 | } | |
792 | ||
ce88decf XG |
793 | gfn = gpte_to_gfn(gpte); |
794 | pte_access = sp->role.access; | |
3d34adec | 795 | pte_access &= gpte_access(vcpu, gpte); |
8ea667f2 | 796 | protect_clean_gpte(&pte_access, gpte); |
ce88decf | 797 | |
f2fd125d XG |
798 | if (sync_mmio_spte(vcpu->kvm, &sp->spt[i], gfn, pte_access, |
799 | &nr_present)) | |
ce88decf XG |
800 | continue; |
801 | ||
407c61c6 | 802 | if (gfn != sp->gfns[i]) { |
c3707958 | 803 | drop_spte(vcpu->kvm, &sp->spt[i]); |
a4ee1ca4 | 804 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
805 | continue; |
806 | } | |
807 | ||
808 | nr_present++; | |
ce88decf | 809 | |
f8e453b0 XG |
810 | host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE; |
811 | ||
c2288505 | 812 | set_spte(vcpu, &sp->spt[i], pte_access, |
640d9b0d | 813 | PT_PAGE_TABLE_LEVEL, gfn, |
1403283a | 814 | spte_to_pfn(sp->spt[i]), true, false, |
9bdbba13 | 815 | host_writable); |
e8bc217a MT |
816 | } |
817 | ||
818 | return !nr_present; | |
819 | } | |
820 | ||
6aa8b732 AK |
821 | #undef pt_element_t |
822 | #undef guest_walker | |
823 | #undef FNAME | |
824 | #undef PT_BASE_ADDR_MASK | |
825 | #undef PT_INDEX | |
e04da980 JR |
826 | #undef PT_LVL_ADDR_MASK |
827 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 828 | #undef PT_LEVEL_BITS |
cea0f0e7 | 829 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 830 | #undef gpte_to_gfn |
e04da980 | 831 | #undef gpte_to_gfn_lvl |
b3e4e63f | 832 | #undef CMPXCHG |