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KVM: Add support to disable MSI for assigned device
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
e495606d 18#include "kvm_svm.h"
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
5fdbf976 21#include "kvm_cache_regs.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
6aa8b732 28
e495606d 29#include <asm/desc.h>
6aa8b732 30
63d1142f
EH		 31#include <asm/virtext.h>
32
4ecac3fd
AK		 33#define __ex(x) __kvm_handle_fault_on_reboot(x)
34
6aa8b732
AK		 35MODULE_AUTHOR("Qumranet");
36MODULE_LICENSE("GPL");
37
38#define IOPM_ALLOC_ORDER 2
39#define MSRPM_ALLOC_ORDER 1
40
6aa8b732
AK		 41#define SEG_TYPE_LDT 2
42#define SEG_TYPE_BUSY_TSS16 3
43
80b7706e
JR		 44#define SVM_FEATURE_NPT (1 << 0)
45#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 46#define SVM_FEATURE_SVML (1 << 2)
80b7706e 47
24e09cbf
JR		 48#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
49
c0725420
AG		 50/* Turn on to get debugging output*/
51/* #define NESTED_DEBUG */
52
53#ifdef NESTED_DEBUG
54#define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
55#else
56#define nsvm_printk(fmt, args...) do {} while(0)
57#endif
58
709ddebf
JR		 59/* enable NPT for AMD64 and X86 with PAE */
60#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
61static bool npt_enabled = true;
62#else
e3da3acd 63static bool npt_enabled = false;
709ddebf 64#endif
6c7dac72
JR		 65static int npt = 1;
66
67module_param(npt, int, S_IRUGO);
e3da3acd 68
236de055
AG		 69static int nested = 0;
70module_param(nested, int, S_IRUGO);
71
04d2cc77 72static void kvm_reput_irq(struct vcpu_svm *svm);
44874f84 73static void svm_flush_tlb(struct kvm_vcpu *vcpu);
04d2cc77 74
cf74a78b
AG		 75static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
76static int nested_svm_vmexit(struct vcpu_svm *svm);
77static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
78 void *arg2, void *opaque);
79static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
80 bool has_error_code, u32 error_code);
81
a2fa3e9f
GH		 82static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
83{
fb3f0f51 84 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 85}
86
3d6368ef
AG		 87static inline bool is_nested(struct vcpu_svm *svm)
88{
89 return svm->nested_vmcb;
90}
91
4866d5e3 92static unsigned long iopm_base;
6aa8b732
AK		 93
94struct kvm_ldttss_desc {
95 u16 limit0;
96 u16 base0;
97 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
98 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
99 u32 base3;
100 u32 zero1;
101} __attribute__((packed));
102
103struct svm_cpu_data {
104 int cpu;
105
5008fdf5
AK		 106 u64 asid_generation;
107 u32 max_asid;
108 u32 next_asid;
6aa8b732
AK		 109 struct kvm_ldttss_desc *tss_desc;
110
111 struct page *save_area;
112};
113
114static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 115static uint32_t svm_features;
6aa8b732
AK		 116
117struct svm_init_data {
118 int cpu;
119 int r;
120};
121
122static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
123
9d8f549d 124#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 125#define MSRS_RANGE_SIZE 2048
126#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
127
128#define MAX_INST_SIZE 15
129
80b7706e
JR		 130static inline u32 svm_has(u32 feat)
131{
132 return svm_features & feat;
133}
134
6aa8b732
AK		 135static inline u8 pop_irq(struct kvm_vcpu *vcpu)
136{
ad312c7c
ZX		 137 int word_index = __ffs(vcpu->arch.irq_summary);
138 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
6aa8b732
AK		 139 int irq = word_index * BITS_PER_LONG + bit_index;
140
ad312c7c
ZX		 141 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
142 if (!vcpu->arch.irq_pending[word_index])
143 clear_bit(word_index, &vcpu->arch.irq_summary);
6aa8b732
AK		 144 return irq;
145}
146
147static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
148{
ad312c7c
ZX		 149 set_bit(irq, vcpu->arch.irq_pending);
150 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
6aa8b732
AK		 151}
152
153static inline void clgi(void)
154{
4ecac3fd 155 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 156}
157
158static inline void stgi(void)
159{
4ecac3fd 160 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 161}
162
163static inline void invlpga(unsigned long addr, u32 asid)
164{
4ecac3fd 165 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 166}
167
168static inline unsigned long kvm_read_cr2(void)
169{
170 unsigned long cr2;
171
172 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
173 return cr2;
174}
175
176static inline void kvm_write_cr2(unsigned long val)
177{
178 asm volatile ("mov %0, %%cr2" :: "r" (val));
179}
180
6aa8b732
AK		 181static inline void force_new_asid(struct kvm_vcpu *vcpu)
182{
a2fa3e9f 183 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 184}
185
186static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
187{
188 force_new_asid(vcpu);
189}
190
191static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
192{
709ddebf 193 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 194 efer &= ~EFER_LME;
6aa8b732 195
9962d032 196 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
ad312c7c 197 vcpu->arch.shadow_efer = efer;
6aa8b732
AK		 198}
199
298101da
AK		 200static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
201 bool has_error_code, u32 error_code)
202{
203 struct vcpu_svm *svm = to_svm(vcpu);
204
cf74a78b
AG		 205 /* If we are within a nested VM we'd better #VMEXIT and let the
206 guest handle the exception */
207 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
208 return;
209
298101da
AK		 210 svm->vmcb->control.event_inj = nr
211 | SVM_EVTINJ_VALID
212 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
213 | SVM_EVTINJ_TYPE_EXEPT;
214 svm->vmcb->control.event_inj_err = error_code;
215}
216
217static bool svm_exception_injected(struct kvm_vcpu *vcpu)
218{
219 struct vcpu_svm *svm = to_svm(vcpu);
220
221 return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
222}
223
6aa8b732
AK		 224static int is_external_interrupt(u32 info)
225{
226 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
227 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
228}
229
230static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
231{
a2fa3e9f
GH		 232 struct vcpu_svm *svm = to_svm(vcpu);
233
234 if (!svm->next_rip) {
b8688d51 235 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 236 return;
237 }
5fdbf976
MT		 238 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
239 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
240 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 241
5fdbf976 242 kvm_rip_write(vcpu, svm->next_rip);
a2fa3e9f 243 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
c1150d8c 244
1371d904 245 vcpu->arch.interrupt_window_open = (svm->vcpu.arch.hflags & HF_GIF_MASK);
6aa8b732
AK		 246}
247
248static int has_svm(void)
249{
63d1142f 250 const char *msg;
6aa8b732 251
63d1142f
EH		 252 if (!cpu_has_svm(&msg)) {
253 printk(KERN_INFO "has_svn: %s\n", msg);
6aa8b732
AK		 254 return 0;
255 }
256
6aa8b732
AK		 257 return 1;
258}
259
260static void svm_hardware_disable(void *garbage)
261{
2c8dceeb 262 cpu_svm_disable();
6aa8b732
AK		 263}
264
265static void svm_hardware_enable(void *garbage)
266{
267
268 struct svm_cpu_data *svm_data;
269 uint64_t efer;
6aa8b732 270 struct desc_ptr gdt_descr;
6aa8b732
AK		 271 struct desc_struct *gdt;
272 int me = raw_smp_processor_id();
273
274 if (!has_svm()) {
275 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
276 return;
277 }
278 svm_data = per_cpu(svm_data, me);
279
280 if (!svm_data) {
281 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
282 me);
283 return;
284 }
285
286 svm_data->asid_generation = 1;
287 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
288 svm_data->next_asid = svm_data->max_asid + 1;
289
d77c26fc 290 asm volatile ("sgdt %0" : "=m"(gdt_descr));
6aa8b732
AK		 291 gdt = (struct desc_struct *)gdt_descr.address;
292 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
293
294 rdmsrl(MSR_EFER, efer);
9962d032 295 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732
AK		 296
297 wrmsrl(MSR_VM_HSAVE_PA,
298 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
299}
300
0da1db75
JR		 301static void svm_cpu_uninit(int cpu)
302{
303 struct svm_cpu_data *svm_data
304 = per_cpu(svm_data, raw_smp_processor_id());
305
306 if (!svm_data)
307 return;
308
309 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
310 __free_page(svm_data->save_area);
311 kfree(svm_data);
312}
313
6aa8b732
AK		 314static int svm_cpu_init(int cpu)
315{
316 struct svm_cpu_data *svm_data;
317 int r;
318
319 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
320 if (!svm_data)
321 return -ENOMEM;
322 svm_data->cpu = cpu;
323 svm_data->save_area = alloc_page(GFP_KERNEL);
324 r = -ENOMEM;
325 if (!svm_data->save_area)
326 goto err_1;
327
328 per_cpu(svm_data, cpu) = svm_data;
329
330 return 0;
331
332err_1:
333 kfree(svm_data);
334 return r;
335
336}
337
bfc733a7
RR		 338static void set_msr_interception(u32 *msrpm, unsigned msr,
339 int read, int write)
6aa8b732
AK		 340{
341 int i;
342
343 for (i = 0; i < NUM_MSR_MAPS; i++) {
344 if (msr >= msrpm_ranges[i] &&
345 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
346 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
347 msrpm_ranges[i]) * 2;
348
349 u32 *base = msrpm + (msr_offset / 32);
350 u32 msr_shift = msr_offset % 32;
351 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
352 *base = (*base & ~(0x3 << msr_shift)) |
353 (mask << msr_shift);
bfc733a7 354 return;
6aa8b732
AK		 355 }
356 }
bfc733a7 357 BUG();
6aa8b732
AK		 358}
359
f65c229c
JR		 360static void svm_vcpu_init_msrpm(u32 *msrpm)
361{
362 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
363
364#ifdef CONFIG_X86_64
365 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
366 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
367 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
368 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
369 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
370 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
371#endif
372 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
373 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
374 set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
375 set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
376}
377
24e09cbf
JR		 378static void svm_enable_lbrv(struct vcpu_svm *svm)
379{
380 u32 *msrpm = svm->msrpm;
381
382 svm->vmcb->control.lbr_ctl = 1;
383 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
384 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
385 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
386 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
387}
388
389static void svm_disable_lbrv(struct vcpu_svm *svm)
390{
391 u32 *msrpm = svm->msrpm;
392
393 svm->vmcb->control.lbr_ctl = 0;
394 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
395 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
396 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
397 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
398}
399
6aa8b732
AK		 400static __init int svm_hardware_setup(void)
401{
402 int cpu;
403 struct page *iopm_pages;
f65c229c 404 void *iopm_va;
6aa8b732
AK		 405 int r;
406
6aa8b732
AK		 407 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
408
409 if (!iopm_pages)
410 return -ENOMEM;
c8681339
AL		 411
412 iopm_va = page_address(iopm_pages);
413 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
414 clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
6aa8b732
AK		 415 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
416
50a37eb4
JR		 417 if (boot_cpu_has(X86_FEATURE_NX))
418 kvm_enable_efer_bits(EFER_NX);
419
236de055
AG		 420 if (nested) {
421 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
422 kvm_enable_efer_bits(EFER_SVME);
423 }
424
6aa8b732
AK		 425 for_each_online_cpu(cpu) {
426 r = svm_cpu_init(cpu);
427 if (r)
f65c229c 428 goto err;
6aa8b732 429 }
33bd6a0b
JR		 430
431 svm_features = cpuid_edx(SVM_CPUID_FUNC);
432
e3da3acd
JR		 433 if (!svm_has(SVM_FEATURE_NPT))
434 npt_enabled = false;
435
6c7dac72
JR		 436 if (npt_enabled && !npt) {
437 printk(KERN_INFO "kvm: Nested Paging disabled\n");
438 npt_enabled = false;
439 }
440
18552672 441 if (npt_enabled) {
e3da3acd 442 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 443 kvm_enable_tdp();
5f4cb662
JR		 444 } else
445 kvm_disable_tdp();
e3da3acd 446
6aa8b732
AK		 447 return 0;
448
f65c229c 449err:
6aa8b732
AK		 450 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
451 iopm_base = 0;
452 return r;
453}
454
455static __exit void svm_hardware_unsetup(void)
456{
0da1db75
JR		 457 int cpu;
458
459 for_each_online_cpu(cpu)
460 svm_cpu_uninit(cpu);
461
6aa8b732 462 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 463 iopm_base = 0;
6aa8b732
AK		 464}
465
466static void init_seg(struct vmcb_seg *seg)
467{
468 seg->selector = 0;
469 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
470 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
471 seg->limit = 0xffff;
472 seg->base = 0;
473}
474
475static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
476{
477 seg->selector = 0;
478 seg->attrib = SVM_SELECTOR_P_MASK | type;
479 seg->limit = 0xffff;
480 seg->base = 0;
481}
482
e6101a96 483static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 484{
e6101a96
JR		 485 struct vmcb_control_area *control = &svm->vmcb->control;
486 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732
AK		 487
488 control->intercept_cr_read = INTERCEPT_CR0_MASK |
489 INTERCEPT_CR3_MASK |
649d6864 490 INTERCEPT_CR4_MASK;
6aa8b732
AK		 491
492 control->intercept_cr_write = INTERCEPT_CR0_MASK |
493 INTERCEPT_CR3_MASK |
80a8119c
AK		 494 INTERCEPT_CR4_MASK |
495 INTERCEPT_CR8_MASK;
6aa8b732
AK		 496
497 control->intercept_dr_read = INTERCEPT_DR0_MASK |
498 INTERCEPT_DR1_MASK |
499 INTERCEPT_DR2_MASK |
500 INTERCEPT_DR3_MASK;
501
502 control->intercept_dr_write = INTERCEPT_DR0_MASK |
503 INTERCEPT_DR1_MASK |
504 INTERCEPT_DR2_MASK |
505 INTERCEPT_DR3_MASK |
506 INTERCEPT_DR5_MASK |
507 INTERCEPT_DR7_MASK;
508
7aa81cc0 509 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 510 (1 << UD_VECTOR) |
511 (1 << MC_VECTOR);
6aa8b732
AK		 512
513
514 control->intercept = (1ULL << INTERCEPT_INTR) |
515 (1ULL << INTERCEPT_NMI) |
0152527b 516 (1ULL << INTERCEPT_SMI) |
6aa8b732 517 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 518 (1ULL << INTERCEPT_INVD) |
6aa8b732 519 (1ULL << INTERCEPT_HLT) |
a7052897 520 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 521 (1ULL << INTERCEPT_INVLPGA) |
522 (1ULL << INTERCEPT_IOIO_PROT) |
523 (1ULL << INTERCEPT_MSR_PROT) |
524 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 525 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 526 (1ULL << INTERCEPT_VMRUN) |
527 (1ULL << INTERCEPT_VMMCALL) |
528 (1ULL << INTERCEPT_VMLOAD) |
529 (1ULL << INTERCEPT_VMSAVE) |
530 (1ULL << INTERCEPT_STGI) |
531 (1ULL << INTERCEPT_CLGI) |
916ce236 532 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 533 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 534 (1ULL << INTERCEPT_MONITOR) |
535 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 536
537 control->iopm_base_pa = iopm_base;
f65c229c 538 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 539 control->tsc_offset = 0;
6aa8b732
AK		 540 control->int_ctl = V_INTR_MASKING_MASK;
541
542 init_seg(&save->es);
543 init_seg(&save->ss);
544 init_seg(&save->ds);
545 init_seg(&save->fs);
546 init_seg(&save->gs);
547
548 save->cs.selector = 0xf000;
549 /* Executable/Readable Code Segment */
550 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
551 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
552 save->cs.limit = 0xffff;
d92899a0
AK		 553 /*
554 * cs.base should really be 0xffff0000, but vmx can't handle that, so
555 * be consistent with it.
556 *
557 * Replace when we have real mode working for vmx.
558 */
559 save->cs.base = 0xf0000;
6aa8b732
AK		 560
561 save->gdtr.limit = 0xffff;
562 save->idtr.limit = 0xffff;
563
564 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
565 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
566
9962d032 567 save->efer = EFER_SVME;
d77c26fc 568 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 569 save->dr7 = 0x400;
570 save->rflags = 2;
571 save->rip = 0x0000fff0;
5fdbf976 572 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732
AK		 573
574 /*
575 * cr0 val on cpu init should be 0x60000010, we enable cpu
576 * cache by default. the orderly way is to enable cache in bios.
577 */
707d92fa 578 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
66aee91a 579 save->cr4 = X86_CR4_PAE;
6aa8b732 580 /* rdx = ?? */
709ddebf
JR		 581
582 if (npt_enabled) {
583 /* Setup VMCB for Nested Paging */
584 control->nested_ctl = 1;
a7052897
MT		 585 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
586 (1ULL << INTERCEPT_INVLPG));
709ddebf
JR		 587 control->intercept_exceptions &= ~(1 << PF_VECTOR);
588 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
589 INTERCEPT_CR3_MASK);
590 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
591 INTERCEPT_CR3_MASK);
592 save->g_pat = 0x0007040600070406ULL;
593 /* enable caching because the QEMU Bios doesn't enable it */
594 save->cr0 = X86_CR0_ET;
595 save->cr3 = 0;
596 save->cr4 = 0;
597 }
a79d2f18 598 force_new_asid(&svm->vcpu);
1371d904 599
3d6368ef 600 svm->nested_vmcb = 0;
1371d904 601 svm->vcpu.arch.hflags = HF_GIF_MASK;
6aa8b732
AK		 602}
603
e00c8cf2 604static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 605{
606 struct vcpu_svm *svm = to_svm(vcpu);
607
e6101a96 608 init_vmcb(svm);
70433389
AK		 609
610 if (vcpu->vcpu_id != 0) {
5fdbf976 611 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 612 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
613 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 614 }
5fdbf976
MT		 615 vcpu->arch.regs_avail = ~0;
616 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 617
618 return 0;
04d2cc77
AK		 619}
620
fb3f0f51 621static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 622{
a2fa3e9f 623 struct vcpu_svm *svm;
6aa8b732 624 struct page *page;
f65c229c 625 struct page *msrpm_pages;
b286d5d8 626 struct page *hsave_page;
3d6368ef 627 struct page *nested_msrpm_pages;
fb3f0f51 628 int err;
6aa8b732 629
c16f862d 630 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 631 if (!svm) {
632 err = -ENOMEM;
633 goto out;
634 }
635
636 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
637 if (err)
638 goto free_svm;
639
6aa8b732 640 page = alloc_page(GFP_KERNEL);
fb3f0f51
RR		 641 if (!page) {
642 err = -ENOMEM;
643 goto uninit;
644 }
6aa8b732 645
f65c229c
JR		 646 err = -ENOMEM;
647 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
648 if (!msrpm_pages)
649 goto uninit;
3d6368ef
AG		 650
651 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
652 if (!nested_msrpm_pages)
653 goto uninit;
654
f65c229c
JR		 655 svm->msrpm = page_address(msrpm_pages);
656 svm_vcpu_init_msrpm(svm->msrpm);
657
b286d5d8
AG		 658 hsave_page = alloc_page(GFP_KERNEL);
659 if (!hsave_page)
660 goto uninit;
661 svm->hsave = page_address(hsave_page);
662
3d6368ef
AG		 663 svm->nested_msrpm = page_address(nested_msrpm_pages);
664
a2fa3e9f
GH		 665 svm->vmcb = page_address(page);
666 clear_page(svm->vmcb);
667 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
668 svm->asid_generation = 0;
e6101a96 669 init_vmcb(svm);
a2fa3e9f 670
fb3f0f51
RR		 671 fx_init(&svm->vcpu);
672 svm->vcpu.fpu_active = 1;
ad312c7c 673 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
fb3f0f51 674 if (svm->vcpu.vcpu_id == 0)
ad312c7c 675 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 676
fb3f0f51 677 return &svm->vcpu;
36241b8c 678
fb3f0f51
RR		 679uninit:
680 kvm_vcpu_uninit(&svm->vcpu);
681free_svm:
a4770347 682 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 683out:
684 return ERR_PTR(err);
6aa8b732
AK		 685}
686
687static void svm_free_vcpu(struct kvm_vcpu *vcpu)
688{
a2fa3e9f
GH		 689 struct vcpu_svm *svm = to_svm(vcpu);
690
fb3f0f51 691 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 692 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
b286d5d8 693 __free_page(virt_to_page(svm->hsave));
3d6368ef 694 __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 695 kvm_vcpu_uninit(vcpu);
a4770347 696 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 697}
698
15ad7146 699static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 700{
a2fa3e9f 701 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 702 int i;
0cc5064d 703
0cc5064d
AK		 704 if (unlikely(cpu != vcpu->cpu)) {
705 u64 tsc_this, delta;
706
707 /*
708 * Make sure that the guest sees a monotonically
709 * increasing TSC.
710 */
711 rdtscll(tsc_this);
ad312c7c 712 delta = vcpu->arch.host_tsc - tsc_this;
a2fa3e9f 713 svm->vmcb->control.tsc_offset += delta;
0cc5064d 714 vcpu->cpu = cpu;
2f599714 715 kvm_migrate_timers(vcpu);
0cc5064d 716 }
94dfbdb3
AL		 717
718 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 719 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 720}
721
722static void svm_vcpu_put(struct kvm_vcpu *vcpu)
723{
a2fa3e9f 724 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 725 int i;
726
e1beb1d3 727 ++vcpu->stat.host_state_reload;
94dfbdb3 728 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 729 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 730
ad312c7c 731 rdtscll(vcpu->arch.host_tsc);
6aa8b732
AK		 732}
733
6aa8b732
AK		 734static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
735{
a2fa3e9f 736 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 737}
738
739static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
740{
a2fa3e9f 741 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 742}
743
f0b85051
AG		 744static void svm_set_vintr(struct vcpu_svm *svm)
745{
746 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
747}
748
749static void svm_clear_vintr(struct vcpu_svm *svm)
750{
751 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
752}
753
6aa8b732
AK		 754static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
755{
a2fa3e9f 756 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 757
758 switch (seg) {
759 case VCPU_SREG_CS: return &save->cs;
760 case VCPU_SREG_DS: return &save->ds;
761 case VCPU_SREG_ES: return &save->es;
762 case VCPU_SREG_FS: return &save->fs;
763 case VCPU_SREG_GS: return &save->gs;
764 case VCPU_SREG_SS: return &save->ss;
765 case VCPU_SREG_TR: return &save->tr;
766 case VCPU_SREG_LDTR: return &save->ldtr;
767 }
768 BUG();
8b6d44c7 769 return NULL;
6aa8b732
AK		 770}
771
772static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
773{
774 struct vmcb_seg *s = svm_seg(vcpu, seg);
775
776 return s->base;
777}
778
779static void svm_get_segment(struct kvm_vcpu *vcpu,
780 struct kvm_segment *var, int seg)
781{
782 struct vmcb_seg *s = svm_seg(vcpu, seg);
783
784 var->base = s->base;
785 var->limit = s->limit;
786 var->selector = s->selector;
787 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
788 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
789 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
790 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
791 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
792 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
793 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
794 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc
AS		 795
796 /*
797 * SVM always stores 0 for the 'G' bit in the CS selector in
798 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
799 * Intel's VMENTRY has a check on the 'G' bit.
800 */
801 if (seg == VCPU_SREG_CS)
802 var->g = s->limit > 0xfffff;
803
c0d09828
AS		 804 /*
805 * Work around a bug where the busy flag in the tr selector
806 * isn't exposed
807 */
808 if (seg == VCPU_SREG_TR)
809 var->type |= 0x2;
810
6aa8b732
AK		 811 var->unusable = !var->present;
812}
813
2e4d2653
IE		 814static int svm_get_cpl(struct kvm_vcpu *vcpu)
815{
816 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
817
818 return save->cpl;
819}
820
6aa8b732
AK		 821static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
822{
a2fa3e9f
GH		 823 struct vcpu_svm *svm = to_svm(vcpu);
824
825 dt->limit = svm->vmcb->save.idtr.limit;
826 dt->base = svm->vmcb->save.idtr.base;
6aa8b732
AK		 827}
828
829static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
830{
a2fa3e9f
GH		 831 struct vcpu_svm *svm = to_svm(vcpu);
832
833 svm->vmcb->save.idtr.limit = dt->limit;
834 svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 835}
836
837static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
838{
a2fa3e9f
GH		 839 struct vcpu_svm *svm = to_svm(vcpu);
840
841 dt->limit = svm->vmcb->save.gdtr.limit;
842 dt->base = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 843}
844
845static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
846{
a2fa3e9f
GH		 847 struct vcpu_svm *svm = to_svm(vcpu);
848
849 svm->vmcb->save.gdtr.limit = dt->limit;
850 svm->vmcb->save.gdtr.base = dt->base ;
6aa8b732
AK		 851}
852
25c4c276 853static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 854{
855}
856
6aa8b732
AK		 857static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
858{
a2fa3e9f
GH		 859 struct vcpu_svm *svm = to_svm(vcpu);
860
05b3e0c2 861#ifdef CONFIG_X86_64
ad312c7c 862 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 863 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
ad312c7c 864 vcpu->arch.shadow_efer |= EFER_LMA;
2b5203ee 865 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 866 }
867
d77c26fc 868 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
ad312c7c 869 vcpu->arch.shadow_efer &= ~EFER_LMA;
2b5203ee 870 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 871 }
872 }
873#endif
709ddebf
JR		 874 if (npt_enabled)
875 goto set;
876
ad312c7c 877 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
a2fa3e9f 878 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
7807fa6c
AL		 879 vcpu->fpu_active = 1;
880 }
881
ad312c7c 882 vcpu->arch.cr0 = cr0;
707d92fa 883 cr0 |= X86_CR0_PG | X86_CR0_WP;
6b390b63
JR		 884 if (!vcpu->fpu_active) {
885 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
334df50a 886 cr0 |= X86_CR0_TS;
6b390b63 887 }
709ddebf
JR		 888set:
889 /*
890 * re-enable caching here because the QEMU bios
891 * does not do it - this results in some delay at
892 * reboot
893 */
894 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 895 svm->vmcb->save.cr0 = cr0;
6aa8b732
AK		 896}
897
898static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
899{
6394b649 900 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 901 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
902
903 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
904 force_new_asid(vcpu);
6394b649 905
ec077263
JR		 906 vcpu->arch.cr4 = cr4;
907 if (!npt_enabled)
908 cr4 |= X86_CR4_PAE;
6394b649 909 cr4 |= host_cr4_mce;
ec077263 910 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 911}
912
913static void svm_set_segment(struct kvm_vcpu *vcpu,
914 struct kvm_segment *var, int seg)
915{
a2fa3e9f 916 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 917 struct vmcb_seg *s = svm_seg(vcpu, seg);
918
919 s->base = var->base;
920 s->limit = var->limit;
921 s->selector = var->selector;
922 if (var->unusable)
923 s->attrib = 0;
924 else {
925 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
926 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
927 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
928 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
929 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
930 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
931 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
932 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
933 }
934 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 935 svm->vmcb->save.cpl
936 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 937 >> SVM_SELECTOR_DPL_SHIFT) & 3;
938
939}
940
d0bfb940 941static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 942{
d0bfb940
JK		 943 int old_debug = vcpu->guest_debug;
944 struct vcpu_svm *svm = to_svm(vcpu);
945
946 vcpu->guest_debug = dbg->control;
947
948 svm->vmcb->control.intercept_exceptions &=
949 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
950 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
951 if (vcpu->guest_debug &
952 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
953 svm->vmcb->control.intercept_exceptions |=
954 1 << DB_VECTOR;
955 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
956 svm->vmcb->control.intercept_exceptions |=
957 1 << BP_VECTOR;
958 } else
959 vcpu->guest_debug = 0;
960
ae675ef0
JK		 961 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
962 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
963 else
964 svm->vmcb->save.dr7 = vcpu->arch.dr7;
965
d0bfb940
JK		 966 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
967 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
968 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
969 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
970
971 return 0;
6aa8b732
AK		 972}
973
2a8067f1
ED		 974static int svm_get_irq(struct kvm_vcpu *vcpu)
975{
976 struct vcpu_svm *svm = to_svm(vcpu);
977 u32 exit_int_info = svm->vmcb->control.exit_int_info;
978
979 if (is_external_interrupt(exit_int_info))
980 return exit_int_info & SVM_EVTINJ_VEC_MASK;
981 return -1;
982}
983
6aa8b732
AK		 984static void load_host_msrs(struct kvm_vcpu *vcpu)
985{
94dfbdb3 986#ifdef CONFIG_X86_64
a2fa3e9f 987 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 988#endif
6aa8b732
AK		 989}
990
991static void save_host_msrs(struct kvm_vcpu *vcpu)
992{
94dfbdb3 993#ifdef CONFIG_X86_64
a2fa3e9f 994 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 995#endif
6aa8b732
AK		 996}
997
e756fc62 998static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
6aa8b732
AK		 999{
1000 if (svm_data->next_asid > svm_data->max_asid) {
1001 ++svm_data->asid_generation;
1002 svm_data->next_asid = 1;
a2fa3e9f 1003 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1004 }
1005
e756fc62 1006 svm->vcpu.cpu = svm_data->cpu;
a2fa3e9f
GH		 1007 svm->asid_generation = svm_data->asid_generation;
1008 svm->vmcb->control.asid = svm_data->next_asid++;
6aa8b732
AK		 1009}
1010
6aa8b732
AK		 1011static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1012{
42dbaa5a
JK		 1013 struct vcpu_svm *svm = to_svm(vcpu);
1014 unsigned long val;
1015
1016 switch (dr) {
1017 case 0 ... 3:
1018 val = vcpu->arch.db[dr];
1019 break;
1020 case 6:
1021 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1022 val = vcpu->arch.dr6;
1023 else
1024 val = svm->vmcb->save.dr6;
1025 break;
1026 case 7:
1027 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1028 val = vcpu->arch.dr7;
1029 else
1030 val = svm->vmcb->save.dr7;
1031 break;
1032 default:
1033 val = 0;
1034 }
1035
af9ca2d7
JR		 1036 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
1037 return val;
6aa8b732
AK		 1038}
1039
1040static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1041 int *exception)
1042{
a2fa3e9f
GH		 1043 struct vcpu_svm *svm = to_svm(vcpu);
1044
42dbaa5a 1045 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)value, handler);
6aa8b732 1046
42dbaa5a 1047 *exception = 0;
6aa8b732
AK		 1048
1049 switch (dr) {
1050 case 0 ... 3:
42dbaa5a
JK		 1051 vcpu->arch.db[dr] = value;
1052 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1053 vcpu->arch.eff_db[dr] = value;
6aa8b732
AK		 1054 return;
1055 case 4 ... 5:
42dbaa5a 1056 if (vcpu->arch.cr4 & X86_CR4_DE)
6aa8b732 1057 *exception = UD_VECTOR;
42dbaa5a
JK		 1058 return;
1059 case 6:
1060 if (value & 0xffffffff00000000ULL) {
1061 *exception = GP_VECTOR;
6aa8b732
AK		 1062 return;
1063 }
42dbaa5a
JK		 1064 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1065 return;
1066 case 7:
1067 if (value & 0xffffffff00000000ULL) {
6aa8b732
AK		 1068 *exception = GP_VECTOR;
1069 return;
1070 }
42dbaa5a
JK		 1071 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1072 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1073 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1074 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1075 }
6aa8b732 1076 return;
6aa8b732 1077 default:
42dbaa5a 1078 /* FIXME: Possible case? */
6aa8b732 1079 printk(KERN_DEBUG "%s: unexpected dr %u\n",
b8688d51 1080 __func__, dr);
6aa8b732
AK		 1081 *exception = UD_VECTOR;
1082 return;
1083 }
1084}
1085
e756fc62 1086static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1087{
a2fa3e9f 1088 u32 exit_int_info = svm->vmcb->control.exit_int_info;
e756fc62 1089 struct kvm *kvm = svm->vcpu.kvm;
6aa8b732
AK		 1090 u64 fault_address;
1091 u32 error_code;
577bdc49 1092 bool event_injection = false;
6aa8b732 1093
85f455f7 1094 if (!irqchip_in_kernel(kvm) &&
577bdc49
AK		 1095 is_external_interrupt(exit_int_info)) {
1096 event_injection = true;
e756fc62 1097 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
577bdc49 1098 }
6aa8b732 1099
a2fa3e9f
GH		 1100 fault_address = svm->vmcb->control.exit_info_2;
1101 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7
JR		 1102
1103 if (!npt_enabled)
1104 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1105 (u32)fault_address, (u32)(fault_address >> 32),
1106 handler);
d2ebb410
JR		 1107 else
1108 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1109 (u32)fault_address, (u32)(fault_address >> 32),
1110 handler);
44874f84
JR		 1111 /*
1112 * FIXME: Tis shouldn't be necessary here, but there is a flush
1113 * missing in the MMU code. Until we find this bug, flush the
1114 * complete TLB here on an NPF
1115 */
1116 if (npt_enabled)
1117 svm_flush_tlb(&svm->vcpu);
af9ca2d7 1118
48d15039 1119 if (!npt_enabled && event_injection)
577bdc49 1120 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1121 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1122}
1123
d0bfb940
JK		 1124static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1125{
1126 if (!(svm->vcpu.guest_debug &
1127 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
1128 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1129 return 1;
1130 }
1131 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1132 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1133 kvm_run->debug.arch.exception = DB_VECTOR;
1134 return 0;
1135}
1136
1137static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1138{
1139 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1140 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1141 kvm_run->debug.arch.exception = BP_VECTOR;
1142 return 0;
1143}
1144
7aa81cc0
AL		 1145static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1146{
1147 int er;
1148
571008da 1149 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1150 if (er != EMULATE_DONE)
7ee5d940 1151 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1152 return 1;
1153}
1154
e756fc62 1155static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
7807fa6c 1156{
a2fa3e9f 1157 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
ad312c7c 1158 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
a2fa3e9f 1159 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
e756fc62 1160 svm->vcpu.fpu_active = 1;
a2fa3e9f
GH		 1161
1162 return 1;
7807fa6c
AL		 1163}
1164
53371b50
JR		 1165static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1166{
1167 /*
1168 * On an #MC intercept the MCE handler is not called automatically in
1169 * the host. So do it by hand here.
1170 */
1171 asm volatile (
1172 "int $0x12\n");
1173 /* not sure if we ever come back to this point */
1174
1175 return 1;
1176}
1177
e756fc62 1178static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
46fe4ddd
JR		 1179{
1180 /*
1181 * VMCB is undefined after a SHUTDOWN intercept
1182 * so reinitialize it.
1183 */
a2fa3e9f 1184 clear_page(svm->vmcb);
e6101a96 1185 init_vmcb(svm);
46fe4ddd
JR		 1186
1187 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1188 return 0;
1189}
1190
e756fc62 1191static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1192{
d77c26fc 1193 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
039576c0
AK		 1194 int size, down, in, string, rep;
1195 unsigned port;
6aa8b732 1196
e756fc62 1197 ++svm->vcpu.stat.io_exits;
6aa8b732 1198
a2fa3e9f 1199 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1200
e70669ab
LV		 1201 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1202
1203 if (string) {
3427318f
LV		 1204 if (emulate_instruction(&svm->vcpu,
1205 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1206 return 0;
1207 return 1;
1208 }
1209
039576c0
AK		 1210 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1211 port = io_info >> 16;
1212 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
039576c0 1213 rep = (io_info & SVM_IOIO_REP_MASK) != 0;
a2fa3e9f 1214 down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
6aa8b732 1215
e93f36bc 1216 skip_emulated_instruction(&svm->vcpu);
3090dd73 1217 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
6aa8b732
AK		 1218}
1219
c47f098d
JR		 1220static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1221{
af9ca2d7 1222 KVMTRACE_0D(NMI, &svm->vcpu, handler);
c47f098d
JR		 1223 return 1;
1224}
1225
a0698055
JR		 1226static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1227{
1228 ++svm->vcpu.stat.irq_exits;
af9ca2d7 1229 KVMTRACE_0D(INTR, &svm->vcpu, handler);
a0698055
JR		 1230 return 1;
1231}
1232
e756fc62 1233static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732
AK		 1234{
1235 return 1;
1236}
1237
e756fc62 1238static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1239{
5fdbf976 1240 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1241 skip_emulated_instruction(&svm->vcpu);
1242 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1243}
1244
e756fc62 1245static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
02e235bc 1246{
5fdbf976 1247 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1248 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1249 kvm_emulate_hypercall(&svm->vcpu);
1250 return 1;
02e235bc
AK		 1251}
1252
c0725420
AG		 1253static int nested_svm_check_permissions(struct vcpu_svm *svm)
1254{
1255 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1256 || !is_paging(&svm->vcpu)) {
1257 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1258 return 1;
1259 }
1260
1261 if (svm->vmcb->save.cpl) {
1262 kvm_inject_gp(&svm->vcpu, 0);
1263 return 1;
1264 }
1265
1266 return 0;
1267}
1268
cf74a78b
AG		 1269static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1270 bool has_error_code, u32 error_code)
1271{
1272 if (is_nested(svm)) {
1273 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1274 svm->vmcb->control.exit_code_hi = 0;
1275 svm->vmcb->control.exit_info_1 = error_code;
1276 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1277 if (nested_svm_exit_handled(svm, false)) {
1278 nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1279
1280 nested_svm_vmexit(svm);
1281 return 1;
1282 }
1283 }
1284
1285 return 0;
1286}
1287
1288static inline int nested_svm_intr(struct vcpu_svm *svm)
1289{
1290 if (is_nested(svm)) {
1291 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1292 return 0;
1293
1294 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1295 return 0;
1296
1297 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1298
1299 if (nested_svm_exit_handled(svm, false)) {
1300 nsvm_printk("VMexit -> INTR\n");
1301 nested_svm_vmexit(svm);
1302 return 1;
1303 }
1304 }
1305
1306 return 0;
1307}
1308
c0725420
AG		 1309static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1310{
1311 struct page *page;
1312
1313 down_read(&current->mm->mmap_sem);
1314 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1315 up_read(&current->mm->mmap_sem);
1316
1317 if (is_error_page(page)) {
1318 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1319 __func__, gpa);
1320 kvm_release_page_clean(page);
1321 kvm_inject_gp(&svm->vcpu, 0);
1322 return NULL;
1323 }
1324 return page;
1325}
1326
1327static int nested_svm_do(struct vcpu_svm *svm,
1328 u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1329 int (*handler)(struct vcpu_svm *svm,
1330 void *arg1,
1331 void *arg2,
1332 void *opaque))
1333{
1334 struct page *arg1_page;
1335 struct page *arg2_page = NULL;
1336 void *arg1;
1337 void *arg2 = NULL;
1338 int retval;
1339
1340 arg1_page = nested_svm_get_page(svm, arg1_gpa);
1341 if(arg1_page == NULL)
1342 return 1;
1343
1344 if (arg2_gpa) {
1345 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1346 if(arg2_page == NULL) {
1347 kvm_release_page_clean(arg1_page);
1348 return 1;
1349 }
1350 }
1351
1352 arg1 = kmap_atomic(arg1_page, KM_USER0);
1353 if (arg2_gpa)
1354 arg2 = kmap_atomic(arg2_page, KM_USER1);
1355
1356 retval = handler(svm, arg1, arg2, opaque);
1357
1358 kunmap_atomic(arg1, KM_USER0);
1359 if (arg2_gpa)
1360 kunmap_atomic(arg2, KM_USER1);
1361
1362 kvm_release_page_dirty(arg1_page);
1363 if (arg2_gpa)
1364 kvm_release_page_dirty(arg2_page);
1365
1366 return retval;
1367}
1368
cf74a78b
AG		 1369static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1370 void *arg1,
1371 void *arg2,
1372 void *opaque)
1373{
1374 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1375 bool kvm_overrides = *(bool *)opaque;
1376 u32 exit_code = svm->vmcb->control.exit_code;
1377
1378 if (kvm_overrides) {
1379 switch (exit_code) {
1380 case SVM_EXIT_INTR:
1381 case SVM_EXIT_NMI:
1382 return 0;
1383 /* For now we are always handling NPFs when using them */
1384 case SVM_EXIT_NPF:
1385 if (npt_enabled)
1386 return 0;
1387 break;
1388 /* When we're shadowing, trap PFs */
1389 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1390 if (!npt_enabled)
1391 return 0;
1392 break;
1393 default:
1394 break;
1395 }
1396 }
1397
1398 switch (exit_code) {
1399 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1400 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1401 if (nested_vmcb->control.intercept_cr_read & cr_bits)
1402 return 1;
1403 break;
1404 }
1405 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1406 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1407 if (nested_vmcb->control.intercept_cr_write & cr_bits)
1408 return 1;
1409 break;
1410 }
1411 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1412 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1413 if (nested_vmcb->control.intercept_dr_read & dr_bits)
1414 return 1;
1415 break;
1416 }
1417 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1418 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1419 if (nested_vmcb->control.intercept_dr_write & dr_bits)
1420 return 1;
1421 break;
1422 }
1423 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1424 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1425 if (nested_vmcb->control.intercept_exceptions & excp_bits)
1426 return 1;
1427 break;
1428 }
1429 default: {
1430 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1431 nsvm_printk("exit code: 0x%x\n", exit_code);
1432 if (nested_vmcb->control.intercept & exit_bits)
1433 return 1;
1434 }
1435 }
1436
1437 return 0;
1438}
1439
1440static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1441 void *arg1, void *arg2,
1442 void *opaque)
1443{
1444 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1445 u8 *msrpm = (u8 *)arg2;
1446 u32 t0, t1;
1447 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1448 u32 param = svm->vmcb->control.exit_info_1 & 1;
1449
1450 if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1451 return 0;
1452
1453 switch(msr) {
1454 case 0 ... 0x1fff:
1455 t0 = (msr * 2) % 8;
1456 t1 = msr / 8;
1457 break;
1458 case 0xc0000000 ... 0xc0001fff:
1459 t0 = (8192 + msr - 0xc0000000) * 2;
1460 t1 = (t0 / 8);
1461 t0 %= 8;
1462 break;
1463 case 0xc0010000 ... 0xc0011fff:
1464 t0 = (16384 + msr - 0xc0010000) * 2;
1465 t1 = (t0 / 8);
1466 t0 %= 8;
1467 break;
1468 default:
1469 return 1;
1470 break;
1471 }
1472 if (msrpm[t1] & ((1 << param) << t0))
1473 return 1;
1474
1475 return 0;
1476}
1477
1478static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1479{
1480 bool k = kvm_override;
1481
1482 switch (svm->vmcb->control.exit_code) {
1483 case SVM_EXIT_MSR:
1484 return nested_svm_do(svm, svm->nested_vmcb,
1485 svm->nested_vmcb_msrpm, NULL,
1486 nested_svm_exit_handled_msr);
1487 default: break;
1488 }
1489
1490 return nested_svm_do(svm, svm->nested_vmcb, 0, &k,
1491 nested_svm_exit_handled_real);
1492}
1493
1494static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1495 void *arg2, void *opaque)
1496{
1497 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1498 struct vmcb *hsave = svm->hsave;
1499 u64 nested_save[] = { nested_vmcb->save.cr0,
1500 nested_vmcb->save.cr3,
1501 nested_vmcb->save.cr4,
1502 nested_vmcb->save.efer,
1503 nested_vmcb->control.intercept_cr_read,
1504 nested_vmcb->control.intercept_cr_write,
1505 nested_vmcb->control.intercept_dr_read,
1506 nested_vmcb->control.intercept_dr_write,
1507 nested_vmcb->control.intercept_exceptions,
1508 nested_vmcb->control.intercept,
1509 nested_vmcb->control.msrpm_base_pa,
1510 nested_vmcb->control.iopm_base_pa,
1511 nested_vmcb->control.tsc_offset };
1512
1513 /* Give the current vmcb to the guest */
1514 memcpy(nested_vmcb, svm->vmcb, sizeof(struct vmcb));
1515 nested_vmcb->save.cr0 = nested_save[0];
1516 if (!npt_enabled)
1517 nested_vmcb->save.cr3 = nested_save[1];
1518 nested_vmcb->save.cr4 = nested_save[2];
1519 nested_vmcb->save.efer = nested_save[3];
1520 nested_vmcb->control.intercept_cr_read = nested_save[4];
1521 nested_vmcb->control.intercept_cr_write = nested_save[5];
1522 nested_vmcb->control.intercept_dr_read = nested_save[6];
1523 nested_vmcb->control.intercept_dr_write = nested_save[7];
1524 nested_vmcb->control.intercept_exceptions = nested_save[8];
1525 nested_vmcb->control.intercept = nested_save[9];
1526 nested_vmcb->control.msrpm_base_pa = nested_save[10];
1527 nested_vmcb->control.iopm_base_pa = nested_save[11];
1528 nested_vmcb->control.tsc_offset = nested_save[12];
1529
1530 /* We always set V_INTR_MASKING and remember the old value in hflags */
1531 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1532 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1533
1534 if ((nested_vmcb->control.int_ctl & V_IRQ_MASK) &&
1535 (nested_vmcb->control.int_vector)) {
1536 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1537 nested_vmcb->control.int_vector);
1538 }
1539
1540 /* Restore the original control entries */
1541 svm->vmcb->control = hsave->control;
1542
1543 /* Kill any pending exceptions */
1544 if (svm->vcpu.arch.exception.pending == true)
1545 nsvm_printk("WARNING: Pending Exception\n");
1546 svm->vcpu.arch.exception.pending = false;
1547
1548 /* Restore selected save entries */
1549 svm->vmcb->save.es = hsave->save.es;
1550 svm->vmcb->save.cs = hsave->save.cs;
1551 svm->vmcb->save.ss = hsave->save.ss;
1552 svm->vmcb->save.ds = hsave->save.ds;
1553 svm->vmcb->save.gdtr = hsave->save.gdtr;
1554 svm->vmcb->save.idtr = hsave->save.idtr;
1555 svm->vmcb->save.rflags = hsave->save.rflags;
1556 svm_set_efer(&svm->vcpu, hsave->save.efer);
1557 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1558 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1559 if (npt_enabled) {
1560 svm->vmcb->save.cr3 = hsave->save.cr3;
1561 svm->vcpu.arch.cr3 = hsave->save.cr3;
1562 } else {
1563 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1564 }
1565 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1566 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1567 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1568 svm->vmcb->save.dr7 = 0;
1569 svm->vmcb->save.cpl = 0;
1570 svm->vmcb->control.exit_int_info = 0;
1571
1572 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1573 /* Exit nested SVM mode */
1574 svm->nested_vmcb = 0;
1575
1576 return 0;
1577}
1578
1579static int nested_svm_vmexit(struct vcpu_svm *svm)
1580{
1581 nsvm_printk("VMexit\n");
1582 if (nested_svm_do(svm, svm->nested_vmcb, 0,
1583 NULL, nested_svm_vmexit_real))
1584 return 1;
1585
1586 kvm_mmu_reset_context(&svm->vcpu);
1587 kvm_mmu_load(&svm->vcpu);
1588
1589 return 0;
1590}
3d6368ef
AG		 1591
1592static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1593 void *arg2, void *opaque)
1594{
1595 int i;
1596 u32 *nested_msrpm = (u32*)arg1;
1597 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1598 svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1599 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
1600
1601 return 0;
1602}
1603
1604static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1605 void *arg2, void *opaque)
1606{
1607 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1608 struct vmcb *hsave = svm->hsave;
1609
1610 /* nested_vmcb is our indicator if nested SVM is activated */
1611 svm->nested_vmcb = svm->vmcb->save.rax;
1612
1613 /* Clear internal status */
1614 svm->vcpu.arch.exception.pending = false;
1615
1616 /* Save the old vmcb, so we don't need to pick what we save, but
1617 can restore everything when a VMEXIT occurs */
1618 memcpy(hsave, svm->vmcb, sizeof(struct vmcb));
1619 /* We need to remember the original CR3 in the SPT case */
1620 if (!npt_enabled)
1621 hsave->save.cr3 = svm->vcpu.arch.cr3;
1622 hsave->save.cr4 = svm->vcpu.arch.cr4;
1623 hsave->save.rip = svm->next_rip;
1624
1625 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1626 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1627 else
1628 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1629
1630 /* Load the nested guest state */
1631 svm->vmcb->save.es = nested_vmcb->save.es;
1632 svm->vmcb->save.cs = nested_vmcb->save.cs;
1633 svm->vmcb->save.ss = nested_vmcb->save.ss;
1634 svm->vmcb->save.ds = nested_vmcb->save.ds;
1635 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1636 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1637 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1638 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1639 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1640 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1641 if (npt_enabled) {
1642 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1643 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1644 } else {
1645 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1646 kvm_mmu_reset_context(&svm->vcpu);
1647 }
1648 svm->vmcb->save.cr2 = nested_vmcb->save.cr2;
1649 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1650 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1651 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1652 /* In case we don't even reach vcpu_run, the fields are not updated */
1653 svm->vmcb->save.rax = nested_vmcb->save.rax;
1654 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1655 svm->vmcb->save.rip = nested_vmcb->save.rip;
1656 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1657 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1658 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1659
1660 /* We don't want a nested guest to be more powerful than the guest,
1661 so all intercepts are ORed */
1662 svm->vmcb->control.intercept_cr_read |=
1663 nested_vmcb->control.intercept_cr_read;
1664 svm->vmcb->control.intercept_cr_write |=
1665 nested_vmcb->control.intercept_cr_write;
1666 svm->vmcb->control.intercept_dr_read |=
1667 nested_vmcb->control.intercept_dr_read;
1668 svm->vmcb->control.intercept_dr_write |=
1669 nested_vmcb->control.intercept_dr_write;
1670 svm->vmcb->control.intercept_exceptions |=
1671 nested_vmcb->control.intercept_exceptions;
1672
1673 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1674
1675 svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1676
1677 force_new_asid(&svm->vcpu);
1678 svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1679 svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1680 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1681 if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1682 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1683 nested_vmcb->control.int_ctl);
1684 }
1685 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1686 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1687 else
1688 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1689
1690 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1691 nested_vmcb->control.exit_int_info,
1692 nested_vmcb->control.int_state);
1693
1694 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1695 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1696 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1697 if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1698 nsvm_printk("Injecting Event: 0x%x\n",
1699 nested_vmcb->control.event_inj);
1700 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1701 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1702
1703 svm->vcpu.arch.hflags |= HF_GIF_MASK;
1704
1705 return 0;
1706}
1707
5542675b
AG		 1708static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1709{
1710 to_vmcb->save.fs = from_vmcb->save.fs;
1711 to_vmcb->save.gs = from_vmcb->save.gs;
1712 to_vmcb->save.tr = from_vmcb->save.tr;
1713 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1714 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1715 to_vmcb->save.star = from_vmcb->save.star;
1716 to_vmcb->save.lstar = from_vmcb->save.lstar;
1717 to_vmcb->save.cstar = from_vmcb->save.cstar;
1718 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1719 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1720 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1721 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1722
1723 return 1;
1724}
1725
1726static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1727 void *arg2, void *opaque)
1728{
1729 return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1730}
1731
1732static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1733 void *arg2, void *opaque)
1734{
1735 return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1736}
1737
1738static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1739{
1740 if (nested_svm_check_permissions(svm))
1741 return 1;
1742
1743 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1744 skip_emulated_instruction(&svm->vcpu);
1745
1746 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1747
1748 return 1;
1749}
1750
1751static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1752{
1753 if (nested_svm_check_permissions(svm))
1754 return 1;
1755
1756 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1757 skip_emulated_instruction(&svm->vcpu);
1758
1759 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1760
1761 return 1;
1762}
1763
3d6368ef
AG		 1764static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1765{
1766 nsvm_printk("VMrun\n");
1767 if (nested_svm_check_permissions(svm))
1768 return 1;
1769
1770 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1771 skip_emulated_instruction(&svm->vcpu);
1772
1773 if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1774 NULL, nested_svm_vmrun))
1775 return 1;
1776
1777 if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
1778 NULL, nested_svm_vmrun_msrpm))
1779 return 1;
1780
1781 return 1;
1782}
1783
1371d904
AG		 1784static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1785{
1786 if (nested_svm_check_permissions(svm))
1787 return 1;
1788
1789 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1790 skip_emulated_instruction(&svm->vcpu);
1791
1792 svm->vcpu.arch.hflags |= HF_GIF_MASK;
1793
1794 return 1;
1795}
1796
1797static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1798{
1799 if (nested_svm_check_permissions(svm))
1800 return 1;
1801
1802 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1803 skip_emulated_instruction(&svm->vcpu);
1804
1805 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1806
1807 /* After a CLGI no interrupts should come */
1808 svm_clear_vintr(svm);
1809 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1810
1811 return 1;
1812}
1813
e756fc62
RR		 1814static int invalid_op_interception(struct vcpu_svm *svm,
1815 struct kvm_run *kvm_run)
6aa8b732 1816{
7ee5d940 1817 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 1818 return 1;
1819}
1820
e756fc62
RR		 1821static int task_switch_interception(struct vcpu_svm *svm,
1822 struct kvm_run *kvm_run)
6aa8b732 1823{
37817f29
IE		 1824 u16 tss_selector;
1825
1826 tss_selector = (u16)svm->vmcb->control.exit_info_1;
1827 if (svm->vmcb->control.exit_info_2 &
1828 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1829 return kvm_task_switch(&svm->vcpu, tss_selector,
1830 TASK_SWITCH_IRET);
1831 if (svm->vmcb->control.exit_info_2 &
1832 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1833 return kvm_task_switch(&svm->vcpu, tss_selector,
1834 TASK_SWITCH_JMP);
1835 return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
6aa8b732
AK		 1836}
1837
e756fc62 1838static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1839{
5fdbf976 1840 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 1841 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 1842 return 1;
6aa8b732
AK		 1843}
1844
a7052897
MT		 1845static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1846{
1847 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1848 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1849 return 1;
1850}
1851
e756fc62
RR		 1852static int emulate_on_interception(struct vcpu_svm *svm,
1853 struct kvm_run *kvm_run)
6aa8b732 1854{
3427318f 1855 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
b8688d51 1856 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 1857 return 1;
1858}
1859
1d075434
JR		 1860static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1861{
1862 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1863 if (irqchip_in_kernel(svm->vcpu.kvm))
1864 return 1;
1865 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1866 return 0;
1867}
1868
6aa8b732
AK		 1869static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1870{
a2fa3e9f
GH		 1871 struct vcpu_svm *svm = to_svm(vcpu);
1872
6aa8b732 1873 switch (ecx) {
6aa8b732
AK		 1874 case MSR_IA32_TIME_STAMP_COUNTER: {
1875 u64 tsc;
1876
1877 rdtscll(tsc);
a2fa3e9f 1878 *data = svm->vmcb->control.tsc_offset + tsc;
6aa8b732
AK		 1879 break;
1880 }
0e859cac 1881 case MSR_K6_STAR:
a2fa3e9f 1882 *data = svm->vmcb->save.star;
6aa8b732 1883 break;
0e859cac 1884#ifdef CONFIG_X86_64
6aa8b732 1885 case MSR_LSTAR:
a2fa3e9f 1886 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 1887 break;
1888 case MSR_CSTAR:
a2fa3e9f 1889 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 1890 break;
1891 case MSR_KERNEL_GS_BASE:
a2fa3e9f 1892 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 1893 break;
1894 case MSR_SYSCALL_MASK:
a2fa3e9f 1895 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 1896 break;
1897#endif
1898 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 1899 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 1900 break;
1901 case MSR_IA32_SYSENTER_EIP:
a2fa3e9f 1902 *data = svm->vmcb->save.sysenter_eip;
6aa8b732
AK		 1903 break;
1904 case MSR_IA32_SYSENTER_ESP:
a2fa3e9f 1905 *data = svm->vmcb->save.sysenter_esp;
6aa8b732 1906 break;
a2938c80
JR		 1907 /* Nobody will change the following 5 values in the VMCB so
1908 we can safely return them on rdmsr. They will always be 0
1909 until LBRV is implemented. */
1910 case MSR_IA32_DEBUGCTLMSR:
1911 *data = svm->vmcb->save.dbgctl;
1912 break;
1913 case MSR_IA32_LASTBRANCHFROMIP:
1914 *data = svm->vmcb->save.br_from;
1915 break;
1916 case MSR_IA32_LASTBRANCHTOIP:
1917 *data = svm->vmcb->save.br_to;
1918 break;
1919 case MSR_IA32_LASTINTFROMIP:
1920 *data = svm->vmcb->save.last_excp_from;
1921 break;
1922 case MSR_IA32_LASTINTTOIP:
1923 *data = svm->vmcb->save.last_excp_to;
1924 break;
b286d5d8
AG		 1925 case MSR_VM_HSAVE_PA:
1926 *data = svm->hsave_msr;
1927 break;
eb6f302e
JR		 1928 case MSR_VM_CR:
1929 *data = 0;
1930 break;
6aa8b732 1931 default:
3bab1f5d 1932 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 1933 }
1934 return 0;
1935}
1936
e756fc62 1937static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1938{
ad312c7c 1939 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 1940 u64 data;
1941
e756fc62 1942 if (svm_get_msr(&svm->vcpu, ecx, &data))
c1a5d4f9 1943 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 1944 else {
af9ca2d7
JR		 1945 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1946 (u32)(data >> 32), handler);
1947
5fdbf976 1948 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 1949 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 1950 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 1951 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 1952 }
1953 return 1;
1954}
1955
1956static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1957{
a2fa3e9f
GH		 1958 struct vcpu_svm *svm = to_svm(vcpu);
1959
6aa8b732 1960 switch (ecx) {
6aa8b732
AK		 1961 case MSR_IA32_TIME_STAMP_COUNTER: {
1962 u64 tsc;
1963
1964 rdtscll(tsc);
a2fa3e9f 1965 svm->vmcb->control.tsc_offset = data - tsc;
6aa8b732
AK		 1966 break;
1967 }
0e859cac 1968 case MSR_K6_STAR:
a2fa3e9f 1969 svm->vmcb->save.star = data;
6aa8b732 1970 break;
49b14f24 1971#ifdef CONFIG_X86_64
6aa8b732 1972 case MSR_LSTAR:
a2fa3e9f 1973 svm->vmcb->save.lstar = data;
6aa8b732
AK		 1974 break;
1975 case MSR_CSTAR:
a2fa3e9f 1976 svm->vmcb->save.cstar = data;
6aa8b732
AK		 1977 break;
1978 case MSR_KERNEL_GS_BASE:
a2fa3e9f 1979 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 1980 break;
1981 case MSR_SYSCALL_MASK:
a2fa3e9f 1982 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 1983 break;
1984#endif
1985 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 1986 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 1987 break;
1988 case MSR_IA32_SYSENTER_EIP:
a2fa3e9f 1989 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 1990 break;
1991 case MSR_IA32_SYSENTER_ESP:
a2fa3e9f 1992 svm->vmcb->save.sysenter_esp = data;
6aa8b732 1993 break;
a2938c80 1994 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 1995 if (!svm_has(SVM_FEATURE_LBRV)) {
1996 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 1997 __func__, data);
24e09cbf
JR		 1998 break;
1999 }
2000 if (data & DEBUGCTL_RESERVED_BITS)
2001 return 1;
2002
2003 svm->vmcb->save.dbgctl = data;
2004 if (data & (1ULL<<0))
2005 svm_enable_lbrv(svm);
2006 else
2007 svm_disable_lbrv(svm);
a2938c80 2008 break;
62b9abaa
JR		 2009 case MSR_K7_EVNTSEL0:
2010 case MSR_K7_EVNTSEL1:
2011 case MSR_K7_EVNTSEL2:
2012 case MSR_K7_EVNTSEL3:
14ae51b6
CL		 2013 case MSR_K7_PERFCTR0:
2014 case MSR_K7_PERFCTR1:
2015 case MSR_K7_PERFCTR2:
2016 case MSR_K7_PERFCTR3:
62b9abaa 2017 /*
14ae51b6
CL		 2018 * Just discard all writes to the performance counters; this
2019 * should keep both older linux and windows 64-bit guests
2020 * happy
62b9abaa 2021 */
14ae51b6
CL		 2022 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
2023
b286d5d8
AG		 2024 break;
2025 case MSR_VM_HSAVE_PA:
2026 svm->hsave_msr = data;
62b9abaa 2027 break;
6aa8b732 2028 default:
3bab1f5d 2029 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2030 }
2031 return 0;
2032}
2033
e756fc62 2034static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2035{
ad312c7c 2036 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2037 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2038 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7
JR		 2039
2040 KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
2041 handler);
2042
5fdbf976 2043 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2044 if (svm_set_msr(&svm->vcpu, ecx, data))
c1a5d4f9 2045 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2046 else
e756fc62 2047 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2048 return 1;
2049}
2050
e756fc62 2051static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2052{
e756fc62
RR		 2053 if (svm->vmcb->control.exit_info_1)
2054 return wrmsr_interception(svm, kvm_run);
6aa8b732 2055 else
e756fc62 2056 return rdmsr_interception(svm, kvm_run);
6aa8b732
AK		 2057}
2058
e756fc62 2059static int interrupt_window_interception(struct vcpu_svm *svm,
c1150d8c
DL		 2060 struct kvm_run *kvm_run)
2061{
af9ca2d7
JR		 2062 KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
2063
f0b85051 2064 svm_clear_vintr(svm);
85f455f7 2065 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2066 /*
2067 * If the user space waits to inject interrupts, exit as soon as
2068 * possible
2069 */
2070 if (kvm_run->request_interrupt_window &&
ad312c7c 2071 !svm->vcpu.arch.irq_summary) {
e756fc62 2072 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2073 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2074 return 0;
2075 }
2076
2077 return 1;
2078}
2079
e756fc62 2080static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
6aa8b732
AK		 2081 struct kvm_run *kvm_run) = {
2082 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2083 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2084 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2085 [SVM_EXIT_READ_CR8] = emulate_on_interception,
6aa8b732
AK		 2086 /* for now: */
2087 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2088 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2089 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2090 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2091 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2092 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2093 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2094 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2095 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2096 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2097 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2098 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2099 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2100 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2101 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2102 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2103 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2104 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2105 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2106 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2107 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2108 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2109 [SVM_EXIT_SMI] = nop_on_interception,
2110 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2111 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2112 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2113 [SVM_EXIT_CPUID] = cpuid_interception,
cf5a94d1 2114 [SVM_EXIT_INVD] = emulate_on_interception,
6aa8b732 2115 [SVM_EXIT_HLT] = halt_interception,
a7052897 2116 [SVM_EXIT_INVLPG] = invlpg_interception,
6aa8b732
AK		 2117 [SVM_EXIT_INVLPGA] = invalid_op_interception,
2118 [SVM_EXIT_IOIO] = io_interception,
2119 [SVM_EXIT_MSR] = msr_interception,
2120 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2121 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2122 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2123 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2124 [SVM_EXIT_VMLOAD] = vmload_interception,
2125 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2126 [SVM_EXIT_STGI] = stgi_interception,
2127 [SVM_EXIT_CLGI] = clgi_interception,
6aa8b732 2128 [SVM_EXIT_SKINIT] = invalid_op_interception,
cf5a94d1 2129 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2130 [SVM_EXIT_MONITOR] = invalid_op_interception,
2131 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2132 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2133};
2134
04d2cc77 2135static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
6aa8b732 2136{
04d2cc77 2137 struct vcpu_svm *svm = to_svm(vcpu);
a2fa3e9f 2138 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2139
af9ca2d7
JR		 2140 KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
2141 (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
2142
cf74a78b
AG		 2143 if (is_nested(svm)) {
2144 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2145 exit_code, svm->vmcb->control.exit_info_1,
2146 svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2147 if (nested_svm_exit_handled(svm, true)) {
2148 nested_svm_vmexit(svm);
2149 nsvm_printk("-> #VMEXIT\n");
2150 return 1;
2151 }
2152 }
2153
709ddebf
JR		 2154 if (npt_enabled) {
2155 int mmu_reload = 0;
2156 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2157 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2158 mmu_reload = 1;
2159 }
2160 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2161 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2162 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2163 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
2164 kvm_inject_gp(vcpu, 0);
2165 return 1;
2166 }
2167 }
2168 if (mmu_reload) {
2169 kvm_mmu_reset_context(vcpu);
2170 kvm_mmu_load(vcpu);
2171 }
2172 }
2173
04d2cc77
AK		 2174 kvm_reput_irq(svm);
2175
2176 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2177 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2178 kvm_run->fail_entry.hardware_entry_failure_reason
2179 = svm->vmcb->control.exit_code;
2180 return 0;
2181 }
2182
a2fa3e9f 2183 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf
JR		 2184 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2185 exit_code != SVM_EXIT_NPF)
6aa8b732
AK		 2186 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2187 "exit_code 0x%x\n",
b8688d51 2188 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2189 exit_code);
2190
9d8f549d 2191 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2192 || !svm_exit_handlers[exit_code]) {
6aa8b732 2193 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2194 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2195 return 0;
2196 }
2197
e756fc62 2198 return svm_exit_handlers[exit_code](svm, kvm_run);
6aa8b732
AK		 2199}
2200
2201static void reload_tss(struct kvm_vcpu *vcpu)
2202{
2203 int cpu = raw_smp_processor_id();
2204
2205 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
d77c26fc 2206 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2207 load_TR_desc();
2208}
2209
e756fc62 2210static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2211{
2212 int cpu = raw_smp_processor_id();
2213
2214 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2215
a2fa3e9f 2216 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
e756fc62 2217 if (svm->vcpu.cpu != cpu ||
a2fa3e9f 2218 svm->asid_generation != svm_data->asid_generation)
e756fc62 2219 new_asid(svm, svm_data);
6aa8b732
AK		 2220}
2221
2222
85f455f7 2223static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2224{
2225 struct vmcb_control_area *control;
2226
af9ca2d7
JR		 2227 KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
2228
fa89a817 2229 ++svm->vcpu.stat.irq_injections;
e756fc62 2230 control = &svm->vmcb->control;
85f455f7 2231 control->int_vector = irq;
6aa8b732
AK		 2232 control->int_ctl &= ~V_INTR_PRIO_MASK;
2233 control->int_ctl |= V_IRQ_MASK |
2234 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2235}
2236
2a8067f1
ED		 2237static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
2238{
2239 struct vcpu_svm *svm = to_svm(vcpu);
2240
cf74a78b
AG		 2241 nested_svm_intr(svm);
2242
2a8067f1
ED		 2243 svm_inject_irq(svm, irq);
2244}
2245
aaacfc9a
JR		 2246static void update_cr8_intercept(struct kvm_vcpu *vcpu)
2247{
2248 struct vcpu_svm *svm = to_svm(vcpu);
2249 struct vmcb *vmcb = svm->vmcb;
2250 int max_irr, tpr;
2251
2252 if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
2253 return;
2254
2255 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2256
2257 max_irr = kvm_lapic_find_highest_irr(vcpu);
2258 if (max_irr == -1)
2259 return;
2260
2261 tpr = kvm_lapic_get_cr8(vcpu) << 4;
2262
2263 if (tpr >= (max_irr & 0xf0))
2264 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2265}
2266
04d2cc77 2267static void svm_intr_assist(struct kvm_vcpu *vcpu)
6aa8b732 2268{
04d2cc77 2269 struct vcpu_svm *svm = to_svm(vcpu);
85f455f7
ED		 2270 struct vmcb *vmcb = svm->vmcb;
2271 int intr_vector = -1;
2272
2273 if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
2274 ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
2275 intr_vector = vmcb->control.exit_int_info &
2276 SVM_EVTINJ_VEC_MASK;
2277 vmcb->control.exit_int_info = 0;
2278 svm_inject_irq(svm, intr_vector);
aaacfc9a 2279 goto out;
85f455f7
ED		 2280 }
2281
2282 if (vmcb->control.int_ctl & V_IRQ_MASK)
aaacfc9a 2283 goto out;
85f455f7 2284
1b9778da 2285 if (!kvm_cpu_has_interrupt(vcpu))
aaacfc9a 2286 goto out;
85f455f7 2287
cf74a78b
AG		 2288 if (nested_svm_intr(svm))
2289 goto out;
2290
1371d904
AG		 2291 if (!(svm->vcpu.arch.hflags & HF_GIF_MASK))
2292 goto out;
2293
85f455f7
ED		 2294 if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
2295 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
2296 (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
2297 /* unable to deliver irq, set pending irq */
f0b85051 2298 svm_set_vintr(svm);
85f455f7 2299 svm_inject_irq(svm, 0x0);
aaacfc9a 2300 goto out;
85f455f7
ED		 2301 }
2302 /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1b9778da 2303 intr_vector = kvm_cpu_get_interrupt(vcpu);
85f455f7 2304 svm_inject_irq(svm, intr_vector);
aaacfc9a
JR		 2305out:
2306 update_cr8_intercept(vcpu);
85f455f7
ED		 2307}
2308
2309static void kvm_reput_irq(struct vcpu_svm *svm)
2310{
e756fc62 2311 struct vmcb_control_area *control = &svm->vmcb->control;
6aa8b732 2312
7017fc3d
ED		 2313 if ((control->int_ctl & V_IRQ_MASK)
2314 && !irqchip_in_kernel(svm->vcpu.kvm)) {
6aa8b732 2315 control->int_ctl &= ~V_IRQ_MASK;
e756fc62 2316 push_irq(&svm->vcpu, control->int_vector);
6aa8b732 2317 }
c1150d8c 2318
ad312c7c 2319 svm->vcpu.arch.interrupt_window_open =
1371d904
AG		 2320 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2321 (svm->vcpu.arch.hflags & HF_GIF_MASK);
c1150d8c
DL		 2322}
2323
85f455f7
ED		 2324static void svm_do_inject_vector(struct vcpu_svm *svm)
2325{
2326 struct kvm_vcpu *vcpu = &svm->vcpu;
ad312c7c
ZX		 2327 int word_index = __ffs(vcpu->arch.irq_summary);
2328 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
85f455f7
ED		 2329 int irq = word_index * BITS_PER_LONG + bit_index;
2330
ad312c7c
ZX		 2331 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2332 if (!vcpu->arch.irq_pending[word_index])
2333 clear_bit(word_index, &vcpu->arch.irq_summary);
85f455f7
ED		 2334 svm_inject_irq(svm, irq);
2335}
2336
04d2cc77 2337static void do_interrupt_requests(struct kvm_vcpu *vcpu,
c1150d8c
DL		 2338 struct kvm_run *kvm_run)
2339{
04d2cc77 2340 struct vcpu_svm *svm = to_svm(vcpu);
a2fa3e9f 2341 struct vmcb_control_area *control = &svm->vmcb->control;
c1150d8c 2342
cf74a78b
AG		 2343 if (nested_svm_intr(svm))
2344 return;
2345
ad312c7c 2346 svm->vcpu.arch.interrupt_window_open =
c1150d8c 2347 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1371d904
AG		 2348 (svm->vmcb->save.rflags & X86_EFLAGS_IF) &&
2349 (svm->vcpu.arch.hflags & HF_GIF_MASK));
c1150d8c 2350
ad312c7c 2351 if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
c1150d8c
DL		 2352 /*
2353 * If interrupts enabled, and not blocked by sti or mov ss. Good.
2354 */
85f455f7 2355 svm_do_inject_vector(svm);
c1150d8c
DL		 2356
2357 /*
2358 * Interrupts blocked. Wait for unblock.
2359 */
ad312c7c
ZX		 2360 if (!svm->vcpu.arch.interrupt_window_open &&
2361 (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
f0b85051
AG		 2362 svm_set_vintr(svm);
2363 else
2364 svm_clear_vintr(svm);
c1150d8c
DL		 2365}
2366
cbc94022
IE		 2367static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2368{
2369 return 0;
2370}
2371
d9e368d6
AK		 2372static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2373{
2374 force_new_asid(vcpu);
2375}
2376
04d2cc77
AK		 2377static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2378{
2379}
2380
d7bf8221
JR		 2381static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2382{
2383 struct vcpu_svm *svm = to_svm(vcpu);
2384
2385 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2386 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2387 kvm_lapic_set_tpr(vcpu, cr8);
2388 }
2389}
2390
649d6864
JR		 2391static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2392{
2393 struct vcpu_svm *svm = to_svm(vcpu);
2394 u64 cr8;
2395
2396 if (!irqchip_in_kernel(vcpu->kvm))
2397 return;
2398
2399 cr8 = kvm_get_cr8(vcpu);
2400 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2401 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2402}
2403
80e31d4f
AK		 2404#ifdef CONFIG_X86_64
2405#define R "r"
2406#else
2407#define R "e"
2408#endif
2409
04d2cc77 2410static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2411{
a2fa3e9f 2412 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2413 u16 fs_selector;
2414 u16 gs_selector;
2415 u16 ldt_selector;
d9e368d6 2416
5fdbf976
MT		 2417 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2418 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2419 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2420
e756fc62 2421 pre_svm_run(svm);
6aa8b732 2422
649d6864
JR		 2423 sync_lapic_to_cr8(vcpu);
2424
6aa8b732 2425 save_host_msrs(vcpu);
d6e88aec
AK		 2426 fs_selector = kvm_read_fs();
2427 gs_selector = kvm_read_gs();
2428 ldt_selector = kvm_read_ldt();
a2fa3e9f 2429 svm->host_cr2 = kvm_read_cr2();
3d6368ef
AG		 2430 if (!is_nested(svm))
2431 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2432 /* required for live migration with NPT */
2433 if (npt_enabled)
2434 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2435
04d2cc77
AK		 2436 clgi();
2437
2438 local_irq_enable();
36241b8c 2439
6aa8b732 2440 asm volatile (
80e31d4f
AK		 2441 "push %%"R"bp; \n\t"
2442 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2443 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2444 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2445 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2446 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2447 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2448#ifdef CONFIG_X86_64
fb3f0f51
RR		 2449 "mov %c[r8](%[svm]), %%r8 \n\t"
2450 "mov %c[r9](%[svm]), %%r9 \n\t"
2451 "mov %c[r10](%[svm]), %%r10 \n\t"
2452 "mov %c[r11](%[svm]), %%r11 \n\t"
2453 "mov %c[r12](%[svm]), %%r12 \n\t"
2454 "mov %c[r13](%[svm]), %%r13 \n\t"
2455 "mov %c[r14](%[svm]), %%r14 \n\t"
2456 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2457#endif
2458
6aa8b732 2459 /* Enter guest mode */
80e31d4f
AK		 2460 "push %%"R"ax \n\t"
2461 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2462 __ex(SVM_VMLOAD) "\n\t"
2463 __ex(SVM_VMRUN) "\n\t"
2464 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2465 "pop %%"R"ax \n\t"
6aa8b732
AK		 2466
2467 /* Save guest registers, load host registers */
80e31d4f
AK		 2468 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2469 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2470 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2471 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2472 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2473 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2474#ifdef CONFIG_X86_64
fb3f0f51
RR		 2475 "mov %%r8, %c[r8](%[svm]) \n\t"
2476 "mov %%r9, %c[r9](%[svm]) \n\t"
2477 "mov %%r10, %c[r10](%[svm]) \n\t"
2478 "mov %%r11, %c[r11](%[svm]) \n\t"
2479 "mov %%r12, %c[r12](%[svm]) \n\t"
2480 "mov %%r13, %c[r13](%[svm]) \n\t"
2481 "mov %%r14, %c[r14](%[svm]) \n\t"
2482 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2483#endif
80e31d4f 2484 "pop %%"R"bp"
6aa8b732 2485 :
fb3f0f51 2486 : [svm]"a"(svm),
6aa8b732 2487 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2488 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2489 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2490 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2491 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2492 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2493 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2494#ifdef CONFIG_X86_64
ad312c7c
ZX		 2495 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2496 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2497 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2498 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2499 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2500 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2501 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2502 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2503#endif
54a08c04 2504 : "cc", "memory"
80e31d4f 2505 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2506#ifdef CONFIG_X86_64
54a08c04
LV		 2507 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2508#endif
2509 );
6aa8b732 2510
ad312c7c 2511 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2512 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2513 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2514 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2515
a2fa3e9f 2516 kvm_write_cr2(svm->host_cr2);
6aa8b732 2517
d6e88aec
AK		 2518 kvm_load_fs(fs_selector);
2519 kvm_load_gs(gs_selector);
2520 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2521 load_host_msrs(vcpu);
2522
2523 reload_tss(vcpu);
2524
56ba47dd
AK		 2525 local_irq_disable();
2526
2527 stgi();
2528
d7bf8221
JR		 2529 sync_cr8_to_lapic(vcpu);
2530
a2fa3e9f 2531 svm->next_rip = 0;
6aa8b732
AK		 2532}
2533
80e31d4f
AK		 2534#undef R
2535
6aa8b732
AK		 2536static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2537{
a2fa3e9f
GH		 2538 struct vcpu_svm *svm = to_svm(vcpu);
2539
709ddebf
JR		 2540 if (npt_enabled) {
2541 svm->vmcb->control.nested_cr3 = root;
2542 force_new_asid(vcpu);
2543 return;
2544 }
2545
a2fa3e9f 2546 svm->vmcb->save.cr3 = root;
6aa8b732 2547 force_new_asid(vcpu);
7807fa6c
AL		 2548
2549 if (vcpu->fpu_active) {
a2fa3e9f
GH		 2550 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2551 svm->vmcb->save.cr0 |= X86_CR0_TS;
7807fa6c
AL		 2552 vcpu->fpu_active = 0;
2553 }
6aa8b732
AK		 2554}
2555
6aa8b732
AK		 2556static int is_disabled(void)
2557{
6031a61c
JR		 2558 u64 vm_cr;
2559
2560 rdmsrl(MSR_VM_CR, vm_cr);
2561 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2562 return 1;
2563
6aa8b732
AK		 2564 return 0;
2565}
2566
102d8325
IM		 2567static void
2568svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2569{
2570 /*
2571 * Patch in the VMMCALL instruction:
2572 */
2573 hypercall[0] = 0x0f;
2574 hypercall[1] = 0x01;
2575 hypercall[2] = 0xd9;
102d8325
IM		 2576}
2577
002c7f7c
YS		 2578static void svm_check_processor_compat(void *rtn)
2579{
2580 *(int *)rtn = 0;
2581}
2582
774ead3a
AK		 2583static bool svm_cpu_has_accelerated_tpr(void)
2584{
2585 return false;
2586}
2587
67253af5
SY		 2588static int get_npt_level(void)
2589{
2590#ifdef CONFIG_X86_64
2591 return PT64_ROOT_LEVEL;
2592#else
2593 return PT32E_ROOT_LEVEL;
2594#endif
2595}
2596
64d4d521
SY		 2597static int svm_get_mt_mask_shift(void)
2598{
2599 return 0;
2600}
2601
cbdd1bea 2602static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 2603 .cpu_has_kvm_support = has_svm,
2604 .disabled_by_bios = is_disabled,
2605 .hardware_setup = svm_hardware_setup,
2606 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 2607 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 2608 .hardware_enable = svm_hardware_enable,
2609 .hardware_disable = svm_hardware_disable,
774ead3a 2610 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 2611
2612 .vcpu_create = svm_create_vcpu,
2613 .vcpu_free = svm_free_vcpu,
04d2cc77 2614 .vcpu_reset = svm_vcpu_reset,
6aa8b732 2615
04d2cc77 2616 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 2617 .vcpu_load = svm_vcpu_load,
2618 .vcpu_put = svm_vcpu_put,
2619
2620 .set_guest_debug = svm_guest_debug,
2621 .get_msr = svm_get_msr,
2622 .set_msr = svm_set_msr,
2623 .get_segment_base = svm_get_segment_base,
2624 .get_segment = svm_get_segment,
2625 .set_segment = svm_set_segment,
2e4d2653 2626 .get_cpl = svm_get_cpl,
1747fb71 2627 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
25c4c276 2628 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 2629 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 2630 .set_cr3 = svm_set_cr3,
2631 .set_cr4 = svm_set_cr4,
2632 .set_efer = svm_set_efer,
2633 .get_idt = svm_get_idt,
2634 .set_idt = svm_set_idt,
2635 .get_gdt = svm_get_gdt,
2636 .set_gdt = svm_set_gdt,
2637 .get_dr = svm_get_dr,
2638 .set_dr = svm_set_dr,
6aa8b732
AK		 2639 .get_rflags = svm_get_rflags,
2640 .set_rflags = svm_set_rflags,
2641
6aa8b732 2642 .tlb_flush = svm_flush_tlb,
6aa8b732 2643
6aa8b732 2644 .run = svm_vcpu_run,
04d2cc77 2645 .handle_exit = handle_exit,
6aa8b732 2646 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 2647 .patch_hypercall = svm_patch_hypercall,
2a8067f1
ED		 2648 .get_irq = svm_get_irq,
2649 .set_irq = svm_set_irq,
298101da
AK		 2650 .queue_exception = svm_queue_exception,
2651 .exception_injected = svm_exception_injected,
04d2cc77
AK		 2652 .inject_pending_irq = svm_intr_assist,
2653 .inject_pending_vectors = do_interrupt_requests,
cbc94022
IE		 2654
2655 .set_tss_addr = svm_set_tss_addr,
67253af5 2656 .get_tdp_level = get_npt_level,
64d4d521 2657 .get_mt_mask_shift = svm_get_mt_mask_shift,
6aa8b732
AK		 2658};
2659
2660static int __init svm_init(void)
2661{
cb498ea2 2662 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 2663 THIS_MODULE);
6aa8b732
AK		 2664}
2665
2666static void __exit svm_exit(void)
2667{
cb498ea2 2668 kvm_exit();
6aa8b732
AK		 2669}
2670
2671module_init(svm_init)
2672module_exit(svm_exit)
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