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KVM: VMX: Allow single-stepping when uninterruptible
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
e495606d 18#include "kvm_svm.h"
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
5fdbf976 21#include "kvm_cache_regs.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
6aa8b732 28
e495606d 29#include <asm/desc.h>
6aa8b732 30
63d1142f
EH		 31#include <asm/virtext.h>
32
4ecac3fd
AK		 33#define __ex(x) __kvm_handle_fault_on_reboot(x)
34
6aa8b732
AK		 35MODULE_AUTHOR("Qumranet");
36MODULE_LICENSE("GPL");
37
38#define IOPM_ALLOC_ORDER 2
39#define MSRPM_ALLOC_ORDER 1
40
6aa8b732
AK		 41#define DR7_GD_MASK (1 << 13)
42#define DR6_BD_MASK (1 << 13)
6aa8b732
AK		 43
44#define SEG_TYPE_LDT 2
45#define SEG_TYPE_BUSY_TSS16 3
46
80b7706e
JR		 47#define SVM_FEATURE_NPT (1 << 0)
48#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 49#define SVM_FEATURE_SVML (1 << 2)
80b7706e 50
24e09cbf
JR		 51#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
52
c0725420
AG		 53/* Turn on to get debugging output*/
54/* #define NESTED_DEBUG */
55
56#ifdef NESTED_DEBUG
57#define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
58#else
59#define nsvm_printk(fmt, args...) do {} while(0)
60#endif
61
709ddebf
JR		 62/* enable NPT for AMD64 and X86 with PAE */
63#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
64static bool npt_enabled = true;
65#else
e3da3acd 66static bool npt_enabled = false;
709ddebf 67#endif
6c7dac72
JR		 68static int npt = 1;
69
70module_param(npt, int, S_IRUGO);
e3da3acd 71
236de055
AG		 72static int nested = 0;
73module_param(nested, int, S_IRUGO);
74
04d2cc77 75static void kvm_reput_irq(struct vcpu_svm *svm);
44874f84 76static void svm_flush_tlb(struct kvm_vcpu *vcpu);
04d2cc77 77
cf74a78b
AG		 78static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
79static int nested_svm_vmexit(struct vcpu_svm *svm);
80static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
81 void *arg2, void *opaque);
82static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
83 bool has_error_code, u32 error_code);
84
a2fa3e9f
GH		 85static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
86{
fb3f0f51 87 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 88}
89
3d6368ef
AG		 90static inline bool is_nested(struct vcpu_svm *svm)
91{
92 return svm->nested_vmcb;
93}
94
4866d5e3 95static unsigned long iopm_base;
6aa8b732
AK		 96
97struct kvm_ldttss_desc {
98 u16 limit0;
99 u16 base0;
100 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
101 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
102 u32 base3;
103 u32 zero1;
104} __attribute__((packed));
105
106struct svm_cpu_data {
107 int cpu;
108
5008fdf5
AK		 109 u64 asid_generation;
110 u32 max_asid;
111 u32 next_asid;
6aa8b732
AK		 112 struct kvm_ldttss_desc *tss_desc;
113
114 struct page *save_area;
115};
116
117static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 118static uint32_t svm_features;
6aa8b732
AK		 119
120struct svm_init_data {
121 int cpu;
122 int r;
123};
124
125static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
126
9d8f549d 127#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 128#define MSRS_RANGE_SIZE 2048
129#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
130
131#define MAX_INST_SIZE 15
132
80b7706e
JR		 133static inline u32 svm_has(u32 feat)
134{
135 return svm_features & feat;
136}
137
6aa8b732
AK		 138static inline u8 pop_irq(struct kvm_vcpu *vcpu)
139{
ad312c7c
ZX		 140 int word_index = __ffs(vcpu->arch.irq_summary);
141 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
6aa8b732
AK		 142 int irq = word_index * BITS_PER_LONG + bit_index;
143
ad312c7c
ZX		 144 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
145 if (!vcpu->arch.irq_pending[word_index])
146 clear_bit(word_index, &vcpu->arch.irq_summary);
6aa8b732
AK		 147 return irq;
148}
149
150static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
151{
ad312c7c
ZX		 152 set_bit(irq, vcpu->arch.irq_pending);
153 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
6aa8b732
AK		 154}
155
156static inline void clgi(void)
157{
4ecac3fd 158 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 159}
160
161static inline void stgi(void)
162{
4ecac3fd 163 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 164}
165
166static inline void invlpga(unsigned long addr, u32 asid)
167{
4ecac3fd 168 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 169}
170
171static inline unsigned long kvm_read_cr2(void)
172{
173 unsigned long cr2;
174
175 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
176 return cr2;
177}
178
179static inline void kvm_write_cr2(unsigned long val)
180{
181 asm volatile ("mov %0, %%cr2" :: "r" (val));
182}
183
184static inline unsigned long read_dr6(void)
185{
186 unsigned long dr6;
187
188 asm volatile ("mov %%dr6, %0" : "=r" (dr6));
189 return dr6;
190}
191
192static inline void write_dr6(unsigned long val)
193{
194 asm volatile ("mov %0, %%dr6" :: "r" (val));
195}
196
197static inline unsigned long read_dr7(void)
198{
199 unsigned long dr7;
200
201 asm volatile ("mov %%dr7, %0" : "=r" (dr7));
202 return dr7;
203}
204
205static inline void write_dr7(unsigned long val)
206{
207 asm volatile ("mov %0, %%dr7" :: "r" (val));
208}
209
6aa8b732
AK		 210static inline void force_new_asid(struct kvm_vcpu *vcpu)
211{
a2fa3e9f 212 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 213}
214
215static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
216{
217 force_new_asid(vcpu);
218}
219
220static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
221{
709ddebf 222 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 223 efer &= ~EFER_LME;
6aa8b732 224
9962d032 225 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
ad312c7c 226 vcpu->arch.shadow_efer = efer;
6aa8b732
AK		 227}
228
298101da
AK		 229static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
230 bool has_error_code, u32 error_code)
231{
232 struct vcpu_svm *svm = to_svm(vcpu);
233
cf74a78b
AG		 234 /* If we are within a nested VM we'd better #VMEXIT and let the
235 guest handle the exception */
236 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
237 return;
238
298101da
AK		 239 svm->vmcb->control.event_inj = nr
240 | SVM_EVTINJ_VALID
241 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
242 | SVM_EVTINJ_TYPE_EXEPT;
243 svm->vmcb->control.event_inj_err = error_code;
244}
245
246static bool svm_exception_injected(struct kvm_vcpu *vcpu)
247{
248 struct vcpu_svm *svm = to_svm(vcpu);
249
250 return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
251}
252
6aa8b732
AK		 253static int is_external_interrupt(u32 info)
254{
255 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
256 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
257}
258
259static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
260{
a2fa3e9f
GH		 261 struct vcpu_svm *svm = to_svm(vcpu);
262
263 if (!svm->next_rip) {
b8688d51 264 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 265 return;
266 }
5fdbf976
MT		 267 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
268 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
269 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 270
5fdbf976 271 kvm_rip_write(vcpu, svm->next_rip);
a2fa3e9f 272 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
c1150d8c 273
1371d904 274 vcpu->arch.interrupt_window_open = (svm->vcpu.arch.hflags & HF_GIF_MASK);
6aa8b732
AK		 275}
276
277static int has_svm(void)
278{
63d1142f 279 const char *msg;
6aa8b732 280
63d1142f
EH		 281 if (!cpu_has_svm(&msg)) {
282 printk(KERN_INFO "has_svn: %s\n", msg);
6aa8b732
AK		 283 return 0;
284 }
285
6aa8b732
AK		 286 return 1;
287}
288
289static void svm_hardware_disable(void *garbage)
290{
2c8dceeb 291 cpu_svm_disable();
6aa8b732
AK		 292}
293
294static void svm_hardware_enable(void *garbage)
295{
296
297 struct svm_cpu_data *svm_data;
298 uint64_t efer;
6aa8b732 299 struct desc_ptr gdt_descr;
6aa8b732
AK		 300 struct desc_struct *gdt;
301 int me = raw_smp_processor_id();
302
303 if (!has_svm()) {
304 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
305 return;
306 }
307 svm_data = per_cpu(svm_data, me);
308
309 if (!svm_data) {
310 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
311 me);
312 return;
313 }
314
315 svm_data->asid_generation = 1;
316 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
317 svm_data->next_asid = svm_data->max_asid + 1;
318
d77c26fc 319 asm volatile ("sgdt %0" : "=m"(gdt_descr));
6aa8b732
AK		 320 gdt = (struct desc_struct *)gdt_descr.address;
321 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
322
323 rdmsrl(MSR_EFER, efer);
9962d032 324 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732
AK		 325
326 wrmsrl(MSR_VM_HSAVE_PA,
327 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
328}
329
0da1db75
JR		 330static void svm_cpu_uninit(int cpu)
331{
332 struct svm_cpu_data *svm_data
333 = per_cpu(svm_data, raw_smp_processor_id());
334
335 if (!svm_data)
336 return;
337
338 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
339 __free_page(svm_data->save_area);
340 kfree(svm_data);
341}
342
6aa8b732
AK		 343static int svm_cpu_init(int cpu)
344{
345 struct svm_cpu_data *svm_data;
346 int r;
347
348 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
349 if (!svm_data)
350 return -ENOMEM;
351 svm_data->cpu = cpu;
352 svm_data->save_area = alloc_page(GFP_KERNEL);
353 r = -ENOMEM;
354 if (!svm_data->save_area)
355 goto err_1;
356
357 per_cpu(svm_data, cpu) = svm_data;
358
359 return 0;
360
361err_1:
362 kfree(svm_data);
363 return r;
364
365}
366
bfc733a7
RR		 367static void set_msr_interception(u32 *msrpm, unsigned msr,
368 int read, int write)
6aa8b732
AK		 369{
370 int i;
371
372 for (i = 0; i < NUM_MSR_MAPS; i++) {
373 if (msr >= msrpm_ranges[i] &&
374 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
375 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
376 msrpm_ranges[i]) * 2;
377
378 u32 *base = msrpm + (msr_offset / 32);
379 u32 msr_shift = msr_offset % 32;
380 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
381 *base = (*base & ~(0x3 << msr_shift)) |
382 (mask << msr_shift);
bfc733a7 383 return;
6aa8b732
AK		 384 }
385 }
bfc733a7 386 BUG();
6aa8b732
AK		 387}
388
f65c229c
JR		 389static void svm_vcpu_init_msrpm(u32 *msrpm)
390{
391 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
392
393#ifdef CONFIG_X86_64
394 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
395 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
396 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
397 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
398 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
399 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
400#endif
401 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
402 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
403 set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
404 set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
405}
406
24e09cbf
JR		 407static void svm_enable_lbrv(struct vcpu_svm *svm)
408{
409 u32 *msrpm = svm->msrpm;
410
411 svm->vmcb->control.lbr_ctl = 1;
412 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
413 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
414 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
415 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
416}
417
418static void svm_disable_lbrv(struct vcpu_svm *svm)
419{
420 u32 *msrpm = svm->msrpm;
421
422 svm->vmcb->control.lbr_ctl = 0;
423 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
424 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
425 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
426 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
427}
428
6aa8b732
AK		 429static __init int svm_hardware_setup(void)
430{
431 int cpu;
432 struct page *iopm_pages;
f65c229c 433 void *iopm_va;
6aa8b732
AK		 434 int r;
435
6aa8b732
AK		 436 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
437
438 if (!iopm_pages)
439 return -ENOMEM;
c8681339
AL		 440
441 iopm_va = page_address(iopm_pages);
442 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
443 clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
6aa8b732
AK		 444 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
445
50a37eb4
JR		 446 if (boot_cpu_has(X86_FEATURE_NX))
447 kvm_enable_efer_bits(EFER_NX);
448
236de055
AG		 449 if (nested) {
450 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
451 kvm_enable_efer_bits(EFER_SVME);
452 }
453
6aa8b732
AK		 454 for_each_online_cpu(cpu) {
455 r = svm_cpu_init(cpu);
456 if (r)
f65c229c 457 goto err;
6aa8b732 458 }
33bd6a0b
JR		 459
460 svm_features = cpuid_edx(SVM_CPUID_FUNC);
461
e3da3acd
JR		 462 if (!svm_has(SVM_FEATURE_NPT))
463 npt_enabled = false;
464
6c7dac72
JR		 465 if (npt_enabled && !npt) {
466 printk(KERN_INFO "kvm: Nested Paging disabled\n");
467 npt_enabled = false;
468 }
469
18552672 470 if (npt_enabled) {
e3da3acd 471 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 472 kvm_enable_tdp();
5f4cb662
JR		 473 } else
474 kvm_disable_tdp();
e3da3acd 475
6aa8b732
AK		 476 return 0;
477
f65c229c 478err:
6aa8b732
AK		 479 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
480 iopm_base = 0;
481 return r;
482}
483
484static __exit void svm_hardware_unsetup(void)
485{
0da1db75
JR		 486 int cpu;
487
488 for_each_online_cpu(cpu)
489 svm_cpu_uninit(cpu);
490
6aa8b732 491 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 492 iopm_base = 0;
6aa8b732
AK		 493}
494
495static void init_seg(struct vmcb_seg *seg)
496{
497 seg->selector = 0;
498 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
499 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
500 seg->limit = 0xffff;
501 seg->base = 0;
502}
503
504static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
505{
506 seg->selector = 0;
507 seg->attrib = SVM_SELECTOR_P_MASK | type;
508 seg->limit = 0xffff;
509 seg->base = 0;
510}
511
e6101a96 512static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 513{
e6101a96
JR		 514 struct vmcb_control_area *control = &svm->vmcb->control;
515 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732
AK		 516
517 control->intercept_cr_read = INTERCEPT_CR0_MASK |
518 INTERCEPT_CR3_MASK |
649d6864 519 INTERCEPT_CR4_MASK;
6aa8b732
AK		 520
521 control->intercept_cr_write = INTERCEPT_CR0_MASK |
522 INTERCEPT_CR3_MASK |
80a8119c
AK		 523 INTERCEPT_CR4_MASK |
524 INTERCEPT_CR8_MASK;
6aa8b732
AK		 525
526 control->intercept_dr_read = INTERCEPT_DR0_MASK |
527 INTERCEPT_DR1_MASK |
528 INTERCEPT_DR2_MASK |
529 INTERCEPT_DR3_MASK;
530
531 control->intercept_dr_write = INTERCEPT_DR0_MASK |
532 INTERCEPT_DR1_MASK |
533 INTERCEPT_DR2_MASK |
534 INTERCEPT_DR3_MASK |
535 INTERCEPT_DR5_MASK |
536 INTERCEPT_DR7_MASK;
537
7aa81cc0 538 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 539 (1 << UD_VECTOR) |
540 (1 << MC_VECTOR);
6aa8b732
AK		 541
542
543 control->intercept = (1ULL << INTERCEPT_INTR) |
544 (1ULL << INTERCEPT_NMI) |
0152527b 545 (1ULL << INTERCEPT_SMI) |
6aa8b732 546 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 547 (1ULL << INTERCEPT_INVD) |
6aa8b732 548 (1ULL << INTERCEPT_HLT) |
a7052897 549 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 550 (1ULL << INTERCEPT_INVLPGA) |
551 (1ULL << INTERCEPT_IOIO_PROT) |
552 (1ULL << INTERCEPT_MSR_PROT) |
553 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 554 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 555 (1ULL << INTERCEPT_VMRUN) |
556 (1ULL << INTERCEPT_VMMCALL) |
557 (1ULL << INTERCEPT_VMLOAD) |
558 (1ULL << INTERCEPT_VMSAVE) |
559 (1ULL << INTERCEPT_STGI) |
560 (1ULL << INTERCEPT_CLGI) |
916ce236 561 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 562 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 563 (1ULL << INTERCEPT_MONITOR) |
564 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 565
566 control->iopm_base_pa = iopm_base;
f65c229c 567 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 568 control->tsc_offset = 0;
6aa8b732
AK		 569 control->int_ctl = V_INTR_MASKING_MASK;
570
571 init_seg(&save->es);
572 init_seg(&save->ss);
573 init_seg(&save->ds);
574 init_seg(&save->fs);
575 init_seg(&save->gs);
576
577 save->cs.selector = 0xf000;
578 /* Executable/Readable Code Segment */
579 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
580 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
581 save->cs.limit = 0xffff;
d92899a0
AK		 582 /*
583 * cs.base should really be 0xffff0000, but vmx can't handle that, so
584 * be consistent with it.
585 *
586 * Replace when we have real mode working for vmx.
587 */
588 save->cs.base = 0xf0000;
6aa8b732
AK		 589
590 save->gdtr.limit = 0xffff;
591 save->idtr.limit = 0xffff;
592
593 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
594 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
595
9962d032 596 save->efer = EFER_SVME;
d77c26fc 597 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 598 save->dr7 = 0x400;
599 save->rflags = 2;
600 save->rip = 0x0000fff0;
5fdbf976 601 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732
AK		 602
603 /*
604 * cr0 val on cpu init should be 0x60000010, we enable cpu
605 * cache by default. the orderly way is to enable cache in bios.
606 */
707d92fa 607 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
66aee91a 608 save->cr4 = X86_CR4_PAE;
6aa8b732 609 /* rdx = ?? */
709ddebf
JR		 610
611 if (npt_enabled) {
612 /* Setup VMCB for Nested Paging */
613 control->nested_ctl = 1;
a7052897
MT		 614 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
615 (1ULL << INTERCEPT_INVLPG));
709ddebf
JR		 616 control->intercept_exceptions &= ~(1 << PF_VECTOR);
617 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
618 INTERCEPT_CR3_MASK);
619 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
620 INTERCEPT_CR3_MASK);
621 save->g_pat = 0x0007040600070406ULL;
622 /* enable caching because the QEMU Bios doesn't enable it */
623 save->cr0 = X86_CR0_ET;
624 save->cr3 = 0;
625 save->cr4 = 0;
626 }
a79d2f18 627 force_new_asid(&svm->vcpu);
1371d904 628
3d6368ef 629 svm->nested_vmcb = 0;
1371d904 630 svm->vcpu.arch.hflags = HF_GIF_MASK;
6aa8b732
AK		 631}
632
e00c8cf2 633static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 634{
635 struct vcpu_svm *svm = to_svm(vcpu);
636
e6101a96 637 init_vmcb(svm);
70433389
AK		 638
639 if (vcpu->vcpu_id != 0) {
5fdbf976 640 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 641 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
642 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 643 }
5fdbf976
MT		 644 vcpu->arch.regs_avail = ~0;
645 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 646
647 return 0;
04d2cc77
AK		 648}
649
fb3f0f51 650static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 651{
a2fa3e9f 652 struct vcpu_svm *svm;
6aa8b732 653 struct page *page;
f65c229c 654 struct page *msrpm_pages;
b286d5d8 655 struct page *hsave_page;
3d6368ef 656 struct page *nested_msrpm_pages;
fb3f0f51 657 int err;
6aa8b732 658
c16f862d 659 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 660 if (!svm) {
661 err = -ENOMEM;
662 goto out;
663 }
664
665 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
666 if (err)
667 goto free_svm;
668
6aa8b732 669 page = alloc_page(GFP_KERNEL);
fb3f0f51
RR		 670 if (!page) {
671 err = -ENOMEM;
672 goto uninit;
673 }
6aa8b732 674
f65c229c
JR		 675 err = -ENOMEM;
676 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
677 if (!msrpm_pages)
678 goto uninit;
3d6368ef
AG		 679
680 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
681 if (!nested_msrpm_pages)
682 goto uninit;
683
f65c229c
JR		 684 svm->msrpm = page_address(msrpm_pages);
685 svm_vcpu_init_msrpm(svm->msrpm);
686
b286d5d8
AG		 687 hsave_page = alloc_page(GFP_KERNEL);
688 if (!hsave_page)
689 goto uninit;
690 svm->hsave = page_address(hsave_page);
691
3d6368ef
AG		 692 svm->nested_msrpm = page_address(nested_msrpm_pages);
693
a2fa3e9f
GH		 694 svm->vmcb = page_address(page);
695 clear_page(svm->vmcb);
696 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
697 svm->asid_generation = 0;
698 memset(svm->db_regs, 0, sizeof(svm->db_regs));
e6101a96 699 init_vmcb(svm);
a2fa3e9f 700
fb3f0f51
RR		 701 fx_init(&svm->vcpu);
702 svm->vcpu.fpu_active = 1;
ad312c7c 703 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
fb3f0f51 704 if (svm->vcpu.vcpu_id == 0)
ad312c7c 705 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 706
fb3f0f51 707 return &svm->vcpu;
36241b8c 708
fb3f0f51
RR		 709uninit:
710 kvm_vcpu_uninit(&svm->vcpu);
711free_svm:
a4770347 712 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 713out:
714 return ERR_PTR(err);
6aa8b732
AK		 715}
716
717static void svm_free_vcpu(struct kvm_vcpu *vcpu)
718{
a2fa3e9f
GH		 719 struct vcpu_svm *svm = to_svm(vcpu);
720
fb3f0f51 721 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 722 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
b286d5d8 723 __free_page(virt_to_page(svm->hsave));
3d6368ef 724 __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 725 kvm_vcpu_uninit(vcpu);
a4770347 726 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 727}
728
15ad7146 729static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 730{
a2fa3e9f 731 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 732 int i;
0cc5064d 733
0cc5064d
AK		 734 if (unlikely(cpu != vcpu->cpu)) {
735 u64 tsc_this, delta;
736
737 /*
738 * Make sure that the guest sees a monotonically
739 * increasing TSC.
740 */
741 rdtscll(tsc_this);
ad312c7c 742 delta = vcpu->arch.host_tsc - tsc_this;
a2fa3e9f 743 svm->vmcb->control.tsc_offset += delta;
0cc5064d 744 vcpu->cpu = cpu;
2f599714 745 kvm_migrate_timers(vcpu);
0cc5064d 746 }
94dfbdb3
AL		 747
748 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 749 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 750}
751
752static void svm_vcpu_put(struct kvm_vcpu *vcpu)
753{
a2fa3e9f 754 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 755 int i;
756
e1beb1d3 757 ++vcpu->stat.host_state_reload;
94dfbdb3 758 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 759 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 760
ad312c7c 761 rdtscll(vcpu->arch.host_tsc);
6aa8b732
AK		 762}
763
6aa8b732
AK		 764static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
765{
a2fa3e9f 766 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 767}
768
769static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
770{
a2fa3e9f 771 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 772}
773
f0b85051
AG		 774static void svm_set_vintr(struct vcpu_svm *svm)
775{
776 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
777}
778
779static void svm_clear_vintr(struct vcpu_svm *svm)
780{
781 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
782}
783
6aa8b732
AK		 784static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
785{
a2fa3e9f 786 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 787
788 switch (seg) {
789 case VCPU_SREG_CS: return &save->cs;
790 case VCPU_SREG_DS: return &save->ds;
791 case VCPU_SREG_ES: return &save->es;
792 case VCPU_SREG_FS: return &save->fs;
793 case VCPU_SREG_GS: return &save->gs;
794 case VCPU_SREG_SS: return &save->ss;
795 case VCPU_SREG_TR: return &save->tr;
796 case VCPU_SREG_LDTR: return &save->ldtr;
797 }
798 BUG();
8b6d44c7 799 return NULL;
6aa8b732
AK		 800}
801
802static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
803{
804 struct vmcb_seg *s = svm_seg(vcpu, seg);
805
806 return s->base;
807}
808
809static void svm_get_segment(struct kvm_vcpu *vcpu,
810 struct kvm_segment *var, int seg)
811{
812 struct vmcb_seg *s = svm_seg(vcpu, seg);
813
814 var->base = s->base;
815 var->limit = s->limit;
816 var->selector = s->selector;
817 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
818 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
819 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
820 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
821 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
822 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
823 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
824 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc
AS		 825
826 /*
827 * SVM always stores 0 for the 'G' bit in the CS selector in
828 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
829 * Intel's VMENTRY has a check on the 'G' bit.
830 */
831 if (seg == VCPU_SREG_CS)
832 var->g = s->limit > 0xfffff;
833
c0d09828
AS		 834 /*
835 * Work around a bug where the busy flag in the tr selector
836 * isn't exposed
837 */
838 if (seg == VCPU_SREG_TR)
839 var->type |= 0x2;
840
6aa8b732
AK		 841 var->unusable = !var->present;
842}
843
2e4d2653
IE		 844static int svm_get_cpl(struct kvm_vcpu *vcpu)
845{
846 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
847
848 return save->cpl;
849}
850
6aa8b732
AK		 851static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
852{
a2fa3e9f
GH		 853 struct vcpu_svm *svm = to_svm(vcpu);
854
855 dt->limit = svm->vmcb->save.idtr.limit;
856 dt->base = svm->vmcb->save.idtr.base;
6aa8b732
AK		 857}
858
859static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
860{
a2fa3e9f
GH		 861 struct vcpu_svm *svm = to_svm(vcpu);
862
863 svm->vmcb->save.idtr.limit = dt->limit;
864 svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 865}
866
867static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
868{
a2fa3e9f
GH		 869 struct vcpu_svm *svm = to_svm(vcpu);
870
871 dt->limit = svm->vmcb->save.gdtr.limit;
872 dt->base = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 873}
874
875static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
876{
a2fa3e9f
GH		 877 struct vcpu_svm *svm = to_svm(vcpu);
878
879 svm->vmcb->save.gdtr.limit = dt->limit;
880 svm->vmcb->save.gdtr.base = dt->base ;
6aa8b732
AK		 881}
882
25c4c276 883static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 884{
885}
886
6aa8b732
AK		 887static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
888{
a2fa3e9f
GH		 889 struct vcpu_svm *svm = to_svm(vcpu);
890
05b3e0c2 891#ifdef CONFIG_X86_64
ad312c7c 892 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 893 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
ad312c7c 894 vcpu->arch.shadow_efer |= EFER_LMA;
2b5203ee 895 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 896 }
897
d77c26fc 898 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
ad312c7c 899 vcpu->arch.shadow_efer &= ~EFER_LMA;
2b5203ee 900 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 901 }
902 }
903#endif
709ddebf
JR		 904 if (npt_enabled)
905 goto set;
906
ad312c7c 907 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
a2fa3e9f 908 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
7807fa6c
AL		 909 vcpu->fpu_active = 1;
910 }
911
ad312c7c 912 vcpu->arch.cr0 = cr0;
707d92fa 913 cr0 |= X86_CR0_PG | X86_CR0_WP;
6b390b63
JR		 914 if (!vcpu->fpu_active) {
915 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
334df50a 916 cr0 |= X86_CR0_TS;
6b390b63 917 }
709ddebf
JR		 918set:
919 /*
920 * re-enable caching here because the QEMU bios
921 * does not do it - this results in some delay at
922 * reboot
923 */
924 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 925 svm->vmcb->save.cr0 = cr0;
6aa8b732
AK		 926}
927
928static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
929{
6394b649 930 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 931 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
932
933 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
934 force_new_asid(vcpu);
6394b649 935
ec077263
JR		 936 vcpu->arch.cr4 = cr4;
937 if (!npt_enabled)
938 cr4 |= X86_CR4_PAE;
6394b649 939 cr4 |= host_cr4_mce;
ec077263 940 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 941}
942
943static void svm_set_segment(struct kvm_vcpu *vcpu,
944 struct kvm_segment *var, int seg)
945{
a2fa3e9f 946 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 947 struct vmcb_seg *s = svm_seg(vcpu, seg);
948
949 s->base = var->base;
950 s->limit = var->limit;
951 s->selector = var->selector;
952 if (var->unusable)
953 s->attrib = 0;
954 else {
955 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
956 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
957 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
958 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
959 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
960 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
961 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
962 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
963 }
964 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 965 svm->vmcb->save.cpl
966 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 967 >> SVM_SELECTOR_DPL_SHIFT) & 3;
968
969}
970
d0bfb940 971static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 972{
d0bfb940
JK		 973 int old_debug = vcpu->guest_debug;
974 struct vcpu_svm *svm = to_svm(vcpu);
975
976 vcpu->guest_debug = dbg->control;
977
978 svm->vmcb->control.intercept_exceptions &=
979 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
980 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
981 if (vcpu->guest_debug &
982 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
983 svm->vmcb->control.intercept_exceptions |=
984 1 << DB_VECTOR;
985 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
986 svm->vmcb->control.intercept_exceptions |=
987 1 << BP_VECTOR;
988 } else
989 vcpu->guest_debug = 0;
990
991 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
992 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
993 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
994 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
995
996 return 0;
6aa8b732
AK		 997}
998
2a8067f1
ED		 999static int svm_get_irq(struct kvm_vcpu *vcpu)
1000{
1001 struct vcpu_svm *svm = to_svm(vcpu);
1002 u32 exit_int_info = svm->vmcb->control.exit_int_info;
1003
1004 if (is_external_interrupt(exit_int_info))
1005 return exit_int_info & SVM_EVTINJ_VEC_MASK;
1006 return -1;
1007}
1008
6aa8b732
AK		 1009static void load_host_msrs(struct kvm_vcpu *vcpu)
1010{
94dfbdb3 1011#ifdef CONFIG_X86_64
a2fa3e9f 1012 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1013#endif
6aa8b732
AK		 1014}
1015
1016static void save_host_msrs(struct kvm_vcpu *vcpu)
1017{
94dfbdb3 1018#ifdef CONFIG_X86_64
a2fa3e9f 1019 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1020#endif
6aa8b732
AK		 1021}
1022
e756fc62 1023static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
6aa8b732
AK		 1024{
1025 if (svm_data->next_asid > svm_data->max_asid) {
1026 ++svm_data->asid_generation;
1027 svm_data->next_asid = 1;
a2fa3e9f 1028 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1029 }
1030
e756fc62 1031 svm->vcpu.cpu = svm_data->cpu;
a2fa3e9f
GH		 1032 svm->asid_generation = svm_data->asid_generation;
1033 svm->vmcb->control.asid = svm_data->next_asid++;
6aa8b732
AK		 1034}
1035
6aa8b732
AK		 1036static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1037{
af9ca2d7
JR		 1038 unsigned long val = to_svm(vcpu)->db_regs[dr];
1039 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
1040 return val;
6aa8b732
AK		 1041}
1042
1043static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1044 int *exception)
1045{
a2fa3e9f
GH		 1046 struct vcpu_svm *svm = to_svm(vcpu);
1047
6aa8b732
AK		 1048 *exception = 0;
1049
a2fa3e9f
GH		 1050 if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
1051 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
1052 svm->vmcb->save.dr6 |= DR6_BD_MASK;
6aa8b732
AK		 1053 *exception = DB_VECTOR;
1054 return;
1055 }
1056
1057 switch (dr) {
1058 case 0 ... 3:
a2fa3e9f 1059 svm->db_regs[dr] = value;
6aa8b732
AK		 1060 return;
1061 case 4 ... 5:
ad312c7c 1062 if (vcpu->arch.cr4 & X86_CR4_DE) {
6aa8b732
AK		 1063 *exception = UD_VECTOR;
1064 return;
1065 }
1066 case 7: {
1067 if (value & ~((1ULL << 32) - 1)) {
1068 *exception = GP_VECTOR;
1069 return;
1070 }
a2fa3e9f 1071 svm->vmcb->save.dr7 = value;
6aa8b732
AK		 1072 return;
1073 }
1074 default:
1075 printk(KERN_DEBUG "%s: unexpected dr %u\n",
b8688d51 1076 __func__, dr);
6aa8b732
AK		 1077 *exception = UD_VECTOR;
1078 return;
1079 }
1080}
1081
e756fc62 1082static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1083{
a2fa3e9f 1084 u32 exit_int_info = svm->vmcb->control.exit_int_info;
e756fc62 1085 struct kvm *kvm = svm->vcpu.kvm;
6aa8b732
AK		 1086 u64 fault_address;
1087 u32 error_code;
577bdc49 1088 bool event_injection = false;
6aa8b732 1089
85f455f7 1090 if (!irqchip_in_kernel(kvm) &&
577bdc49
AK		 1091 is_external_interrupt(exit_int_info)) {
1092 event_injection = true;
e756fc62 1093 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
577bdc49 1094 }
6aa8b732 1095
a2fa3e9f
GH		 1096 fault_address = svm->vmcb->control.exit_info_2;
1097 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7
JR		 1098
1099 if (!npt_enabled)
1100 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1101 (u32)fault_address, (u32)(fault_address >> 32),
1102 handler);
d2ebb410
JR		 1103 else
1104 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1105 (u32)fault_address, (u32)(fault_address >> 32),
1106 handler);
44874f84
JR		 1107 /*
1108 * FIXME: Tis shouldn't be necessary here, but there is a flush
1109 * missing in the MMU code. Until we find this bug, flush the
1110 * complete TLB here on an NPF
1111 */
1112 if (npt_enabled)
1113 svm_flush_tlb(&svm->vcpu);
af9ca2d7 1114
48d15039 1115 if (!npt_enabled && event_injection)
577bdc49 1116 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1117 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1118}
1119
d0bfb940
JK		 1120static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1121{
1122 if (!(svm->vcpu.guest_debug &
1123 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
1124 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1125 return 1;
1126 }
1127 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1128 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1129 kvm_run->debug.arch.exception = DB_VECTOR;
1130 return 0;
1131}
1132
1133static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1134{
1135 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1136 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1137 kvm_run->debug.arch.exception = BP_VECTOR;
1138 return 0;
1139}
1140
7aa81cc0
AL		 1141static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1142{
1143 int er;
1144
571008da 1145 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1146 if (er != EMULATE_DONE)
7ee5d940 1147 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1148 return 1;
1149}
1150
e756fc62 1151static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
7807fa6c 1152{
a2fa3e9f 1153 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
ad312c7c 1154 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
a2fa3e9f 1155 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
e756fc62 1156 svm->vcpu.fpu_active = 1;
a2fa3e9f
GH		 1157
1158 return 1;
7807fa6c
AL		 1159}
1160
53371b50
JR		 1161static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1162{
1163 /*
1164 * On an #MC intercept the MCE handler is not called automatically in
1165 * the host. So do it by hand here.
1166 */
1167 asm volatile (
1168 "int $0x12\n");
1169 /* not sure if we ever come back to this point */
1170
1171 return 1;
1172}
1173
e756fc62 1174static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
46fe4ddd
JR		 1175{
1176 /*
1177 * VMCB is undefined after a SHUTDOWN intercept
1178 * so reinitialize it.
1179 */
a2fa3e9f 1180 clear_page(svm->vmcb);
e6101a96 1181 init_vmcb(svm);
46fe4ddd
JR		 1182
1183 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1184 return 0;
1185}
1186
e756fc62 1187static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1188{
d77c26fc 1189 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
039576c0
AK		 1190 int size, down, in, string, rep;
1191 unsigned port;
6aa8b732 1192
e756fc62 1193 ++svm->vcpu.stat.io_exits;
6aa8b732 1194
a2fa3e9f 1195 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1196
e70669ab
LV		 1197 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1198
1199 if (string) {
3427318f
LV		 1200 if (emulate_instruction(&svm->vcpu,
1201 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1202 return 0;
1203 return 1;
1204 }
1205
039576c0
AK		 1206 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1207 port = io_info >> 16;
1208 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
039576c0 1209 rep = (io_info & SVM_IOIO_REP_MASK) != 0;
a2fa3e9f 1210 down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
6aa8b732 1211
e93f36bc 1212 skip_emulated_instruction(&svm->vcpu);
3090dd73 1213 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
6aa8b732
AK		 1214}
1215
c47f098d
JR		 1216static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1217{
af9ca2d7 1218 KVMTRACE_0D(NMI, &svm->vcpu, handler);
c47f098d
JR		 1219 return 1;
1220}
1221
a0698055
JR		 1222static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1223{
1224 ++svm->vcpu.stat.irq_exits;
af9ca2d7 1225 KVMTRACE_0D(INTR, &svm->vcpu, handler);
a0698055
JR		 1226 return 1;
1227}
1228
e756fc62 1229static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732
AK		 1230{
1231 return 1;
1232}
1233
e756fc62 1234static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1235{
5fdbf976 1236 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1237 skip_emulated_instruction(&svm->vcpu);
1238 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1239}
1240
e756fc62 1241static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
02e235bc 1242{
5fdbf976 1243 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1244 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1245 kvm_emulate_hypercall(&svm->vcpu);
1246 return 1;
02e235bc
AK		 1247}
1248
c0725420
AG		 1249static int nested_svm_check_permissions(struct vcpu_svm *svm)
1250{
1251 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1252 || !is_paging(&svm->vcpu)) {
1253 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1254 return 1;
1255 }
1256
1257 if (svm->vmcb->save.cpl) {
1258 kvm_inject_gp(&svm->vcpu, 0);
1259 return 1;
1260 }
1261
1262 return 0;
1263}
1264
cf74a78b
AG		 1265static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1266 bool has_error_code, u32 error_code)
1267{
1268 if (is_nested(svm)) {
1269 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1270 svm->vmcb->control.exit_code_hi = 0;
1271 svm->vmcb->control.exit_info_1 = error_code;
1272 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1273 if (nested_svm_exit_handled(svm, false)) {
1274 nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1275
1276 nested_svm_vmexit(svm);
1277 return 1;
1278 }
1279 }
1280
1281 return 0;
1282}
1283
1284static inline int nested_svm_intr(struct vcpu_svm *svm)
1285{
1286 if (is_nested(svm)) {
1287 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1288 return 0;
1289
1290 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1291 return 0;
1292
1293 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1294
1295 if (nested_svm_exit_handled(svm, false)) {
1296 nsvm_printk("VMexit -> INTR\n");
1297 nested_svm_vmexit(svm);
1298 return 1;
1299 }
1300 }
1301
1302 return 0;
1303}
1304
c0725420
AG		 1305static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1306{
1307 struct page *page;
1308
1309 down_read(&current->mm->mmap_sem);
1310 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1311 up_read(&current->mm->mmap_sem);
1312
1313 if (is_error_page(page)) {
1314 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1315 __func__, gpa);
1316 kvm_release_page_clean(page);
1317 kvm_inject_gp(&svm->vcpu, 0);
1318 return NULL;
1319 }
1320 return page;
1321}
1322
1323static int nested_svm_do(struct vcpu_svm *svm,
1324 u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1325 int (*handler)(struct vcpu_svm *svm,
1326 void *arg1,
1327 void *arg2,
1328 void *opaque))
1329{
1330 struct page *arg1_page;
1331 struct page *arg2_page = NULL;
1332 void *arg1;
1333 void *arg2 = NULL;
1334 int retval;
1335
1336 arg1_page = nested_svm_get_page(svm, arg1_gpa);
1337 if(arg1_page == NULL)
1338 return 1;
1339
1340 if (arg2_gpa) {
1341 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1342 if(arg2_page == NULL) {
1343 kvm_release_page_clean(arg1_page);
1344 return 1;
1345 }
1346 }
1347
1348 arg1 = kmap_atomic(arg1_page, KM_USER0);
1349 if (arg2_gpa)
1350 arg2 = kmap_atomic(arg2_page, KM_USER1);
1351
1352 retval = handler(svm, arg1, arg2, opaque);
1353
1354 kunmap_atomic(arg1, KM_USER0);
1355 if (arg2_gpa)
1356 kunmap_atomic(arg2, KM_USER1);
1357
1358 kvm_release_page_dirty(arg1_page);
1359 if (arg2_gpa)
1360 kvm_release_page_dirty(arg2_page);
1361
1362 return retval;
1363}
1364
cf74a78b
AG		 1365static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1366 void *arg1,
1367 void *arg2,
1368 void *opaque)
1369{
1370 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1371 bool kvm_overrides = *(bool *)opaque;
1372 u32 exit_code = svm->vmcb->control.exit_code;
1373
1374 if (kvm_overrides) {
1375 switch (exit_code) {
1376 case SVM_EXIT_INTR:
1377 case SVM_EXIT_NMI:
1378 return 0;
1379 /* For now we are always handling NPFs when using them */
1380 case SVM_EXIT_NPF:
1381 if (npt_enabled)
1382 return 0;
1383 break;
1384 /* When we're shadowing, trap PFs */
1385 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1386 if (!npt_enabled)
1387 return 0;
1388 break;
1389 default:
1390 break;
1391 }
1392 }
1393
1394 switch (exit_code) {
1395 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1396 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1397 if (nested_vmcb->control.intercept_cr_read & cr_bits)
1398 return 1;
1399 break;
1400 }
1401 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1402 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1403 if (nested_vmcb->control.intercept_cr_write & cr_bits)
1404 return 1;
1405 break;
1406 }
1407 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1408 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1409 if (nested_vmcb->control.intercept_dr_read & dr_bits)
1410 return 1;
1411 break;
1412 }
1413 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1414 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1415 if (nested_vmcb->control.intercept_dr_write & dr_bits)
1416 return 1;
1417 break;
1418 }
1419 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1420 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1421 if (nested_vmcb->control.intercept_exceptions & excp_bits)
1422 return 1;
1423 break;
1424 }
1425 default: {
1426 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1427 nsvm_printk("exit code: 0x%x\n", exit_code);
1428 if (nested_vmcb->control.intercept & exit_bits)
1429 return 1;
1430 }
1431 }
1432
1433 return 0;
1434}
1435
1436static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1437 void *arg1, void *arg2,
1438 void *opaque)
1439{
1440 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1441 u8 *msrpm = (u8 *)arg2;
1442 u32 t0, t1;
1443 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1444 u32 param = svm->vmcb->control.exit_info_1 & 1;
1445
1446 if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1447 return 0;
1448
1449 switch(msr) {
1450 case 0 ... 0x1fff:
1451 t0 = (msr * 2) % 8;
1452 t1 = msr / 8;
1453 break;
1454 case 0xc0000000 ... 0xc0001fff:
1455 t0 = (8192 + msr - 0xc0000000) * 2;
1456 t1 = (t0 / 8);
1457 t0 %= 8;
1458 break;
1459 case 0xc0010000 ... 0xc0011fff:
1460 t0 = (16384 + msr - 0xc0010000) * 2;
1461 t1 = (t0 / 8);
1462 t0 %= 8;
1463 break;
1464 default:
1465 return 1;
1466 break;
1467 }
1468 if (msrpm[t1] & ((1 << param) << t0))
1469 return 1;
1470
1471 return 0;
1472}
1473
1474static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1475{
1476 bool k = kvm_override;
1477
1478 switch (svm->vmcb->control.exit_code) {
1479 case SVM_EXIT_MSR:
1480 return nested_svm_do(svm, svm->nested_vmcb,
1481 svm->nested_vmcb_msrpm, NULL,
1482 nested_svm_exit_handled_msr);
1483 default: break;
1484 }
1485
1486 return nested_svm_do(svm, svm->nested_vmcb, 0, &k,
1487 nested_svm_exit_handled_real);
1488}
1489
1490static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1491 void *arg2, void *opaque)
1492{
1493 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1494 struct vmcb *hsave = svm->hsave;
1495 u64 nested_save[] = { nested_vmcb->save.cr0,
1496 nested_vmcb->save.cr3,
1497 nested_vmcb->save.cr4,
1498 nested_vmcb->save.efer,
1499 nested_vmcb->control.intercept_cr_read,
1500 nested_vmcb->control.intercept_cr_write,
1501 nested_vmcb->control.intercept_dr_read,
1502 nested_vmcb->control.intercept_dr_write,
1503 nested_vmcb->control.intercept_exceptions,
1504 nested_vmcb->control.intercept,
1505 nested_vmcb->control.msrpm_base_pa,
1506 nested_vmcb->control.iopm_base_pa,
1507 nested_vmcb->control.tsc_offset };
1508
1509 /* Give the current vmcb to the guest */
1510 memcpy(nested_vmcb, svm->vmcb, sizeof(struct vmcb));
1511 nested_vmcb->save.cr0 = nested_save[0];
1512 if (!npt_enabled)
1513 nested_vmcb->save.cr3 = nested_save[1];
1514 nested_vmcb->save.cr4 = nested_save[2];
1515 nested_vmcb->save.efer = nested_save[3];
1516 nested_vmcb->control.intercept_cr_read = nested_save[4];
1517 nested_vmcb->control.intercept_cr_write = nested_save[5];
1518 nested_vmcb->control.intercept_dr_read = nested_save[6];
1519 nested_vmcb->control.intercept_dr_write = nested_save[7];
1520 nested_vmcb->control.intercept_exceptions = nested_save[8];
1521 nested_vmcb->control.intercept = nested_save[9];
1522 nested_vmcb->control.msrpm_base_pa = nested_save[10];
1523 nested_vmcb->control.iopm_base_pa = nested_save[11];
1524 nested_vmcb->control.tsc_offset = nested_save[12];
1525
1526 /* We always set V_INTR_MASKING and remember the old value in hflags */
1527 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1528 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1529
1530 if ((nested_vmcb->control.int_ctl & V_IRQ_MASK) &&
1531 (nested_vmcb->control.int_vector)) {
1532 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1533 nested_vmcb->control.int_vector);
1534 }
1535
1536 /* Restore the original control entries */
1537 svm->vmcb->control = hsave->control;
1538
1539 /* Kill any pending exceptions */
1540 if (svm->vcpu.arch.exception.pending == true)
1541 nsvm_printk("WARNING: Pending Exception\n");
1542 svm->vcpu.arch.exception.pending = false;
1543
1544 /* Restore selected save entries */
1545 svm->vmcb->save.es = hsave->save.es;
1546 svm->vmcb->save.cs = hsave->save.cs;
1547 svm->vmcb->save.ss = hsave->save.ss;
1548 svm->vmcb->save.ds = hsave->save.ds;
1549 svm->vmcb->save.gdtr = hsave->save.gdtr;
1550 svm->vmcb->save.idtr = hsave->save.idtr;
1551 svm->vmcb->save.rflags = hsave->save.rflags;
1552 svm_set_efer(&svm->vcpu, hsave->save.efer);
1553 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1554 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1555 if (npt_enabled) {
1556 svm->vmcb->save.cr3 = hsave->save.cr3;
1557 svm->vcpu.arch.cr3 = hsave->save.cr3;
1558 } else {
1559 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1560 }
1561 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1562 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1563 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1564 svm->vmcb->save.dr7 = 0;
1565 svm->vmcb->save.cpl = 0;
1566 svm->vmcb->control.exit_int_info = 0;
1567
1568 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1569 /* Exit nested SVM mode */
1570 svm->nested_vmcb = 0;
1571
1572 return 0;
1573}
1574
1575static int nested_svm_vmexit(struct vcpu_svm *svm)
1576{
1577 nsvm_printk("VMexit\n");
1578 if (nested_svm_do(svm, svm->nested_vmcb, 0,
1579 NULL, nested_svm_vmexit_real))
1580 return 1;
1581
1582 kvm_mmu_reset_context(&svm->vcpu);
1583 kvm_mmu_load(&svm->vcpu);
1584
1585 return 0;
1586}
3d6368ef
AG		 1587
1588static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1589 void *arg2, void *opaque)
1590{
1591 int i;
1592 u32 *nested_msrpm = (u32*)arg1;
1593 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1594 svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1595 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
1596
1597 return 0;
1598}
1599
1600static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1601 void *arg2, void *opaque)
1602{
1603 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1604 struct vmcb *hsave = svm->hsave;
1605
1606 /* nested_vmcb is our indicator if nested SVM is activated */
1607 svm->nested_vmcb = svm->vmcb->save.rax;
1608
1609 /* Clear internal status */
1610 svm->vcpu.arch.exception.pending = false;
1611
1612 /* Save the old vmcb, so we don't need to pick what we save, but
1613 can restore everything when a VMEXIT occurs */
1614 memcpy(hsave, svm->vmcb, sizeof(struct vmcb));
1615 /* We need to remember the original CR3 in the SPT case */
1616 if (!npt_enabled)
1617 hsave->save.cr3 = svm->vcpu.arch.cr3;
1618 hsave->save.cr4 = svm->vcpu.arch.cr4;
1619 hsave->save.rip = svm->next_rip;
1620
1621 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1622 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1623 else
1624 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1625
1626 /* Load the nested guest state */
1627 svm->vmcb->save.es = nested_vmcb->save.es;
1628 svm->vmcb->save.cs = nested_vmcb->save.cs;
1629 svm->vmcb->save.ss = nested_vmcb->save.ss;
1630 svm->vmcb->save.ds = nested_vmcb->save.ds;
1631 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1632 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1633 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1634 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1635 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1636 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1637 if (npt_enabled) {
1638 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1639 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1640 } else {
1641 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1642 kvm_mmu_reset_context(&svm->vcpu);
1643 }
1644 svm->vmcb->save.cr2 = nested_vmcb->save.cr2;
1645 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1646 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1647 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1648 /* In case we don't even reach vcpu_run, the fields are not updated */
1649 svm->vmcb->save.rax = nested_vmcb->save.rax;
1650 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1651 svm->vmcb->save.rip = nested_vmcb->save.rip;
1652 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1653 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1654 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1655
1656 /* We don't want a nested guest to be more powerful than the guest,
1657 so all intercepts are ORed */
1658 svm->vmcb->control.intercept_cr_read |=
1659 nested_vmcb->control.intercept_cr_read;
1660 svm->vmcb->control.intercept_cr_write |=
1661 nested_vmcb->control.intercept_cr_write;
1662 svm->vmcb->control.intercept_dr_read |=
1663 nested_vmcb->control.intercept_dr_read;
1664 svm->vmcb->control.intercept_dr_write |=
1665 nested_vmcb->control.intercept_dr_write;
1666 svm->vmcb->control.intercept_exceptions |=
1667 nested_vmcb->control.intercept_exceptions;
1668
1669 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1670
1671 svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1672
1673 force_new_asid(&svm->vcpu);
1674 svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1675 svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1676 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1677 if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1678 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1679 nested_vmcb->control.int_ctl);
1680 }
1681 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1682 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1683 else
1684 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1685
1686 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1687 nested_vmcb->control.exit_int_info,
1688 nested_vmcb->control.int_state);
1689
1690 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1691 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1692 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1693 if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1694 nsvm_printk("Injecting Event: 0x%x\n",
1695 nested_vmcb->control.event_inj);
1696 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1697 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1698
1699 svm->vcpu.arch.hflags |= HF_GIF_MASK;
1700
1701 return 0;
1702}
1703
5542675b
AG		 1704static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1705{
1706 to_vmcb->save.fs = from_vmcb->save.fs;
1707 to_vmcb->save.gs = from_vmcb->save.gs;
1708 to_vmcb->save.tr = from_vmcb->save.tr;
1709 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1710 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1711 to_vmcb->save.star = from_vmcb->save.star;
1712 to_vmcb->save.lstar = from_vmcb->save.lstar;
1713 to_vmcb->save.cstar = from_vmcb->save.cstar;
1714 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1715 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1716 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1717 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1718
1719 return 1;
1720}
1721
1722static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1723 void *arg2, void *opaque)
1724{
1725 return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1726}
1727
1728static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1729 void *arg2, void *opaque)
1730{
1731 return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1732}
1733
1734static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1735{
1736 if (nested_svm_check_permissions(svm))
1737 return 1;
1738
1739 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1740 skip_emulated_instruction(&svm->vcpu);
1741
1742 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1743
1744 return 1;
1745}
1746
1747static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1748{
1749 if (nested_svm_check_permissions(svm))
1750 return 1;
1751
1752 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1753 skip_emulated_instruction(&svm->vcpu);
1754
1755 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1756
1757 return 1;
1758}
1759
3d6368ef
AG		 1760static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1761{
1762 nsvm_printk("VMrun\n");
1763 if (nested_svm_check_permissions(svm))
1764 return 1;
1765
1766 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1767 skip_emulated_instruction(&svm->vcpu);
1768
1769 if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1770 NULL, nested_svm_vmrun))
1771 return 1;
1772
1773 if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
1774 NULL, nested_svm_vmrun_msrpm))
1775 return 1;
1776
1777 return 1;
1778}
1779
1371d904
AG		 1780static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1781{
1782 if (nested_svm_check_permissions(svm))
1783 return 1;
1784
1785 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1786 skip_emulated_instruction(&svm->vcpu);
1787
1788 svm->vcpu.arch.hflags |= HF_GIF_MASK;
1789
1790 return 1;
1791}
1792
1793static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1794{
1795 if (nested_svm_check_permissions(svm))
1796 return 1;
1797
1798 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1799 skip_emulated_instruction(&svm->vcpu);
1800
1801 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1802
1803 /* After a CLGI no interrupts should come */
1804 svm_clear_vintr(svm);
1805 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1806
1807 return 1;
1808}
1809
e756fc62
RR		 1810static int invalid_op_interception(struct vcpu_svm *svm,
1811 struct kvm_run *kvm_run)
6aa8b732 1812{
7ee5d940 1813 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 1814 return 1;
1815}
1816
e756fc62
RR		 1817static int task_switch_interception(struct vcpu_svm *svm,
1818 struct kvm_run *kvm_run)
6aa8b732 1819{
37817f29
IE		 1820 u16 tss_selector;
1821
1822 tss_selector = (u16)svm->vmcb->control.exit_info_1;
1823 if (svm->vmcb->control.exit_info_2 &
1824 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1825 return kvm_task_switch(&svm->vcpu, tss_selector,
1826 TASK_SWITCH_IRET);
1827 if (svm->vmcb->control.exit_info_2 &
1828 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1829 return kvm_task_switch(&svm->vcpu, tss_selector,
1830 TASK_SWITCH_JMP);
1831 return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
6aa8b732
AK		 1832}
1833
e756fc62 1834static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1835{
5fdbf976 1836 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 1837 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 1838 return 1;
6aa8b732
AK		 1839}
1840
a7052897
MT		 1841static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1842{
1843 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1844 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1845 return 1;
1846}
1847
e756fc62
RR		 1848static int emulate_on_interception(struct vcpu_svm *svm,
1849 struct kvm_run *kvm_run)
6aa8b732 1850{
3427318f 1851 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
b8688d51 1852 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 1853 return 1;
1854}
1855
1d075434
JR		 1856static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1857{
1858 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1859 if (irqchip_in_kernel(svm->vcpu.kvm))
1860 return 1;
1861 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1862 return 0;
1863}
1864
6aa8b732
AK		 1865static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1866{
a2fa3e9f
GH		 1867 struct vcpu_svm *svm = to_svm(vcpu);
1868
6aa8b732 1869 switch (ecx) {
6aa8b732
AK		 1870 case MSR_IA32_TIME_STAMP_COUNTER: {
1871 u64 tsc;
1872
1873 rdtscll(tsc);
a2fa3e9f 1874 *data = svm->vmcb->control.tsc_offset + tsc;
6aa8b732
AK		 1875 break;
1876 }
0e859cac 1877 case MSR_K6_STAR:
a2fa3e9f 1878 *data = svm->vmcb->save.star;
6aa8b732 1879 break;
0e859cac 1880#ifdef CONFIG_X86_64
6aa8b732 1881 case MSR_LSTAR:
a2fa3e9f 1882 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 1883 break;
1884 case MSR_CSTAR:
a2fa3e9f 1885 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 1886 break;
1887 case MSR_KERNEL_GS_BASE:
a2fa3e9f 1888 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 1889 break;
1890 case MSR_SYSCALL_MASK:
a2fa3e9f 1891 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 1892 break;
1893#endif
1894 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 1895 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 1896 break;
1897 case MSR_IA32_SYSENTER_EIP:
a2fa3e9f 1898 *data = svm->vmcb->save.sysenter_eip;
6aa8b732
AK		 1899 break;
1900 case MSR_IA32_SYSENTER_ESP:
a2fa3e9f 1901 *data = svm->vmcb->save.sysenter_esp;
6aa8b732 1902 break;
a2938c80
JR		 1903 /* Nobody will change the following 5 values in the VMCB so
1904 we can safely return them on rdmsr. They will always be 0
1905 until LBRV is implemented. */
1906 case MSR_IA32_DEBUGCTLMSR:
1907 *data = svm->vmcb->save.dbgctl;
1908 break;
1909 case MSR_IA32_LASTBRANCHFROMIP:
1910 *data = svm->vmcb->save.br_from;
1911 break;
1912 case MSR_IA32_LASTBRANCHTOIP:
1913 *data = svm->vmcb->save.br_to;
1914 break;
1915 case MSR_IA32_LASTINTFROMIP:
1916 *data = svm->vmcb->save.last_excp_from;
1917 break;
1918 case MSR_IA32_LASTINTTOIP:
1919 *data = svm->vmcb->save.last_excp_to;
1920 break;
b286d5d8
AG		 1921 case MSR_VM_HSAVE_PA:
1922 *data = svm->hsave_msr;
1923 break;
eb6f302e
JR		 1924 case MSR_VM_CR:
1925 *data = 0;
1926 break;
6aa8b732 1927 default:
3bab1f5d 1928 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 1929 }
1930 return 0;
1931}
1932
e756fc62 1933static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1934{
ad312c7c 1935 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 1936 u64 data;
1937
e756fc62 1938 if (svm_get_msr(&svm->vcpu, ecx, &data))
c1a5d4f9 1939 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 1940 else {
af9ca2d7
JR		 1941 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1942 (u32)(data >> 32), handler);
1943
5fdbf976 1944 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 1945 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 1946 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 1947 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 1948 }
1949 return 1;
1950}
1951
1952static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1953{
a2fa3e9f
GH		 1954 struct vcpu_svm *svm = to_svm(vcpu);
1955
6aa8b732 1956 switch (ecx) {
6aa8b732
AK		 1957 case MSR_IA32_TIME_STAMP_COUNTER: {
1958 u64 tsc;
1959
1960 rdtscll(tsc);
a2fa3e9f 1961 svm->vmcb->control.tsc_offset = data - tsc;
6aa8b732
AK		 1962 break;
1963 }
0e859cac 1964 case MSR_K6_STAR:
a2fa3e9f 1965 svm->vmcb->save.star = data;
6aa8b732 1966 break;
49b14f24 1967#ifdef CONFIG_X86_64
6aa8b732 1968 case MSR_LSTAR:
a2fa3e9f 1969 svm->vmcb->save.lstar = data;
6aa8b732
AK		 1970 break;
1971 case MSR_CSTAR:
a2fa3e9f 1972 svm->vmcb->save.cstar = data;
6aa8b732
AK		 1973 break;
1974 case MSR_KERNEL_GS_BASE:
a2fa3e9f 1975 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 1976 break;
1977 case MSR_SYSCALL_MASK:
a2fa3e9f 1978 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 1979 break;
1980#endif
1981 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 1982 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 1983 break;
1984 case MSR_IA32_SYSENTER_EIP:
a2fa3e9f 1985 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 1986 break;
1987 case MSR_IA32_SYSENTER_ESP:
a2fa3e9f 1988 svm->vmcb->save.sysenter_esp = data;
6aa8b732 1989 break;
a2938c80 1990 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 1991 if (!svm_has(SVM_FEATURE_LBRV)) {
1992 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 1993 __func__, data);
24e09cbf
JR		 1994 break;
1995 }
1996 if (data & DEBUGCTL_RESERVED_BITS)
1997 return 1;
1998
1999 svm->vmcb->save.dbgctl = data;
2000 if (data & (1ULL<<0))
2001 svm_enable_lbrv(svm);
2002 else
2003 svm_disable_lbrv(svm);
a2938c80 2004 break;
62b9abaa
JR		 2005 case MSR_K7_EVNTSEL0:
2006 case MSR_K7_EVNTSEL1:
2007 case MSR_K7_EVNTSEL2:
2008 case MSR_K7_EVNTSEL3:
14ae51b6
CL		 2009 case MSR_K7_PERFCTR0:
2010 case MSR_K7_PERFCTR1:
2011 case MSR_K7_PERFCTR2:
2012 case MSR_K7_PERFCTR3:
62b9abaa 2013 /*
14ae51b6
CL		 2014 * Just discard all writes to the performance counters; this
2015 * should keep both older linux and windows 64-bit guests
2016 * happy
62b9abaa 2017 */
14ae51b6
CL		 2018 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
2019
b286d5d8
AG		 2020 break;
2021 case MSR_VM_HSAVE_PA:
2022 svm->hsave_msr = data;
62b9abaa 2023 break;
6aa8b732 2024 default:
3bab1f5d 2025 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2026 }
2027 return 0;
2028}
2029
e756fc62 2030static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2031{
ad312c7c 2032 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2033 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2034 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7
JR		 2035
2036 KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
2037 handler);
2038
5fdbf976 2039 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2040 if (svm_set_msr(&svm->vcpu, ecx, data))
c1a5d4f9 2041 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2042 else
e756fc62 2043 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2044 return 1;
2045}
2046
e756fc62 2047static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2048{
e756fc62
RR		 2049 if (svm->vmcb->control.exit_info_1)
2050 return wrmsr_interception(svm, kvm_run);
6aa8b732 2051 else
e756fc62 2052 return rdmsr_interception(svm, kvm_run);
6aa8b732
AK		 2053}
2054
e756fc62 2055static int interrupt_window_interception(struct vcpu_svm *svm,
c1150d8c
DL		 2056 struct kvm_run *kvm_run)
2057{
af9ca2d7
JR		 2058 KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
2059
f0b85051 2060 svm_clear_vintr(svm);
85f455f7 2061 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2062 /*
2063 * If the user space waits to inject interrupts, exit as soon as
2064 * possible
2065 */
2066 if (kvm_run->request_interrupt_window &&
ad312c7c 2067 !svm->vcpu.arch.irq_summary) {
e756fc62 2068 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2069 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2070 return 0;
2071 }
2072
2073 return 1;
2074}
2075
e756fc62 2076static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
6aa8b732
AK		 2077 struct kvm_run *kvm_run) = {
2078 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2079 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2080 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2081 [SVM_EXIT_READ_CR8] = emulate_on_interception,
6aa8b732
AK		 2082 /* for now: */
2083 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2084 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2085 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2086 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2087 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2088 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2089 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2090 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2091 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2092 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2093 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2094 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2095 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2096 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2097 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2098 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2099 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2100 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2101 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2102 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2103 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2104 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2105 [SVM_EXIT_SMI] = nop_on_interception,
2106 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2107 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2108 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2109 [SVM_EXIT_CPUID] = cpuid_interception,
cf5a94d1 2110 [SVM_EXIT_INVD] = emulate_on_interception,
6aa8b732 2111 [SVM_EXIT_HLT] = halt_interception,
a7052897 2112 [SVM_EXIT_INVLPG] = invlpg_interception,
6aa8b732
AK		 2113 [SVM_EXIT_INVLPGA] = invalid_op_interception,
2114 [SVM_EXIT_IOIO] = io_interception,
2115 [SVM_EXIT_MSR] = msr_interception,
2116 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2117 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2118 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2119 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2120 [SVM_EXIT_VMLOAD] = vmload_interception,
2121 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2122 [SVM_EXIT_STGI] = stgi_interception,
2123 [SVM_EXIT_CLGI] = clgi_interception,
6aa8b732 2124 [SVM_EXIT_SKINIT] = invalid_op_interception,
cf5a94d1 2125 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2126 [SVM_EXIT_MONITOR] = invalid_op_interception,
2127 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2128 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2129};
2130
04d2cc77 2131static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
6aa8b732 2132{
04d2cc77 2133 struct vcpu_svm *svm = to_svm(vcpu);
a2fa3e9f 2134 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2135
af9ca2d7
JR		 2136 KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
2137 (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
2138
cf74a78b
AG		 2139 if (is_nested(svm)) {
2140 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2141 exit_code, svm->vmcb->control.exit_info_1,
2142 svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2143 if (nested_svm_exit_handled(svm, true)) {
2144 nested_svm_vmexit(svm);
2145 nsvm_printk("-> #VMEXIT\n");
2146 return 1;
2147 }
2148 }
2149
709ddebf
JR		 2150 if (npt_enabled) {
2151 int mmu_reload = 0;
2152 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2153 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2154 mmu_reload = 1;
2155 }
2156 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2157 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2158 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2159 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
2160 kvm_inject_gp(vcpu, 0);
2161 return 1;
2162 }
2163 }
2164 if (mmu_reload) {
2165 kvm_mmu_reset_context(vcpu);
2166 kvm_mmu_load(vcpu);
2167 }
2168 }
2169
04d2cc77
AK		 2170 kvm_reput_irq(svm);
2171
2172 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2173 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2174 kvm_run->fail_entry.hardware_entry_failure_reason
2175 = svm->vmcb->control.exit_code;
2176 return 0;
2177 }
2178
a2fa3e9f 2179 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf
JR		 2180 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2181 exit_code != SVM_EXIT_NPF)
6aa8b732
AK		 2182 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2183 "exit_code 0x%x\n",
b8688d51 2184 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2185 exit_code);
2186
9d8f549d 2187 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2188 || !svm_exit_handlers[exit_code]) {
6aa8b732 2189 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2190 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2191 return 0;
2192 }
2193
e756fc62 2194 return svm_exit_handlers[exit_code](svm, kvm_run);
6aa8b732
AK		 2195}
2196
2197static void reload_tss(struct kvm_vcpu *vcpu)
2198{
2199 int cpu = raw_smp_processor_id();
2200
2201 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
d77c26fc 2202 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2203 load_TR_desc();
2204}
2205
e756fc62 2206static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2207{
2208 int cpu = raw_smp_processor_id();
2209
2210 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2211
a2fa3e9f 2212 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
e756fc62 2213 if (svm->vcpu.cpu != cpu ||
a2fa3e9f 2214 svm->asid_generation != svm_data->asid_generation)
e756fc62 2215 new_asid(svm, svm_data);
6aa8b732
AK		 2216}
2217
2218
85f455f7 2219static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2220{
2221 struct vmcb_control_area *control;
2222
af9ca2d7
JR		 2223 KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
2224
fa89a817 2225 ++svm->vcpu.stat.irq_injections;
e756fc62 2226 control = &svm->vmcb->control;
85f455f7 2227 control->int_vector = irq;
6aa8b732
AK		 2228 control->int_ctl &= ~V_INTR_PRIO_MASK;
2229 control->int_ctl |= V_IRQ_MASK |
2230 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2231}
2232
2a8067f1
ED		 2233static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
2234{
2235 struct vcpu_svm *svm = to_svm(vcpu);
2236
cf74a78b
AG		 2237 nested_svm_intr(svm);
2238
2a8067f1
ED		 2239 svm_inject_irq(svm, irq);
2240}
2241
aaacfc9a
JR		 2242static void update_cr8_intercept(struct kvm_vcpu *vcpu)
2243{
2244 struct vcpu_svm *svm = to_svm(vcpu);
2245 struct vmcb *vmcb = svm->vmcb;
2246 int max_irr, tpr;
2247
2248 if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
2249 return;
2250
2251 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2252
2253 max_irr = kvm_lapic_find_highest_irr(vcpu);
2254 if (max_irr == -1)
2255 return;
2256
2257 tpr = kvm_lapic_get_cr8(vcpu) << 4;
2258
2259 if (tpr >= (max_irr & 0xf0))
2260 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2261}
2262
04d2cc77 2263static void svm_intr_assist(struct kvm_vcpu *vcpu)
6aa8b732 2264{
04d2cc77 2265 struct vcpu_svm *svm = to_svm(vcpu);
85f455f7
ED		 2266 struct vmcb *vmcb = svm->vmcb;
2267 int intr_vector = -1;
2268
2269 if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
2270 ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
2271 intr_vector = vmcb->control.exit_int_info &
2272 SVM_EVTINJ_VEC_MASK;
2273 vmcb->control.exit_int_info = 0;
2274 svm_inject_irq(svm, intr_vector);
aaacfc9a 2275 goto out;
85f455f7
ED		 2276 }
2277
2278 if (vmcb->control.int_ctl & V_IRQ_MASK)
aaacfc9a 2279 goto out;
85f455f7 2280
1b9778da 2281 if (!kvm_cpu_has_interrupt(vcpu))
aaacfc9a 2282 goto out;
85f455f7 2283
cf74a78b
AG		 2284 if (nested_svm_intr(svm))
2285 goto out;
2286
1371d904
AG		 2287 if (!(svm->vcpu.arch.hflags & HF_GIF_MASK))
2288 goto out;
2289
85f455f7
ED		 2290 if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
2291 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
2292 (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
2293 /* unable to deliver irq, set pending irq */
f0b85051 2294 svm_set_vintr(svm);
85f455f7 2295 svm_inject_irq(svm, 0x0);
aaacfc9a 2296 goto out;
85f455f7
ED		 2297 }
2298 /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1b9778da 2299 intr_vector = kvm_cpu_get_interrupt(vcpu);
85f455f7 2300 svm_inject_irq(svm, intr_vector);
aaacfc9a
JR		 2301out:
2302 update_cr8_intercept(vcpu);
85f455f7
ED		 2303}
2304
2305static void kvm_reput_irq(struct vcpu_svm *svm)
2306{
e756fc62 2307 struct vmcb_control_area *control = &svm->vmcb->control;
6aa8b732 2308
7017fc3d
ED		 2309 if ((control->int_ctl & V_IRQ_MASK)
2310 && !irqchip_in_kernel(svm->vcpu.kvm)) {
6aa8b732 2311 control->int_ctl &= ~V_IRQ_MASK;
e756fc62 2312 push_irq(&svm->vcpu, control->int_vector);
6aa8b732 2313 }
c1150d8c 2314
ad312c7c 2315 svm->vcpu.arch.interrupt_window_open =
1371d904
AG		 2316 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2317 (svm->vcpu.arch.hflags & HF_GIF_MASK);
c1150d8c
DL		 2318}
2319
85f455f7
ED		 2320static void svm_do_inject_vector(struct vcpu_svm *svm)
2321{
2322 struct kvm_vcpu *vcpu = &svm->vcpu;
ad312c7c
ZX		 2323 int word_index = __ffs(vcpu->arch.irq_summary);
2324 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
85f455f7
ED		 2325 int irq = word_index * BITS_PER_LONG + bit_index;
2326
ad312c7c
ZX		 2327 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2328 if (!vcpu->arch.irq_pending[word_index])
2329 clear_bit(word_index, &vcpu->arch.irq_summary);
85f455f7
ED		 2330 svm_inject_irq(svm, irq);
2331}
2332
04d2cc77 2333static void do_interrupt_requests(struct kvm_vcpu *vcpu,
c1150d8c
DL		 2334 struct kvm_run *kvm_run)
2335{
04d2cc77 2336 struct vcpu_svm *svm = to_svm(vcpu);
a2fa3e9f 2337 struct vmcb_control_area *control = &svm->vmcb->control;
c1150d8c 2338
cf74a78b
AG		 2339 if (nested_svm_intr(svm))
2340 return;
2341
ad312c7c 2342 svm->vcpu.arch.interrupt_window_open =
c1150d8c 2343 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1371d904
AG		 2344 (svm->vmcb->save.rflags & X86_EFLAGS_IF) &&
2345 (svm->vcpu.arch.hflags & HF_GIF_MASK));
c1150d8c 2346
ad312c7c 2347 if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
c1150d8c
DL		 2348 /*
2349 * If interrupts enabled, and not blocked by sti or mov ss. Good.
2350 */
85f455f7 2351 svm_do_inject_vector(svm);
c1150d8c
DL		 2352
2353 /*
2354 * Interrupts blocked. Wait for unblock.
2355 */
ad312c7c
ZX		 2356 if (!svm->vcpu.arch.interrupt_window_open &&
2357 (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
f0b85051
AG		 2358 svm_set_vintr(svm);
2359 else
2360 svm_clear_vintr(svm);
c1150d8c
DL		 2361}
2362
cbc94022
IE		 2363static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2364{
2365 return 0;
2366}
2367
6aa8b732
AK		 2368static void save_db_regs(unsigned long *db_regs)
2369{
5aff458e
AK		 2370 asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
2371 asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
2372 asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
2373 asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
6aa8b732
AK		 2374}
2375
2376static void load_db_regs(unsigned long *db_regs)
2377{
5aff458e
AK		 2378 asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
2379 asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
2380 asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
2381 asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
6aa8b732
AK		 2382}
2383
d9e368d6
AK		 2384static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2385{
2386 force_new_asid(vcpu);
2387}
2388
04d2cc77
AK		 2389static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2390{
2391}
2392
d7bf8221
JR		 2393static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2394{
2395 struct vcpu_svm *svm = to_svm(vcpu);
2396
2397 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2398 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2399 kvm_lapic_set_tpr(vcpu, cr8);
2400 }
2401}
2402
649d6864
JR		 2403static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2404{
2405 struct vcpu_svm *svm = to_svm(vcpu);
2406 u64 cr8;
2407
2408 if (!irqchip_in_kernel(vcpu->kvm))
2409 return;
2410
2411 cr8 = kvm_get_cr8(vcpu);
2412 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2413 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2414}
2415
80e31d4f
AK		 2416#ifdef CONFIG_X86_64
2417#define R "r"
2418#else
2419#define R "e"
2420#endif
2421
04d2cc77 2422static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2423{
a2fa3e9f 2424 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2425 u16 fs_selector;
2426 u16 gs_selector;
2427 u16 ldt_selector;
d9e368d6 2428
5fdbf976
MT		 2429 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2430 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2431 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2432
e756fc62 2433 pre_svm_run(svm);
6aa8b732 2434
649d6864
JR		 2435 sync_lapic_to_cr8(vcpu);
2436
6aa8b732 2437 save_host_msrs(vcpu);
d6e88aec
AK		 2438 fs_selector = kvm_read_fs();
2439 gs_selector = kvm_read_gs();
2440 ldt_selector = kvm_read_ldt();
a2fa3e9f
GH		 2441 svm->host_cr2 = kvm_read_cr2();
2442 svm->host_dr6 = read_dr6();
2443 svm->host_dr7 = read_dr7();
3d6368ef
AG		 2444 if (!is_nested(svm))
2445 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2446 /* required for live migration with NPT */
2447 if (npt_enabled)
2448 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2449
a2fa3e9f 2450 if (svm->vmcb->save.dr7 & 0xff) {
6aa8b732 2451 write_dr7(0);
a2fa3e9f
GH		 2452 save_db_regs(svm->host_db_regs);
2453 load_db_regs(svm->db_regs);
6aa8b732 2454 }
36241b8c 2455
04d2cc77
AK		 2456 clgi();
2457
2458 local_irq_enable();
36241b8c 2459
6aa8b732 2460 asm volatile (
80e31d4f
AK		 2461 "push %%"R"bp; \n\t"
2462 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2463 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2464 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2465 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2466 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2467 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2468#ifdef CONFIG_X86_64
fb3f0f51
RR		 2469 "mov %c[r8](%[svm]), %%r8 \n\t"
2470 "mov %c[r9](%[svm]), %%r9 \n\t"
2471 "mov %c[r10](%[svm]), %%r10 \n\t"
2472 "mov %c[r11](%[svm]), %%r11 \n\t"
2473 "mov %c[r12](%[svm]), %%r12 \n\t"
2474 "mov %c[r13](%[svm]), %%r13 \n\t"
2475 "mov %c[r14](%[svm]), %%r14 \n\t"
2476 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2477#endif
2478
6aa8b732 2479 /* Enter guest mode */
80e31d4f
AK		 2480 "push %%"R"ax \n\t"
2481 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2482 __ex(SVM_VMLOAD) "\n\t"
2483 __ex(SVM_VMRUN) "\n\t"
2484 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2485 "pop %%"R"ax \n\t"
6aa8b732
AK		 2486
2487 /* Save guest registers, load host registers */
80e31d4f
AK		 2488 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2489 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2490 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2491 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2492 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2493 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2494#ifdef CONFIG_X86_64
fb3f0f51
RR		 2495 "mov %%r8, %c[r8](%[svm]) \n\t"
2496 "mov %%r9, %c[r9](%[svm]) \n\t"
2497 "mov %%r10, %c[r10](%[svm]) \n\t"
2498 "mov %%r11, %c[r11](%[svm]) \n\t"
2499 "mov %%r12, %c[r12](%[svm]) \n\t"
2500 "mov %%r13, %c[r13](%[svm]) \n\t"
2501 "mov %%r14, %c[r14](%[svm]) \n\t"
2502 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2503#endif
80e31d4f 2504 "pop %%"R"bp"
6aa8b732 2505 :
fb3f0f51 2506 : [svm]"a"(svm),
6aa8b732 2507 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2508 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2509 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2510 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2511 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2512 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2513 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2514#ifdef CONFIG_X86_64
ad312c7c
ZX		 2515 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2516 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2517 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2518 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2519 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2520 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2521 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2522 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2523#endif
54a08c04 2524 : "cc", "memory"
80e31d4f 2525 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2526#ifdef CONFIG_X86_64
54a08c04
LV		 2527 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2528#endif
2529 );
6aa8b732 2530
a2fa3e9f
GH		 2531 if ((svm->vmcb->save.dr7 & 0xff))
2532 load_db_regs(svm->host_db_regs);
6aa8b732 2533
ad312c7c 2534 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2535 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2536 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2537 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2538
a2fa3e9f
GH		 2539 write_dr6(svm->host_dr6);
2540 write_dr7(svm->host_dr7);
2541 kvm_write_cr2(svm->host_cr2);
6aa8b732 2542
d6e88aec
AK		 2543 kvm_load_fs(fs_selector);
2544 kvm_load_gs(gs_selector);
2545 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2546 load_host_msrs(vcpu);
2547
2548 reload_tss(vcpu);
2549
56ba47dd
AK		 2550 local_irq_disable();
2551
2552 stgi();
2553
d7bf8221
JR		 2554 sync_cr8_to_lapic(vcpu);
2555
a2fa3e9f 2556 svm->next_rip = 0;
6aa8b732
AK		 2557}
2558
80e31d4f
AK		 2559#undef R
2560
6aa8b732
AK		 2561static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2562{
a2fa3e9f
GH		 2563 struct vcpu_svm *svm = to_svm(vcpu);
2564
709ddebf
JR		 2565 if (npt_enabled) {
2566 svm->vmcb->control.nested_cr3 = root;
2567 force_new_asid(vcpu);
2568 return;
2569 }
2570
a2fa3e9f 2571 svm->vmcb->save.cr3 = root;
6aa8b732 2572 force_new_asid(vcpu);
7807fa6c
AL		 2573
2574 if (vcpu->fpu_active) {
a2fa3e9f
GH		 2575 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2576 svm->vmcb->save.cr0 |= X86_CR0_TS;
7807fa6c
AL		 2577 vcpu->fpu_active = 0;
2578 }
6aa8b732
AK		 2579}
2580
6aa8b732
AK		 2581static int is_disabled(void)
2582{
6031a61c
JR		 2583 u64 vm_cr;
2584
2585 rdmsrl(MSR_VM_CR, vm_cr);
2586 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2587 return 1;
2588
6aa8b732
AK		 2589 return 0;
2590}
2591
102d8325
IM		 2592static void
2593svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2594{
2595 /*
2596 * Patch in the VMMCALL instruction:
2597 */
2598 hypercall[0] = 0x0f;
2599 hypercall[1] = 0x01;
2600 hypercall[2] = 0xd9;
102d8325
IM		 2601}
2602
002c7f7c
YS		 2603static void svm_check_processor_compat(void *rtn)
2604{
2605 *(int *)rtn = 0;
2606}
2607
774ead3a
AK		 2608static bool svm_cpu_has_accelerated_tpr(void)
2609{
2610 return false;
2611}
2612
67253af5
SY		 2613static int get_npt_level(void)
2614{
2615#ifdef CONFIG_X86_64
2616 return PT64_ROOT_LEVEL;
2617#else
2618 return PT32E_ROOT_LEVEL;
2619#endif
2620}
2621
64d4d521
SY		 2622static int svm_get_mt_mask_shift(void)
2623{
2624 return 0;
2625}
2626
cbdd1bea 2627static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 2628 .cpu_has_kvm_support = has_svm,
2629 .disabled_by_bios = is_disabled,
2630 .hardware_setup = svm_hardware_setup,
2631 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 2632 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 2633 .hardware_enable = svm_hardware_enable,
2634 .hardware_disable = svm_hardware_disable,
774ead3a 2635 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 2636
2637 .vcpu_create = svm_create_vcpu,
2638 .vcpu_free = svm_free_vcpu,
04d2cc77 2639 .vcpu_reset = svm_vcpu_reset,
6aa8b732 2640
04d2cc77 2641 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 2642 .vcpu_load = svm_vcpu_load,
2643 .vcpu_put = svm_vcpu_put,
2644
2645 .set_guest_debug = svm_guest_debug,
2646 .get_msr = svm_get_msr,
2647 .set_msr = svm_set_msr,
2648 .get_segment_base = svm_get_segment_base,
2649 .get_segment = svm_get_segment,
2650 .set_segment = svm_set_segment,
2e4d2653 2651 .get_cpl = svm_get_cpl,
1747fb71 2652 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
25c4c276 2653 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 2654 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 2655 .set_cr3 = svm_set_cr3,
2656 .set_cr4 = svm_set_cr4,
2657 .set_efer = svm_set_efer,
2658 .get_idt = svm_get_idt,
2659 .set_idt = svm_set_idt,
2660 .get_gdt = svm_get_gdt,
2661 .set_gdt = svm_set_gdt,
2662 .get_dr = svm_get_dr,
2663 .set_dr = svm_set_dr,
6aa8b732
AK		 2664 .get_rflags = svm_get_rflags,
2665 .set_rflags = svm_set_rflags,
2666
6aa8b732 2667 .tlb_flush = svm_flush_tlb,
6aa8b732 2668
6aa8b732 2669 .run = svm_vcpu_run,
04d2cc77 2670 .handle_exit = handle_exit,
6aa8b732 2671 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 2672 .patch_hypercall = svm_patch_hypercall,
2a8067f1
ED		 2673 .get_irq = svm_get_irq,
2674 .set_irq = svm_set_irq,
298101da
AK		 2675 .queue_exception = svm_queue_exception,
2676 .exception_injected = svm_exception_injected,
04d2cc77
AK		 2677 .inject_pending_irq = svm_intr_assist,
2678 .inject_pending_vectors = do_interrupt_requests,
cbc94022
IE		 2679
2680 .set_tss_addr = svm_set_tss_addr,
67253af5 2681 .get_tdp_level = get_npt_level,
64d4d521 2682 .get_mt_mask_shift = svm_get_mt_mask_shift,
6aa8b732
AK		 2683};
2684
2685static int __init svm_init(void)
2686{
cb498ea2 2687 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 2688 THIS_MODULE);
6aa8b732
AK		 2689}
2690
2691static void __exit svm_exit(void)
2692{
cb498ea2 2693 kvm_exit();
6aa8b732
AK		 2694}
2695
2696module_init(svm_init)
2697module_exit(svm_exit)
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