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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 8 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
9 | * |
10 | * Authors: | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * | |
14 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
15 | * the COPYING file in the top-level directory. | |
16 | * | |
17 | */ | |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
00b27a3e | 21 | #include "cpuid.h" |
d62caabb | 22 | #include "lapic.h" |
e495606d | 23 | |
edf88417 | 24 | #include <linux/kvm_host.h> |
6aa8b732 | 25 | #include <linux/module.h> |
9d8f549d | 26 | #include <linux/kernel.h> |
6aa8b732 AK |
27 | #include <linux/mm.h> |
28 | #include <linux/highmem.h> | |
e8edc6e0 | 29 | #include <linux/sched.h> |
c7addb90 | 30 | #include <linux/moduleparam.h> |
e9bda3b3 | 31 | #include <linux/mod_devicetable.h> |
af658dca | 32 | #include <linux/trace_events.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
cafd6659 | 34 | #include <linux/tboot.h> |
f4124500 | 35 | #include <linux/hrtimer.h> |
c207aee4 | 36 | #include <linux/frame.h> |
5fdbf976 | 37 | #include "kvm_cache_regs.h" |
35920a35 | 38 | #include "x86.h" |
e495606d | 39 | |
28b835d6 | 40 | #include <asm/cpu.h> |
6aa8b732 | 41 | #include <asm/io.h> |
3b3be0d1 | 42 | #include <asm/desc.h> |
13673a90 | 43 | #include <asm/vmx.h> |
6210e37b | 44 | #include <asm/virtext.h> |
a0861c02 | 45 | #include <asm/mce.h> |
952f07ec | 46 | #include <asm/fpu/internal.h> |
d7cd9796 | 47 | #include <asm/perf_event.h> |
81908bf4 | 48 | #include <asm/debugreg.h> |
8f536b76 | 49 | #include <asm/kexec.h> |
dab2087d | 50 | #include <asm/apic.h> |
efc64404 | 51 | #include <asm/irq_remapping.h> |
d6e41f11 | 52 | #include <asm/mmu_context.h> |
6aa8b732 | 53 | |
229456fc | 54 | #include "trace.h" |
25462f7f | 55 | #include "pmu.h" |
229456fc | 56 | |
4ecac3fd | 57 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
5e520e62 AK |
58 | #define __ex_clear(x, reg) \ |
59 | ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg) | |
4ecac3fd | 60 | |
6aa8b732 AK |
61 | MODULE_AUTHOR("Qumranet"); |
62 | MODULE_LICENSE("GPL"); | |
63 | ||
e9bda3b3 JT |
64 | static const struct x86_cpu_id vmx_cpu_id[] = { |
65 | X86_FEATURE_MATCH(X86_FEATURE_VMX), | |
66 | {} | |
67 | }; | |
68 | MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); | |
69 | ||
476bc001 | 70 | static bool __read_mostly enable_vpid = 1; |
736caefe | 71 | module_param_named(vpid, enable_vpid, bool, 0444); |
2384d2b3 | 72 | |
d02fcf50 PB |
73 | static bool __read_mostly enable_vnmi = 1; |
74 | module_param_named(vnmi, enable_vnmi, bool, S_IRUGO); | |
75 | ||
476bc001 | 76 | static bool __read_mostly flexpriority_enabled = 1; |
736caefe | 77 | module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); |
4c9fc8ef | 78 | |
476bc001 | 79 | static bool __read_mostly enable_ept = 1; |
736caefe | 80 | module_param_named(ept, enable_ept, bool, S_IRUGO); |
d56f546d | 81 | |
476bc001 | 82 | static bool __read_mostly enable_unrestricted_guest = 1; |
3a624e29 NK |
83 | module_param_named(unrestricted_guest, |
84 | enable_unrestricted_guest, bool, S_IRUGO); | |
85 | ||
83c3a331 XH |
86 | static bool __read_mostly enable_ept_ad_bits = 1; |
87 | module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); | |
88 | ||
a27685c3 | 89 | static bool __read_mostly emulate_invalid_guest_state = true; |
c1f8bc04 | 90 | module_param(emulate_invalid_guest_state, bool, S_IRUGO); |
04fa4d32 | 91 | |
476bc001 | 92 | static bool __read_mostly fasteoi = 1; |
58fbbf26 KT |
93 | module_param(fasteoi, bool, S_IRUGO); |
94 | ||
5a71785d | 95 | static bool __read_mostly enable_apicv = 1; |
01e439be | 96 | module_param(enable_apicv, bool, S_IRUGO); |
83d4c286 | 97 | |
abc4fc58 AG |
98 | static bool __read_mostly enable_shadow_vmcs = 1; |
99 | module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO); | |
801d3424 NHE |
100 | /* |
101 | * If nested=1, nested virtualization is supported, i.e., guests may use | |
102 | * VMX and be a hypervisor for its own guests. If nested=0, guests may not | |
103 | * use VMX instructions. | |
104 | */ | |
476bc001 | 105 | static bool __read_mostly nested = 0; |
801d3424 NHE |
106 | module_param(nested, bool, S_IRUGO); |
107 | ||
20300099 WL |
108 | static u64 __read_mostly host_xss; |
109 | ||
843e4330 KH |
110 | static bool __read_mostly enable_pml = 1; |
111 | module_param_named(pml, enable_pml, bool, S_IRUGO); | |
112 | ||
64903d61 HZ |
113 | #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL |
114 | ||
64672c95 YJ |
115 | /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ |
116 | static int __read_mostly cpu_preemption_timer_multi; | |
117 | static bool __read_mostly enable_preemption_timer = 1; | |
118 | #ifdef CONFIG_X86_64 | |
119 | module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); | |
120 | #endif | |
121 | ||
5037878e GN |
122 | #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD) |
123 | #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE) | |
cdc0e244 AK |
124 | #define KVM_VM_CR0_ALWAYS_ON \ |
125 | (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE) | |
4c38609a AK |
126 | #define KVM_CR4_GUEST_OWNED_BITS \ |
127 | (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
fd8cb433 | 128 | | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD) |
4c38609a | 129 | |
cdc0e244 AK |
130 | #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) |
131 | #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) | |
132 | ||
78ac8b47 AK |
133 | #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) |
134 | ||
f4124500 JK |
135 | #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5 |
136 | ||
16c2aec6 JD |
137 | /* |
138 | * Hyper-V requires all of these, so mark them as supported even though | |
139 | * they are just treated the same as all-context. | |
140 | */ | |
141 | #define VMX_VPID_EXTENT_SUPPORTED_MASK \ | |
142 | (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \ | |
143 | VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \ | |
144 | VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \ | |
145 | VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT) | |
146 | ||
4b8d54f9 ZE |
147 | /* |
148 | * These 2 parameters are used to config the controls for Pause-Loop Exiting: | |
149 | * ple_gap: upper bound on the amount of time between two successive | |
150 | * executions of PAUSE in a loop. Also indicate if ple enabled. | |
00c25bce | 151 | * According to test, this time is usually smaller than 128 cycles. |
4b8d54f9 ZE |
152 | * ple_window: upper bound on the amount of time a guest is allowed to execute |
153 | * in a PAUSE loop. Tests indicate that most spinlocks are held for | |
154 | * less than 2^12 cycles | |
155 | * Time is measured based on a counter that runs at the same rate as the TSC, | |
156 | * refer SDM volume 3b section 21.6.13 & 22.1.3. | |
157 | */ | |
b4a2d31d RK |
158 | #define KVM_VMX_DEFAULT_PLE_GAP 128 |
159 | #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 | |
160 | #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2 | |
161 | #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0 | |
162 | #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \ | |
163 | INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW | |
164 | ||
4b8d54f9 ZE |
165 | static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP; |
166 | module_param(ple_gap, int, S_IRUGO); | |
167 | ||
168 | static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; | |
169 | module_param(ple_window, int, S_IRUGO); | |
170 | ||
b4a2d31d RK |
171 | /* Default doubles per-vcpu window every exit. */ |
172 | static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW; | |
173 | module_param(ple_window_grow, int, S_IRUGO); | |
174 | ||
175 | /* Default resets per-vcpu window every exit to ple_window. */ | |
176 | static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK; | |
177 | module_param(ple_window_shrink, int, S_IRUGO); | |
178 | ||
179 | /* Default is to compute the maximum so we can never overflow. */ | |
180 | static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; | |
181 | static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; | |
182 | module_param(ple_window_max, int, S_IRUGO); | |
183 | ||
83287ea4 AK |
184 | extern const ulong vmx_return; |
185 | ||
8bf00a52 | 186 | #define NR_AUTOLOAD_MSRS 8 |
ff2f6fe9 | 187 | #define VMCS02_POOL_SIZE 1 |
61d2ef2c | 188 | |
a2fa3e9f GH |
189 | struct vmcs { |
190 | u32 revision_id; | |
191 | u32 abort; | |
192 | char data[0]; | |
193 | }; | |
194 | ||
d462b819 NHE |
195 | /* |
196 | * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also | |
197 | * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs | |
198 | * loaded on this CPU (so we can clear them if the CPU goes down). | |
199 | */ | |
200 | struct loaded_vmcs { | |
201 | struct vmcs *vmcs; | |
355f4fb1 | 202 | struct vmcs *shadow_vmcs; |
d462b819 | 203 | int cpu; |
4c4a6f79 PB |
204 | bool launched; |
205 | bool nmi_known_unmasked; | |
44889942 LP |
206 | unsigned long vmcs_host_cr3; /* May not match real cr3 */ |
207 | unsigned long vmcs_host_cr4; /* May not match real cr4 */ | |
8a1b4392 PB |
208 | /* Support for vnmi-less CPUs */ |
209 | int soft_vnmi_blocked; | |
210 | ktime_t entry_time; | |
211 | s64 vnmi_blocked_time; | |
d462b819 NHE |
212 | struct list_head loaded_vmcss_on_cpu_link; |
213 | }; | |
214 | ||
26bb0981 AK |
215 | struct shared_msr_entry { |
216 | unsigned index; | |
217 | u64 data; | |
d5696725 | 218 | u64 mask; |
26bb0981 AK |
219 | }; |
220 | ||
a9d30f33 NHE |
221 | /* |
222 | * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a | |
223 | * single nested guest (L2), hence the name vmcs12. Any VMX implementation has | |
224 | * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is | |
225 | * stored in guest memory specified by VMPTRLD, but is opaque to the guest, | |
226 | * which must access it using VMREAD/VMWRITE/VMCLEAR instructions. | |
227 | * More than one of these structures may exist, if L1 runs multiple L2 guests. | |
228 | * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the | |
229 | * underlying hardware which will be used to run L2. | |
230 | * This structure is packed to ensure that its layout is identical across | |
231 | * machines (necessary for live migration). | |
232 | * If there are changes in this struct, VMCS12_REVISION must be changed. | |
233 | */ | |
22bd0358 | 234 | typedef u64 natural_width; |
a9d30f33 NHE |
235 | struct __packed vmcs12 { |
236 | /* According to the Intel spec, a VMCS region must start with the | |
237 | * following two fields. Then follow implementation-specific data. | |
238 | */ | |
239 | u32 revision_id; | |
240 | u32 abort; | |
22bd0358 | 241 | |
27d6c865 NHE |
242 | u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */ |
243 | u32 padding[7]; /* room for future expansion */ | |
244 | ||
22bd0358 NHE |
245 | u64 io_bitmap_a; |
246 | u64 io_bitmap_b; | |
247 | u64 msr_bitmap; | |
248 | u64 vm_exit_msr_store_addr; | |
249 | u64 vm_exit_msr_load_addr; | |
250 | u64 vm_entry_msr_load_addr; | |
251 | u64 tsc_offset; | |
252 | u64 virtual_apic_page_addr; | |
253 | u64 apic_access_addr; | |
705699a1 | 254 | u64 posted_intr_desc_addr; |
27c42a1b | 255 | u64 vm_function_control; |
22bd0358 | 256 | u64 ept_pointer; |
608406e2 WV |
257 | u64 eoi_exit_bitmap0; |
258 | u64 eoi_exit_bitmap1; | |
259 | u64 eoi_exit_bitmap2; | |
260 | u64 eoi_exit_bitmap3; | |
41ab9372 | 261 | u64 eptp_list_address; |
81dc01f7 | 262 | u64 xss_exit_bitmap; |
22bd0358 NHE |
263 | u64 guest_physical_address; |
264 | u64 vmcs_link_pointer; | |
c5f983f6 | 265 | u64 pml_address; |
22bd0358 NHE |
266 | u64 guest_ia32_debugctl; |
267 | u64 guest_ia32_pat; | |
268 | u64 guest_ia32_efer; | |
269 | u64 guest_ia32_perf_global_ctrl; | |
270 | u64 guest_pdptr0; | |
271 | u64 guest_pdptr1; | |
272 | u64 guest_pdptr2; | |
273 | u64 guest_pdptr3; | |
36be0b9d | 274 | u64 guest_bndcfgs; |
22bd0358 NHE |
275 | u64 host_ia32_pat; |
276 | u64 host_ia32_efer; | |
277 | u64 host_ia32_perf_global_ctrl; | |
278 | u64 padding64[8]; /* room for future expansion */ | |
279 | /* | |
280 | * To allow migration of L1 (complete with its L2 guests) between | |
281 | * machines of different natural widths (32 or 64 bit), we cannot have | |
282 | * unsigned long fields with no explict size. We use u64 (aliased | |
283 | * natural_width) instead. Luckily, x86 is little-endian. | |
284 | */ | |
285 | natural_width cr0_guest_host_mask; | |
286 | natural_width cr4_guest_host_mask; | |
287 | natural_width cr0_read_shadow; | |
288 | natural_width cr4_read_shadow; | |
289 | natural_width cr3_target_value0; | |
290 | natural_width cr3_target_value1; | |
291 | natural_width cr3_target_value2; | |
292 | natural_width cr3_target_value3; | |
293 | natural_width exit_qualification; | |
294 | natural_width guest_linear_address; | |
295 | natural_width guest_cr0; | |
296 | natural_width guest_cr3; | |
297 | natural_width guest_cr4; | |
298 | natural_width guest_es_base; | |
299 | natural_width guest_cs_base; | |
300 | natural_width guest_ss_base; | |
301 | natural_width guest_ds_base; | |
302 | natural_width guest_fs_base; | |
303 | natural_width guest_gs_base; | |
304 | natural_width guest_ldtr_base; | |
305 | natural_width guest_tr_base; | |
306 | natural_width guest_gdtr_base; | |
307 | natural_width guest_idtr_base; | |
308 | natural_width guest_dr7; | |
309 | natural_width guest_rsp; | |
310 | natural_width guest_rip; | |
311 | natural_width guest_rflags; | |
312 | natural_width guest_pending_dbg_exceptions; | |
313 | natural_width guest_sysenter_esp; | |
314 | natural_width guest_sysenter_eip; | |
315 | natural_width host_cr0; | |
316 | natural_width host_cr3; | |
317 | natural_width host_cr4; | |
318 | natural_width host_fs_base; | |
319 | natural_width host_gs_base; | |
320 | natural_width host_tr_base; | |
321 | natural_width host_gdtr_base; | |
322 | natural_width host_idtr_base; | |
323 | natural_width host_ia32_sysenter_esp; | |
324 | natural_width host_ia32_sysenter_eip; | |
325 | natural_width host_rsp; | |
326 | natural_width host_rip; | |
327 | natural_width paddingl[8]; /* room for future expansion */ | |
328 | u32 pin_based_vm_exec_control; | |
329 | u32 cpu_based_vm_exec_control; | |
330 | u32 exception_bitmap; | |
331 | u32 page_fault_error_code_mask; | |
332 | u32 page_fault_error_code_match; | |
333 | u32 cr3_target_count; | |
334 | u32 vm_exit_controls; | |
335 | u32 vm_exit_msr_store_count; | |
336 | u32 vm_exit_msr_load_count; | |
337 | u32 vm_entry_controls; | |
338 | u32 vm_entry_msr_load_count; | |
339 | u32 vm_entry_intr_info_field; | |
340 | u32 vm_entry_exception_error_code; | |
341 | u32 vm_entry_instruction_len; | |
342 | u32 tpr_threshold; | |
343 | u32 secondary_vm_exec_control; | |
344 | u32 vm_instruction_error; | |
345 | u32 vm_exit_reason; | |
346 | u32 vm_exit_intr_info; | |
347 | u32 vm_exit_intr_error_code; | |
348 | u32 idt_vectoring_info_field; | |
349 | u32 idt_vectoring_error_code; | |
350 | u32 vm_exit_instruction_len; | |
351 | u32 vmx_instruction_info; | |
352 | u32 guest_es_limit; | |
353 | u32 guest_cs_limit; | |
354 | u32 guest_ss_limit; | |
355 | u32 guest_ds_limit; | |
356 | u32 guest_fs_limit; | |
357 | u32 guest_gs_limit; | |
358 | u32 guest_ldtr_limit; | |
359 | u32 guest_tr_limit; | |
360 | u32 guest_gdtr_limit; | |
361 | u32 guest_idtr_limit; | |
362 | u32 guest_es_ar_bytes; | |
363 | u32 guest_cs_ar_bytes; | |
364 | u32 guest_ss_ar_bytes; | |
365 | u32 guest_ds_ar_bytes; | |
366 | u32 guest_fs_ar_bytes; | |
367 | u32 guest_gs_ar_bytes; | |
368 | u32 guest_ldtr_ar_bytes; | |
369 | u32 guest_tr_ar_bytes; | |
370 | u32 guest_interruptibility_info; | |
371 | u32 guest_activity_state; | |
372 | u32 guest_sysenter_cs; | |
373 | u32 host_ia32_sysenter_cs; | |
0238ea91 JK |
374 | u32 vmx_preemption_timer_value; |
375 | u32 padding32[7]; /* room for future expansion */ | |
22bd0358 | 376 | u16 virtual_processor_id; |
705699a1 | 377 | u16 posted_intr_nv; |
22bd0358 NHE |
378 | u16 guest_es_selector; |
379 | u16 guest_cs_selector; | |
380 | u16 guest_ss_selector; | |
381 | u16 guest_ds_selector; | |
382 | u16 guest_fs_selector; | |
383 | u16 guest_gs_selector; | |
384 | u16 guest_ldtr_selector; | |
385 | u16 guest_tr_selector; | |
608406e2 | 386 | u16 guest_intr_status; |
c5f983f6 | 387 | u16 guest_pml_index; |
22bd0358 NHE |
388 | u16 host_es_selector; |
389 | u16 host_cs_selector; | |
390 | u16 host_ss_selector; | |
391 | u16 host_ds_selector; | |
392 | u16 host_fs_selector; | |
393 | u16 host_gs_selector; | |
394 | u16 host_tr_selector; | |
a9d30f33 NHE |
395 | }; |
396 | ||
397 | /* | |
398 | * VMCS12_REVISION is an arbitrary id that should be changed if the content or | |
399 | * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and | |
400 | * VMPTRLD verifies that the VMCS region that L1 is loading contains this id. | |
401 | */ | |
402 | #define VMCS12_REVISION 0x11e57ed0 | |
403 | ||
404 | /* | |
405 | * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region | |
406 | * and any VMCS region. Although only sizeof(struct vmcs12) are used by the | |
407 | * current implementation, 4K are reserved to avoid future complications. | |
408 | */ | |
409 | #define VMCS12_SIZE 0x1000 | |
410 | ||
ff2f6fe9 NHE |
411 | /* Used to remember the last vmcs02 used for some recently used vmcs12s */ |
412 | struct vmcs02_list { | |
413 | struct list_head list; | |
414 | gpa_t vmptr; | |
415 | struct loaded_vmcs vmcs02; | |
416 | }; | |
417 | ||
ec378aee NHE |
418 | /* |
419 | * The nested_vmx structure is part of vcpu_vmx, and holds information we need | |
420 | * for correct emulation of VMX (i.e., nested VMX) on this vcpu. | |
421 | */ | |
422 | struct nested_vmx { | |
423 | /* Has the level1 guest done vmxon? */ | |
424 | bool vmxon; | |
3573e22c | 425 | gpa_t vmxon_ptr; |
c5f983f6 | 426 | bool pml_full; |
a9d30f33 NHE |
427 | |
428 | /* The guest-physical address of the current VMCS L1 keeps for L2 */ | |
429 | gpa_t current_vmptr; | |
4f2777bc DM |
430 | /* |
431 | * Cache of the guest's VMCS, existing outside of guest memory. | |
432 | * Loaded from guest memory during VMPTRLD. Flushed to guest | |
8ca44e88 | 433 | * memory during VMCLEAR and VMPTRLD. |
4f2777bc DM |
434 | */ |
435 | struct vmcs12 *cached_vmcs12; | |
012f83cb AG |
436 | /* |
437 | * Indicates if the shadow vmcs must be updated with the | |
438 | * data hold by vmcs12 | |
439 | */ | |
440 | bool sync_shadow_vmcs; | |
ff2f6fe9 NHE |
441 | |
442 | /* vmcs02_list cache of VMCSs recently used to run L2 guests */ | |
443 | struct list_head vmcs02_pool; | |
444 | int vmcs02_num; | |
dccbfcf5 | 445 | bool change_vmcs01_virtual_x2apic_mode; |
644d711a NHE |
446 | /* L2 must run next, and mustn't decide to exit to L1. */ |
447 | bool nested_run_pending; | |
fe3ef05c NHE |
448 | /* |
449 | * Guest pages referred to in vmcs02 with host-physical pointers, so | |
450 | * we must keep them pinned while L2 runs. | |
451 | */ | |
452 | struct page *apic_access_page; | |
a7c0b07d | 453 | struct page *virtual_apic_page; |
705699a1 WV |
454 | struct page *pi_desc_page; |
455 | struct pi_desc *pi_desc; | |
456 | bool pi_pending; | |
457 | u16 posted_intr_nv; | |
f4124500 | 458 | |
d048c098 RK |
459 | unsigned long *msr_bitmap; |
460 | ||
f4124500 JK |
461 | struct hrtimer preemption_timer; |
462 | bool preemption_timer_expired; | |
2996fca0 JK |
463 | |
464 | /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */ | |
465 | u64 vmcs01_debugctl; | |
b9c237bb | 466 | |
5c614b35 WL |
467 | u16 vpid02; |
468 | u16 last_vpid; | |
469 | ||
0115f9cb DM |
470 | /* |
471 | * We only store the "true" versions of the VMX capability MSRs. We | |
472 | * generate the "non-true" versions by setting the must-be-1 bits | |
473 | * according to the SDM. | |
474 | */ | |
b9c237bb WV |
475 | u32 nested_vmx_procbased_ctls_low; |
476 | u32 nested_vmx_procbased_ctls_high; | |
b9c237bb WV |
477 | u32 nested_vmx_secondary_ctls_low; |
478 | u32 nested_vmx_secondary_ctls_high; | |
479 | u32 nested_vmx_pinbased_ctls_low; | |
480 | u32 nested_vmx_pinbased_ctls_high; | |
481 | u32 nested_vmx_exit_ctls_low; | |
482 | u32 nested_vmx_exit_ctls_high; | |
b9c237bb WV |
483 | u32 nested_vmx_entry_ctls_low; |
484 | u32 nested_vmx_entry_ctls_high; | |
b9c237bb WV |
485 | u32 nested_vmx_misc_low; |
486 | u32 nested_vmx_misc_high; | |
487 | u32 nested_vmx_ept_caps; | |
99b83ac8 | 488 | u32 nested_vmx_vpid_caps; |
62cc6b9d DM |
489 | u64 nested_vmx_basic; |
490 | u64 nested_vmx_cr0_fixed0; | |
491 | u64 nested_vmx_cr0_fixed1; | |
492 | u64 nested_vmx_cr4_fixed0; | |
493 | u64 nested_vmx_cr4_fixed1; | |
494 | u64 nested_vmx_vmcs_enum; | |
27c42a1b | 495 | u64 nested_vmx_vmfunc_controls; |
72e9cbdb LP |
496 | |
497 | /* SMM related state */ | |
498 | struct { | |
499 | /* in VMX operation on SMM entry? */ | |
500 | bool vmxon; | |
501 | /* in guest mode on SMM entry? */ | |
502 | bool guest_mode; | |
503 | } smm; | |
ec378aee NHE |
504 | }; |
505 | ||
01e439be | 506 | #define POSTED_INTR_ON 0 |
ebbfc765 FW |
507 | #define POSTED_INTR_SN 1 |
508 | ||
01e439be YZ |
509 | /* Posted-Interrupt Descriptor */ |
510 | struct pi_desc { | |
511 | u32 pir[8]; /* Posted interrupt requested */ | |
6ef1522f FW |
512 | union { |
513 | struct { | |
514 | /* bit 256 - Outstanding Notification */ | |
515 | u16 on : 1, | |
516 | /* bit 257 - Suppress Notification */ | |
517 | sn : 1, | |
518 | /* bit 271:258 - Reserved */ | |
519 | rsvd_1 : 14; | |
520 | /* bit 279:272 - Notification Vector */ | |
521 | u8 nv; | |
522 | /* bit 287:280 - Reserved */ | |
523 | u8 rsvd_2; | |
524 | /* bit 319:288 - Notification Destination */ | |
525 | u32 ndst; | |
526 | }; | |
527 | u64 control; | |
528 | }; | |
529 | u32 rsvd[6]; | |
01e439be YZ |
530 | } __aligned(64); |
531 | ||
a20ed54d YZ |
532 | static bool pi_test_and_set_on(struct pi_desc *pi_desc) |
533 | { | |
534 | return test_and_set_bit(POSTED_INTR_ON, | |
535 | (unsigned long *)&pi_desc->control); | |
536 | } | |
537 | ||
538 | static bool pi_test_and_clear_on(struct pi_desc *pi_desc) | |
539 | { | |
540 | return test_and_clear_bit(POSTED_INTR_ON, | |
541 | (unsigned long *)&pi_desc->control); | |
542 | } | |
543 | ||
544 | static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc) | |
545 | { | |
546 | return test_and_set_bit(vector, (unsigned long *)pi_desc->pir); | |
547 | } | |
548 | ||
ebbfc765 FW |
549 | static inline void pi_clear_sn(struct pi_desc *pi_desc) |
550 | { | |
551 | return clear_bit(POSTED_INTR_SN, | |
552 | (unsigned long *)&pi_desc->control); | |
553 | } | |
554 | ||
555 | static inline void pi_set_sn(struct pi_desc *pi_desc) | |
556 | { | |
557 | return set_bit(POSTED_INTR_SN, | |
558 | (unsigned long *)&pi_desc->control); | |
559 | } | |
560 | ||
ad361091 PB |
561 | static inline void pi_clear_on(struct pi_desc *pi_desc) |
562 | { | |
563 | clear_bit(POSTED_INTR_ON, | |
564 | (unsigned long *)&pi_desc->control); | |
565 | } | |
566 | ||
ebbfc765 FW |
567 | static inline int pi_test_on(struct pi_desc *pi_desc) |
568 | { | |
569 | return test_bit(POSTED_INTR_ON, | |
570 | (unsigned long *)&pi_desc->control); | |
571 | } | |
572 | ||
573 | static inline int pi_test_sn(struct pi_desc *pi_desc) | |
574 | { | |
575 | return test_bit(POSTED_INTR_SN, | |
576 | (unsigned long *)&pi_desc->control); | |
577 | } | |
578 | ||
a2fa3e9f | 579 | struct vcpu_vmx { |
fb3f0f51 | 580 | struct kvm_vcpu vcpu; |
313dbd49 | 581 | unsigned long host_rsp; |
29bd8a78 | 582 | u8 fail; |
51aa01d1 | 583 | u32 exit_intr_info; |
1155f76a | 584 | u32 idt_vectoring_info; |
6de12732 | 585 | ulong rflags; |
26bb0981 | 586 | struct shared_msr_entry *guest_msrs; |
a2fa3e9f GH |
587 | int nmsrs; |
588 | int save_nmsrs; | |
a547c6db | 589 | unsigned long host_idt_base; |
a2fa3e9f | 590 | #ifdef CONFIG_X86_64 |
44ea2b17 AK |
591 | u64 msr_host_kernel_gs_base; |
592 | u64 msr_guest_kernel_gs_base; | |
a2fa3e9f | 593 | #endif |
2961e876 GN |
594 | u32 vm_entry_controls_shadow; |
595 | u32 vm_exit_controls_shadow; | |
80154d77 PB |
596 | u32 secondary_exec_control; |
597 | ||
d462b819 NHE |
598 | /* |
599 | * loaded_vmcs points to the VMCS currently used in this vcpu. For a | |
600 | * non-nested (L1) guest, it always points to vmcs01. For a nested | |
601 | * guest (L2), it points to a different VMCS. | |
602 | */ | |
603 | struct loaded_vmcs vmcs01; | |
604 | struct loaded_vmcs *loaded_vmcs; | |
605 | bool __launched; /* temporary, used in vmx_vcpu_run */ | |
61d2ef2c AK |
606 | struct msr_autoload { |
607 | unsigned nr; | |
608 | struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS]; | |
609 | struct vmx_msr_entry host[NR_AUTOLOAD_MSRS]; | |
610 | } msr_autoload; | |
a2fa3e9f GH |
611 | struct { |
612 | int loaded; | |
613 | u16 fs_sel, gs_sel, ldt_sel; | |
b2da15ac AK |
614 | #ifdef CONFIG_X86_64 |
615 | u16 ds_sel, es_sel; | |
616 | #endif | |
152d3f2f LV |
617 | int gs_ldt_reload_needed; |
618 | int fs_reload_needed; | |
da8999d3 | 619 | u64 msr_host_bndcfgs; |
d77c26fc | 620 | } host_state; |
9c8cba37 | 621 | struct { |
7ffd92c5 | 622 | int vm86_active; |
78ac8b47 | 623 | ulong save_rflags; |
f5f7b2fe AK |
624 | struct kvm_segment segs[8]; |
625 | } rmode; | |
626 | struct { | |
627 | u32 bitmask; /* 4 bits per segment (1 bit per field) */ | |
7ffd92c5 AK |
628 | struct kvm_save_segment { |
629 | u16 selector; | |
630 | unsigned long base; | |
631 | u32 limit; | |
632 | u32 ar; | |
f5f7b2fe | 633 | } seg[8]; |
2fb92db1 | 634 | } segment_cache; |
2384d2b3 | 635 | int vpid; |
04fa4d32 | 636 | bool emulation_required; |
3b86cd99 | 637 | |
a0861c02 | 638 | u32 exit_reason; |
4e47c7a6 | 639 | |
01e439be YZ |
640 | /* Posted interrupt descriptor */ |
641 | struct pi_desc pi_desc; | |
642 | ||
ec378aee NHE |
643 | /* Support for a guest hypervisor (nested VMX) */ |
644 | struct nested_vmx nested; | |
a7653ecd RK |
645 | |
646 | /* Dynamic PLE window. */ | |
647 | int ple_window; | |
648 | bool ple_window_dirty; | |
843e4330 KH |
649 | |
650 | /* Support for PML */ | |
651 | #define PML_ENTITY_NUM 512 | |
652 | struct page *pml_pg; | |
2680d6da | 653 | |
64672c95 YJ |
654 | /* apic deadline value in host tsc */ |
655 | u64 hv_deadline_tsc; | |
656 | ||
2680d6da | 657 | u64 current_tsc_ratio; |
1be0e61c | 658 | |
1be0e61c | 659 | u32 host_pkru; |
3b84080b | 660 | |
37e4c997 HZ |
661 | /* |
662 | * Only bits masked by msr_ia32_feature_control_valid_bits can be set in | |
663 | * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included | |
664 | * in msr_ia32_feature_control_valid_bits. | |
665 | */ | |
3b84080b | 666 | u64 msr_ia32_feature_control; |
37e4c997 | 667 | u64 msr_ia32_feature_control_valid_bits; |
a2fa3e9f GH |
668 | }; |
669 | ||
2fb92db1 AK |
670 | enum segment_cache_field { |
671 | SEG_FIELD_SEL = 0, | |
672 | SEG_FIELD_BASE = 1, | |
673 | SEG_FIELD_LIMIT = 2, | |
674 | SEG_FIELD_AR = 3, | |
675 | ||
676 | SEG_FIELD_NR = 4 | |
677 | }; | |
678 | ||
a2fa3e9f GH |
679 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) |
680 | { | |
fb3f0f51 | 681 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
682 | } |
683 | ||
efc64404 FW |
684 | static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu) |
685 | { | |
686 | return &(to_vmx(vcpu)->pi_desc); | |
687 | } | |
688 | ||
22bd0358 NHE |
689 | #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x) |
690 | #define FIELD(number, name) [number] = VMCS12_OFFSET(name) | |
691 | #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \ | |
692 | [number##_HIGH] = VMCS12_OFFSET(name)+4 | |
693 | ||
4607c2d7 | 694 | |
fe2b201b | 695 | static unsigned long shadow_read_only_fields[] = { |
4607c2d7 AG |
696 | /* |
697 | * We do NOT shadow fields that are modified when L0 | |
698 | * traps and emulates any vmx instruction (e.g. VMPTRLD, | |
699 | * VMXON...) executed by L1. | |
700 | * For example, VM_INSTRUCTION_ERROR is read | |
701 | * by L1 if a vmx instruction fails (part of the error path). | |
702 | * Note the code assumes this logic. If for some reason | |
703 | * we start shadowing these fields then we need to | |
704 | * force a shadow sync when L0 emulates vmx instructions | |
705 | * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified | |
706 | * by nested_vmx_failValid) | |
707 | */ | |
708 | VM_EXIT_REASON, | |
709 | VM_EXIT_INTR_INFO, | |
710 | VM_EXIT_INSTRUCTION_LEN, | |
711 | IDT_VECTORING_INFO_FIELD, | |
712 | IDT_VECTORING_ERROR_CODE, | |
713 | VM_EXIT_INTR_ERROR_CODE, | |
714 | EXIT_QUALIFICATION, | |
715 | GUEST_LINEAR_ADDRESS, | |
716 | GUEST_PHYSICAL_ADDRESS | |
717 | }; | |
fe2b201b | 718 | static int max_shadow_read_only_fields = |
4607c2d7 AG |
719 | ARRAY_SIZE(shadow_read_only_fields); |
720 | ||
fe2b201b | 721 | static unsigned long shadow_read_write_fields[] = { |
a7c0b07d | 722 | TPR_THRESHOLD, |
4607c2d7 AG |
723 | GUEST_RIP, |
724 | GUEST_RSP, | |
725 | GUEST_CR0, | |
726 | GUEST_CR3, | |
727 | GUEST_CR4, | |
728 | GUEST_INTERRUPTIBILITY_INFO, | |
729 | GUEST_RFLAGS, | |
730 | GUEST_CS_SELECTOR, | |
731 | GUEST_CS_AR_BYTES, | |
732 | GUEST_CS_LIMIT, | |
733 | GUEST_CS_BASE, | |
734 | GUEST_ES_BASE, | |
36be0b9d | 735 | GUEST_BNDCFGS, |
4607c2d7 AG |
736 | CR0_GUEST_HOST_MASK, |
737 | CR0_READ_SHADOW, | |
738 | CR4_READ_SHADOW, | |
739 | TSC_OFFSET, | |
740 | EXCEPTION_BITMAP, | |
741 | CPU_BASED_VM_EXEC_CONTROL, | |
742 | VM_ENTRY_EXCEPTION_ERROR_CODE, | |
743 | VM_ENTRY_INTR_INFO_FIELD, | |
744 | VM_ENTRY_INSTRUCTION_LEN, | |
745 | VM_ENTRY_EXCEPTION_ERROR_CODE, | |
746 | HOST_FS_BASE, | |
747 | HOST_GS_BASE, | |
748 | HOST_FS_SELECTOR, | |
749 | HOST_GS_SELECTOR | |
750 | }; | |
fe2b201b | 751 | static int max_shadow_read_write_fields = |
4607c2d7 AG |
752 | ARRAY_SIZE(shadow_read_write_fields); |
753 | ||
772e0318 | 754 | static const unsigned short vmcs_field_to_offset_table[] = { |
22bd0358 | 755 | FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id), |
705699a1 | 756 | FIELD(POSTED_INTR_NV, posted_intr_nv), |
22bd0358 NHE |
757 | FIELD(GUEST_ES_SELECTOR, guest_es_selector), |
758 | FIELD(GUEST_CS_SELECTOR, guest_cs_selector), | |
759 | FIELD(GUEST_SS_SELECTOR, guest_ss_selector), | |
760 | FIELD(GUEST_DS_SELECTOR, guest_ds_selector), | |
761 | FIELD(GUEST_FS_SELECTOR, guest_fs_selector), | |
762 | FIELD(GUEST_GS_SELECTOR, guest_gs_selector), | |
763 | FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector), | |
764 | FIELD(GUEST_TR_SELECTOR, guest_tr_selector), | |
608406e2 | 765 | FIELD(GUEST_INTR_STATUS, guest_intr_status), |
c5f983f6 | 766 | FIELD(GUEST_PML_INDEX, guest_pml_index), |
22bd0358 NHE |
767 | FIELD(HOST_ES_SELECTOR, host_es_selector), |
768 | FIELD(HOST_CS_SELECTOR, host_cs_selector), | |
769 | FIELD(HOST_SS_SELECTOR, host_ss_selector), | |
770 | FIELD(HOST_DS_SELECTOR, host_ds_selector), | |
771 | FIELD(HOST_FS_SELECTOR, host_fs_selector), | |
772 | FIELD(HOST_GS_SELECTOR, host_gs_selector), | |
773 | FIELD(HOST_TR_SELECTOR, host_tr_selector), | |
774 | FIELD64(IO_BITMAP_A, io_bitmap_a), | |
775 | FIELD64(IO_BITMAP_B, io_bitmap_b), | |
776 | FIELD64(MSR_BITMAP, msr_bitmap), | |
777 | FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr), | |
778 | FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr), | |
779 | FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr), | |
780 | FIELD64(TSC_OFFSET, tsc_offset), | |
781 | FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr), | |
782 | FIELD64(APIC_ACCESS_ADDR, apic_access_addr), | |
705699a1 | 783 | FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr), |
27c42a1b | 784 | FIELD64(VM_FUNCTION_CONTROL, vm_function_control), |
22bd0358 | 785 | FIELD64(EPT_POINTER, ept_pointer), |
608406e2 WV |
786 | FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0), |
787 | FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1), | |
788 | FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2), | |
789 | FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3), | |
41ab9372 | 790 | FIELD64(EPTP_LIST_ADDRESS, eptp_list_address), |
81dc01f7 | 791 | FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap), |
22bd0358 NHE |
792 | FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address), |
793 | FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer), | |
c5f983f6 | 794 | FIELD64(PML_ADDRESS, pml_address), |
22bd0358 NHE |
795 | FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl), |
796 | FIELD64(GUEST_IA32_PAT, guest_ia32_pat), | |
797 | FIELD64(GUEST_IA32_EFER, guest_ia32_efer), | |
798 | FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl), | |
799 | FIELD64(GUEST_PDPTR0, guest_pdptr0), | |
800 | FIELD64(GUEST_PDPTR1, guest_pdptr1), | |
801 | FIELD64(GUEST_PDPTR2, guest_pdptr2), | |
802 | FIELD64(GUEST_PDPTR3, guest_pdptr3), | |
36be0b9d | 803 | FIELD64(GUEST_BNDCFGS, guest_bndcfgs), |
22bd0358 NHE |
804 | FIELD64(HOST_IA32_PAT, host_ia32_pat), |
805 | FIELD64(HOST_IA32_EFER, host_ia32_efer), | |
806 | FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl), | |
807 | FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control), | |
808 | FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control), | |
809 | FIELD(EXCEPTION_BITMAP, exception_bitmap), | |
810 | FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask), | |
811 | FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match), | |
812 | FIELD(CR3_TARGET_COUNT, cr3_target_count), | |
813 | FIELD(VM_EXIT_CONTROLS, vm_exit_controls), | |
814 | FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count), | |
815 | FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count), | |
816 | FIELD(VM_ENTRY_CONTROLS, vm_entry_controls), | |
817 | FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count), | |
818 | FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field), | |
819 | FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code), | |
820 | FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len), | |
821 | FIELD(TPR_THRESHOLD, tpr_threshold), | |
822 | FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control), | |
823 | FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error), | |
824 | FIELD(VM_EXIT_REASON, vm_exit_reason), | |
825 | FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info), | |
826 | FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code), | |
827 | FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field), | |
828 | FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code), | |
829 | FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len), | |
830 | FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info), | |
831 | FIELD(GUEST_ES_LIMIT, guest_es_limit), | |
832 | FIELD(GUEST_CS_LIMIT, guest_cs_limit), | |
833 | FIELD(GUEST_SS_LIMIT, guest_ss_limit), | |
834 | FIELD(GUEST_DS_LIMIT, guest_ds_limit), | |
835 | FIELD(GUEST_FS_LIMIT, guest_fs_limit), | |
836 | FIELD(GUEST_GS_LIMIT, guest_gs_limit), | |
837 | FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit), | |
838 | FIELD(GUEST_TR_LIMIT, guest_tr_limit), | |
839 | FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit), | |
840 | FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit), | |
841 | FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes), | |
842 | FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes), | |
843 | FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes), | |
844 | FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes), | |
845 | FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes), | |
846 | FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes), | |
847 | FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes), | |
848 | FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes), | |
849 | FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info), | |
850 | FIELD(GUEST_ACTIVITY_STATE, guest_activity_state), | |
851 | FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs), | |
852 | FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs), | |
0238ea91 | 853 | FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value), |
22bd0358 NHE |
854 | FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask), |
855 | FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask), | |
856 | FIELD(CR0_READ_SHADOW, cr0_read_shadow), | |
857 | FIELD(CR4_READ_SHADOW, cr4_read_shadow), | |
858 | FIELD(CR3_TARGET_VALUE0, cr3_target_value0), | |
859 | FIELD(CR3_TARGET_VALUE1, cr3_target_value1), | |
860 | FIELD(CR3_TARGET_VALUE2, cr3_target_value2), | |
861 | FIELD(CR3_TARGET_VALUE3, cr3_target_value3), | |
862 | FIELD(EXIT_QUALIFICATION, exit_qualification), | |
863 | FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address), | |
864 | FIELD(GUEST_CR0, guest_cr0), | |
865 | FIELD(GUEST_CR3, guest_cr3), | |
866 | FIELD(GUEST_CR4, guest_cr4), | |
867 | FIELD(GUEST_ES_BASE, guest_es_base), | |
868 | FIELD(GUEST_CS_BASE, guest_cs_base), | |
869 | FIELD(GUEST_SS_BASE, guest_ss_base), | |
870 | FIELD(GUEST_DS_BASE, guest_ds_base), | |
871 | FIELD(GUEST_FS_BASE, guest_fs_base), | |
872 | FIELD(GUEST_GS_BASE, guest_gs_base), | |
873 | FIELD(GUEST_LDTR_BASE, guest_ldtr_base), | |
874 | FIELD(GUEST_TR_BASE, guest_tr_base), | |
875 | FIELD(GUEST_GDTR_BASE, guest_gdtr_base), | |
876 | FIELD(GUEST_IDTR_BASE, guest_idtr_base), | |
877 | FIELD(GUEST_DR7, guest_dr7), | |
878 | FIELD(GUEST_RSP, guest_rsp), | |
879 | FIELD(GUEST_RIP, guest_rip), | |
880 | FIELD(GUEST_RFLAGS, guest_rflags), | |
881 | FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions), | |
882 | FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp), | |
883 | FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip), | |
884 | FIELD(HOST_CR0, host_cr0), | |
885 | FIELD(HOST_CR3, host_cr3), | |
886 | FIELD(HOST_CR4, host_cr4), | |
887 | FIELD(HOST_FS_BASE, host_fs_base), | |
888 | FIELD(HOST_GS_BASE, host_gs_base), | |
889 | FIELD(HOST_TR_BASE, host_tr_base), | |
890 | FIELD(HOST_GDTR_BASE, host_gdtr_base), | |
891 | FIELD(HOST_IDTR_BASE, host_idtr_base), | |
892 | FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp), | |
893 | FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip), | |
894 | FIELD(HOST_RSP, host_rsp), | |
895 | FIELD(HOST_RIP, host_rip), | |
896 | }; | |
22bd0358 NHE |
897 | |
898 | static inline short vmcs_field_to_offset(unsigned long field) | |
899 | { | |
a2ae9df7 PB |
900 | BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX); |
901 | ||
902 | if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) || | |
903 | vmcs_field_to_offset_table[field] == 0) | |
904 | return -ENOENT; | |
905 | ||
22bd0358 NHE |
906 | return vmcs_field_to_offset_table[field]; |
907 | } | |
908 | ||
a9d30f33 NHE |
909 | static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu) |
910 | { | |
4f2777bc | 911 | return to_vmx(vcpu)->nested.cached_vmcs12; |
a9d30f33 NHE |
912 | } |
913 | ||
995f00a6 | 914 | static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu); |
bfd0a56b | 915 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu); |
995f00a6 | 916 | static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa); |
f53cd63c | 917 | static bool vmx_xsaves_supported(void); |
b246dd5d OW |
918 | static void vmx_set_segment(struct kvm_vcpu *vcpu, |
919 | struct kvm_segment *var, int seg); | |
920 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
921 | struct kvm_segment *var, int seg); | |
d99e4152 GN |
922 | static bool guest_state_valid(struct kvm_vcpu *vcpu); |
923 | static u32 vmx_segment_access_rights(struct kvm_segment *var); | |
16f5b903 | 924 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx); |
b96fb439 PB |
925 | static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu); |
926 | static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked); | |
927 | static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12, | |
928 | u16 error_code); | |
75880a01 | 929 | |
6aa8b732 AK |
930 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
931 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
d462b819 NHE |
932 | /* |
933 | * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed | |
934 | * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. | |
935 | */ | |
936 | static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); | |
6aa8b732 | 937 | |
bf9f6ac8 FW |
938 | /* |
939 | * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we | |
940 | * can find which vCPU should be waken up. | |
941 | */ | |
942 | static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); | |
943 | static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); | |
944 | ||
23611332 RK |
945 | enum { |
946 | VMX_IO_BITMAP_A, | |
947 | VMX_IO_BITMAP_B, | |
948 | VMX_MSR_BITMAP_LEGACY, | |
949 | VMX_MSR_BITMAP_LONGMODE, | |
950 | VMX_MSR_BITMAP_LEGACY_X2APIC_APICV, | |
951 | VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV, | |
952 | VMX_MSR_BITMAP_LEGACY_X2APIC, | |
953 | VMX_MSR_BITMAP_LONGMODE_X2APIC, | |
954 | VMX_VMREAD_BITMAP, | |
955 | VMX_VMWRITE_BITMAP, | |
956 | VMX_BITMAP_NR | |
957 | }; | |
958 | ||
959 | static unsigned long *vmx_bitmap[VMX_BITMAP_NR]; | |
960 | ||
961 | #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A]) | |
962 | #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B]) | |
963 | #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY]) | |
964 | #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE]) | |
965 | #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV]) | |
966 | #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV]) | |
967 | #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC]) | |
968 | #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC]) | |
969 | #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP]) | |
970 | #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP]) | |
fdef3ad1 | 971 | |
110312c8 | 972 | static bool cpu_has_load_ia32_efer; |
8bf00a52 | 973 | static bool cpu_has_load_perf_global_ctrl; |
110312c8 | 974 | |
2384d2b3 SY |
975 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
976 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
977 | ||
1c3d14fe | 978 | static struct vmcs_config { |
6aa8b732 AK |
979 | int size; |
980 | int order; | |
9ac7e3e8 | 981 | u32 basic_cap; |
6aa8b732 | 982 | u32 revision_id; |
1c3d14fe YS |
983 | u32 pin_based_exec_ctrl; |
984 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 985 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
986 | u32 vmexit_ctrl; |
987 | u32 vmentry_ctrl; | |
988 | } vmcs_config; | |
6aa8b732 | 989 | |
efff9e53 | 990 | static struct vmx_capability { |
d56f546d SY |
991 | u32 ept; |
992 | u32 vpid; | |
993 | } vmx_capability; | |
994 | ||
6aa8b732 AK |
995 | #define VMX_SEGMENT_FIELD(seg) \ |
996 | [VCPU_SREG_##seg] = { \ | |
997 | .selector = GUEST_##seg##_SELECTOR, \ | |
998 | .base = GUEST_##seg##_BASE, \ | |
999 | .limit = GUEST_##seg##_LIMIT, \ | |
1000 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
1001 | } | |
1002 | ||
772e0318 | 1003 | static const struct kvm_vmx_segment_field { |
6aa8b732 AK |
1004 | unsigned selector; |
1005 | unsigned base; | |
1006 | unsigned limit; | |
1007 | unsigned ar_bytes; | |
1008 | } kvm_vmx_segment_fields[] = { | |
1009 | VMX_SEGMENT_FIELD(CS), | |
1010 | VMX_SEGMENT_FIELD(DS), | |
1011 | VMX_SEGMENT_FIELD(ES), | |
1012 | VMX_SEGMENT_FIELD(FS), | |
1013 | VMX_SEGMENT_FIELD(GS), | |
1014 | VMX_SEGMENT_FIELD(SS), | |
1015 | VMX_SEGMENT_FIELD(TR), | |
1016 | VMX_SEGMENT_FIELD(LDTR), | |
1017 | }; | |
1018 | ||
26bb0981 AK |
1019 | static u64 host_efer; |
1020 | ||
6de4f3ad AK |
1021 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu); |
1022 | ||
4d56c8a7 | 1023 | /* |
8c06585d | 1024 | * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it |
4d56c8a7 AK |
1025 | * away by decrementing the array size. |
1026 | */ | |
6aa8b732 | 1027 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 1028 | #ifdef CONFIG_X86_64 |
44ea2b17 | 1029 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, |
6aa8b732 | 1030 | #endif |
8c06585d | 1031 | MSR_EFER, MSR_TSC_AUX, MSR_STAR, |
6aa8b732 | 1032 | }; |
6aa8b732 | 1033 | |
5bb16016 | 1034 | static inline bool is_exception_n(u32 intr_info, u8 vector) |
6aa8b732 AK |
1035 | { |
1036 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
1037 | INTR_INFO_VALID_MASK)) == | |
5bb16016 JK |
1038 | (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK); |
1039 | } | |
1040 | ||
6f05485d JK |
1041 | static inline bool is_debug(u32 intr_info) |
1042 | { | |
1043 | return is_exception_n(intr_info, DB_VECTOR); | |
1044 | } | |
1045 | ||
1046 | static inline bool is_breakpoint(u32 intr_info) | |
1047 | { | |
1048 | return is_exception_n(intr_info, BP_VECTOR); | |
1049 | } | |
1050 | ||
5bb16016 JK |
1051 | static inline bool is_page_fault(u32 intr_info) |
1052 | { | |
1053 | return is_exception_n(intr_info, PF_VECTOR); | |
6aa8b732 AK |
1054 | } |
1055 | ||
31299944 | 1056 | static inline bool is_no_device(u32 intr_info) |
2ab455cc | 1057 | { |
5bb16016 | 1058 | return is_exception_n(intr_info, NM_VECTOR); |
2ab455cc AL |
1059 | } |
1060 | ||
31299944 | 1061 | static inline bool is_invalid_opcode(u32 intr_info) |
7aa81cc0 | 1062 | { |
5bb16016 | 1063 | return is_exception_n(intr_info, UD_VECTOR); |
7aa81cc0 AL |
1064 | } |
1065 | ||
31299944 | 1066 | static inline bool is_external_interrupt(u32 intr_info) |
6aa8b732 AK |
1067 | { |
1068 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
1069 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
1070 | } | |
1071 | ||
31299944 | 1072 | static inline bool is_machine_check(u32 intr_info) |
a0861c02 AK |
1073 | { |
1074 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
1075 | INTR_INFO_VALID_MASK)) == | |
1076 | (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK); | |
1077 | } | |
1078 | ||
31299944 | 1079 | static inline bool cpu_has_vmx_msr_bitmap(void) |
25c5f225 | 1080 | { |
04547156 | 1081 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; |
25c5f225 SY |
1082 | } |
1083 | ||
31299944 | 1084 | static inline bool cpu_has_vmx_tpr_shadow(void) |
6e5d865c | 1085 | { |
04547156 | 1086 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; |
6e5d865c YS |
1087 | } |
1088 | ||
35754c98 | 1089 | static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu) |
6e5d865c | 1090 | { |
35754c98 | 1091 | return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu); |
6e5d865c YS |
1092 | } |
1093 | ||
31299944 | 1094 | static inline bool cpu_has_secondary_exec_ctrls(void) |
f78e0e2e | 1095 | { |
04547156 SY |
1096 | return vmcs_config.cpu_based_exec_ctrl & |
1097 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
f78e0e2e SY |
1098 | } |
1099 | ||
774ead3a | 1100 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 1101 | { |
04547156 SY |
1102 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1103 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
1104 | } | |
1105 | ||
8d14695f YZ |
1106 | static inline bool cpu_has_vmx_virtualize_x2apic_mode(void) |
1107 | { | |
1108 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1109 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
1110 | } | |
1111 | ||
83d4c286 YZ |
1112 | static inline bool cpu_has_vmx_apic_register_virt(void) |
1113 | { | |
1114 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1115 | SECONDARY_EXEC_APIC_REGISTER_VIRT; | |
1116 | } | |
1117 | ||
c7c9c56c YZ |
1118 | static inline bool cpu_has_vmx_virtual_intr_delivery(void) |
1119 | { | |
1120 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1121 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY; | |
1122 | } | |
1123 | ||
64672c95 YJ |
1124 | /* |
1125 | * Comment's format: document - errata name - stepping - processor name. | |
1126 | * Refer from | |
1127 | * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp | |
1128 | */ | |
1129 | static u32 vmx_preemption_cpu_tfms[] = { | |
1130 | /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ | |
1131 | 0x000206E6, | |
1132 | /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ | |
1133 | /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ | |
1134 | /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
1135 | 0x00020652, | |
1136 | /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
1137 | 0x00020655, | |
1138 | /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ | |
1139 | /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ | |
1140 | /* | |
1141 | * 320767.pdf - AAP86 - B1 - | |
1142 | * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile | |
1143 | */ | |
1144 | 0x000106E5, | |
1145 | /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ | |
1146 | 0x000106A0, | |
1147 | /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ | |
1148 | 0x000106A1, | |
1149 | /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ | |
1150 | 0x000106A4, | |
1151 | /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ | |
1152 | /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ | |
1153 | /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ | |
1154 | 0x000106A5, | |
1155 | }; | |
1156 | ||
1157 | static inline bool cpu_has_broken_vmx_preemption_timer(void) | |
1158 | { | |
1159 | u32 eax = cpuid_eax(0x00000001), i; | |
1160 | ||
1161 | /* Clear the reserved bits */ | |
1162 | eax &= ~(0x3U << 14 | 0xfU << 28); | |
03f6a22a | 1163 | for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) |
64672c95 YJ |
1164 | if (eax == vmx_preemption_cpu_tfms[i]) |
1165 | return true; | |
1166 | ||
1167 | return false; | |
1168 | } | |
1169 | ||
1170 | static inline bool cpu_has_vmx_preemption_timer(void) | |
1171 | { | |
64672c95 YJ |
1172 | return vmcs_config.pin_based_exec_ctrl & |
1173 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
1174 | } | |
1175 | ||
01e439be YZ |
1176 | static inline bool cpu_has_vmx_posted_intr(void) |
1177 | { | |
d6a858d1 PB |
1178 | return IS_ENABLED(CONFIG_X86_LOCAL_APIC) && |
1179 | vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR; | |
01e439be YZ |
1180 | } |
1181 | ||
1182 | static inline bool cpu_has_vmx_apicv(void) | |
1183 | { | |
1184 | return cpu_has_vmx_apic_register_virt() && | |
1185 | cpu_has_vmx_virtual_intr_delivery() && | |
1186 | cpu_has_vmx_posted_intr(); | |
1187 | } | |
1188 | ||
04547156 SY |
1189 | static inline bool cpu_has_vmx_flexpriority(void) |
1190 | { | |
1191 | return cpu_has_vmx_tpr_shadow() && | |
1192 | cpu_has_vmx_virtualize_apic_accesses(); | |
f78e0e2e SY |
1193 | } |
1194 | ||
e799794e MT |
1195 | static inline bool cpu_has_vmx_ept_execute_only(void) |
1196 | { | |
31299944 | 1197 | return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT; |
e799794e MT |
1198 | } |
1199 | ||
e799794e MT |
1200 | static inline bool cpu_has_vmx_ept_2m_page(void) |
1201 | { | |
31299944 | 1202 | return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT; |
e799794e MT |
1203 | } |
1204 | ||
878403b7 SY |
1205 | static inline bool cpu_has_vmx_ept_1g_page(void) |
1206 | { | |
31299944 | 1207 | return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT; |
878403b7 SY |
1208 | } |
1209 | ||
4bc9b982 SY |
1210 | static inline bool cpu_has_vmx_ept_4levels(void) |
1211 | { | |
1212 | return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT; | |
1213 | } | |
1214 | ||
42aa53b4 DH |
1215 | static inline bool cpu_has_vmx_ept_mt_wb(void) |
1216 | { | |
1217 | return vmx_capability.ept & VMX_EPTP_WB_BIT; | |
1218 | } | |
1219 | ||
855feb67 YZ |
1220 | static inline bool cpu_has_vmx_ept_5levels(void) |
1221 | { | |
1222 | return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT; | |
1223 | } | |
1224 | ||
83c3a331 XH |
1225 | static inline bool cpu_has_vmx_ept_ad_bits(void) |
1226 | { | |
1227 | return vmx_capability.ept & VMX_EPT_AD_BIT; | |
1228 | } | |
1229 | ||
31299944 | 1230 | static inline bool cpu_has_vmx_invept_context(void) |
d56f546d | 1231 | { |
31299944 | 1232 | return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT; |
d56f546d SY |
1233 | } |
1234 | ||
31299944 | 1235 | static inline bool cpu_has_vmx_invept_global(void) |
d56f546d | 1236 | { |
31299944 | 1237 | return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT; |
d56f546d SY |
1238 | } |
1239 | ||
518c8aee GJ |
1240 | static inline bool cpu_has_vmx_invvpid_single(void) |
1241 | { | |
1242 | return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT; | |
1243 | } | |
1244 | ||
b9d762fa GJ |
1245 | static inline bool cpu_has_vmx_invvpid_global(void) |
1246 | { | |
1247 | return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; | |
1248 | } | |
1249 | ||
08d839c4 WL |
1250 | static inline bool cpu_has_vmx_invvpid(void) |
1251 | { | |
1252 | return vmx_capability.vpid & VMX_VPID_INVVPID_BIT; | |
1253 | } | |
1254 | ||
31299944 | 1255 | static inline bool cpu_has_vmx_ept(void) |
d56f546d | 1256 | { |
04547156 SY |
1257 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1258 | SECONDARY_EXEC_ENABLE_EPT; | |
d56f546d SY |
1259 | } |
1260 | ||
31299944 | 1261 | static inline bool cpu_has_vmx_unrestricted_guest(void) |
3a624e29 NK |
1262 | { |
1263 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1264 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
1265 | } | |
1266 | ||
31299944 | 1267 | static inline bool cpu_has_vmx_ple(void) |
4b8d54f9 ZE |
1268 | { |
1269 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1270 | SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
1271 | } | |
1272 | ||
9ac7e3e8 JD |
1273 | static inline bool cpu_has_vmx_basic_inout(void) |
1274 | { | |
1275 | return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT); | |
1276 | } | |
1277 | ||
35754c98 | 1278 | static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) |
f78e0e2e | 1279 | { |
35754c98 | 1280 | return flexpriority_enabled && lapic_in_kernel(vcpu); |
f78e0e2e SY |
1281 | } |
1282 | ||
31299944 | 1283 | static inline bool cpu_has_vmx_vpid(void) |
2384d2b3 | 1284 | { |
04547156 SY |
1285 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1286 | SECONDARY_EXEC_ENABLE_VPID; | |
2384d2b3 SY |
1287 | } |
1288 | ||
31299944 | 1289 | static inline bool cpu_has_vmx_rdtscp(void) |
4e47c7a6 SY |
1290 | { |
1291 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1292 | SECONDARY_EXEC_RDTSCP; | |
1293 | } | |
1294 | ||
ad756a16 MJ |
1295 | static inline bool cpu_has_vmx_invpcid(void) |
1296 | { | |
1297 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1298 | SECONDARY_EXEC_ENABLE_INVPCID; | |
1299 | } | |
1300 | ||
8a1b4392 PB |
1301 | static inline bool cpu_has_virtual_nmis(void) |
1302 | { | |
1303 | return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; | |
1304 | } | |
1305 | ||
f5f48ee1 SY |
1306 | static inline bool cpu_has_vmx_wbinvd_exit(void) |
1307 | { | |
1308 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1309 | SECONDARY_EXEC_WBINVD_EXITING; | |
1310 | } | |
1311 | ||
abc4fc58 AG |
1312 | static inline bool cpu_has_vmx_shadow_vmcs(void) |
1313 | { | |
1314 | u64 vmx_msr; | |
1315 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
1316 | /* check if the cpu supports writing r/o exit information fields */ | |
1317 | if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) | |
1318 | return false; | |
1319 | ||
1320 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1321 | SECONDARY_EXEC_SHADOW_VMCS; | |
1322 | } | |
1323 | ||
843e4330 KH |
1324 | static inline bool cpu_has_vmx_pml(void) |
1325 | { | |
1326 | return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML; | |
1327 | } | |
1328 | ||
64903d61 HZ |
1329 | static inline bool cpu_has_vmx_tsc_scaling(void) |
1330 | { | |
1331 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1332 | SECONDARY_EXEC_TSC_SCALING; | |
1333 | } | |
1334 | ||
2a499e49 BD |
1335 | static inline bool cpu_has_vmx_vmfunc(void) |
1336 | { | |
1337 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1338 | SECONDARY_EXEC_ENABLE_VMFUNC; | |
1339 | } | |
1340 | ||
04547156 SY |
1341 | static inline bool report_flexpriority(void) |
1342 | { | |
1343 | return flexpriority_enabled; | |
1344 | } | |
1345 | ||
c7c2c709 JM |
1346 | static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu) |
1347 | { | |
1348 | return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low); | |
1349 | } | |
1350 | ||
fe3ef05c NHE |
1351 | static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit) |
1352 | { | |
1353 | return vmcs12->cpu_based_vm_exec_control & bit; | |
1354 | } | |
1355 | ||
1356 | static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit) | |
1357 | { | |
1358 | return (vmcs12->cpu_based_vm_exec_control & | |
1359 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && | |
1360 | (vmcs12->secondary_vm_exec_control & bit); | |
1361 | } | |
1362 | ||
f4124500 JK |
1363 | static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12) |
1364 | { | |
1365 | return vmcs12->pin_based_vm_exec_control & | |
1366 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
1367 | } | |
1368 | ||
155a97a3 NHE |
1369 | static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12) |
1370 | { | |
1371 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT); | |
1372 | } | |
1373 | ||
81dc01f7 WL |
1374 | static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12) |
1375 | { | |
3db13480 | 1376 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES); |
81dc01f7 WL |
1377 | } |
1378 | ||
c5f983f6 BD |
1379 | static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12) |
1380 | { | |
1381 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML); | |
1382 | } | |
1383 | ||
f2b93280 WV |
1384 | static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12) |
1385 | { | |
1386 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); | |
1387 | } | |
1388 | ||
5c614b35 WL |
1389 | static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12) |
1390 | { | |
1391 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID); | |
1392 | } | |
1393 | ||
82f0dd4b WV |
1394 | static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12) |
1395 | { | |
1396 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT); | |
1397 | } | |
1398 | ||
608406e2 WV |
1399 | static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12) |
1400 | { | |
1401 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
1402 | } | |
1403 | ||
705699a1 WV |
1404 | static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12) |
1405 | { | |
1406 | return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR; | |
1407 | } | |
1408 | ||
27c42a1b BD |
1409 | static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12) |
1410 | { | |
1411 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC); | |
1412 | } | |
1413 | ||
41ab9372 BD |
1414 | static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12) |
1415 | { | |
1416 | return nested_cpu_has_vmfunc(vmcs12) && | |
1417 | (vmcs12->vm_function_control & | |
1418 | VMX_VMFUNC_EPTP_SWITCHING); | |
1419 | } | |
1420 | ||
ef85b673 | 1421 | static inline bool is_nmi(u32 intr_info) |
644d711a NHE |
1422 | { |
1423 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
ef85b673 | 1424 | == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK); |
644d711a NHE |
1425 | } |
1426 | ||
533558bc JK |
1427 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
1428 | u32 exit_intr_info, | |
1429 | unsigned long exit_qualification); | |
7c177938 NHE |
1430 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, |
1431 | struct vmcs12 *vmcs12, | |
1432 | u32 reason, unsigned long qualification); | |
1433 | ||
8b9cf98c | 1434 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
1435 | { |
1436 | int i; | |
1437 | ||
a2fa3e9f | 1438 | for (i = 0; i < vmx->nmsrs; ++i) |
26bb0981 | 1439 | if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) |
a75beee6 ED |
1440 | return i; |
1441 | return -1; | |
1442 | } | |
1443 | ||
2384d2b3 SY |
1444 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
1445 | { | |
1446 | struct { | |
1447 | u64 vpid : 16; | |
1448 | u64 rsvd : 48; | |
1449 | u64 gva; | |
1450 | } operand = { vpid, 0, gva }; | |
1451 | ||
4ecac3fd | 1452 | asm volatile (__ex(ASM_VMX_INVVPID) |
2384d2b3 SY |
1453 | /* CF==1 or ZF==1 --> rc = -1 */ |
1454 | "; ja 1f ; ud2 ; 1:" | |
1455 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
1456 | } | |
1457 | ||
1439442c SY |
1458 | static inline void __invept(int ext, u64 eptp, gpa_t gpa) |
1459 | { | |
1460 | struct { | |
1461 | u64 eptp, gpa; | |
1462 | } operand = {eptp, gpa}; | |
1463 | ||
4ecac3fd | 1464 | asm volatile (__ex(ASM_VMX_INVEPT) |
1439442c SY |
1465 | /* CF==1 or ZF==1 --> rc = -1 */ |
1466 | "; ja 1f ; ud2 ; 1:\n" | |
1467 | : : "a" (&operand), "c" (ext) : "cc", "memory"); | |
1468 | } | |
1469 | ||
26bb0981 | 1470 | static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
1471 | { |
1472 | int i; | |
1473 | ||
8b9cf98c | 1474 | i = __find_msr_index(vmx, msr); |
a75beee6 | 1475 | if (i >= 0) |
a2fa3e9f | 1476 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 1477 | return NULL; |
7725f0ba AK |
1478 | } |
1479 | ||
6aa8b732 AK |
1480 | static void vmcs_clear(struct vmcs *vmcs) |
1481 | { | |
1482 | u64 phys_addr = __pa(vmcs); | |
1483 | u8 error; | |
1484 | ||
4ecac3fd | 1485 | asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0" |
16d8f72f | 1486 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
6aa8b732 AK |
1487 | : "cc", "memory"); |
1488 | if (error) | |
1489 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
1490 | vmcs, phys_addr); | |
1491 | } | |
1492 | ||
d462b819 NHE |
1493 | static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) |
1494 | { | |
1495 | vmcs_clear(loaded_vmcs->vmcs); | |
355f4fb1 JM |
1496 | if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) |
1497 | vmcs_clear(loaded_vmcs->shadow_vmcs); | |
d462b819 NHE |
1498 | loaded_vmcs->cpu = -1; |
1499 | loaded_vmcs->launched = 0; | |
1500 | } | |
1501 | ||
7725b894 DX |
1502 | static void vmcs_load(struct vmcs *vmcs) |
1503 | { | |
1504 | u64 phys_addr = __pa(vmcs); | |
1505 | u8 error; | |
1506 | ||
1507 | asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0" | |
16d8f72f | 1508 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
7725b894 DX |
1509 | : "cc", "memory"); |
1510 | if (error) | |
2844d849 | 1511 | printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n", |
7725b894 DX |
1512 | vmcs, phys_addr); |
1513 | } | |
1514 | ||
2965faa5 | 1515 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
1516 | /* |
1517 | * This bitmap is used to indicate whether the vmclear | |
1518 | * operation is enabled on all cpus. All disabled by | |
1519 | * default. | |
1520 | */ | |
1521 | static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE; | |
1522 | ||
1523 | static inline void crash_enable_local_vmclear(int cpu) | |
1524 | { | |
1525 | cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1526 | } | |
1527 | ||
1528 | static inline void crash_disable_local_vmclear(int cpu) | |
1529 | { | |
1530 | cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1531 | } | |
1532 | ||
1533 | static inline int crash_local_vmclear_enabled(int cpu) | |
1534 | { | |
1535 | return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1536 | } | |
1537 | ||
1538 | static void crash_vmclear_local_loaded_vmcss(void) | |
1539 | { | |
1540 | int cpu = raw_smp_processor_id(); | |
1541 | struct loaded_vmcs *v; | |
1542 | ||
1543 | if (!crash_local_vmclear_enabled(cpu)) | |
1544 | return; | |
1545 | ||
1546 | list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), | |
1547 | loaded_vmcss_on_cpu_link) | |
1548 | vmcs_clear(v->vmcs); | |
1549 | } | |
1550 | #else | |
1551 | static inline void crash_enable_local_vmclear(int cpu) { } | |
1552 | static inline void crash_disable_local_vmclear(int cpu) { } | |
2965faa5 | 1553 | #endif /* CONFIG_KEXEC_CORE */ |
8f536b76 | 1554 | |
d462b819 | 1555 | static void __loaded_vmcs_clear(void *arg) |
6aa8b732 | 1556 | { |
d462b819 | 1557 | struct loaded_vmcs *loaded_vmcs = arg; |
d3b2c338 | 1558 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 1559 | |
d462b819 NHE |
1560 | if (loaded_vmcs->cpu != cpu) |
1561 | return; /* vcpu migration can race with cpu offline */ | |
1562 | if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) | |
6aa8b732 | 1563 | per_cpu(current_vmcs, cpu) = NULL; |
8f536b76 | 1564 | crash_disable_local_vmclear(cpu); |
d462b819 | 1565 | list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); |
5a560f8b XG |
1566 | |
1567 | /* | |
1568 | * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link | |
1569 | * is before setting loaded_vmcs->vcpu to -1 which is done in | |
1570 | * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist | |
1571 | * then adds the vmcs into percpu list before it is deleted. | |
1572 | */ | |
1573 | smp_wmb(); | |
1574 | ||
d462b819 | 1575 | loaded_vmcs_init(loaded_vmcs); |
8f536b76 | 1576 | crash_enable_local_vmclear(cpu); |
6aa8b732 AK |
1577 | } |
1578 | ||
d462b819 | 1579 | static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) |
8d0be2b3 | 1580 | { |
e6c7d321 XG |
1581 | int cpu = loaded_vmcs->cpu; |
1582 | ||
1583 | if (cpu != -1) | |
1584 | smp_call_function_single(cpu, | |
1585 | __loaded_vmcs_clear, loaded_vmcs, 1); | |
8d0be2b3 AK |
1586 | } |
1587 | ||
dd5f5341 | 1588 | static inline void vpid_sync_vcpu_single(int vpid) |
2384d2b3 | 1589 | { |
dd5f5341 | 1590 | if (vpid == 0) |
2384d2b3 SY |
1591 | return; |
1592 | ||
518c8aee | 1593 | if (cpu_has_vmx_invvpid_single()) |
dd5f5341 | 1594 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0); |
2384d2b3 SY |
1595 | } |
1596 | ||
b9d762fa GJ |
1597 | static inline void vpid_sync_vcpu_global(void) |
1598 | { | |
1599 | if (cpu_has_vmx_invvpid_global()) | |
1600 | __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0); | |
1601 | } | |
1602 | ||
dd5f5341 | 1603 | static inline void vpid_sync_context(int vpid) |
b9d762fa GJ |
1604 | { |
1605 | if (cpu_has_vmx_invvpid_single()) | |
dd5f5341 | 1606 | vpid_sync_vcpu_single(vpid); |
b9d762fa GJ |
1607 | else |
1608 | vpid_sync_vcpu_global(); | |
1609 | } | |
1610 | ||
1439442c SY |
1611 | static inline void ept_sync_global(void) |
1612 | { | |
f5f51586 | 1613 | __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); |
1439442c SY |
1614 | } |
1615 | ||
1616 | static inline void ept_sync_context(u64 eptp) | |
1617 | { | |
0e1252dc DH |
1618 | if (cpu_has_vmx_invept_context()) |
1619 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | |
1620 | else | |
1621 | ept_sync_global(); | |
1439442c SY |
1622 | } |
1623 | ||
8a86aea9 PB |
1624 | static __always_inline void vmcs_check16(unsigned long field) |
1625 | { | |
1626 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000, | |
1627 | "16-bit accessor invalid for 64-bit field"); | |
1628 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1629 | "16-bit accessor invalid for 64-bit high field"); | |
1630 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1631 | "16-bit accessor invalid for 32-bit high field"); | |
1632 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1633 | "16-bit accessor invalid for natural width field"); | |
1634 | } | |
1635 | ||
1636 | static __always_inline void vmcs_check32(unsigned long field) | |
1637 | { | |
1638 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1639 | "32-bit accessor invalid for 16-bit field"); | |
1640 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1641 | "32-bit accessor invalid for natural width field"); | |
1642 | } | |
1643 | ||
1644 | static __always_inline void vmcs_check64(unsigned long field) | |
1645 | { | |
1646 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1647 | "64-bit accessor invalid for 16-bit field"); | |
1648 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1649 | "64-bit accessor invalid for 64-bit high field"); | |
1650 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1651 | "64-bit accessor invalid for 32-bit field"); | |
1652 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1653 | "64-bit accessor invalid for natural width field"); | |
1654 | } | |
1655 | ||
1656 | static __always_inline void vmcs_checkl(unsigned long field) | |
1657 | { | |
1658 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1659 | "Natural width accessor invalid for 16-bit field"); | |
1660 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000, | |
1661 | "Natural width accessor invalid for 64-bit field"); | |
1662 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1663 | "Natural width accessor invalid for 64-bit high field"); | |
1664 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1665 | "Natural width accessor invalid for 32-bit field"); | |
1666 | } | |
1667 | ||
1668 | static __always_inline unsigned long __vmcs_readl(unsigned long field) | |
6aa8b732 | 1669 | { |
5e520e62 | 1670 | unsigned long value; |
6aa8b732 | 1671 | |
5e520e62 AK |
1672 | asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0") |
1673 | : "=a"(value) : "d"(field) : "cc"); | |
6aa8b732 AK |
1674 | return value; |
1675 | } | |
1676 | ||
96304217 | 1677 | static __always_inline u16 vmcs_read16(unsigned long field) |
6aa8b732 | 1678 | { |
8a86aea9 PB |
1679 | vmcs_check16(field); |
1680 | return __vmcs_readl(field); | |
6aa8b732 AK |
1681 | } |
1682 | ||
96304217 | 1683 | static __always_inline u32 vmcs_read32(unsigned long field) |
6aa8b732 | 1684 | { |
8a86aea9 PB |
1685 | vmcs_check32(field); |
1686 | return __vmcs_readl(field); | |
6aa8b732 AK |
1687 | } |
1688 | ||
96304217 | 1689 | static __always_inline u64 vmcs_read64(unsigned long field) |
6aa8b732 | 1690 | { |
8a86aea9 | 1691 | vmcs_check64(field); |
05b3e0c2 | 1692 | #ifdef CONFIG_X86_64 |
8a86aea9 | 1693 | return __vmcs_readl(field); |
6aa8b732 | 1694 | #else |
8a86aea9 | 1695 | return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32); |
6aa8b732 AK |
1696 | #endif |
1697 | } | |
1698 | ||
8a86aea9 PB |
1699 | static __always_inline unsigned long vmcs_readl(unsigned long field) |
1700 | { | |
1701 | vmcs_checkl(field); | |
1702 | return __vmcs_readl(field); | |
1703 | } | |
1704 | ||
e52de1b8 AK |
1705 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
1706 | { | |
1707 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
1708 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
1709 | dump_stack(); | |
1710 | } | |
1711 | ||
8a86aea9 | 1712 | static __always_inline void __vmcs_writel(unsigned long field, unsigned long value) |
6aa8b732 AK |
1713 | { |
1714 | u8 error; | |
1715 | ||
4ecac3fd | 1716 | asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0" |
d77c26fc | 1717 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
1718 | if (unlikely(error)) |
1719 | vmwrite_error(field, value); | |
6aa8b732 AK |
1720 | } |
1721 | ||
8a86aea9 | 1722 | static __always_inline void vmcs_write16(unsigned long field, u16 value) |
6aa8b732 | 1723 | { |
8a86aea9 PB |
1724 | vmcs_check16(field); |
1725 | __vmcs_writel(field, value); | |
6aa8b732 AK |
1726 | } |
1727 | ||
8a86aea9 | 1728 | static __always_inline void vmcs_write32(unsigned long field, u32 value) |
6aa8b732 | 1729 | { |
8a86aea9 PB |
1730 | vmcs_check32(field); |
1731 | __vmcs_writel(field, value); | |
6aa8b732 AK |
1732 | } |
1733 | ||
8a86aea9 | 1734 | static __always_inline void vmcs_write64(unsigned long field, u64 value) |
6aa8b732 | 1735 | { |
8a86aea9 PB |
1736 | vmcs_check64(field); |
1737 | __vmcs_writel(field, value); | |
7682f2d0 | 1738 | #ifndef CONFIG_X86_64 |
6aa8b732 | 1739 | asm volatile (""); |
8a86aea9 | 1740 | __vmcs_writel(field+1, value >> 32); |
6aa8b732 AK |
1741 | #endif |
1742 | } | |
1743 | ||
8a86aea9 | 1744 | static __always_inline void vmcs_writel(unsigned long field, unsigned long value) |
2ab455cc | 1745 | { |
8a86aea9 PB |
1746 | vmcs_checkl(field); |
1747 | __vmcs_writel(field, value); | |
2ab455cc AL |
1748 | } |
1749 | ||
8a86aea9 | 1750 | static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask) |
2ab455cc | 1751 | { |
8a86aea9 PB |
1752 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000, |
1753 | "vmcs_clear_bits does not support 64-bit fields"); | |
1754 | __vmcs_writel(field, __vmcs_readl(field) & ~mask); | |
2ab455cc AL |
1755 | } |
1756 | ||
8a86aea9 | 1757 | static __always_inline void vmcs_set_bits(unsigned long field, u32 mask) |
2ab455cc | 1758 | { |
8a86aea9 PB |
1759 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000, |
1760 | "vmcs_set_bits does not support 64-bit fields"); | |
1761 | __vmcs_writel(field, __vmcs_readl(field) | mask); | |
2ab455cc AL |
1762 | } |
1763 | ||
8391ce44 PB |
1764 | static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx) |
1765 | { | |
1766 | vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS); | |
1767 | } | |
1768 | ||
2961e876 GN |
1769 | static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val) |
1770 | { | |
1771 | vmcs_write32(VM_ENTRY_CONTROLS, val); | |
1772 | vmx->vm_entry_controls_shadow = val; | |
1773 | } | |
1774 | ||
1775 | static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val) | |
1776 | { | |
1777 | if (vmx->vm_entry_controls_shadow != val) | |
1778 | vm_entry_controls_init(vmx, val); | |
1779 | } | |
1780 | ||
1781 | static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx) | |
1782 | { | |
1783 | return vmx->vm_entry_controls_shadow; | |
1784 | } | |
1785 | ||
1786 | ||
1787 | static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
1788 | { | |
1789 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val); | |
1790 | } | |
1791 | ||
1792 | static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
1793 | { | |
1794 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val); | |
1795 | } | |
1796 | ||
8391ce44 PB |
1797 | static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx) |
1798 | { | |
1799 | vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS); | |
1800 | } | |
1801 | ||
2961e876 GN |
1802 | static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val) |
1803 | { | |
1804 | vmcs_write32(VM_EXIT_CONTROLS, val); | |
1805 | vmx->vm_exit_controls_shadow = val; | |
1806 | } | |
1807 | ||
1808 | static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val) | |
1809 | { | |
1810 | if (vmx->vm_exit_controls_shadow != val) | |
1811 | vm_exit_controls_init(vmx, val); | |
1812 | } | |
1813 | ||
1814 | static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx) | |
1815 | { | |
1816 | return vmx->vm_exit_controls_shadow; | |
1817 | } | |
1818 | ||
1819 | ||
1820 | static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
1821 | { | |
1822 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val); | |
1823 | } | |
1824 | ||
1825 | static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
1826 | { | |
1827 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val); | |
1828 | } | |
1829 | ||
2fb92db1 AK |
1830 | static void vmx_segment_cache_clear(struct vcpu_vmx *vmx) |
1831 | { | |
1832 | vmx->segment_cache.bitmask = 0; | |
1833 | } | |
1834 | ||
1835 | static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, | |
1836 | unsigned field) | |
1837 | { | |
1838 | bool ret; | |
1839 | u32 mask = 1 << (seg * SEG_FIELD_NR + field); | |
1840 | ||
1841 | if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) { | |
1842 | vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS); | |
1843 | vmx->segment_cache.bitmask = 0; | |
1844 | } | |
1845 | ret = vmx->segment_cache.bitmask & mask; | |
1846 | vmx->segment_cache.bitmask |= mask; | |
1847 | return ret; | |
1848 | } | |
1849 | ||
1850 | static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) | |
1851 | { | |
1852 | u16 *p = &vmx->segment_cache.seg[seg].selector; | |
1853 | ||
1854 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) | |
1855 | *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); | |
1856 | return *p; | |
1857 | } | |
1858 | ||
1859 | static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) | |
1860 | { | |
1861 | ulong *p = &vmx->segment_cache.seg[seg].base; | |
1862 | ||
1863 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) | |
1864 | *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); | |
1865 | return *p; | |
1866 | } | |
1867 | ||
1868 | static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) | |
1869 | { | |
1870 | u32 *p = &vmx->segment_cache.seg[seg].limit; | |
1871 | ||
1872 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) | |
1873 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); | |
1874 | return *p; | |
1875 | } | |
1876 | ||
1877 | static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) | |
1878 | { | |
1879 | u32 *p = &vmx->segment_cache.seg[seg].ar; | |
1880 | ||
1881 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) | |
1882 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); | |
1883 | return *p; | |
1884 | } | |
1885 | ||
abd3f2d6 AK |
1886 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
1887 | { | |
1888 | u32 eb; | |
1889 | ||
ac9b305c | 1890 | eb = (1u << PF_VECTOR) | (1u << MC_VECTOR) | |
bd7e5b08 | 1891 | (1u << DB_VECTOR) | (1u << AC_VECTOR); |
fd7373cc JK |
1892 | if ((vcpu->guest_debug & |
1893 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == | |
1894 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) | |
1895 | eb |= 1u << BP_VECTOR; | |
7ffd92c5 | 1896 | if (to_vmx(vcpu)->rmode.vm86_active) |
abd3f2d6 | 1897 | eb = ~0; |
089d034e | 1898 | if (enable_ept) |
1439442c | 1899 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ |
36cf24e0 NHE |
1900 | |
1901 | /* When we are running a nested L2 guest and L1 specified for it a | |
1902 | * certain exception bitmap, we must trap the same exceptions and pass | |
1903 | * them to L1. When running L2, we will only handle the exceptions | |
1904 | * specified above if L1 did not want them. | |
1905 | */ | |
1906 | if (is_guest_mode(vcpu)) | |
1907 | eb |= get_vmcs12(vcpu)->exception_bitmap; | |
ac9b305c LA |
1908 | else |
1909 | eb |= 1u << UD_VECTOR; | |
36cf24e0 | 1910 | |
abd3f2d6 AK |
1911 | vmcs_write32(EXCEPTION_BITMAP, eb); |
1912 | } | |
1913 | ||
2961e876 GN |
1914 | static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
1915 | unsigned long entry, unsigned long exit) | |
8bf00a52 | 1916 | { |
2961e876 GN |
1917 | vm_entry_controls_clearbit(vmx, entry); |
1918 | vm_exit_controls_clearbit(vmx, exit); | |
8bf00a52 GN |
1919 | } |
1920 | ||
61d2ef2c AK |
1921 | static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) |
1922 | { | |
1923 | unsigned i; | |
1924 | struct msr_autoload *m = &vmx->msr_autoload; | |
1925 | ||
8bf00a52 GN |
1926 | switch (msr) { |
1927 | case MSR_EFER: | |
1928 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
1929 | clear_atomic_switch_msr_special(vmx, |
1930 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
1931 | VM_EXIT_LOAD_IA32_EFER); |
1932 | return; | |
1933 | } | |
1934 | break; | |
1935 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
1936 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 1937 | clear_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
1938 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
1939 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
1940 | return; | |
1941 | } | |
1942 | break; | |
110312c8 AK |
1943 | } |
1944 | ||
61d2ef2c AK |
1945 | for (i = 0; i < m->nr; ++i) |
1946 | if (m->guest[i].index == msr) | |
1947 | break; | |
1948 | ||
1949 | if (i == m->nr) | |
1950 | return; | |
1951 | --m->nr; | |
1952 | m->guest[i] = m->guest[m->nr]; | |
1953 | m->host[i] = m->host[m->nr]; | |
1954 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
1955 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
1956 | } | |
1957 | ||
2961e876 GN |
1958 | static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
1959 | unsigned long entry, unsigned long exit, | |
1960 | unsigned long guest_val_vmcs, unsigned long host_val_vmcs, | |
1961 | u64 guest_val, u64 host_val) | |
8bf00a52 GN |
1962 | { |
1963 | vmcs_write64(guest_val_vmcs, guest_val); | |
1964 | vmcs_write64(host_val_vmcs, host_val); | |
2961e876 GN |
1965 | vm_entry_controls_setbit(vmx, entry); |
1966 | vm_exit_controls_setbit(vmx, exit); | |
8bf00a52 GN |
1967 | } |
1968 | ||
61d2ef2c AK |
1969 | static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, |
1970 | u64 guest_val, u64 host_val) | |
1971 | { | |
1972 | unsigned i; | |
1973 | struct msr_autoload *m = &vmx->msr_autoload; | |
1974 | ||
8bf00a52 GN |
1975 | switch (msr) { |
1976 | case MSR_EFER: | |
1977 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
1978 | add_atomic_switch_msr_special(vmx, |
1979 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
1980 | VM_EXIT_LOAD_IA32_EFER, |
1981 | GUEST_IA32_EFER, | |
1982 | HOST_IA32_EFER, | |
1983 | guest_val, host_val); | |
1984 | return; | |
1985 | } | |
1986 | break; | |
1987 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
1988 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 1989 | add_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
1990 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
1991 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, | |
1992 | GUEST_IA32_PERF_GLOBAL_CTRL, | |
1993 | HOST_IA32_PERF_GLOBAL_CTRL, | |
1994 | guest_val, host_val); | |
1995 | return; | |
1996 | } | |
1997 | break; | |
7099e2e1 RK |
1998 | case MSR_IA32_PEBS_ENABLE: |
1999 | /* PEBS needs a quiescent period after being disabled (to write | |
2000 | * a record). Disabling PEBS through VMX MSR swapping doesn't | |
2001 | * provide that period, so a CPU could write host's record into | |
2002 | * guest's memory. | |
2003 | */ | |
2004 | wrmsrl(MSR_IA32_PEBS_ENABLE, 0); | |
110312c8 AK |
2005 | } |
2006 | ||
61d2ef2c AK |
2007 | for (i = 0; i < m->nr; ++i) |
2008 | if (m->guest[i].index == msr) | |
2009 | break; | |
2010 | ||
e7fc6f93 | 2011 | if (i == NR_AUTOLOAD_MSRS) { |
60266204 | 2012 | printk_once(KERN_WARNING "Not enough msr switch entries. " |
e7fc6f93 GN |
2013 | "Can't add msr %x\n", msr); |
2014 | return; | |
2015 | } else if (i == m->nr) { | |
61d2ef2c AK |
2016 | ++m->nr; |
2017 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
2018 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
2019 | } | |
2020 | ||
2021 | m->guest[i].index = msr; | |
2022 | m->guest[i].value = guest_val; | |
2023 | m->host[i].index = msr; | |
2024 | m->host[i].value = host_val; | |
2025 | } | |
2026 | ||
92c0d900 | 2027 | static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) |
2cc51560 | 2028 | { |
844a5fe2 PB |
2029 | u64 guest_efer = vmx->vcpu.arch.efer; |
2030 | u64 ignore_bits = 0; | |
2031 | ||
2032 | if (!enable_ept) { | |
2033 | /* | |
2034 | * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing | |
2035 | * host CPUID is more efficient than testing guest CPUID | |
2036 | * or CR4. Host SMEP is anyway a requirement for guest SMEP. | |
2037 | */ | |
2038 | if (boot_cpu_has(X86_FEATURE_SMEP)) | |
2039 | guest_efer |= EFER_NX; | |
2040 | else if (!(guest_efer & EFER_NX)) | |
2041 | ignore_bits |= EFER_NX; | |
2042 | } | |
3a34a881 | 2043 | |
51c6cf66 | 2044 | /* |
844a5fe2 | 2045 | * LMA and LME handled by hardware; SCE meaningless outside long mode. |
51c6cf66 | 2046 | */ |
844a5fe2 | 2047 | ignore_bits |= EFER_SCE; |
51c6cf66 AK |
2048 | #ifdef CONFIG_X86_64 |
2049 | ignore_bits |= EFER_LMA | EFER_LME; | |
2050 | /* SCE is meaningful only in long mode on Intel */ | |
2051 | if (guest_efer & EFER_LMA) | |
2052 | ignore_bits &= ~(u64)EFER_SCE; | |
2053 | #endif | |
84ad33ef AK |
2054 | |
2055 | clear_atomic_switch_msr(vmx, MSR_EFER); | |
f6577a5f AL |
2056 | |
2057 | /* | |
2058 | * On EPT, we can't emulate NX, so we must switch EFER atomically. | |
2059 | * On CPUs that support "load IA32_EFER", always switch EFER | |
2060 | * atomically, since it's faster than switching it manually. | |
2061 | */ | |
2062 | if (cpu_has_load_ia32_efer || | |
2063 | (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { | |
84ad33ef AK |
2064 | if (!(guest_efer & EFER_LMA)) |
2065 | guest_efer &= ~EFER_LME; | |
54b98bff AL |
2066 | if (guest_efer != host_efer) |
2067 | add_atomic_switch_msr(vmx, MSR_EFER, | |
2068 | guest_efer, host_efer); | |
84ad33ef | 2069 | return false; |
844a5fe2 PB |
2070 | } else { |
2071 | guest_efer &= ~ignore_bits; | |
2072 | guest_efer |= host_efer & ignore_bits; | |
2073 | ||
2074 | vmx->guest_msrs[efer_offset].data = guest_efer; | |
2075 | vmx->guest_msrs[efer_offset].mask = ~ignore_bits; | |
84ad33ef | 2076 | |
844a5fe2 PB |
2077 | return true; |
2078 | } | |
51c6cf66 AK |
2079 | } |
2080 | ||
e28baead AL |
2081 | #ifdef CONFIG_X86_32 |
2082 | /* | |
2083 | * On 32-bit kernels, VM exits still load the FS and GS bases from the | |
2084 | * VMCS rather than the segment table. KVM uses this helper to figure | |
2085 | * out the current bases to poke them into the VMCS before entry. | |
2086 | */ | |
2d49ec72 GN |
2087 | static unsigned long segment_base(u16 selector) |
2088 | { | |
8c2e41f7 | 2089 | struct desc_struct *table; |
2d49ec72 GN |
2090 | unsigned long v; |
2091 | ||
8c2e41f7 | 2092 | if (!(selector & ~SEGMENT_RPL_MASK)) |
2d49ec72 GN |
2093 | return 0; |
2094 | ||
45fc8757 | 2095 | table = get_current_gdt_ro(); |
2d49ec72 | 2096 | |
8c2e41f7 | 2097 | if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) { |
2d49ec72 GN |
2098 | u16 ldt_selector = kvm_read_ldt(); |
2099 | ||
8c2e41f7 | 2100 | if (!(ldt_selector & ~SEGMENT_RPL_MASK)) |
2d49ec72 GN |
2101 | return 0; |
2102 | ||
8c2e41f7 | 2103 | table = (struct desc_struct *)segment_base(ldt_selector); |
2d49ec72 | 2104 | } |
8c2e41f7 | 2105 | v = get_desc_base(&table[selector >> 3]); |
2d49ec72 GN |
2106 | return v; |
2107 | } | |
e28baead | 2108 | #endif |
2d49ec72 | 2109 | |
04d2cc77 | 2110 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 2111 | { |
04d2cc77 | 2112 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 2113 | int i; |
04d2cc77 | 2114 | |
a2fa3e9f | 2115 | if (vmx->host_state.loaded) |
33ed6329 AK |
2116 | return; |
2117 | ||
a2fa3e9f | 2118 | vmx->host_state.loaded = 1; |
33ed6329 AK |
2119 | /* |
2120 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
2121 | * allow segment selectors with cpl > 0 or ti == 1. | |
2122 | */ | |
d6e88aec | 2123 | vmx->host_state.ldt_sel = kvm_read_ldt(); |
152d3f2f | 2124 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
9581d442 | 2125 | savesegment(fs, vmx->host_state.fs_sel); |
152d3f2f | 2126 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 2127 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
2128 | vmx->host_state.fs_reload_needed = 0; |
2129 | } else { | |
33ed6329 | 2130 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 2131 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 2132 | } |
9581d442 | 2133 | savesegment(gs, vmx->host_state.gs_sel); |
a2fa3e9f GH |
2134 | if (!(vmx->host_state.gs_sel & 7)) |
2135 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
2136 | else { |
2137 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 2138 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
2139 | } |
2140 | ||
b2da15ac AK |
2141 | #ifdef CONFIG_X86_64 |
2142 | savesegment(ds, vmx->host_state.ds_sel); | |
2143 | savesegment(es, vmx->host_state.es_sel); | |
2144 | #endif | |
2145 | ||
33ed6329 AK |
2146 | #ifdef CONFIG_X86_64 |
2147 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
2148 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
2149 | #else | |
a2fa3e9f GH |
2150 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
2151 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 2152 | #endif |
707c0874 AK |
2153 | |
2154 | #ifdef CONFIG_X86_64 | |
c8770e7b AK |
2155 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
2156 | if (is_long_mode(&vmx->vcpu)) | |
44ea2b17 | 2157 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); |
707c0874 | 2158 | #endif |
da8999d3 LJ |
2159 | if (boot_cpu_has(X86_FEATURE_MPX)) |
2160 | rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
26bb0981 AK |
2161 | for (i = 0; i < vmx->save_nmsrs; ++i) |
2162 | kvm_set_shared_msr(vmx->guest_msrs[i].index, | |
d5696725 AK |
2163 | vmx->guest_msrs[i].data, |
2164 | vmx->guest_msrs[i].mask); | |
33ed6329 AK |
2165 | } |
2166 | ||
a9b21b62 | 2167 | static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 2168 | { |
a2fa3e9f | 2169 | if (!vmx->host_state.loaded) |
33ed6329 AK |
2170 | return; |
2171 | ||
e1beb1d3 | 2172 | ++vmx->vcpu.stat.host_state_reload; |
a2fa3e9f | 2173 | vmx->host_state.loaded = 0; |
c8770e7b AK |
2174 | #ifdef CONFIG_X86_64 |
2175 | if (is_long_mode(&vmx->vcpu)) | |
2176 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); | |
2177 | #endif | |
152d3f2f | 2178 | if (vmx->host_state.gs_ldt_reload_needed) { |
d6e88aec | 2179 | kvm_load_ldt(vmx->host_state.ldt_sel); |
33ed6329 | 2180 | #ifdef CONFIG_X86_64 |
9581d442 | 2181 | load_gs_index(vmx->host_state.gs_sel); |
9581d442 AK |
2182 | #else |
2183 | loadsegment(gs, vmx->host_state.gs_sel); | |
33ed6329 | 2184 | #endif |
33ed6329 | 2185 | } |
0a77fe4c AK |
2186 | if (vmx->host_state.fs_reload_needed) |
2187 | loadsegment(fs, vmx->host_state.fs_sel); | |
b2da15ac AK |
2188 | #ifdef CONFIG_X86_64 |
2189 | if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) { | |
2190 | loadsegment(ds, vmx->host_state.ds_sel); | |
2191 | loadsegment(es, vmx->host_state.es_sel); | |
2192 | } | |
b2da15ac | 2193 | #endif |
b7ffc44d | 2194 | invalidate_tss_limit(); |
44ea2b17 | 2195 | #ifdef CONFIG_X86_64 |
c8770e7b | 2196 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
44ea2b17 | 2197 | #endif |
da8999d3 LJ |
2198 | if (vmx->host_state.msr_host_bndcfgs) |
2199 | wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
45fc8757 | 2200 | load_fixmap_gdt(raw_smp_processor_id()); |
33ed6329 AK |
2201 | } |
2202 | ||
a9b21b62 AK |
2203 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
2204 | { | |
2205 | preempt_disable(); | |
2206 | __vmx_load_host_state(vmx); | |
2207 | preempt_enable(); | |
2208 | } | |
2209 | ||
28b835d6 FW |
2210 | static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) |
2211 | { | |
2212 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
2213 | struct pi_desc old, new; | |
2214 | unsigned int dest; | |
2215 | ||
31afb2ea PB |
2216 | /* |
2217 | * In case of hot-plug or hot-unplug, we may have to undo | |
2218 | * vmx_vcpu_pi_put even if there is no assigned device. And we | |
2219 | * always keep PI.NDST up to date for simplicity: it makes the | |
2220 | * code easier, and CPU migration is not a fast path. | |
2221 | */ | |
2222 | if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu) | |
28b835d6 FW |
2223 | return; |
2224 | ||
31afb2ea PB |
2225 | /* |
2226 | * First handle the simple case where no cmpxchg is necessary; just | |
2227 | * allow posting non-urgent interrupts. | |
2228 | * | |
2229 | * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change | |
2230 | * PI.NDST: pi_post_block will do it for us and the wakeup_handler | |
2231 | * expects the VCPU to be on the blocked_vcpu_list that matches | |
2232 | * PI.NDST. | |
2233 | */ | |
2234 | if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || | |
2235 | vcpu->cpu == cpu) { | |
2236 | pi_clear_sn(pi_desc); | |
28b835d6 | 2237 | return; |
31afb2ea | 2238 | } |
28b835d6 | 2239 | |
31afb2ea | 2240 | /* The full case. */ |
28b835d6 FW |
2241 | do { |
2242 | old.control = new.control = pi_desc->control; | |
2243 | ||
31afb2ea | 2244 | dest = cpu_physical_id(cpu); |
28b835d6 | 2245 | |
31afb2ea PB |
2246 | if (x2apic_enabled()) |
2247 | new.ndst = dest; | |
2248 | else | |
2249 | new.ndst = (dest << 8) & 0xFF00; | |
28b835d6 | 2250 | |
28b835d6 | 2251 | new.sn = 0; |
c0a1666b PB |
2252 | } while (cmpxchg64(&pi_desc->control, old.control, |
2253 | new.control) != old.control); | |
28b835d6 | 2254 | } |
1be0e61c | 2255 | |
c95ba92a PF |
2256 | static void decache_tsc_multiplier(struct vcpu_vmx *vmx) |
2257 | { | |
2258 | vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio; | |
2259 | vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio); | |
2260 | } | |
2261 | ||
6aa8b732 AK |
2262 | /* |
2263 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
2264 | * vcpu mutex is already taken. | |
2265 | */ | |
15ad7146 | 2266 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 2267 | { |
a2fa3e9f | 2268 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
b80c76ec | 2269 | bool already_loaded = vmx->loaded_vmcs->cpu == cpu; |
6aa8b732 | 2270 | |
b80c76ec | 2271 | if (!already_loaded) { |
fe0e80be | 2272 | loaded_vmcs_clear(vmx->loaded_vmcs); |
92fe13be | 2273 | local_irq_disable(); |
8f536b76 | 2274 | crash_disable_local_vmclear(cpu); |
5a560f8b XG |
2275 | |
2276 | /* | |
2277 | * Read loaded_vmcs->cpu should be before fetching | |
2278 | * loaded_vmcs->loaded_vmcss_on_cpu_link. | |
2279 | * See the comments in __loaded_vmcs_clear(). | |
2280 | */ | |
2281 | smp_rmb(); | |
2282 | ||
d462b819 NHE |
2283 | list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, |
2284 | &per_cpu(loaded_vmcss_on_cpu, cpu)); | |
8f536b76 | 2285 | crash_enable_local_vmclear(cpu); |
92fe13be | 2286 | local_irq_enable(); |
b80c76ec JM |
2287 | } |
2288 | ||
2289 | if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { | |
2290 | per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; | |
2291 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
2292 | } | |
2293 | ||
2294 | if (!already_loaded) { | |
59c58ceb | 2295 | void *gdt = get_current_gdt_ro(); |
b80c76ec JM |
2296 | unsigned long sysenter_esp; |
2297 | ||
2298 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
92fe13be | 2299 | |
6aa8b732 AK |
2300 | /* |
2301 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
e0c23063 | 2302 | * processors. See 22.2.4. |
6aa8b732 | 2303 | */ |
e0c23063 | 2304 | vmcs_writel(HOST_TR_BASE, |
72f5e08d | 2305 | (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss); |
59c58ceb | 2306 | vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */ |
6aa8b732 | 2307 | |
b7ffc44d AL |
2308 | /* |
2309 | * VM exits change the host TR limit to 0x67 after a VM | |
2310 | * exit. This is okay, since 0x67 covers everything except | |
2311 | * the IO bitmap and have have code to handle the IO bitmap | |
2312 | * being lost after a VM exit. | |
2313 | */ | |
2314 | BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67); | |
2315 | ||
6aa8b732 AK |
2316 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); |
2317 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
ff2c3a18 | 2318 | |
d462b819 | 2319 | vmx->loaded_vmcs->cpu = cpu; |
6aa8b732 | 2320 | } |
28b835d6 | 2321 | |
2680d6da OH |
2322 | /* Setup TSC multiplier */ |
2323 | if (kvm_has_tsc_control && | |
c95ba92a PF |
2324 | vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) |
2325 | decache_tsc_multiplier(vmx); | |
2680d6da | 2326 | |
28b835d6 | 2327 | vmx_vcpu_pi_load(vcpu, cpu); |
1be0e61c | 2328 | vmx->host_pkru = read_pkru(); |
28b835d6 FW |
2329 | } |
2330 | ||
2331 | static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) | |
2332 | { | |
2333 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
2334 | ||
2335 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
2336 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
2337 | !kvm_vcpu_apicv_active(vcpu)) | |
28b835d6 FW |
2338 | return; |
2339 | ||
2340 | /* Set SN when the vCPU is preempted */ | |
2341 | if (vcpu->preempted) | |
2342 | pi_set_sn(pi_desc); | |
6aa8b732 AK |
2343 | } |
2344 | ||
2345 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
2346 | { | |
28b835d6 FW |
2347 | vmx_vcpu_pi_put(vcpu); |
2348 | ||
a9b21b62 | 2349 | __vmx_load_host_state(to_vmx(vcpu)); |
6aa8b732 AK |
2350 | } |
2351 | ||
f244deed WL |
2352 | static bool emulation_required(struct kvm_vcpu *vcpu) |
2353 | { | |
2354 | return emulate_invalid_guest_state && !guest_state_valid(vcpu); | |
2355 | } | |
2356 | ||
edcafe3c AK |
2357 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu); |
2358 | ||
fe3ef05c NHE |
2359 | /* |
2360 | * Return the cr0 value that a nested guest would read. This is a combination | |
2361 | * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by | |
2362 | * its hypervisor (cr0_read_shadow). | |
2363 | */ | |
2364 | static inline unsigned long nested_read_cr0(struct vmcs12 *fields) | |
2365 | { | |
2366 | return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) | | |
2367 | (fields->cr0_read_shadow & fields->cr0_guest_host_mask); | |
2368 | } | |
2369 | static inline unsigned long nested_read_cr4(struct vmcs12 *fields) | |
2370 | { | |
2371 | return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) | | |
2372 | (fields->cr4_read_shadow & fields->cr4_guest_host_mask); | |
2373 | } | |
2374 | ||
6aa8b732 AK |
2375 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
2376 | { | |
78ac8b47 | 2377 | unsigned long rflags, save_rflags; |
345dcaa8 | 2378 | |
6de12732 AK |
2379 | if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) { |
2380 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); | |
2381 | rflags = vmcs_readl(GUEST_RFLAGS); | |
2382 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
2383 | rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; | |
2384 | save_rflags = to_vmx(vcpu)->rmode.save_rflags; | |
2385 | rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
2386 | } | |
2387 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 | 2388 | } |
6de12732 | 2389 | return to_vmx(vcpu)->rflags; |
6aa8b732 AK |
2390 | } |
2391 | ||
2392 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
2393 | { | |
f244deed WL |
2394 | unsigned long old_rflags = vmx_get_rflags(vcpu); |
2395 | ||
6de12732 AK |
2396 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); |
2397 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 AK |
2398 | if (to_vmx(vcpu)->rmode.vm86_active) { |
2399 | to_vmx(vcpu)->rmode.save_rflags = rflags; | |
053de044 | 2400 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
78ac8b47 | 2401 | } |
6aa8b732 | 2402 | vmcs_writel(GUEST_RFLAGS, rflags); |
f244deed WL |
2403 | |
2404 | if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM) | |
2405 | to_vmx(vcpu)->emulation_required = emulation_required(vcpu); | |
6aa8b732 AK |
2406 | } |
2407 | ||
37ccdcbe | 2408 | static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) |
2809f5d2 GC |
2409 | { |
2410 | u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2411 | int ret = 0; | |
2412 | ||
2413 | if (interruptibility & GUEST_INTR_STATE_STI) | |
48005f64 | 2414 | ret |= KVM_X86_SHADOW_INT_STI; |
2809f5d2 | 2415 | if (interruptibility & GUEST_INTR_STATE_MOV_SS) |
48005f64 | 2416 | ret |= KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 | 2417 | |
37ccdcbe | 2418 | return ret; |
2809f5d2 GC |
2419 | } |
2420 | ||
2421 | static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
2422 | { | |
2423 | u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2424 | u32 interruptibility = interruptibility_old; | |
2425 | ||
2426 | interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); | |
2427 | ||
48005f64 | 2428 | if (mask & KVM_X86_SHADOW_INT_MOV_SS) |
2809f5d2 | 2429 | interruptibility |= GUEST_INTR_STATE_MOV_SS; |
48005f64 | 2430 | else if (mask & KVM_X86_SHADOW_INT_STI) |
2809f5d2 GC |
2431 | interruptibility |= GUEST_INTR_STATE_STI; |
2432 | ||
2433 | if ((interruptibility != interruptibility_old)) | |
2434 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); | |
2435 | } | |
2436 | ||
6aa8b732 AK |
2437 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
2438 | { | |
2439 | unsigned long rip; | |
6aa8b732 | 2440 | |
5fdbf976 | 2441 | rip = kvm_rip_read(vcpu); |
6aa8b732 | 2442 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
5fdbf976 | 2443 | kvm_rip_write(vcpu, rip); |
6aa8b732 | 2444 | |
2809f5d2 GC |
2445 | /* skipping an emulated instruction also counts */ |
2446 | vmx_set_interrupt_shadow(vcpu, 0); | |
6aa8b732 AK |
2447 | } |
2448 | ||
b96fb439 PB |
2449 | static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu, |
2450 | unsigned long exit_qual) | |
2451 | { | |
2452 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
2453 | unsigned int nr = vcpu->arch.exception.nr; | |
2454 | u32 intr_info = nr | INTR_INFO_VALID_MASK; | |
2455 | ||
2456 | if (vcpu->arch.exception.has_error_code) { | |
2457 | vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code; | |
2458 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; | |
2459 | } | |
2460 | ||
2461 | if (kvm_exception_is_soft(nr)) | |
2462 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; | |
2463 | else | |
2464 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
2465 | ||
2466 | if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) && | |
2467 | vmx_get_nmi_mask(vcpu)) | |
2468 | intr_info |= INTR_INFO_UNBLOCK_NMI; | |
2469 | ||
2470 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual); | |
2471 | } | |
2472 | ||
0b6ac343 NHE |
2473 | /* |
2474 | * KVM wants to inject page-faults which it got to the guest. This function | |
2475 | * checks whether in a nested guest, we need to inject them to L1 or L2. | |
0b6ac343 | 2476 | */ |
bfcf83b1 | 2477 | static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual) |
0b6ac343 NHE |
2478 | { |
2479 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
adfe20fb | 2480 | unsigned int nr = vcpu->arch.exception.nr; |
0b6ac343 | 2481 | |
b96fb439 PB |
2482 | if (nr == PF_VECTOR) { |
2483 | if (vcpu->arch.exception.nested_apf) { | |
bfcf83b1 | 2484 | *exit_qual = vcpu->arch.apf.nested_apf_token; |
b96fb439 PB |
2485 | return 1; |
2486 | } | |
2487 | /* | |
2488 | * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception. | |
2489 | * The fix is to add the ancillary datum (CR2 or DR6) to structs | |
2490 | * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 | |
2491 | * can be written only when inject_pending_event runs. This should be | |
2492 | * conditional on a new capability---if the capability is disabled, | |
2493 | * kvm_multiple_exception would write the ancillary information to | |
2494 | * CR2 or DR6, for backwards ABI-compatibility. | |
2495 | */ | |
2496 | if (nested_vmx_is_page_fault_vmexit(vmcs12, | |
2497 | vcpu->arch.exception.error_code)) { | |
bfcf83b1 | 2498 | *exit_qual = vcpu->arch.cr2; |
b96fb439 PB |
2499 | return 1; |
2500 | } | |
2501 | } else { | |
b96fb439 | 2502 | if (vmcs12->exception_bitmap & (1u << nr)) { |
bfcf83b1 WL |
2503 | if (nr == DB_VECTOR) |
2504 | *exit_qual = vcpu->arch.dr6; | |
2505 | else | |
2506 | *exit_qual = 0; | |
b96fb439 PB |
2507 | return 1; |
2508 | } | |
adfe20fb WL |
2509 | } |
2510 | ||
b96fb439 | 2511 | return 0; |
0b6ac343 NHE |
2512 | } |
2513 | ||
cfcd20e5 | 2514 | static void vmx_queue_exception(struct kvm_vcpu *vcpu) |
298101da | 2515 | { |
77ab6db0 | 2516 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
cfcd20e5 WL |
2517 | unsigned nr = vcpu->arch.exception.nr; |
2518 | bool has_error_code = vcpu->arch.exception.has_error_code; | |
cfcd20e5 | 2519 | u32 error_code = vcpu->arch.exception.error_code; |
8ab2d2e2 | 2520 | u32 intr_info = nr | INTR_INFO_VALID_MASK; |
77ab6db0 | 2521 | |
8ab2d2e2 | 2522 | if (has_error_code) { |
77ab6db0 | 2523 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); |
8ab2d2e2 JK |
2524 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; |
2525 | } | |
77ab6db0 | 2526 | |
7ffd92c5 | 2527 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
2528 | int inc_eip = 0; |
2529 | if (kvm_exception_is_soft(nr)) | |
2530 | inc_eip = vcpu->arch.event_exit_inst_len; | |
2531 | if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE) | |
a92601bb | 2532 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
77ab6db0 JK |
2533 | return; |
2534 | } | |
2535 | ||
66fd3f7f GN |
2536 | if (kvm_exception_is_soft(nr)) { |
2537 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
2538 | vmx->vcpu.arch.event_exit_inst_len); | |
8ab2d2e2 JK |
2539 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; |
2540 | } else | |
2541 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
2542 | ||
2543 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); | |
298101da AK |
2544 | } |
2545 | ||
4e47c7a6 SY |
2546 | static bool vmx_rdtscp_supported(void) |
2547 | { | |
2548 | return cpu_has_vmx_rdtscp(); | |
2549 | } | |
2550 | ||
ad756a16 MJ |
2551 | static bool vmx_invpcid_supported(void) |
2552 | { | |
2553 | return cpu_has_vmx_invpcid() && enable_ept; | |
2554 | } | |
2555 | ||
a75beee6 ED |
2556 | /* |
2557 | * Swap MSR entry in host/guest MSR entry array. | |
2558 | */ | |
8b9cf98c | 2559 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 2560 | { |
26bb0981 | 2561 | struct shared_msr_entry tmp; |
a2fa3e9f GH |
2562 | |
2563 | tmp = vmx->guest_msrs[to]; | |
2564 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
2565 | vmx->guest_msrs[from] = tmp; | |
a75beee6 ED |
2566 | } |
2567 | ||
8d14695f YZ |
2568 | static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu) |
2569 | { | |
2570 | unsigned long *msr_bitmap; | |
2571 | ||
670125bd | 2572 | if (is_guest_mode(vcpu)) |
d048c098 | 2573 | msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap; |
3ce424e4 RK |
2574 | else if (cpu_has_secondary_exec_ctrls() && |
2575 | (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) & | |
2576 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { | |
f6e90f9e WL |
2577 | if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) { |
2578 | if (is_long_mode(vcpu)) | |
c63e4563 | 2579 | msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv; |
f6e90f9e | 2580 | else |
c63e4563 | 2581 | msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv; |
f6e90f9e WL |
2582 | } else { |
2583 | if (is_long_mode(vcpu)) | |
c63e4563 | 2584 | msr_bitmap = vmx_msr_bitmap_longmode_x2apic; |
f6e90f9e | 2585 | else |
c63e4563 | 2586 | msr_bitmap = vmx_msr_bitmap_legacy_x2apic; |
f6e90f9e | 2587 | } |
8d14695f YZ |
2588 | } else { |
2589 | if (is_long_mode(vcpu)) | |
2590 | msr_bitmap = vmx_msr_bitmap_longmode; | |
2591 | else | |
2592 | msr_bitmap = vmx_msr_bitmap_legacy; | |
2593 | } | |
2594 | ||
2595 | vmcs_write64(MSR_BITMAP, __pa(msr_bitmap)); | |
2596 | } | |
2597 | ||
e38aea3e AK |
2598 | /* |
2599 | * Set up the vmcs to automatically save and restore system | |
2600 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
2601 | * mode, as fiddling with msrs is very expensive. | |
2602 | */ | |
8b9cf98c | 2603 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 2604 | { |
26bb0981 | 2605 | int save_nmsrs, index; |
e38aea3e | 2606 | |
a75beee6 ED |
2607 | save_nmsrs = 0; |
2608 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 2609 | if (is_long_mode(&vmx->vcpu)) { |
8b9cf98c | 2610 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 2611 | if (index >= 0) |
8b9cf98c RR |
2612 | move_msr_up(vmx, index, save_nmsrs++); |
2613 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 2614 | if (index >= 0) |
8b9cf98c RR |
2615 | move_msr_up(vmx, index, save_nmsrs++); |
2616 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 2617 | if (index >= 0) |
8b9cf98c | 2618 | move_msr_up(vmx, index, save_nmsrs++); |
4e47c7a6 | 2619 | index = __find_msr_index(vmx, MSR_TSC_AUX); |
d6321d49 | 2620 | if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP)) |
4e47c7a6 | 2621 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 | 2622 | /* |
8c06585d | 2623 | * MSR_STAR is only needed on long mode guests, and only |
a75beee6 ED |
2624 | * if efer.sce is enabled. |
2625 | */ | |
8c06585d | 2626 | index = __find_msr_index(vmx, MSR_STAR); |
f6801dff | 2627 | if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE)) |
8b9cf98c | 2628 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
2629 | } |
2630 | #endif | |
92c0d900 AK |
2631 | index = __find_msr_index(vmx, MSR_EFER); |
2632 | if (index >= 0 && update_transition_efer(vmx, index)) | |
26bb0981 | 2633 | move_msr_up(vmx, index, save_nmsrs++); |
e38aea3e | 2634 | |
26bb0981 | 2635 | vmx->save_nmsrs = save_nmsrs; |
5897297b | 2636 | |
8d14695f YZ |
2637 | if (cpu_has_vmx_msr_bitmap()) |
2638 | vmx_set_msr_bitmap(&vmx->vcpu); | |
e38aea3e AK |
2639 | } |
2640 | ||
6aa8b732 AK |
2641 | /* |
2642 | * reads and returns guest's timestamp counter "register" | |
be7b263e HZ |
2643 | * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset |
2644 | * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3 | |
6aa8b732 | 2645 | */ |
be7b263e | 2646 | static u64 guest_read_tsc(struct kvm_vcpu *vcpu) |
6aa8b732 AK |
2647 | { |
2648 | u64 host_tsc, tsc_offset; | |
2649 | ||
4ea1636b | 2650 | host_tsc = rdtsc(); |
6aa8b732 | 2651 | tsc_offset = vmcs_read64(TSC_OFFSET); |
be7b263e | 2652 | return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset; |
6aa8b732 AK |
2653 | } |
2654 | ||
2655 | /* | |
99e3e30a | 2656 | * writes 'offset' into guest's timestamp counter offset register |
6aa8b732 | 2657 | */ |
99e3e30a | 2658 | static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
6aa8b732 | 2659 | { |
27fc51b2 | 2660 | if (is_guest_mode(vcpu)) { |
7991825b | 2661 | /* |
27fc51b2 NHE |
2662 | * We're here if L1 chose not to trap WRMSR to TSC. According |
2663 | * to the spec, this should set L1's TSC; The offset that L1 | |
2664 | * set for L2 remains unchanged, and still needs to be added | |
2665 | * to the newly set TSC to get L2's TSC. | |
7991825b | 2666 | */ |
27fc51b2 | 2667 | struct vmcs12 *vmcs12; |
27fc51b2 NHE |
2668 | /* recalculate vmcs02.TSC_OFFSET: */ |
2669 | vmcs12 = get_vmcs12(vcpu); | |
2670 | vmcs_write64(TSC_OFFSET, offset + | |
2671 | (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ? | |
2672 | vmcs12->tsc_offset : 0)); | |
2673 | } else { | |
489223ed YY |
2674 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, |
2675 | vmcs_read64(TSC_OFFSET), offset); | |
27fc51b2 NHE |
2676 | vmcs_write64(TSC_OFFSET, offset); |
2677 | } | |
6aa8b732 AK |
2678 | } |
2679 | ||
801d3424 NHE |
2680 | /* |
2681 | * nested_vmx_allowed() checks whether a guest should be allowed to use VMX | |
2682 | * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for | |
2683 | * all guests if the "nested" module option is off, and can also be disabled | |
2684 | * for a single guest by disabling its VMX cpuid bit. | |
2685 | */ | |
2686 | static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu) | |
2687 | { | |
d6321d49 | 2688 | return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX); |
801d3424 NHE |
2689 | } |
2690 | ||
b87a51ae NHE |
2691 | /* |
2692 | * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be | |
2693 | * returned for the various VMX controls MSRs when nested VMX is enabled. | |
2694 | * The same values should also be used to verify that vmcs12 control fields are | |
2695 | * valid during nested entry from L1 to L2. | |
2696 | * Each of these control msrs has a low and high 32-bit half: A low bit is on | |
2697 | * if the corresponding bit in the (32-bit) control field *must* be on, and a | |
2698 | * bit in the high half is on if the corresponding bit in the control field | |
2699 | * may be on. See also vmx_control_verify(). | |
b87a51ae | 2700 | */ |
b9c237bb | 2701 | static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx) |
b87a51ae NHE |
2702 | { |
2703 | /* | |
2704 | * Note that as a general rule, the high half of the MSRs (bits in | |
2705 | * the control fields which may be 1) should be initialized by the | |
2706 | * intersection of the underlying hardware's MSR (i.e., features which | |
2707 | * can be supported) and the list of features we want to expose - | |
2708 | * because they are known to be properly supported in our code. | |
2709 | * Also, usually, the low half of the MSRs (bits which must be 1) can | |
2710 | * be set to 0, meaning that L1 may turn off any of these bits. The | |
2711 | * reason is that if one of these bits is necessary, it will appear | |
2712 | * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control | |
2713 | * fields of vmcs01 and vmcs02, will turn these bits off - and | |
7313c698 | 2714 | * nested_vmx_exit_reflected() will not pass related exits to L1. |
b87a51ae NHE |
2715 | * These rules have exceptions below. |
2716 | */ | |
2717 | ||
2718 | /* pin-based controls */ | |
eabeaacc | 2719 | rdmsr(MSR_IA32_VMX_PINBASED_CTLS, |
b9c237bb WV |
2720 | vmx->nested.nested_vmx_pinbased_ctls_low, |
2721 | vmx->nested.nested_vmx_pinbased_ctls_high); | |
2722 | vmx->nested.nested_vmx_pinbased_ctls_low |= | |
2723 | PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
2724 | vmx->nested.nested_vmx_pinbased_ctls_high &= | |
2725 | PIN_BASED_EXT_INTR_MASK | | |
2726 | PIN_BASED_NMI_EXITING | | |
2727 | PIN_BASED_VIRTUAL_NMIS; | |
2728 | vmx->nested.nested_vmx_pinbased_ctls_high |= | |
2729 | PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR | | |
0238ea91 | 2730 | PIN_BASED_VMX_PREEMPTION_TIMER; |
d62caabb | 2731 | if (kvm_vcpu_apicv_active(&vmx->vcpu)) |
705699a1 WV |
2732 | vmx->nested.nested_vmx_pinbased_ctls_high |= |
2733 | PIN_BASED_POSTED_INTR; | |
b87a51ae | 2734 | |
3dbcd8da | 2735 | /* exit controls */ |
c0dfee58 | 2736 | rdmsr(MSR_IA32_VMX_EXIT_CTLS, |
b9c237bb WV |
2737 | vmx->nested.nested_vmx_exit_ctls_low, |
2738 | vmx->nested.nested_vmx_exit_ctls_high); | |
2739 | vmx->nested.nested_vmx_exit_ctls_low = | |
2740 | VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; | |
e0ba1a6f | 2741 | |
b9c237bb | 2742 | vmx->nested.nested_vmx_exit_ctls_high &= |
b87a51ae | 2743 | #ifdef CONFIG_X86_64 |
c0dfee58 | 2744 | VM_EXIT_HOST_ADDR_SPACE_SIZE | |
b87a51ae | 2745 | #endif |
f4124500 | 2746 | VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT; |
b9c237bb WV |
2747 | vmx->nested.nested_vmx_exit_ctls_high |= |
2748 | VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR | | |
f4124500 | 2749 | VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER | |
e0ba1a6f BD |
2750 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT; |
2751 | ||
a87036ad | 2752 | if (kvm_mpx_supported()) |
b9c237bb | 2753 | vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; |
b87a51ae | 2754 | |
2996fca0 | 2755 | /* We support free control of debug control saving. */ |
0115f9cb | 2756 | vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS; |
2996fca0 | 2757 | |
b87a51ae NHE |
2758 | /* entry controls */ |
2759 | rdmsr(MSR_IA32_VMX_ENTRY_CTLS, | |
b9c237bb WV |
2760 | vmx->nested.nested_vmx_entry_ctls_low, |
2761 | vmx->nested.nested_vmx_entry_ctls_high); | |
2762 | vmx->nested.nested_vmx_entry_ctls_low = | |
2763 | VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; | |
2764 | vmx->nested.nested_vmx_entry_ctls_high &= | |
57435349 JK |
2765 | #ifdef CONFIG_X86_64 |
2766 | VM_ENTRY_IA32E_MODE | | |
2767 | #endif | |
2768 | VM_ENTRY_LOAD_IA32_PAT; | |
b9c237bb WV |
2769 | vmx->nested.nested_vmx_entry_ctls_high |= |
2770 | (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER); | |
a87036ad | 2771 | if (kvm_mpx_supported()) |
b9c237bb | 2772 | vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; |
57435349 | 2773 | |
2996fca0 | 2774 | /* We support free control of debug control loading. */ |
0115f9cb | 2775 | vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS; |
2996fca0 | 2776 | |
b87a51ae NHE |
2777 | /* cpu-based controls */ |
2778 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, | |
b9c237bb WV |
2779 | vmx->nested.nested_vmx_procbased_ctls_low, |
2780 | vmx->nested.nested_vmx_procbased_ctls_high); | |
2781 | vmx->nested.nested_vmx_procbased_ctls_low = | |
2782 | CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
2783 | vmx->nested.nested_vmx_procbased_ctls_high &= | |
a294c9bb JK |
2784 | CPU_BASED_VIRTUAL_INTR_PENDING | |
2785 | CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING | | |
b87a51ae NHE |
2786 | CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING | |
2787 | CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING | | |
2788 | CPU_BASED_CR3_STORE_EXITING | | |
2789 | #ifdef CONFIG_X86_64 | |
2790 | CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING | | |
2791 | #endif | |
2792 | CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING | | |
5f3d45e7 MD |
2793 | CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG | |
2794 | CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING | | |
2795 | CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING | | |
2796 | CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
b87a51ae NHE |
2797 | /* |
2798 | * We can allow some features even when not supported by the | |
2799 | * hardware. For example, L1 can specify an MSR bitmap - and we | |
2800 | * can use it to avoid exits to L1 - even when L0 runs L2 | |
2801 | * without MSR bitmaps. | |
2802 | */ | |
b9c237bb WV |
2803 | vmx->nested.nested_vmx_procbased_ctls_high |= |
2804 | CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR | | |
560b7ee1 | 2805 | CPU_BASED_USE_MSR_BITMAPS; |
b87a51ae | 2806 | |
3dcdf3ec | 2807 | /* We support free control of CR3 access interception. */ |
0115f9cb | 2808 | vmx->nested.nested_vmx_procbased_ctls_low &= |
3dcdf3ec JK |
2809 | ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING); |
2810 | ||
80154d77 PB |
2811 | /* |
2812 | * secondary cpu-based controls. Do not include those that | |
2813 | * depend on CPUID bits, they are added later by vmx_cpuid_update. | |
2814 | */ | |
b87a51ae | 2815 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, |
b9c237bb WV |
2816 | vmx->nested.nested_vmx_secondary_ctls_low, |
2817 | vmx->nested.nested_vmx_secondary_ctls_high); | |
2818 | vmx->nested.nested_vmx_secondary_ctls_low = 0; | |
2819 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
d6851fbe | 2820 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
1b07304c | 2821 | SECONDARY_EXEC_DESC | |
f2b93280 | 2822 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
82f0dd4b | 2823 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
608406e2 | 2824 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
3db13480 | 2825 | SECONDARY_EXEC_WBINVD_EXITING; |
c18911a2 | 2826 | |
afa61f75 NHE |
2827 | if (enable_ept) { |
2828 | /* nested EPT: emulate EPT also to L1 */ | |
b9c237bb | 2829 | vmx->nested.nested_vmx_secondary_ctls_high |= |
0790ec17 | 2830 | SECONDARY_EXEC_ENABLE_EPT; |
b9c237bb | 2831 | vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT | |
7db74265 | 2832 | VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT; |
02120c45 BD |
2833 | if (cpu_has_vmx_ept_execute_only()) |
2834 | vmx->nested.nested_vmx_ept_caps |= | |
2835 | VMX_EPT_EXECUTE_ONLY_BIT; | |
b9c237bb | 2836 | vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept; |
45e11817 | 2837 | vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT | |
7db74265 PB |
2838 | VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT | |
2839 | VMX_EPT_1GB_PAGE_BIT; | |
03efce6f BD |
2840 | if (enable_ept_ad_bits) { |
2841 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
2842 | SECONDARY_EXEC_ENABLE_PML; | |
7461fbc4 | 2843 | vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT; |
03efce6f | 2844 | } |
1c13bffd | 2845 | } |
afa61f75 | 2846 | |
27c42a1b BD |
2847 | if (cpu_has_vmx_vmfunc()) { |
2848 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
2849 | SECONDARY_EXEC_ENABLE_VMFUNC; | |
41ab9372 BD |
2850 | /* |
2851 | * Advertise EPTP switching unconditionally | |
2852 | * since we emulate it | |
2853 | */ | |
575b3a2c WL |
2854 | if (enable_ept) |
2855 | vmx->nested.nested_vmx_vmfunc_controls = | |
2856 | VMX_VMFUNC_EPTP_SWITCHING; | |
27c42a1b BD |
2857 | } |
2858 | ||
ef697a71 PB |
2859 | /* |
2860 | * Old versions of KVM use the single-context version without | |
2861 | * checking for support, so declare that it is supported even | |
2862 | * though it is treated as global context. The alternative is | |
2863 | * not failing the single-context invvpid, and it is worse. | |
2864 | */ | |
63cb6d5f WL |
2865 | if (enable_vpid) { |
2866 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
2867 | SECONDARY_EXEC_ENABLE_VPID; | |
089d7b6e | 2868 | vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT | |
bcdde302 | 2869 | VMX_VPID_EXTENT_SUPPORTED_MASK; |
1c13bffd | 2870 | } |
99b83ac8 | 2871 | |
0790ec17 RK |
2872 | if (enable_unrestricted_guest) |
2873 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
2874 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
2875 | ||
c18911a2 | 2876 | /* miscellaneous data */ |
b9c237bb WV |
2877 | rdmsr(MSR_IA32_VMX_MISC, |
2878 | vmx->nested.nested_vmx_misc_low, | |
2879 | vmx->nested.nested_vmx_misc_high); | |
2880 | vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA; | |
2881 | vmx->nested.nested_vmx_misc_low |= | |
2882 | VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE | | |
f4124500 | 2883 | VMX_MISC_ACTIVITY_HLT; |
b9c237bb | 2884 | vmx->nested.nested_vmx_misc_high = 0; |
62cc6b9d DM |
2885 | |
2886 | /* | |
2887 | * This MSR reports some information about VMX support. We | |
2888 | * should return information about the VMX we emulate for the | |
2889 | * guest, and the VMCS structure we give it - not about the | |
2890 | * VMX support of the underlying hardware. | |
2891 | */ | |
2892 | vmx->nested.nested_vmx_basic = | |
2893 | VMCS12_REVISION | | |
2894 | VMX_BASIC_TRUE_CTLS | | |
2895 | ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) | | |
2896 | (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT); | |
2897 | ||
2898 | if (cpu_has_vmx_basic_inout()) | |
2899 | vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT; | |
2900 | ||
2901 | /* | |
8322ebbb | 2902 | * These MSRs specify bits which the guest must keep fixed on |
62cc6b9d DM |
2903 | * while L1 is in VMXON mode (in L1's root mode, or running an L2). |
2904 | * We picked the standard core2 setting. | |
2905 | */ | |
2906 | #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE) | |
2907 | #define VMXON_CR4_ALWAYSON X86_CR4_VMXE | |
2908 | vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON; | |
62cc6b9d | 2909 | vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON; |
8322ebbb DM |
2910 | |
2911 | /* These MSRs specify bits which the guest must keep fixed off. */ | |
2912 | rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1); | |
2913 | rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1); | |
62cc6b9d DM |
2914 | |
2915 | /* highest index: VMX_PREEMPTION_TIMER_VALUE */ | |
2916 | vmx->nested.nested_vmx_vmcs_enum = 0x2e; | |
b87a51ae NHE |
2917 | } |
2918 | ||
3899152c DM |
2919 | /* |
2920 | * if fixed0[i] == 1: val[i] must be 1 | |
2921 | * if fixed1[i] == 0: val[i] must be 0 | |
2922 | */ | |
2923 | static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1) | |
2924 | { | |
2925 | return ((val & fixed1) | fixed0) == val; | |
b87a51ae NHE |
2926 | } |
2927 | ||
2928 | static inline bool vmx_control_verify(u32 control, u32 low, u32 high) | |
2929 | { | |
3899152c | 2930 | return fixed_bits_valid(control, low, high); |
b87a51ae NHE |
2931 | } |
2932 | ||
2933 | static inline u64 vmx_control_msr(u32 low, u32 high) | |
2934 | { | |
2935 | return low | ((u64)high << 32); | |
2936 | } | |
2937 | ||
62cc6b9d DM |
2938 | static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask) |
2939 | { | |
2940 | superset &= mask; | |
2941 | subset &= mask; | |
2942 | ||
2943 | return (superset | subset) == superset; | |
2944 | } | |
2945 | ||
2946 | static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data) | |
2947 | { | |
2948 | const u64 feature_and_reserved = | |
2949 | /* feature (except bit 48; see below) */ | |
2950 | BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) | | |
2951 | /* reserved */ | |
2952 | BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56); | |
2953 | u64 vmx_basic = vmx->nested.nested_vmx_basic; | |
2954 | ||
2955 | if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved)) | |
2956 | return -EINVAL; | |
2957 | ||
2958 | /* | |
2959 | * KVM does not emulate a version of VMX that constrains physical | |
2960 | * addresses of VMX structures (e.g. VMCS) to 32-bits. | |
2961 | */ | |
2962 | if (data & BIT_ULL(48)) | |
2963 | return -EINVAL; | |
2964 | ||
2965 | if (vmx_basic_vmcs_revision_id(vmx_basic) != | |
2966 | vmx_basic_vmcs_revision_id(data)) | |
2967 | return -EINVAL; | |
2968 | ||
2969 | if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data)) | |
2970 | return -EINVAL; | |
2971 | ||
2972 | vmx->nested.nested_vmx_basic = data; | |
2973 | return 0; | |
2974 | } | |
2975 | ||
2976 | static int | |
2977 | vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data) | |
2978 | { | |
2979 | u64 supported; | |
2980 | u32 *lowp, *highp; | |
2981 | ||
2982 | switch (msr_index) { | |
2983 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
2984 | lowp = &vmx->nested.nested_vmx_pinbased_ctls_low; | |
2985 | highp = &vmx->nested.nested_vmx_pinbased_ctls_high; | |
2986 | break; | |
2987 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
2988 | lowp = &vmx->nested.nested_vmx_procbased_ctls_low; | |
2989 | highp = &vmx->nested.nested_vmx_procbased_ctls_high; | |
2990 | break; | |
2991 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
2992 | lowp = &vmx->nested.nested_vmx_exit_ctls_low; | |
2993 | highp = &vmx->nested.nested_vmx_exit_ctls_high; | |
2994 | break; | |
2995 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
2996 | lowp = &vmx->nested.nested_vmx_entry_ctls_low; | |
2997 | highp = &vmx->nested.nested_vmx_entry_ctls_high; | |
2998 | break; | |
2999 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
3000 | lowp = &vmx->nested.nested_vmx_secondary_ctls_low; | |
3001 | highp = &vmx->nested.nested_vmx_secondary_ctls_high; | |
3002 | break; | |
3003 | default: | |
3004 | BUG(); | |
3005 | } | |
3006 | ||
3007 | supported = vmx_control_msr(*lowp, *highp); | |
3008 | ||
3009 | /* Check must-be-1 bits are still 1. */ | |
3010 | if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0))) | |
3011 | return -EINVAL; | |
3012 | ||
3013 | /* Check must-be-0 bits are still 0. */ | |
3014 | if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32))) | |
3015 | return -EINVAL; | |
3016 | ||
3017 | *lowp = data; | |
3018 | *highp = data >> 32; | |
3019 | return 0; | |
3020 | } | |
3021 | ||
3022 | static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data) | |
3023 | { | |
3024 | const u64 feature_and_reserved_bits = | |
3025 | /* feature */ | |
3026 | BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) | | |
3027 | BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) | | |
3028 | /* reserved */ | |
3029 | GENMASK_ULL(13, 9) | BIT_ULL(31); | |
3030 | u64 vmx_misc; | |
3031 | ||
3032 | vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low, | |
3033 | vmx->nested.nested_vmx_misc_high); | |
3034 | ||
3035 | if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits)) | |
3036 | return -EINVAL; | |
3037 | ||
3038 | if ((vmx->nested.nested_vmx_pinbased_ctls_high & | |
3039 | PIN_BASED_VMX_PREEMPTION_TIMER) && | |
3040 | vmx_misc_preemption_timer_rate(data) != | |
3041 | vmx_misc_preemption_timer_rate(vmx_misc)) | |
3042 | return -EINVAL; | |
3043 | ||
3044 | if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc)) | |
3045 | return -EINVAL; | |
3046 | ||
3047 | if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc)) | |
3048 | return -EINVAL; | |
3049 | ||
3050 | if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc)) | |
3051 | return -EINVAL; | |
3052 | ||
3053 | vmx->nested.nested_vmx_misc_low = data; | |
3054 | vmx->nested.nested_vmx_misc_high = data >> 32; | |
3055 | return 0; | |
3056 | } | |
3057 | ||
3058 | static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data) | |
3059 | { | |
3060 | u64 vmx_ept_vpid_cap; | |
3061 | ||
3062 | vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps, | |
3063 | vmx->nested.nested_vmx_vpid_caps); | |
3064 | ||
3065 | /* Every bit is either reserved or a feature bit. */ | |
3066 | if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL)) | |
3067 | return -EINVAL; | |
3068 | ||
3069 | vmx->nested.nested_vmx_ept_caps = data; | |
3070 | vmx->nested.nested_vmx_vpid_caps = data >> 32; | |
3071 | return 0; | |
3072 | } | |
3073 | ||
3074 | static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data) | |
3075 | { | |
3076 | u64 *msr; | |
3077 | ||
3078 | switch (msr_index) { | |
3079 | case MSR_IA32_VMX_CR0_FIXED0: | |
3080 | msr = &vmx->nested.nested_vmx_cr0_fixed0; | |
3081 | break; | |
3082 | case MSR_IA32_VMX_CR4_FIXED0: | |
3083 | msr = &vmx->nested.nested_vmx_cr4_fixed0; | |
3084 | break; | |
3085 | default: | |
3086 | BUG(); | |
3087 | } | |
3088 | ||
3089 | /* | |
3090 | * 1 bits (which indicates bits which "must-be-1" during VMX operation) | |
3091 | * must be 1 in the restored value. | |
3092 | */ | |
3093 | if (!is_bitwise_subset(data, *msr, -1ULL)) | |
3094 | return -EINVAL; | |
3095 | ||
3096 | *msr = data; | |
3097 | return 0; | |
3098 | } | |
3099 | ||
3100 | /* | |
3101 | * Called when userspace is restoring VMX MSRs. | |
3102 | * | |
3103 | * Returns 0 on success, non-0 otherwise. | |
3104 | */ | |
3105 | static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
b87a51ae | 3106 | { |
b9c237bb WV |
3107 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3108 | ||
b87a51ae | 3109 | switch (msr_index) { |
b87a51ae | 3110 | case MSR_IA32_VMX_BASIC: |
62cc6b9d DM |
3111 | return vmx_restore_vmx_basic(vmx, data); |
3112 | case MSR_IA32_VMX_PINBASED_CTLS: | |
3113 | case MSR_IA32_VMX_PROCBASED_CTLS: | |
3114 | case MSR_IA32_VMX_EXIT_CTLS: | |
3115 | case MSR_IA32_VMX_ENTRY_CTLS: | |
b87a51ae | 3116 | /* |
62cc6b9d DM |
3117 | * The "non-true" VMX capability MSRs are generated from the |
3118 | * "true" MSRs, so we do not support restoring them directly. | |
3119 | * | |
3120 | * If userspace wants to emulate VMX_BASIC[55]=0, userspace | |
3121 | * should restore the "true" MSRs with the must-be-1 bits | |
3122 | * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND | |
3123 | * DEFAULT SETTINGS". | |
b87a51ae | 3124 | */ |
62cc6b9d DM |
3125 | return -EINVAL; |
3126 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
3127 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
3128 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
3129 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
3130 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
3131 | return vmx_restore_control_msr(vmx, msr_index, data); | |
3132 | case MSR_IA32_VMX_MISC: | |
3133 | return vmx_restore_vmx_misc(vmx, data); | |
3134 | case MSR_IA32_VMX_CR0_FIXED0: | |
3135 | case MSR_IA32_VMX_CR4_FIXED0: | |
3136 | return vmx_restore_fixed0_msr(vmx, msr_index, data); | |
3137 | case MSR_IA32_VMX_CR0_FIXED1: | |
3138 | case MSR_IA32_VMX_CR4_FIXED1: | |
3139 | /* | |
3140 | * These MSRs are generated based on the vCPU's CPUID, so we | |
3141 | * do not support restoring them directly. | |
3142 | */ | |
3143 | return -EINVAL; | |
3144 | case MSR_IA32_VMX_EPT_VPID_CAP: | |
3145 | return vmx_restore_vmx_ept_vpid_cap(vmx, data); | |
3146 | case MSR_IA32_VMX_VMCS_ENUM: | |
3147 | vmx->nested.nested_vmx_vmcs_enum = data; | |
3148 | return 0; | |
3149 | default: | |
b87a51ae | 3150 | /* |
62cc6b9d | 3151 | * The rest of the VMX capability MSRs do not support restore. |
b87a51ae | 3152 | */ |
62cc6b9d DM |
3153 | return -EINVAL; |
3154 | } | |
3155 | } | |
3156 | ||
3157 | /* Returns 0 on success, non-0 otherwise. */ | |
3158 | static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
3159 | { | |
3160 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
3161 | ||
3162 | switch (msr_index) { | |
3163 | case MSR_IA32_VMX_BASIC: | |
3164 | *pdata = vmx->nested.nested_vmx_basic; | |
b87a51ae NHE |
3165 | break; |
3166 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
3167 | case MSR_IA32_VMX_PINBASED_CTLS: | |
b9c237bb WV |
3168 | *pdata = vmx_control_msr( |
3169 | vmx->nested.nested_vmx_pinbased_ctls_low, | |
3170 | vmx->nested.nested_vmx_pinbased_ctls_high); | |
0115f9cb DM |
3171 | if (msr_index == MSR_IA32_VMX_PINBASED_CTLS) |
3172 | *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3173 | break; |
3174 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
3175 | case MSR_IA32_VMX_PROCBASED_CTLS: | |
b9c237bb WV |
3176 | *pdata = vmx_control_msr( |
3177 | vmx->nested.nested_vmx_procbased_ctls_low, | |
3178 | vmx->nested.nested_vmx_procbased_ctls_high); | |
0115f9cb DM |
3179 | if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS) |
3180 | *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3181 | break; |
3182 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
3183 | case MSR_IA32_VMX_EXIT_CTLS: | |
b9c237bb WV |
3184 | *pdata = vmx_control_msr( |
3185 | vmx->nested.nested_vmx_exit_ctls_low, | |
3186 | vmx->nested.nested_vmx_exit_ctls_high); | |
0115f9cb DM |
3187 | if (msr_index == MSR_IA32_VMX_EXIT_CTLS) |
3188 | *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3189 | break; |
3190 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
3191 | case MSR_IA32_VMX_ENTRY_CTLS: | |
b9c237bb WV |
3192 | *pdata = vmx_control_msr( |
3193 | vmx->nested.nested_vmx_entry_ctls_low, | |
3194 | vmx->nested.nested_vmx_entry_ctls_high); | |
0115f9cb DM |
3195 | if (msr_index == MSR_IA32_VMX_ENTRY_CTLS) |
3196 | *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3197 | break; |
3198 | case MSR_IA32_VMX_MISC: | |
b9c237bb WV |
3199 | *pdata = vmx_control_msr( |
3200 | vmx->nested.nested_vmx_misc_low, | |
3201 | vmx->nested.nested_vmx_misc_high); | |
b87a51ae | 3202 | break; |
b87a51ae | 3203 | case MSR_IA32_VMX_CR0_FIXED0: |
62cc6b9d | 3204 | *pdata = vmx->nested.nested_vmx_cr0_fixed0; |
b87a51ae NHE |
3205 | break; |
3206 | case MSR_IA32_VMX_CR0_FIXED1: | |
62cc6b9d | 3207 | *pdata = vmx->nested.nested_vmx_cr0_fixed1; |
b87a51ae NHE |
3208 | break; |
3209 | case MSR_IA32_VMX_CR4_FIXED0: | |
62cc6b9d | 3210 | *pdata = vmx->nested.nested_vmx_cr4_fixed0; |
b87a51ae NHE |
3211 | break; |
3212 | case MSR_IA32_VMX_CR4_FIXED1: | |
62cc6b9d | 3213 | *pdata = vmx->nested.nested_vmx_cr4_fixed1; |
b87a51ae NHE |
3214 | break; |
3215 | case MSR_IA32_VMX_VMCS_ENUM: | |
62cc6b9d | 3216 | *pdata = vmx->nested.nested_vmx_vmcs_enum; |
b87a51ae NHE |
3217 | break; |
3218 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
b9c237bb WV |
3219 | *pdata = vmx_control_msr( |
3220 | vmx->nested.nested_vmx_secondary_ctls_low, | |
3221 | vmx->nested.nested_vmx_secondary_ctls_high); | |
b87a51ae NHE |
3222 | break; |
3223 | case MSR_IA32_VMX_EPT_VPID_CAP: | |
089d7b6e WL |
3224 | *pdata = vmx->nested.nested_vmx_ept_caps | |
3225 | ((u64)vmx->nested.nested_vmx_vpid_caps << 32); | |
b87a51ae | 3226 | break; |
27c42a1b BD |
3227 | case MSR_IA32_VMX_VMFUNC: |
3228 | *pdata = vmx->nested.nested_vmx_vmfunc_controls; | |
3229 | break; | |
b87a51ae | 3230 | default: |
b87a51ae | 3231 | return 1; |
b3897a49 NHE |
3232 | } |
3233 | ||
b87a51ae NHE |
3234 | return 0; |
3235 | } | |
3236 | ||
37e4c997 HZ |
3237 | static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, |
3238 | uint64_t val) | |
3239 | { | |
3240 | uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; | |
3241 | ||
3242 | return !(val & ~valid_bits); | |
3243 | } | |
3244 | ||
6aa8b732 AK |
3245 | /* |
3246 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
3247 | * Returns 0 on success, non-0 otherwise. | |
3248 | * Assumes vcpu_load() was already called. | |
3249 | */ | |
609e36d3 | 3250 | static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3251 | { |
26bb0981 | 3252 | struct shared_msr_entry *msr; |
6aa8b732 | 3253 | |
609e36d3 | 3254 | switch (msr_info->index) { |
05b3e0c2 | 3255 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3256 | case MSR_FS_BASE: |
609e36d3 | 3257 | msr_info->data = vmcs_readl(GUEST_FS_BASE); |
6aa8b732 AK |
3258 | break; |
3259 | case MSR_GS_BASE: | |
609e36d3 | 3260 | msr_info->data = vmcs_readl(GUEST_GS_BASE); |
6aa8b732 | 3261 | break; |
44ea2b17 AK |
3262 | case MSR_KERNEL_GS_BASE: |
3263 | vmx_load_host_state(to_vmx(vcpu)); | |
609e36d3 | 3264 | msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base; |
44ea2b17 | 3265 | break; |
26bb0981 | 3266 | #endif |
6aa8b732 | 3267 | case MSR_EFER: |
609e36d3 | 3268 | return kvm_get_msr_common(vcpu, msr_info); |
af24a4e4 | 3269 | case MSR_IA32_TSC: |
be7b263e | 3270 | msr_info->data = guest_read_tsc(vcpu); |
6aa8b732 AK |
3271 | break; |
3272 | case MSR_IA32_SYSENTER_CS: | |
609e36d3 | 3273 | msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); |
6aa8b732 AK |
3274 | break; |
3275 | case MSR_IA32_SYSENTER_EIP: | |
609e36d3 | 3276 | msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
3277 | break; |
3278 | case MSR_IA32_SYSENTER_ESP: | |
609e36d3 | 3279 | msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 3280 | break; |
0dd376e7 | 3281 | case MSR_IA32_BNDCFGS: |
691bd434 | 3282 | if (!kvm_mpx_supported() || |
d6321d49 RK |
3283 | (!msr_info->host_initiated && |
3284 | !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) | |
93c4adc7 | 3285 | return 1; |
609e36d3 | 3286 | msr_info->data = vmcs_read64(GUEST_BNDCFGS); |
0dd376e7 | 3287 | break; |
c45dcc71 AR |
3288 | case MSR_IA32_MCG_EXT_CTL: |
3289 | if (!msr_info->host_initiated && | |
3290 | !(to_vmx(vcpu)->msr_ia32_feature_control & | |
3291 | FEATURE_CONTROL_LMCE)) | |
cae50139 | 3292 | return 1; |
c45dcc71 AR |
3293 | msr_info->data = vcpu->arch.mcg_ext_ctl; |
3294 | break; | |
cae50139 | 3295 | case MSR_IA32_FEATURE_CONTROL: |
3b84080b | 3296 | msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control; |
cae50139 JK |
3297 | break; |
3298 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
3299 | if (!nested_vmx_allowed(vcpu)) | |
3300 | return 1; | |
609e36d3 | 3301 | return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data); |
20300099 WL |
3302 | case MSR_IA32_XSS: |
3303 | if (!vmx_xsaves_supported()) | |
3304 | return 1; | |
609e36d3 | 3305 | msr_info->data = vcpu->arch.ia32_xss; |
20300099 | 3306 | break; |
4e47c7a6 | 3307 | case MSR_TSC_AUX: |
d6321d49 RK |
3308 | if (!msr_info->host_initiated && |
3309 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) | |
4e47c7a6 SY |
3310 | return 1; |
3311 | /* Otherwise falls through */ | |
6aa8b732 | 3312 | default: |
609e36d3 | 3313 | msr = find_msr_entry(to_vmx(vcpu), msr_info->index); |
3bab1f5d | 3314 | if (msr) { |
609e36d3 | 3315 | msr_info->data = msr->data; |
3bab1f5d | 3316 | break; |
6aa8b732 | 3317 | } |
609e36d3 | 3318 | return kvm_get_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3319 | } |
3320 | ||
6aa8b732 AK |
3321 | return 0; |
3322 | } | |
3323 | ||
cae50139 JK |
3324 | static void vmx_leave_nested(struct kvm_vcpu *vcpu); |
3325 | ||
6aa8b732 AK |
3326 | /* |
3327 | * Writes msr value into into the appropriate "register". | |
3328 | * Returns 0 on success, non-0 otherwise. | |
3329 | * Assumes vcpu_load() was already called. | |
3330 | */ | |
8fe8ab46 | 3331 | static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3332 | { |
a2fa3e9f | 3333 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 3334 | struct shared_msr_entry *msr; |
2cc51560 | 3335 | int ret = 0; |
8fe8ab46 WA |
3336 | u32 msr_index = msr_info->index; |
3337 | u64 data = msr_info->data; | |
2cc51560 | 3338 | |
6aa8b732 | 3339 | switch (msr_index) { |
3bab1f5d | 3340 | case MSR_EFER: |
8fe8ab46 | 3341 | ret = kvm_set_msr_common(vcpu, msr_info); |
2cc51560 | 3342 | break; |
16175a79 | 3343 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3344 | case MSR_FS_BASE: |
2fb92db1 | 3345 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
3346 | vmcs_writel(GUEST_FS_BASE, data); |
3347 | break; | |
3348 | case MSR_GS_BASE: | |
2fb92db1 | 3349 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
3350 | vmcs_writel(GUEST_GS_BASE, data); |
3351 | break; | |
44ea2b17 AK |
3352 | case MSR_KERNEL_GS_BASE: |
3353 | vmx_load_host_state(vmx); | |
3354 | vmx->msr_guest_kernel_gs_base = data; | |
3355 | break; | |
6aa8b732 AK |
3356 | #endif |
3357 | case MSR_IA32_SYSENTER_CS: | |
3358 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
3359 | break; | |
3360 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 3361 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
3362 | break; |
3363 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 3364 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 3365 | break; |
0dd376e7 | 3366 | case MSR_IA32_BNDCFGS: |
691bd434 | 3367 | if (!kvm_mpx_supported() || |
d6321d49 RK |
3368 | (!msr_info->host_initiated && |
3369 | !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) | |
93c4adc7 | 3370 | return 1; |
fd8cb433 | 3371 | if (is_noncanonical_address(data & PAGE_MASK, vcpu) || |
4531662d | 3372 | (data & MSR_IA32_BNDCFGS_RSVD)) |
93c4adc7 | 3373 | return 1; |
0dd376e7 LJ |
3374 | vmcs_write64(GUEST_BNDCFGS, data); |
3375 | break; | |
af24a4e4 | 3376 | case MSR_IA32_TSC: |
8fe8ab46 | 3377 | kvm_write_tsc(vcpu, msr_info); |
6aa8b732 | 3378 | break; |
468d472f SY |
3379 | case MSR_IA32_CR_PAT: |
3380 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
4566654b NA |
3381 | if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data)) |
3382 | return 1; | |
468d472f SY |
3383 | vmcs_write64(GUEST_IA32_PAT, data); |
3384 | vcpu->arch.pat = data; | |
3385 | break; | |
3386 | } | |
8fe8ab46 | 3387 | ret = kvm_set_msr_common(vcpu, msr_info); |
4e47c7a6 | 3388 | break; |
ba904635 WA |
3389 | case MSR_IA32_TSC_ADJUST: |
3390 | ret = kvm_set_msr_common(vcpu, msr_info); | |
4e47c7a6 | 3391 | break; |
c45dcc71 AR |
3392 | case MSR_IA32_MCG_EXT_CTL: |
3393 | if ((!msr_info->host_initiated && | |
3394 | !(to_vmx(vcpu)->msr_ia32_feature_control & | |
3395 | FEATURE_CONTROL_LMCE)) || | |
3396 | (data & ~MCG_EXT_CTL_LMCE_EN)) | |
3397 | return 1; | |
3398 | vcpu->arch.mcg_ext_ctl = data; | |
3399 | break; | |
cae50139 | 3400 | case MSR_IA32_FEATURE_CONTROL: |
37e4c997 | 3401 | if (!vmx_feature_control_msr_valid(vcpu, data) || |
3b84080b | 3402 | (to_vmx(vcpu)->msr_ia32_feature_control & |
cae50139 JK |
3403 | FEATURE_CONTROL_LOCKED && !msr_info->host_initiated)) |
3404 | return 1; | |
3b84080b | 3405 | vmx->msr_ia32_feature_control = data; |
cae50139 JK |
3406 | if (msr_info->host_initiated && data == 0) |
3407 | vmx_leave_nested(vcpu); | |
3408 | break; | |
3409 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
62cc6b9d DM |
3410 | if (!msr_info->host_initiated) |
3411 | return 1; /* they are read-only */ | |
3412 | if (!nested_vmx_allowed(vcpu)) | |
3413 | return 1; | |
3414 | return vmx_set_vmx_msr(vcpu, msr_index, data); | |
20300099 WL |
3415 | case MSR_IA32_XSS: |
3416 | if (!vmx_xsaves_supported()) | |
3417 | return 1; | |
3418 | /* | |
3419 | * The only supported bit as of Skylake is bit 8, but | |
3420 | * it is not supported on KVM. | |
3421 | */ | |
3422 | if (data != 0) | |
3423 | return 1; | |
3424 | vcpu->arch.ia32_xss = data; | |
3425 | if (vcpu->arch.ia32_xss != host_xss) | |
3426 | add_atomic_switch_msr(vmx, MSR_IA32_XSS, | |
3427 | vcpu->arch.ia32_xss, host_xss); | |
3428 | else | |
3429 | clear_atomic_switch_msr(vmx, MSR_IA32_XSS); | |
3430 | break; | |
4e47c7a6 | 3431 | case MSR_TSC_AUX: |
d6321d49 RK |
3432 | if (!msr_info->host_initiated && |
3433 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) | |
4e47c7a6 SY |
3434 | return 1; |
3435 | /* Check reserved bit, higher 32 bits should be zero */ | |
3436 | if ((data >> 32) != 0) | |
3437 | return 1; | |
3438 | /* Otherwise falls through */ | |
6aa8b732 | 3439 | default: |
8b9cf98c | 3440 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d | 3441 | if (msr) { |
8b3c3104 | 3442 | u64 old_msr_data = msr->data; |
3bab1f5d | 3443 | msr->data = data; |
2225fd56 AK |
3444 | if (msr - vmx->guest_msrs < vmx->save_nmsrs) { |
3445 | preempt_disable(); | |
8b3c3104 AH |
3446 | ret = kvm_set_shared_msr(msr->index, msr->data, |
3447 | msr->mask); | |
2225fd56 | 3448 | preempt_enable(); |
8b3c3104 AH |
3449 | if (ret) |
3450 | msr->data = old_msr_data; | |
2225fd56 | 3451 | } |
3bab1f5d | 3452 | break; |
6aa8b732 | 3453 | } |
8fe8ab46 | 3454 | ret = kvm_set_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3455 | } |
3456 | ||
2cc51560 | 3457 | return ret; |
6aa8b732 AK |
3458 | } |
3459 | ||
5fdbf976 | 3460 | static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
6aa8b732 | 3461 | { |
5fdbf976 MT |
3462 | __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); |
3463 | switch (reg) { | |
3464 | case VCPU_REGS_RSP: | |
3465 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
3466 | break; | |
3467 | case VCPU_REGS_RIP: | |
3468 | vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); | |
3469 | break; | |
6de4f3ad AK |
3470 | case VCPU_EXREG_PDPTR: |
3471 | if (enable_ept) | |
3472 | ept_save_pdptrs(vcpu); | |
3473 | break; | |
5fdbf976 MT |
3474 | default: |
3475 | break; | |
3476 | } | |
6aa8b732 AK |
3477 | } |
3478 | ||
6aa8b732 AK |
3479 | static __init int cpu_has_kvm_support(void) |
3480 | { | |
6210e37b | 3481 | return cpu_has_vmx(); |
6aa8b732 AK |
3482 | } |
3483 | ||
3484 | static __init int vmx_disabled_by_bios(void) | |
3485 | { | |
3486 | u64 msr; | |
3487 | ||
3488 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
cafd6659 | 3489 | if (msr & FEATURE_CONTROL_LOCKED) { |
23f3e991 | 3490 | /* launched w/ TXT and VMX disabled */ |
cafd6659 SW |
3491 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
3492 | && tboot_enabled()) | |
3493 | return 1; | |
23f3e991 | 3494 | /* launched w/o TXT and VMX only enabled w/ TXT */ |
cafd6659 | 3495 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) |
23f3e991 | 3496 | && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
f9335afe SW |
3497 | && !tboot_enabled()) { |
3498 | printk(KERN_WARNING "kvm: disable TXT in the BIOS or " | |
23f3e991 | 3499 | "activate TXT before enabling KVM\n"); |
cafd6659 | 3500 | return 1; |
f9335afe | 3501 | } |
23f3e991 JC |
3502 | /* launched w/o TXT and VMX disabled */ |
3503 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) | |
3504 | && !tboot_enabled()) | |
3505 | return 1; | |
cafd6659 SW |
3506 | } |
3507 | ||
3508 | return 0; | |
6aa8b732 AK |
3509 | } |
3510 | ||
7725b894 DX |
3511 | static void kvm_cpu_vmxon(u64 addr) |
3512 | { | |
fe0e80be | 3513 | cr4_set_bits(X86_CR4_VMXE); |
1c5ac21a AS |
3514 | intel_pt_handle_vmx(1); |
3515 | ||
7725b894 DX |
3516 | asm volatile (ASM_VMX_VMXON_RAX |
3517 | : : "a"(&addr), "m"(addr) | |
3518 | : "memory", "cc"); | |
3519 | } | |
3520 | ||
13a34e06 | 3521 | static int hardware_enable(void) |
6aa8b732 AK |
3522 | { |
3523 | int cpu = raw_smp_processor_id(); | |
3524 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
cafd6659 | 3525 | u64 old, test_bits; |
6aa8b732 | 3526 | |
1e02ce4c | 3527 | if (cr4_read_shadow() & X86_CR4_VMXE) |
10474ae8 AG |
3528 | return -EBUSY; |
3529 | ||
d462b819 | 3530 | INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); |
bf9f6ac8 FW |
3531 | INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); |
3532 | spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
8f536b76 ZY |
3533 | |
3534 | /* | |
3535 | * Now we can enable the vmclear operation in kdump | |
3536 | * since the loaded_vmcss_on_cpu list on this cpu | |
3537 | * has been initialized. | |
3538 | * | |
3539 | * Though the cpu is not in VMX operation now, there | |
3540 | * is no problem to enable the vmclear operation | |
3541 | * for the loaded_vmcss_on_cpu list is empty! | |
3542 | */ | |
3543 | crash_enable_local_vmclear(cpu); | |
3544 | ||
6aa8b732 | 3545 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
cafd6659 SW |
3546 | |
3547 | test_bits = FEATURE_CONTROL_LOCKED; | |
3548 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
3549 | if (tboot_enabled()) | |
3550 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX; | |
3551 | ||
3552 | if ((old & test_bits) != test_bits) { | |
6aa8b732 | 3553 | /* enable and lock */ |
cafd6659 SW |
3554 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); |
3555 | } | |
fe0e80be | 3556 | kvm_cpu_vmxon(phys_addr); |
fdf288bf DH |
3557 | if (enable_ept) |
3558 | ept_sync_global(); | |
10474ae8 AG |
3559 | |
3560 | return 0; | |
6aa8b732 AK |
3561 | } |
3562 | ||
d462b819 | 3563 | static void vmclear_local_loaded_vmcss(void) |
543e4243 AK |
3564 | { |
3565 | int cpu = raw_smp_processor_id(); | |
d462b819 | 3566 | struct loaded_vmcs *v, *n; |
543e4243 | 3567 | |
d462b819 NHE |
3568 | list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), |
3569 | loaded_vmcss_on_cpu_link) | |
3570 | __loaded_vmcs_clear(v); | |
543e4243 AK |
3571 | } |
3572 | ||
710ff4a8 EH |
3573 | |
3574 | /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() | |
3575 | * tricks. | |
3576 | */ | |
3577 | static void kvm_cpu_vmxoff(void) | |
6aa8b732 | 3578 | { |
4ecac3fd | 3579 | asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc"); |
1c5ac21a AS |
3580 | |
3581 | intel_pt_handle_vmx(0); | |
fe0e80be | 3582 | cr4_clear_bits(X86_CR4_VMXE); |
6aa8b732 AK |
3583 | } |
3584 | ||
13a34e06 | 3585 | static void hardware_disable(void) |
710ff4a8 | 3586 | { |
fe0e80be DH |
3587 | vmclear_local_loaded_vmcss(); |
3588 | kvm_cpu_vmxoff(); | |
710ff4a8 EH |
3589 | } |
3590 | ||
1c3d14fe | 3591 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 3592 | u32 msr, u32 *result) |
1c3d14fe YS |
3593 | { |
3594 | u32 vmx_msr_low, vmx_msr_high; | |
3595 | u32 ctl = ctl_min | ctl_opt; | |
3596 | ||
3597 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
3598 | ||
3599 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
3600 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
3601 | ||
3602 | /* Ensure minimum (required) set of control bits are supported. */ | |
3603 | if (ctl_min & ~ctl) | |
002c7f7c | 3604 | return -EIO; |
1c3d14fe YS |
3605 | |
3606 | *result = ctl; | |
3607 | return 0; | |
3608 | } | |
3609 | ||
110312c8 AK |
3610 | static __init bool allow_1_setting(u32 msr, u32 ctl) |
3611 | { | |
3612 | u32 vmx_msr_low, vmx_msr_high; | |
3613 | ||
3614 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
3615 | return vmx_msr_high & ctl; | |
3616 | } | |
3617 | ||
002c7f7c | 3618 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
3619 | { |
3620 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 3621 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
3622 | u32 _pin_based_exec_control = 0; |
3623 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 3624 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
3625 | u32 _vmexit_control = 0; |
3626 | u32 _vmentry_control = 0; | |
3627 | ||
10166744 | 3628 | min = CPU_BASED_HLT_EXITING | |
1c3d14fe YS |
3629 | #ifdef CONFIG_X86_64 |
3630 | CPU_BASED_CR8_LOAD_EXITING | | |
3631 | CPU_BASED_CR8_STORE_EXITING | | |
3632 | #endif | |
d56f546d SY |
3633 | CPU_BASED_CR3_LOAD_EXITING | |
3634 | CPU_BASED_CR3_STORE_EXITING | | |
1c3d14fe YS |
3635 | CPU_BASED_USE_IO_BITMAPS | |
3636 | CPU_BASED_MOV_DR_EXITING | | |
a7052897 | 3637 | CPU_BASED_USE_TSC_OFFSETING | |
fee84b07 AK |
3638 | CPU_BASED_INVLPG_EXITING | |
3639 | CPU_BASED_RDPMC_EXITING; | |
443381a8 | 3640 | |
668fffa3 MT |
3641 | if (!kvm_mwait_in_guest()) |
3642 | min |= CPU_BASED_MWAIT_EXITING | | |
3643 | CPU_BASED_MONITOR_EXITING; | |
3644 | ||
f78e0e2e | 3645 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 3646 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 3647 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
3648 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
3649 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 3650 | return -EIO; |
6e5d865c YS |
3651 | #ifdef CONFIG_X86_64 |
3652 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
3653 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
3654 | ~CPU_BASED_CR8_STORE_EXITING; | |
3655 | #endif | |
f78e0e2e | 3656 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
3657 | min2 = 0; |
3658 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
8d14695f | 3659 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
2384d2b3 | 3660 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d | 3661 | SECONDARY_EXEC_ENABLE_VPID | |
3a624e29 | 3662 | SECONDARY_EXEC_ENABLE_EPT | |
4b8d54f9 | 3663 | SECONDARY_EXEC_UNRESTRICTED_GUEST | |
4e47c7a6 | 3664 | SECONDARY_EXEC_PAUSE_LOOP_EXITING | |
ad756a16 | 3665 | SECONDARY_EXEC_RDTSCP | |
83d4c286 | 3666 | SECONDARY_EXEC_ENABLE_INVPCID | |
c7c9c56c | 3667 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
abc4fc58 | 3668 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
20300099 | 3669 | SECONDARY_EXEC_SHADOW_VMCS | |
843e4330 | 3670 | SECONDARY_EXEC_XSAVES | |
736fdf72 DH |
3671 | SECONDARY_EXEC_RDSEED_EXITING | |
3672 | SECONDARY_EXEC_RDRAND_EXITING | | |
8b3e34e4 | 3673 | SECONDARY_EXEC_ENABLE_PML | |
2a499e49 BD |
3674 | SECONDARY_EXEC_TSC_SCALING | |
3675 | SECONDARY_EXEC_ENABLE_VMFUNC; | |
d56f546d SY |
3676 | if (adjust_vmx_controls(min2, opt2, |
3677 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
3678 | &_cpu_based_2nd_exec_control) < 0) |
3679 | return -EIO; | |
3680 | } | |
3681 | #ifndef CONFIG_X86_64 | |
3682 | if (!(_cpu_based_2nd_exec_control & | |
3683 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
3684 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
3685 | #endif | |
83d4c286 YZ |
3686 | |
3687 | if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
3688 | _cpu_based_2nd_exec_control &= ~( | |
8d14695f | 3689 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
c7c9c56c YZ |
3690 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
3691 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
83d4c286 | 3692 | |
61f1dd90 WL |
3693 | rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, |
3694 | &vmx_capability.ept, &vmx_capability.vpid); | |
3695 | ||
d56f546d | 3696 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
a7052897 MT |
3697 | /* CR3 accesses and invlpg don't need to cause VM Exits when EPT |
3698 | enabled */ | |
5fff7d27 GN |
3699 | _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | |
3700 | CPU_BASED_CR3_STORE_EXITING | | |
3701 | CPU_BASED_INVLPG_EXITING); | |
61f1dd90 WL |
3702 | } else if (vmx_capability.ept) { |
3703 | vmx_capability.ept = 0; | |
3704 | pr_warn_once("EPT CAP should not exist if not support " | |
3705 | "1-setting enable EPT VM-execution control\n"); | |
3706 | } | |
3707 | if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) && | |
3708 | vmx_capability.vpid) { | |
3709 | vmx_capability.vpid = 0; | |
3710 | pr_warn_once("VPID CAP should not exist if not support " | |
3711 | "1-setting enable VPID VM-execution control\n"); | |
d56f546d | 3712 | } |
1c3d14fe | 3713 | |
91fa0f8e | 3714 | min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; |
1c3d14fe YS |
3715 | #ifdef CONFIG_X86_64 |
3716 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
3717 | #endif | |
a547c6db | 3718 | opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT | |
91fa0f8e | 3719 | VM_EXIT_CLEAR_BNDCFGS; |
1c3d14fe YS |
3720 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, |
3721 | &_vmexit_control) < 0) | |
002c7f7c | 3722 | return -EIO; |
1c3d14fe | 3723 | |
8a1b4392 PB |
3724 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; |
3725 | opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | | |
3726 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be YZ |
3727 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, |
3728 | &_pin_based_exec_control) < 0) | |
3729 | return -EIO; | |
3730 | ||
1c17c3e6 PB |
3731 | if (cpu_has_broken_vmx_preemption_timer()) |
3732 | _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be | 3733 | if (!(_cpu_based_2nd_exec_control & |
91fa0f8e | 3734 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) |
01e439be YZ |
3735 | _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; |
3736 | ||
c845f9c6 | 3737 | min = VM_ENTRY_LOAD_DEBUG_CONTROLS; |
da8999d3 | 3738 | opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS; |
1c3d14fe YS |
3739 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, |
3740 | &_vmentry_control) < 0) | |
002c7f7c | 3741 | return -EIO; |
6aa8b732 | 3742 | |
c68876fd | 3743 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
3744 | |
3745 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
3746 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 3747 | return -EIO; |
1c3d14fe YS |
3748 | |
3749 | #ifdef CONFIG_X86_64 | |
3750 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
3751 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 3752 | return -EIO; |
1c3d14fe YS |
3753 | #endif |
3754 | ||
3755 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
3756 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 3757 | return -EIO; |
1c3d14fe | 3758 | |
002c7f7c | 3759 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
16cb0255 | 3760 | vmcs_conf->order = get_order(vmcs_conf->size); |
9ac7e3e8 | 3761 | vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; |
002c7f7c | 3762 | vmcs_conf->revision_id = vmx_msr_low; |
1c3d14fe | 3763 | |
002c7f7c YS |
3764 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
3765 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 3766 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
3767 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
3768 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe | 3769 | |
110312c8 AK |
3770 | cpu_has_load_ia32_efer = |
3771 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
3772 | VM_ENTRY_LOAD_IA32_EFER) | |
3773 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
3774 | VM_EXIT_LOAD_IA32_EFER); | |
3775 | ||
8bf00a52 GN |
3776 | cpu_has_load_perf_global_ctrl = |
3777 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
3778 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
3779 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
3780 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
3781 | ||
3782 | /* | |
3783 | * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL | |
bb3541f1 | 3784 | * but due to errata below it can't be used. Workaround is to use |
8bf00a52 GN |
3785 | * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL. |
3786 | * | |
3787 | * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32] | |
3788 | * | |
3789 | * AAK155 (model 26) | |
3790 | * AAP115 (model 30) | |
3791 | * AAT100 (model 37) | |
3792 | * BC86,AAY89,BD102 (model 44) | |
3793 | * BA97 (model 46) | |
3794 | * | |
3795 | */ | |
3796 | if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) { | |
3797 | switch (boot_cpu_data.x86_model) { | |
3798 | case 26: | |
3799 | case 30: | |
3800 | case 37: | |
3801 | case 44: | |
3802 | case 46: | |
3803 | cpu_has_load_perf_global_ctrl = false; | |
3804 | printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " | |
3805 | "does not work properly. Using workaround\n"); | |
3806 | break; | |
3807 | default: | |
3808 | break; | |
3809 | } | |
3810 | } | |
3811 | ||
782511b0 | 3812 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
20300099 WL |
3813 | rdmsrl(MSR_IA32_XSS, host_xss); |
3814 | ||
1c3d14fe | 3815 | return 0; |
c68876fd | 3816 | } |
6aa8b732 AK |
3817 | |
3818 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
3819 | { | |
3820 | int node = cpu_to_node(cpu); | |
3821 | struct page *pages; | |
3822 | struct vmcs *vmcs; | |
3823 | ||
96db800f | 3824 | pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
3825 | if (!pages) |
3826 | return NULL; | |
3827 | vmcs = page_address(pages); | |
1c3d14fe YS |
3828 | memset(vmcs, 0, vmcs_config.size); |
3829 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
3830 | return vmcs; |
3831 | } | |
3832 | ||
3833 | static struct vmcs *alloc_vmcs(void) | |
3834 | { | |
d3b2c338 | 3835 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
3836 | } |
3837 | ||
3838 | static void free_vmcs(struct vmcs *vmcs) | |
3839 | { | |
1c3d14fe | 3840 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
3841 | } |
3842 | ||
d462b819 NHE |
3843 | /* |
3844 | * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded | |
3845 | */ | |
3846 | static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) | |
3847 | { | |
3848 | if (!loaded_vmcs->vmcs) | |
3849 | return; | |
3850 | loaded_vmcs_clear(loaded_vmcs); | |
3851 | free_vmcs(loaded_vmcs->vmcs); | |
3852 | loaded_vmcs->vmcs = NULL; | |
355f4fb1 | 3853 | WARN_ON(loaded_vmcs->shadow_vmcs != NULL); |
d462b819 NHE |
3854 | } |
3855 | ||
39959588 | 3856 | static void free_kvm_area(void) |
6aa8b732 AK |
3857 | { |
3858 | int cpu; | |
3859 | ||
3230bb47 | 3860 | for_each_possible_cpu(cpu) { |
6aa8b732 | 3861 | free_vmcs(per_cpu(vmxarea, cpu)); |
3230bb47 ZA |
3862 | per_cpu(vmxarea, cpu) = NULL; |
3863 | } | |
6aa8b732 AK |
3864 | } |
3865 | ||
85fd514e JM |
3866 | enum vmcs_field_type { |
3867 | VMCS_FIELD_TYPE_U16 = 0, | |
3868 | VMCS_FIELD_TYPE_U64 = 1, | |
3869 | VMCS_FIELD_TYPE_U32 = 2, | |
3870 | VMCS_FIELD_TYPE_NATURAL_WIDTH = 3 | |
3871 | }; | |
3872 | ||
3873 | static inline int vmcs_field_type(unsigned long field) | |
3874 | { | |
3875 | if (0x1 & field) /* the *_HIGH fields are all 32 bit */ | |
3876 | return VMCS_FIELD_TYPE_U32; | |
3877 | return (field >> 13) & 0x3 ; | |
3878 | } | |
3879 | ||
3880 | static inline int vmcs_field_readonly(unsigned long field) | |
3881 | { | |
3882 | return (((field >> 10) & 0x3) == 1); | |
3883 | } | |
3884 | ||
fe2b201b BD |
3885 | static void init_vmcs_shadow_fields(void) |
3886 | { | |
3887 | int i, j; | |
3888 | ||
3889 | /* No checks for read only fields yet */ | |
3890 | ||
3891 | for (i = j = 0; i < max_shadow_read_write_fields; i++) { | |
3892 | switch (shadow_read_write_fields[i]) { | |
3893 | case GUEST_BNDCFGS: | |
a87036ad | 3894 | if (!kvm_mpx_supported()) |
fe2b201b BD |
3895 | continue; |
3896 | break; | |
3897 | default: | |
3898 | break; | |
3899 | } | |
3900 | ||
3901 | if (j < i) | |
3902 | shadow_read_write_fields[j] = | |
3903 | shadow_read_write_fields[i]; | |
3904 | j++; | |
3905 | } | |
3906 | max_shadow_read_write_fields = j; | |
3907 | ||
3908 | /* shadowed fields guest access without vmexit */ | |
3909 | for (i = 0; i < max_shadow_read_write_fields; i++) { | |
85fd514e JM |
3910 | unsigned long field = shadow_read_write_fields[i]; |
3911 | ||
3912 | clear_bit(field, vmx_vmwrite_bitmap); | |
3913 | clear_bit(field, vmx_vmread_bitmap); | |
3914 | if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) { | |
3915 | clear_bit(field + 1, vmx_vmwrite_bitmap); | |
3916 | clear_bit(field + 1, vmx_vmread_bitmap); | |
3917 | } | |
3918 | } | |
3919 | for (i = 0; i < max_shadow_read_only_fields; i++) { | |
3920 | unsigned long field = shadow_read_only_fields[i]; | |
3921 | ||
3922 | clear_bit(field, vmx_vmread_bitmap); | |
3923 | if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) | |
3924 | clear_bit(field + 1, vmx_vmread_bitmap); | |
fe2b201b | 3925 | } |
fe2b201b BD |
3926 | } |
3927 | ||
6aa8b732 AK |
3928 | static __init int alloc_kvm_area(void) |
3929 | { | |
3930 | int cpu; | |
3931 | ||
3230bb47 | 3932 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
3933 | struct vmcs *vmcs; |
3934 | ||
3935 | vmcs = alloc_vmcs_cpu(cpu); | |
3936 | if (!vmcs) { | |
3937 | free_kvm_area(); | |
3938 | return -ENOMEM; | |
3939 | } | |
3940 | ||
3941 | per_cpu(vmxarea, cpu) = vmcs; | |
3942 | } | |
3943 | return 0; | |
3944 | } | |
3945 | ||
91b0aa2c | 3946 | static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, |
d99e4152 | 3947 | struct kvm_segment *save) |
6aa8b732 | 3948 | { |
d99e4152 GN |
3949 | if (!emulate_invalid_guest_state) { |
3950 | /* | |
3951 | * CS and SS RPL should be equal during guest entry according | |
3952 | * to VMX spec, but in reality it is not always so. Since vcpu | |
3953 | * is in the middle of the transition from real mode to | |
3954 | * protected mode it is safe to assume that RPL 0 is a good | |
3955 | * default value. | |
3956 | */ | |
3957 | if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) | |
b32a9918 NA |
3958 | save->selector &= ~SEGMENT_RPL_MASK; |
3959 | save->dpl = save->selector & SEGMENT_RPL_MASK; | |
d99e4152 | 3960 | save->s = 1; |
6aa8b732 | 3961 | } |
d99e4152 | 3962 | vmx_set_segment(vcpu, save, seg); |
6aa8b732 AK |
3963 | } |
3964 | ||
3965 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
3966 | { | |
3967 | unsigned long flags; | |
a89a8fb9 | 3968 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 3969 | |
d99e4152 GN |
3970 | /* |
3971 | * Update real mode segment cache. It may be not up-to-date if sement | |
3972 | * register was written while vcpu was in a guest mode. | |
3973 | */ | |
3974 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
3975 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
3976 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
3977 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
3978 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); | |
3979 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
3980 | ||
7ffd92c5 | 3981 | vmx->rmode.vm86_active = 0; |
6aa8b732 | 3982 | |
2fb92db1 AK |
3983 | vmx_segment_cache_clear(vmx); |
3984 | ||
f5f7b2fe | 3985 | vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
6aa8b732 AK |
3986 | |
3987 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 AK |
3988 | flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; |
3989 | flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
6aa8b732 AK |
3990 | vmcs_writel(GUEST_RFLAGS, flags); |
3991 | ||
66aee91a RR |
3992 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
3993 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
3994 | |
3995 | update_exception_bitmap(vcpu); | |
3996 | ||
91b0aa2c GN |
3997 | fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); |
3998 | fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); | |
3999 | fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
4000 | fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
4001 | fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
4002 | fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
6aa8b732 AK |
4003 | } |
4004 | ||
f5f7b2fe | 4005 | static void fix_rmode_seg(int seg, struct kvm_segment *save) |
6aa8b732 | 4006 | { |
772e0318 | 4007 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
d99e4152 GN |
4008 | struct kvm_segment var = *save; |
4009 | ||
4010 | var.dpl = 0x3; | |
4011 | if (seg == VCPU_SREG_CS) | |
4012 | var.type = 0x3; | |
4013 | ||
4014 | if (!emulate_invalid_guest_state) { | |
4015 | var.selector = var.base >> 4; | |
4016 | var.base = var.base & 0xffff0; | |
4017 | var.limit = 0xffff; | |
4018 | var.g = 0; | |
4019 | var.db = 0; | |
4020 | var.present = 1; | |
4021 | var.s = 1; | |
4022 | var.l = 0; | |
4023 | var.unusable = 0; | |
4024 | var.type = 0x3; | |
4025 | var.avl = 0; | |
4026 | if (save->base & 0xf) | |
4027 | printk_once(KERN_WARNING "kvm: segment base is not " | |
4028 | "paragraph aligned when entering " | |
4029 | "protected mode (seg=%d)", seg); | |
4030 | } | |
6aa8b732 | 4031 | |
d99e4152 | 4032 | vmcs_write16(sf->selector, var.selector); |
96794e4e | 4033 | vmcs_writel(sf->base, var.base); |
d99e4152 GN |
4034 | vmcs_write32(sf->limit, var.limit); |
4035 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); | |
6aa8b732 AK |
4036 | } |
4037 | ||
4038 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
4039 | { | |
4040 | unsigned long flags; | |
a89a8fb9 | 4041 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 4042 | |
f5f7b2fe AK |
4043 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
4044 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
4045 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
4046 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
4047 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
c6ad1153 GN |
4048 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); |
4049 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
f5f7b2fe | 4050 | |
7ffd92c5 | 4051 | vmx->rmode.vm86_active = 1; |
6aa8b732 | 4052 | |
776e58ea GN |
4053 | /* |
4054 | * Very old userspace does not call KVM_SET_TSS_ADDR before entering | |
4918c6ca | 4055 | * vcpu. Warn the user that an update is overdue. |
776e58ea | 4056 | */ |
4918c6ca | 4057 | if (!vcpu->kvm->arch.tss_addr) |
776e58ea GN |
4058 | printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " |
4059 | "called before entering vcpu\n"); | |
776e58ea | 4060 | |
2fb92db1 AK |
4061 | vmx_segment_cache_clear(vmx); |
4062 | ||
4918c6ca | 4063 | vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr); |
6aa8b732 | 4064 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
6aa8b732 AK |
4065 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
4066 | ||
4067 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 | 4068 | vmx->rmode.save_rflags = flags; |
6aa8b732 | 4069 | |
053de044 | 4070 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
4071 | |
4072 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 4073 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
4074 | update_exception_bitmap(vcpu); |
4075 | ||
d99e4152 GN |
4076 | fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); |
4077 | fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); | |
4078 | fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
4079 | fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
4080 | fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
4081 | fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
b246dd5d | 4082 | |
8668a3c4 | 4083 | kvm_mmu_reset_context(vcpu); |
6aa8b732 AK |
4084 | } |
4085 | ||
401d10de AS |
4086 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
4087 | { | |
4088 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
26bb0981 AK |
4089 | struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); |
4090 | ||
4091 | if (!msr) | |
4092 | return; | |
401d10de | 4093 | |
44ea2b17 AK |
4094 | /* |
4095 | * Force kernel_gs_base reloading before EFER changes, as control | |
4096 | * of this msr depends on is_long_mode(). | |
4097 | */ | |
4098 | vmx_load_host_state(to_vmx(vcpu)); | |
f6801dff | 4099 | vcpu->arch.efer = efer; |
401d10de | 4100 | if (efer & EFER_LMA) { |
2961e876 | 4101 | vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
4102 | msr->data = efer; |
4103 | } else { | |
2961e876 | 4104 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
4105 | |
4106 | msr->data = efer & ~EFER_LME; | |
4107 | } | |
4108 | setup_msrs(vmx); | |
4109 | } | |
4110 | ||
05b3e0c2 | 4111 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
4112 | |
4113 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
4114 | { | |
4115 | u32 guest_tr_ar; | |
4116 | ||
2fb92db1 AK |
4117 | vmx_segment_cache_clear(to_vmx(vcpu)); |
4118 | ||
6aa8b732 | 4119 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); |
4d283ec9 | 4120 | if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { |
bd80158a JK |
4121 | pr_debug_ratelimited("%s: tss fixup for long mode. \n", |
4122 | __func__); | |
6aa8b732 | 4123 | vmcs_write32(GUEST_TR_AR_BYTES, |
4d283ec9 AL |
4124 | (guest_tr_ar & ~VMX_AR_TYPE_MASK) |
4125 | | VMX_AR_TYPE_BUSY_64_TSS); | |
6aa8b732 | 4126 | } |
da38f438 | 4127 | vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); |
6aa8b732 AK |
4128 | } |
4129 | ||
4130 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
4131 | { | |
2961e876 | 4132 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
da38f438 | 4133 | vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); |
6aa8b732 AK |
4134 | } |
4135 | ||
4136 | #endif | |
4137 | ||
dd5f5341 | 4138 | static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid) |
2384d2b3 | 4139 | { |
dd180b3e XG |
4140 | if (enable_ept) { |
4141 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
4142 | return; | |
995f00a6 | 4143 | ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa)); |
f0b98c02 JM |
4144 | } else { |
4145 | vpid_sync_context(vpid); | |
dd180b3e | 4146 | } |
2384d2b3 SY |
4147 | } |
4148 | ||
dd5f5341 WL |
4149 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
4150 | { | |
4151 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid); | |
4152 | } | |
4153 | ||
fb6c8198 JM |
4154 | static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu) |
4155 | { | |
4156 | if (enable_ept) | |
4157 | vmx_flush_tlb(vcpu); | |
4158 | } | |
4159 | ||
e8467fda AK |
4160 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
4161 | { | |
4162 | ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; | |
4163 | ||
4164 | vcpu->arch.cr0 &= ~cr0_guest_owned_bits; | |
4165 | vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; | |
4166 | } | |
4167 | ||
aff48baa AK |
4168 | static void vmx_decache_cr3(struct kvm_vcpu *vcpu) |
4169 | { | |
4170 | if (enable_ept && is_paging(vcpu)) | |
4171 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); | |
4172 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
4173 | } | |
4174 | ||
25c4c276 | 4175 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 4176 | { |
fc78f519 AK |
4177 | ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; |
4178 | ||
4179 | vcpu->arch.cr4 &= ~cr4_guest_owned_bits; | |
4180 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; | |
399badf3 AK |
4181 | } |
4182 | ||
1439442c SY |
4183 | static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
4184 | { | |
d0d538b9 GN |
4185 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
4186 | ||
6de4f3ad AK |
4187 | if (!test_bit(VCPU_EXREG_PDPTR, |
4188 | (unsigned long *)&vcpu->arch.regs_dirty)) | |
4189 | return; | |
4190 | ||
1439442c | 4191 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
d0d538b9 GN |
4192 | vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); |
4193 | vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); | |
4194 | vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); | |
4195 | vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); | |
1439442c SY |
4196 | } |
4197 | } | |
4198 | ||
8f5d549f AK |
4199 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu) |
4200 | { | |
d0d538b9 GN |
4201 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
4202 | ||
8f5d549f | 4203 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
d0d538b9 GN |
4204 | mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); |
4205 | mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); | |
4206 | mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); | |
4207 | mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); | |
8f5d549f | 4208 | } |
6de4f3ad AK |
4209 | |
4210 | __set_bit(VCPU_EXREG_PDPTR, | |
4211 | (unsigned long *)&vcpu->arch.regs_avail); | |
4212 | __set_bit(VCPU_EXREG_PDPTR, | |
4213 | (unsigned long *)&vcpu->arch.regs_dirty); | |
8f5d549f AK |
4214 | } |
4215 | ||
3899152c DM |
4216 | static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) |
4217 | { | |
4218 | u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0; | |
4219 | u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1; | |
4220 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
4221 | ||
4222 | if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high & | |
4223 | SECONDARY_EXEC_UNRESTRICTED_GUEST && | |
4224 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST)) | |
4225 | fixed0 &= ~(X86_CR0_PE | X86_CR0_PG); | |
4226 | ||
4227 | return fixed_bits_valid(val, fixed0, fixed1); | |
4228 | } | |
4229 | ||
4230 | static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) | |
4231 | { | |
4232 | u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0; | |
4233 | u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1; | |
4234 | ||
4235 | return fixed_bits_valid(val, fixed0, fixed1); | |
4236 | } | |
4237 | ||
4238 | static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val) | |
4239 | { | |
4240 | u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0; | |
4241 | u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1; | |
4242 | ||
4243 | return fixed_bits_valid(val, fixed0, fixed1); | |
4244 | } | |
4245 | ||
4246 | /* No difference in the restrictions on guest and host CR4 in VMX operation. */ | |
4247 | #define nested_guest_cr4_valid nested_cr4_valid | |
4248 | #define nested_host_cr4_valid nested_cr4_valid | |
4249 | ||
5e1746d6 | 4250 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
1439442c SY |
4251 | |
4252 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, | |
4253 | unsigned long cr0, | |
4254 | struct kvm_vcpu *vcpu) | |
4255 | { | |
5233dd51 MT |
4256 | if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) |
4257 | vmx_decache_cr3(vcpu); | |
1439442c SY |
4258 | if (!(cr0 & X86_CR0_PG)) { |
4259 | /* From paging/starting to nonpaging */ | |
4260 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 4261 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | |
1439442c SY |
4262 | (CPU_BASED_CR3_LOAD_EXITING | |
4263 | CPU_BASED_CR3_STORE_EXITING)); | |
4264 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 4265 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c SY |
4266 | } else if (!is_paging(vcpu)) { |
4267 | /* From nonpaging to paging */ | |
4268 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 4269 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & |
1439442c SY |
4270 | ~(CPU_BASED_CR3_LOAD_EXITING | |
4271 | CPU_BASED_CR3_STORE_EXITING)); | |
4272 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 4273 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c | 4274 | } |
95eb84a7 SY |
4275 | |
4276 | if (!(cr0 & X86_CR0_WP)) | |
4277 | *hw_cr0 &= ~X86_CR0_WP; | |
1439442c SY |
4278 | } |
4279 | ||
6aa8b732 AK |
4280 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
4281 | { | |
7ffd92c5 | 4282 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3a624e29 NK |
4283 | unsigned long hw_cr0; |
4284 | ||
5037878e | 4285 | hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK); |
3a624e29 | 4286 | if (enable_unrestricted_guest) |
5037878e | 4287 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; |
218e763f | 4288 | else { |
5037878e | 4289 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; |
1439442c | 4290 | |
218e763f GN |
4291 | if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) |
4292 | enter_pmode(vcpu); | |
6aa8b732 | 4293 | |
218e763f GN |
4294 | if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) |
4295 | enter_rmode(vcpu); | |
4296 | } | |
6aa8b732 | 4297 | |
05b3e0c2 | 4298 | #ifdef CONFIG_X86_64 |
f6801dff | 4299 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 4300 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 4301 | enter_lmode(vcpu); |
707d92fa | 4302 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
4303 | exit_lmode(vcpu); |
4304 | } | |
4305 | #endif | |
4306 | ||
089d034e | 4307 | if (enable_ept) |
1439442c SY |
4308 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); |
4309 | ||
6aa8b732 | 4310 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 4311 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 4312 | vcpu->arch.cr0 = cr0; |
14168786 GN |
4313 | |
4314 | /* depends on vcpu->arch.cr0 to be set to a new value */ | |
4315 | vmx->emulation_required = emulation_required(vcpu); | |
6aa8b732 AK |
4316 | } |
4317 | ||
855feb67 YZ |
4318 | static int get_ept_level(struct kvm_vcpu *vcpu) |
4319 | { | |
4320 | if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48)) | |
4321 | return 5; | |
4322 | return 4; | |
4323 | } | |
4324 | ||
995f00a6 | 4325 | static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa) |
1439442c | 4326 | { |
855feb67 YZ |
4327 | u64 eptp = VMX_EPTP_MT_WB; |
4328 | ||
4329 | eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4; | |
1439442c | 4330 | |
995f00a6 PF |
4331 | if (enable_ept_ad_bits && |
4332 | (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu))) | |
bb97a016 | 4333 | eptp |= VMX_EPTP_AD_ENABLE_BIT; |
1439442c SY |
4334 | eptp |= (root_hpa & PAGE_MASK); |
4335 | ||
4336 | return eptp; | |
4337 | } | |
4338 | ||
6aa8b732 AK |
4339 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
4340 | { | |
1439442c SY |
4341 | unsigned long guest_cr3; |
4342 | u64 eptp; | |
4343 | ||
4344 | guest_cr3 = cr3; | |
089d034e | 4345 | if (enable_ept) { |
995f00a6 | 4346 | eptp = construct_eptp(vcpu, cr3); |
1439442c | 4347 | vmcs_write64(EPT_POINTER, eptp); |
59ab5a8f JK |
4348 | if (is_paging(vcpu) || is_guest_mode(vcpu)) |
4349 | guest_cr3 = kvm_read_cr3(vcpu); | |
4350 | else | |
4351 | guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr; | |
7c93be44 | 4352 | ept_load_pdptrs(vcpu); |
1439442c SY |
4353 | } |
4354 | ||
2384d2b3 | 4355 | vmx_flush_tlb(vcpu); |
1439442c | 4356 | vmcs_writel(GUEST_CR3, guest_cr3); |
6aa8b732 AK |
4357 | } |
4358 | ||
5e1746d6 | 4359 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 4360 | { |
085e68ee BS |
4361 | /* |
4362 | * Pass through host's Machine Check Enable value to hw_cr4, which | |
4363 | * is in force while we are in guest mode. Do not let guests control | |
4364 | * this bit, even if host CR4.MCE == 0. | |
4365 | */ | |
4366 | unsigned long hw_cr4 = | |
4367 | (cr4_read_shadow() & X86_CR4_MCE) | | |
4368 | (cr4 & ~X86_CR4_MCE) | | |
4369 | (to_vmx(vcpu)->rmode.vm86_active ? | |
4370 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); | |
1439442c | 4371 | |
5e1746d6 NHE |
4372 | if (cr4 & X86_CR4_VMXE) { |
4373 | /* | |
4374 | * To use VMXON (and later other VMX instructions), a guest | |
4375 | * must first be able to turn on cr4.VMXE (see handle_vmon()). | |
4376 | * So basically the check on whether to allow nested VMX | |
4377 | * is here. | |
4378 | */ | |
4379 | if (!nested_vmx_allowed(vcpu)) | |
4380 | return 1; | |
1a0d74e6 | 4381 | } |
3899152c DM |
4382 | |
4383 | if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) | |
5e1746d6 NHE |
4384 | return 1; |
4385 | ||
ad312c7c | 4386 | vcpu->arch.cr4 = cr4; |
bc23008b AK |
4387 | if (enable_ept) { |
4388 | if (!is_paging(vcpu)) { | |
4389 | hw_cr4 &= ~X86_CR4_PAE; | |
4390 | hw_cr4 |= X86_CR4_PSE; | |
4391 | } else if (!(cr4 & X86_CR4_PAE)) { | |
4392 | hw_cr4 &= ~X86_CR4_PAE; | |
4393 | } | |
4394 | } | |
1439442c | 4395 | |
656ec4a4 RK |
4396 | if (!enable_unrestricted_guest && !is_paging(vcpu)) |
4397 | /* | |
ddba2628 HH |
4398 | * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in |
4399 | * hardware. To emulate this behavior, SMEP/SMAP/PKU needs | |
4400 | * to be manually disabled when guest switches to non-paging | |
4401 | * mode. | |
4402 | * | |
4403 | * If !enable_unrestricted_guest, the CPU is always running | |
4404 | * with CR0.PG=1 and CR4 needs to be modified. | |
4405 | * If enable_unrestricted_guest, the CPU automatically | |
4406 | * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. | |
656ec4a4 | 4407 | */ |
ddba2628 | 4408 | hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); |
656ec4a4 | 4409 | |
1439442c SY |
4410 | vmcs_writel(CR4_READ_SHADOW, cr4); |
4411 | vmcs_writel(GUEST_CR4, hw_cr4); | |
5e1746d6 | 4412 | return 0; |
6aa8b732 AK |
4413 | } |
4414 | ||
6aa8b732 AK |
4415 | static void vmx_get_segment(struct kvm_vcpu *vcpu, |
4416 | struct kvm_segment *var, int seg) | |
4417 | { | |
a9179499 | 4418 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 AK |
4419 | u32 ar; |
4420 | ||
c6ad1153 | 4421 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
f5f7b2fe | 4422 | *var = vmx->rmode.segs[seg]; |
a9179499 | 4423 | if (seg == VCPU_SREG_TR |
2fb92db1 | 4424 | || var->selector == vmx_read_guest_seg_selector(vmx, seg)) |
f5f7b2fe | 4425 | return; |
1390a28b AK |
4426 | var->base = vmx_read_guest_seg_base(vmx, seg); |
4427 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
4428 | return; | |
a9179499 | 4429 | } |
2fb92db1 AK |
4430 | var->base = vmx_read_guest_seg_base(vmx, seg); |
4431 | var->limit = vmx_read_guest_seg_limit(vmx, seg); | |
4432 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
4433 | ar = vmx_read_guest_seg_ar(vmx, seg); | |
03617c18 | 4434 | var->unusable = (ar >> 16) & 1; |
6aa8b732 AK |
4435 | var->type = ar & 15; |
4436 | var->s = (ar >> 4) & 1; | |
4437 | var->dpl = (ar >> 5) & 3; | |
03617c18 GN |
4438 | /* |
4439 | * Some userspaces do not preserve unusable property. Since usable | |
4440 | * segment has to be present according to VMX spec we can use present | |
4441 | * property to amend userspace bug by making unusable segment always | |
4442 | * nonpresent. vmx_segment_access_rights() already marks nonpresent | |
4443 | * segment as unusable. | |
4444 | */ | |
4445 | var->present = !var->unusable; | |
6aa8b732 AK |
4446 | var->avl = (ar >> 12) & 1; |
4447 | var->l = (ar >> 13) & 1; | |
4448 | var->db = (ar >> 14) & 1; | |
4449 | var->g = (ar >> 15) & 1; | |
6aa8b732 AK |
4450 | } |
4451 | ||
a9179499 AK |
4452 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
4453 | { | |
a9179499 AK |
4454 | struct kvm_segment s; |
4455 | ||
4456 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
4457 | vmx_get_segment(vcpu, &s, seg); | |
4458 | return s.base; | |
4459 | } | |
2fb92db1 | 4460 | return vmx_read_guest_seg_base(to_vmx(vcpu), seg); |
a9179499 AK |
4461 | } |
4462 | ||
b09408d0 | 4463 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
2e4d2653 | 4464 | { |
b09408d0 MT |
4465 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4466 | ||
ae9fedc7 | 4467 | if (unlikely(vmx->rmode.vm86_active)) |
2e4d2653 | 4468 | return 0; |
ae9fedc7 PB |
4469 | else { |
4470 | int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); | |
4d283ec9 | 4471 | return VMX_AR_DPL(ar); |
69c73028 | 4472 | } |
69c73028 AK |
4473 | } |
4474 | ||
653e3108 | 4475 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 4476 | { |
6aa8b732 AK |
4477 | u32 ar; |
4478 | ||
f0495f9b | 4479 | if (var->unusable || !var->present) |
6aa8b732 AK |
4480 | ar = 1 << 16; |
4481 | else { | |
4482 | ar = var->type & 15; | |
4483 | ar |= (var->s & 1) << 4; | |
4484 | ar |= (var->dpl & 3) << 5; | |
4485 | ar |= (var->present & 1) << 7; | |
4486 | ar |= (var->avl & 1) << 12; | |
4487 | ar |= (var->l & 1) << 13; | |
4488 | ar |= (var->db & 1) << 14; | |
4489 | ar |= (var->g & 1) << 15; | |
4490 | } | |
653e3108 AK |
4491 | |
4492 | return ar; | |
4493 | } | |
4494 | ||
4495 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
4496 | struct kvm_segment *var, int seg) | |
4497 | { | |
7ffd92c5 | 4498 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
772e0318 | 4499 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
653e3108 | 4500 | |
2fb92db1 AK |
4501 | vmx_segment_cache_clear(vmx); |
4502 | ||
1ecd50a9 GN |
4503 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
4504 | vmx->rmode.segs[seg] = *var; | |
4505 | if (seg == VCPU_SREG_TR) | |
4506 | vmcs_write16(sf->selector, var->selector); | |
4507 | else if (var->s) | |
4508 | fix_rmode_seg(seg, &vmx->rmode.segs[seg]); | |
d99e4152 | 4509 | goto out; |
653e3108 | 4510 | } |
1ecd50a9 | 4511 | |
653e3108 AK |
4512 | vmcs_writel(sf->base, var->base); |
4513 | vmcs_write32(sf->limit, var->limit); | |
4514 | vmcs_write16(sf->selector, var->selector); | |
3a624e29 NK |
4515 | |
4516 | /* | |
4517 | * Fix the "Accessed" bit in AR field of segment registers for older | |
4518 | * qemu binaries. | |
4519 | * IA32 arch specifies that at the time of processor reset the | |
4520 | * "Accessed" bit in the AR field of segment registers is 1. And qemu | |
0fa06071 | 4521 | * is setting it to 0 in the userland code. This causes invalid guest |
3a624e29 NK |
4522 | * state vmexit when "unrestricted guest" mode is turned on. |
4523 | * Fix for this setup issue in cpu_reset is being pushed in the qemu | |
4524 | * tree. Newer qemu binaries with that qemu fix would not need this | |
4525 | * kvm hack. | |
4526 | */ | |
4527 | if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) | |
f924d66d | 4528 | var->type |= 0x1; /* Accessed */ |
3a624e29 | 4529 | |
f924d66d | 4530 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); |
d99e4152 GN |
4531 | |
4532 | out: | |
98eb2f8b | 4533 | vmx->emulation_required = emulation_required(vcpu); |
6aa8b732 AK |
4534 | } |
4535 | ||
6aa8b732 AK |
4536 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
4537 | { | |
2fb92db1 | 4538 | u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); |
6aa8b732 AK |
4539 | |
4540 | *db = (ar >> 14) & 1; | |
4541 | *l = (ar >> 13) & 1; | |
4542 | } | |
4543 | ||
89a27f4d | 4544 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4545 | { |
89a27f4d GN |
4546 | dt->size = vmcs_read32(GUEST_IDTR_LIMIT); |
4547 | dt->address = vmcs_readl(GUEST_IDTR_BASE); | |
6aa8b732 AK |
4548 | } |
4549 | ||
89a27f4d | 4550 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4551 | { |
89a27f4d GN |
4552 | vmcs_write32(GUEST_IDTR_LIMIT, dt->size); |
4553 | vmcs_writel(GUEST_IDTR_BASE, dt->address); | |
6aa8b732 AK |
4554 | } |
4555 | ||
89a27f4d | 4556 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4557 | { |
89a27f4d GN |
4558 | dt->size = vmcs_read32(GUEST_GDTR_LIMIT); |
4559 | dt->address = vmcs_readl(GUEST_GDTR_BASE); | |
6aa8b732 AK |
4560 | } |
4561 | ||
89a27f4d | 4562 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4563 | { |
89a27f4d GN |
4564 | vmcs_write32(GUEST_GDTR_LIMIT, dt->size); |
4565 | vmcs_writel(GUEST_GDTR_BASE, dt->address); | |
6aa8b732 AK |
4566 | } |
4567 | ||
648dfaa7 MG |
4568 | static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) |
4569 | { | |
4570 | struct kvm_segment var; | |
4571 | u32 ar; | |
4572 | ||
4573 | vmx_get_segment(vcpu, &var, seg); | |
07f42f5f | 4574 | var.dpl = 0x3; |
0647f4aa GN |
4575 | if (seg == VCPU_SREG_CS) |
4576 | var.type = 0x3; | |
648dfaa7 MG |
4577 | ar = vmx_segment_access_rights(&var); |
4578 | ||
4579 | if (var.base != (var.selector << 4)) | |
4580 | return false; | |
89efbed0 | 4581 | if (var.limit != 0xffff) |
648dfaa7 | 4582 | return false; |
07f42f5f | 4583 | if (ar != 0xf3) |
648dfaa7 MG |
4584 | return false; |
4585 | ||
4586 | return true; | |
4587 | } | |
4588 | ||
4589 | static bool code_segment_valid(struct kvm_vcpu *vcpu) | |
4590 | { | |
4591 | struct kvm_segment cs; | |
4592 | unsigned int cs_rpl; | |
4593 | ||
4594 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
b32a9918 | 4595 | cs_rpl = cs.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4596 | |
1872a3f4 AK |
4597 | if (cs.unusable) |
4598 | return false; | |
4d283ec9 | 4599 | if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) |
648dfaa7 MG |
4600 | return false; |
4601 | if (!cs.s) | |
4602 | return false; | |
4d283ec9 | 4603 | if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { |
648dfaa7 MG |
4604 | if (cs.dpl > cs_rpl) |
4605 | return false; | |
1872a3f4 | 4606 | } else { |
648dfaa7 MG |
4607 | if (cs.dpl != cs_rpl) |
4608 | return false; | |
4609 | } | |
4610 | if (!cs.present) | |
4611 | return false; | |
4612 | ||
4613 | /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ | |
4614 | return true; | |
4615 | } | |
4616 | ||
4617 | static bool stack_segment_valid(struct kvm_vcpu *vcpu) | |
4618 | { | |
4619 | struct kvm_segment ss; | |
4620 | unsigned int ss_rpl; | |
4621 | ||
4622 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
b32a9918 | 4623 | ss_rpl = ss.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4624 | |
1872a3f4 AK |
4625 | if (ss.unusable) |
4626 | return true; | |
4627 | if (ss.type != 3 && ss.type != 7) | |
648dfaa7 MG |
4628 | return false; |
4629 | if (!ss.s) | |
4630 | return false; | |
4631 | if (ss.dpl != ss_rpl) /* DPL != RPL */ | |
4632 | return false; | |
4633 | if (!ss.present) | |
4634 | return false; | |
4635 | ||
4636 | return true; | |
4637 | } | |
4638 | ||
4639 | static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) | |
4640 | { | |
4641 | struct kvm_segment var; | |
4642 | unsigned int rpl; | |
4643 | ||
4644 | vmx_get_segment(vcpu, &var, seg); | |
b32a9918 | 4645 | rpl = var.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4646 | |
1872a3f4 AK |
4647 | if (var.unusable) |
4648 | return true; | |
648dfaa7 MG |
4649 | if (!var.s) |
4650 | return false; | |
4651 | if (!var.present) | |
4652 | return false; | |
4d283ec9 | 4653 | if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { |
648dfaa7 MG |
4654 | if (var.dpl < rpl) /* DPL < RPL */ |
4655 | return false; | |
4656 | } | |
4657 | ||
4658 | /* TODO: Add other members to kvm_segment_field to allow checking for other access | |
4659 | * rights flags | |
4660 | */ | |
4661 | return true; | |
4662 | } | |
4663 | ||
4664 | static bool tr_valid(struct kvm_vcpu *vcpu) | |
4665 | { | |
4666 | struct kvm_segment tr; | |
4667 | ||
4668 | vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); | |
4669 | ||
1872a3f4 AK |
4670 | if (tr.unusable) |
4671 | return false; | |
b32a9918 | 4672 | if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 | 4673 | return false; |
1872a3f4 | 4674 | if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ |
648dfaa7 MG |
4675 | return false; |
4676 | if (!tr.present) | |
4677 | return false; | |
4678 | ||
4679 | return true; | |
4680 | } | |
4681 | ||
4682 | static bool ldtr_valid(struct kvm_vcpu *vcpu) | |
4683 | { | |
4684 | struct kvm_segment ldtr; | |
4685 | ||
4686 | vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); | |
4687 | ||
1872a3f4 AK |
4688 | if (ldtr.unusable) |
4689 | return true; | |
b32a9918 | 4690 | if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 MG |
4691 | return false; |
4692 | if (ldtr.type != 2) | |
4693 | return false; | |
4694 | if (!ldtr.present) | |
4695 | return false; | |
4696 | ||
4697 | return true; | |
4698 | } | |
4699 | ||
4700 | static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) | |
4701 | { | |
4702 | struct kvm_segment cs, ss; | |
4703 | ||
4704 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
4705 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
4706 | ||
b32a9918 NA |
4707 | return ((cs.selector & SEGMENT_RPL_MASK) == |
4708 | (ss.selector & SEGMENT_RPL_MASK)); | |
648dfaa7 MG |
4709 | } |
4710 | ||
4711 | /* | |
4712 | * Check if guest state is valid. Returns true if valid, false if | |
4713 | * not. | |
4714 | * We assume that registers are always usable | |
4715 | */ | |
4716 | static bool guest_state_valid(struct kvm_vcpu *vcpu) | |
4717 | { | |
c5e97c80 GN |
4718 | if (enable_unrestricted_guest) |
4719 | return true; | |
4720 | ||
648dfaa7 | 4721 | /* real mode guest state checks */ |
f13882d8 | 4722 | if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { |
648dfaa7 MG |
4723 | if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) |
4724 | return false; | |
4725 | if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) | |
4726 | return false; | |
4727 | if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) | |
4728 | return false; | |
4729 | if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) | |
4730 | return false; | |
4731 | if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) | |
4732 | return false; | |
4733 | if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) | |
4734 | return false; | |
4735 | } else { | |
4736 | /* protected mode guest state checks */ | |
4737 | if (!cs_ss_rpl_check(vcpu)) | |
4738 | return false; | |
4739 | if (!code_segment_valid(vcpu)) | |
4740 | return false; | |
4741 | if (!stack_segment_valid(vcpu)) | |
4742 | return false; | |
4743 | if (!data_segment_valid(vcpu, VCPU_SREG_DS)) | |
4744 | return false; | |
4745 | if (!data_segment_valid(vcpu, VCPU_SREG_ES)) | |
4746 | return false; | |
4747 | if (!data_segment_valid(vcpu, VCPU_SREG_FS)) | |
4748 | return false; | |
4749 | if (!data_segment_valid(vcpu, VCPU_SREG_GS)) | |
4750 | return false; | |
4751 | if (!tr_valid(vcpu)) | |
4752 | return false; | |
4753 | if (!ldtr_valid(vcpu)) | |
4754 | return false; | |
4755 | } | |
4756 | /* TODO: | |
4757 | * - Add checks on RIP | |
4758 | * - Add checks on RFLAGS | |
4759 | */ | |
4760 | ||
4761 | return true; | |
4762 | } | |
4763 | ||
5fa99cbe JM |
4764 | static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa) |
4765 | { | |
4766 | return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu)); | |
4767 | } | |
4768 | ||
d77c26fc | 4769 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 4770 | { |
40dcaa9f | 4771 | gfn_t fn; |
195aefde | 4772 | u16 data = 0; |
1f755a82 | 4773 | int idx, r; |
6aa8b732 | 4774 | |
40dcaa9f | 4775 | idx = srcu_read_lock(&kvm->srcu); |
4918c6ca | 4776 | fn = kvm->arch.tss_addr >> PAGE_SHIFT; |
195aefde IE |
4777 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
4778 | if (r < 0) | |
10589a46 | 4779 | goto out; |
195aefde | 4780 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
464d17c8 SY |
4781 | r = kvm_write_guest_page(kvm, fn++, &data, |
4782 | TSS_IOPB_BASE_OFFSET, sizeof(u16)); | |
195aefde | 4783 | if (r < 0) |
10589a46 | 4784 | goto out; |
195aefde IE |
4785 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
4786 | if (r < 0) | |
10589a46 | 4787 | goto out; |
195aefde IE |
4788 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
4789 | if (r < 0) | |
10589a46 | 4790 | goto out; |
195aefde | 4791 | data = ~0; |
10589a46 MT |
4792 | r = kvm_write_guest_page(kvm, fn, &data, |
4793 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
4794 | sizeof(u8)); | |
10589a46 | 4795 | out: |
40dcaa9f | 4796 | srcu_read_unlock(&kvm->srcu, idx); |
1f755a82 | 4797 | return r; |
6aa8b732 AK |
4798 | } |
4799 | ||
b7ebfb05 SY |
4800 | static int init_rmode_identity_map(struct kvm *kvm) |
4801 | { | |
f51770ed | 4802 | int i, idx, r = 0; |
ba049e93 | 4803 | kvm_pfn_t identity_map_pfn; |
b7ebfb05 SY |
4804 | u32 tmp; |
4805 | ||
a255d479 TC |
4806 | /* Protect kvm->arch.ept_identity_pagetable_done. */ |
4807 | mutex_lock(&kvm->slots_lock); | |
4808 | ||
f51770ed | 4809 | if (likely(kvm->arch.ept_identity_pagetable_done)) |
a255d479 | 4810 | goto out2; |
a255d479 | 4811 | |
d8a6e365 DH |
4812 | if (!kvm->arch.ept_identity_map_addr) |
4813 | kvm->arch.ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
b927a3ce | 4814 | identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT; |
a255d479 | 4815 | |
d8a6e365 DH |
4816 | r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, |
4817 | kvm->arch.ept_identity_map_addr, PAGE_SIZE); | |
f51770ed | 4818 | if (r < 0) |
a255d479 TC |
4819 | goto out2; |
4820 | ||
40dcaa9f | 4821 | idx = srcu_read_lock(&kvm->srcu); |
b7ebfb05 SY |
4822 | r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); |
4823 | if (r < 0) | |
4824 | goto out; | |
4825 | /* Set up identity-mapping pagetable for EPT in real mode */ | |
4826 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
4827 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
4828 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
4829 | r = kvm_write_guest_page(kvm, identity_map_pfn, | |
4830 | &tmp, i * sizeof(tmp), sizeof(tmp)); | |
4831 | if (r < 0) | |
4832 | goto out; | |
4833 | } | |
4834 | kvm->arch.ept_identity_pagetable_done = true; | |
f51770ed | 4835 | |
b7ebfb05 | 4836 | out: |
40dcaa9f | 4837 | srcu_read_unlock(&kvm->srcu, idx); |
a255d479 TC |
4838 | |
4839 | out2: | |
4840 | mutex_unlock(&kvm->slots_lock); | |
f51770ed | 4841 | return r; |
b7ebfb05 SY |
4842 | } |
4843 | ||
6aa8b732 AK |
4844 | static void seg_setup(int seg) |
4845 | { | |
772e0318 | 4846 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
3a624e29 | 4847 | unsigned int ar; |
6aa8b732 AK |
4848 | |
4849 | vmcs_write16(sf->selector, 0); | |
4850 | vmcs_writel(sf->base, 0); | |
4851 | vmcs_write32(sf->limit, 0xffff); | |
d54d07b2 GN |
4852 | ar = 0x93; |
4853 | if (seg == VCPU_SREG_CS) | |
4854 | ar |= 0x08; /* code segment */ | |
3a624e29 NK |
4855 | |
4856 | vmcs_write32(sf->ar_bytes, ar); | |
6aa8b732 AK |
4857 | } |
4858 | ||
f78e0e2e SY |
4859 | static int alloc_apic_access_page(struct kvm *kvm) |
4860 | { | |
4484141a | 4861 | struct page *page; |
f78e0e2e SY |
4862 | int r = 0; |
4863 | ||
79fac95e | 4864 | mutex_lock(&kvm->slots_lock); |
c24ae0dc | 4865 | if (kvm->arch.apic_access_page_done) |
f78e0e2e | 4866 | goto out; |
1d8007bd PB |
4867 | r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, |
4868 | APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); | |
f78e0e2e SY |
4869 | if (r) |
4870 | goto out; | |
72dc67a6 | 4871 | |
73a6d941 | 4872 | page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
4484141a XG |
4873 | if (is_error_page(page)) { |
4874 | r = -EFAULT; | |
4875 | goto out; | |
4876 | } | |
4877 | ||
c24ae0dc TC |
4878 | /* |
4879 | * Do not pin the page in memory, so that memory hot-unplug | |
4880 | * is able to migrate it. | |
4881 | */ | |
4882 | put_page(page); | |
4883 | kvm->arch.apic_access_page_done = true; | |
f78e0e2e | 4884 | out: |
79fac95e | 4885 | mutex_unlock(&kvm->slots_lock); |
f78e0e2e SY |
4886 | return r; |
4887 | } | |
4888 | ||
991e7a0e | 4889 | static int allocate_vpid(void) |
2384d2b3 SY |
4890 | { |
4891 | int vpid; | |
4892 | ||
919818ab | 4893 | if (!enable_vpid) |
991e7a0e | 4894 | return 0; |
2384d2b3 SY |
4895 | spin_lock(&vmx_vpid_lock); |
4896 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
991e7a0e | 4897 | if (vpid < VMX_NR_VPIDS) |
2384d2b3 | 4898 | __set_bit(vpid, vmx_vpid_bitmap); |
991e7a0e WL |
4899 | else |
4900 | vpid = 0; | |
2384d2b3 | 4901 | spin_unlock(&vmx_vpid_lock); |
991e7a0e | 4902 | return vpid; |
2384d2b3 SY |
4903 | } |
4904 | ||
991e7a0e | 4905 | static void free_vpid(int vpid) |
cdbecfc3 | 4906 | { |
991e7a0e | 4907 | if (!enable_vpid || vpid == 0) |
cdbecfc3 LJ |
4908 | return; |
4909 | spin_lock(&vmx_vpid_lock); | |
991e7a0e | 4910 | __clear_bit(vpid, vmx_vpid_bitmap); |
cdbecfc3 LJ |
4911 | spin_unlock(&vmx_vpid_lock); |
4912 | } | |
4913 | ||
8d14695f YZ |
4914 | #define MSR_TYPE_R 1 |
4915 | #define MSR_TYPE_W 2 | |
4916 | static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, | |
4917 | u32 msr, int type) | |
25c5f225 | 4918 | { |
3e7c73e9 | 4919 | int f = sizeof(unsigned long); |
25c5f225 SY |
4920 | |
4921 | if (!cpu_has_vmx_msr_bitmap()) | |
4922 | return; | |
4923 | ||
4924 | /* | |
4925 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
4926 | * have the write-low and read-high bitmap offsets the wrong way round. | |
4927 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
4928 | */ | |
25c5f225 | 4929 | if (msr <= 0x1fff) { |
8d14695f YZ |
4930 | if (type & MSR_TYPE_R) |
4931 | /* read-low */ | |
4932 | __clear_bit(msr, msr_bitmap + 0x000 / f); | |
4933 | ||
4934 | if (type & MSR_TYPE_W) | |
4935 | /* write-low */ | |
4936 | __clear_bit(msr, msr_bitmap + 0x800 / f); | |
4937 | ||
25c5f225 SY |
4938 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { |
4939 | msr &= 0x1fff; | |
8d14695f YZ |
4940 | if (type & MSR_TYPE_R) |
4941 | /* read-high */ | |
4942 | __clear_bit(msr, msr_bitmap + 0x400 / f); | |
4943 | ||
4944 | if (type & MSR_TYPE_W) | |
4945 | /* write-high */ | |
4946 | __clear_bit(msr, msr_bitmap + 0xc00 / f); | |
4947 | ||
4948 | } | |
4949 | } | |
4950 | ||
f2b93280 WV |
4951 | /* |
4952 | * If a msr is allowed by L0, we should check whether it is allowed by L1. | |
4953 | * The corresponding bit will be cleared unless both of L0 and L1 allow it. | |
4954 | */ | |
4955 | static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1, | |
4956 | unsigned long *msr_bitmap_nested, | |
4957 | u32 msr, int type) | |
4958 | { | |
4959 | int f = sizeof(unsigned long); | |
4960 | ||
4961 | if (!cpu_has_vmx_msr_bitmap()) { | |
4962 | WARN_ON(1); | |
4963 | return; | |
4964 | } | |
4965 | ||
4966 | /* | |
4967 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
4968 | * have the write-low and read-high bitmap offsets the wrong way round. | |
4969 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
4970 | */ | |
4971 | if (msr <= 0x1fff) { | |
4972 | if (type & MSR_TYPE_R && | |
4973 | !test_bit(msr, msr_bitmap_l1 + 0x000 / f)) | |
4974 | /* read-low */ | |
4975 | __clear_bit(msr, msr_bitmap_nested + 0x000 / f); | |
4976 | ||
4977 | if (type & MSR_TYPE_W && | |
4978 | !test_bit(msr, msr_bitmap_l1 + 0x800 / f)) | |
4979 | /* write-low */ | |
4980 | __clear_bit(msr, msr_bitmap_nested + 0x800 / f); | |
4981 | ||
4982 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
4983 | msr &= 0x1fff; | |
4984 | if (type & MSR_TYPE_R && | |
4985 | !test_bit(msr, msr_bitmap_l1 + 0x400 / f)) | |
4986 | /* read-high */ | |
4987 | __clear_bit(msr, msr_bitmap_nested + 0x400 / f); | |
4988 | ||
4989 | if (type & MSR_TYPE_W && | |
4990 | !test_bit(msr, msr_bitmap_l1 + 0xc00 / f)) | |
4991 | /* write-high */ | |
4992 | __clear_bit(msr, msr_bitmap_nested + 0xc00 / f); | |
4993 | ||
4994 | } | |
4995 | } | |
4996 | ||
5897297b AK |
4997 | static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only) |
4998 | { | |
4999 | if (!longmode_only) | |
8d14695f YZ |
5000 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, |
5001 | msr, MSR_TYPE_R | MSR_TYPE_W); | |
5002 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, | |
5003 | msr, MSR_TYPE_R | MSR_TYPE_W); | |
5004 | } | |
5005 | ||
2e69f865 | 5006 | static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active) |
8d14695f | 5007 | { |
f6e90f9e | 5008 | if (apicv_active) { |
c63e4563 | 5009 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv, |
2e69f865 | 5010 | msr, type); |
c63e4563 | 5011 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv, |
2e69f865 | 5012 | msr, type); |
f6e90f9e | 5013 | } else { |
f6e90f9e | 5014 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic, |
2e69f865 | 5015 | msr, type); |
f6e90f9e | 5016 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic, |
2e69f865 | 5017 | msr, type); |
f6e90f9e | 5018 | } |
5897297b AK |
5019 | } |
5020 | ||
b2a05fef | 5021 | static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu) |
d50ab6c1 | 5022 | { |
d62caabb | 5023 | return enable_apicv; |
d50ab6c1 PB |
5024 | } |
5025 | ||
c9f04407 DM |
5026 | static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu) |
5027 | { | |
5028 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
5029 | gfn_t gfn; | |
5030 | ||
5031 | /* | |
5032 | * Don't need to mark the APIC access page dirty; it is never | |
5033 | * written to by the CPU during APIC virtualization. | |
5034 | */ | |
5035 | ||
5036 | if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { | |
5037 | gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT; | |
5038 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
5039 | } | |
5040 | ||
5041 | if (nested_cpu_has_posted_intr(vmcs12)) { | |
5042 | gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT; | |
5043 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
5044 | } | |
5045 | } | |
5046 | ||
5047 | ||
6342c50a | 5048 | static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu) |
705699a1 WV |
5049 | { |
5050 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5051 | int max_irr; | |
5052 | void *vapic_page; | |
5053 | u16 status; | |
5054 | ||
c9f04407 DM |
5055 | if (!vmx->nested.pi_desc || !vmx->nested.pi_pending) |
5056 | return; | |
705699a1 | 5057 | |
c9f04407 DM |
5058 | vmx->nested.pi_pending = false; |
5059 | if (!pi_test_and_clear_on(vmx->nested.pi_desc)) | |
5060 | return; | |
705699a1 | 5061 | |
c9f04407 DM |
5062 | max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256); |
5063 | if (max_irr != 256) { | |
705699a1 | 5064 | vapic_page = kmap(vmx->nested.virtual_apic_page); |
705699a1 WV |
5065 | __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page); |
5066 | kunmap(vmx->nested.virtual_apic_page); | |
5067 | ||
5068 | status = vmcs_read16(GUEST_INTR_STATUS); | |
5069 | if ((u8)max_irr > ((u8)status & 0xff)) { | |
5070 | status &= ~0xff; | |
5071 | status |= (u8)max_irr; | |
5072 | vmcs_write16(GUEST_INTR_STATUS, status); | |
5073 | } | |
5074 | } | |
c9f04407 DM |
5075 | |
5076 | nested_mark_vmcs12_pages_dirty(vcpu); | |
705699a1 WV |
5077 | } |
5078 | ||
06a5524f WV |
5079 | static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu, |
5080 | bool nested) | |
21bc8dc5 RK |
5081 | { |
5082 | #ifdef CONFIG_SMP | |
06a5524f WV |
5083 | int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR; |
5084 | ||
21bc8dc5 | 5085 | if (vcpu->mode == IN_GUEST_MODE) { |
28b835d6 | 5086 | /* |
5753743f HZ |
5087 | * The vector of interrupt to be delivered to vcpu had |
5088 | * been set in PIR before this function. | |
5089 | * | |
5090 | * Following cases will be reached in this block, and | |
5091 | * we always send a notification event in all cases as | |
5092 | * explained below. | |
5093 | * | |
5094 | * Case 1: vcpu keeps in non-root mode. Sending a | |
5095 | * notification event posts the interrupt to vcpu. | |
5096 | * | |
5097 | * Case 2: vcpu exits to root mode and is still | |
5098 | * runnable. PIR will be synced to vIRR before the | |
5099 | * next vcpu entry. Sending a notification event in | |
5100 | * this case has no effect, as vcpu is not in root | |
5101 | * mode. | |
28b835d6 | 5102 | * |
5753743f HZ |
5103 | * Case 3: vcpu exits to root mode and is blocked. |
5104 | * vcpu_block() has already synced PIR to vIRR and | |
5105 | * never blocks vcpu if vIRR is not cleared. Therefore, | |
5106 | * a blocked vcpu here does not wait for any requested | |
5107 | * interrupts in PIR, and sending a notification event | |
5108 | * which has no effect is safe here. | |
28b835d6 | 5109 | */ |
28b835d6 | 5110 | |
06a5524f | 5111 | apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); |
21bc8dc5 RK |
5112 | return true; |
5113 | } | |
5114 | #endif | |
5115 | return false; | |
5116 | } | |
5117 | ||
705699a1 WV |
5118 | static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, |
5119 | int vector) | |
5120 | { | |
5121 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5122 | ||
5123 | if (is_guest_mode(vcpu) && | |
5124 | vector == vmx->nested.posted_intr_nv) { | |
5125 | /* the PIR and ON have been set by L1. */ | |
06a5524f | 5126 | kvm_vcpu_trigger_posted_interrupt(vcpu, true); |
705699a1 WV |
5127 | /* |
5128 | * If a posted intr is not recognized by hardware, | |
5129 | * we will accomplish it in the next vmentry. | |
5130 | */ | |
5131 | vmx->nested.pi_pending = true; | |
5132 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
5133 | return 0; | |
5134 | } | |
5135 | return -1; | |
5136 | } | |
a20ed54d YZ |
5137 | /* |
5138 | * Send interrupt to vcpu via posted interrupt way. | |
5139 | * 1. If target vcpu is running(non-root mode), send posted interrupt | |
5140 | * notification to vcpu and hardware will sync PIR to vIRR atomically. | |
5141 | * 2. If target vcpu isn't running(root mode), kick it to pick up the | |
5142 | * interrupt from PIR in next vmentry. | |
5143 | */ | |
5144 | static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) | |
5145 | { | |
5146 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5147 | int r; | |
5148 | ||
705699a1 WV |
5149 | r = vmx_deliver_nested_posted_interrupt(vcpu, vector); |
5150 | if (!r) | |
5151 | return; | |
5152 | ||
a20ed54d YZ |
5153 | if (pi_test_and_set_pir(vector, &vmx->pi_desc)) |
5154 | return; | |
5155 | ||
b95234c8 PB |
5156 | /* If a previous notification has sent the IPI, nothing to do. */ |
5157 | if (pi_test_and_set_on(&vmx->pi_desc)) | |
5158 | return; | |
5159 | ||
06a5524f | 5160 | if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false)) |
a20ed54d YZ |
5161 | kvm_vcpu_kick(vcpu); |
5162 | } | |
5163 | ||
a3a8ff8e NHE |
5164 | /* |
5165 | * Set up the vmcs's constant host-state fields, i.e., host-state fields that | |
5166 | * will not change in the lifetime of the guest. | |
5167 | * Note that host-state that does change is set elsewhere. E.g., host-state | |
5168 | * that is set differently for each CPU is set in vmx_vcpu_load(), not here. | |
5169 | */ | |
a547c6db | 5170 | static void vmx_set_constant_host_state(struct vcpu_vmx *vmx) |
a3a8ff8e NHE |
5171 | { |
5172 | u32 low32, high32; | |
5173 | unsigned long tmpl; | |
5174 | struct desc_ptr dt; | |
d6e41f11 | 5175 | unsigned long cr0, cr3, cr4; |
a3a8ff8e | 5176 | |
04ac88ab AL |
5177 | cr0 = read_cr0(); |
5178 | WARN_ON(cr0 & X86_CR0_TS); | |
5179 | vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */ | |
d6e41f11 AL |
5180 | |
5181 | /* | |
5182 | * Save the most likely value for this task's CR3 in the VMCS. | |
5183 | * We can't use __get_current_cr3_fast() because we're not atomic. | |
5184 | */ | |
6c690ee1 | 5185 | cr3 = __read_cr3(); |
d6e41f11 | 5186 | vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */ |
44889942 | 5187 | vmx->loaded_vmcs->vmcs_host_cr3 = cr3; |
a3a8ff8e | 5188 | |
d974baa3 | 5189 | /* Save the most likely value for this task's CR4 in the VMCS. */ |
1e02ce4c | 5190 | cr4 = cr4_read_shadow(); |
d974baa3 | 5191 | vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ |
44889942 | 5192 | vmx->loaded_vmcs->vmcs_host_cr4 = cr4; |
d974baa3 | 5193 | |
a3a8ff8e | 5194 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ |
b2da15ac AK |
5195 | #ifdef CONFIG_X86_64 |
5196 | /* | |
5197 | * Load null selectors, so we can avoid reloading them in | |
5198 | * __vmx_load_host_state(), in case userspace uses the null selectors | |
5199 | * too (the expected case). | |
5200 | */ | |
5201 | vmcs_write16(HOST_DS_SELECTOR, 0); | |
5202 | vmcs_write16(HOST_ES_SELECTOR, 0); | |
5203 | #else | |
a3a8ff8e NHE |
5204 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
5205 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
b2da15ac | 5206 | #endif |
a3a8ff8e NHE |
5207 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
5208 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
5209 | ||
87930019 | 5210 | store_idt(&dt); |
a3a8ff8e | 5211 | vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */ |
a547c6db | 5212 | vmx->host_idt_base = dt.address; |
a3a8ff8e | 5213 | |
83287ea4 | 5214 | vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */ |
a3a8ff8e NHE |
5215 | |
5216 | rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); | |
5217 | vmcs_write32(HOST_IA32_SYSENTER_CS, low32); | |
5218 | rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); | |
5219 | vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ | |
5220 | ||
5221 | if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { | |
5222 | rdmsr(MSR_IA32_CR_PAT, low32, high32); | |
5223 | vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); | |
5224 | } | |
5225 | } | |
5226 | ||
bf8179a0 NHE |
5227 | static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) |
5228 | { | |
5229 | vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; | |
5230 | if (enable_ept) | |
5231 | vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; | |
fe3ef05c NHE |
5232 | if (is_guest_mode(&vmx->vcpu)) |
5233 | vmx->vcpu.arch.cr4_guest_owned_bits &= | |
5234 | ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; | |
bf8179a0 NHE |
5235 | vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); |
5236 | } | |
5237 | ||
01e439be YZ |
5238 | static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) |
5239 | { | |
5240 | u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; | |
5241 | ||
d62caabb | 5242 | if (!kvm_vcpu_apicv_active(&vmx->vcpu)) |
01e439be | 5243 | pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; |
d02fcf50 PB |
5244 | |
5245 | if (!enable_vnmi) | |
5246 | pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS; | |
5247 | ||
64672c95 YJ |
5248 | /* Enable the preemption timer dynamically */ |
5249 | pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be YZ |
5250 | return pin_based_exec_ctrl; |
5251 | } | |
5252 | ||
d62caabb AS |
5253 | static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) |
5254 | { | |
5255 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5256 | ||
5257 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); | |
3ce424e4 RK |
5258 | if (cpu_has_secondary_exec_ctrls()) { |
5259 | if (kvm_vcpu_apicv_active(vcpu)) | |
5260 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
5261 | SECONDARY_EXEC_APIC_REGISTER_VIRT | | |
5262 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
5263 | else | |
5264 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, | |
5265 | SECONDARY_EXEC_APIC_REGISTER_VIRT | | |
5266 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
5267 | } | |
5268 | ||
5269 | if (cpu_has_vmx_msr_bitmap()) | |
5270 | vmx_set_msr_bitmap(vcpu); | |
d62caabb AS |
5271 | } |
5272 | ||
bf8179a0 NHE |
5273 | static u32 vmx_exec_control(struct vcpu_vmx *vmx) |
5274 | { | |
5275 | u32 exec_control = vmcs_config.cpu_based_exec_ctrl; | |
d16c293e PB |
5276 | |
5277 | if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) | |
5278 | exec_control &= ~CPU_BASED_MOV_DR_EXITING; | |
5279 | ||
35754c98 | 5280 | if (!cpu_need_tpr_shadow(&vmx->vcpu)) { |
bf8179a0 NHE |
5281 | exec_control &= ~CPU_BASED_TPR_SHADOW; |
5282 | #ifdef CONFIG_X86_64 | |
5283 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
5284 | CPU_BASED_CR8_LOAD_EXITING; | |
5285 | #endif | |
5286 | } | |
5287 | if (!enable_ept) | |
5288 | exec_control |= CPU_BASED_CR3_STORE_EXITING | | |
5289 | CPU_BASED_CR3_LOAD_EXITING | | |
5290 | CPU_BASED_INVLPG_EXITING; | |
5291 | return exec_control; | |
5292 | } | |
5293 | ||
45ec368c | 5294 | static bool vmx_rdrand_supported(void) |
bf8179a0 | 5295 | { |
45ec368c | 5296 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
736fdf72 | 5297 | SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c JM |
5298 | } |
5299 | ||
75f4fc8d JM |
5300 | static bool vmx_rdseed_supported(void) |
5301 | { | |
5302 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
736fdf72 | 5303 | SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d JM |
5304 | } |
5305 | ||
80154d77 | 5306 | static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) |
bf8179a0 | 5307 | { |
80154d77 PB |
5308 | struct kvm_vcpu *vcpu = &vmx->vcpu; |
5309 | ||
bf8179a0 | 5310 | u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; |
80154d77 | 5311 | if (!cpu_need_virtualize_apic_accesses(vcpu)) |
bf8179a0 NHE |
5312 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; |
5313 | if (vmx->vpid == 0) | |
5314 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
5315 | if (!enable_ept) { | |
5316 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; | |
5317 | enable_unrestricted_guest = 0; | |
ad756a16 MJ |
5318 | /* Enable INVPCID for non-ept guests may cause performance regression. */ |
5319 | exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; | |
bf8179a0 NHE |
5320 | } |
5321 | if (!enable_unrestricted_guest) | |
5322 | exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
5323 | if (!ple_gap) | |
5324 | exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
80154d77 | 5325 | if (!kvm_vcpu_apicv_active(vcpu)) |
c7c9c56c YZ |
5326 | exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | |
5327 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
8d14695f | 5328 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; |
abc4fc58 AG |
5329 | /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD |
5330 | (handle_vmptrld). | |
5331 | We can NOT enable shadow_vmcs here because we don't have yet | |
5332 | a current VMCS12 | |
5333 | */ | |
5334 | exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; | |
a3eaa864 KH |
5335 | |
5336 | if (!enable_pml) | |
5337 | exec_control &= ~SECONDARY_EXEC_ENABLE_PML; | |
843e4330 | 5338 | |
3db13480 PB |
5339 | if (vmx_xsaves_supported()) { |
5340 | /* Exposing XSAVES only when XSAVE is exposed */ | |
5341 | bool xsaves_enabled = | |
5342 | guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && | |
5343 | guest_cpuid_has(vcpu, X86_FEATURE_XSAVES); | |
5344 | ||
5345 | if (!xsaves_enabled) | |
5346 | exec_control &= ~SECONDARY_EXEC_XSAVES; | |
5347 | ||
5348 | if (nested) { | |
5349 | if (xsaves_enabled) | |
5350 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
5351 | SECONDARY_EXEC_XSAVES; | |
5352 | else | |
5353 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
5354 | ~SECONDARY_EXEC_XSAVES; | |
5355 | } | |
5356 | } | |
5357 | ||
80154d77 PB |
5358 | if (vmx_rdtscp_supported()) { |
5359 | bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP); | |
5360 | if (!rdtscp_enabled) | |
5361 | exec_control &= ~SECONDARY_EXEC_RDTSCP; | |
5362 | ||
5363 | if (nested) { | |
5364 | if (rdtscp_enabled) | |
5365 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
5366 | SECONDARY_EXEC_RDTSCP; | |
5367 | else | |
5368 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
5369 | ~SECONDARY_EXEC_RDTSCP; | |
5370 | } | |
5371 | } | |
5372 | ||
5373 | if (vmx_invpcid_supported()) { | |
5374 | /* Exposing INVPCID only when PCID is exposed */ | |
5375 | bool invpcid_enabled = | |
5376 | guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) && | |
5377 | guest_cpuid_has(vcpu, X86_FEATURE_PCID); | |
5378 | ||
5379 | if (!invpcid_enabled) { | |
5380 | exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; | |
5381 | guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID); | |
5382 | } | |
5383 | ||
5384 | if (nested) { | |
5385 | if (invpcid_enabled) | |
5386 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
5387 | SECONDARY_EXEC_ENABLE_INVPCID; | |
5388 | else | |
5389 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
5390 | ~SECONDARY_EXEC_ENABLE_INVPCID; | |
5391 | } | |
5392 | } | |
5393 | ||
45ec368c JM |
5394 | if (vmx_rdrand_supported()) { |
5395 | bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND); | |
5396 | if (rdrand_enabled) | |
736fdf72 | 5397 | exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c JM |
5398 | |
5399 | if (nested) { | |
5400 | if (rdrand_enabled) | |
5401 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
736fdf72 | 5402 | SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c JM |
5403 | else |
5404 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
736fdf72 | 5405 | ~SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c JM |
5406 | } |
5407 | } | |
5408 | ||
75f4fc8d JM |
5409 | if (vmx_rdseed_supported()) { |
5410 | bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED); | |
5411 | if (rdseed_enabled) | |
736fdf72 | 5412 | exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d JM |
5413 | |
5414 | if (nested) { | |
5415 | if (rdseed_enabled) | |
5416 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
736fdf72 | 5417 | SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d JM |
5418 | else |
5419 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
736fdf72 | 5420 | ~SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d JM |
5421 | } |
5422 | } | |
5423 | ||
80154d77 | 5424 | vmx->secondary_exec_control = exec_control; |
bf8179a0 NHE |
5425 | } |
5426 | ||
ce88decf XG |
5427 | static void ept_set_mmio_spte_mask(void) |
5428 | { | |
5429 | /* | |
5430 | * EPT Misconfigurations can be generated if the value of bits 2:0 | |
5431 | * of an EPT paging-structure entry is 110b (write/execute). | |
ce88decf | 5432 | */ |
dcdca5fe PF |
5433 | kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK, |
5434 | VMX_EPT_MISCONFIG_WX_VALUE); | |
ce88decf XG |
5435 | } |
5436 | ||
f53cd63c | 5437 | #define VMX_XSS_EXIT_BITMAP 0 |
6aa8b732 AK |
5438 | /* |
5439 | * Sets up the vmcs for emulated real mode. | |
5440 | */ | |
12d79917 | 5441 | static void vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 | 5442 | { |
2e4ce7f5 | 5443 | #ifdef CONFIG_X86_64 |
6aa8b732 | 5444 | unsigned long a; |
2e4ce7f5 | 5445 | #endif |
6aa8b732 | 5446 | int i; |
6aa8b732 | 5447 | |
6aa8b732 | 5448 | /* I/O */ |
3e7c73e9 AK |
5449 | vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a)); |
5450 | vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b)); | |
6aa8b732 | 5451 | |
4607c2d7 AG |
5452 | if (enable_shadow_vmcs) { |
5453 | vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap)); | |
5454 | vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap)); | |
5455 | } | |
25c5f225 | 5456 | if (cpu_has_vmx_msr_bitmap()) |
5897297b | 5457 | vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy)); |
25c5f225 | 5458 | |
6aa8b732 AK |
5459 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
5460 | ||
6aa8b732 | 5461 | /* Control */ |
01e439be | 5462 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); |
64672c95 | 5463 | vmx->hv_deadline_tsc = -1; |
6e5d865c | 5464 | |
bf8179a0 | 5465 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx)); |
6aa8b732 | 5466 | |
dfa169bb | 5467 | if (cpu_has_secondary_exec_ctrls()) { |
80154d77 | 5468 | vmx_compute_secondary_exec_control(vmx); |
bf8179a0 | 5469 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, |
80154d77 | 5470 | vmx->secondary_exec_control); |
dfa169bb | 5471 | } |
f78e0e2e | 5472 | |
d62caabb | 5473 | if (kvm_vcpu_apicv_active(&vmx->vcpu)) { |
c7c9c56c YZ |
5474 | vmcs_write64(EOI_EXIT_BITMAP0, 0); |
5475 | vmcs_write64(EOI_EXIT_BITMAP1, 0); | |
5476 | vmcs_write64(EOI_EXIT_BITMAP2, 0); | |
5477 | vmcs_write64(EOI_EXIT_BITMAP3, 0); | |
5478 | ||
5479 | vmcs_write16(GUEST_INTR_STATUS, 0); | |
01e439be | 5480 | |
0bcf261c | 5481 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); |
01e439be | 5482 | vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); |
c7c9c56c YZ |
5483 | } |
5484 | ||
4b8d54f9 ZE |
5485 | if (ple_gap) { |
5486 | vmcs_write32(PLE_GAP, ple_gap); | |
a7653ecd RK |
5487 | vmx->ple_window = ple_window; |
5488 | vmx->ple_window_dirty = true; | |
4b8d54f9 ZE |
5489 | } |
5490 | ||
c3707958 XG |
5491 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); |
5492 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); | |
6aa8b732 AK |
5493 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
5494 | ||
9581d442 AK |
5495 | vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ |
5496 | vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ | |
a547c6db | 5497 | vmx_set_constant_host_state(vmx); |
05b3e0c2 | 5498 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
5499 | rdmsrl(MSR_FS_BASE, a); |
5500 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
5501 | rdmsrl(MSR_GS_BASE, a); | |
5502 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
5503 | #else | |
5504 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
5505 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
5506 | #endif | |
5507 | ||
2a499e49 BD |
5508 | if (cpu_has_vmx_vmfunc()) |
5509 | vmcs_write64(VM_FUNCTION_CONTROL, 0); | |
5510 | ||
2cc51560 ED |
5511 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
5512 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
61d2ef2c | 5513 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host)); |
2cc51560 | 5514 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); |
61d2ef2c | 5515 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest)); |
6aa8b732 | 5516 | |
74545705 RK |
5517 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) |
5518 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); | |
468d472f | 5519 | |
03916db9 | 5520 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { |
6aa8b732 AK |
5521 | u32 index = vmx_msr_index[i]; |
5522 | u32 data_low, data_high; | |
a2fa3e9f | 5523 | int j = vmx->nmsrs; |
6aa8b732 AK |
5524 | |
5525 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
5526 | continue; | |
432bd6cb AK |
5527 | if (wrmsr_safe(index, data_low, data_high) < 0) |
5528 | continue; | |
26bb0981 AK |
5529 | vmx->guest_msrs[j].index = i; |
5530 | vmx->guest_msrs[j].data = 0; | |
d5696725 | 5531 | vmx->guest_msrs[j].mask = -1ull; |
a2fa3e9f | 5532 | ++vmx->nmsrs; |
6aa8b732 | 5533 | } |
6aa8b732 | 5534 | |
2961e876 GN |
5535 | |
5536 | vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl); | |
6aa8b732 AK |
5537 | |
5538 | /* 22.2.1, 20.8.1 */ | |
2961e876 | 5539 | vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl); |
1c3d14fe | 5540 | |
bd7e5b08 PB |
5541 | vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS; |
5542 | vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS); | |
5543 | ||
bf8179a0 | 5544 | set_cr4_guest_host_mask(vmx); |
e00c8cf2 | 5545 | |
f53cd63c WL |
5546 | if (vmx_xsaves_supported()) |
5547 | vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); | |
5548 | ||
4e59516a PF |
5549 | if (enable_pml) { |
5550 | ASSERT(vmx->pml_pg); | |
5551 | vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); | |
5552 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
5553 | } | |
e00c8cf2 AK |
5554 | } |
5555 | ||
d28bc9dd | 5556 | static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e00c8cf2 AK |
5557 | { |
5558 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
58cb628d | 5559 | struct msr_data apic_base_msr; |
d28bc9dd | 5560 | u64 cr0; |
e00c8cf2 | 5561 | |
7ffd92c5 | 5562 | vmx->rmode.vm86_active = 0; |
e00c8cf2 | 5563 | |
ad312c7c | 5564 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
d28bc9dd NA |
5565 | kvm_set_cr8(vcpu, 0); |
5566 | ||
5567 | if (!init_event) { | |
5568 | apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | | |
5569 | MSR_IA32_APICBASE_ENABLE; | |
5570 | if (kvm_vcpu_is_reset_bsp(vcpu)) | |
5571 | apic_base_msr.data |= MSR_IA32_APICBASE_BSP; | |
5572 | apic_base_msr.host_initiated = true; | |
5573 | kvm_set_apic_base(vcpu, &apic_base_msr); | |
5574 | } | |
e00c8cf2 | 5575 | |
2fb92db1 AK |
5576 | vmx_segment_cache_clear(vmx); |
5577 | ||
5706be0d | 5578 | seg_setup(VCPU_SREG_CS); |
66450a21 | 5579 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); |
f3531054 | 5580 | vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); |
e00c8cf2 AK |
5581 | |
5582 | seg_setup(VCPU_SREG_DS); | |
5583 | seg_setup(VCPU_SREG_ES); | |
5584 | seg_setup(VCPU_SREG_FS); | |
5585 | seg_setup(VCPU_SREG_GS); | |
5586 | seg_setup(VCPU_SREG_SS); | |
5587 | ||
5588 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
5589 | vmcs_writel(GUEST_TR_BASE, 0); | |
5590 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
5591 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
5592 | ||
5593 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
5594 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
5595 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
5596 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
5597 | ||
d28bc9dd NA |
5598 | if (!init_event) { |
5599 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
5600 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
5601 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
5602 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
5603 | } | |
e00c8cf2 | 5604 | |
c37c2873 | 5605 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); |
66450a21 | 5606 | kvm_rip_write(vcpu, 0xfff0); |
e00c8cf2 | 5607 | |
e00c8cf2 AK |
5608 | vmcs_writel(GUEST_GDTR_BASE, 0); |
5609 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
5610 | ||
5611 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
5612 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
5613 | ||
443381a8 | 5614 | vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); |
e00c8cf2 | 5615 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); |
f3531054 | 5616 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); |
a554d207 WL |
5617 | if (kvm_mpx_supported()) |
5618 | vmcs_write64(GUEST_BNDCFGS, 0); | |
e00c8cf2 | 5619 | |
e00c8cf2 AK |
5620 | setup_msrs(vmx); |
5621 | ||
6aa8b732 AK |
5622 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
5623 | ||
d28bc9dd | 5624 | if (cpu_has_vmx_tpr_shadow() && !init_event) { |
f78e0e2e | 5625 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); |
35754c98 | 5626 | if (cpu_need_tpr_shadow(vcpu)) |
f78e0e2e | 5627 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, |
d28bc9dd | 5628 | __pa(vcpu->arch.apic->regs)); |
f78e0e2e SY |
5629 | vmcs_write32(TPR_THRESHOLD, 0); |
5630 | } | |
5631 | ||
a73896cb | 5632 | kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); |
6aa8b732 | 5633 | |
2384d2b3 SY |
5634 | if (vmx->vpid != 0) |
5635 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
5636 | ||
d28bc9dd | 5637 | cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; |
d28bc9dd | 5638 | vmx->vcpu.arch.cr0 = cr0; |
f2463247 | 5639 | vmx_set_cr0(vcpu, cr0); /* enter rmode */ |
d28bc9dd | 5640 | vmx_set_cr4(vcpu, 0); |
5690891b | 5641 | vmx_set_efer(vcpu, 0); |
bd7e5b08 | 5642 | |
d28bc9dd | 5643 | update_exception_bitmap(vcpu); |
6aa8b732 | 5644 | |
dd5f5341 | 5645 | vpid_sync_context(vmx->vpid); |
6aa8b732 AK |
5646 | } |
5647 | ||
b6f1250e NHE |
5648 | /* |
5649 | * In nested virtualization, check if L1 asked to exit on external interrupts. | |
5650 | * For most existing hypervisors, this will always return true. | |
5651 | */ | |
5652 | static bool nested_exit_on_intr(struct kvm_vcpu *vcpu) | |
5653 | { | |
5654 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
5655 | PIN_BASED_EXT_INTR_MASK; | |
5656 | } | |
5657 | ||
77b0f5d6 BD |
5658 | /* |
5659 | * In nested virtualization, check if L1 has set | |
5660 | * VM_EXIT_ACK_INTR_ON_EXIT | |
5661 | */ | |
5662 | static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu) | |
5663 | { | |
5664 | return get_vmcs12(vcpu)->vm_exit_controls & | |
5665 | VM_EXIT_ACK_INTR_ON_EXIT; | |
5666 | } | |
5667 | ||
ea8ceb83 JK |
5668 | static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu) |
5669 | { | |
5670 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
5671 | PIN_BASED_NMI_EXITING; | |
5672 | } | |
5673 | ||
c9a7953f | 5674 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
3b86cd99 | 5675 | { |
47c0152e PB |
5676 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, |
5677 | CPU_BASED_VIRTUAL_INTR_PENDING); | |
3b86cd99 JK |
5678 | } |
5679 | ||
c9a7953f | 5680 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
3b86cd99 | 5681 | { |
d02fcf50 | 5682 | if (!enable_vnmi || |
8a1b4392 | 5683 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { |
c9a7953f JK |
5684 | enable_irq_window(vcpu); |
5685 | return; | |
5686 | } | |
3b86cd99 | 5687 | |
47c0152e PB |
5688 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, |
5689 | CPU_BASED_VIRTUAL_NMI_PENDING); | |
3b86cd99 JK |
5690 | } |
5691 | ||
66fd3f7f | 5692 | static void vmx_inject_irq(struct kvm_vcpu *vcpu) |
85f455f7 | 5693 | { |
9c8cba37 | 5694 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
66fd3f7f GN |
5695 | uint32_t intr; |
5696 | int irq = vcpu->arch.interrupt.nr; | |
9c8cba37 | 5697 | |
229456fc | 5698 | trace_kvm_inj_virq(irq); |
2714d1d3 | 5699 | |
fa89a817 | 5700 | ++vcpu->stat.irq_injections; |
7ffd92c5 | 5701 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
5702 | int inc_eip = 0; |
5703 | if (vcpu->arch.interrupt.soft) | |
5704 | inc_eip = vcpu->arch.event_exit_inst_len; | |
5705 | if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE) | |
a92601bb | 5706 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
85f455f7 ED |
5707 | return; |
5708 | } | |
66fd3f7f GN |
5709 | intr = irq | INTR_INFO_VALID_MASK; |
5710 | if (vcpu->arch.interrupt.soft) { | |
5711 | intr |= INTR_TYPE_SOFT_INTR; | |
5712 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
5713 | vmx->vcpu.arch.event_exit_inst_len); | |
5714 | } else | |
5715 | intr |= INTR_TYPE_EXT_INTR; | |
5716 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); | |
85f455f7 ED |
5717 | } |
5718 | ||
f08864b4 SY |
5719 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
5720 | { | |
66a5a347 JK |
5721 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
5722 | ||
d02fcf50 | 5723 | if (!enable_vnmi) { |
8a1b4392 PB |
5724 | /* |
5725 | * Tracking the NMI-blocked state in software is built upon | |
5726 | * finding the next open IRQ window. This, in turn, depends on | |
5727 | * well-behaving guests: They have to keep IRQs disabled at | |
5728 | * least as long as the NMI handler runs. Otherwise we may | |
5729 | * cause NMI nesting, maybe breaking the guest. But as this is | |
5730 | * highly unlikely, we can live with the residual risk. | |
5731 | */ | |
5732 | vmx->loaded_vmcs->soft_vnmi_blocked = 1; | |
5733 | vmx->loaded_vmcs->vnmi_blocked_time = 0; | |
5734 | } | |
5735 | ||
4c4a6f79 PB |
5736 | ++vcpu->stat.nmi_injections; |
5737 | vmx->loaded_vmcs->nmi_known_unmasked = false; | |
3b86cd99 | 5738 | |
7ffd92c5 | 5739 | if (vmx->rmode.vm86_active) { |
71f9833b | 5740 | if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE) |
a92601bb | 5741 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
66a5a347 JK |
5742 | return; |
5743 | } | |
c5a6d5f7 | 5744 | |
f08864b4 SY |
5745 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
5746 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | |
f08864b4 SY |
5747 | } |
5748 | ||
3cfc3092 JK |
5749 | static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) |
5750 | { | |
4c4a6f79 PB |
5751 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
5752 | bool masked; | |
5753 | ||
d02fcf50 | 5754 | if (!enable_vnmi) |
8a1b4392 | 5755 | return vmx->loaded_vmcs->soft_vnmi_blocked; |
4c4a6f79 | 5756 | if (vmx->loaded_vmcs->nmi_known_unmasked) |
9d58b931 | 5757 | return false; |
4c4a6f79 PB |
5758 | masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; |
5759 | vmx->loaded_vmcs->nmi_known_unmasked = !masked; | |
5760 | return masked; | |
3cfc3092 JK |
5761 | } |
5762 | ||
5763 | static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
5764 | { | |
5765 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5766 | ||
d02fcf50 | 5767 | if (!enable_vnmi) { |
8a1b4392 PB |
5768 | if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) { |
5769 | vmx->loaded_vmcs->soft_vnmi_blocked = masked; | |
5770 | vmx->loaded_vmcs->vnmi_blocked_time = 0; | |
5771 | } | |
5772 | } else { | |
5773 | vmx->loaded_vmcs->nmi_known_unmasked = !masked; | |
5774 | if (masked) | |
5775 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
5776 | GUEST_INTR_STATE_NMI); | |
5777 | else | |
5778 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
5779 | GUEST_INTR_STATE_NMI); | |
5780 | } | |
3cfc3092 JK |
5781 | } |
5782 | ||
2505dc9f JK |
5783 | static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) |
5784 | { | |
b6b8a145 JK |
5785 | if (to_vmx(vcpu)->nested.nested_run_pending) |
5786 | return 0; | |
ea8ceb83 | 5787 | |
d02fcf50 | 5788 | if (!enable_vnmi && |
8a1b4392 PB |
5789 | to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked) |
5790 | return 0; | |
5791 | ||
2505dc9f JK |
5792 | return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
5793 | (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI | |
5794 | | GUEST_INTR_STATE_NMI)); | |
5795 | } | |
5796 | ||
78646121 GN |
5797 | static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) |
5798 | { | |
b6b8a145 JK |
5799 | return (!to_vmx(vcpu)->nested.nested_run_pending && |
5800 | vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
c4282df9 GN |
5801 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
5802 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); | |
78646121 GN |
5803 | } |
5804 | ||
cbc94022 IE |
5805 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
5806 | { | |
5807 | int ret; | |
cbc94022 | 5808 | |
1d8007bd PB |
5809 | ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, |
5810 | PAGE_SIZE * 3); | |
cbc94022 IE |
5811 | if (ret) |
5812 | return ret; | |
bfc6d222 | 5813 | kvm->arch.tss_addr = addr; |
1f755a82 | 5814 | return init_rmode_tss(kvm); |
cbc94022 IE |
5815 | } |
5816 | ||
0ca1b4f4 | 5817 | static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) |
6aa8b732 | 5818 | { |
77ab6db0 | 5819 | switch (vec) { |
77ab6db0 | 5820 | case BP_VECTOR: |
c573cd22 JK |
5821 | /* |
5822 | * Update instruction length as we may reinject the exception | |
5823 | * from user space while in guest debugging mode. | |
5824 | */ | |
5825 | to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = | |
5826 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
d0bfb940 | 5827 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
0ca1b4f4 GN |
5828 | return false; |
5829 | /* fall through */ | |
5830 | case DB_VECTOR: | |
5831 | if (vcpu->guest_debug & | |
5832 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
5833 | return false; | |
d0bfb940 JK |
5834 | /* fall through */ |
5835 | case DE_VECTOR: | |
77ab6db0 JK |
5836 | case OF_VECTOR: |
5837 | case BR_VECTOR: | |
5838 | case UD_VECTOR: | |
5839 | case DF_VECTOR: | |
5840 | case SS_VECTOR: | |
5841 | case GP_VECTOR: | |
5842 | case MF_VECTOR: | |
0ca1b4f4 GN |
5843 | return true; |
5844 | break; | |
77ab6db0 | 5845 | } |
0ca1b4f4 GN |
5846 | return false; |
5847 | } | |
5848 | ||
5849 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
5850 | int vec, u32 err_code) | |
5851 | { | |
5852 | /* | |
5853 | * Instruction with address size override prefix opcode 0x67 | |
5854 | * Cause the #SS fault with 0 error code in VM86 mode. | |
5855 | */ | |
5856 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { | |
5857 | if (emulate_instruction(vcpu, 0) == EMULATE_DONE) { | |
5858 | if (vcpu->arch.halt_request) { | |
5859 | vcpu->arch.halt_request = 0; | |
5cb56059 | 5860 | return kvm_vcpu_halt(vcpu); |
0ca1b4f4 GN |
5861 | } |
5862 | return 1; | |
5863 | } | |
5864 | return 0; | |
5865 | } | |
5866 | ||
5867 | /* | |
5868 | * Forward all other exceptions that are valid in real mode. | |
5869 | * FIXME: Breaks guest debugging in real mode, needs to be fixed with | |
5870 | * the required debugging infrastructure rework. | |
5871 | */ | |
5872 | kvm_queue_exception(vcpu, vec); | |
5873 | return 1; | |
6aa8b732 AK |
5874 | } |
5875 | ||
a0861c02 AK |
5876 | /* |
5877 | * Trigger machine check on the host. We assume all the MSRs are already set up | |
5878 | * by the CPU and that we still run on the same CPU as the MCE occurred on. | |
5879 | * We pass a fake environment to the machine check handler because we want | |
5880 | * the guest to be always treated like user space, no matter what context | |
5881 | * it used internally. | |
5882 | */ | |
5883 | static void kvm_machine_check(void) | |
5884 | { | |
5885 | #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) | |
5886 | struct pt_regs regs = { | |
5887 | .cs = 3, /* Fake ring 3 no matter what the guest ran on */ | |
5888 | .flags = X86_EFLAGS_IF, | |
5889 | }; | |
5890 | ||
5891 | do_machine_check(®s, 0); | |
5892 | #endif | |
5893 | } | |
5894 | ||
851ba692 | 5895 | static int handle_machine_check(struct kvm_vcpu *vcpu) |
a0861c02 AK |
5896 | { |
5897 | /* already handled by vcpu_run */ | |
5898 | return 1; | |
5899 | } | |
5900 | ||
851ba692 | 5901 | static int handle_exception(struct kvm_vcpu *vcpu) |
6aa8b732 | 5902 | { |
1155f76a | 5903 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
851ba692 | 5904 | struct kvm_run *kvm_run = vcpu->run; |
d0bfb940 | 5905 | u32 intr_info, ex_no, error_code; |
42dbaa5a | 5906 | unsigned long cr2, rip, dr6; |
6aa8b732 AK |
5907 | u32 vect_info; |
5908 | enum emulation_result er; | |
5909 | ||
1155f76a | 5910 | vect_info = vmx->idt_vectoring_info; |
88786475 | 5911 | intr_info = vmx->exit_intr_info; |
6aa8b732 | 5912 | |
a0861c02 | 5913 | if (is_machine_check(intr_info)) |
851ba692 | 5914 | return handle_machine_check(vcpu); |
a0861c02 | 5915 | |
ef85b673 | 5916 | if (is_nmi(intr_info)) |
1b6269db | 5917 | return 1; /* already handled by vmx_vcpu_run() */ |
2ab455cc | 5918 | |
7aa81cc0 | 5919 | if (is_invalid_opcode(intr_info)) { |
ac9b305c | 5920 | WARN_ON_ONCE(is_guest_mode(vcpu)); |
51d8b661 | 5921 | er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD); |
61cb57c9 LA |
5922 | if (er == EMULATE_USER_EXIT) |
5923 | return 0; | |
7aa81cc0 | 5924 | if (er != EMULATE_DONE) |
7ee5d940 | 5925 | kvm_queue_exception(vcpu, UD_VECTOR); |
7aa81cc0 AL |
5926 | return 1; |
5927 | } | |
5928 | ||
6aa8b732 | 5929 | error_code = 0; |
2e11384c | 5930 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 | 5931 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
bf4ca23e XG |
5932 | |
5933 | /* | |
5934 | * The #PF with PFEC.RSVD = 1 indicates the guest is accessing | |
5935 | * MMIO, it is better to report an internal error. | |
5936 | * See the comments in vmx_handle_exit. | |
5937 | */ | |
5938 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
5939 | !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { | |
5940 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
5941 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; | |
80f0e95d | 5942 | vcpu->run->internal.ndata = 3; |
bf4ca23e XG |
5943 | vcpu->run->internal.data[0] = vect_info; |
5944 | vcpu->run->internal.data[1] = intr_info; | |
80f0e95d | 5945 | vcpu->run->internal.data[2] = error_code; |
bf4ca23e XG |
5946 | return 0; |
5947 | } | |
5948 | ||
6aa8b732 AK |
5949 | if (is_page_fault(intr_info)) { |
5950 | cr2 = vmcs_readl(EXIT_QUALIFICATION); | |
1261bfa3 WL |
5951 | /* EPT won't cause page fault directly */ |
5952 | WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept); | |
d0006530 | 5953 | return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0); |
6aa8b732 AK |
5954 | } |
5955 | ||
d0bfb940 | 5956 | ex_no = intr_info & INTR_INFO_VECTOR_MASK; |
0ca1b4f4 GN |
5957 | |
5958 | if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) | |
5959 | return handle_rmode_exception(vcpu, ex_no, error_code); | |
5960 | ||
42dbaa5a | 5961 | switch (ex_no) { |
54a20552 EN |
5962 | case AC_VECTOR: |
5963 | kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); | |
5964 | return 1; | |
42dbaa5a JK |
5965 | case DB_VECTOR: |
5966 | dr6 = vmcs_readl(EXIT_QUALIFICATION); | |
5967 | if (!(vcpu->guest_debug & | |
5968 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { | |
8246bf52 | 5969 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 5970 | vcpu->arch.dr6 |= dr6 | DR6_RTM; |
fd2a445a HD |
5971 | if (!(dr6 & ~DR6_RESERVED)) /* icebp */ |
5972 | skip_emulated_instruction(vcpu); | |
5973 | ||
42dbaa5a JK |
5974 | kvm_queue_exception(vcpu, DB_VECTOR); |
5975 | return 1; | |
5976 | } | |
5977 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; | |
5978 | kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); | |
5979 | /* fall through */ | |
5980 | case BP_VECTOR: | |
c573cd22 JK |
5981 | /* |
5982 | * Update instruction length as we may reinject #BP from | |
5983 | * user space while in guest debugging mode. Reading it for | |
5984 | * #DB as well causes no harm, it is not used in that case. | |
5985 | */ | |
5986 | vmx->vcpu.arch.event_exit_inst_len = | |
5987 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
6aa8b732 | 5988 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
0a434bb2 | 5989 | rip = kvm_rip_read(vcpu); |
d0bfb940 JK |
5990 | kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; |
5991 | kvm_run->debug.arch.exception = ex_no; | |
42dbaa5a JK |
5992 | break; |
5993 | default: | |
d0bfb940 JK |
5994 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; |
5995 | kvm_run->ex.exception = ex_no; | |
5996 | kvm_run->ex.error_code = error_code; | |
42dbaa5a | 5997 | break; |
6aa8b732 | 5998 | } |
6aa8b732 AK |
5999 | return 0; |
6000 | } | |
6001 | ||
851ba692 | 6002 | static int handle_external_interrupt(struct kvm_vcpu *vcpu) |
6aa8b732 | 6003 | { |
1165f5fe | 6004 | ++vcpu->stat.irq_exits; |
6aa8b732 AK |
6005 | return 1; |
6006 | } | |
6007 | ||
851ba692 | 6008 | static int handle_triple_fault(struct kvm_vcpu *vcpu) |
988ad74f | 6009 | { |
851ba692 | 6010 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
bbeac283 | 6011 | vcpu->mmio_needed = 0; |
988ad74f AK |
6012 | return 0; |
6013 | } | |
6aa8b732 | 6014 | |
851ba692 | 6015 | static int handle_io(struct kvm_vcpu *vcpu) |
6aa8b732 | 6016 | { |
bfdaab09 | 6017 | unsigned long exit_qualification; |
6affcbed | 6018 | int size, in, string, ret; |
039576c0 | 6019 | unsigned port; |
6aa8b732 | 6020 | |
bfdaab09 | 6021 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 6022 | string = (exit_qualification & 16) != 0; |
cf8f70bf | 6023 | in = (exit_qualification & 8) != 0; |
e70669ab | 6024 | |
cf8f70bf | 6025 | ++vcpu->stat.io_exits; |
e70669ab | 6026 | |
cf8f70bf | 6027 | if (string || in) |
51d8b661 | 6028 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
e70669ab | 6029 | |
cf8f70bf GN |
6030 | port = exit_qualification >> 16; |
6031 | size = (exit_qualification & 7) + 1; | |
cf8f70bf | 6032 | |
6affcbed KH |
6033 | ret = kvm_skip_emulated_instruction(vcpu); |
6034 | ||
6035 | /* | |
6036 | * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered | |
6037 | * KVM_EXIT_DEBUG here. | |
6038 | */ | |
6039 | return kvm_fast_pio_out(vcpu, size, port) && ret; | |
6aa8b732 AK |
6040 | } |
6041 | ||
102d8325 IM |
6042 | static void |
6043 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
6044 | { | |
6045 | /* | |
6046 | * Patch in the VMCALL instruction: | |
6047 | */ | |
6048 | hypercall[0] = 0x0f; | |
6049 | hypercall[1] = 0x01; | |
6050 | hypercall[2] = 0xc1; | |
102d8325 IM |
6051 | } |
6052 | ||
0fa06071 | 6053 | /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ |
eeadf9e7 NHE |
6054 | static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) |
6055 | { | |
eeadf9e7 | 6056 | if (is_guest_mode(vcpu)) { |
1a0d74e6 JK |
6057 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
6058 | unsigned long orig_val = val; | |
6059 | ||
eeadf9e7 NHE |
6060 | /* |
6061 | * We get here when L2 changed cr0 in a way that did not change | |
6062 | * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), | |
1a0d74e6 JK |
6063 | * but did change L0 shadowed bits. So we first calculate the |
6064 | * effective cr0 value that L1 would like to write into the | |
6065 | * hardware. It consists of the L2-owned bits from the new | |
6066 | * value combined with the L1-owned bits from L1's guest_cr0. | |
eeadf9e7 | 6067 | */ |
1a0d74e6 JK |
6068 | val = (val & ~vmcs12->cr0_guest_host_mask) | |
6069 | (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); | |
6070 | ||
3899152c | 6071 | if (!nested_guest_cr0_valid(vcpu, val)) |
eeadf9e7 | 6072 | return 1; |
1a0d74e6 JK |
6073 | |
6074 | if (kvm_set_cr0(vcpu, val)) | |
6075 | return 1; | |
6076 | vmcs_writel(CR0_READ_SHADOW, orig_val); | |
eeadf9e7 | 6077 | return 0; |
1a0d74e6 JK |
6078 | } else { |
6079 | if (to_vmx(vcpu)->nested.vmxon && | |
3899152c | 6080 | !nested_host_cr0_valid(vcpu, val)) |
1a0d74e6 | 6081 | return 1; |
3899152c | 6082 | |
eeadf9e7 | 6083 | return kvm_set_cr0(vcpu, val); |
1a0d74e6 | 6084 | } |
eeadf9e7 NHE |
6085 | } |
6086 | ||
6087 | static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) | |
6088 | { | |
6089 | if (is_guest_mode(vcpu)) { | |
1a0d74e6 JK |
6090 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
6091 | unsigned long orig_val = val; | |
6092 | ||
6093 | /* analogously to handle_set_cr0 */ | |
6094 | val = (val & ~vmcs12->cr4_guest_host_mask) | | |
6095 | (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); | |
6096 | if (kvm_set_cr4(vcpu, val)) | |
eeadf9e7 | 6097 | return 1; |
1a0d74e6 | 6098 | vmcs_writel(CR4_READ_SHADOW, orig_val); |
eeadf9e7 NHE |
6099 | return 0; |
6100 | } else | |
6101 | return kvm_set_cr4(vcpu, val); | |
6102 | } | |
6103 | ||
851ba692 | 6104 | static int handle_cr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6105 | { |
229456fc | 6106 | unsigned long exit_qualification, val; |
6aa8b732 AK |
6107 | int cr; |
6108 | int reg; | |
49a9b07e | 6109 | int err; |
6affcbed | 6110 | int ret; |
6aa8b732 | 6111 | |
bfdaab09 | 6112 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
6113 | cr = exit_qualification & 15; |
6114 | reg = (exit_qualification >> 8) & 15; | |
6115 | switch ((exit_qualification >> 4) & 3) { | |
6116 | case 0: /* mov to cr */ | |
1e32c079 | 6117 | val = kvm_register_readl(vcpu, reg); |
229456fc | 6118 | trace_kvm_cr_write(cr, val); |
6aa8b732 AK |
6119 | switch (cr) { |
6120 | case 0: | |
eeadf9e7 | 6121 | err = handle_set_cr0(vcpu, val); |
6affcbed | 6122 | return kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 6123 | case 3: |
2390218b | 6124 | err = kvm_set_cr3(vcpu, val); |
6affcbed | 6125 | return kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 6126 | case 4: |
eeadf9e7 | 6127 | err = handle_set_cr4(vcpu, val); |
6affcbed | 6128 | return kvm_complete_insn_gp(vcpu, err); |
0a5fff19 GN |
6129 | case 8: { |
6130 | u8 cr8_prev = kvm_get_cr8(vcpu); | |
1e32c079 | 6131 | u8 cr8 = (u8)val; |
eea1cff9 | 6132 | err = kvm_set_cr8(vcpu, cr8); |
6affcbed | 6133 | ret = kvm_complete_insn_gp(vcpu, err); |
35754c98 | 6134 | if (lapic_in_kernel(vcpu)) |
6affcbed | 6135 | return ret; |
0a5fff19 | 6136 | if (cr8_prev <= cr8) |
6affcbed KH |
6137 | return ret; |
6138 | /* | |
6139 | * TODO: we might be squashing a | |
6140 | * KVM_GUESTDBG_SINGLESTEP-triggered | |
6141 | * KVM_EXIT_DEBUG here. | |
6142 | */ | |
851ba692 | 6143 | vcpu->run->exit_reason = KVM_EXIT_SET_TPR; |
0a5fff19 GN |
6144 | return 0; |
6145 | } | |
4b8073e4 | 6146 | } |
6aa8b732 | 6147 | break; |
25c4c276 | 6148 | case 2: /* clts */ |
bd7e5b08 PB |
6149 | WARN_ONCE(1, "Guest should always own CR0.TS"); |
6150 | vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); | |
4d4ec087 | 6151 | trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); |
6affcbed | 6152 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6153 | case 1: /*mov from cr*/ |
6154 | switch (cr) { | |
6155 | case 3: | |
9f8fe504 AK |
6156 | val = kvm_read_cr3(vcpu); |
6157 | kvm_register_write(vcpu, reg, val); | |
6158 | trace_kvm_cr_read(cr, val); | |
6affcbed | 6159 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 | 6160 | case 8: |
229456fc MT |
6161 | val = kvm_get_cr8(vcpu); |
6162 | kvm_register_write(vcpu, reg, val); | |
6163 | trace_kvm_cr_read(cr, val); | |
6affcbed | 6164 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6165 | } |
6166 | break; | |
6167 | case 3: /* lmsw */ | |
a1f83a74 | 6168 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
4d4ec087 | 6169 | trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); |
a1f83a74 | 6170 | kvm_lmsw(vcpu, val); |
6aa8b732 | 6171 | |
6affcbed | 6172 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6173 | default: |
6174 | break; | |
6175 | } | |
851ba692 | 6176 | vcpu->run->exit_reason = 0; |
a737f256 | 6177 | vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
6178 | (int)(exit_qualification >> 4) & 3, cr); |
6179 | return 0; | |
6180 | } | |
6181 | ||
851ba692 | 6182 | static int handle_dr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6183 | { |
bfdaab09 | 6184 | unsigned long exit_qualification; |
16f8a6f9 NA |
6185 | int dr, dr7, reg; |
6186 | ||
6187 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6188 | dr = exit_qualification & DEBUG_REG_ACCESS_NUM; | |
6189 | ||
6190 | /* First, if DR does not exist, trigger UD */ | |
6191 | if (!kvm_require_dr(vcpu, dr)) | |
6192 | return 1; | |
6aa8b732 | 6193 | |
f2483415 | 6194 | /* Do not handle if the CPL > 0, will trigger GP on re-entry */ |
0a79b009 AK |
6195 | if (!kvm_require_cpl(vcpu, 0)) |
6196 | return 1; | |
16f8a6f9 NA |
6197 | dr7 = vmcs_readl(GUEST_DR7); |
6198 | if (dr7 & DR7_GD) { | |
42dbaa5a JK |
6199 | /* |
6200 | * As the vm-exit takes precedence over the debug trap, we | |
6201 | * need to emulate the latter, either for the host or the | |
6202 | * guest debugging itself. | |
6203 | */ | |
6204 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
851ba692 | 6205 | vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; |
16f8a6f9 | 6206 | vcpu->run->debug.arch.dr7 = dr7; |
82b32774 | 6207 | vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
851ba692 AK |
6208 | vcpu->run->debug.arch.exception = DB_VECTOR; |
6209 | vcpu->run->exit_reason = KVM_EXIT_DEBUG; | |
42dbaa5a JK |
6210 | return 0; |
6211 | } else { | |
7305eb5d | 6212 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 6213 | vcpu->arch.dr6 |= DR6_BD | DR6_RTM; |
42dbaa5a JK |
6214 | kvm_queue_exception(vcpu, DB_VECTOR); |
6215 | return 1; | |
6216 | } | |
6217 | } | |
6218 | ||
81908bf4 | 6219 | if (vcpu->guest_debug == 0) { |
8f22372f PB |
6220 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
6221 | CPU_BASED_MOV_DR_EXITING); | |
81908bf4 PB |
6222 | |
6223 | /* | |
6224 | * No more DR vmexits; force a reload of the debug registers | |
6225 | * and reenter on this instruction. The next vmexit will | |
6226 | * retrieve the full state of the debug registers. | |
6227 | */ | |
6228 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
6229 | return 1; | |
6230 | } | |
6231 | ||
42dbaa5a JK |
6232 | reg = DEBUG_REG_ACCESS_REG(exit_qualification); |
6233 | if (exit_qualification & TYPE_MOV_FROM_DR) { | |
020df079 | 6234 | unsigned long val; |
4c4d563b JK |
6235 | |
6236 | if (kvm_get_dr(vcpu, dr, &val)) | |
6237 | return 1; | |
6238 | kvm_register_write(vcpu, reg, val); | |
020df079 | 6239 | } else |
5777392e | 6240 | if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) |
4c4d563b JK |
6241 | return 1; |
6242 | ||
6affcbed | 6243 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6244 | } |
6245 | ||
73aaf249 JK |
6246 | static u64 vmx_get_dr6(struct kvm_vcpu *vcpu) |
6247 | { | |
6248 | return vcpu->arch.dr6; | |
6249 | } | |
6250 | ||
6251 | static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) | |
6252 | { | |
6253 | } | |
6254 | ||
81908bf4 PB |
6255 | static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
6256 | { | |
81908bf4 PB |
6257 | get_debugreg(vcpu->arch.db[0], 0); |
6258 | get_debugreg(vcpu->arch.db[1], 1); | |
6259 | get_debugreg(vcpu->arch.db[2], 2); | |
6260 | get_debugreg(vcpu->arch.db[3], 3); | |
6261 | get_debugreg(vcpu->arch.dr6, 6); | |
6262 | vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); | |
6263 | ||
6264 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
8f22372f | 6265 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING); |
81908bf4 PB |
6266 | } |
6267 | ||
020df079 GN |
6268 | static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) |
6269 | { | |
6270 | vmcs_writel(GUEST_DR7, val); | |
6271 | } | |
6272 | ||
851ba692 | 6273 | static int handle_cpuid(struct kvm_vcpu *vcpu) |
6aa8b732 | 6274 | { |
6a908b62 | 6275 | return kvm_emulate_cpuid(vcpu); |
6aa8b732 AK |
6276 | } |
6277 | ||
851ba692 | 6278 | static int handle_rdmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6279 | { |
ad312c7c | 6280 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
609e36d3 | 6281 | struct msr_data msr_info; |
6aa8b732 | 6282 | |
609e36d3 PB |
6283 | msr_info.index = ecx; |
6284 | msr_info.host_initiated = false; | |
6285 | if (vmx_get_msr(vcpu, &msr_info)) { | |
59200273 | 6286 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 6287 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
6288 | return 1; |
6289 | } | |
6290 | ||
609e36d3 | 6291 | trace_kvm_msr_read(ecx, msr_info.data); |
2714d1d3 | 6292 | |
6aa8b732 | 6293 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
609e36d3 PB |
6294 | vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u; |
6295 | vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u; | |
6affcbed | 6296 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6297 | } |
6298 | ||
851ba692 | 6299 | static int handle_wrmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6300 | { |
8fe8ab46 | 6301 | struct msr_data msr; |
ad312c7c ZX |
6302 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
6303 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
6304 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 | 6305 | |
8fe8ab46 WA |
6306 | msr.data = data; |
6307 | msr.index = ecx; | |
6308 | msr.host_initiated = false; | |
854e8bb1 | 6309 | if (kvm_set_msr(vcpu, &msr) != 0) { |
59200273 | 6310 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 6311 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
6312 | return 1; |
6313 | } | |
6314 | ||
59200273 | 6315 | trace_kvm_msr_write(ecx, data); |
6affcbed | 6316 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6317 | } |
6318 | ||
851ba692 | 6319 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) |
6e5d865c | 6320 | { |
eb90f341 | 6321 | kvm_apic_update_ppr(vcpu); |
6e5d865c YS |
6322 | return 1; |
6323 | } | |
6324 | ||
851ba692 | 6325 | static int handle_interrupt_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 6326 | { |
47c0152e PB |
6327 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
6328 | CPU_BASED_VIRTUAL_INTR_PENDING); | |
2714d1d3 | 6329 | |
3842d135 AK |
6330 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6331 | ||
a26bf12a | 6332 | ++vcpu->stat.irq_window_exits; |
6aa8b732 AK |
6333 | return 1; |
6334 | } | |
6335 | ||
851ba692 | 6336 | static int handle_halt(struct kvm_vcpu *vcpu) |
6aa8b732 | 6337 | { |
d3bef15f | 6338 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
6339 | } |
6340 | ||
851ba692 | 6341 | static int handle_vmcall(struct kvm_vcpu *vcpu) |
c21415e8 | 6342 | { |
0d9c055e | 6343 | return kvm_emulate_hypercall(vcpu); |
c21415e8 IM |
6344 | } |
6345 | ||
ec25d5e6 GN |
6346 | static int handle_invd(struct kvm_vcpu *vcpu) |
6347 | { | |
51d8b661 | 6348 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
ec25d5e6 GN |
6349 | } |
6350 | ||
851ba692 | 6351 | static int handle_invlpg(struct kvm_vcpu *vcpu) |
a7052897 | 6352 | { |
f9c617f6 | 6353 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
a7052897 MT |
6354 | |
6355 | kvm_mmu_invlpg(vcpu, exit_qualification); | |
6affcbed | 6356 | return kvm_skip_emulated_instruction(vcpu); |
a7052897 MT |
6357 | } |
6358 | ||
fee84b07 AK |
6359 | static int handle_rdpmc(struct kvm_vcpu *vcpu) |
6360 | { | |
6361 | int err; | |
6362 | ||
6363 | err = kvm_rdpmc(vcpu); | |
6affcbed | 6364 | return kvm_complete_insn_gp(vcpu, err); |
fee84b07 AK |
6365 | } |
6366 | ||
851ba692 | 6367 | static int handle_wbinvd(struct kvm_vcpu *vcpu) |
e5edaa01 | 6368 | { |
6affcbed | 6369 | return kvm_emulate_wbinvd(vcpu); |
e5edaa01 ED |
6370 | } |
6371 | ||
2acf923e DC |
6372 | static int handle_xsetbv(struct kvm_vcpu *vcpu) |
6373 | { | |
6374 | u64 new_bv = kvm_read_edx_eax(vcpu); | |
6375 | u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
6376 | ||
6377 | if (kvm_set_xcr(vcpu, index, new_bv) == 0) | |
6affcbed | 6378 | return kvm_skip_emulated_instruction(vcpu); |
2acf923e DC |
6379 | return 1; |
6380 | } | |
6381 | ||
f53cd63c WL |
6382 | static int handle_xsaves(struct kvm_vcpu *vcpu) |
6383 | { | |
6affcbed | 6384 | kvm_skip_emulated_instruction(vcpu); |
f53cd63c WL |
6385 | WARN(1, "this should never happen\n"); |
6386 | return 1; | |
6387 | } | |
6388 | ||
6389 | static int handle_xrstors(struct kvm_vcpu *vcpu) | |
6390 | { | |
6affcbed | 6391 | kvm_skip_emulated_instruction(vcpu); |
f53cd63c WL |
6392 | WARN(1, "this should never happen\n"); |
6393 | return 1; | |
6394 | } | |
6395 | ||
851ba692 | 6396 | static int handle_apic_access(struct kvm_vcpu *vcpu) |
f78e0e2e | 6397 | { |
58fbbf26 KT |
6398 | if (likely(fasteoi)) { |
6399 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6400 | int access_type, offset; | |
6401 | ||
6402 | access_type = exit_qualification & APIC_ACCESS_TYPE; | |
6403 | offset = exit_qualification & APIC_ACCESS_OFFSET; | |
6404 | /* | |
6405 | * Sane guest uses MOV to write EOI, with written value | |
6406 | * not cared. So make a short-circuit here by avoiding | |
6407 | * heavy instruction emulation. | |
6408 | */ | |
6409 | if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && | |
6410 | (offset == APIC_EOI)) { | |
6411 | kvm_lapic_set_eoi(vcpu); | |
6affcbed | 6412 | return kvm_skip_emulated_instruction(vcpu); |
58fbbf26 KT |
6413 | } |
6414 | } | |
51d8b661 | 6415 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
f78e0e2e SY |
6416 | } |
6417 | ||
c7c9c56c YZ |
6418 | static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) |
6419 | { | |
6420 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6421 | int vector = exit_qualification & 0xff; | |
6422 | ||
6423 | /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ | |
6424 | kvm_apic_set_eoi_accelerated(vcpu, vector); | |
6425 | return 1; | |
6426 | } | |
6427 | ||
83d4c286 YZ |
6428 | static int handle_apic_write(struct kvm_vcpu *vcpu) |
6429 | { | |
6430 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6431 | u32 offset = exit_qualification & 0xfff; | |
6432 | ||
6433 | /* APIC-write VM exit is trap-like and thus no need to adjust IP */ | |
6434 | kvm_apic_write_nodecode(vcpu, offset); | |
6435 | return 1; | |
6436 | } | |
6437 | ||
851ba692 | 6438 | static int handle_task_switch(struct kvm_vcpu *vcpu) |
37817f29 | 6439 | { |
60637aac | 6440 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
37817f29 | 6441 | unsigned long exit_qualification; |
e269fb21 JK |
6442 | bool has_error_code = false; |
6443 | u32 error_code = 0; | |
37817f29 | 6444 | u16 tss_selector; |
7f3d35fd | 6445 | int reason, type, idt_v, idt_index; |
64a7ec06 GN |
6446 | |
6447 | idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); | |
7f3d35fd | 6448 | idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); |
64a7ec06 | 6449 | type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); |
37817f29 IE |
6450 | |
6451 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6452 | ||
6453 | reason = (u32)exit_qualification >> 30; | |
64a7ec06 GN |
6454 | if (reason == TASK_SWITCH_GATE && idt_v) { |
6455 | switch (type) { | |
6456 | case INTR_TYPE_NMI_INTR: | |
6457 | vcpu->arch.nmi_injected = false; | |
654f06fc | 6458 | vmx_set_nmi_mask(vcpu, true); |
64a7ec06 GN |
6459 | break; |
6460 | case INTR_TYPE_EXT_INTR: | |
66fd3f7f | 6461 | case INTR_TYPE_SOFT_INTR: |
64a7ec06 GN |
6462 | kvm_clear_interrupt_queue(vcpu); |
6463 | break; | |
6464 | case INTR_TYPE_HARD_EXCEPTION: | |
e269fb21 JK |
6465 | if (vmx->idt_vectoring_info & |
6466 | VECTORING_INFO_DELIVER_CODE_MASK) { | |
6467 | has_error_code = true; | |
6468 | error_code = | |
6469 | vmcs_read32(IDT_VECTORING_ERROR_CODE); | |
6470 | } | |
6471 | /* fall through */ | |
64a7ec06 GN |
6472 | case INTR_TYPE_SOFT_EXCEPTION: |
6473 | kvm_clear_exception_queue(vcpu); | |
6474 | break; | |
6475 | default: | |
6476 | break; | |
6477 | } | |
60637aac | 6478 | } |
37817f29 IE |
6479 | tss_selector = exit_qualification; |
6480 | ||
64a7ec06 GN |
6481 | if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && |
6482 | type != INTR_TYPE_EXT_INTR && | |
6483 | type != INTR_TYPE_NMI_INTR)) | |
6484 | skip_emulated_instruction(vcpu); | |
6485 | ||
7f3d35fd KW |
6486 | if (kvm_task_switch(vcpu, tss_selector, |
6487 | type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason, | |
6488 | has_error_code, error_code) == EMULATE_FAIL) { | |
acb54517 GN |
6489 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
6490 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6491 | vcpu->run->internal.ndata = 0; | |
42dbaa5a | 6492 | return 0; |
acb54517 | 6493 | } |
42dbaa5a | 6494 | |
42dbaa5a JK |
6495 | /* |
6496 | * TODO: What about debug traps on tss switch? | |
6497 | * Are we supposed to inject them and update dr6? | |
6498 | */ | |
6499 | ||
6500 | return 1; | |
37817f29 IE |
6501 | } |
6502 | ||
851ba692 | 6503 | static int handle_ept_violation(struct kvm_vcpu *vcpu) |
1439442c | 6504 | { |
f9c617f6 | 6505 | unsigned long exit_qualification; |
1439442c | 6506 | gpa_t gpa; |
eebed243 | 6507 | u64 error_code; |
1439442c | 6508 | |
f9c617f6 | 6509 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
1439442c | 6510 | |
0be9c7a8 GN |
6511 | /* |
6512 | * EPT violation happened while executing iret from NMI, | |
6513 | * "blocked by NMI" bit has to be set before next VM entry. | |
6514 | * There are errata that may cause this bit to not be set: | |
6515 | * AAK134, BY25. | |
6516 | */ | |
bcd1c294 | 6517 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && |
d02fcf50 | 6518 | enable_vnmi && |
bcd1c294 | 6519 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) |
0be9c7a8 GN |
6520 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); |
6521 | ||
1439442c | 6522 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); |
229456fc | 6523 | trace_kvm_page_fault(gpa, exit_qualification); |
4f5982a5 | 6524 | |
27959a44 | 6525 | /* Is it a read fault? */ |
ab22a473 | 6526 | error_code = (exit_qualification & EPT_VIOLATION_ACC_READ) |
27959a44 JS |
6527 | ? PFERR_USER_MASK : 0; |
6528 | /* Is it a write fault? */ | |
ab22a473 | 6529 | error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE) |
27959a44 JS |
6530 | ? PFERR_WRITE_MASK : 0; |
6531 | /* Is it a fetch fault? */ | |
ab22a473 | 6532 | error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR) |
27959a44 JS |
6533 | ? PFERR_FETCH_MASK : 0; |
6534 | /* ept page table entry is present? */ | |
6535 | error_code |= (exit_qualification & | |
6536 | (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE | | |
6537 | EPT_VIOLATION_EXECUTABLE)) | |
6538 | ? PFERR_PRESENT_MASK : 0; | |
4f5982a5 | 6539 | |
eebed243 PB |
6540 | error_code |= (exit_qualification & 0x100) != 0 ? |
6541 | PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK; | |
25d92081 | 6542 | |
25d92081 | 6543 | vcpu->arch.exit_qualification = exit_qualification; |
4f5982a5 | 6544 | return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); |
1439442c SY |
6545 | } |
6546 | ||
851ba692 | 6547 | static int handle_ept_misconfig(struct kvm_vcpu *vcpu) |
68f89400 | 6548 | { |
f735d4af | 6549 | int ret; |
68f89400 MT |
6550 | gpa_t gpa; |
6551 | ||
9034e6e8 PB |
6552 | /* |
6553 | * A nested guest cannot optimize MMIO vmexits, because we have an | |
6554 | * nGPA here instead of the required GPA. | |
6555 | */ | |
68f89400 | 6556 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); |
9034e6e8 PB |
6557 | if (!is_guest_mode(vcpu) && |
6558 | !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { | |
931c33b1 | 6559 | trace_kvm_fast_mmio(gpa); |
6affcbed | 6560 | return kvm_skip_emulated_instruction(vcpu); |
68c3b4d1 | 6561 | } |
68f89400 | 6562 | |
e08d26f0 PB |
6563 | ret = kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0); |
6564 | if (ret >= 0) | |
6565 | return ret; | |
ce88decf XG |
6566 | |
6567 | /* It is the real ept misconfig */ | |
f735d4af | 6568 | WARN_ON(1); |
68f89400 | 6569 | |
851ba692 AK |
6570 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
6571 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG; | |
68f89400 MT |
6572 | |
6573 | return 0; | |
6574 | } | |
6575 | ||
851ba692 | 6576 | static int handle_nmi_window(struct kvm_vcpu *vcpu) |
f08864b4 | 6577 | { |
d02fcf50 | 6578 | WARN_ON_ONCE(!enable_vnmi); |
47c0152e PB |
6579 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
6580 | CPU_BASED_VIRTUAL_NMI_PENDING); | |
f08864b4 | 6581 | ++vcpu->stat.nmi_window_exits; |
3842d135 | 6582 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f08864b4 SY |
6583 | |
6584 | return 1; | |
6585 | } | |
6586 | ||
80ced186 | 6587 | static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) |
ea953ef0 | 6588 | { |
8b3079a5 AK |
6589 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6590 | enum emulation_result err = EMULATE_DONE; | |
80ced186 | 6591 | int ret = 1; |
49e9d557 AK |
6592 | u32 cpu_exec_ctrl; |
6593 | bool intr_window_requested; | |
b8405c18 | 6594 | unsigned count = 130; |
49e9d557 AK |
6595 | |
6596 | cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
6597 | intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING; | |
ea953ef0 | 6598 | |
98eb2f8b | 6599 | while (vmx->emulation_required && count-- != 0) { |
bdea48e3 | 6600 | if (intr_window_requested && vmx_interrupt_allowed(vcpu)) |
49e9d557 AK |
6601 | return handle_interrupt_window(&vmx->vcpu); |
6602 | ||
72875d8a | 6603 | if (kvm_test_request(KVM_REQ_EVENT, vcpu)) |
de87dcdd AK |
6604 | return 1; |
6605 | ||
9b8ae637 | 6606 | err = emulate_instruction(vcpu, 0); |
ea953ef0 | 6607 | |
ac0a48c3 | 6608 | if (err == EMULATE_USER_EXIT) { |
94452b9e | 6609 | ++vcpu->stat.mmio_exits; |
80ced186 MG |
6610 | ret = 0; |
6611 | goto out; | |
6612 | } | |
1d5a4d9b | 6613 | |
de5f70e0 AK |
6614 | if (err != EMULATE_DONE) { |
6615 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
6616 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6617 | vcpu->run->internal.ndata = 0; | |
6d77dbfc | 6618 | return 0; |
de5f70e0 | 6619 | } |
ea953ef0 | 6620 | |
8d76c49e GN |
6621 | if (vcpu->arch.halt_request) { |
6622 | vcpu->arch.halt_request = 0; | |
5cb56059 | 6623 | ret = kvm_vcpu_halt(vcpu); |
8d76c49e GN |
6624 | goto out; |
6625 | } | |
6626 | ||
ea953ef0 | 6627 | if (signal_pending(current)) |
80ced186 | 6628 | goto out; |
ea953ef0 MG |
6629 | if (need_resched()) |
6630 | schedule(); | |
6631 | } | |
6632 | ||
80ced186 MG |
6633 | out: |
6634 | return ret; | |
ea953ef0 MG |
6635 | } |
6636 | ||
b4a2d31d RK |
6637 | static int __grow_ple_window(int val) |
6638 | { | |
6639 | if (ple_window_grow < 1) | |
6640 | return ple_window; | |
6641 | ||
6642 | val = min(val, ple_window_actual_max); | |
6643 | ||
6644 | if (ple_window_grow < ple_window) | |
6645 | val *= ple_window_grow; | |
6646 | else | |
6647 | val += ple_window_grow; | |
6648 | ||
6649 | return val; | |
6650 | } | |
6651 | ||
6652 | static int __shrink_ple_window(int val, int modifier, int minimum) | |
6653 | { | |
6654 | if (modifier < 1) | |
6655 | return ple_window; | |
6656 | ||
6657 | if (modifier < ple_window) | |
6658 | val /= modifier; | |
6659 | else | |
6660 | val -= modifier; | |
6661 | ||
6662 | return max(val, minimum); | |
6663 | } | |
6664 | ||
6665 | static void grow_ple_window(struct kvm_vcpu *vcpu) | |
6666 | { | |
6667 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6668 | int old = vmx->ple_window; | |
6669 | ||
6670 | vmx->ple_window = __grow_ple_window(old); | |
6671 | ||
6672 | if (vmx->ple_window != old) | |
6673 | vmx->ple_window_dirty = true; | |
7b46268d RK |
6674 | |
6675 | trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
6676 | } |
6677 | ||
6678 | static void shrink_ple_window(struct kvm_vcpu *vcpu) | |
6679 | { | |
6680 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6681 | int old = vmx->ple_window; | |
6682 | ||
6683 | vmx->ple_window = __shrink_ple_window(old, | |
6684 | ple_window_shrink, ple_window); | |
6685 | ||
6686 | if (vmx->ple_window != old) | |
6687 | vmx->ple_window_dirty = true; | |
7b46268d RK |
6688 | |
6689 | trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
6690 | } |
6691 | ||
6692 | /* | |
6693 | * ple_window_actual_max is computed to be one grow_ple_window() below | |
6694 | * ple_window_max. (See __grow_ple_window for the reason.) | |
6695 | * This prevents overflows, because ple_window_max is int. | |
6696 | * ple_window_max effectively rounded down to a multiple of ple_window_grow in | |
6697 | * this process. | |
6698 | * ple_window_max is also prevented from setting vmx->ple_window < ple_window. | |
6699 | */ | |
6700 | static void update_ple_window_actual_max(void) | |
6701 | { | |
6702 | ple_window_actual_max = | |
6703 | __shrink_ple_window(max(ple_window_max, ple_window), | |
6704 | ple_window_grow, INT_MIN); | |
6705 | } | |
6706 | ||
bf9f6ac8 FW |
6707 | /* |
6708 | * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. | |
6709 | */ | |
6710 | static void wakeup_handler(void) | |
6711 | { | |
6712 | struct kvm_vcpu *vcpu; | |
6713 | int cpu = smp_processor_id(); | |
6714 | ||
6715 | spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
6716 | list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), | |
6717 | blocked_vcpu_list) { | |
6718 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
6719 | ||
6720 | if (pi_test_on(pi_desc) == 1) | |
6721 | kvm_vcpu_kick(vcpu); | |
6722 | } | |
6723 | spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
6724 | } | |
6725 | ||
f160c7b7 JS |
6726 | void vmx_enable_tdp(void) |
6727 | { | |
6728 | kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, | |
6729 | enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull, | |
6730 | enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull, | |
6731 | 0ull, VMX_EPT_EXECUTABLE_MASK, | |
6732 | cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK, | |
d0ec49d4 | 6733 | VMX_EPT_RWX_MASK, 0ull); |
f160c7b7 JS |
6734 | |
6735 | ept_set_mmio_spte_mask(); | |
6736 | kvm_enable_tdp(); | |
6737 | } | |
6738 | ||
f2c7648d TC |
6739 | static __init int hardware_setup(void) |
6740 | { | |
34a1cd60 TC |
6741 | int r = -ENOMEM, i, msr; |
6742 | ||
6743 | rdmsrl_safe(MSR_EFER, &host_efer); | |
6744 | ||
6745 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) | |
6746 | kvm_define_shared_msr(i, vmx_msr_index[i]); | |
6747 | ||
23611332 RK |
6748 | for (i = 0; i < VMX_BITMAP_NR; i++) { |
6749 | vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL); | |
6750 | if (!vmx_bitmap[i]) | |
6751 | goto out; | |
6752 | } | |
34a1cd60 | 6753 | |
34a1cd60 TC |
6754 | memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE); |
6755 | memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE); | |
6756 | ||
34a1cd60 | 6757 | memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE); |
34a1cd60 TC |
6758 | |
6759 | memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE); | |
6760 | ||
6761 | memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE); | |
6762 | memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE); | |
6763 | ||
34a1cd60 TC |
6764 | if (setup_vmcs_config(&vmcs_config) < 0) { |
6765 | r = -EIO; | |
23611332 | 6766 | goto out; |
baa03522 | 6767 | } |
f2c7648d TC |
6768 | |
6769 | if (boot_cpu_has(X86_FEATURE_NX)) | |
6770 | kvm_enable_efer_bits(EFER_NX); | |
6771 | ||
08d839c4 WL |
6772 | if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() || |
6773 | !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global())) | |
f2c7648d | 6774 | enable_vpid = 0; |
08d839c4 | 6775 | |
f2c7648d TC |
6776 | if (!cpu_has_vmx_shadow_vmcs()) |
6777 | enable_shadow_vmcs = 0; | |
6778 | if (enable_shadow_vmcs) | |
6779 | init_vmcs_shadow_fields(); | |
6780 | ||
6781 | if (!cpu_has_vmx_ept() || | |
42aa53b4 | 6782 | !cpu_has_vmx_ept_4levels() || |
f5f51586 | 6783 | !cpu_has_vmx_ept_mt_wb() || |
8ad8182e | 6784 | !cpu_has_vmx_invept_global()) |
f2c7648d | 6785 | enable_ept = 0; |
f2c7648d | 6786 | |
fce6ac4c | 6787 | if (!cpu_has_vmx_ept_ad_bits() || !enable_ept) |
f2c7648d TC |
6788 | enable_ept_ad_bits = 0; |
6789 | ||
8ad8182e | 6790 | if (!cpu_has_vmx_unrestricted_guest() || !enable_ept) |
f2c7648d TC |
6791 | enable_unrestricted_guest = 0; |
6792 | ||
ad15a296 | 6793 | if (!cpu_has_vmx_flexpriority()) |
f2c7648d TC |
6794 | flexpriority_enabled = 0; |
6795 | ||
d02fcf50 PB |
6796 | if (!cpu_has_virtual_nmis()) |
6797 | enable_vnmi = 0; | |
6798 | ||
ad15a296 PB |
6799 | /* |
6800 | * set_apic_access_page_addr() is used to reload apic access | |
6801 | * page upon invalidation. No need to do anything if not | |
6802 | * using the APIC_ACCESS_ADDR VMCS field. | |
6803 | */ | |
6804 | if (!flexpriority_enabled) | |
f2c7648d | 6805 | kvm_x86_ops->set_apic_access_page_addr = NULL; |
f2c7648d TC |
6806 | |
6807 | if (!cpu_has_vmx_tpr_shadow()) | |
6808 | kvm_x86_ops->update_cr8_intercept = NULL; | |
6809 | ||
6810 | if (enable_ept && !cpu_has_vmx_ept_2m_page()) | |
6811 | kvm_disable_largepages(); | |
6812 | ||
0f107682 | 6813 | if (!cpu_has_vmx_ple()) { |
f2c7648d | 6814 | ple_gap = 0; |
0f107682 WL |
6815 | ple_window = 0; |
6816 | ple_window_grow = 0; | |
6817 | ple_window_max = 0; | |
6818 | ple_window_shrink = 0; | |
6819 | } | |
f2c7648d | 6820 | |
76dfafd5 | 6821 | if (!cpu_has_vmx_apicv()) { |
f2c7648d | 6822 | enable_apicv = 0; |
76dfafd5 PB |
6823 | kvm_x86_ops->sync_pir_to_irr = NULL; |
6824 | } | |
f2c7648d | 6825 | |
64903d61 HZ |
6826 | if (cpu_has_vmx_tsc_scaling()) { |
6827 | kvm_has_tsc_control = true; | |
6828 | kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; | |
6829 | kvm_tsc_scaling_ratio_frac_bits = 48; | |
6830 | } | |
6831 | ||
baa03522 TC |
6832 | vmx_disable_intercept_for_msr(MSR_FS_BASE, false); |
6833 | vmx_disable_intercept_for_msr(MSR_GS_BASE, false); | |
6834 | vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true); | |
6835 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false); | |
6836 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false); | |
6837 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false); | |
baa03522 | 6838 | |
c63e4563 | 6839 | memcpy(vmx_msr_bitmap_legacy_x2apic_apicv, |
baa03522 | 6840 | vmx_msr_bitmap_legacy, PAGE_SIZE); |
c63e4563 | 6841 | memcpy(vmx_msr_bitmap_longmode_x2apic_apicv, |
baa03522 | 6842 | vmx_msr_bitmap_longmode, PAGE_SIZE); |
c63e4563 | 6843 | memcpy(vmx_msr_bitmap_legacy_x2apic, |
f6e90f9e | 6844 | vmx_msr_bitmap_legacy, PAGE_SIZE); |
c63e4563 | 6845 | memcpy(vmx_msr_bitmap_longmode_x2apic, |
f6e90f9e | 6846 | vmx_msr_bitmap_longmode, PAGE_SIZE); |
baa03522 | 6847 | |
04bb92e4 WL |
6848 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
6849 | ||
40d8338d RK |
6850 | for (msr = 0x800; msr <= 0x8ff; msr++) { |
6851 | if (msr == 0x839 /* TMCCT */) | |
6852 | continue; | |
2e69f865 | 6853 | vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true); |
40d8338d | 6854 | } |
3ce424e4 | 6855 | |
f6e90f9e | 6856 | /* |
2e69f865 RK |
6857 | * TPR reads and writes can be virtualized even if virtual interrupt |
6858 | * delivery is not in use. | |
f6e90f9e | 6859 | */ |
2e69f865 RK |
6860 | vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true); |
6861 | vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false); | |
3ce424e4 | 6862 | |
3ce424e4 | 6863 | /* EOI */ |
2e69f865 | 6864 | vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true); |
3ce424e4 | 6865 | /* SELF-IPI */ |
2e69f865 | 6866 | vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true); |
baa03522 | 6867 | |
f160c7b7 JS |
6868 | if (enable_ept) |
6869 | vmx_enable_tdp(); | |
6870 | else | |
baa03522 TC |
6871 | kvm_disable_tdp(); |
6872 | ||
6873 | update_ple_window_actual_max(); | |
6874 | ||
843e4330 KH |
6875 | /* |
6876 | * Only enable PML when hardware supports PML feature, and both EPT | |
6877 | * and EPT A/D bit features are enabled -- PML depends on them to work. | |
6878 | */ | |
6879 | if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) | |
6880 | enable_pml = 0; | |
6881 | ||
6882 | if (!enable_pml) { | |
6883 | kvm_x86_ops->slot_enable_log_dirty = NULL; | |
6884 | kvm_x86_ops->slot_disable_log_dirty = NULL; | |
6885 | kvm_x86_ops->flush_log_dirty = NULL; | |
6886 | kvm_x86_ops->enable_log_dirty_pt_masked = NULL; | |
6887 | } | |
6888 | ||
64672c95 YJ |
6889 | if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) { |
6890 | u64 vmx_msr; | |
6891 | ||
6892 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
6893 | cpu_preemption_timer_multi = | |
6894 | vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; | |
6895 | } else { | |
6896 | kvm_x86_ops->set_hv_timer = NULL; | |
6897 | kvm_x86_ops->cancel_hv_timer = NULL; | |
6898 | } | |
6899 | ||
bf9f6ac8 FW |
6900 | kvm_set_posted_intr_wakeup_handler(wakeup_handler); |
6901 | ||
c45dcc71 AR |
6902 | kvm_mce_cap_supported |= MCG_LMCE_P; |
6903 | ||
f2c7648d | 6904 | return alloc_kvm_area(); |
34a1cd60 | 6905 | |
34a1cd60 | 6906 | out: |
23611332 RK |
6907 | for (i = 0; i < VMX_BITMAP_NR; i++) |
6908 | free_page((unsigned long)vmx_bitmap[i]); | |
34a1cd60 TC |
6909 | |
6910 | return r; | |
f2c7648d TC |
6911 | } |
6912 | ||
6913 | static __exit void hardware_unsetup(void) | |
6914 | { | |
23611332 RK |
6915 | int i; |
6916 | ||
6917 | for (i = 0; i < VMX_BITMAP_NR; i++) | |
6918 | free_page((unsigned long)vmx_bitmap[i]); | |
34a1cd60 | 6919 | |
f2c7648d TC |
6920 | free_kvm_area(); |
6921 | } | |
6922 | ||
4b8d54f9 ZE |
6923 | /* |
6924 | * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE | |
6925 | * exiting, so only get here on cpu with PAUSE-Loop-Exiting. | |
6926 | */ | |
9fb41ba8 | 6927 | static int handle_pause(struct kvm_vcpu *vcpu) |
4b8d54f9 | 6928 | { |
b4a2d31d RK |
6929 | if (ple_gap) |
6930 | grow_ple_window(vcpu); | |
6931 | ||
de63ad4c LM |
6932 | /* |
6933 | * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting" | |
6934 | * VM-execution control is ignored if CPL > 0. OTOH, KVM | |
6935 | * never set PAUSE_EXITING and just set PLE if supported, | |
6936 | * so the vcpu must be CPL=0 if it gets a PAUSE exit. | |
6937 | */ | |
6938 | kvm_vcpu_on_spin(vcpu, true); | |
6affcbed | 6939 | return kvm_skip_emulated_instruction(vcpu); |
4b8d54f9 ZE |
6940 | } |
6941 | ||
87c00572 | 6942 | static int handle_nop(struct kvm_vcpu *vcpu) |
59708670 | 6943 | { |
6affcbed | 6944 | return kvm_skip_emulated_instruction(vcpu); |
59708670 SY |
6945 | } |
6946 | ||
87c00572 GS |
6947 | static int handle_mwait(struct kvm_vcpu *vcpu) |
6948 | { | |
6949 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
6950 | return handle_nop(vcpu); | |
6951 | } | |
6952 | ||
45ec368c JM |
6953 | static int handle_invalid_op(struct kvm_vcpu *vcpu) |
6954 | { | |
6955 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6956 | return 1; | |
6957 | } | |
6958 | ||
5f3d45e7 MD |
6959 | static int handle_monitor_trap(struct kvm_vcpu *vcpu) |
6960 | { | |
6961 | return 1; | |
6962 | } | |
6963 | ||
87c00572 GS |
6964 | static int handle_monitor(struct kvm_vcpu *vcpu) |
6965 | { | |
6966 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
6967 | return handle_nop(vcpu); | |
6968 | } | |
6969 | ||
ff2f6fe9 NHE |
6970 | /* |
6971 | * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12. | |
6972 | * We could reuse a single VMCS for all the L2 guests, but we also want the | |
6973 | * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this | |
6974 | * allows keeping them loaded on the processor, and in the future will allow | |
6975 | * optimizations where prepare_vmcs02 doesn't need to set all the fields on | |
6976 | * every entry if they never change. | |
6977 | * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE | |
6978 | * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first. | |
6979 | * | |
6980 | * The following functions allocate and free a vmcs02 in this pool. | |
6981 | */ | |
6982 | ||
6983 | /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */ | |
6984 | static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx) | |
6985 | { | |
6986 | struct vmcs02_list *item; | |
6987 | list_for_each_entry(item, &vmx->nested.vmcs02_pool, list) | |
6988 | if (item->vmptr == vmx->nested.current_vmptr) { | |
6989 | list_move(&item->list, &vmx->nested.vmcs02_pool); | |
6990 | return &item->vmcs02; | |
6991 | } | |
6992 | ||
6993 | if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) { | |
6994 | /* Recycle the least recently used VMCS. */ | |
d74c0e6b GT |
6995 | item = list_last_entry(&vmx->nested.vmcs02_pool, |
6996 | struct vmcs02_list, list); | |
ff2f6fe9 NHE |
6997 | item->vmptr = vmx->nested.current_vmptr; |
6998 | list_move(&item->list, &vmx->nested.vmcs02_pool); | |
6999 | return &item->vmcs02; | |
7000 | } | |
7001 | ||
7002 | /* Create a new VMCS */ | |
8a1b4392 | 7003 | item = kzalloc(sizeof(struct vmcs02_list), GFP_KERNEL); |
ff2f6fe9 NHE |
7004 | if (!item) |
7005 | return NULL; | |
7006 | item->vmcs02.vmcs = alloc_vmcs(); | |
355f4fb1 | 7007 | item->vmcs02.shadow_vmcs = NULL; |
ff2f6fe9 NHE |
7008 | if (!item->vmcs02.vmcs) { |
7009 | kfree(item); | |
7010 | return NULL; | |
7011 | } | |
7012 | loaded_vmcs_init(&item->vmcs02); | |
7013 | item->vmptr = vmx->nested.current_vmptr; | |
7014 | list_add(&(item->list), &(vmx->nested.vmcs02_pool)); | |
7015 | vmx->nested.vmcs02_num++; | |
7016 | return &item->vmcs02; | |
7017 | } | |
7018 | ||
7019 | /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */ | |
7020 | static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr) | |
7021 | { | |
7022 | struct vmcs02_list *item; | |
7023 | list_for_each_entry(item, &vmx->nested.vmcs02_pool, list) | |
7024 | if (item->vmptr == vmptr) { | |
7025 | free_loaded_vmcs(&item->vmcs02); | |
7026 | list_del(&item->list); | |
7027 | kfree(item); | |
7028 | vmx->nested.vmcs02_num--; | |
7029 | return; | |
7030 | } | |
7031 | } | |
7032 | ||
7033 | /* | |
7034 | * Free all VMCSs saved for this vcpu, except the one pointed by | |
4fa7734c PB |
7035 | * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs |
7036 | * must be &vmx->vmcs01. | |
ff2f6fe9 NHE |
7037 | */ |
7038 | static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx) | |
7039 | { | |
7040 | struct vmcs02_list *item, *n; | |
4fa7734c PB |
7041 | |
7042 | WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01); | |
ff2f6fe9 | 7043 | list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) { |
4fa7734c PB |
7044 | /* |
7045 | * Something will leak if the above WARN triggers. Better than | |
7046 | * a use-after-free. | |
7047 | */ | |
7048 | if (vmx->loaded_vmcs == &item->vmcs02) | |
7049 | continue; | |
7050 | ||
7051 | free_loaded_vmcs(&item->vmcs02); | |
ff2f6fe9 NHE |
7052 | list_del(&item->list); |
7053 | kfree(item); | |
4fa7734c | 7054 | vmx->nested.vmcs02_num--; |
ff2f6fe9 | 7055 | } |
ff2f6fe9 NHE |
7056 | } |
7057 | ||
0658fbaa ACL |
7058 | /* |
7059 | * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(), | |
7060 | * set the success or error code of an emulated VMX instruction, as specified | |
7061 | * by Vol 2B, VMX Instruction Reference, "Conventions". | |
7062 | */ | |
7063 | static void nested_vmx_succeed(struct kvm_vcpu *vcpu) | |
7064 | { | |
7065 | vmx_set_rflags(vcpu, vmx_get_rflags(vcpu) | |
7066 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
7067 | X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF)); | |
7068 | } | |
7069 | ||
7070 | static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu) | |
7071 | { | |
7072 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
7073 | & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | | |
7074 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
7075 | | X86_EFLAGS_CF); | |
7076 | } | |
7077 | ||
145c28dd | 7078 | static void nested_vmx_failValid(struct kvm_vcpu *vcpu, |
0658fbaa ACL |
7079 | u32 vm_instruction_error) |
7080 | { | |
7081 | if (to_vmx(vcpu)->nested.current_vmptr == -1ull) { | |
7082 | /* | |
7083 | * failValid writes the error number to the current VMCS, which | |
7084 | * can't be done there isn't a current VMCS. | |
7085 | */ | |
7086 | nested_vmx_failInvalid(vcpu); | |
7087 | return; | |
7088 | } | |
7089 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
7090 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
7091 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
7092 | | X86_EFLAGS_ZF); | |
7093 | get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error; | |
7094 | /* | |
7095 | * We don't need to force a shadow sync because | |
7096 | * VM_INSTRUCTION_ERROR is not shadowed | |
7097 | */ | |
7098 | } | |
145c28dd | 7099 | |
ff651cb6 WV |
7100 | static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator) |
7101 | { | |
7102 | /* TODO: not to reset guest simply here. */ | |
7103 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
bbe41b95 | 7104 | pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator); |
ff651cb6 WV |
7105 | } |
7106 | ||
f4124500 JK |
7107 | static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer) |
7108 | { | |
7109 | struct vcpu_vmx *vmx = | |
7110 | container_of(timer, struct vcpu_vmx, nested.preemption_timer); | |
7111 | ||
7112 | vmx->nested.preemption_timer_expired = true; | |
7113 | kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu); | |
7114 | kvm_vcpu_kick(&vmx->vcpu); | |
7115 | ||
7116 | return HRTIMER_NORESTART; | |
7117 | } | |
7118 | ||
19677e32 BD |
7119 | /* |
7120 | * Decode the memory-address operand of a vmx instruction, as recorded on an | |
7121 | * exit caused by such an instruction (run by a guest hypervisor). | |
7122 | * On success, returns 0. When the operand is invalid, returns 1 and throws | |
7123 | * #UD or #GP. | |
7124 | */ | |
7125 | static int get_vmx_mem_address(struct kvm_vcpu *vcpu, | |
7126 | unsigned long exit_qualification, | |
f9eb4af6 | 7127 | u32 vmx_instruction_info, bool wr, gva_t *ret) |
19677e32 | 7128 | { |
f9eb4af6 EK |
7129 | gva_t off; |
7130 | bool exn; | |
7131 | struct kvm_segment s; | |
7132 | ||
19677e32 BD |
7133 | /* |
7134 | * According to Vol. 3B, "Information for VM Exits Due to Instruction | |
7135 | * Execution", on an exit, vmx_instruction_info holds most of the | |
7136 | * addressing components of the operand. Only the displacement part | |
7137 | * is put in exit_qualification (see 3B, "Basic VM-Exit Information"). | |
7138 | * For how an actual address is calculated from all these components, | |
7139 | * refer to Vol. 1, "Operand Addressing". | |
7140 | */ | |
7141 | int scaling = vmx_instruction_info & 3; | |
7142 | int addr_size = (vmx_instruction_info >> 7) & 7; | |
7143 | bool is_reg = vmx_instruction_info & (1u << 10); | |
7144 | int seg_reg = (vmx_instruction_info >> 15) & 7; | |
7145 | int index_reg = (vmx_instruction_info >> 18) & 0xf; | |
7146 | bool index_is_valid = !(vmx_instruction_info & (1u << 22)); | |
7147 | int base_reg = (vmx_instruction_info >> 23) & 0xf; | |
7148 | bool base_is_valid = !(vmx_instruction_info & (1u << 27)); | |
7149 | ||
7150 | if (is_reg) { | |
7151 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7152 | return 1; | |
7153 | } | |
7154 | ||
7155 | /* Addr = segment_base + offset */ | |
7156 | /* offset = base + [index * scale] + displacement */ | |
f9eb4af6 | 7157 | off = exit_qualification; /* holds the displacement */ |
19677e32 | 7158 | if (base_is_valid) |
f9eb4af6 | 7159 | off += kvm_register_read(vcpu, base_reg); |
19677e32 | 7160 | if (index_is_valid) |
f9eb4af6 EK |
7161 | off += kvm_register_read(vcpu, index_reg)<<scaling; |
7162 | vmx_get_segment(vcpu, &s, seg_reg); | |
7163 | *ret = s.base + off; | |
19677e32 BD |
7164 | |
7165 | if (addr_size == 1) /* 32 bit */ | |
7166 | *ret &= 0xffffffff; | |
7167 | ||
f9eb4af6 EK |
7168 | /* Checks for #GP/#SS exceptions. */ |
7169 | exn = false; | |
ff30ef40 QC |
7170 | if (is_long_mode(vcpu)) { |
7171 | /* Long mode: #GP(0)/#SS(0) if the memory address is in a | |
7172 | * non-canonical form. This is the only check on the memory | |
7173 | * destination for long mode! | |
7174 | */ | |
fd8cb433 | 7175 | exn = is_noncanonical_address(*ret, vcpu); |
ff30ef40 | 7176 | } else if (is_protmode(vcpu)) { |
f9eb4af6 EK |
7177 | /* Protected mode: apply checks for segment validity in the |
7178 | * following order: | |
7179 | * - segment type check (#GP(0) may be thrown) | |
7180 | * - usability check (#GP(0)/#SS(0)) | |
7181 | * - limit check (#GP(0)/#SS(0)) | |
7182 | */ | |
7183 | if (wr) | |
7184 | /* #GP(0) if the destination operand is located in a | |
7185 | * read-only data segment or any code segment. | |
7186 | */ | |
7187 | exn = ((s.type & 0xa) == 0 || (s.type & 8)); | |
7188 | else | |
7189 | /* #GP(0) if the source operand is located in an | |
7190 | * execute-only code segment | |
7191 | */ | |
7192 | exn = ((s.type & 0xa) == 8); | |
ff30ef40 QC |
7193 | if (exn) { |
7194 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
7195 | return 1; | |
7196 | } | |
f9eb4af6 EK |
7197 | /* Protected mode: #GP(0)/#SS(0) if the segment is unusable. |
7198 | */ | |
7199 | exn = (s.unusable != 0); | |
7200 | /* Protected mode: #GP(0)/#SS(0) if the memory | |
7201 | * operand is outside the segment limit. | |
7202 | */ | |
7203 | exn = exn || (off + sizeof(u64) > s.limit); | |
7204 | } | |
7205 | if (exn) { | |
7206 | kvm_queue_exception_e(vcpu, | |
7207 | seg_reg == VCPU_SREG_SS ? | |
7208 | SS_VECTOR : GP_VECTOR, | |
7209 | 0); | |
7210 | return 1; | |
7211 | } | |
7212 | ||
19677e32 BD |
7213 | return 0; |
7214 | } | |
7215 | ||
cbf71279 | 7216 | static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer) |
3573e22c BD |
7217 | { |
7218 | gva_t gva; | |
3573e22c | 7219 | struct x86_exception e; |
3573e22c BD |
7220 | |
7221 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
f9eb4af6 | 7222 | vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva)) |
3573e22c BD |
7223 | return 1; |
7224 | ||
cbf71279 RK |
7225 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer, |
7226 | sizeof(*vmpointer), &e)) { | |
3573e22c BD |
7227 | kvm_inject_page_fault(vcpu, &e); |
7228 | return 1; | |
7229 | } | |
7230 | ||
3573e22c BD |
7231 | return 0; |
7232 | } | |
7233 | ||
e29acc55 JM |
7234 | static int enter_vmx_operation(struct kvm_vcpu *vcpu) |
7235 | { | |
7236 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7237 | struct vmcs *shadow_vmcs; | |
7238 | ||
7239 | if (cpu_has_vmx_msr_bitmap()) { | |
7240 | vmx->nested.msr_bitmap = | |
7241 | (unsigned long *)__get_free_page(GFP_KERNEL); | |
7242 | if (!vmx->nested.msr_bitmap) | |
7243 | goto out_msr_bitmap; | |
7244 | } | |
7245 | ||
7246 | vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL); | |
7247 | if (!vmx->nested.cached_vmcs12) | |
7248 | goto out_cached_vmcs12; | |
7249 | ||
7250 | if (enable_shadow_vmcs) { | |
7251 | shadow_vmcs = alloc_vmcs(); | |
7252 | if (!shadow_vmcs) | |
7253 | goto out_shadow_vmcs; | |
7254 | /* mark vmcs as shadow */ | |
7255 | shadow_vmcs->revision_id |= (1u << 31); | |
7256 | /* init shadow vmcs */ | |
7257 | vmcs_clear(shadow_vmcs); | |
7258 | vmx->vmcs01.shadow_vmcs = shadow_vmcs; | |
7259 | } | |
7260 | ||
7261 | INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool)); | |
7262 | vmx->nested.vmcs02_num = 0; | |
7263 | ||
7264 | hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC, | |
7265 | HRTIMER_MODE_REL_PINNED); | |
7266 | vmx->nested.preemption_timer.function = vmx_preemption_timer_fn; | |
7267 | ||
7268 | vmx->nested.vmxon = true; | |
7269 | return 0; | |
7270 | ||
7271 | out_shadow_vmcs: | |
7272 | kfree(vmx->nested.cached_vmcs12); | |
7273 | ||
7274 | out_cached_vmcs12: | |
7275 | free_page((unsigned long)vmx->nested.msr_bitmap); | |
7276 | ||
7277 | out_msr_bitmap: | |
7278 | return -ENOMEM; | |
7279 | } | |
7280 | ||
ec378aee NHE |
7281 | /* |
7282 | * Emulate the VMXON instruction. | |
7283 | * Currently, we just remember that VMX is active, and do not save or even | |
7284 | * inspect the argument to VMXON (the so-called "VMXON pointer") because we | |
7285 | * do not currently need to store anything in that guest-allocated memory | |
7286 | * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their | |
7287 | * argument is different from the VMXON pointer (which the spec says they do). | |
7288 | */ | |
7289 | static int handle_vmon(struct kvm_vcpu *vcpu) | |
7290 | { | |
e29acc55 | 7291 | int ret; |
cbf71279 RK |
7292 | gpa_t vmptr; |
7293 | struct page *page; | |
ec378aee | 7294 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
b3897a49 NHE |
7295 | const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED |
7296 | | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
ec378aee | 7297 | |
70f3aac9 JM |
7298 | /* |
7299 | * The Intel VMX Instruction Reference lists a bunch of bits that are | |
7300 | * prerequisite to running VMXON, most notably cr4.VMXE must be set to | |
7301 | * 1 (see vmx_set_cr4() for when we allow the guest to set this). | |
7302 | * Otherwise, we should fail with #UD. But most faulting conditions | |
7303 | * have already been checked by hardware, prior to the VM-exit for | |
7304 | * VMXON. We do test guest cr4.VMXE because processor CR4 always has | |
7305 | * that bit set to 1 in non-root mode. | |
ec378aee | 7306 | */ |
70f3aac9 | 7307 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) { |
ec378aee NHE |
7308 | kvm_queue_exception(vcpu, UD_VECTOR); |
7309 | return 1; | |
7310 | } | |
7311 | ||
145c28dd AG |
7312 | if (vmx->nested.vmxon) { |
7313 | nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION); | |
6affcbed | 7314 | return kvm_skip_emulated_instruction(vcpu); |
145c28dd | 7315 | } |
b3897a49 | 7316 | |
3b84080b | 7317 | if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES) |
b3897a49 NHE |
7318 | != VMXON_NEEDED_FEATURES) { |
7319 | kvm_inject_gp(vcpu, 0); | |
7320 | return 1; | |
7321 | } | |
7322 | ||
cbf71279 | 7323 | if (nested_vmx_get_vmptr(vcpu, &vmptr)) |
21e7fbe7 | 7324 | return 1; |
cbf71279 RK |
7325 | |
7326 | /* | |
7327 | * SDM 3: 24.11.5 | |
7328 | * The first 4 bytes of VMXON region contain the supported | |
7329 | * VMCS revision identifier | |
7330 | * | |
7331 | * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case; | |
7332 | * which replaces physical address width with 32 | |
7333 | */ | |
7334 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) { | |
7335 | nested_vmx_failInvalid(vcpu); | |
7336 | return kvm_skip_emulated_instruction(vcpu); | |
7337 | } | |
7338 | ||
5e2f30b7 DH |
7339 | page = kvm_vcpu_gpa_to_page(vcpu, vmptr); |
7340 | if (is_error_page(page)) { | |
cbf71279 RK |
7341 | nested_vmx_failInvalid(vcpu); |
7342 | return kvm_skip_emulated_instruction(vcpu); | |
7343 | } | |
7344 | if (*(u32 *)kmap(page) != VMCS12_REVISION) { | |
7345 | kunmap(page); | |
53a70daf | 7346 | kvm_release_page_clean(page); |
cbf71279 RK |
7347 | nested_vmx_failInvalid(vcpu); |
7348 | return kvm_skip_emulated_instruction(vcpu); | |
7349 | } | |
7350 | kunmap(page); | |
53a70daf | 7351 | kvm_release_page_clean(page); |
cbf71279 RK |
7352 | |
7353 | vmx->nested.vmxon_ptr = vmptr; | |
e29acc55 JM |
7354 | ret = enter_vmx_operation(vcpu); |
7355 | if (ret) | |
7356 | return ret; | |
ec378aee | 7357 | |
a25eb114 | 7358 | nested_vmx_succeed(vcpu); |
6affcbed | 7359 | return kvm_skip_emulated_instruction(vcpu); |
ec378aee NHE |
7360 | } |
7361 | ||
7362 | /* | |
7363 | * Intel's VMX Instruction Reference specifies a common set of prerequisites | |
7364 | * for running VMX instructions (except VMXON, whose prerequisites are | |
7365 | * slightly different). It also specifies what exception to inject otherwise. | |
70f3aac9 JM |
7366 | * Note that many of these exceptions have priority over VM exits, so they |
7367 | * don't have to be checked again here. | |
ec378aee NHE |
7368 | */ |
7369 | static int nested_vmx_check_permission(struct kvm_vcpu *vcpu) | |
7370 | { | |
70f3aac9 | 7371 | if (!to_vmx(vcpu)->nested.vmxon) { |
ec378aee NHE |
7372 | kvm_queue_exception(vcpu, UD_VECTOR); |
7373 | return 0; | |
7374 | } | |
ec378aee NHE |
7375 | return 1; |
7376 | } | |
7377 | ||
8ca44e88 DM |
7378 | static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx) |
7379 | { | |
7380 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS); | |
7381 | vmcs_write64(VMCS_LINK_POINTER, -1ull); | |
7382 | } | |
7383 | ||
e7953d7f AG |
7384 | static inline void nested_release_vmcs12(struct vcpu_vmx *vmx) |
7385 | { | |
9a2a05b9 PB |
7386 | if (vmx->nested.current_vmptr == -1ull) |
7387 | return; | |
7388 | ||
012f83cb | 7389 | if (enable_shadow_vmcs) { |
9a2a05b9 PB |
7390 | /* copy to memory all shadowed fields in case |
7391 | they were modified */ | |
7392 | copy_shadow_to_vmcs12(vmx); | |
7393 | vmx->nested.sync_shadow_vmcs = false; | |
8ca44e88 | 7394 | vmx_disable_shadow_vmcs(vmx); |
012f83cb | 7395 | } |
705699a1 | 7396 | vmx->nested.posted_intr_nv = -1; |
4f2777bc DM |
7397 | |
7398 | /* Flush VMCS12 to guest memory */ | |
9f744c59 PB |
7399 | kvm_vcpu_write_guest_page(&vmx->vcpu, |
7400 | vmx->nested.current_vmptr >> PAGE_SHIFT, | |
7401 | vmx->nested.cached_vmcs12, 0, VMCS12_SIZE); | |
4f2777bc | 7402 | |
9a2a05b9 | 7403 | vmx->nested.current_vmptr = -1ull; |
e7953d7f AG |
7404 | } |
7405 | ||
ec378aee NHE |
7406 | /* |
7407 | * Free whatever needs to be freed from vmx->nested when L1 goes down, or | |
7408 | * just stops using VMX. | |
7409 | */ | |
7410 | static void free_nested(struct vcpu_vmx *vmx) | |
7411 | { | |
b7455825 | 7412 | if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon) |
ec378aee | 7413 | return; |
9a2a05b9 | 7414 | |
ec378aee | 7415 | vmx->nested.vmxon = false; |
b7455825 | 7416 | vmx->nested.smm.vmxon = false; |
5c614b35 | 7417 | free_vpid(vmx->nested.vpid02); |
8ca44e88 DM |
7418 | vmx->nested.posted_intr_nv = -1; |
7419 | vmx->nested.current_vmptr = -1ull; | |
d048c098 RK |
7420 | if (vmx->nested.msr_bitmap) { |
7421 | free_page((unsigned long)vmx->nested.msr_bitmap); | |
7422 | vmx->nested.msr_bitmap = NULL; | |
7423 | } | |
355f4fb1 | 7424 | if (enable_shadow_vmcs) { |
8ca44e88 | 7425 | vmx_disable_shadow_vmcs(vmx); |
355f4fb1 JM |
7426 | vmcs_clear(vmx->vmcs01.shadow_vmcs); |
7427 | free_vmcs(vmx->vmcs01.shadow_vmcs); | |
7428 | vmx->vmcs01.shadow_vmcs = NULL; | |
7429 | } | |
4f2777bc | 7430 | kfree(vmx->nested.cached_vmcs12); |
fe3ef05c NHE |
7431 | /* Unpin physical memory we referred to in current vmcs02 */ |
7432 | if (vmx->nested.apic_access_page) { | |
53a70daf | 7433 | kvm_release_page_dirty(vmx->nested.apic_access_page); |
48d89b92 | 7434 | vmx->nested.apic_access_page = NULL; |
fe3ef05c | 7435 | } |
a7c0b07d | 7436 | if (vmx->nested.virtual_apic_page) { |
53a70daf | 7437 | kvm_release_page_dirty(vmx->nested.virtual_apic_page); |
48d89b92 | 7438 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 7439 | } |
705699a1 WV |
7440 | if (vmx->nested.pi_desc_page) { |
7441 | kunmap(vmx->nested.pi_desc_page); | |
53a70daf | 7442 | kvm_release_page_dirty(vmx->nested.pi_desc_page); |
705699a1 WV |
7443 | vmx->nested.pi_desc_page = NULL; |
7444 | vmx->nested.pi_desc = NULL; | |
7445 | } | |
ff2f6fe9 NHE |
7446 | |
7447 | nested_free_all_saved_vmcss(vmx); | |
ec378aee NHE |
7448 | } |
7449 | ||
7450 | /* Emulate the VMXOFF instruction */ | |
7451 | static int handle_vmoff(struct kvm_vcpu *vcpu) | |
7452 | { | |
7453 | if (!nested_vmx_check_permission(vcpu)) | |
7454 | return 1; | |
7455 | free_nested(to_vmx(vcpu)); | |
a25eb114 | 7456 | nested_vmx_succeed(vcpu); |
6affcbed | 7457 | return kvm_skip_emulated_instruction(vcpu); |
ec378aee NHE |
7458 | } |
7459 | ||
27d6c865 NHE |
7460 | /* Emulate the VMCLEAR instruction */ |
7461 | static int handle_vmclear(struct kvm_vcpu *vcpu) | |
7462 | { | |
7463 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
587d7e72 | 7464 | u32 zero = 0; |
27d6c865 | 7465 | gpa_t vmptr; |
27d6c865 NHE |
7466 | |
7467 | if (!nested_vmx_check_permission(vcpu)) | |
7468 | return 1; | |
7469 | ||
cbf71279 | 7470 | if (nested_vmx_get_vmptr(vcpu, &vmptr)) |
27d6c865 | 7471 | return 1; |
27d6c865 | 7472 | |
cbf71279 RK |
7473 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) { |
7474 | nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS); | |
7475 | return kvm_skip_emulated_instruction(vcpu); | |
7476 | } | |
7477 | ||
7478 | if (vmptr == vmx->nested.vmxon_ptr) { | |
7479 | nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER); | |
7480 | return kvm_skip_emulated_instruction(vcpu); | |
7481 | } | |
7482 | ||
9a2a05b9 | 7483 | if (vmptr == vmx->nested.current_vmptr) |
e7953d7f | 7484 | nested_release_vmcs12(vmx); |
27d6c865 | 7485 | |
587d7e72 JM |
7486 | kvm_vcpu_write_guest(vcpu, |
7487 | vmptr + offsetof(struct vmcs12, launch_state), | |
7488 | &zero, sizeof(zero)); | |
27d6c865 NHE |
7489 | |
7490 | nested_free_vmcs02(vmx, vmptr); | |
7491 | ||
27d6c865 | 7492 | nested_vmx_succeed(vcpu); |
6affcbed | 7493 | return kvm_skip_emulated_instruction(vcpu); |
27d6c865 NHE |
7494 | } |
7495 | ||
cd232ad0 NHE |
7496 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch); |
7497 | ||
7498 | /* Emulate the VMLAUNCH instruction */ | |
7499 | static int handle_vmlaunch(struct kvm_vcpu *vcpu) | |
7500 | { | |
7501 | return nested_vmx_run(vcpu, true); | |
7502 | } | |
7503 | ||
7504 | /* Emulate the VMRESUME instruction */ | |
7505 | static int handle_vmresume(struct kvm_vcpu *vcpu) | |
7506 | { | |
7507 | ||
7508 | return nested_vmx_run(vcpu, false); | |
7509 | } | |
7510 | ||
49f705c5 NHE |
7511 | /* |
7512 | * Read a vmcs12 field. Since these can have varying lengths and we return | |
7513 | * one type, we chose the biggest type (u64) and zero-extend the return value | |
7514 | * to that size. Note that the caller, handle_vmread, might need to use only | |
7515 | * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of | |
7516 | * 64-bit fields are to be returned). | |
7517 | */ | |
a2ae9df7 PB |
7518 | static inline int vmcs12_read_any(struct kvm_vcpu *vcpu, |
7519 | unsigned long field, u64 *ret) | |
49f705c5 NHE |
7520 | { |
7521 | short offset = vmcs_field_to_offset(field); | |
7522 | char *p; | |
7523 | ||
7524 | if (offset < 0) | |
a2ae9df7 | 7525 | return offset; |
49f705c5 NHE |
7526 | |
7527 | p = ((char *)(get_vmcs12(vcpu))) + offset; | |
7528 | ||
7529 | switch (vmcs_field_type(field)) { | |
7530 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7531 | *ret = *((natural_width *)p); | |
a2ae9df7 | 7532 | return 0; |
49f705c5 NHE |
7533 | case VMCS_FIELD_TYPE_U16: |
7534 | *ret = *((u16 *)p); | |
a2ae9df7 | 7535 | return 0; |
49f705c5 NHE |
7536 | case VMCS_FIELD_TYPE_U32: |
7537 | *ret = *((u32 *)p); | |
a2ae9df7 | 7538 | return 0; |
49f705c5 NHE |
7539 | case VMCS_FIELD_TYPE_U64: |
7540 | *ret = *((u64 *)p); | |
a2ae9df7 | 7541 | return 0; |
49f705c5 | 7542 | default: |
a2ae9df7 PB |
7543 | WARN_ON(1); |
7544 | return -ENOENT; | |
49f705c5 NHE |
7545 | } |
7546 | } | |
7547 | ||
20b97fea | 7548 | |
a2ae9df7 PB |
7549 | static inline int vmcs12_write_any(struct kvm_vcpu *vcpu, |
7550 | unsigned long field, u64 field_value){ | |
20b97fea AG |
7551 | short offset = vmcs_field_to_offset(field); |
7552 | char *p = ((char *) get_vmcs12(vcpu)) + offset; | |
7553 | if (offset < 0) | |
a2ae9df7 | 7554 | return offset; |
20b97fea AG |
7555 | |
7556 | switch (vmcs_field_type(field)) { | |
7557 | case VMCS_FIELD_TYPE_U16: | |
7558 | *(u16 *)p = field_value; | |
a2ae9df7 | 7559 | return 0; |
20b97fea AG |
7560 | case VMCS_FIELD_TYPE_U32: |
7561 | *(u32 *)p = field_value; | |
a2ae9df7 | 7562 | return 0; |
20b97fea AG |
7563 | case VMCS_FIELD_TYPE_U64: |
7564 | *(u64 *)p = field_value; | |
a2ae9df7 | 7565 | return 0; |
20b97fea AG |
7566 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: |
7567 | *(natural_width *)p = field_value; | |
a2ae9df7 | 7568 | return 0; |
20b97fea | 7569 | default: |
a2ae9df7 PB |
7570 | WARN_ON(1); |
7571 | return -ENOENT; | |
20b97fea AG |
7572 | } |
7573 | ||
7574 | } | |
7575 | ||
16f5b903 AG |
7576 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx) |
7577 | { | |
7578 | int i; | |
7579 | unsigned long field; | |
7580 | u64 field_value; | |
355f4fb1 | 7581 | struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; |
c2bae893 MK |
7582 | const unsigned long *fields = shadow_read_write_fields; |
7583 | const int num_fields = max_shadow_read_write_fields; | |
16f5b903 | 7584 | |
282da870 JK |
7585 | preempt_disable(); |
7586 | ||
16f5b903 AG |
7587 | vmcs_load(shadow_vmcs); |
7588 | ||
7589 | for (i = 0; i < num_fields; i++) { | |
7590 | field = fields[i]; | |
7591 | switch (vmcs_field_type(field)) { | |
7592 | case VMCS_FIELD_TYPE_U16: | |
7593 | field_value = vmcs_read16(field); | |
7594 | break; | |
7595 | case VMCS_FIELD_TYPE_U32: | |
7596 | field_value = vmcs_read32(field); | |
7597 | break; | |
7598 | case VMCS_FIELD_TYPE_U64: | |
7599 | field_value = vmcs_read64(field); | |
7600 | break; | |
7601 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7602 | field_value = vmcs_readl(field); | |
7603 | break; | |
a2ae9df7 PB |
7604 | default: |
7605 | WARN_ON(1); | |
7606 | continue; | |
16f5b903 AG |
7607 | } |
7608 | vmcs12_write_any(&vmx->vcpu, field, field_value); | |
7609 | } | |
7610 | ||
7611 | vmcs_clear(shadow_vmcs); | |
7612 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
282da870 JK |
7613 | |
7614 | preempt_enable(); | |
16f5b903 AG |
7615 | } |
7616 | ||
c3114420 AG |
7617 | static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx) |
7618 | { | |
c2bae893 MK |
7619 | const unsigned long *fields[] = { |
7620 | shadow_read_write_fields, | |
7621 | shadow_read_only_fields | |
c3114420 | 7622 | }; |
c2bae893 | 7623 | const int max_fields[] = { |
c3114420 AG |
7624 | max_shadow_read_write_fields, |
7625 | max_shadow_read_only_fields | |
7626 | }; | |
7627 | int i, q; | |
7628 | unsigned long field; | |
7629 | u64 field_value = 0; | |
355f4fb1 | 7630 | struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; |
c3114420 AG |
7631 | |
7632 | vmcs_load(shadow_vmcs); | |
7633 | ||
c2bae893 | 7634 | for (q = 0; q < ARRAY_SIZE(fields); q++) { |
c3114420 AG |
7635 | for (i = 0; i < max_fields[q]; i++) { |
7636 | field = fields[q][i]; | |
7637 | vmcs12_read_any(&vmx->vcpu, field, &field_value); | |
7638 | ||
7639 | switch (vmcs_field_type(field)) { | |
7640 | case VMCS_FIELD_TYPE_U16: | |
7641 | vmcs_write16(field, (u16)field_value); | |
7642 | break; | |
7643 | case VMCS_FIELD_TYPE_U32: | |
7644 | vmcs_write32(field, (u32)field_value); | |
7645 | break; | |
7646 | case VMCS_FIELD_TYPE_U64: | |
7647 | vmcs_write64(field, (u64)field_value); | |
7648 | break; | |
7649 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7650 | vmcs_writel(field, (long)field_value); | |
7651 | break; | |
a2ae9df7 PB |
7652 | default: |
7653 | WARN_ON(1); | |
7654 | break; | |
c3114420 AG |
7655 | } |
7656 | } | |
7657 | } | |
7658 | ||
7659 | vmcs_clear(shadow_vmcs); | |
7660 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
7661 | } | |
7662 | ||
49f705c5 NHE |
7663 | /* |
7664 | * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was | |
7665 | * used before) all generate the same failure when it is missing. | |
7666 | */ | |
7667 | static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu) | |
7668 | { | |
7669 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7670 | if (vmx->nested.current_vmptr == -1ull) { | |
7671 | nested_vmx_failInvalid(vcpu); | |
49f705c5 NHE |
7672 | return 0; |
7673 | } | |
7674 | return 1; | |
7675 | } | |
7676 | ||
7677 | static int handle_vmread(struct kvm_vcpu *vcpu) | |
7678 | { | |
7679 | unsigned long field; | |
7680 | u64 field_value; | |
7681 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7682 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7683 | gva_t gva = 0; | |
7684 | ||
eb277562 | 7685 | if (!nested_vmx_check_permission(vcpu)) |
49f705c5 NHE |
7686 | return 1; |
7687 | ||
6affcbed KH |
7688 | if (!nested_vmx_check_vmcs12(vcpu)) |
7689 | return kvm_skip_emulated_instruction(vcpu); | |
49f705c5 NHE |
7690 | |
7691 | /* Decode instruction info and find the field to read */ | |
27e6fb5d | 7692 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 | 7693 | /* Read the field, zero-extended to a u64 field_value */ |
a2ae9df7 | 7694 | if (vmcs12_read_any(vcpu, field, &field_value) < 0) { |
49f705c5 | 7695 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
6affcbed | 7696 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7697 | } |
7698 | /* | |
7699 | * Now copy part of this value to register or memory, as requested. | |
7700 | * Note that the number of bits actually copied is 32 or 64 depending | |
7701 | * on the guest's mode (32 or 64 bit), not on the given field's length. | |
7702 | */ | |
7703 | if (vmx_instruction_info & (1u << 10)) { | |
27e6fb5d | 7704 | kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf), |
49f705c5 NHE |
7705 | field_value); |
7706 | } else { | |
7707 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7708 | vmx_instruction_info, true, &gva)) |
49f705c5 | 7709 | return 1; |
70f3aac9 | 7710 | /* _system ok, as hardware has verified cpl=0 */ |
49f705c5 NHE |
7711 | kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva, |
7712 | &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL); | |
7713 | } | |
7714 | ||
7715 | nested_vmx_succeed(vcpu); | |
6affcbed | 7716 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7717 | } |
7718 | ||
7719 | ||
7720 | static int handle_vmwrite(struct kvm_vcpu *vcpu) | |
7721 | { | |
7722 | unsigned long field; | |
7723 | gva_t gva; | |
7724 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7725 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
49f705c5 NHE |
7726 | /* The value to write might be 32 or 64 bits, depending on L1's long |
7727 | * mode, and eventually we need to write that into a field of several | |
7728 | * possible lengths. The code below first zero-extends the value to 64 | |
6a6256f9 | 7729 | * bit (field_value), and then copies only the appropriate number of |
49f705c5 NHE |
7730 | * bits into the vmcs12 field. |
7731 | */ | |
7732 | u64 field_value = 0; | |
7733 | struct x86_exception e; | |
7734 | ||
eb277562 | 7735 | if (!nested_vmx_check_permission(vcpu)) |
49f705c5 NHE |
7736 | return 1; |
7737 | ||
6affcbed KH |
7738 | if (!nested_vmx_check_vmcs12(vcpu)) |
7739 | return kvm_skip_emulated_instruction(vcpu); | |
eb277562 | 7740 | |
49f705c5 | 7741 | if (vmx_instruction_info & (1u << 10)) |
27e6fb5d | 7742 | field_value = kvm_register_readl(vcpu, |
49f705c5 NHE |
7743 | (((vmx_instruction_info) >> 3) & 0xf)); |
7744 | else { | |
7745 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7746 | vmx_instruction_info, false, &gva)) |
49f705c5 NHE |
7747 | return 1; |
7748 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, | |
27e6fb5d | 7749 | &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) { |
49f705c5 NHE |
7750 | kvm_inject_page_fault(vcpu, &e); |
7751 | return 1; | |
7752 | } | |
7753 | } | |
7754 | ||
7755 | ||
27e6fb5d | 7756 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 NHE |
7757 | if (vmcs_field_readonly(field)) { |
7758 | nested_vmx_failValid(vcpu, | |
7759 | VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT); | |
6affcbed | 7760 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7761 | } |
7762 | ||
a2ae9df7 | 7763 | if (vmcs12_write_any(vcpu, field, field_value) < 0) { |
49f705c5 | 7764 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
6affcbed | 7765 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7766 | } |
7767 | ||
7768 | nested_vmx_succeed(vcpu); | |
6affcbed | 7769 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
7770 | } |
7771 | ||
a8bc284e JM |
7772 | static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr) |
7773 | { | |
7774 | vmx->nested.current_vmptr = vmptr; | |
7775 | if (enable_shadow_vmcs) { | |
7776 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
7777 | SECONDARY_EXEC_SHADOW_VMCS); | |
7778 | vmcs_write64(VMCS_LINK_POINTER, | |
7779 | __pa(vmx->vmcs01.shadow_vmcs)); | |
7780 | vmx->nested.sync_shadow_vmcs = true; | |
7781 | } | |
7782 | } | |
7783 | ||
63846663 NHE |
7784 | /* Emulate the VMPTRLD instruction */ |
7785 | static int handle_vmptrld(struct kvm_vcpu *vcpu) | |
7786 | { | |
7787 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
63846663 | 7788 | gpa_t vmptr; |
63846663 NHE |
7789 | |
7790 | if (!nested_vmx_check_permission(vcpu)) | |
7791 | return 1; | |
7792 | ||
cbf71279 | 7793 | if (nested_vmx_get_vmptr(vcpu, &vmptr)) |
63846663 | 7794 | return 1; |
63846663 | 7795 | |
cbf71279 RK |
7796 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) { |
7797 | nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS); | |
7798 | return kvm_skip_emulated_instruction(vcpu); | |
7799 | } | |
7800 | ||
7801 | if (vmptr == vmx->nested.vmxon_ptr) { | |
7802 | nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER); | |
7803 | return kvm_skip_emulated_instruction(vcpu); | |
7804 | } | |
7805 | ||
63846663 NHE |
7806 | if (vmx->nested.current_vmptr != vmptr) { |
7807 | struct vmcs12 *new_vmcs12; | |
7808 | struct page *page; | |
5e2f30b7 DH |
7809 | page = kvm_vcpu_gpa_to_page(vcpu, vmptr); |
7810 | if (is_error_page(page)) { | |
63846663 | 7811 | nested_vmx_failInvalid(vcpu); |
6affcbed | 7812 | return kvm_skip_emulated_instruction(vcpu); |
63846663 NHE |
7813 | } |
7814 | new_vmcs12 = kmap(page); | |
7815 | if (new_vmcs12->revision_id != VMCS12_REVISION) { | |
7816 | kunmap(page); | |
53a70daf | 7817 | kvm_release_page_clean(page); |
63846663 NHE |
7818 | nested_vmx_failValid(vcpu, |
7819 | VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID); | |
6affcbed | 7820 | return kvm_skip_emulated_instruction(vcpu); |
63846663 | 7821 | } |
63846663 | 7822 | |
9a2a05b9 | 7823 | nested_release_vmcs12(vmx); |
4f2777bc DM |
7824 | /* |
7825 | * Load VMCS12 from guest memory since it is not already | |
7826 | * cached. | |
7827 | */ | |
9f744c59 PB |
7828 | memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE); |
7829 | kunmap(page); | |
53a70daf | 7830 | kvm_release_page_clean(page); |
9f744c59 | 7831 | |
a8bc284e | 7832 | set_current_vmptr(vmx, vmptr); |
63846663 NHE |
7833 | } |
7834 | ||
7835 | nested_vmx_succeed(vcpu); | |
6affcbed | 7836 | return kvm_skip_emulated_instruction(vcpu); |
63846663 NHE |
7837 | } |
7838 | ||
6a4d7550 NHE |
7839 | /* Emulate the VMPTRST instruction */ |
7840 | static int handle_vmptrst(struct kvm_vcpu *vcpu) | |
7841 | { | |
7842 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7843 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7844 | gva_t vmcs_gva; | |
7845 | struct x86_exception e; | |
7846 | ||
7847 | if (!nested_vmx_check_permission(vcpu)) | |
7848 | return 1; | |
7849 | ||
7850 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 7851 | vmx_instruction_info, true, &vmcs_gva)) |
6a4d7550 | 7852 | return 1; |
70f3aac9 | 7853 | /* ok to use *_system, as hardware has verified cpl=0 */ |
6a4d7550 NHE |
7854 | if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva, |
7855 | (void *)&to_vmx(vcpu)->nested.current_vmptr, | |
7856 | sizeof(u64), &e)) { | |
7857 | kvm_inject_page_fault(vcpu, &e); | |
7858 | return 1; | |
7859 | } | |
7860 | nested_vmx_succeed(vcpu); | |
6affcbed | 7861 | return kvm_skip_emulated_instruction(vcpu); |
6a4d7550 NHE |
7862 | } |
7863 | ||
bfd0a56b NHE |
7864 | /* Emulate the INVEPT instruction */ |
7865 | static int handle_invept(struct kvm_vcpu *vcpu) | |
7866 | { | |
b9c237bb | 7867 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
bfd0a56b NHE |
7868 | u32 vmx_instruction_info, types; |
7869 | unsigned long type; | |
7870 | gva_t gva; | |
7871 | struct x86_exception e; | |
7872 | struct { | |
7873 | u64 eptp, gpa; | |
7874 | } operand; | |
bfd0a56b | 7875 | |
b9c237bb WV |
7876 | if (!(vmx->nested.nested_vmx_secondary_ctls_high & |
7877 | SECONDARY_EXEC_ENABLE_EPT) || | |
7878 | !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) { | |
bfd0a56b NHE |
7879 | kvm_queue_exception(vcpu, UD_VECTOR); |
7880 | return 1; | |
7881 | } | |
7882 | ||
7883 | if (!nested_vmx_check_permission(vcpu)) | |
7884 | return 1; | |
7885 | ||
bfd0a56b | 7886 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); |
27e6fb5d | 7887 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); |
bfd0a56b | 7888 | |
b9c237bb | 7889 | types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6; |
bfd0a56b | 7890 | |
85c856b3 | 7891 | if (type >= 32 || !(types & (1 << type))) { |
bfd0a56b NHE |
7892 | nested_vmx_failValid(vcpu, |
7893 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 7894 | return kvm_skip_emulated_instruction(vcpu); |
bfd0a56b NHE |
7895 | } |
7896 | ||
7897 | /* According to the Intel VMX instruction reference, the memory | |
7898 | * operand is read even if it isn't needed (e.g., for type==global) | |
7899 | */ | |
7900 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
f9eb4af6 | 7901 | vmx_instruction_info, false, &gva)) |
bfd0a56b NHE |
7902 | return 1; |
7903 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand, | |
7904 | sizeof(operand), &e)) { | |
7905 | kvm_inject_page_fault(vcpu, &e); | |
7906 | return 1; | |
7907 | } | |
7908 | ||
7909 | switch (type) { | |
bfd0a56b | 7910 | case VMX_EPT_EXTENT_GLOBAL: |
45e11817 BD |
7911 | /* |
7912 | * TODO: track mappings and invalidate | |
7913 | * single context requests appropriately | |
7914 | */ | |
7915 | case VMX_EPT_EXTENT_CONTEXT: | |
bfd0a56b | 7916 | kvm_mmu_sync_roots(vcpu); |
77c3913b | 7917 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
bfd0a56b NHE |
7918 | nested_vmx_succeed(vcpu); |
7919 | break; | |
7920 | default: | |
7921 | BUG_ON(1); | |
7922 | break; | |
7923 | } | |
7924 | ||
6affcbed | 7925 | return kvm_skip_emulated_instruction(vcpu); |
bfd0a56b NHE |
7926 | } |
7927 | ||
a642fc30 PM |
7928 | static int handle_invvpid(struct kvm_vcpu *vcpu) |
7929 | { | |
99b83ac8 WL |
7930 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
7931 | u32 vmx_instruction_info; | |
7932 | unsigned long type, types; | |
7933 | gva_t gva; | |
7934 | struct x86_exception e; | |
40352605 JM |
7935 | struct { |
7936 | u64 vpid; | |
7937 | u64 gla; | |
7938 | } operand; | |
99b83ac8 WL |
7939 | |
7940 | if (!(vmx->nested.nested_vmx_secondary_ctls_high & | |
7941 | SECONDARY_EXEC_ENABLE_VPID) || | |
7942 | !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) { | |
7943 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7944 | return 1; | |
7945 | } | |
7946 | ||
7947 | if (!nested_vmx_check_permission(vcpu)) | |
7948 | return 1; | |
7949 | ||
7950 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
7951 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); | |
7952 | ||
bcdde302 JD |
7953 | types = (vmx->nested.nested_vmx_vpid_caps & |
7954 | VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8; | |
99b83ac8 | 7955 | |
85c856b3 | 7956 | if (type >= 32 || !(types & (1 << type))) { |
99b83ac8 WL |
7957 | nested_vmx_failValid(vcpu, |
7958 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 7959 | return kvm_skip_emulated_instruction(vcpu); |
99b83ac8 WL |
7960 | } |
7961 | ||
7962 | /* according to the intel vmx instruction reference, the memory | |
7963 | * operand is read even if it isn't needed (e.g., for type==global) | |
7964 | */ | |
7965 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
7966 | vmx_instruction_info, false, &gva)) | |
7967 | return 1; | |
40352605 JM |
7968 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand, |
7969 | sizeof(operand), &e)) { | |
99b83ac8 WL |
7970 | kvm_inject_page_fault(vcpu, &e); |
7971 | return 1; | |
7972 | } | |
40352605 JM |
7973 | if (operand.vpid >> 16) { |
7974 | nested_vmx_failValid(vcpu, | |
7975 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
7976 | return kvm_skip_emulated_instruction(vcpu); | |
7977 | } | |
99b83ac8 WL |
7978 | |
7979 | switch (type) { | |
bcdde302 | 7980 | case VMX_VPID_EXTENT_INDIVIDUAL_ADDR: |
fd8cb433 | 7981 | if (is_noncanonical_address(operand.gla, vcpu)) { |
40352605 JM |
7982 | nested_vmx_failValid(vcpu, |
7983 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
7984 | return kvm_skip_emulated_instruction(vcpu); | |
7985 | } | |
7986 | /* fall through */ | |
ef697a71 | 7987 | case VMX_VPID_EXTENT_SINGLE_CONTEXT: |
bcdde302 | 7988 | case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL: |
40352605 | 7989 | if (!operand.vpid) { |
bcdde302 JD |
7990 | nested_vmx_failValid(vcpu, |
7991 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 7992 | return kvm_skip_emulated_instruction(vcpu); |
bcdde302 JD |
7993 | } |
7994 | break; | |
99b83ac8 | 7995 | case VMX_VPID_EXTENT_ALL_CONTEXT: |
99b83ac8 WL |
7996 | break; |
7997 | default: | |
bcdde302 | 7998 | WARN_ON_ONCE(1); |
6affcbed | 7999 | return kvm_skip_emulated_instruction(vcpu); |
99b83ac8 WL |
8000 | } |
8001 | ||
bcdde302 JD |
8002 | __vmx_flush_tlb(vcpu, vmx->nested.vpid02); |
8003 | nested_vmx_succeed(vcpu); | |
8004 | ||
6affcbed | 8005 | return kvm_skip_emulated_instruction(vcpu); |
a642fc30 PM |
8006 | } |
8007 | ||
843e4330 KH |
8008 | static int handle_pml_full(struct kvm_vcpu *vcpu) |
8009 | { | |
8010 | unsigned long exit_qualification; | |
8011 | ||
8012 | trace_kvm_pml_full(vcpu->vcpu_id); | |
8013 | ||
8014 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
8015 | ||
8016 | /* | |
8017 | * PML buffer FULL happened while executing iret from NMI, | |
8018 | * "blocked by NMI" bit has to be set before next VM entry. | |
8019 | */ | |
8020 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && | |
d02fcf50 | 8021 | enable_vnmi && |
843e4330 KH |
8022 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) |
8023 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
8024 | GUEST_INTR_STATE_NMI); | |
8025 | ||
8026 | /* | |
8027 | * PML buffer already flushed at beginning of VMEXIT. Nothing to do | |
8028 | * here.., and there's no userspace involvement needed for PML. | |
8029 | */ | |
8030 | return 1; | |
8031 | } | |
8032 | ||
64672c95 YJ |
8033 | static int handle_preemption_timer(struct kvm_vcpu *vcpu) |
8034 | { | |
8035 | kvm_lapic_expired_hv_timer(vcpu); | |
8036 | return 1; | |
8037 | } | |
8038 | ||
41ab9372 BD |
8039 | static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address) |
8040 | { | |
8041 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
41ab9372 BD |
8042 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
8043 | ||
8044 | /* Check for memory type validity */ | |
bb97a016 DH |
8045 | switch (address & VMX_EPTP_MT_MASK) { |
8046 | case VMX_EPTP_MT_UC: | |
41ab9372 BD |
8047 | if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_UC_BIT)) |
8048 | return false; | |
8049 | break; | |
bb97a016 | 8050 | case VMX_EPTP_MT_WB: |
41ab9372 BD |
8051 | if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_WB_BIT)) |
8052 | return false; | |
8053 | break; | |
8054 | default: | |
8055 | return false; | |
8056 | } | |
8057 | ||
bb97a016 DH |
8058 | /* only 4 levels page-walk length are valid */ |
8059 | if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4) | |
41ab9372 BD |
8060 | return false; |
8061 | ||
8062 | /* Reserved bits should not be set */ | |
8063 | if (address >> maxphyaddr || ((address >> 7) & 0x1f)) | |
8064 | return false; | |
8065 | ||
8066 | /* AD, if set, should be supported */ | |
bb97a016 | 8067 | if (address & VMX_EPTP_AD_ENABLE_BIT) { |
41ab9372 BD |
8068 | if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPT_AD_BIT)) |
8069 | return false; | |
8070 | } | |
8071 | ||
8072 | return true; | |
8073 | } | |
8074 | ||
8075 | static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu, | |
8076 | struct vmcs12 *vmcs12) | |
8077 | { | |
8078 | u32 index = vcpu->arch.regs[VCPU_REGS_RCX]; | |
8079 | u64 address; | |
8080 | bool accessed_dirty; | |
8081 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; | |
8082 | ||
8083 | if (!nested_cpu_has_eptp_switching(vmcs12) || | |
8084 | !nested_cpu_has_ept(vmcs12)) | |
8085 | return 1; | |
8086 | ||
8087 | if (index >= VMFUNC_EPTP_ENTRIES) | |
8088 | return 1; | |
8089 | ||
8090 | ||
8091 | if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT, | |
8092 | &address, index * 8, 8)) | |
8093 | return 1; | |
8094 | ||
bb97a016 | 8095 | accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT); |
41ab9372 BD |
8096 | |
8097 | /* | |
8098 | * If the (L2) guest does a vmfunc to the currently | |
8099 | * active ept pointer, we don't have to do anything else | |
8100 | */ | |
8101 | if (vmcs12->ept_pointer != address) { | |
8102 | if (!valid_ept_address(vcpu, address)) | |
8103 | return 1; | |
8104 | ||
8105 | kvm_mmu_unload(vcpu); | |
8106 | mmu->ept_ad = accessed_dirty; | |
8107 | mmu->base_role.ad_disabled = !accessed_dirty; | |
8108 | vmcs12->ept_pointer = address; | |
8109 | /* | |
8110 | * TODO: Check what's the correct approach in case | |
8111 | * mmu reload fails. Currently, we just let the next | |
8112 | * reload potentially fail | |
8113 | */ | |
8114 | kvm_mmu_reload(vcpu); | |
8115 | } | |
8116 | ||
8117 | return 0; | |
8118 | } | |
8119 | ||
2a499e49 BD |
8120 | static int handle_vmfunc(struct kvm_vcpu *vcpu) |
8121 | { | |
27c42a1b BD |
8122 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
8123 | struct vmcs12 *vmcs12; | |
8124 | u32 function = vcpu->arch.regs[VCPU_REGS_RAX]; | |
8125 | ||
8126 | /* | |
8127 | * VMFUNC is only supported for nested guests, but we always enable the | |
8128 | * secondary control for simplicity; for non-nested mode, fake that we | |
8129 | * didn't by injecting #UD. | |
8130 | */ | |
8131 | if (!is_guest_mode(vcpu)) { | |
8132 | kvm_queue_exception(vcpu, UD_VECTOR); | |
8133 | return 1; | |
8134 | } | |
8135 | ||
8136 | vmcs12 = get_vmcs12(vcpu); | |
8137 | if ((vmcs12->vm_function_control & (1 << function)) == 0) | |
8138 | goto fail; | |
41ab9372 BD |
8139 | |
8140 | switch (function) { | |
8141 | case 0: | |
8142 | if (nested_vmx_eptp_switching(vcpu, vmcs12)) | |
8143 | goto fail; | |
8144 | break; | |
8145 | default: | |
8146 | goto fail; | |
8147 | } | |
8148 | return kvm_skip_emulated_instruction(vcpu); | |
27c42a1b BD |
8149 | |
8150 | fail: | |
8151 | nested_vmx_vmexit(vcpu, vmx->exit_reason, | |
8152 | vmcs_read32(VM_EXIT_INTR_INFO), | |
8153 | vmcs_readl(EXIT_QUALIFICATION)); | |
2a499e49 BD |
8154 | return 1; |
8155 | } | |
8156 | ||
6aa8b732 AK |
8157 | /* |
8158 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
8159 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
8160 | * to be done to userspace and return 0. | |
8161 | */ | |
772e0318 | 8162 | static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { |
6aa8b732 AK |
8163 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, |
8164 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 8165 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
f08864b4 | 8166 | [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, |
6aa8b732 | 8167 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
8168 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
8169 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
8170 | [EXIT_REASON_CPUID] = handle_cpuid, | |
8171 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
8172 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
8173 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
8174 | [EXIT_REASON_HLT] = handle_halt, | |
ec25d5e6 | 8175 | [EXIT_REASON_INVD] = handle_invd, |
a7052897 | 8176 | [EXIT_REASON_INVLPG] = handle_invlpg, |
fee84b07 | 8177 | [EXIT_REASON_RDPMC] = handle_rdpmc, |
c21415e8 | 8178 | [EXIT_REASON_VMCALL] = handle_vmcall, |
27d6c865 | 8179 | [EXIT_REASON_VMCLEAR] = handle_vmclear, |
cd232ad0 | 8180 | [EXIT_REASON_VMLAUNCH] = handle_vmlaunch, |
63846663 | 8181 | [EXIT_REASON_VMPTRLD] = handle_vmptrld, |
6a4d7550 | 8182 | [EXIT_REASON_VMPTRST] = handle_vmptrst, |
49f705c5 | 8183 | [EXIT_REASON_VMREAD] = handle_vmread, |
cd232ad0 | 8184 | [EXIT_REASON_VMRESUME] = handle_vmresume, |
49f705c5 | 8185 | [EXIT_REASON_VMWRITE] = handle_vmwrite, |
ec378aee NHE |
8186 | [EXIT_REASON_VMOFF] = handle_vmoff, |
8187 | [EXIT_REASON_VMON] = handle_vmon, | |
f78e0e2e SY |
8188 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
8189 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
83d4c286 | 8190 | [EXIT_REASON_APIC_WRITE] = handle_apic_write, |
c7c9c56c | 8191 | [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, |
e5edaa01 | 8192 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
2acf923e | 8193 | [EXIT_REASON_XSETBV] = handle_xsetbv, |
37817f29 | 8194 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
a0861c02 | 8195 | [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, |
68f89400 MT |
8196 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
8197 | [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, | |
4b8d54f9 | 8198 | [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, |
87c00572 | 8199 | [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, |
5f3d45e7 | 8200 | [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, |
87c00572 | 8201 | [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, |
bfd0a56b | 8202 | [EXIT_REASON_INVEPT] = handle_invept, |
a642fc30 | 8203 | [EXIT_REASON_INVVPID] = handle_invvpid, |
45ec368c | 8204 | [EXIT_REASON_RDRAND] = handle_invalid_op, |
75f4fc8d | 8205 | [EXIT_REASON_RDSEED] = handle_invalid_op, |
f53cd63c WL |
8206 | [EXIT_REASON_XSAVES] = handle_xsaves, |
8207 | [EXIT_REASON_XRSTORS] = handle_xrstors, | |
843e4330 | 8208 | [EXIT_REASON_PML_FULL] = handle_pml_full, |
2a499e49 | 8209 | [EXIT_REASON_VMFUNC] = handle_vmfunc, |
64672c95 | 8210 | [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, |
6aa8b732 AK |
8211 | }; |
8212 | ||
8213 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 8214 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 | 8215 | |
908a7bdd JK |
8216 | static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu, |
8217 | struct vmcs12 *vmcs12) | |
8218 | { | |
8219 | unsigned long exit_qualification; | |
8220 | gpa_t bitmap, last_bitmap; | |
8221 | unsigned int port; | |
8222 | int size; | |
8223 | u8 b; | |
8224 | ||
908a7bdd | 8225 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) |
2f0a6397 | 8226 | return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING); |
908a7bdd JK |
8227 | |
8228 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
8229 | ||
8230 | port = exit_qualification >> 16; | |
8231 | size = (exit_qualification & 7) + 1; | |
8232 | ||
8233 | last_bitmap = (gpa_t)-1; | |
8234 | b = -1; | |
8235 | ||
8236 | while (size > 0) { | |
8237 | if (port < 0x8000) | |
8238 | bitmap = vmcs12->io_bitmap_a; | |
8239 | else if (port < 0x10000) | |
8240 | bitmap = vmcs12->io_bitmap_b; | |
8241 | else | |
1d804d07 | 8242 | return true; |
908a7bdd JK |
8243 | bitmap += (port & 0x7fff) / 8; |
8244 | ||
8245 | if (last_bitmap != bitmap) | |
54bf36aa | 8246 | if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1)) |
1d804d07 | 8247 | return true; |
908a7bdd | 8248 | if (b & (1 << (port & 7))) |
1d804d07 | 8249 | return true; |
908a7bdd JK |
8250 | |
8251 | port++; | |
8252 | size--; | |
8253 | last_bitmap = bitmap; | |
8254 | } | |
8255 | ||
1d804d07 | 8256 | return false; |
908a7bdd JK |
8257 | } |
8258 | ||
644d711a NHE |
8259 | /* |
8260 | * Return 1 if we should exit from L2 to L1 to handle an MSR access access, | |
8261 | * rather than handle it ourselves in L0. I.e., check whether L1 expressed | |
8262 | * disinterest in the current event (read or write a specific MSR) by using an | |
8263 | * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps. | |
8264 | */ | |
8265 | static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu, | |
8266 | struct vmcs12 *vmcs12, u32 exit_reason) | |
8267 | { | |
8268 | u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX]; | |
8269 | gpa_t bitmap; | |
8270 | ||
cbd29cb6 | 8271 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) |
1d804d07 | 8272 | return true; |
644d711a NHE |
8273 | |
8274 | /* | |
8275 | * The MSR_BITMAP page is divided into four 1024-byte bitmaps, | |
8276 | * for the four combinations of read/write and low/high MSR numbers. | |
8277 | * First we need to figure out which of the four to use: | |
8278 | */ | |
8279 | bitmap = vmcs12->msr_bitmap; | |
8280 | if (exit_reason == EXIT_REASON_MSR_WRITE) | |
8281 | bitmap += 2048; | |
8282 | if (msr_index >= 0xc0000000) { | |
8283 | msr_index -= 0xc0000000; | |
8284 | bitmap += 1024; | |
8285 | } | |
8286 | ||
8287 | /* Then read the msr_index'th bit from this bitmap: */ | |
8288 | if (msr_index < 1024*8) { | |
8289 | unsigned char b; | |
54bf36aa | 8290 | if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1)) |
1d804d07 | 8291 | return true; |
644d711a NHE |
8292 | return 1 & (b >> (msr_index & 7)); |
8293 | } else | |
1d804d07 | 8294 | return true; /* let L1 handle the wrong parameter */ |
644d711a NHE |
8295 | } |
8296 | ||
8297 | /* | |
8298 | * Return 1 if we should exit from L2 to L1 to handle a CR access exit, | |
8299 | * rather than handle it ourselves in L0. I.e., check if L1 wanted to | |
8300 | * intercept (via guest_host_mask etc.) the current event. | |
8301 | */ | |
8302 | static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu, | |
8303 | struct vmcs12 *vmcs12) | |
8304 | { | |
8305 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
8306 | int cr = exit_qualification & 15; | |
e1d39b17 JS |
8307 | int reg; |
8308 | unsigned long val; | |
644d711a NHE |
8309 | |
8310 | switch ((exit_qualification >> 4) & 3) { | |
8311 | case 0: /* mov to cr */ | |
e1d39b17 JS |
8312 | reg = (exit_qualification >> 8) & 15; |
8313 | val = kvm_register_readl(vcpu, reg); | |
644d711a NHE |
8314 | switch (cr) { |
8315 | case 0: | |
8316 | if (vmcs12->cr0_guest_host_mask & | |
8317 | (val ^ vmcs12->cr0_read_shadow)) | |
1d804d07 | 8318 | return true; |
644d711a NHE |
8319 | break; |
8320 | case 3: | |
8321 | if ((vmcs12->cr3_target_count >= 1 && | |
8322 | vmcs12->cr3_target_value0 == val) || | |
8323 | (vmcs12->cr3_target_count >= 2 && | |
8324 | vmcs12->cr3_target_value1 == val) || | |
8325 | (vmcs12->cr3_target_count >= 3 && | |
8326 | vmcs12->cr3_target_value2 == val) || | |
8327 | (vmcs12->cr3_target_count >= 4 && | |
8328 | vmcs12->cr3_target_value3 == val)) | |
1d804d07 | 8329 | return false; |
644d711a | 8330 | if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING)) |
1d804d07 | 8331 | return true; |
644d711a NHE |
8332 | break; |
8333 | case 4: | |
8334 | if (vmcs12->cr4_guest_host_mask & | |
8335 | (vmcs12->cr4_read_shadow ^ val)) | |
1d804d07 | 8336 | return true; |
644d711a NHE |
8337 | break; |
8338 | case 8: | |
8339 | if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING)) | |
1d804d07 | 8340 | return true; |
644d711a NHE |
8341 | break; |
8342 | } | |
8343 | break; | |
8344 | case 2: /* clts */ | |
8345 | if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) && | |
8346 | (vmcs12->cr0_read_shadow & X86_CR0_TS)) | |
1d804d07 | 8347 | return true; |
644d711a NHE |
8348 | break; |
8349 | case 1: /* mov from cr */ | |
8350 | switch (cr) { | |
8351 | case 3: | |
8352 | if (vmcs12->cpu_based_vm_exec_control & | |
8353 | CPU_BASED_CR3_STORE_EXITING) | |
1d804d07 | 8354 | return true; |
644d711a NHE |
8355 | break; |
8356 | case 8: | |
8357 | if (vmcs12->cpu_based_vm_exec_control & | |
8358 | CPU_BASED_CR8_STORE_EXITING) | |
1d804d07 | 8359 | return true; |
644d711a NHE |
8360 | break; |
8361 | } | |
8362 | break; | |
8363 | case 3: /* lmsw */ | |
8364 | /* | |
8365 | * lmsw can change bits 1..3 of cr0, and only set bit 0 of | |
8366 | * cr0. Other attempted changes are ignored, with no exit. | |
8367 | */ | |
e1d39b17 | 8368 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
644d711a NHE |
8369 | if (vmcs12->cr0_guest_host_mask & 0xe & |
8370 | (val ^ vmcs12->cr0_read_shadow)) | |
1d804d07 | 8371 | return true; |
644d711a NHE |
8372 | if ((vmcs12->cr0_guest_host_mask & 0x1) && |
8373 | !(vmcs12->cr0_read_shadow & 0x1) && | |
8374 | (val & 0x1)) | |
1d804d07 | 8375 | return true; |
644d711a NHE |
8376 | break; |
8377 | } | |
1d804d07 | 8378 | return false; |
644d711a NHE |
8379 | } |
8380 | ||
8381 | /* | |
8382 | * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we | |
8383 | * should handle it ourselves in L0 (and then continue L2). Only call this | |
8384 | * when in is_guest_mode (L2). | |
8385 | */ | |
7313c698 | 8386 | static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason) |
644d711a | 8387 | { |
644d711a NHE |
8388 | u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
8389 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8390 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
8391 | ||
4f350c6d JM |
8392 | if (vmx->nested.nested_run_pending) |
8393 | return false; | |
8394 | ||
8395 | if (unlikely(vmx->fail)) { | |
8396 | pr_info_ratelimited("%s failed vm entry %x\n", __func__, | |
8397 | vmcs_read32(VM_INSTRUCTION_ERROR)); | |
8398 | return true; | |
8399 | } | |
542060ea | 8400 | |
c9f04407 DM |
8401 | /* |
8402 | * The host physical addresses of some pages of guest memory | |
8403 | * are loaded into VMCS02 (e.g. L1's Virtual APIC Page). The CPU | |
8404 | * may write to these pages via their host physical address while | |
8405 | * L2 is running, bypassing any address-translation-based dirty | |
8406 | * tracking (e.g. EPT write protection). | |
8407 | * | |
8408 | * Mark them dirty on every exit from L2 to prevent them from | |
8409 | * getting out of sync with dirty tracking. | |
8410 | */ | |
8411 | nested_mark_vmcs12_pages_dirty(vcpu); | |
8412 | ||
4f350c6d JM |
8413 | trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason, |
8414 | vmcs_readl(EXIT_QUALIFICATION), | |
8415 | vmx->idt_vectoring_info, | |
8416 | intr_info, | |
8417 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
8418 | KVM_ISA_VMX); | |
644d711a NHE |
8419 | |
8420 | switch (exit_reason) { | |
8421 | case EXIT_REASON_EXCEPTION_NMI: | |
ef85b673 | 8422 | if (is_nmi(intr_info)) |
1d804d07 | 8423 | return false; |
644d711a | 8424 | else if (is_page_fault(intr_info)) |
52a5c155 | 8425 | return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept; |
e504c909 | 8426 | else if (is_no_device(intr_info) && |
ccf9844e | 8427 | !(vmcs12->guest_cr0 & X86_CR0_TS)) |
1d804d07 | 8428 | return false; |
6f05485d JK |
8429 | else if (is_debug(intr_info) && |
8430 | vcpu->guest_debug & | |
8431 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
8432 | return false; | |
8433 | else if (is_breakpoint(intr_info) && | |
8434 | vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) | |
8435 | return false; | |
644d711a NHE |
8436 | return vmcs12->exception_bitmap & |
8437 | (1u << (intr_info & INTR_INFO_VECTOR_MASK)); | |
8438 | case EXIT_REASON_EXTERNAL_INTERRUPT: | |
1d804d07 | 8439 | return false; |
644d711a | 8440 | case EXIT_REASON_TRIPLE_FAULT: |
1d804d07 | 8441 | return true; |
644d711a | 8442 | case EXIT_REASON_PENDING_INTERRUPT: |
3b656cf7 | 8443 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING); |
644d711a | 8444 | case EXIT_REASON_NMI_WINDOW: |
3b656cf7 | 8445 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING); |
644d711a | 8446 | case EXIT_REASON_TASK_SWITCH: |
1d804d07 | 8447 | return true; |
644d711a | 8448 | case EXIT_REASON_CPUID: |
1d804d07 | 8449 | return true; |
644d711a NHE |
8450 | case EXIT_REASON_HLT: |
8451 | return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING); | |
8452 | case EXIT_REASON_INVD: | |
1d804d07 | 8453 | return true; |
644d711a NHE |
8454 | case EXIT_REASON_INVLPG: |
8455 | return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); | |
8456 | case EXIT_REASON_RDPMC: | |
8457 | return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING); | |
a5f46457 | 8458 | case EXIT_REASON_RDRAND: |
736fdf72 | 8459 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING); |
a5f46457 | 8460 | case EXIT_REASON_RDSEED: |
736fdf72 | 8461 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING); |
b3a2a907 | 8462 | case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP: |
644d711a NHE |
8463 | return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING); |
8464 | case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR: | |
8465 | case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD: | |
8466 | case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD: | |
8467 | case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE: | |
8468 | case EXIT_REASON_VMOFF: case EXIT_REASON_VMON: | |
a642fc30 | 8469 | case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID: |
644d711a NHE |
8470 | /* |
8471 | * VMX instructions trap unconditionally. This allows L1 to | |
8472 | * emulate them for its L2 guest, i.e., allows 3-level nesting! | |
8473 | */ | |
1d804d07 | 8474 | return true; |
644d711a NHE |
8475 | case EXIT_REASON_CR_ACCESS: |
8476 | return nested_vmx_exit_handled_cr(vcpu, vmcs12); | |
8477 | case EXIT_REASON_DR_ACCESS: | |
8478 | return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING); | |
8479 | case EXIT_REASON_IO_INSTRUCTION: | |
908a7bdd | 8480 | return nested_vmx_exit_handled_io(vcpu, vmcs12); |
1b07304c PB |
8481 | case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR: |
8482 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC); | |
644d711a NHE |
8483 | case EXIT_REASON_MSR_READ: |
8484 | case EXIT_REASON_MSR_WRITE: | |
8485 | return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason); | |
8486 | case EXIT_REASON_INVALID_STATE: | |
1d804d07 | 8487 | return true; |
644d711a NHE |
8488 | case EXIT_REASON_MWAIT_INSTRUCTION: |
8489 | return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING); | |
5f3d45e7 MD |
8490 | case EXIT_REASON_MONITOR_TRAP_FLAG: |
8491 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG); | |
644d711a NHE |
8492 | case EXIT_REASON_MONITOR_INSTRUCTION: |
8493 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING); | |
8494 | case EXIT_REASON_PAUSE_INSTRUCTION: | |
8495 | return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) || | |
8496 | nested_cpu_has2(vmcs12, | |
8497 | SECONDARY_EXEC_PAUSE_LOOP_EXITING); | |
8498 | case EXIT_REASON_MCE_DURING_VMENTRY: | |
1d804d07 | 8499 | return false; |
644d711a | 8500 | case EXIT_REASON_TPR_BELOW_THRESHOLD: |
a7c0b07d | 8501 | return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW); |
644d711a NHE |
8502 | case EXIT_REASON_APIC_ACCESS: |
8503 | return nested_cpu_has2(vmcs12, | |
8504 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
82f0dd4b | 8505 | case EXIT_REASON_APIC_WRITE: |
608406e2 WV |
8506 | case EXIT_REASON_EOI_INDUCED: |
8507 | /* apic_write and eoi_induced should exit unconditionally. */ | |
1d804d07 | 8508 | return true; |
644d711a | 8509 | case EXIT_REASON_EPT_VIOLATION: |
2b1be677 NHE |
8510 | /* |
8511 | * L0 always deals with the EPT violation. If nested EPT is | |
8512 | * used, and the nested mmu code discovers that the address is | |
8513 | * missing in the guest EPT table (EPT12), the EPT violation | |
8514 | * will be injected with nested_ept_inject_page_fault() | |
8515 | */ | |
1d804d07 | 8516 | return false; |
644d711a | 8517 | case EXIT_REASON_EPT_MISCONFIG: |
2b1be677 NHE |
8518 | /* |
8519 | * L2 never uses directly L1's EPT, but rather L0's own EPT | |
8520 | * table (shadow on EPT) or a merged EPT table that L0 built | |
8521 | * (EPT on EPT). So any problems with the structure of the | |
8522 | * table is L0's fault. | |
8523 | */ | |
1d804d07 | 8524 | return false; |
90a2db6d PB |
8525 | case EXIT_REASON_INVPCID: |
8526 | return | |
8527 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) && | |
8528 | nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); | |
644d711a NHE |
8529 | case EXIT_REASON_WBINVD: |
8530 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING); | |
8531 | case EXIT_REASON_XSETBV: | |
1d804d07 | 8532 | return true; |
81dc01f7 WL |
8533 | case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS: |
8534 | /* | |
8535 | * This should never happen, since it is not possible to | |
8536 | * set XSS to a non-zero value---neither in L1 nor in L2. | |
8537 | * If if it were, XSS would have to be checked against | |
8538 | * the XSS exit bitmap in vmcs12. | |
8539 | */ | |
8540 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES); | |
55123e3c WL |
8541 | case EXIT_REASON_PREEMPTION_TIMER: |
8542 | return false; | |
ab007cc9 | 8543 | case EXIT_REASON_PML_FULL: |
03efce6f | 8544 | /* We emulate PML support to L1. */ |
ab007cc9 | 8545 | return false; |
2a499e49 BD |
8546 | case EXIT_REASON_VMFUNC: |
8547 | /* VM functions are emulated through L2->L0 vmexits. */ | |
8548 | return false; | |
644d711a | 8549 | default: |
1d804d07 | 8550 | return true; |
644d711a NHE |
8551 | } |
8552 | } | |
8553 | ||
7313c698 PB |
8554 | static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason) |
8555 | { | |
8556 | u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
8557 | ||
8558 | /* | |
8559 | * At this point, the exit interruption info in exit_intr_info | |
8560 | * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT | |
8561 | * we need to query the in-kernel LAPIC. | |
8562 | */ | |
8563 | WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT); | |
8564 | if ((exit_intr_info & | |
8565 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) == | |
8566 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) { | |
8567 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
8568 | vmcs12->vm_exit_intr_error_code = | |
8569 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE); | |
8570 | } | |
8571 | ||
8572 | nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info, | |
8573 | vmcs_readl(EXIT_QUALIFICATION)); | |
8574 | return 1; | |
8575 | } | |
8576 | ||
586f9607 AK |
8577 | static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
8578 | { | |
8579 | *info1 = vmcs_readl(EXIT_QUALIFICATION); | |
8580 | *info2 = vmcs_read32(VM_EXIT_INTR_INFO); | |
8581 | } | |
8582 | ||
a3eaa864 | 8583 | static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) |
843e4330 | 8584 | { |
a3eaa864 KH |
8585 | if (vmx->pml_pg) { |
8586 | __free_page(vmx->pml_pg); | |
8587 | vmx->pml_pg = NULL; | |
8588 | } | |
843e4330 KH |
8589 | } |
8590 | ||
54bf36aa | 8591 | static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) |
843e4330 | 8592 | { |
54bf36aa | 8593 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
843e4330 KH |
8594 | u64 *pml_buf; |
8595 | u16 pml_idx; | |
8596 | ||
8597 | pml_idx = vmcs_read16(GUEST_PML_INDEX); | |
8598 | ||
8599 | /* Do nothing if PML buffer is empty */ | |
8600 | if (pml_idx == (PML_ENTITY_NUM - 1)) | |
8601 | return; | |
8602 | ||
8603 | /* PML index always points to next available PML buffer entity */ | |
8604 | if (pml_idx >= PML_ENTITY_NUM) | |
8605 | pml_idx = 0; | |
8606 | else | |
8607 | pml_idx++; | |
8608 | ||
8609 | pml_buf = page_address(vmx->pml_pg); | |
8610 | for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { | |
8611 | u64 gpa; | |
8612 | ||
8613 | gpa = pml_buf[pml_idx]; | |
8614 | WARN_ON(gpa & (PAGE_SIZE - 1)); | |
54bf36aa | 8615 | kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); |
843e4330 KH |
8616 | } |
8617 | ||
8618 | /* reset PML index */ | |
8619 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
8620 | } | |
8621 | ||
8622 | /* | |
8623 | * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. | |
8624 | * Called before reporting dirty_bitmap to userspace. | |
8625 | */ | |
8626 | static void kvm_flush_pml_buffers(struct kvm *kvm) | |
8627 | { | |
8628 | int i; | |
8629 | struct kvm_vcpu *vcpu; | |
8630 | /* | |
8631 | * We only need to kick vcpu out of guest mode here, as PML buffer | |
8632 | * is flushed at beginning of all VMEXITs, and it's obvious that only | |
8633 | * vcpus running in guest are possible to have unflushed GPAs in PML | |
8634 | * buffer. | |
8635 | */ | |
8636 | kvm_for_each_vcpu(i, vcpu, kvm) | |
8637 | kvm_vcpu_kick(vcpu); | |
8638 | } | |
8639 | ||
4eb64dce PB |
8640 | static void vmx_dump_sel(char *name, uint32_t sel) |
8641 | { | |
8642 | pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", | |
96794e4e | 8643 | name, vmcs_read16(sel), |
4eb64dce PB |
8644 | vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), |
8645 | vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), | |
8646 | vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); | |
8647 | } | |
8648 | ||
8649 | static void vmx_dump_dtsel(char *name, uint32_t limit) | |
8650 | { | |
8651 | pr_err("%s limit=0x%08x, base=0x%016lx\n", | |
8652 | name, vmcs_read32(limit), | |
8653 | vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); | |
8654 | } | |
8655 | ||
8656 | static void dump_vmcs(void) | |
8657 | { | |
8658 | u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); | |
8659 | u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); | |
8660 | u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
8661 | u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); | |
8662 | u32 secondary_exec_control = 0; | |
8663 | unsigned long cr4 = vmcs_readl(GUEST_CR4); | |
f3531054 | 8664 | u64 efer = vmcs_read64(GUEST_IA32_EFER); |
4eb64dce PB |
8665 | int i, n; |
8666 | ||
8667 | if (cpu_has_secondary_exec_ctrls()) | |
8668 | secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
8669 | ||
8670 | pr_err("*** Guest State ***\n"); | |
8671 | pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
8672 | vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), | |
8673 | vmcs_readl(CR0_GUEST_HOST_MASK)); | |
8674 | pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
8675 | cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); | |
8676 | pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); | |
8677 | if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && | |
8678 | (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) | |
8679 | { | |
845c5b40 PB |
8680 | pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", |
8681 | vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); | |
8682 | pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", | |
8683 | vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); | |
4eb64dce PB |
8684 | } |
8685 | pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", | |
8686 | vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); | |
8687 | pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", | |
8688 | vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); | |
8689 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
8690 | vmcs_readl(GUEST_SYSENTER_ESP), | |
8691 | vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); | |
8692 | vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); | |
8693 | vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); | |
8694 | vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); | |
8695 | vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); | |
8696 | vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); | |
8697 | vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); | |
8698 | vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); | |
8699 | vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); | |
8700 | vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); | |
8701 | vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); | |
8702 | if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || | |
8703 | (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) | |
845c5b40 PB |
8704 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", |
8705 | efer, vmcs_read64(GUEST_IA32_PAT)); | |
8706 | pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", | |
8707 | vmcs_read64(GUEST_IA32_DEBUGCTL), | |
4eb64dce PB |
8708 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); |
8709 | if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
845c5b40 PB |
8710 | pr_err("PerfGlobCtl = 0x%016llx\n", |
8711 | vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); | |
4eb64dce | 8712 | if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) |
845c5b40 | 8713 | pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); |
4eb64dce PB |
8714 | pr_err("Interruptibility = %08x ActivityState = %08x\n", |
8715 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), | |
8716 | vmcs_read32(GUEST_ACTIVITY_STATE)); | |
8717 | if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) | |
8718 | pr_err("InterruptStatus = %04x\n", | |
8719 | vmcs_read16(GUEST_INTR_STATUS)); | |
8720 | ||
8721 | pr_err("*** Host State ***\n"); | |
8722 | pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", | |
8723 | vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); | |
8724 | pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", | |
8725 | vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), | |
8726 | vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), | |
8727 | vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), | |
8728 | vmcs_read16(HOST_TR_SELECTOR)); | |
8729 | pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", | |
8730 | vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), | |
8731 | vmcs_readl(HOST_TR_BASE)); | |
8732 | pr_err("GDTBase=%016lx IDTBase=%016lx\n", | |
8733 | vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); | |
8734 | pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", | |
8735 | vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), | |
8736 | vmcs_readl(HOST_CR4)); | |
8737 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
8738 | vmcs_readl(HOST_IA32_SYSENTER_ESP), | |
8739 | vmcs_read32(HOST_IA32_SYSENTER_CS), | |
8740 | vmcs_readl(HOST_IA32_SYSENTER_EIP)); | |
8741 | if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) | |
845c5b40 PB |
8742 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", |
8743 | vmcs_read64(HOST_IA32_EFER), | |
8744 | vmcs_read64(HOST_IA32_PAT)); | |
4eb64dce | 8745 | if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) |
845c5b40 PB |
8746 | pr_err("PerfGlobCtl = 0x%016llx\n", |
8747 | vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); | |
4eb64dce PB |
8748 | |
8749 | pr_err("*** Control State ***\n"); | |
8750 | pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", | |
8751 | pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); | |
8752 | pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); | |
8753 | pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", | |
8754 | vmcs_read32(EXCEPTION_BITMAP), | |
8755 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), | |
8756 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); | |
8757 | pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", | |
8758 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), | |
8759 | vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), | |
8760 | vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); | |
8761 | pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", | |
8762 | vmcs_read32(VM_EXIT_INTR_INFO), | |
8763 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
8764 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); | |
8765 | pr_err(" reason=%08x qualification=%016lx\n", | |
8766 | vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); | |
8767 | pr_err("IDTVectoring: info=%08x errcode=%08x\n", | |
8768 | vmcs_read32(IDT_VECTORING_INFO_FIELD), | |
8769 | vmcs_read32(IDT_VECTORING_ERROR_CODE)); | |
845c5b40 | 8770 | pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); |
8cfe9866 | 8771 | if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) |
845c5b40 PB |
8772 | pr_err("TSC Multiplier = 0x%016llx\n", |
8773 | vmcs_read64(TSC_MULTIPLIER)); | |
4eb64dce PB |
8774 | if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) |
8775 | pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); | |
8776 | if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) | |
8777 | pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); | |
8778 | if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) | |
845c5b40 | 8779 | pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); |
4eb64dce PB |
8780 | n = vmcs_read32(CR3_TARGET_COUNT); |
8781 | for (i = 0; i + 1 < n; i += 4) | |
8782 | pr_err("CR3 target%u=%016lx target%u=%016lx\n", | |
8783 | i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2), | |
8784 | i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2)); | |
8785 | if (i < n) | |
8786 | pr_err("CR3 target%u=%016lx\n", | |
8787 | i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2)); | |
8788 | if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) | |
8789 | pr_err("PLE Gap=%08x Window=%08x\n", | |
8790 | vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); | |
8791 | if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) | |
8792 | pr_err("Virtual processor ID = 0x%04x\n", | |
8793 | vmcs_read16(VIRTUAL_PROCESSOR_ID)); | |
8794 | } | |
8795 | ||
6aa8b732 AK |
8796 | /* |
8797 | * The guest has exited. See if we can fix it or if we need userspace | |
8798 | * assistance. | |
8799 | */ | |
851ba692 | 8800 | static int vmx_handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 8801 | { |
29bd8a78 | 8802 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
a0861c02 | 8803 | u32 exit_reason = vmx->exit_reason; |
1155f76a | 8804 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 8805 | |
8b89fe1f PB |
8806 | trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); |
8807 | ||
843e4330 KH |
8808 | /* |
8809 | * Flush logged GPAs PML buffer, this will make dirty_bitmap more | |
8810 | * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before | |
8811 | * querying dirty_bitmap, we only need to kick all vcpus out of guest | |
8812 | * mode as if vcpus is in root mode, the PML buffer must has been | |
8813 | * flushed already. | |
8814 | */ | |
8815 | if (enable_pml) | |
54bf36aa | 8816 | vmx_flush_pml_buffer(vcpu); |
843e4330 | 8817 | |
80ced186 | 8818 | /* If guest state is invalid, start emulating */ |
14168786 | 8819 | if (vmx->emulation_required) |
80ced186 | 8820 | return handle_invalid_guest_state(vcpu); |
1d5a4d9b | 8821 | |
7313c698 PB |
8822 | if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason)) |
8823 | return nested_vmx_reflect_vmexit(vcpu, exit_reason); | |
644d711a | 8824 | |
5120702e | 8825 | if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { |
4eb64dce | 8826 | dump_vmcs(); |
5120702e MG |
8827 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
8828 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
8829 | = exit_reason; | |
8830 | return 0; | |
8831 | } | |
8832 | ||
29bd8a78 | 8833 | if (unlikely(vmx->fail)) { |
851ba692 AK |
8834 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
8835 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
29bd8a78 AK |
8836 | = vmcs_read32(VM_INSTRUCTION_ERROR); |
8837 | return 0; | |
8838 | } | |
6aa8b732 | 8839 | |
b9bf6882 XG |
8840 | /* |
8841 | * Note: | |
8842 | * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by | |
8843 | * delivery event since it indicates guest is accessing MMIO. | |
8844 | * The vm-exit can be triggered again after return to guest that | |
8845 | * will cause infinite loop. | |
8846 | */ | |
d77c26fc | 8847 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
1439442c | 8848 | (exit_reason != EXIT_REASON_EXCEPTION_NMI && |
60637aac | 8849 | exit_reason != EXIT_REASON_EPT_VIOLATION && |
b244c9fc | 8850 | exit_reason != EXIT_REASON_PML_FULL && |
b9bf6882 XG |
8851 | exit_reason != EXIT_REASON_TASK_SWITCH)) { |
8852 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
8853 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; | |
70bcd708 | 8854 | vcpu->run->internal.ndata = 3; |
b9bf6882 XG |
8855 | vcpu->run->internal.data[0] = vectoring_info; |
8856 | vcpu->run->internal.data[1] = exit_reason; | |
70bcd708 PB |
8857 | vcpu->run->internal.data[2] = vcpu->arch.exit_qualification; |
8858 | if (exit_reason == EXIT_REASON_EPT_MISCONFIG) { | |
8859 | vcpu->run->internal.ndata++; | |
8860 | vcpu->run->internal.data[3] = | |
8861 | vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
8862 | } | |
b9bf6882 XG |
8863 | return 0; |
8864 | } | |
3b86cd99 | 8865 | |
d02fcf50 | 8866 | if (unlikely(!enable_vnmi && |
8a1b4392 PB |
8867 | vmx->loaded_vmcs->soft_vnmi_blocked)) { |
8868 | if (vmx_interrupt_allowed(vcpu)) { | |
8869 | vmx->loaded_vmcs->soft_vnmi_blocked = 0; | |
8870 | } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL && | |
8871 | vcpu->arch.nmi_pending) { | |
8872 | /* | |
8873 | * This CPU don't support us in finding the end of an | |
8874 | * NMI-blocked window if the guest runs with IRQs | |
8875 | * disabled. So we pull the trigger after 1 s of | |
8876 | * futile waiting, but inform the user about this. | |
8877 | */ | |
8878 | printk(KERN_WARNING "%s: Breaking out of NMI-blocked " | |
8879 | "state on VCPU %d after 1 s timeout\n", | |
8880 | __func__, vcpu->vcpu_id); | |
8881 | vmx->loaded_vmcs->soft_vnmi_blocked = 0; | |
8882 | } | |
8883 | } | |
8884 | ||
6aa8b732 AK |
8885 | if (exit_reason < kvm_vmx_max_exit_handlers |
8886 | && kvm_vmx_exit_handlers[exit_reason]) | |
851ba692 | 8887 | return kvm_vmx_exit_handlers[exit_reason](vcpu); |
6aa8b732 | 8888 | else { |
6c6c5e03 RK |
8889 | vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", |
8890 | exit_reason); | |
2bc19dc3 MT |
8891 | kvm_queue_exception(vcpu, UD_VECTOR); |
8892 | return 1; | |
6aa8b732 | 8893 | } |
6aa8b732 AK |
8894 | } |
8895 | ||
95ba8273 | 8896 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
6e5d865c | 8897 | { |
a7c0b07d WL |
8898 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
8899 | ||
8900 | if (is_guest_mode(vcpu) && | |
8901 | nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
8902 | return; | |
8903 | ||
95ba8273 | 8904 | if (irr == -1 || tpr < irr) { |
6e5d865c YS |
8905 | vmcs_write32(TPR_THRESHOLD, 0); |
8906 | return; | |
8907 | } | |
8908 | ||
95ba8273 | 8909 | vmcs_write32(TPR_THRESHOLD, irr); |
6e5d865c YS |
8910 | } |
8911 | ||
8d14695f YZ |
8912 | static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) |
8913 | { | |
8914 | u32 sec_exec_control; | |
8915 | ||
dccbfcf5 RK |
8916 | /* Postpone execution until vmcs01 is the current VMCS. */ |
8917 | if (is_guest_mode(vcpu)) { | |
8918 | to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true; | |
8919 | return; | |
8920 | } | |
8921 | ||
f6e90f9e | 8922 | if (!cpu_has_vmx_virtualize_x2apic_mode()) |
8d14695f YZ |
8923 | return; |
8924 | ||
35754c98 | 8925 | if (!cpu_need_tpr_shadow(vcpu)) |
8d14695f YZ |
8926 | return; |
8927 | ||
8928 | sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
8929 | ||
8930 | if (set) { | |
8931 | sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
8932 | sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
8933 | } else { | |
8934 | sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
8935 | sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
fb6c8198 | 8936 | vmx_flush_tlb_ept_only(vcpu); |
8d14695f YZ |
8937 | } |
8938 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control); | |
8939 | ||
8940 | vmx_set_msr_bitmap(vcpu); | |
8941 | } | |
8942 | ||
38b99173 TC |
8943 | static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) |
8944 | { | |
8945 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8946 | ||
8947 | /* | |
8948 | * Currently we do not handle the nested case where L2 has an | |
8949 | * APIC access page of its own; that page is still pinned. | |
8950 | * Hence, we skip the case where the VCPU is in guest mode _and_ | |
8951 | * L1 prepared an APIC access page for L2. | |
8952 | * | |
8953 | * For the case where L1 and L2 share the same APIC access page | |
8954 | * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear | |
8955 | * in the vmcs12), this function will only update either the vmcs01 | |
8956 | * or the vmcs02. If the former, the vmcs02 will be updated by | |
8957 | * prepare_vmcs02. If the latter, the vmcs01 will be updated in | |
8958 | * the next L2->L1 exit. | |
8959 | */ | |
8960 | if (!is_guest_mode(vcpu) || | |
4f2777bc | 8961 | !nested_cpu_has2(get_vmcs12(&vmx->vcpu), |
fb6c8198 | 8962 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { |
38b99173 | 8963 | vmcs_write64(APIC_ACCESS_ADDR, hpa); |
fb6c8198 JM |
8964 | vmx_flush_tlb_ept_only(vcpu); |
8965 | } | |
38b99173 TC |
8966 | } |
8967 | ||
67c9dddc | 8968 | static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) |
c7c9c56c YZ |
8969 | { |
8970 | u16 status; | |
8971 | u8 old; | |
8972 | ||
67c9dddc PB |
8973 | if (max_isr == -1) |
8974 | max_isr = 0; | |
c7c9c56c YZ |
8975 | |
8976 | status = vmcs_read16(GUEST_INTR_STATUS); | |
8977 | old = status >> 8; | |
67c9dddc | 8978 | if (max_isr != old) { |
c7c9c56c | 8979 | status &= 0xff; |
67c9dddc | 8980 | status |= max_isr << 8; |
c7c9c56c YZ |
8981 | vmcs_write16(GUEST_INTR_STATUS, status); |
8982 | } | |
8983 | } | |
8984 | ||
8985 | static void vmx_set_rvi(int vector) | |
8986 | { | |
8987 | u16 status; | |
8988 | u8 old; | |
8989 | ||
4114c27d WW |
8990 | if (vector == -1) |
8991 | vector = 0; | |
8992 | ||
c7c9c56c YZ |
8993 | status = vmcs_read16(GUEST_INTR_STATUS); |
8994 | old = (u8)status & 0xff; | |
8995 | if ((u8)vector != old) { | |
8996 | status &= ~0xff; | |
8997 | status |= (u8)vector; | |
8998 | vmcs_write16(GUEST_INTR_STATUS, status); | |
8999 | } | |
9000 | } | |
9001 | ||
9002 | static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) | |
9003 | { | |
4114c27d WW |
9004 | if (!is_guest_mode(vcpu)) { |
9005 | vmx_set_rvi(max_irr); | |
9006 | return; | |
9007 | } | |
9008 | ||
c7c9c56c YZ |
9009 | if (max_irr == -1) |
9010 | return; | |
9011 | ||
963fee16 | 9012 | /* |
4114c27d WW |
9013 | * In guest mode. If a vmexit is needed, vmx_check_nested_events |
9014 | * handles it. | |
963fee16 | 9015 | */ |
4114c27d | 9016 | if (nested_exit_on_intr(vcpu)) |
963fee16 WL |
9017 | return; |
9018 | ||
963fee16 | 9019 | /* |
4114c27d | 9020 | * Else, fall back to pre-APICv interrupt injection since L2 |
963fee16 WL |
9021 | * is run without virtual interrupt delivery. |
9022 | */ | |
9023 | if (!kvm_event_needs_reinjection(vcpu) && | |
9024 | vmx_interrupt_allowed(vcpu)) { | |
9025 | kvm_queue_interrupt(vcpu, max_irr, false); | |
9026 | vmx_inject_irq(vcpu); | |
9027 | } | |
c7c9c56c YZ |
9028 | } |
9029 | ||
76dfafd5 | 9030 | static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) |
810e6def PB |
9031 | { |
9032 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
76dfafd5 | 9033 | int max_irr; |
810e6def | 9034 | |
76dfafd5 PB |
9035 | WARN_ON(!vcpu->arch.apicv_active); |
9036 | if (pi_test_on(&vmx->pi_desc)) { | |
9037 | pi_clear_on(&vmx->pi_desc); | |
9038 | /* | |
9039 | * IOMMU can write to PIR.ON, so the barrier matters even on UP. | |
9040 | * But on x86 this is just a compiler barrier anyway. | |
9041 | */ | |
9042 | smp_mb__after_atomic(); | |
9043 | max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir); | |
9044 | } else { | |
9045 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
9046 | } | |
9047 | vmx_hwapic_irr_update(vcpu, max_irr); | |
9048 | return max_irr; | |
810e6def PB |
9049 | } |
9050 | ||
6308630b | 9051 | static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) |
c7c9c56c | 9052 | { |
d62caabb | 9053 | if (!kvm_vcpu_apicv_active(vcpu)) |
3d81bc7e YZ |
9054 | return; |
9055 | ||
c7c9c56c YZ |
9056 | vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); |
9057 | vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); | |
9058 | vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); | |
9059 | vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); | |
9060 | } | |
9061 | ||
967235d3 PB |
9062 | static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu) |
9063 | { | |
9064 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9065 | ||
9066 | pi_clear_on(&vmx->pi_desc); | |
9067 | memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir)); | |
9068 | } | |
9069 | ||
51aa01d1 | 9070 | static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx) |
cf393f75 | 9071 | { |
48ae0fb4 JM |
9072 | u32 exit_intr_info = 0; |
9073 | u16 basic_exit_reason = (u16)vmx->exit_reason; | |
00eba012 | 9074 | |
48ae0fb4 JM |
9075 | if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY |
9076 | || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI)) | |
00eba012 AK |
9077 | return; |
9078 | ||
48ae0fb4 JM |
9079 | if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) |
9080 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
9081 | vmx->exit_intr_info = exit_intr_info; | |
a0861c02 | 9082 | |
1261bfa3 WL |
9083 | /* if exit due to PF check for async PF */ |
9084 | if (is_page_fault(exit_intr_info)) | |
9085 | vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); | |
9086 | ||
a0861c02 | 9087 | /* Handle machine checks before interrupts are enabled */ |
48ae0fb4 JM |
9088 | if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY || |
9089 | is_machine_check(exit_intr_info)) | |
a0861c02 AK |
9090 | kvm_machine_check(); |
9091 | ||
20f65983 | 9092 | /* We need to handle NMIs before interrupts are enabled */ |
ef85b673 | 9093 | if (is_nmi(exit_intr_info)) { |
ff9d07a0 | 9094 | kvm_before_handle_nmi(&vmx->vcpu); |
20f65983 | 9095 | asm("int $2"); |
ff9d07a0 ZY |
9096 | kvm_after_handle_nmi(&vmx->vcpu); |
9097 | } | |
51aa01d1 | 9098 | } |
20f65983 | 9099 | |
a547c6db YZ |
9100 | static void vmx_handle_external_intr(struct kvm_vcpu *vcpu) |
9101 | { | |
9102 | u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
9103 | ||
a547c6db YZ |
9104 | if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK)) |
9105 | == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) { | |
9106 | unsigned int vector; | |
9107 | unsigned long entry; | |
9108 | gate_desc *desc; | |
9109 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9110 | #ifdef CONFIG_X86_64 | |
9111 | unsigned long tmp; | |
9112 | #endif | |
9113 | ||
9114 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
9115 | desc = (gate_desc *)vmx->host_idt_base + vector; | |
64b163fa | 9116 | entry = gate_offset(desc); |
a547c6db YZ |
9117 | asm volatile( |
9118 | #ifdef CONFIG_X86_64 | |
9119 | "mov %%" _ASM_SP ", %[sp]\n\t" | |
9120 | "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" | |
9121 | "push $%c[ss]\n\t" | |
9122 | "push %[sp]\n\t" | |
9123 | #endif | |
9124 | "pushf\n\t" | |
a547c6db YZ |
9125 | __ASM_SIZE(push) " $%c[cs]\n\t" |
9126 | "call *%[entry]\n\t" | |
9127 | : | |
9128 | #ifdef CONFIG_X86_64 | |
3f62de5f | 9129 | [sp]"=&r"(tmp), |
a547c6db | 9130 | #endif |
f5caf621 | 9131 | ASM_CALL_CONSTRAINT |
a547c6db YZ |
9132 | : |
9133 | [entry]"r"(entry), | |
9134 | [ss]"i"(__KERNEL_DS), | |
9135 | [cs]"i"(__KERNEL_CS) | |
9136 | ); | |
f2485b3e | 9137 | } |
a547c6db | 9138 | } |
c207aee4 | 9139 | STACK_FRAME_NON_STANDARD(vmx_handle_external_intr); |
a547c6db | 9140 | |
6d396b55 PB |
9141 | static bool vmx_has_high_real_mode_segbase(void) |
9142 | { | |
9143 | return enable_unrestricted_guest || emulate_invalid_guest_state; | |
9144 | } | |
9145 | ||
da8999d3 LJ |
9146 | static bool vmx_mpx_supported(void) |
9147 | { | |
9148 | return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) && | |
9149 | (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS); | |
9150 | } | |
9151 | ||
55412b2e WL |
9152 | static bool vmx_xsaves_supported(void) |
9153 | { | |
9154 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
9155 | SECONDARY_EXEC_XSAVES; | |
9156 | } | |
9157 | ||
51aa01d1 AK |
9158 | static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) |
9159 | { | |
c5ca8e57 | 9160 | u32 exit_intr_info; |
51aa01d1 AK |
9161 | bool unblock_nmi; |
9162 | u8 vector; | |
9163 | bool idtv_info_valid; | |
9164 | ||
9165 | idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
20f65983 | 9166 | |
d02fcf50 | 9167 | if (enable_vnmi) { |
8a1b4392 PB |
9168 | if (vmx->loaded_vmcs->nmi_known_unmasked) |
9169 | return; | |
9170 | /* | |
9171 | * Can't use vmx->exit_intr_info since we're not sure what | |
9172 | * the exit reason is. | |
9173 | */ | |
9174 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
9175 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; | |
9176 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
9177 | /* | |
9178 | * SDM 3: 27.7.1.2 (September 2008) | |
9179 | * Re-set bit "block by NMI" before VM entry if vmexit caused by | |
9180 | * a guest IRET fault. | |
9181 | * SDM 3: 23.2.2 (September 2008) | |
9182 | * Bit 12 is undefined in any of the following cases: | |
9183 | * If the VM exit sets the valid bit in the IDT-vectoring | |
9184 | * information field. | |
9185 | * If the VM exit is due to a double fault. | |
9186 | */ | |
9187 | if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && | |
9188 | vector != DF_VECTOR && !idtv_info_valid) | |
9189 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
9190 | GUEST_INTR_STATE_NMI); | |
9191 | else | |
9192 | vmx->loaded_vmcs->nmi_known_unmasked = | |
9193 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) | |
9194 | & GUEST_INTR_STATE_NMI); | |
9195 | } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked)) | |
9196 | vmx->loaded_vmcs->vnmi_blocked_time += | |
9197 | ktime_to_ns(ktime_sub(ktime_get(), | |
9198 | vmx->loaded_vmcs->entry_time)); | |
51aa01d1 AK |
9199 | } |
9200 | ||
3ab66e8a | 9201 | static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, |
83422e17 AK |
9202 | u32 idt_vectoring_info, |
9203 | int instr_len_field, | |
9204 | int error_code_field) | |
51aa01d1 | 9205 | { |
51aa01d1 AK |
9206 | u8 vector; |
9207 | int type; | |
9208 | bool idtv_info_valid; | |
9209 | ||
9210 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
668f612f | 9211 | |
3ab66e8a JK |
9212 | vcpu->arch.nmi_injected = false; |
9213 | kvm_clear_exception_queue(vcpu); | |
9214 | kvm_clear_interrupt_queue(vcpu); | |
37b96e98 GN |
9215 | |
9216 | if (!idtv_info_valid) | |
9217 | return; | |
9218 | ||
3ab66e8a | 9219 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3842d135 | 9220 | |
668f612f AK |
9221 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; |
9222 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; | |
37b96e98 | 9223 | |
64a7ec06 | 9224 | switch (type) { |
37b96e98 | 9225 | case INTR_TYPE_NMI_INTR: |
3ab66e8a | 9226 | vcpu->arch.nmi_injected = true; |
668f612f | 9227 | /* |
7b4a25cb | 9228 | * SDM 3: 27.7.1.2 (September 2008) |
37b96e98 GN |
9229 | * Clear bit "block by NMI" before VM entry if a NMI |
9230 | * delivery faulted. | |
668f612f | 9231 | */ |
3ab66e8a | 9232 | vmx_set_nmi_mask(vcpu, false); |
37b96e98 | 9233 | break; |
37b96e98 | 9234 | case INTR_TYPE_SOFT_EXCEPTION: |
3ab66e8a | 9235 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f GN |
9236 | /* fall through */ |
9237 | case INTR_TYPE_HARD_EXCEPTION: | |
35920a35 | 9238 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { |
83422e17 | 9239 | u32 err = vmcs_read32(error_code_field); |
851eb667 | 9240 | kvm_requeue_exception_e(vcpu, vector, err); |
35920a35 | 9241 | } else |
851eb667 | 9242 | kvm_requeue_exception(vcpu, vector); |
37b96e98 | 9243 | break; |
66fd3f7f | 9244 | case INTR_TYPE_SOFT_INTR: |
3ab66e8a | 9245 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f | 9246 | /* fall through */ |
37b96e98 | 9247 | case INTR_TYPE_EXT_INTR: |
3ab66e8a | 9248 | kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); |
37b96e98 GN |
9249 | break; |
9250 | default: | |
9251 | break; | |
f7d9238f | 9252 | } |
cf393f75 AK |
9253 | } |
9254 | ||
83422e17 AK |
9255 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) |
9256 | { | |
3ab66e8a | 9257 | __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, |
83422e17 AK |
9258 | VM_EXIT_INSTRUCTION_LEN, |
9259 | IDT_VECTORING_ERROR_CODE); | |
9260 | } | |
9261 | ||
b463a6f7 AK |
9262 | static void vmx_cancel_injection(struct kvm_vcpu *vcpu) |
9263 | { | |
3ab66e8a | 9264 | __vmx_complete_interrupts(vcpu, |
b463a6f7 AK |
9265 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), |
9266 | VM_ENTRY_INSTRUCTION_LEN, | |
9267 | VM_ENTRY_EXCEPTION_ERROR_CODE); | |
9268 | ||
9269 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); | |
9270 | } | |
9271 | ||
d7cd9796 GN |
9272 | static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) |
9273 | { | |
9274 | int i, nr_msrs; | |
9275 | struct perf_guest_switch_msr *msrs; | |
9276 | ||
9277 | msrs = perf_guest_get_msrs(&nr_msrs); | |
9278 | ||
9279 | if (!msrs) | |
9280 | return; | |
9281 | ||
9282 | for (i = 0; i < nr_msrs; i++) | |
9283 | if (msrs[i].host == msrs[i].guest) | |
9284 | clear_atomic_switch_msr(vmx, msrs[i].msr); | |
9285 | else | |
9286 | add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, | |
9287 | msrs[i].host); | |
9288 | } | |
9289 | ||
33365e7a | 9290 | static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu) |
64672c95 YJ |
9291 | { |
9292 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9293 | u64 tscl; | |
9294 | u32 delta_tsc; | |
9295 | ||
9296 | if (vmx->hv_deadline_tsc == -1) | |
9297 | return; | |
9298 | ||
9299 | tscl = rdtsc(); | |
9300 | if (vmx->hv_deadline_tsc > tscl) | |
9301 | /* sure to be 32 bit only because checked on set_hv_timer */ | |
9302 | delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> | |
9303 | cpu_preemption_timer_multi); | |
9304 | else | |
9305 | delta_tsc = 0; | |
9306 | ||
9307 | vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); | |
9308 | } | |
9309 | ||
a3b5ba49 | 9310 | static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 9311 | { |
a2fa3e9f | 9312 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
d6e41f11 | 9313 | unsigned long debugctlmsr, cr3, cr4; |
104f226b | 9314 | |
8a1b4392 | 9315 | /* Record the guest's net vcpu time for enforced NMI injections. */ |
d02fcf50 | 9316 | if (unlikely(!enable_vnmi && |
8a1b4392 PB |
9317 | vmx->loaded_vmcs->soft_vnmi_blocked)) |
9318 | vmx->loaded_vmcs->entry_time = ktime_get(); | |
9319 | ||
104f226b AK |
9320 | /* Don't enter VMX if guest state is invalid, let the exit handler |
9321 | start emulation until we arrive back to a valid state */ | |
14168786 | 9322 | if (vmx->emulation_required) |
104f226b AK |
9323 | return; |
9324 | ||
a7653ecd RK |
9325 | if (vmx->ple_window_dirty) { |
9326 | vmx->ple_window_dirty = false; | |
9327 | vmcs_write32(PLE_WINDOW, vmx->ple_window); | |
9328 | } | |
9329 | ||
012f83cb AG |
9330 | if (vmx->nested.sync_shadow_vmcs) { |
9331 | copy_vmcs12_to_shadow(vmx); | |
9332 | vmx->nested.sync_shadow_vmcs = false; | |
9333 | } | |
9334 | ||
104f226b AK |
9335 | if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty)) |
9336 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); | |
9337 | if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
9338 | vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); | |
9339 | ||
d6e41f11 | 9340 | cr3 = __get_current_cr3_fast(); |
44889942 | 9341 | if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) { |
d6e41f11 | 9342 | vmcs_writel(HOST_CR3, cr3); |
44889942 | 9343 | vmx->loaded_vmcs->vmcs_host_cr3 = cr3; |
d6e41f11 AL |
9344 | } |
9345 | ||
1e02ce4c | 9346 | cr4 = cr4_read_shadow(); |
44889942 | 9347 | if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) { |
d974baa3 | 9348 | vmcs_writel(HOST_CR4, cr4); |
44889942 | 9349 | vmx->loaded_vmcs->vmcs_host_cr4 = cr4; |
d974baa3 AL |
9350 | } |
9351 | ||
104f226b AK |
9352 | /* When single-stepping over STI and MOV SS, we must clear the |
9353 | * corresponding interruptibility bits in the guest state. Otherwise | |
9354 | * vmentry fails as it then expects bit 14 (BS) in pending debug | |
9355 | * exceptions being set, but that's not correct for the guest debugging | |
9356 | * case. */ | |
9357 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
9358 | vmx_set_interrupt_shadow(vcpu, 0); | |
9359 | ||
b9dd21e1 PB |
9360 | if (static_cpu_has(X86_FEATURE_PKU) && |
9361 | kvm_read_cr4_bits(vcpu, X86_CR4_PKE) && | |
9362 | vcpu->arch.pkru != vmx->host_pkru) | |
9363 | __write_pkru(vcpu->arch.pkru); | |
1be0e61c | 9364 | |
d7cd9796 | 9365 | atomic_switch_perf_msrs(vmx); |
2a7921b7 | 9366 | debugctlmsr = get_debugctlmsr(); |
d7cd9796 | 9367 | |
64672c95 YJ |
9368 | vmx_arm_hv_timer(vcpu); |
9369 | ||
d462b819 | 9370 | vmx->__launched = vmx->loaded_vmcs->launched; |
104f226b | 9371 | asm( |
6aa8b732 | 9372 | /* Store host registers */ |
b188c81f AK |
9373 | "push %%" _ASM_DX "; push %%" _ASM_BP ";" |
9374 | "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */ | |
9375 | "push %%" _ASM_CX " \n\t" | |
9376 | "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t" | |
313dbd49 | 9377 | "je 1f \n\t" |
b188c81f | 9378 | "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t" |
4ecac3fd | 9379 | __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t" |
313dbd49 | 9380 | "1: \n\t" |
d3edefc0 | 9381 | /* Reload cr2 if changed */ |
b188c81f AK |
9382 | "mov %c[cr2](%0), %%" _ASM_AX " \n\t" |
9383 | "mov %%cr2, %%" _ASM_DX " \n\t" | |
9384 | "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t" | |
d3edefc0 | 9385 | "je 2f \n\t" |
b188c81f | 9386 | "mov %%" _ASM_AX", %%cr2 \n\t" |
d3edefc0 | 9387 | "2: \n\t" |
6aa8b732 | 9388 | /* Check if vmlaunch of vmresume is needed */ |
e08aa78a | 9389 | "cmpl $0, %c[launched](%0) \n\t" |
6aa8b732 | 9390 | /* Load guest registers. Don't clobber flags. */ |
b188c81f AK |
9391 | "mov %c[rax](%0), %%" _ASM_AX " \n\t" |
9392 | "mov %c[rbx](%0), %%" _ASM_BX " \n\t" | |
9393 | "mov %c[rdx](%0), %%" _ASM_DX " \n\t" | |
9394 | "mov %c[rsi](%0), %%" _ASM_SI " \n\t" | |
9395 | "mov %c[rdi](%0), %%" _ASM_DI " \n\t" | |
9396 | "mov %c[rbp](%0), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 9397 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
9398 | "mov %c[r8](%0), %%r8 \n\t" |
9399 | "mov %c[r9](%0), %%r9 \n\t" | |
9400 | "mov %c[r10](%0), %%r10 \n\t" | |
9401 | "mov %c[r11](%0), %%r11 \n\t" | |
9402 | "mov %c[r12](%0), %%r12 \n\t" | |
9403 | "mov %c[r13](%0), %%r13 \n\t" | |
9404 | "mov %c[r14](%0), %%r14 \n\t" | |
9405 | "mov %c[r15](%0), %%r15 \n\t" | |
6aa8b732 | 9406 | #endif |
b188c81f | 9407 | "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */ |
c801949d | 9408 | |
6aa8b732 | 9409 | /* Enter guest mode */ |
83287ea4 | 9410 | "jne 1f \n\t" |
4ecac3fd | 9411 | __ex(ASM_VMX_VMLAUNCH) "\n\t" |
83287ea4 AK |
9412 | "jmp 2f \n\t" |
9413 | "1: " __ex(ASM_VMX_VMRESUME) "\n\t" | |
9414 | "2: " | |
6aa8b732 | 9415 | /* Save guest registers, load host registers, keep flags */ |
b188c81f | 9416 | "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t" |
40712fae | 9417 | "pop %0 \n\t" |
0cb5b306 | 9418 | "setbe %c[fail](%0)\n\t" |
b188c81f AK |
9419 | "mov %%" _ASM_AX ", %c[rax](%0) \n\t" |
9420 | "mov %%" _ASM_BX ", %c[rbx](%0) \n\t" | |
9421 | __ASM_SIZE(pop) " %c[rcx](%0) \n\t" | |
9422 | "mov %%" _ASM_DX ", %c[rdx](%0) \n\t" | |
9423 | "mov %%" _ASM_SI ", %c[rsi](%0) \n\t" | |
9424 | "mov %%" _ASM_DI ", %c[rdi](%0) \n\t" | |
9425 | "mov %%" _ASM_BP ", %c[rbp](%0) \n\t" | |
05b3e0c2 | 9426 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
9427 | "mov %%r8, %c[r8](%0) \n\t" |
9428 | "mov %%r9, %c[r9](%0) \n\t" | |
9429 | "mov %%r10, %c[r10](%0) \n\t" | |
9430 | "mov %%r11, %c[r11](%0) \n\t" | |
9431 | "mov %%r12, %c[r12](%0) \n\t" | |
9432 | "mov %%r13, %c[r13](%0) \n\t" | |
9433 | "mov %%r14, %c[r14](%0) \n\t" | |
9434 | "mov %%r15, %c[r15](%0) \n\t" | |
0cb5b306 JM |
9435 | "xor %%r8d, %%r8d \n\t" |
9436 | "xor %%r9d, %%r9d \n\t" | |
9437 | "xor %%r10d, %%r10d \n\t" | |
9438 | "xor %%r11d, %%r11d \n\t" | |
9439 | "xor %%r12d, %%r12d \n\t" | |
9440 | "xor %%r13d, %%r13d \n\t" | |
9441 | "xor %%r14d, %%r14d \n\t" | |
9442 | "xor %%r15d, %%r15d \n\t" | |
6aa8b732 | 9443 | #endif |
b188c81f AK |
9444 | "mov %%cr2, %%" _ASM_AX " \n\t" |
9445 | "mov %%" _ASM_AX ", %c[cr2](%0) \n\t" | |
c801949d | 9446 | |
0cb5b306 JM |
9447 | "xor %%eax, %%eax \n\t" |
9448 | "xor %%ebx, %%ebx \n\t" | |
9449 | "xor %%esi, %%esi \n\t" | |
9450 | "xor %%edi, %%edi \n\t" | |
b188c81f | 9451 | "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t" |
83287ea4 AK |
9452 | ".pushsection .rodata \n\t" |
9453 | ".global vmx_return \n\t" | |
9454 | "vmx_return: " _ASM_PTR " 2b \n\t" | |
9455 | ".popsection" | |
e08aa78a | 9456 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), |
d462b819 | 9457 | [launched]"i"(offsetof(struct vcpu_vmx, __launched)), |
e08aa78a | 9458 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), |
313dbd49 | 9459 | [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)), |
ad312c7c ZX |
9460 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
9461 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
9462 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
9463 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
9464 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
9465 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
9466 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 9467 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
9468 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
9469 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
9470 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
9471 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
9472 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
9473 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
9474 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
9475 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 9476 | #endif |
40712fae AK |
9477 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)), |
9478 | [wordsize]"i"(sizeof(ulong)) | |
c2036300 LV |
9479 | : "cc", "memory" |
9480 | #ifdef CONFIG_X86_64 | |
b188c81f | 9481 | , "rax", "rbx", "rdi", "rsi" |
c2036300 | 9482 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
b188c81f AK |
9483 | #else |
9484 | , "eax", "ebx", "edi", "esi" | |
c2036300 LV |
9485 | #endif |
9486 | ); | |
6aa8b732 | 9487 | |
2a7921b7 GN |
9488 | /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ |
9489 | if (debugctlmsr) | |
9490 | update_debugctlmsr(debugctlmsr); | |
9491 | ||
aa67f609 AK |
9492 | #ifndef CONFIG_X86_64 |
9493 | /* | |
9494 | * The sysexit path does not restore ds/es, so we must set them to | |
9495 | * a reasonable value ourselves. | |
9496 | * | |
9497 | * We can't defer this to vmx_load_host_state() since that function | |
9498 | * may be executed in interrupt context, which saves and restore segments | |
9499 | * around it, nullifying its effect. | |
9500 | */ | |
9501 | loadsegment(ds, __USER_DS); | |
9502 | loadsegment(es, __USER_DS); | |
9503 | #endif | |
9504 | ||
6de4f3ad | 9505 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) |
6de12732 | 9506 | | (1 << VCPU_EXREG_RFLAGS) |
aff48baa | 9507 | | (1 << VCPU_EXREG_PDPTR) |
2fb92db1 | 9508 | | (1 << VCPU_EXREG_SEGMENTS) |
aff48baa | 9509 | | (1 << VCPU_EXREG_CR3)); |
5fdbf976 MT |
9510 | vcpu->arch.regs_dirty = 0; |
9511 | ||
1be0e61c XG |
9512 | /* |
9513 | * eager fpu is enabled if PKEY is supported and CR4 is switched | |
9514 | * back on host, so it is safe to read guest PKRU from current | |
9515 | * XSAVE. | |
9516 | */ | |
b9dd21e1 PB |
9517 | if (static_cpu_has(X86_FEATURE_PKU) && |
9518 | kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) { | |
9519 | vcpu->arch.pkru = __read_pkru(); | |
9520 | if (vcpu->arch.pkru != vmx->host_pkru) | |
1be0e61c | 9521 | __write_pkru(vmx->host_pkru); |
1be0e61c XG |
9522 | } |
9523 | ||
e0b890d3 GN |
9524 | /* |
9525 | * the KVM_REQ_EVENT optimization bit is only on for one entry, and if | |
9526 | * we did not inject a still-pending event to L1 now because of | |
9527 | * nested_run_pending, we need to re-enable this bit. | |
9528 | */ | |
9529 | if (vmx->nested.nested_run_pending) | |
9530 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
9531 | ||
9532 | vmx->nested.nested_run_pending = 0; | |
b060ca3b JM |
9533 | vmx->idt_vectoring_info = 0; |
9534 | ||
9535 | vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON); | |
9536 | if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) | |
9537 | return; | |
9538 | ||
9539 | vmx->loaded_vmcs->launched = 1; | |
9540 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
e0b890d3 | 9541 | |
51aa01d1 AK |
9542 | vmx_complete_atomic_exit(vmx); |
9543 | vmx_recover_nmi_blocking(vmx); | |
cf393f75 | 9544 | vmx_complete_interrupts(vmx); |
6aa8b732 | 9545 | } |
c207aee4 | 9546 | STACK_FRAME_NON_STANDARD(vmx_vcpu_run); |
6aa8b732 | 9547 | |
1279a6b1 | 9548 | static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs) |
4fa7734c PB |
9549 | { |
9550 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9551 | int cpu; | |
9552 | ||
1279a6b1 | 9553 | if (vmx->loaded_vmcs == vmcs) |
4fa7734c PB |
9554 | return; |
9555 | ||
9556 | cpu = get_cpu(); | |
1279a6b1 | 9557 | vmx->loaded_vmcs = vmcs; |
4fa7734c PB |
9558 | vmx_vcpu_put(vcpu); |
9559 | vmx_vcpu_load(vcpu, cpu); | |
4fa7734c PB |
9560 | put_cpu(); |
9561 | } | |
9562 | ||
2f1fe811 JM |
9563 | /* |
9564 | * Ensure that the current vmcs of the logical processor is the | |
9565 | * vmcs01 of the vcpu before calling free_nested(). | |
9566 | */ | |
9567 | static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu) | |
9568 | { | |
9569 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9570 | int r; | |
9571 | ||
9572 | r = vcpu_load(vcpu); | |
9573 | BUG_ON(r); | |
1279a6b1 | 9574 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); |
2f1fe811 JM |
9575 | free_nested(vmx); |
9576 | vcpu_put(vcpu); | |
9577 | } | |
9578 | ||
6aa8b732 AK |
9579 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) |
9580 | { | |
fb3f0f51 RR |
9581 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
9582 | ||
843e4330 | 9583 | if (enable_pml) |
a3eaa864 | 9584 | vmx_destroy_pml_buffer(vmx); |
991e7a0e | 9585 | free_vpid(vmx->vpid); |
4fa7734c | 9586 | leave_guest_mode(vcpu); |
2f1fe811 | 9587 | vmx_free_vcpu_nested(vcpu); |
4fa7734c | 9588 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 RR |
9589 | kfree(vmx->guest_msrs); |
9590 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 9591 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
9592 | } |
9593 | ||
fb3f0f51 | 9594 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 9595 | { |
fb3f0f51 | 9596 | int err; |
c16f862d | 9597 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
15ad7146 | 9598 | int cpu; |
6aa8b732 | 9599 | |
a2fa3e9f | 9600 | if (!vmx) |
fb3f0f51 RR |
9601 | return ERR_PTR(-ENOMEM); |
9602 | ||
991e7a0e | 9603 | vmx->vpid = allocate_vpid(); |
2384d2b3 | 9604 | |
fb3f0f51 RR |
9605 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
9606 | if (err) | |
9607 | goto free_vcpu; | |
965b58a5 | 9608 | |
4e59516a PF |
9609 | err = -ENOMEM; |
9610 | ||
9611 | /* | |
9612 | * If PML is turned on, failure on enabling PML just results in failure | |
9613 | * of creating the vcpu, therefore we can simplify PML logic (by | |
9614 | * avoiding dealing with cases, such as enabling PML partially on vcpus | |
9615 | * for the guest, etc. | |
9616 | */ | |
9617 | if (enable_pml) { | |
9618 | vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
9619 | if (!vmx->pml_pg) | |
9620 | goto uninit_vcpu; | |
9621 | } | |
9622 | ||
a2fa3e9f | 9623 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
03916db9 PB |
9624 | BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0]) |
9625 | > PAGE_SIZE); | |
0123be42 | 9626 | |
4e59516a PF |
9627 | if (!vmx->guest_msrs) |
9628 | goto free_pml; | |
965b58a5 | 9629 | |
d462b819 NHE |
9630 | vmx->loaded_vmcs = &vmx->vmcs01; |
9631 | vmx->loaded_vmcs->vmcs = alloc_vmcs(); | |
355f4fb1 | 9632 | vmx->loaded_vmcs->shadow_vmcs = NULL; |
d462b819 | 9633 | if (!vmx->loaded_vmcs->vmcs) |
fb3f0f51 | 9634 | goto free_msrs; |
d462b819 | 9635 | loaded_vmcs_init(vmx->loaded_vmcs); |
a2fa3e9f | 9636 | |
15ad7146 AK |
9637 | cpu = get_cpu(); |
9638 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
e48672fa | 9639 | vmx->vcpu.cpu = cpu; |
12d79917 | 9640 | vmx_vcpu_setup(vmx); |
fb3f0f51 | 9641 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 9642 | put_cpu(); |
35754c98 | 9643 | if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { |
be6d05cf JK |
9644 | err = alloc_apic_access_page(kvm); |
9645 | if (err) | |
5e4a0b3c | 9646 | goto free_vmcs; |
a63cb560 | 9647 | } |
fb3f0f51 | 9648 | |
b927a3ce | 9649 | if (enable_ept) { |
f51770ed TC |
9650 | err = init_rmode_identity_map(kvm); |
9651 | if (err) | |
93ea5388 | 9652 | goto free_vmcs; |
b927a3ce | 9653 | } |
b7ebfb05 | 9654 | |
5c614b35 | 9655 | if (nested) { |
b9c237bb | 9656 | nested_vmx_setup_ctls_msrs(vmx); |
5c614b35 WL |
9657 | vmx->nested.vpid02 = allocate_vpid(); |
9658 | } | |
b9c237bb | 9659 | |
705699a1 | 9660 | vmx->nested.posted_intr_nv = -1; |
a9d30f33 | 9661 | vmx->nested.current_vmptr = -1ull; |
a9d30f33 | 9662 | |
37e4c997 HZ |
9663 | vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED; |
9664 | ||
31afb2ea PB |
9665 | /* |
9666 | * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR | |
9667 | * or POSTED_INTR_WAKEUP_VECTOR. | |
9668 | */ | |
9669 | vmx->pi_desc.nv = POSTED_INTR_VECTOR; | |
9670 | vmx->pi_desc.sn = 1; | |
9671 | ||
fb3f0f51 RR |
9672 | return &vmx->vcpu; |
9673 | ||
9674 | free_vmcs: | |
5c614b35 | 9675 | free_vpid(vmx->nested.vpid02); |
5f3fbc34 | 9676 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 | 9677 | free_msrs: |
fb3f0f51 | 9678 | kfree(vmx->guest_msrs); |
4e59516a PF |
9679 | free_pml: |
9680 | vmx_destroy_pml_buffer(vmx); | |
fb3f0f51 RR |
9681 | uninit_vcpu: |
9682 | kvm_vcpu_uninit(&vmx->vcpu); | |
9683 | free_vcpu: | |
991e7a0e | 9684 | free_vpid(vmx->vpid); |
a4770347 | 9685 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 9686 | return ERR_PTR(err); |
6aa8b732 AK |
9687 | } |
9688 | ||
002c7f7c YS |
9689 | static void __init vmx_check_processor_compat(void *rtn) |
9690 | { | |
9691 | struct vmcs_config vmcs_conf; | |
9692 | ||
9693 | *(int *)rtn = 0; | |
9694 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
9695 | *(int *)rtn = -EIO; | |
9696 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
9697 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
9698 | smp_processor_id()); | |
9699 | *(int *)rtn = -EIO; | |
9700 | } | |
9701 | } | |
9702 | ||
4b12f0de | 9703 | static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 | 9704 | { |
b18d5431 XG |
9705 | u8 cache; |
9706 | u64 ipat = 0; | |
4b12f0de | 9707 | |
522c68c4 | 9708 | /* For VT-d and EPT combination |
606decd6 | 9709 | * 1. MMIO: always map as UC |
522c68c4 SY |
9710 | * 2. EPT with VT-d: |
9711 | * a. VT-d without snooping control feature: can't guarantee the | |
606decd6 | 9712 | * result, try to trust guest. |
522c68c4 SY |
9713 | * b. VT-d with snooping control feature: snooping control feature of |
9714 | * VT-d engine can guarantee the cache correctness. Just set it | |
9715 | * to WB to keep consistent with host. So the same as item 3. | |
a19a6d11 | 9716 | * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep |
522c68c4 SY |
9717 | * consistent with host MTRR |
9718 | */ | |
606decd6 PB |
9719 | if (is_mmio) { |
9720 | cache = MTRR_TYPE_UNCACHABLE; | |
9721 | goto exit; | |
9722 | } | |
9723 | ||
9724 | if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { | |
b18d5431 XG |
9725 | ipat = VMX_EPT_IPAT_BIT; |
9726 | cache = MTRR_TYPE_WRBACK; | |
9727 | goto exit; | |
9728 | } | |
9729 | ||
9730 | if (kvm_read_cr0(vcpu) & X86_CR0_CD) { | |
9731 | ipat = VMX_EPT_IPAT_BIT; | |
0da029ed | 9732 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) |
fb279950 XG |
9733 | cache = MTRR_TYPE_WRBACK; |
9734 | else | |
9735 | cache = MTRR_TYPE_UNCACHABLE; | |
b18d5431 XG |
9736 | goto exit; |
9737 | } | |
9738 | ||
ff53604b | 9739 | cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); |
b18d5431 XG |
9740 | |
9741 | exit: | |
9742 | return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; | |
64d4d521 SY |
9743 | } |
9744 | ||
17cc3935 | 9745 | static int vmx_get_lpage_level(void) |
344f414f | 9746 | { |
878403b7 SY |
9747 | if (enable_ept && !cpu_has_vmx_ept_1g_page()) |
9748 | return PT_DIRECTORY_LEVEL; | |
9749 | else | |
9750 | /* For shadow and EPT supported 1GB page */ | |
9751 | return PT_PDPE_LEVEL; | |
344f414f JR |
9752 | } |
9753 | ||
feda805f XG |
9754 | static void vmcs_set_secondary_exec_control(u32 new_ctl) |
9755 | { | |
9756 | /* | |
9757 | * These bits in the secondary execution controls field | |
9758 | * are dynamic, the others are mostly based on the hypervisor | |
9759 | * architecture and the guest's CPUID. Do not touch the | |
9760 | * dynamic bits. | |
9761 | */ | |
9762 | u32 mask = | |
9763 | SECONDARY_EXEC_SHADOW_VMCS | | |
9764 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | | |
9765 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
9766 | ||
9767 | u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
9768 | ||
9769 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, | |
9770 | (new_ctl & ~mask) | (cur_ctl & mask)); | |
9771 | } | |
9772 | ||
8322ebbb DM |
9773 | /* |
9774 | * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits | |
9775 | * (indicating "allowed-1") if they are supported in the guest's CPUID. | |
9776 | */ | |
9777 | static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) | |
9778 | { | |
9779 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9780 | struct kvm_cpuid_entry2 *entry; | |
9781 | ||
9782 | vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff; | |
9783 | vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE; | |
9784 | ||
9785 | #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ | |
9786 | if (entry && (entry->_reg & (_cpuid_mask))) \ | |
9787 | vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \ | |
9788 | } while (0) | |
9789 | ||
9790 | entry = kvm_find_cpuid_entry(vcpu, 0x1, 0); | |
9791 | cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME)); | |
9792 | cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME)); | |
9793 | cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC)); | |
9794 | cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE)); | |
9795 | cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE)); | |
9796 | cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE)); | |
9797 | cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE)); | |
9798 | cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE)); | |
9799 | cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR)); | |
9800 | cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM)); | |
9801 | cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX)); | |
9802 | cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX)); | |
9803 | cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID)); | |
9804 | cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE)); | |
9805 | ||
9806 | entry = kvm_find_cpuid_entry(vcpu, 0x7, 0); | |
9807 | cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE)); | |
9808 | cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP)); | |
9809 | cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP)); | |
9810 | cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU)); | |
c4ad77e0 | 9811 | cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP)); |
8322ebbb DM |
9812 | |
9813 | #undef cr4_fixed1_update | |
9814 | } | |
9815 | ||
0e851880 SY |
9816 | static void vmx_cpuid_update(struct kvm_vcpu *vcpu) |
9817 | { | |
4e47c7a6 | 9818 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4e47c7a6 | 9819 | |
80154d77 PB |
9820 | if (cpu_has_secondary_exec_ctrls()) { |
9821 | vmx_compute_secondary_exec_control(vmx); | |
9822 | vmcs_set_secondary_exec_control(vmx->secondary_exec_control); | |
ad756a16 | 9823 | } |
8b3e34e4 | 9824 | |
37e4c997 HZ |
9825 | if (nested_vmx_allowed(vcpu)) |
9826 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= | |
9827 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
9828 | else | |
9829 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= | |
9830 | ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
8322ebbb DM |
9831 | |
9832 | if (nested_vmx_allowed(vcpu)) | |
9833 | nested_vmx_cr_fixed1_bits_update(vcpu); | |
0e851880 SY |
9834 | } |
9835 | ||
d4330ef2 JR |
9836 | static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
9837 | { | |
7b8050f5 NHE |
9838 | if (func == 1 && nested) |
9839 | entry->ecx |= bit(X86_FEATURE_VMX); | |
d4330ef2 JR |
9840 | } |
9841 | ||
25d92081 YZ |
9842 | static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu, |
9843 | struct x86_exception *fault) | |
9844 | { | |
533558bc | 9845 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
c5f983f6 | 9846 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
533558bc | 9847 | u32 exit_reason; |
c5f983f6 | 9848 | unsigned long exit_qualification = vcpu->arch.exit_qualification; |
25d92081 | 9849 | |
c5f983f6 BD |
9850 | if (vmx->nested.pml_full) { |
9851 | exit_reason = EXIT_REASON_PML_FULL; | |
9852 | vmx->nested.pml_full = false; | |
9853 | exit_qualification &= INTR_INFO_UNBLOCK_NMI; | |
9854 | } else if (fault->error_code & PFERR_RSVD_MASK) | |
533558bc | 9855 | exit_reason = EXIT_REASON_EPT_MISCONFIG; |
25d92081 | 9856 | else |
533558bc | 9857 | exit_reason = EXIT_REASON_EPT_VIOLATION; |
c5f983f6 BD |
9858 | |
9859 | nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification); | |
25d92081 YZ |
9860 | vmcs12->guest_physical_address = fault->address; |
9861 | } | |
9862 | ||
995f00a6 PF |
9863 | static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu) |
9864 | { | |
bb97a016 | 9865 | return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT; |
995f00a6 PF |
9866 | } |
9867 | ||
155a97a3 NHE |
9868 | /* Callbacks for nested_ept_init_mmu_context: */ |
9869 | ||
9870 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu) | |
9871 | { | |
9872 | /* return the page table to be shadowed - in our case, EPT12 */ | |
9873 | return get_vmcs12(vcpu)->ept_pointer; | |
9874 | } | |
9875 | ||
ae1e2d10 | 9876 | static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu) |
155a97a3 | 9877 | { |
ad896af0 | 9878 | WARN_ON(mmu_is_nested(vcpu)); |
a057e0e2 | 9879 | if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu))) |
ae1e2d10 PB |
9880 | return 1; |
9881 | ||
9882 | kvm_mmu_unload(vcpu); | |
ad896af0 | 9883 | kvm_init_shadow_ept_mmu(vcpu, |
b9c237bb | 9884 | to_vmx(vcpu)->nested.nested_vmx_ept_caps & |
ae1e2d10 | 9885 | VMX_EPT_EXECUTE_ONLY_BIT, |
a057e0e2 | 9886 | nested_ept_ad_enabled(vcpu)); |
155a97a3 NHE |
9887 | vcpu->arch.mmu.set_cr3 = vmx_set_cr3; |
9888 | vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3; | |
9889 | vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault; | |
9890 | ||
9891 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
ae1e2d10 | 9892 | return 0; |
155a97a3 NHE |
9893 | } |
9894 | ||
9895 | static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
9896 | { | |
9897 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
9898 | } | |
9899 | ||
19d5f10b EK |
9900 | static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12, |
9901 | u16 error_code) | |
9902 | { | |
9903 | bool inequality, bit; | |
9904 | ||
9905 | bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0; | |
9906 | inequality = | |
9907 | (error_code & vmcs12->page_fault_error_code_mask) != | |
9908 | vmcs12->page_fault_error_code_match; | |
9909 | return inequality ^ bit; | |
9910 | } | |
9911 | ||
feaf0c7d GN |
9912 | static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu, |
9913 | struct x86_exception *fault) | |
9914 | { | |
9915 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
9916 | ||
9917 | WARN_ON(!is_guest_mode(vcpu)); | |
9918 | ||
305d0ab4 WL |
9919 | if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) && |
9920 | !to_vmx(vcpu)->nested.nested_run_pending) { | |
b96fb439 PB |
9921 | vmcs12->vm_exit_intr_error_code = fault->error_code; |
9922 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, | |
9923 | PF_VECTOR | INTR_TYPE_HARD_EXCEPTION | | |
9924 | INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK, | |
9925 | fault->address); | |
7313c698 | 9926 | } else { |
feaf0c7d | 9927 | kvm_inject_page_fault(vcpu, fault); |
7313c698 | 9928 | } |
feaf0c7d GN |
9929 | } |
9930 | ||
6beb7bd5 JM |
9931 | static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu, |
9932 | struct vmcs12 *vmcs12); | |
9933 | ||
9934 | static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu, | |
a2bcba50 WL |
9935 | struct vmcs12 *vmcs12) |
9936 | { | |
9937 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5e2f30b7 | 9938 | struct page *page; |
6beb7bd5 | 9939 | u64 hpa; |
a2bcba50 WL |
9940 | |
9941 | if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
a2bcba50 WL |
9942 | /* |
9943 | * Translate L1 physical address to host physical | |
9944 | * address for vmcs02. Keep the page pinned, so this | |
9945 | * physical address remains valid. We keep a reference | |
9946 | * to it so we can release it later. | |
9947 | */ | |
5e2f30b7 | 9948 | if (vmx->nested.apic_access_page) { /* shouldn't happen */ |
53a70daf | 9949 | kvm_release_page_dirty(vmx->nested.apic_access_page); |
5e2f30b7 DH |
9950 | vmx->nested.apic_access_page = NULL; |
9951 | } | |
9952 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr); | |
6beb7bd5 JM |
9953 | /* |
9954 | * If translation failed, no matter: This feature asks | |
9955 | * to exit when accessing the given address, and if it | |
9956 | * can never be accessed, this feature won't do | |
9957 | * anything anyway. | |
9958 | */ | |
5e2f30b7 DH |
9959 | if (!is_error_page(page)) { |
9960 | vmx->nested.apic_access_page = page; | |
6beb7bd5 JM |
9961 | hpa = page_to_phys(vmx->nested.apic_access_page); |
9962 | vmcs_write64(APIC_ACCESS_ADDR, hpa); | |
9963 | } else { | |
9964 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, | |
9965 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
9966 | } | |
9967 | } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) && | |
9968 | cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { | |
9969 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
9970 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
9971 | kvm_vcpu_reload_apic_access_page(vcpu); | |
a2bcba50 | 9972 | } |
a7c0b07d WL |
9973 | |
9974 | if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { | |
5e2f30b7 | 9975 | if (vmx->nested.virtual_apic_page) { /* shouldn't happen */ |
53a70daf | 9976 | kvm_release_page_dirty(vmx->nested.virtual_apic_page); |
5e2f30b7 DH |
9977 | vmx->nested.virtual_apic_page = NULL; |
9978 | } | |
9979 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr); | |
a7c0b07d WL |
9980 | |
9981 | /* | |
6beb7bd5 JM |
9982 | * If translation failed, VM entry will fail because |
9983 | * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull. | |
9984 | * Failing the vm entry is _not_ what the processor | |
9985 | * does but it's basically the only possibility we | |
9986 | * have. We could still enter the guest if CR8 load | |
9987 | * exits are enabled, CR8 store exits are enabled, and | |
9988 | * virtualize APIC access is disabled; in this case | |
9989 | * the processor would never use the TPR shadow and we | |
9990 | * could simply clear the bit from the execution | |
9991 | * control. But such a configuration is useless, so | |
9992 | * let's keep the code simple. | |
a7c0b07d | 9993 | */ |
5e2f30b7 DH |
9994 | if (!is_error_page(page)) { |
9995 | vmx->nested.virtual_apic_page = page; | |
6beb7bd5 JM |
9996 | hpa = page_to_phys(vmx->nested.virtual_apic_page); |
9997 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa); | |
9998 | } | |
a7c0b07d WL |
9999 | } |
10000 | ||
705699a1 | 10001 | if (nested_cpu_has_posted_intr(vmcs12)) { |
705699a1 WV |
10002 | if (vmx->nested.pi_desc_page) { /* shouldn't happen */ |
10003 | kunmap(vmx->nested.pi_desc_page); | |
53a70daf | 10004 | kvm_release_page_dirty(vmx->nested.pi_desc_page); |
5e2f30b7 | 10005 | vmx->nested.pi_desc_page = NULL; |
705699a1 | 10006 | } |
5e2f30b7 DH |
10007 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr); |
10008 | if (is_error_page(page)) | |
6beb7bd5 | 10009 | return; |
5e2f30b7 DH |
10010 | vmx->nested.pi_desc_page = page; |
10011 | vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page); | |
705699a1 WV |
10012 | vmx->nested.pi_desc = |
10013 | (struct pi_desc *)((void *)vmx->nested.pi_desc + | |
10014 | (unsigned long)(vmcs12->posted_intr_desc_addr & | |
10015 | (PAGE_SIZE - 1))); | |
6beb7bd5 JM |
10016 | vmcs_write64(POSTED_INTR_DESC_ADDR, |
10017 | page_to_phys(vmx->nested.pi_desc_page) + | |
10018 | (unsigned long)(vmcs12->posted_intr_desc_addr & | |
10019 | (PAGE_SIZE - 1))); | |
705699a1 | 10020 | } |
6beb7bd5 JM |
10021 | if (cpu_has_vmx_msr_bitmap() && |
10022 | nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) && | |
10023 | nested_vmx_merge_msr_bitmap(vcpu, vmcs12)) | |
10024 | ; | |
10025 | else | |
10026 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, | |
10027 | CPU_BASED_USE_MSR_BITMAPS); | |
a2bcba50 WL |
10028 | } |
10029 | ||
f4124500 JK |
10030 | static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu) |
10031 | { | |
10032 | u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value; | |
10033 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10034 | ||
10035 | if (vcpu->arch.virtual_tsc_khz == 0) | |
10036 | return; | |
10037 | ||
10038 | /* Make sure short timeouts reliably trigger an immediate vmexit. | |
10039 | * hrtimer_start does not guarantee this. */ | |
10040 | if (preemption_timeout <= 1) { | |
10041 | vmx_preemption_timer_fn(&vmx->nested.preemption_timer); | |
10042 | return; | |
10043 | } | |
10044 | ||
10045 | preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
10046 | preemption_timeout *= 1000000; | |
10047 | do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz); | |
10048 | hrtimer_start(&vmx->nested.preemption_timer, | |
10049 | ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL); | |
10050 | } | |
10051 | ||
56a20510 JM |
10052 | static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu, |
10053 | struct vmcs12 *vmcs12) | |
10054 | { | |
10055 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) | |
10056 | return 0; | |
10057 | ||
10058 | if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) || | |
10059 | !page_address_valid(vcpu, vmcs12->io_bitmap_b)) | |
10060 | return -EINVAL; | |
10061 | ||
10062 | return 0; | |
10063 | } | |
10064 | ||
3af18d9c WV |
10065 | static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, |
10066 | struct vmcs12 *vmcs12) | |
10067 | { | |
3af18d9c WV |
10068 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) |
10069 | return 0; | |
10070 | ||
5fa99cbe | 10071 | if (!page_address_valid(vcpu, vmcs12->msr_bitmap)) |
3af18d9c WV |
10072 | return -EINVAL; |
10073 | ||
10074 | return 0; | |
10075 | } | |
10076 | ||
712b12d7 JM |
10077 | static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu, |
10078 | struct vmcs12 *vmcs12) | |
10079 | { | |
10080 | if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
10081 | return 0; | |
10082 | ||
10083 | if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr)) | |
10084 | return -EINVAL; | |
10085 | ||
10086 | return 0; | |
10087 | } | |
10088 | ||
3af18d9c WV |
10089 | /* |
10090 | * Merge L0's and L1's MSR bitmap, return false to indicate that | |
10091 | * we do not use the hardware. | |
10092 | */ | |
10093 | static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu, | |
10094 | struct vmcs12 *vmcs12) | |
10095 | { | |
82f0dd4b | 10096 | int msr; |
f2b93280 | 10097 | struct page *page; |
d048c098 RK |
10098 | unsigned long *msr_bitmap_l1; |
10099 | unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap; | |
f2b93280 | 10100 | |
d048c098 | 10101 | /* This shortcut is ok because we support only x2APIC MSRs so far. */ |
f2b93280 WV |
10102 | if (!nested_cpu_has_virt_x2apic_mode(vmcs12)) |
10103 | return false; | |
10104 | ||
5e2f30b7 DH |
10105 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap); |
10106 | if (is_error_page(page)) | |
f2b93280 | 10107 | return false; |
d048c098 | 10108 | msr_bitmap_l1 = (unsigned long *)kmap(page); |
f2b93280 | 10109 | |
d048c098 RK |
10110 | memset(msr_bitmap_l0, 0xff, PAGE_SIZE); |
10111 | ||
f2b93280 | 10112 | if (nested_cpu_has_virt_x2apic_mode(vmcs12)) { |
82f0dd4b WV |
10113 | if (nested_cpu_has_apic_reg_virt(vmcs12)) |
10114 | for (msr = 0x800; msr <= 0x8ff; msr++) | |
10115 | nested_vmx_disable_intercept_for_msr( | |
d048c098 | 10116 | msr_bitmap_l1, msr_bitmap_l0, |
82f0dd4b | 10117 | msr, MSR_TYPE_R); |
d048c098 RK |
10118 | |
10119 | nested_vmx_disable_intercept_for_msr( | |
10120 | msr_bitmap_l1, msr_bitmap_l0, | |
f2b93280 WV |
10121 | APIC_BASE_MSR + (APIC_TASKPRI >> 4), |
10122 | MSR_TYPE_R | MSR_TYPE_W); | |
d048c098 | 10123 | |
608406e2 | 10124 | if (nested_cpu_has_vid(vmcs12)) { |
608406e2 | 10125 | nested_vmx_disable_intercept_for_msr( |
d048c098 | 10126 | msr_bitmap_l1, msr_bitmap_l0, |
608406e2 WV |
10127 | APIC_BASE_MSR + (APIC_EOI >> 4), |
10128 | MSR_TYPE_W); | |
10129 | nested_vmx_disable_intercept_for_msr( | |
d048c098 | 10130 | msr_bitmap_l1, msr_bitmap_l0, |
608406e2 WV |
10131 | APIC_BASE_MSR + (APIC_SELF_IPI >> 4), |
10132 | MSR_TYPE_W); | |
10133 | } | |
82f0dd4b | 10134 | } |
f2b93280 | 10135 | kunmap(page); |
53a70daf | 10136 | kvm_release_page_clean(page); |
f2b93280 WV |
10137 | |
10138 | return true; | |
10139 | } | |
10140 | ||
10141 | static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu, | |
10142 | struct vmcs12 *vmcs12) | |
10143 | { | |
82f0dd4b | 10144 | if (!nested_cpu_has_virt_x2apic_mode(vmcs12) && |
608406e2 | 10145 | !nested_cpu_has_apic_reg_virt(vmcs12) && |
705699a1 WV |
10146 | !nested_cpu_has_vid(vmcs12) && |
10147 | !nested_cpu_has_posted_intr(vmcs12)) | |
f2b93280 WV |
10148 | return 0; |
10149 | ||
10150 | /* | |
10151 | * If virtualize x2apic mode is enabled, | |
10152 | * virtualize apic access must be disabled. | |
10153 | */ | |
82f0dd4b WV |
10154 | if (nested_cpu_has_virt_x2apic_mode(vmcs12) && |
10155 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
f2b93280 WV |
10156 | return -EINVAL; |
10157 | ||
608406e2 WV |
10158 | /* |
10159 | * If virtual interrupt delivery is enabled, | |
10160 | * we must exit on external interrupts. | |
10161 | */ | |
10162 | if (nested_cpu_has_vid(vmcs12) && | |
10163 | !nested_exit_on_intr(vcpu)) | |
10164 | return -EINVAL; | |
10165 | ||
705699a1 WV |
10166 | /* |
10167 | * bits 15:8 should be zero in posted_intr_nv, | |
10168 | * the descriptor address has been already checked | |
10169 | * in nested_get_vmcs12_pages. | |
10170 | */ | |
10171 | if (nested_cpu_has_posted_intr(vmcs12) && | |
10172 | (!nested_cpu_has_vid(vmcs12) || | |
10173 | !nested_exit_intr_ack_set(vcpu) || | |
10174 | vmcs12->posted_intr_nv & 0xff00)) | |
10175 | return -EINVAL; | |
10176 | ||
f2b93280 WV |
10177 | /* tpr shadow is needed by all apicv features. */ |
10178 | if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
10179 | return -EINVAL; | |
10180 | ||
10181 | return 0; | |
3af18d9c WV |
10182 | } |
10183 | ||
e9ac033e EK |
10184 | static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu, |
10185 | unsigned long count_field, | |
92d71bc6 | 10186 | unsigned long addr_field) |
ff651cb6 | 10187 | { |
92d71bc6 | 10188 | int maxphyaddr; |
e9ac033e EK |
10189 | u64 count, addr; |
10190 | ||
10191 | if (vmcs12_read_any(vcpu, count_field, &count) || | |
10192 | vmcs12_read_any(vcpu, addr_field, &addr)) { | |
10193 | WARN_ON(1); | |
10194 | return -EINVAL; | |
10195 | } | |
10196 | if (count == 0) | |
10197 | return 0; | |
92d71bc6 | 10198 | maxphyaddr = cpuid_maxphyaddr(vcpu); |
e9ac033e EK |
10199 | if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr || |
10200 | (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) { | |
bbe41b95 | 10201 | pr_debug_ratelimited( |
e9ac033e EK |
10202 | "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)", |
10203 | addr_field, maxphyaddr, count, addr); | |
10204 | return -EINVAL; | |
10205 | } | |
10206 | return 0; | |
10207 | } | |
10208 | ||
10209 | static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu, | |
10210 | struct vmcs12 *vmcs12) | |
10211 | { | |
e9ac033e EK |
10212 | if (vmcs12->vm_exit_msr_load_count == 0 && |
10213 | vmcs12->vm_exit_msr_store_count == 0 && | |
10214 | vmcs12->vm_entry_msr_load_count == 0) | |
10215 | return 0; /* Fast path */ | |
e9ac033e | 10216 | if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT, |
92d71bc6 | 10217 | VM_EXIT_MSR_LOAD_ADDR) || |
e9ac033e | 10218 | nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT, |
92d71bc6 | 10219 | VM_EXIT_MSR_STORE_ADDR) || |
e9ac033e | 10220 | nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT, |
92d71bc6 | 10221 | VM_ENTRY_MSR_LOAD_ADDR)) |
e9ac033e EK |
10222 | return -EINVAL; |
10223 | return 0; | |
10224 | } | |
10225 | ||
c5f983f6 BD |
10226 | static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu, |
10227 | struct vmcs12 *vmcs12) | |
10228 | { | |
10229 | u64 address = vmcs12->pml_address; | |
10230 | int maxphyaddr = cpuid_maxphyaddr(vcpu); | |
10231 | ||
10232 | if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) { | |
10233 | if (!nested_cpu_has_ept(vmcs12) || | |
10234 | !IS_ALIGNED(address, 4096) || | |
10235 | address >> maxphyaddr) | |
10236 | return -EINVAL; | |
10237 | } | |
10238 | ||
10239 | return 0; | |
10240 | } | |
10241 | ||
e9ac033e EK |
10242 | static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu, |
10243 | struct vmx_msr_entry *e) | |
10244 | { | |
10245 | /* x2APIC MSR accesses are not allowed */ | |
8a9781f7 | 10246 | if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8) |
e9ac033e EK |
10247 | return -EINVAL; |
10248 | if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */ | |
10249 | e->index == MSR_IA32_UCODE_REV) | |
10250 | return -EINVAL; | |
10251 | if (e->reserved != 0) | |
ff651cb6 WV |
10252 | return -EINVAL; |
10253 | return 0; | |
10254 | } | |
10255 | ||
e9ac033e EK |
10256 | static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu, |
10257 | struct vmx_msr_entry *e) | |
ff651cb6 WV |
10258 | { |
10259 | if (e->index == MSR_FS_BASE || | |
10260 | e->index == MSR_GS_BASE || | |
e9ac033e EK |
10261 | e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */ |
10262 | nested_vmx_msr_check_common(vcpu, e)) | |
10263 | return -EINVAL; | |
10264 | return 0; | |
10265 | } | |
10266 | ||
10267 | static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu, | |
10268 | struct vmx_msr_entry *e) | |
10269 | { | |
10270 | if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */ | |
10271 | nested_vmx_msr_check_common(vcpu, e)) | |
ff651cb6 WV |
10272 | return -EINVAL; |
10273 | return 0; | |
10274 | } | |
10275 | ||
10276 | /* | |
10277 | * Load guest's/host's msr at nested entry/exit. | |
10278 | * return 0 for success, entry index for failure. | |
10279 | */ | |
10280 | static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) | |
10281 | { | |
10282 | u32 i; | |
10283 | struct vmx_msr_entry e; | |
10284 | struct msr_data msr; | |
10285 | ||
10286 | msr.host_initiated = false; | |
10287 | for (i = 0; i < count; i++) { | |
54bf36aa PB |
10288 | if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e), |
10289 | &e, sizeof(e))) { | |
bbe41b95 | 10290 | pr_debug_ratelimited( |
e9ac033e EK |
10291 | "%s cannot read MSR entry (%u, 0x%08llx)\n", |
10292 | __func__, i, gpa + i * sizeof(e)); | |
ff651cb6 | 10293 | goto fail; |
e9ac033e EK |
10294 | } |
10295 | if (nested_vmx_load_msr_check(vcpu, &e)) { | |
bbe41b95 | 10296 | pr_debug_ratelimited( |
e9ac033e EK |
10297 | "%s check failed (%u, 0x%x, 0x%x)\n", |
10298 | __func__, i, e.index, e.reserved); | |
10299 | goto fail; | |
10300 | } | |
ff651cb6 WV |
10301 | msr.index = e.index; |
10302 | msr.data = e.value; | |
e9ac033e | 10303 | if (kvm_set_msr(vcpu, &msr)) { |
bbe41b95 | 10304 | pr_debug_ratelimited( |
e9ac033e EK |
10305 | "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", |
10306 | __func__, i, e.index, e.value); | |
ff651cb6 | 10307 | goto fail; |
e9ac033e | 10308 | } |
ff651cb6 WV |
10309 | } |
10310 | return 0; | |
10311 | fail: | |
10312 | return i + 1; | |
10313 | } | |
10314 | ||
10315 | static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) | |
10316 | { | |
10317 | u32 i; | |
10318 | struct vmx_msr_entry e; | |
10319 | ||
10320 | for (i = 0; i < count; i++) { | |
609e36d3 | 10321 | struct msr_data msr_info; |
54bf36aa PB |
10322 | if (kvm_vcpu_read_guest(vcpu, |
10323 | gpa + i * sizeof(e), | |
10324 | &e, 2 * sizeof(u32))) { | |
bbe41b95 | 10325 | pr_debug_ratelimited( |
e9ac033e EK |
10326 | "%s cannot read MSR entry (%u, 0x%08llx)\n", |
10327 | __func__, i, gpa + i * sizeof(e)); | |
ff651cb6 | 10328 | return -EINVAL; |
e9ac033e EK |
10329 | } |
10330 | if (nested_vmx_store_msr_check(vcpu, &e)) { | |
bbe41b95 | 10331 | pr_debug_ratelimited( |
e9ac033e EK |
10332 | "%s check failed (%u, 0x%x, 0x%x)\n", |
10333 | __func__, i, e.index, e.reserved); | |
ff651cb6 | 10334 | return -EINVAL; |
e9ac033e | 10335 | } |
609e36d3 PB |
10336 | msr_info.host_initiated = false; |
10337 | msr_info.index = e.index; | |
10338 | if (kvm_get_msr(vcpu, &msr_info)) { | |
bbe41b95 | 10339 | pr_debug_ratelimited( |
e9ac033e EK |
10340 | "%s cannot read MSR (%u, 0x%x)\n", |
10341 | __func__, i, e.index); | |
10342 | return -EINVAL; | |
10343 | } | |
54bf36aa PB |
10344 | if (kvm_vcpu_write_guest(vcpu, |
10345 | gpa + i * sizeof(e) + | |
10346 | offsetof(struct vmx_msr_entry, value), | |
10347 | &msr_info.data, sizeof(msr_info.data))) { | |
bbe41b95 | 10348 | pr_debug_ratelimited( |
e9ac033e | 10349 | "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", |
609e36d3 | 10350 | __func__, i, e.index, msr_info.data); |
e9ac033e EK |
10351 | return -EINVAL; |
10352 | } | |
ff651cb6 WV |
10353 | } |
10354 | return 0; | |
10355 | } | |
10356 | ||
1dc35dac LP |
10357 | static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val) |
10358 | { | |
10359 | unsigned long invalid_mask; | |
10360 | ||
10361 | invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu); | |
10362 | return (val & invalid_mask) == 0; | |
10363 | } | |
10364 | ||
9ed38ffa LP |
10365 | /* |
10366 | * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are | |
10367 | * emulating VM entry into a guest with EPT enabled. | |
10368 | * Returns 0 on success, 1 on failure. Invalid state exit qualification code | |
10369 | * is assigned to entry_failure_code on failure. | |
10370 | */ | |
10371 | static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept, | |
ca0bde28 | 10372 | u32 *entry_failure_code) |
9ed38ffa | 10373 | { |
9ed38ffa | 10374 | if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) { |
1dc35dac | 10375 | if (!nested_cr3_valid(vcpu, cr3)) { |
9ed38ffa LP |
10376 | *entry_failure_code = ENTRY_FAIL_DEFAULT; |
10377 | return 1; | |
10378 | } | |
10379 | ||
10380 | /* | |
10381 | * If PAE paging and EPT are both on, CR3 is not used by the CPU and | |
10382 | * must not be dereferenced. | |
10383 | */ | |
10384 | if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) && | |
10385 | !nested_ept) { | |
10386 | if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) { | |
10387 | *entry_failure_code = ENTRY_FAIL_PDPTE; | |
10388 | return 1; | |
10389 | } | |
10390 | } | |
10391 | ||
10392 | vcpu->arch.cr3 = cr3; | |
10393 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
10394 | } | |
10395 | ||
10396 | kvm_mmu_reset_context(vcpu); | |
10397 | return 0; | |
10398 | } | |
10399 | ||
fe3ef05c NHE |
10400 | /* |
10401 | * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested | |
10402 | * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it | |
b4619660 | 10403 | * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2 |
fe3ef05c NHE |
10404 | * guest in a way that will both be appropriate to L1's requests, and our |
10405 | * needs. In addition to modifying the active vmcs (which is vmcs02), this | |
10406 | * function also has additional necessary side-effects, like setting various | |
10407 | * vcpu->arch fields. | |
ee146c1c LP |
10408 | * Returns 0 on success, 1 on failure. Invalid state exit qualification code |
10409 | * is assigned to entry_failure_code on failure. | |
fe3ef05c | 10410 | */ |
ee146c1c | 10411 | static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, |
ca0bde28 | 10412 | bool from_vmentry, u32 *entry_failure_code) |
fe3ef05c NHE |
10413 | { |
10414 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
03efce6f | 10415 | u32 exec_control, vmcs12_exec_ctrl; |
fe3ef05c NHE |
10416 | |
10417 | vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector); | |
10418 | vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector); | |
10419 | vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector); | |
10420 | vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector); | |
10421 | vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector); | |
10422 | vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector); | |
10423 | vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector); | |
10424 | vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector); | |
10425 | vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit); | |
10426 | vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit); | |
10427 | vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit); | |
10428 | vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit); | |
10429 | vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit); | |
10430 | vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit); | |
10431 | vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit); | |
10432 | vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit); | |
10433 | vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit); | |
10434 | vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit); | |
10435 | vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes); | |
10436 | vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes); | |
10437 | vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes); | |
10438 | vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes); | |
10439 | vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes); | |
10440 | vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes); | |
10441 | vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes); | |
10442 | vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes); | |
10443 | vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base); | |
10444 | vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base); | |
10445 | vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base); | |
10446 | vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base); | |
10447 | vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base); | |
10448 | vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base); | |
10449 | vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base); | |
10450 | vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base); | |
10451 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base); | |
10452 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base); | |
10453 | ||
cf8b84f4 JM |
10454 | if (from_vmentry && |
10455 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) { | |
2996fca0 JK |
10456 | kvm_set_dr(vcpu, 7, vmcs12->guest_dr7); |
10457 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl); | |
10458 | } else { | |
10459 | kvm_set_dr(vcpu, 7, vcpu->arch.dr7); | |
10460 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl); | |
10461 | } | |
cf8b84f4 JM |
10462 | if (from_vmentry) { |
10463 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
10464 | vmcs12->vm_entry_intr_info_field); | |
10465 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, | |
10466 | vmcs12->vm_entry_exception_error_code); | |
10467 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
10468 | vmcs12->vm_entry_instruction_len); | |
10469 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
10470 | vmcs12->guest_interruptibility_info); | |
2d6144e3 WL |
10471 | vmx->loaded_vmcs->nmi_known_unmasked = |
10472 | !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI); | |
cf8b84f4 JM |
10473 | } else { |
10474 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); | |
10475 | } | |
fe3ef05c | 10476 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs); |
63fbf59f | 10477 | vmx_set_rflags(vcpu, vmcs12->guest_rflags); |
fe3ef05c NHE |
10478 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, |
10479 | vmcs12->guest_pending_dbg_exceptions); | |
10480 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp); | |
10481 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip); | |
10482 | ||
81dc01f7 WL |
10483 | if (nested_cpu_has_xsaves(vmcs12)) |
10484 | vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap); | |
fe3ef05c NHE |
10485 | vmcs_write64(VMCS_LINK_POINTER, -1ull); |
10486 | ||
f4124500 | 10487 | exec_control = vmcs12->pin_based_vm_exec_control; |
9314006d PB |
10488 | |
10489 | /* Preemption timer setting is only taken from vmcs01. */ | |
705699a1 | 10490 | exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; |
9314006d PB |
10491 | exec_control |= vmcs_config.pin_based_exec_ctrl; |
10492 | if (vmx->hv_deadline_tsc == -1) | |
10493 | exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
705699a1 | 10494 | |
9314006d | 10495 | /* Posted interrupts setting is only taken from vmcs12. */ |
705699a1 | 10496 | if (nested_cpu_has_posted_intr(vmcs12)) { |
705699a1 WV |
10497 | vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv; |
10498 | vmx->nested.pi_pending = false; | |
06a5524f | 10499 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR); |
6beb7bd5 | 10500 | } else { |
705699a1 | 10501 | exec_control &= ~PIN_BASED_POSTED_INTR; |
6beb7bd5 | 10502 | } |
705699a1 | 10503 | |
f4124500 | 10504 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control); |
fe3ef05c | 10505 | |
f4124500 JK |
10506 | vmx->nested.preemption_timer_expired = false; |
10507 | if (nested_cpu_has_preemption_timer(vmcs12)) | |
10508 | vmx_start_preemption_timer(vcpu); | |
0238ea91 | 10509 | |
fe3ef05c NHE |
10510 | /* |
10511 | * Whether page-faults are trapped is determined by a combination of | |
10512 | * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF. | |
10513 | * If enable_ept, L0 doesn't care about page faults and we should | |
10514 | * set all of these to L1's desires. However, if !enable_ept, L0 does | |
10515 | * care about (at least some) page faults, and because it is not easy | |
10516 | * (if at all possible?) to merge L0 and L1's desires, we simply ask | |
10517 | * to exit on each and every L2 page fault. This is done by setting | |
10518 | * MASK=MATCH=0 and (see below) EB.PF=1. | |
10519 | * Note that below we don't need special code to set EB.PF beyond the | |
10520 | * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept, | |
10521 | * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when | |
10522 | * !enable_ept, EB.PF is 1, so the "or" will always be 1. | |
fe3ef05c NHE |
10523 | */ |
10524 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, | |
10525 | enable_ept ? vmcs12->page_fault_error_code_mask : 0); | |
10526 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, | |
10527 | enable_ept ? vmcs12->page_fault_error_code_match : 0); | |
10528 | ||
10529 | if (cpu_has_secondary_exec_ctrls()) { | |
80154d77 | 10530 | exec_control = vmx->secondary_exec_control; |
e2821620 | 10531 | |
fe3ef05c | 10532 | /* Take the following fields only from vmcs12 */ |
696dfd95 | 10533 | exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
90a2db6d | 10534 | SECONDARY_EXEC_ENABLE_INVPCID | |
b3a2a907 | 10535 | SECONDARY_EXEC_RDTSCP | |
3db13480 | 10536 | SECONDARY_EXEC_XSAVES | |
696dfd95 | 10537 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
27c42a1b BD |
10538 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
10539 | SECONDARY_EXEC_ENABLE_VMFUNC); | |
fe3ef05c | 10540 | if (nested_cpu_has(vmcs12, |
03efce6f BD |
10541 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) { |
10542 | vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control & | |
10543 | ~SECONDARY_EXEC_ENABLE_PML; | |
10544 | exec_control |= vmcs12_exec_ctrl; | |
10545 | } | |
fe3ef05c | 10546 | |
27c42a1b BD |
10547 | /* All VMFUNCs are currently emulated through L0 vmexits. */ |
10548 | if (exec_control & SECONDARY_EXEC_ENABLE_VMFUNC) | |
10549 | vmcs_write64(VM_FUNCTION_CONTROL, 0); | |
10550 | ||
608406e2 WV |
10551 | if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { |
10552 | vmcs_write64(EOI_EXIT_BITMAP0, | |
10553 | vmcs12->eoi_exit_bitmap0); | |
10554 | vmcs_write64(EOI_EXIT_BITMAP1, | |
10555 | vmcs12->eoi_exit_bitmap1); | |
10556 | vmcs_write64(EOI_EXIT_BITMAP2, | |
10557 | vmcs12->eoi_exit_bitmap2); | |
10558 | vmcs_write64(EOI_EXIT_BITMAP3, | |
10559 | vmcs12->eoi_exit_bitmap3); | |
10560 | vmcs_write16(GUEST_INTR_STATUS, | |
10561 | vmcs12->guest_intr_status); | |
10562 | } | |
10563 | ||
6beb7bd5 JM |
10564 | /* |
10565 | * Write an illegal value to APIC_ACCESS_ADDR. Later, | |
10566 | * nested_get_vmcs12_pages will either fix it up or | |
10567 | * remove the VM execution control. | |
10568 | */ | |
10569 | if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) | |
10570 | vmcs_write64(APIC_ACCESS_ADDR, -1ull); | |
10571 | ||
fe3ef05c NHE |
10572 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); |
10573 | } | |
10574 | ||
10575 | ||
10576 | /* | |
10577 | * Set host-state according to L0's settings (vmcs12 is irrelevant here) | |
10578 | * Some constant fields are set here by vmx_set_constant_host_state(). | |
10579 | * Other fields are different per CPU, and will be set later when | |
10580 | * vmx_vcpu_load() is called, and when vmx_save_host_state() is called. | |
10581 | */ | |
a547c6db | 10582 | vmx_set_constant_host_state(vmx); |
fe3ef05c | 10583 | |
83bafef1 JM |
10584 | /* |
10585 | * Set the MSR load/store lists to match L0's settings. | |
10586 | */ | |
10587 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); | |
10588 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr); | |
10589 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host)); | |
10590 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr); | |
10591 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest)); | |
10592 | ||
fe3ef05c NHE |
10593 | /* |
10594 | * HOST_RSP is normally set correctly in vmx_vcpu_run() just before | |
10595 | * entry, but only if the current (host) sp changed from the value | |
10596 | * we wrote last (vmx->host_rsp). This cache is no longer relevant | |
10597 | * if we switch vmcs, and rather than hold a separate cache per vmcs, | |
10598 | * here we just force the write to happen on entry. | |
10599 | */ | |
10600 | vmx->host_rsp = 0; | |
10601 | ||
10602 | exec_control = vmx_exec_control(vmx); /* L0's desires */ | |
10603 | exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
10604 | exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
10605 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
10606 | exec_control |= vmcs12->cpu_based_vm_exec_control; | |
a7c0b07d | 10607 | |
6beb7bd5 JM |
10608 | /* |
10609 | * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if | |
10610 | * nested_get_vmcs12_pages can't fix it up, the illegal value | |
10611 | * will result in a VM entry failure. | |
10612 | */ | |
a7c0b07d | 10613 | if (exec_control & CPU_BASED_TPR_SHADOW) { |
6beb7bd5 | 10614 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull); |
a7c0b07d | 10615 | vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold); |
51aa68e7 JM |
10616 | } else { |
10617 | #ifdef CONFIG_X86_64 | |
10618 | exec_control |= CPU_BASED_CR8_LOAD_EXITING | | |
10619 | CPU_BASED_CR8_STORE_EXITING; | |
10620 | #endif | |
a7c0b07d WL |
10621 | } |
10622 | ||
fe3ef05c | 10623 | /* |
3af18d9c | 10624 | * Merging of IO bitmap not currently supported. |
fe3ef05c NHE |
10625 | * Rather, exit every time. |
10626 | */ | |
fe3ef05c NHE |
10627 | exec_control &= ~CPU_BASED_USE_IO_BITMAPS; |
10628 | exec_control |= CPU_BASED_UNCOND_IO_EXITING; | |
10629 | ||
10630 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); | |
10631 | ||
10632 | /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the | |
10633 | * bitwise-or of what L1 wants to trap for L2, and what we want to | |
10634 | * trap. Note that CR0.TS also needs updating - we do this later. | |
10635 | */ | |
10636 | update_exception_bitmap(vcpu); | |
10637 | vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask; | |
10638 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
10639 | ||
8049d651 NHE |
10640 | /* L2->L1 exit controls are emulated - the hardware exit is to L0 so |
10641 | * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER | |
10642 | * bits are further modified by vmx_set_efer() below. | |
10643 | */ | |
f4124500 | 10644 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
8049d651 NHE |
10645 | |
10646 | /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are | |
10647 | * emulated by vmx_set_efer(), below. | |
10648 | */ | |
2961e876 | 10649 | vm_entry_controls_init(vmx, |
8049d651 NHE |
10650 | (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER & |
10651 | ~VM_ENTRY_IA32E_MODE) | | |
fe3ef05c NHE |
10652 | (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE)); |
10653 | ||
cf8b84f4 JM |
10654 | if (from_vmentry && |
10655 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) { | |
fe3ef05c | 10656 | vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat); |
44811c02 | 10657 | vcpu->arch.pat = vmcs12->guest_ia32_pat; |
cf8b84f4 | 10658 | } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { |
fe3ef05c | 10659 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); |
cf8b84f4 | 10660 | } |
fe3ef05c NHE |
10661 | |
10662 | set_cr4_guest_host_mask(vmx); | |
10663 | ||
cf8b84f4 JM |
10664 | if (from_vmentry && |
10665 | vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) | |
36be0b9d PB |
10666 | vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs); |
10667 | ||
27fc51b2 NHE |
10668 | if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING) |
10669 | vmcs_write64(TSC_OFFSET, | |
ea26e4ec | 10670 | vcpu->arch.tsc_offset + vmcs12->tsc_offset); |
27fc51b2 | 10671 | else |
ea26e4ec | 10672 | vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); |
c95ba92a PF |
10673 | if (kvm_has_tsc_control) |
10674 | decache_tsc_multiplier(vmx); | |
fe3ef05c NHE |
10675 | |
10676 | if (enable_vpid) { | |
10677 | /* | |
5c614b35 WL |
10678 | * There is no direct mapping between vpid02 and vpid12, the |
10679 | * vpid02 is per-vCPU for L0 and reused while the value of | |
10680 | * vpid12 is changed w/ one invvpid during nested vmentry. | |
10681 | * The vpid12 is allocated by L1 for L2, so it will not | |
10682 | * influence global bitmap(for vpid01 and vpid02 allocation) | |
10683 | * even if spawn a lot of nested vCPUs. | |
fe3ef05c | 10684 | */ |
5c614b35 WL |
10685 | if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) { |
10686 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02); | |
10687 | if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) { | |
10688 | vmx->nested.last_vpid = vmcs12->virtual_processor_id; | |
10689 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02); | |
10690 | } | |
10691 | } else { | |
10692 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
10693 | vmx_flush_tlb(vcpu); | |
10694 | } | |
10695 | ||
fe3ef05c NHE |
10696 | } |
10697 | ||
1fb883bb LP |
10698 | if (enable_pml) { |
10699 | /* | |
10700 | * Conceptually we want to copy the PML address and index from | |
10701 | * vmcs01 here, and then back to vmcs01 on nested vmexit. But, | |
10702 | * since we always flush the log on each vmexit, this happens | |
10703 | * to be equivalent to simply resetting the fields in vmcs02. | |
10704 | */ | |
10705 | ASSERT(vmx->pml_pg); | |
10706 | vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); | |
10707 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
10708 | } | |
10709 | ||
155a97a3 | 10710 | if (nested_cpu_has_ept(vmcs12)) { |
ae1e2d10 PB |
10711 | if (nested_ept_init_mmu_context(vcpu)) { |
10712 | *entry_failure_code = ENTRY_FAIL_DEFAULT; | |
10713 | return 1; | |
10714 | } | |
fb6c8198 JM |
10715 | } else if (nested_cpu_has2(vmcs12, |
10716 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
10717 | vmx_flush_tlb_ept_only(vcpu); | |
155a97a3 NHE |
10718 | } |
10719 | ||
fe3ef05c | 10720 | /* |
bd7e5b08 PB |
10721 | * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those |
10722 | * bits which we consider mandatory enabled. | |
fe3ef05c NHE |
10723 | * The CR0_READ_SHADOW is what L2 should have expected to read given |
10724 | * the specifications by L1; It's not enough to take | |
10725 | * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we | |
10726 | * have more bits than L1 expected. | |
10727 | */ | |
10728 | vmx_set_cr0(vcpu, vmcs12->guest_cr0); | |
10729 | vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12)); | |
10730 | ||
10731 | vmx_set_cr4(vcpu, vmcs12->guest_cr4); | |
10732 | vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12)); | |
10733 | ||
cf8b84f4 JM |
10734 | if (from_vmentry && |
10735 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) | |
5a6a9748 DM |
10736 | vcpu->arch.efer = vmcs12->guest_ia32_efer; |
10737 | else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) | |
10738 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); | |
10739 | else | |
10740 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
10741 | /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */ | |
10742 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
10743 | ||
9ed38ffa | 10744 | /* Shadow page tables on either EPT or shadow page tables. */ |
7ad658b6 | 10745 | if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12), |
9ed38ffa LP |
10746 | entry_failure_code)) |
10747 | return 1; | |
7ca29de2 | 10748 | |
feaf0c7d GN |
10749 | if (!enable_ept) |
10750 | vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested; | |
10751 | ||
3633cfc3 NHE |
10752 | /* |
10753 | * L1 may access the L2's PDPTR, so save them to construct vmcs12 | |
10754 | */ | |
10755 | if (enable_ept) { | |
10756 | vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0); | |
10757 | vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1); | |
10758 | vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2); | |
10759 | vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3); | |
10760 | } | |
10761 | ||
fe3ef05c NHE |
10762 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp); |
10763 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip); | |
ee146c1c | 10764 | return 0; |
fe3ef05c NHE |
10765 | } |
10766 | ||
ca0bde28 | 10767 | static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) |
cd232ad0 | 10768 | { |
cd232ad0 | 10769 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
7c177938 | 10770 | |
6dfacadd | 10771 | if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE && |
ca0bde28 JM |
10772 | vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) |
10773 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
26539bd0 | 10774 | |
56a20510 JM |
10775 | if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12)) |
10776 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
10777 | ||
ca0bde28 JM |
10778 | if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) |
10779 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
7c177938 | 10780 | |
712b12d7 JM |
10781 | if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12)) |
10782 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
10783 | ||
ca0bde28 JM |
10784 | if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) |
10785 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
f2b93280 | 10786 | |
ca0bde28 JM |
10787 | if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) |
10788 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
e9ac033e | 10789 | |
c5f983f6 BD |
10790 | if (nested_vmx_check_pml_controls(vcpu, vmcs12)) |
10791 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
10792 | ||
7c177938 | 10793 | if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control, |
0115f9cb | 10794 | vmx->nested.nested_vmx_procbased_ctls_low, |
b9c237bb | 10795 | vmx->nested.nested_vmx_procbased_ctls_high) || |
2e5b0bd9 JM |
10796 | (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && |
10797 | !vmx_control_verify(vmcs12->secondary_vm_exec_control, | |
10798 | vmx->nested.nested_vmx_secondary_ctls_low, | |
10799 | vmx->nested.nested_vmx_secondary_ctls_high)) || | |
7c177938 | 10800 | !vmx_control_verify(vmcs12->pin_based_vm_exec_control, |
b9c237bb WV |
10801 | vmx->nested.nested_vmx_pinbased_ctls_low, |
10802 | vmx->nested.nested_vmx_pinbased_ctls_high) || | |
7c177938 | 10803 | !vmx_control_verify(vmcs12->vm_exit_controls, |
0115f9cb | 10804 | vmx->nested.nested_vmx_exit_ctls_low, |
b9c237bb | 10805 | vmx->nested.nested_vmx_exit_ctls_high) || |
7c177938 | 10806 | !vmx_control_verify(vmcs12->vm_entry_controls, |
0115f9cb | 10807 | vmx->nested.nested_vmx_entry_ctls_low, |
b9c237bb | 10808 | vmx->nested.nested_vmx_entry_ctls_high)) |
ca0bde28 | 10809 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; |
7c177938 | 10810 | |
41ab9372 BD |
10811 | if (nested_cpu_has_vmfunc(vmcs12)) { |
10812 | if (vmcs12->vm_function_control & | |
10813 | ~vmx->nested.nested_vmx_vmfunc_controls) | |
10814 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
10815 | ||
10816 | if (nested_cpu_has_eptp_switching(vmcs12)) { | |
10817 | if (!nested_cpu_has_ept(vmcs12) || | |
10818 | !page_address_valid(vcpu, vmcs12->eptp_list_address)) | |
10819 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
10820 | } | |
10821 | } | |
27c42a1b | 10822 | |
c7c2c709 JM |
10823 | if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu)) |
10824 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
10825 | ||
3899152c | 10826 | if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) || |
1dc35dac | 10827 | !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) || |
ca0bde28 JM |
10828 | !nested_cr3_valid(vcpu, vmcs12->host_cr3)) |
10829 | return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; | |
10830 | ||
10831 | return 0; | |
10832 | } | |
10833 | ||
10834 | static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, | |
10835 | u32 *exit_qual) | |
10836 | { | |
10837 | bool ia32e; | |
10838 | ||
10839 | *exit_qual = ENTRY_FAIL_DEFAULT; | |
7c177938 | 10840 | |
3899152c | 10841 | if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) || |
ca0bde28 | 10842 | !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4)) |
b428018a | 10843 | return 1; |
ca0bde28 JM |
10844 | |
10845 | if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) && | |
10846 | vmcs12->vmcs_link_pointer != -1ull) { | |
10847 | *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR; | |
b428018a | 10848 | return 1; |
7c177938 NHE |
10849 | } |
10850 | ||
384bb783 | 10851 | /* |
cb0c8cda | 10852 | * If the load IA32_EFER VM-entry control is 1, the following checks |
384bb783 JK |
10853 | * are performed on the field for the IA32_EFER MSR: |
10854 | * - Bits reserved in the IA32_EFER MSR must be 0. | |
10855 | * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of | |
10856 | * the IA-32e mode guest VM-exit control. It must also be identical | |
10857 | * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to | |
10858 | * CR0.PG) is 1. | |
10859 | */ | |
ca0bde28 JM |
10860 | if (to_vmx(vcpu)->nested.nested_run_pending && |
10861 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) { | |
384bb783 JK |
10862 | ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0; |
10863 | if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) || | |
10864 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) || | |
10865 | ((vmcs12->guest_cr0 & X86_CR0_PG) && | |
ca0bde28 | 10866 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) |
b428018a | 10867 | return 1; |
384bb783 JK |
10868 | } |
10869 | ||
10870 | /* | |
10871 | * If the load IA32_EFER VM-exit control is 1, bits reserved in the | |
10872 | * IA32_EFER MSR must be 0 in the field for that register. In addition, | |
10873 | * the values of the LMA and LME bits in the field must each be that of | |
10874 | * the host address-space size VM-exit control. | |
10875 | */ | |
10876 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) { | |
10877 | ia32e = (vmcs12->vm_exit_controls & | |
10878 | VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0; | |
10879 | if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) || | |
10880 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) || | |
ca0bde28 | 10881 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) |
b428018a | 10882 | return 1; |
ca0bde28 JM |
10883 | } |
10884 | ||
f1b026a3 WL |
10885 | if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) && |
10886 | (is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu) || | |
10887 | (vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD))) | |
10888 | return 1; | |
10889 | ||
ca0bde28 JM |
10890 | return 0; |
10891 | } | |
10892 | ||
858e25c0 JM |
10893 | static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry) |
10894 | { | |
10895 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10896 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
10897 | struct loaded_vmcs *vmcs02; | |
858e25c0 JM |
10898 | u32 msr_entry_idx; |
10899 | u32 exit_qual; | |
10900 | ||
10901 | vmcs02 = nested_get_current_vmcs02(vmx); | |
10902 | if (!vmcs02) | |
10903 | return -ENOMEM; | |
10904 | ||
10905 | enter_guest_mode(vcpu); | |
10906 | ||
10907 | if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) | |
10908 | vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
10909 | ||
1279a6b1 | 10910 | vmx_switch_vmcs(vcpu, vmcs02); |
858e25c0 JM |
10911 | vmx_segment_cache_clear(vmx); |
10912 | ||
10913 | if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) { | |
10914 | leave_guest_mode(vcpu); | |
1279a6b1 | 10915 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); |
858e25c0 JM |
10916 | nested_vmx_entry_failure(vcpu, vmcs12, |
10917 | EXIT_REASON_INVALID_STATE, exit_qual); | |
10918 | return 1; | |
10919 | } | |
10920 | ||
10921 | nested_get_vmcs12_pages(vcpu, vmcs12); | |
10922 | ||
10923 | msr_entry_idx = nested_vmx_load_msr(vcpu, | |
10924 | vmcs12->vm_entry_msr_load_addr, | |
10925 | vmcs12->vm_entry_msr_load_count); | |
10926 | if (msr_entry_idx) { | |
10927 | leave_guest_mode(vcpu); | |
1279a6b1 | 10928 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); |
858e25c0 JM |
10929 | nested_vmx_entry_failure(vcpu, vmcs12, |
10930 | EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx); | |
10931 | return 1; | |
10932 | } | |
10933 | ||
858e25c0 JM |
10934 | /* |
10935 | * Note no nested_vmx_succeed or nested_vmx_fail here. At this point | |
10936 | * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet | |
10937 | * returned as far as L1 is concerned. It will only return (and set | |
10938 | * the success flag) when L2 exits (see nested_vmx_vmexit()). | |
10939 | */ | |
10940 | return 0; | |
10941 | } | |
10942 | ||
ca0bde28 JM |
10943 | /* |
10944 | * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1 | |
10945 | * for running an L2 nested guest. | |
10946 | */ | |
10947 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch) | |
10948 | { | |
10949 | struct vmcs12 *vmcs12; | |
10950 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
b3f1dfb6 | 10951 | u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu); |
ca0bde28 JM |
10952 | u32 exit_qual; |
10953 | int ret; | |
10954 | ||
10955 | if (!nested_vmx_check_permission(vcpu)) | |
10956 | return 1; | |
10957 | ||
10958 | if (!nested_vmx_check_vmcs12(vcpu)) | |
10959 | goto out; | |
10960 | ||
10961 | vmcs12 = get_vmcs12(vcpu); | |
10962 | ||
10963 | if (enable_shadow_vmcs) | |
10964 | copy_shadow_to_vmcs12(vmx); | |
10965 | ||
10966 | /* | |
10967 | * The nested entry process starts with enforcing various prerequisites | |
10968 | * on vmcs12 as required by the Intel SDM, and act appropriately when | |
10969 | * they fail: As the SDM explains, some conditions should cause the | |
10970 | * instruction to fail, while others will cause the instruction to seem | |
10971 | * to succeed, but return an EXIT_REASON_INVALID_STATE. | |
10972 | * To speed up the normal (success) code path, we should avoid checking | |
10973 | * for misconfigurations which will anyway be caught by the processor | |
10974 | * when using the merged vmcs02. | |
10975 | */ | |
b3f1dfb6 JM |
10976 | if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) { |
10977 | nested_vmx_failValid(vcpu, | |
10978 | VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS); | |
10979 | goto out; | |
10980 | } | |
10981 | ||
ca0bde28 JM |
10982 | if (vmcs12->launch_state == launch) { |
10983 | nested_vmx_failValid(vcpu, | |
10984 | launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS | |
10985 | : VMXERR_VMRESUME_NONLAUNCHED_VMCS); | |
10986 | goto out; | |
10987 | } | |
10988 | ||
10989 | ret = check_vmentry_prereqs(vcpu, vmcs12); | |
10990 | if (ret) { | |
10991 | nested_vmx_failValid(vcpu, ret); | |
10992 | goto out; | |
10993 | } | |
10994 | ||
10995 | /* | |
10996 | * After this point, the trap flag no longer triggers a singlestep trap | |
10997 | * on the vm entry instructions; don't call kvm_skip_emulated_instruction. | |
10998 | * This is not 100% correct; for performance reasons, we delegate most | |
10999 | * of the checks on host state to the processor. If those fail, | |
11000 | * the singlestep trap is missed. | |
11001 | */ | |
11002 | skip_emulated_instruction(vcpu); | |
11003 | ||
11004 | ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual); | |
11005 | if (ret) { | |
11006 | nested_vmx_entry_failure(vcpu, vmcs12, | |
11007 | EXIT_REASON_INVALID_STATE, exit_qual); | |
11008 | return 1; | |
384bb783 JK |
11009 | } |
11010 | ||
7c177938 NHE |
11011 | /* |
11012 | * We're finally done with prerequisite checking, and can start with | |
11013 | * the nested entry. | |
11014 | */ | |
11015 | ||
858e25c0 JM |
11016 | ret = enter_vmx_non_root_mode(vcpu, true); |
11017 | if (ret) | |
11018 | return ret; | |
ff651cb6 | 11019 | |
6dfacadd | 11020 | if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) |
5cb56059 | 11021 | return kvm_vcpu_halt(vcpu); |
6dfacadd | 11022 | |
7af40ad3 JK |
11023 | vmx->nested.nested_run_pending = 1; |
11024 | ||
cd232ad0 | 11025 | return 1; |
eb277562 KH |
11026 | |
11027 | out: | |
6affcbed | 11028 | return kvm_skip_emulated_instruction(vcpu); |
cd232ad0 NHE |
11029 | } |
11030 | ||
4704d0be NHE |
11031 | /* |
11032 | * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date | |
11033 | * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK). | |
11034 | * This function returns the new value we should put in vmcs12.guest_cr0. | |
11035 | * It's not enough to just return the vmcs02 GUEST_CR0. Rather, | |
11036 | * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now | |
11037 | * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0 | |
11038 | * didn't trap the bit, because if L1 did, so would L0). | |
11039 | * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have | |
11040 | * been modified by L2, and L1 knows it. So just leave the old value of | |
11041 | * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0 | |
11042 | * isn't relevant, because if L0 traps this bit it can set it to anything. | |
11043 | * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have | |
11044 | * changed these bits, and therefore they need to be updated, but L0 | |
11045 | * didn't necessarily allow them to be changed in GUEST_CR0 - and rather | |
11046 | * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there. | |
11047 | */ | |
11048 | static inline unsigned long | |
11049 | vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
11050 | { | |
11051 | return | |
11052 | /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) | | |
11053 | /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) | | |
11054 | /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask | | |
11055 | vcpu->arch.cr0_guest_owned_bits)); | |
11056 | } | |
11057 | ||
11058 | static inline unsigned long | |
11059 | vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
11060 | { | |
11061 | return | |
11062 | /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) | | |
11063 | /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) | | |
11064 | /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask | | |
11065 | vcpu->arch.cr4_guest_owned_bits)); | |
11066 | } | |
11067 | ||
5f3d5799 JK |
11068 | static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu, |
11069 | struct vmcs12 *vmcs12) | |
11070 | { | |
11071 | u32 idt_vectoring; | |
11072 | unsigned int nr; | |
11073 | ||
664f8e26 | 11074 | if (vcpu->arch.exception.injected) { |
5f3d5799 JK |
11075 | nr = vcpu->arch.exception.nr; |
11076 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
11077 | ||
11078 | if (kvm_exception_is_soft(nr)) { | |
11079 | vmcs12->vm_exit_instruction_len = | |
11080 | vcpu->arch.event_exit_inst_len; | |
11081 | idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION; | |
11082 | } else | |
11083 | idt_vectoring |= INTR_TYPE_HARD_EXCEPTION; | |
11084 | ||
11085 | if (vcpu->arch.exception.has_error_code) { | |
11086 | idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK; | |
11087 | vmcs12->idt_vectoring_error_code = | |
11088 | vcpu->arch.exception.error_code; | |
11089 | } | |
11090 | ||
11091 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
cd2633c5 | 11092 | } else if (vcpu->arch.nmi_injected) { |
5f3d5799 JK |
11093 | vmcs12->idt_vectoring_info_field = |
11094 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR; | |
11095 | } else if (vcpu->arch.interrupt.pending) { | |
11096 | nr = vcpu->arch.interrupt.nr; | |
11097 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
11098 | ||
11099 | if (vcpu->arch.interrupt.soft) { | |
11100 | idt_vectoring |= INTR_TYPE_SOFT_INTR; | |
11101 | vmcs12->vm_entry_instruction_len = | |
11102 | vcpu->arch.event_exit_inst_len; | |
11103 | } else | |
11104 | idt_vectoring |= INTR_TYPE_EXT_INTR; | |
11105 | ||
11106 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
11107 | } | |
11108 | } | |
11109 | ||
b6b8a145 JK |
11110 | static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr) |
11111 | { | |
11112 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
bfcf83b1 | 11113 | unsigned long exit_qual; |
917dc606 LA |
11114 | bool block_nested_events = |
11115 | vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu); | |
acc9ab60 | 11116 | |
bfcf83b1 WL |
11117 | if (vcpu->arch.exception.pending && |
11118 | nested_vmx_check_exception(vcpu, &exit_qual)) { | |
917dc606 | 11119 | if (block_nested_events) |
bfcf83b1 WL |
11120 | return -EBUSY; |
11121 | nested_vmx_inject_exception_vmexit(vcpu, exit_qual); | |
11122 | vcpu->arch.exception.pending = false; | |
11123 | return 0; | |
11124 | } | |
11125 | ||
f4124500 JK |
11126 | if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) && |
11127 | vmx->nested.preemption_timer_expired) { | |
917dc606 | 11128 | if (block_nested_events) |
f4124500 JK |
11129 | return -EBUSY; |
11130 | nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0); | |
11131 | return 0; | |
11132 | } | |
11133 | ||
b6b8a145 | 11134 | if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) { |
917dc606 | 11135 | if (block_nested_events) |
b6b8a145 JK |
11136 | return -EBUSY; |
11137 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, | |
11138 | NMI_VECTOR | INTR_TYPE_NMI_INTR | | |
11139 | INTR_INFO_VALID_MASK, 0); | |
11140 | /* | |
11141 | * The NMI-triggered VM exit counts as injection: | |
11142 | * clear this one and block further NMIs. | |
11143 | */ | |
11144 | vcpu->arch.nmi_pending = 0; | |
11145 | vmx_set_nmi_mask(vcpu, true); | |
11146 | return 0; | |
11147 | } | |
11148 | ||
11149 | if ((kvm_cpu_has_interrupt(vcpu) || external_intr) && | |
11150 | nested_exit_on_intr(vcpu)) { | |
917dc606 | 11151 | if (block_nested_events) |
b6b8a145 JK |
11152 | return -EBUSY; |
11153 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0); | |
705699a1 | 11154 | return 0; |
b6b8a145 JK |
11155 | } |
11156 | ||
6342c50a DH |
11157 | vmx_complete_nested_posted_interrupt(vcpu); |
11158 | return 0; | |
b6b8a145 JK |
11159 | } |
11160 | ||
f4124500 JK |
11161 | static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu) |
11162 | { | |
11163 | ktime_t remaining = | |
11164 | hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer); | |
11165 | u64 value; | |
11166 | ||
11167 | if (ktime_to_ns(remaining) <= 0) | |
11168 | return 0; | |
11169 | ||
11170 | value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz; | |
11171 | do_div(value, 1000000); | |
11172 | return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
11173 | } | |
11174 | ||
4704d0be | 11175 | /* |
cf8b84f4 JM |
11176 | * Update the guest state fields of vmcs12 to reflect changes that |
11177 | * occurred while L2 was running. (The "IA-32e mode guest" bit of the | |
11178 | * VM-entry controls is also updated, since this is really a guest | |
11179 | * state bit.) | |
4704d0be | 11180 | */ |
cf8b84f4 | 11181 | static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) |
4704d0be | 11182 | { |
4704d0be NHE |
11183 | vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12); |
11184 | vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12); | |
11185 | ||
4704d0be NHE |
11186 | vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); |
11187 | vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP); | |
11188 | vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS); | |
11189 | ||
11190 | vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR); | |
11191 | vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR); | |
11192 | vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR); | |
11193 | vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR); | |
11194 | vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR); | |
11195 | vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR); | |
11196 | vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR); | |
11197 | vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR); | |
11198 | vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT); | |
11199 | vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT); | |
11200 | vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT); | |
11201 | vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT); | |
11202 | vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT); | |
11203 | vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT); | |
11204 | vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT); | |
11205 | vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT); | |
11206 | vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
11207 | vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
11208 | vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES); | |
11209 | vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES); | |
11210 | vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES); | |
11211 | vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES); | |
11212 | vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES); | |
11213 | vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES); | |
11214 | vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES); | |
11215 | vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES); | |
11216 | vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE); | |
11217 | vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE); | |
11218 | vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE); | |
11219 | vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE); | |
11220 | vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE); | |
11221 | vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE); | |
11222 | vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE); | |
11223 | vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE); | |
11224 | vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE); | |
11225 | vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE); | |
11226 | ||
4704d0be NHE |
11227 | vmcs12->guest_interruptibility_info = |
11228 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
11229 | vmcs12->guest_pending_dbg_exceptions = | |
11230 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS); | |
3edf1e69 JK |
11231 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) |
11232 | vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT; | |
11233 | else | |
11234 | vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE; | |
4704d0be | 11235 | |
f4124500 JK |
11236 | if (nested_cpu_has_preemption_timer(vmcs12)) { |
11237 | if (vmcs12->vm_exit_controls & | |
11238 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER) | |
11239 | vmcs12->vmx_preemption_timer_value = | |
11240 | vmx_get_preemption_timer_value(vcpu); | |
11241 | hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer); | |
11242 | } | |
7854cbca | 11243 | |
3633cfc3 NHE |
11244 | /* |
11245 | * In some cases (usually, nested EPT), L2 is allowed to change its | |
11246 | * own CR3 without exiting. If it has changed it, we must keep it. | |
11247 | * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined | |
11248 | * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12. | |
11249 | * | |
11250 | * Additionally, restore L2's PDPTR to vmcs12. | |
11251 | */ | |
11252 | if (enable_ept) { | |
f3531054 | 11253 | vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3); |
3633cfc3 NHE |
11254 | vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0); |
11255 | vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1); | |
11256 | vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2); | |
11257 | vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3); | |
11258 | } | |
11259 | ||
d281e13b | 11260 | vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS); |
119a9c01 | 11261 | |
608406e2 WV |
11262 | if (nested_cpu_has_vid(vmcs12)) |
11263 | vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS); | |
11264 | ||
c18911a2 JK |
11265 | vmcs12->vm_entry_controls = |
11266 | (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) | | |
2961e876 | 11267 | (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE); |
c18911a2 | 11268 | |
2996fca0 JK |
11269 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) { |
11270 | kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7); | |
11271 | vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
11272 | } | |
11273 | ||
4704d0be NHE |
11274 | /* TODO: These cannot have changed unless we have MSR bitmaps and |
11275 | * the relevant bit asks not to trap the change */ | |
b8c07d55 | 11276 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) |
4704d0be | 11277 | vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT); |
10ba54a5 JK |
11278 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER) |
11279 | vmcs12->guest_ia32_efer = vcpu->arch.efer; | |
4704d0be NHE |
11280 | vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS); |
11281 | vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP); | |
11282 | vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP); | |
a87036ad | 11283 | if (kvm_mpx_supported()) |
36be0b9d | 11284 | vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS); |
cf8b84f4 JM |
11285 | } |
11286 | ||
11287 | /* | |
11288 | * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits | |
11289 | * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12), | |
11290 | * and this function updates it to reflect the changes to the guest state while | |
11291 | * L2 was running (and perhaps made some exits which were handled directly by L0 | |
11292 | * without going back to L1), and to reflect the exit reason. | |
11293 | * Note that we do not have to copy here all VMCS fields, just those that | |
11294 | * could have changed by the L2 guest or the exit - i.e., the guest-state and | |
11295 | * exit-information fields only. Other fields are modified by L1 with VMWRITE, | |
11296 | * which already writes to vmcs12 directly. | |
11297 | */ | |
11298 | static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, | |
11299 | u32 exit_reason, u32 exit_intr_info, | |
11300 | unsigned long exit_qualification) | |
11301 | { | |
11302 | /* update guest state fields: */ | |
11303 | sync_vmcs12(vcpu, vmcs12); | |
4704d0be NHE |
11304 | |
11305 | /* update exit information fields: */ | |
11306 | ||
533558bc JK |
11307 | vmcs12->vm_exit_reason = exit_reason; |
11308 | vmcs12->exit_qualification = exit_qualification; | |
533558bc | 11309 | vmcs12->vm_exit_intr_info = exit_intr_info; |
7313c698 | 11310 | |
5f3d5799 | 11311 | vmcs12->idt_vectoring_info_field = 0; |
4704d0be NHE |
11312 | vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
11313 | vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
11314 | ||
5f3d5799 | 11315 | if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) { |
7cdc2d62 JM |
11316 | vmcs12->launch_state = 1; |
11317 | ||
5f3d5799 JK |
11318 | /* vm_entry_intr_info_field is cleared on exit. Emulate this |
11319 | * instead of reading the real value. */ | |
4704d0be | 11320 | vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK; |
5f3d5799 JK |
11321 | |
11322 | /* | |
11323 | * Transfer the event that L0 or L1 may wanted to inject into | |
11324 | * L2 to IDT_VECTORING_INFO_FIELD. | |
11325 | */ | |
11326 | vmcs12_save_pending_event(vcpu, vmcs12); | |
11327 | } | |
11328 | ||
11329 | /* | |
11330 | * Drop what we picked up for L2 via vmx_complete_interrupts. It is | |
11331 | * preserved above and would only end up incorrectly in L1. | |
11332 | */ | |
11333 | vcpu->arch.nmi_injected = false; | |
11334 | kvm_clear_exception_queue(vcpu); | |
11335 | kvm_clear_interrupt_queue(vcpu); | |
4704d0be NHE |
11336 | } |
11337 | ||
5af41573 WL |
11338 | static void load_vmcs12_mmu_host_state(struct kvm_vcpu *vcpu, |
11339 | struct vmcs12 *vmcs12) | |
11340 | { | |
11341 | u32 entry_failure_code; | |
11342 | ||
11343 | nested_ept_uninit_mmu_context(vcpu); | |
11344 | ||
11345 | /* | |
11346 | * Only PDPTE load can fail as the value of cr3 was checked on entry and | |
11347 | * couldn't have changed. | |
11348 | */ | |
11349 | if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code)) | |
11350 | nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL); | |
11351 | ||
11352 | if (!enable_ept) | |
11353 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; | |
11354 | } | |
11355 | ||
4704d0be NHE |
11356 | /* |
11357 | * A part of what we need to when the nested L2 guest exits and we want to | |
11358 | * run its L1 parent, is to reset L1's guest state to the host state specified | |
11359 | * in vmcs12. | |
11360 | * This function is to be called not only on normal nested exit, but also on | |
11361 | * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry | |
11362 | * Failures During or After Loading Guest State"). | |
11363 | * This function should be called when the active VMCS is L1's (vmcs01). | |
11364 | */ | |
733568f9 JK |
11365 | static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, |
11366 | struct vmcs12 *vmcs12) | |
4704d0be | 11367 | { |
21feb4eb ACL |
11368 | struct kvm_segment seg; |
11369 | ||
4704d0be NHE |
11370 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) |
11371 | vcpu->arch.efer = vmcs12->host_ia32_efer; | |
d1fa0352 | 11372 | else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) |
4704d0be NHE |
11373 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); |
11374 | else | |
11375 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
11376 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
11377 | ||
11378 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp); | |
11379 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip); | |
1adfa76a | 11380 | vmx_set_rflags(vcpu, X86_EFLAGS_FIXED); |
4704d0be NHE |
11381 | /* |
11382 | * Note that calling vmx_set_cr0 is important, even if cr0 hasn't | |
bd7e5b08 PB |
11383 | * actually changed, because vmx_set_cr0 refers to efer set above. |
11384 | * | |
11385 | * CR0_GUEST_HOST_MASK is already set in the original vmcs01 | |
11386 | * (KVM doesn't change it); | |
4704d0be | 11387 | */ |
bd7e5b08 | 11388 | vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS; |
9e3e4dbf | 11389 | vmx_set_cr0(vcpu, vmcs12->host_cr0); |
4704d0be | 11390 | |
bd7e5b08 | 11391 | /* Same as above - no reason to call set_cr4_guest_host_mask(). */ |
4704d0be | 11392 | vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK); |
8eb3f87d | 11393 | vmx_set_cr4(vcpu, vmcs12->host_cr4); |
4704d0be | 11394 | |
5af41573 | 11395 | load_vmcs12_mmu_host_state(vcpu, vmcs12); |
feaf0c7d | 11396 | |
4704d0be NHE |
11397 | if (enable_vpid) { |
11398 | /* | |
11399 | * Trivially support vpid by letting L2s share their parent | |
11400 | * L1's vpid. TODO: move to a more elaborate solution, giving | |
11401 | * each L2 its own vpid and exposing the vpid feature to L1. | |
11402 | */ | |
11403 | vmx_flush_tlb(vcpu); | |
11404 | } | |
06a5524f WV |
11405 | /* Restore posted intr vector. */ |
11406 | if (nested_cpu_has_posted_intr(vmcs12)) | |
11407 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); | |
4704d0be NHE |
11408 | |
11409 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs); | |
11410 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp); | |
11411 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip); | |
11412 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base); | |
11413 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base); | |
21f2d551 LP |
11414 | vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF); |
11415 | vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF); | |
4704d0be | 11416 | |
36be0b9d PB |
11417 | /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */ |
11418 | if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS) | |
11419 | vmcs_write64(GUEST_BNDCFGS, 0); | |
11420 | ||
44811c02 | 11421 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) { |
4704d0be | 11422 | vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat); |
44811c02 JK |
11423 | vcpu->arch.pat = vmcs12->host_ia32_pat; |
11424 | } | |
4704d0be NHE |
11425 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) |
11426 | vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL, | |
11427 | vmcs12->host_ia32_perf_global_ctrl); | |
503cd0c5 | 11428 | |
21feb4eb ACL |
11429 | /* Set L1 segment info according to Intel SDM |
11430 | 27.5.2 Loading Host Segment and Descriptor-Table Registers */ | |
11431 | seg = (struct kvm_segment) { | |
11432 | .base = 0, | |
11433 | .limit = 0xFFFFFFFF, | |
11434 | .selector = vmcs12->host_cs_selector, | |
11435 | .type = 11, | |
11436 | .present = 1, | |
11437 | .s = 1, | |
11438 | .g = 1 | |
11439 | }; | |
11440 | if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) | |
11441 | seg.l = 1; | |
11442 | else | |
11443 | seg.db = 1; | |
11444 | vmx_set_segment(vcpu, &seg, VCPU_SREG_CS); | |
11445 | seg = (struct kvm_segment) { | |
11446 | .base = 0, | |
11447 | .limit = 0xFFFFFFFF, | |
11448 | .type = 3, | |
11449 | .present = 1, | |
11450 | .s = 1, | |
11451 | .db = 1, | |
11452 | .g = 1 | |
11453 | }; | |
11454 | seg.selector = vmcs12->host_ds_selector; | |
11455 | vmx_set_segment(vcpu, &seg, VCPU_SREG_DS); | |
11456 | seg.selector = vmcs12->host_es_selector; | |
11457 | vmx_set_segment(vcpu, &seg, VCPU_SREG_ES); | |
11458 | seg.selector = vmcs12->host_ss_selector; | |
11459 | vmx_set_segment(vcpu, &seg, VCPU_SREG_SS); | |
11460 | seg.selector = vmcs12->host_fs_selector; | |
11461 | seg.base = vmcs12->host_fs_base; | |
11462 | vmx_set_segment(vcpu, &seg, VCPU_SREG_FS); | |
11463 | seg.selector = vmcs12->host_gs_selector; | |
11464 | seg.base = vmcs12->host_gs_base; | |
11465 | vmx_set_segment(vcpu, &seg, VCPU_SREG_GS); | |
11466 | seg = (struct kvm_segment) { | |
205befd9 | 11467 | .base = vmcs12->host_tr_base, |
21feb4eb ACL |
11468 | .limit = 0x67, |
11469 | .selector = vmcs12->host_tr_selector, | |
11470 | .type = 11, | |
11471 | .present = 1 | |
11472 | }; | |
11473 | vmx_set_segment(vcpu, &seg, VCPU_SREG_TR); | |
11474 | ||
503cd0c5 JK |
11475 | kvm_set_dr(vcpu, 7, 0x400); |
11476 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
ff651cb6 | 11477 | |
3af18d9c WV |
11478 | if (cpu_has_vmx_msr_bitmap()) |
11479 | vmx_set_msr_bitmap(vcpu); | |
11480 | ||
ff651cb6 WV |
11481 | if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr, |
11482 | vmcs12->vm_exit_msr_load_count)) | |
11483 | nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL); | |
4704d0be NHE |
11484 | } |
11485 | ||
11486 | /* | |
11487 | * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1 | |
11488 | * and modify vmcs12 to make it see what it would expect to see there if | |
11489 | * L2 was its real guest. Must only be called when in L2 (is_guest_mode()) | |
11490 | */ | |
533558bc JK |
11491 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
11492 | u32 exit_intr_info, | |
11493 | unsigned long exit_qualification) | |
4704d0be NHE |
11494 | { |
11495 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4704d0be NHE |
11496 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
11497 | ||
5f3d5799 JK |
11498 | /* trying to cancel vmlaunch/vmresume is a bug */ |
11499 | WARN_ON_ONCE(vmx->nested.nested_run_pending); | |
11500 | ||
4f350c6d JM |
11501 | /* |
11502 | * The only expected VM-instruction error is "VM entry with | |
11503 | * invalid control field(s)." Anything else indicates a | |
11504 | * problem with L0. | |
11505 | */ | |
11506 | WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) != | |
11507 | VMXERR_ENTRY_INVALID_CONTROL_FIELD)); | |
11508 | ||
4704d0be | 11509 | leave_guest_mode(vcpu); |
4704d0be | 11510 | |
4f350c6d | 11511 | if (likely(!vmx->fail)) { |
72e9cbdb LP |
11512 | if (exit_reason == -1) |
11513 | sync_vmcs12(vcpu, vmcs12); | |
11514 | else | |
11515 | prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info, | |
11516 | exit_qualification); | |
ff651cb6 | 11517 | |
4f350c6d JM |
11518 | if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr, |
11519 | vmcs12->vm_exit_msr_store_count)) | |
11520 | nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL); | |
11521 | } | |
cf3215d9 | 11522 | |
1279a6b1 | 11523 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); |
8391ce44 PB |
11524 | vm_entry_controls_reset_shadow(vmx); |
11525 | vm_exit_controls_reset_shadow(vmx); | |
36c3cc42 JK |
11526 | vmx_segment_cache_clear(vmx); |
11527 | ||
4704d0be NHE |
11528 | /* if no vmcs02 cache requested, remove the one we used */ |
11529 | if (VMCS02_POOL_SIZE == 0) | |
11530 | nested_free_vmcs02(vmx, vmx->nested.current_vmptr); | |
11531 | ||
9314006d | 11532 | /* Update any VMCS fields that might have changed while L2 ran */ |
83bafef1 JM |
11533 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr); |
11534 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr); | |
ea26e4ec | 11535 | vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); |
9314006d PB |
11536 | if (vmx->hv_deadline_tsc == -1) |
11537 | vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL, | |
11538 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
11539 | else | |
11540 | vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL, | |
11541 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
c95ba92a PF |
11542 | if (kvm_has_tsc_control) |
11543 | decache_tsc_multiplier(vmx); | |
4704d0be | 11544 | |
dccbfcf5 RK |
11545 | if (vmx->nested.change_vmcs01_virtual_x2apic_mode) { |
11546 | vmx->nested.change_vmcs01_virtual_x2apic_mode = false; | |
11547 | vmx_set_virtual_x2apic_mode(vcpu, | |
11548 | vcpu->arch.apic_base & X2APIC_ENABLE); | |
fb6c8198 JM |
11549 | } else if (!nested_cpu_has_ept(vmcs12) && |
11550 | nested_cpu_has2(vmcs12, | |
11551 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
11552 | vmx_flush_tlb_ept_only(vcpu); | |
dccbfcf5 | 11553 | } |
4704d0be NHE |
11554 | |
11555 | /* This is needed for same reason as it was needed in prepare_vmcs02 */ | |
11556 | vmx->host_rsp = 0; | |
11557 | ||
11558 | /* Unpin physical memory we referred to in vmcs02 */ | |
11559 | if (vmx->nested.apic_access_page) { | |
53a70daf | 11560 | kvm_release_page_dirty(vmx->nested.apic_access_page); |
48d89b92 | 11561 | vmx->nested.apic_access_page = NULL; |
4704d0be | 11562 | } |
a7c0b07d | 11563 | if (vmx->nested.virtual_apic_page) { |
53a70daf | 11564 | kvm_release_page_dirty(vmx->nested.virtual_apic_page); |
48d89b92 | 11565 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 11566 | } |
705699a1 WV |
11567 | if (vmx->nested.pi_desc_page) { |
11568 | kunmap(vmx->nested.pi_desc_page); | |
53a70daf | 11569 | kvm_release_page_dirty(vmx->nested.pi_desc_page); |
705699a1 WV |
11570 | vmx->nested.pi_desc_page = NULL; |
11571 | vmx->nested.pi_desc = NULL; | |
11572 | } | |
4704d0be | 11573 | |
38b99173 TC |
11574 | /* |
11575 | * We are now running in L2, mmu_notifier will force to reload the | |
11576 | * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1. | |
11577 | */ | |
c83b6d15 | 11578 | kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); |
38b99173 | 11579 | |
72e9cbdb | 11580 | if (enable_shadow_vmcs && exit_reason != -1) |
012f83cb | 11581 | vmx->nested.sync_shadow_vmcs = true; |
b6b8a145 JK |
11582 | |
11583 | /* in case we halted in L2 */ | |
11584 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
4f350c6d JM |
11585 | |
11586 | if (likely(!vmx->fail)) { | |
11587 | /* | |
11588 | * TODO: SDM says that with acknowledge interrupt on | |
11589 | * exit, bit 31 of the VM-exit interrupt information | |
11590 | * (valid interrupt) is always set to 1 on | |
11591 | * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't | |
11592 | * need kvm_cpu_has_interrupt(). See the commit | |
11593 | * message for details. | |
11594 | */ | |
11595 | if (nested_exit_intr_ack_set(vcpu) && | |
11596 | exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT && | |
11597 | kvm_cpu_has_interrupt(vcpu)) { | |
11598 | int irq = kvm_cpu_get_interrupt(vcpu); | |
11599 | WARN_ON(irq < 0); | |
11600 | vmcs12->vm_exit_intr_info = irq | | |
11601 | INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR; | |
11602 | } | |
11603 | ||
72e9cbdb LP |
11604 | if (exit_reason != -1) |
11605 | trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason, | |
11606 | vmcs12->exit_qualification, | |
11607 | vmcs12->idt_vectoring_info_field, | |
11608 | vmcs12->vm_exit_intr_info, | |
11609 | vmcs12->vm_exit_intr_error_code, | |
11610 | KVM_ISA_VMX); | |
4f350c6d JM |
11611 | |
11612 | load_vmcs12_host_state(vcpu, vmcs12); | |
11613 | ||
11614 | return; | |
11615 | } | |
11616 | ||
11617 | /* | |
11618 | * After an early L2 VM-entry failure, we're now back | |
11619 | * in L1 which thinks it just finished a VMLAUNCH or | |
11620 | * VMRESUME instruction, so we need to set the failure | |
11621 | * flag and the VM-instruction error field of the VMCS | |
11622 | * accordingly. | |
11623 | */ | |
11624 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
5af41573 WL |
11625 | |
11626 | load_vmcs12_mmu_host_state(vcpu, vmcs12); | |
11627 | ||
4f350c6d JM |
11628 | /* |
11629 | * The emulated instruction was already skipped in | |
11630 | * nested_vmx_run, but the updated RIP was never | |
11631 | * written back to the vmcs01. | |
11632 | */ | |
11633 | skip_emulated_instruction(vcpu); | |
11634 | vmx->fail = 0; | |
4704d0be NHE |
11635 | } |
11636 | ||
42124925 JK |
11637 | /* |
11638 | * Forcibly leave nested mode in order to be able to reset the VCPU later on. | |
11639 | */ | |
11640 | static void vmx_leave_nested(struct kvm_vcpu *vcpu) | |
11641 | { | |
2f707d97 WL |
11642 | if (is_guest_mode(vcpu)) { |
11643 | to_vmx(vcpu)->nested.nested_run_pending = 0; | |
533558bc | 11644 | nested_vmx_vmexit(vcpu, -1, 0, 0); |
2f707d97 | 11645 | } |
42124925 JK |
11646 | free_nested(to_vmx(vcpu)); |
11647 | } | |
11648 | ||
7c177938 NHE |
11649 | /* |
11650 | * L1's failure to enter L2 is a subset of a normal exit, as explained in | |
11651 | * 23.7 "VM-entry failures during or after loading guest state" (this also | |
11652 | * lists the acceptable exit-reason and exit-qualification parameters). | |
11653 | * It should only be called before L2 actually succeeded to run, and when | |
11654 | * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss). | |
11655 | */ | |
11656 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, | |
11657 | struct vmcs12 *vmcs12, | |
11658 | u32 reason, unsigned long qualification) | |
11659 | { | |
11660 | load_vmcs12_host_state(vcpu, vmcs12); | |
11661 | vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY; | |
11662 | vmcs12->exit_qualification = qualification; | |
11663 | nested_vmx_succeed(vcpu); | |
012f83cb AG |
11664 | if (enable_shadow_vmcs) |
11665 | to_vmx(vcpu)->nested.sync_shadow_vmcs = true; | |
7c177938 NHE |
11666 | } |
11667 | ||
8a76d7f2 JR |
11668 | static int vmx_check_intercept(struct kvm_vcpu *vcpu, |
11669 | struct x86_instruction_info *info, | |
11670 | enum x86_intercept_stage stage) | |
11671 | { | |
11672 | return X86EMUL_CONTINUE; | |
11673 | } | |
11674 | ||
64672c95 YJ |
11675 | #ifdef CONFIG_X86_64 |
11676 | /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ | |
11677 | static inline int u64_shl_div_u64(u64 a, unsigned int shift, | |
11678 | u64 divisor, u64 *result) | |
11679 | { | |
11680 | u64 low = a << shift, high = a >> (64 - shift); | |
11681 | ||
11682 | /* To avoid the overflow on divq */ | |
11683 | if (high >= divisor) | |
11684 | return 1; | |
11685 | ||
11686 | /* Low hold the result, high hold rem which is discarded */ | |
11687 | asm("divq %2\n\t" : "=a" (low), "=d" (high) : | |
11688 | "rm" (divisor), "0" (low), "1" (high)); | |
11689 | *result = low; | |
11690 | ||
11691 | return 0; | |
11692 | } | |
11693 | ||
11694 | static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc) | |
11695 | { | |
11696 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9175d2e9 PB |
11697 | u64 tscl = rdtsc(); |
11698 | u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl); | |
11699 | u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; | |
64672c95 YJ |
11700 | |
11701 | /* Convert to host delta tsc if tsc scaling is enabled */ | |
11702 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && | |
11703 | u64_shl_div_u64(delta_tsc, | |
11704 | kvm_tsc_scaling_ratio_frac_bits, | |
11705 | vcpu->arch.tsc_scaling_ratio, | |
11706 | &delta_tsc)) | |
11707 | return -ERANGE; | |
11708 | ||
11709 | /* | |
11710 | * If the delta tsc can't fit in the 32 bit after the multi shift, | |
11711 | * we can't use the preemption timer. | |
11712 | * It's possible that it fits on later vmentries, but checking | |
11713 | * on every vmentry is costly so we just use an hrtimer. | |
11714 | */ | |
11715 | if (delta_tsc >> (cpu_preemption_timer_multi + 32)) | |
11716 | return -ERANGE; | |
11717 | ||
11718 | vmx->hv_deadline_tsc = tscl + delta_tsc; | |
11719 | vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL, | |
11720 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
c8533544 WL |
11721 | |
11722 | return delta_tsc == 0; | |
64672c95 YJ |
11723 | } |
11724 | ||
11725 | static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) | |
11726 | { | |
11727 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
11728 | vmx->hv_deadline_tsc = -1; | |
11729 | vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL, | |
11730 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
11731 | } | |
11732 | #endif | |
11733 | ||
48d89b92 | 11734 | static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) |
ae97a3b8 | 11735 | { |
b4a2d31d RK |
11736 | if (ple_gap) |
11737 | shrink_ple_window(vcpu); | |
ae97a3b8 RK |
11738 | } |
11739 | ||
843e4330 KH |
11740 | static void vmx_slot_enable_log_dirty(struct kvm *kvm, |
11741 | struct kvm_memory_slot *slot) | |
11742 | { | |
11743 | kvm_mmu_slot_leaf_clear_dirty(kvm, slot); | |
11744 | kvm_mmu_slot_largepage_remove_write_access(kvm, slot); | |
11745 | } | |
11746 | ||
11747 | static void vmx_slot_disable_log_dirty(struct kvm *kvm, | |
11748 | struct kvm_memory_slot *slot) | |
11749 | { | |
11750 | kvm_mmu_slot_set_dirty(kvm, slot); | |
11751 | } | |
11752 | ||
11753 | static void vmx_flush_log_dirty(struct kvm *kvm) | |
11754 | { | |
11755 | kvm_flush_pml_buffers(kvm); | |
11756 | } | |
11757 | ||
c5f983f6 BD |
11758 | static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu) |
11759 | { | |
11760 | struct vmcs12 *vmcs12; | |
11761 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
11762 | gpa_t gpa; | |
11763 | struct page *page = NULL; | |
11764 | u64 *pml_address; | |
11765 | ||
11766 | if (is_guest_mode(vcpu)) { | |
11767 | WARN_ON_ONCE(vmx->nested.pml_full); | |
11768 | ||
11769 | /* | |
11770 | * Check if PML is enabled for the nested guest. | |
11771 | * Whether eptp bit 6 is set is already checked | |
11772 | * as part of A/D emulation. | |
11773 | */ | |
11774 | vmcs12 = get_vmcs12(vcpu); | |
11775 | if (!nested_cpu_has_pml(vmcs12)) | |
11776 | return 0; | |
11777 | ||
4769886b | 11778 | if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) { |
c5f983f6 BD |
11779 | vmx->nested.pml_full = true; |
11780 | return 1; | |
11781 | } | |
11782 | ||
11783 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull; | |
11784 | ||
5e2f30b7 DH |
11785 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address); |
11786 | if (is_error_page(page)) | |
c5f983f6 BD |
11787 | return 0; |
11788 | ||
11789 | pml_address = kmap(page); | |
11790 | pml_address[vmcs12->guest_pml_index--] = gpa; | |
11791 | kunmap(page); | |
53a70daf | 11792 | kvm_release_page_clean(page); |
c5f983f6 BD |
11793 | } |
11794 | ||
11795 | return 0; | |
11796 | } | |
11797 | ||
843e4330 KH |
11798 | static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, |
11799 | struct kvm_memory_slot *memslot, | |
11800 | gfn_t offset, unsigned long mask) | |
11801 | { | |
11802 | kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); | |
11803 | } | |
11804 | ||
cd39e117 PB |
11805 | static void __pi_post_block(struct kvm_vcpu *vcpu) |
11806 | { | |
11807 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
11808 | struct pi_desc old, new; | |
11809 | unsigned int dest; | |
cd39e117 PB |
11810 | |
11811 | do { | |
11812 | old.control = new.control = pi_desc->control; | |
8b306e2f PB |
11813 | WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR, |
11814 | "Wakeup handler not enabled while the VCPU is blocked\n"); | |
cd39e117 PB |
11815 | |
11816 | dest = cpu_physical_id(vcpu->cpu); | |
11817 | ||
11818 | if (x2apic_enabled()) | |
11819 | new.ndst = dest; | |
11820 | else | |
11821 | new.ndst = (dest << 8) & 0xFF00; | |
11822 | ||
cd39e117 PB |
11823 | /* set 'NV' to 'notification vector' */ |
11824 | new.nv = POSTED_INTR_VECTOR; | |
c0a1666b PB |
11825 | } while (cmpxchg64(&pi_desc->control, old.control, |
11826 | new.control) != old.control); | |
cd39e117 | 11827 | |
8b306e2f PB |
11828 | if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) { |
11829 | spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); | |
cd39e117 | 11830 | list_del(&vcpu->blocked_vcpu_list); |
8b306e2f | 11831 | spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); |
cd39e117 PB |
11832 | vcpu->pre_pcpu = -1; |
11833 | } | |
11834 | } | |
11835 | ||
bf9f6ac8 FW |
11836 | /* |
11837 | * This routine does the following things for vCPU which is going | |
11838 | * to be blocked if VT-d PI is enabled. | |
11839 | * - Store the vCPU to the wakeup list, so when interrupts happen | |
11840 | * we can find the right vCPU to wake up. | |
11841 | * - Change the Posted-interrupt descriptor as below: | |
11842 | * 'NDST' <-- vcpu->pre_pcpu | |
11843 | * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR | |
11844 | * - If 'ON' is set during this process, which means at least one | |
11845 | * interrupt is posted for this vCPU, we cannot block it, in | |
11846 | * this case, return 1, otherwise, return 0. | |
11847 | * | |
11848 | */ | |
bc22512b | 11849 | static int pi_pre_block(struct kvm_vcpu *vcpu) |
bf9f6ac8 | 11850 | { |
bf9f6ac8 FW |
11851 | unsigned int dest; |
11852 | struct pi_desc old, new; | |
11853 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
11854 | ||
11855 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
11856 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
11857 | !kvm_vcpu_apicv_active(vcpu)) | |
bf9f6ac8 FW |
11858 | return 0; |
11859 | ||
8b306e2f PB |
11860 | WARN_ON(irqs_disabled()); |
11861 | local_irq_disable(); | |
11862 | if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) { | |
11863 | vcpu->pre_pcpu = vcpu->cpu; | |
11864 | spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); | |
11865 | list_add_tail(&vcpu->blocked_vcpu_list, | |
11866 | &per_cpu(blocked_vcpu_on_cpu, | |
11867 | vcpu->pre_pcpu)); | |
11868 | spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); | |
11869 | } | |
bf9f6ac8 FW |
11870 | |
11871 | do { | |
11872 | old.control = new.control = pi_desc->control; | |
11873 | ||
bf9f6ac8 FW |
11874 | WARN((pi_desc->sn == 1), |
11875 | "Warning: SN field of posted-interrupts " | |
11876 | "is set before blocking\n"); | |
11877 | ||
11878 | /* | |
11879 | * Since vCPU can be preempted during this process, | |
11880 | * vcpu->cpu could be different with pre_pcpu, we | |
11881 | * need to set pre_pcpu as the destination of wakeup | |
11882 | * notification event, then we can find the right vCPU | |
11883 | * to wakeup in wakeup handler if interrupts happen | |
11884 | * when the vCPU is in blocked state. | |
11885 | */ | |
11886 | dest = cpu_physical_id(vcpu->pre_pcpu); | |
11887 | ||
11888 | if (x2apic_enabled()) | |
11889 | new.ndst = dest; | |
11890 | else | |
11891 | new.ndst = (dest << 8) & 0xFF00; | |
11892 | ||
11893 | /* set 'NV' to 'wakeup vector' */ | |
11894 | new.nv = POSTED_INTR_WAKEUP_VECTOR; | |
c0a1666b PB |
11895 | } while (cmpxchg64(&pi_desc->control, old.control, |
11896 | new.control) != old.control); | |
bf9f6ac8 | 11897 | |
8b306e2f PB |
11898 | /* We should not block the vCPU if an interrupt is posted for it. */ |
11899 | if (pi_test_on(pi_desc) == 1) | |
11900 | __pi_post_block(vcpu); | |
11901 | ||
11902 | local_irq_enable(); | |
11903 | return (vcpu->pre_pcpu == -1); | |
bf9f6ac8 FW |
11904 | } |
11905 | ||
bc22512b YJ |
11906 | static int vmx_pre_block(struct kvm_vcpu *vcpu) |
11907 | { | |
11908 | if (pi_pre_block(vcpu)) | |
11909 | return 1; | |
11910 | ||
64672c95 YJ |
11911 | if (kvm_lapic_hv_timer_in_use(vcpu)) |
11912 | kvm_lapic_switch_to_sw_timer(vcpu); | |
11913 | ||
bc22512b YJ |
11914 | return 0; |
11915 | } | |
11916 | ||
11917 | static void pi_post_block(struct kvm_vcpu *vcpu) | |
bf9f6ac8 | 11918 | { |
8b306e2f | 11919 | if (vcpu->pre_pcpu == -1) |
bf9f6ac8 FW |
11920 | return; |
11921 | ||
8b306e2f PB |
11922 | WARN_ON(irqs_disabled()); |
11923 | local_irq_disable(); | |
cd39e117 | 11924 | __pi_post_block(vcpu); |
8b306e2f | 11925 | local_irq_enable(); |
bf9f6ac8 FW |
11926 | } |
11927 | ||
bc22512b YJ |
11928 | static void vmx_post_block(struct kvm_vcpu *vcpu) |
11929 | { | |
64672c95 YJ |
11930 | if (kvm_x86_ops->set_hv_timer) |
11931 | kvm_lapic_switch_to_hv_timer(vcpu); | |
11932 | ||
bc22512b YJ |
11933 | pi_post_block(vcpu); |
11934 | } | |
11935 | ||
efc64404 FW |
11936 | /* |
11937 | * vmx_update_pi_irte - set IRTE for Posted-Interrupts | |
11938 | * | |
11939 | * @kvm: kvm | |
11940 | * @host_irq: host irq of the interrupt | |
11941 | * @guest_irq: gsi of the interrupt | |
11942 | * @set: set or unset PI | |
11943 | * returns 0 on success, < 0 on failure | |
11944 | */ | |
11945 | static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, | |
11946 | uint32_t guest_irq, bool set) | |
11947 | { | |
11948 | struct kvm_kernel_irq_routing_entry *e; | |
11949 | struct kvm_irq_routing_table *irq_rt; | |
11950 | struct kvm_lapic_irq irq; | |
11951 | struct kvm_vcpu *vcpu; | |
11952 | struct vcpu_data vcpu_info; | |
3a8b0677 | 11953 | int idx, ret = 0; |
efc64404 FW |
11954 | |
11955 | if (!kvm_arch_has_assigned_device(kvm) || | |
a0052191 YZ |
11956 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
11957 | !kvm_vcpu_apicv_active(kvm->vcpus[0])) | |
efc64404 FW |
11958 | return 0; |
11959 | ||
11960 | idx = srcu_read_lock(&kvm->irq_srcu); | |
11961 | irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); | |
3a8b0677 JS |
11962 | if (guest_irq >= irq_rt->nr_rt_entries || |
11963 | hlist_empty(&irq_rt->map[guest_irq])) { | |
11964 | pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n", | |
11965 | guest_irq, irq_rt->nr_rt_entries); | |
11966 | goto out; | |
11967 | } | |
efc64404 FW |
11968 | |
11969 | hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { | |
11970 | if (e->type != KVM_IRQ_ROUTING_MSI) | |
11971 | continue; | |
11972 | /* | |
11973 | * VT-d PI cannot support posting multicast/broadcast | |
11974 | * interrupts to a vCPU, we still use interrupt remapping | |
11975 | * for these kind of interrupts. | |
11976 | * | |
11977 | * For lowest-priority interrupts, we only support | |
11978 | * those with single CPU as the destination, e.g. user | |
11979 | * configures the interrupts via /proc/irq or uses | |
11980 | * irqbalance to make the interrupts single-CPU. | |
11981 | * | |
11982 | * We will support full lowest-priority interrupt later. | |
11983 | */ | |
11984 | ||
37131313 | 11985 | kvm_set_msi_irq(kvm, e, &irq); |
23a1c257 FW |
11986 | if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) { |
11987 | /* | |
11988 | * Make sure the IRTE is in remapped mode if | |
11989 | * we don't handle it in posted mode. | |
11990 | */ | |
11991 | ret = irq_set_vcpu_affinity(host_irq, NULL); | |
11992 | if (ret < 0) { | |
11993 | printk(KERN_INFO | |
11994 | "failed to back to remapped mode, irq: %u\n", | |
11995 | host_irq); | |
11996 | goto out; | |
11997 | } | |
11998 | ||
efc64404 | 11999 | continue; |
23a1c257 | 12000 | } |
efc64404 FW |
12001 | |
12002 | vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); | |
12003 | vcpu_info.vector = irq.vector; | |
12004 | ||
b6ce9780 | 12005 | trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi, |
efc64404 FW |
12006 | vcpu_info.vector, vcpu_info.pi_desc_addr, set); |
12007 | ||
12008 | if (set) | |
12009 | ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); | |
dc91f2eb | 12010 | else |
efc64404 | 12011 | ret = irq_set_vcpu_affinity(host_irq, NULL); |
efc64404 FW |
12012 | |
12013 | if (ret < 0) { | |
12014 | printk(KERN_INFO "%s: failed to update PI IRTE\n", | |
12015 | __func__); | |
12016 | goto out; | |
12017 | } | |
12018 | } | |
12019 | ||
12020 | ret = 0; | |
12021 | out: | |
12022 | srcu_read_unlock(&kvm->irq_srcu, idx); | |
12023 | return ret; | |
12024 | } | |
12025 | ||
c45dcc71 AR |
12026 | static void vmx_setup_mce(struct kvm_vcpu *vcpu) |
12027 | { | |
12028 | if (vcpu->arch.mcg_cap & MCG_LMCE_P) | |
12029 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= | |
12030 | FEATURE_CONTROL_LMCE; | |
12031 | else | |
12032 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= | |
12033 | ~FEATURE_CONTROL_LMCE; | |
12034 | } | |
12035 | ||
72d7b374 LP |
12036 | static int vmx_smi_allowed(struct kvm_vcpu *vcpu) |
12037 | { | |
72e9cbdb LP |
12038 | /* we need a nested vmexit to enter SMM, postpone if run is pending */ |
12039 | if (to_vmx(vcpu)->nested.nested_run_pending) | |
12040 | return 0; | |
72d7b374 LP |
12041 | return 1; |
12042 | } | |
12043 | ||
0234bf88 LP |
12044 | static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) |
12045 | { | |
72e9cbdb LP |
12046 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
12047 | ||
12048 | vmx->nested.smm.guest_mode = is_guest_mode(vcpu); | |
12049 | if (vmx->nested.smm.guest_mode) | |
12050 | nested_vmx_vmexit(vcpu, -1, 0, 0); | |
12051 | ||
12052 | vmx->nested.smm.vmxon = vmx->nested.vmxon; | |
12053 | vmx->nested.vmxon = false; | |
0234bf88 LP |
12054 | return 0; |
12055 | } | |
12056 | ||
12057 | static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase) | |
12058 | { | |
72e9cbdb LP |
12059 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
12060 | int ret; | |
12061 | ||
12062 | if (vmx->nested.smm.vmxon) { | |
12063 | vmx->nested.vmxon = true; | |
12064 | vmx->nested.smm.vmxon = false; | |
12065 | } | |
12066 | ||
12067 | if (vmx->nested.smm.guest_mode) { | |
12068 | vcpu->arch.hflags &= ~HF_SMM_MASK; | |
12069 | ret = enter_vmx_non_root_mode(vcpu, false); | |
12070 | vcpu->arch.hflags |= HF_SMM_MASK; | |
12071 | if (ret) | |
12072 | return ret; | |
12073 | ||
12074 | vmx->nested.smm.guest_mode = false; | |
12075 | } | |
0234bf88 LP |
12076 | return 0; |
12077 | } | |
12078 | ||
cc3d967f LP |
12079 | static int enable_smi_window(struct kvm_vcpu *vcpu) |
12080 | { | |
12081 | return 0; | |
12082 | } | |
12083 | ||
404f6aac | 12084 | static struct kvm_x86_ops vmx_x86_ops __ro_after_init = { |
6aa8b732 AK |
12085 | .cpu_has_kvm_support = cpu_has_kvm_support, |
12086 | .disabled_by_bios = vmx_disabled_by_bios, | |
12087 | .hardware_setup = hardware_setup, | |
12088 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 12089 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
12090 | .hardware_enable = hardware_enable, |
12091 | .hardware_disable = hardware_disable, | |
04547156 | 12092 | .cpu_has_accelerated_tpr = report_flexpriority, |
6d396b55 | 12093 | .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase, |
6aa8b732 AK |
12094 | |
12095 | .vcpu_create = vmx_create_vcpu, | |
12096 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 12097 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 12098 | |
04d2cc77 | 12099 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
12100 | .vcpu_load = vmx_vcpu_load, |
12101 | .vcpu_put = vmx_vcpu_put, | |
12102 | ||
a96036b8 | 12103 | .update_bp_intercept = update_exception_bitmap, |
6aa8b732 AK |
12104 | .get_msr = vmx_get_msr, |
12105 | .set_msr = vmx_set_msr, | |
12106 | .get_segment_base = vmx_get_segment_base, | |
12107 | .get_segment = vmx_get_segment, | |
12108 | .set_segment = vmx_set_segment, | |
2e4d2653 | 12109 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 12110 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
e8467fda | 12111 | .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, |
aff48baa | 12112 | .decache_cr3 = vmx_decache_cr3, |
25c4c276 | 12113 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 12114 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
12115 | .set_cr3 = vmx_set_cr3, |
12116 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 12117 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
12118 | .get_idt = vmx_get_idt, |
12119 | .set_idt = vmx_set_idt, | |
12120 | .get_gdt = vmx_get_gdt, | |
12121 | .set_gdt = vmx_set_gdt, | |
73aaf249 JK |
12122 | .get_dr6 = vmx_get_dr6, |
12123 | .set_dr6 = vmx_set_dr6, | |
020df079 | 12124 | .set_dr7 = vmx_set_dr7, |
81908bf4 | 12125 | .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, |
5fdbf976 | 12126 | .cache_reg = vmx_cache_reg, |
6aa8b732 AK |
12127 | .get_rflags = vmx_get_rflags, |
12128 | .set_rflags = vmx_set_rflags, | |
be94f6b7 | 12129 | |
6aa8b732 | 12130 | .tlb_flush = vmx_flush_tlb, |
6aa8b732 | 12131 | |
6aa8b732 | 12132 | .run = vmx_vcpu_run, |
6062d012 | 12133 | .handle_exit = vmx_handle_exit, |
6aa8b732 | 12134 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
12135 | .set_interrupt_shadow = vmx_set_interrupt_shadow, |
12136 | .get_interrupt_shadow = vmx_get_interrupt_shadow, | |
102d8325 | 12137 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 | 12138 | .set_irq = vmx_inject_irq, |
95ba8273 | 12139 | .set_nmi = vmx_inject_nmi, |
298101da | 12140 | .queue_exception = vmx_queue_exception, |
b463a6f7 | 12141 | .cancel_injection = vmx_cancel_injection, |
78646121 | 12142 | .interrupt_allowed = vmx_interrupt_allowed, |
95ba8273 | 12143 | .nmi_allowed = vmx_nmi_allowed, |
3cfc3092 JK |
12144 | .get_nmi_mask = vmx_get_nmi_mask, |
12145 | .set_nmi_mask = vmx_set_nmi_mask, | |
95ba8273 GN |
12146 | .enable_nmi_window = enable_nmi_window, |
12147 | .enable_irq_window = enable_irq_window, | |
12148 | .update_cr8_intercept = update_cr8_intercept, | |
8d14695f | 12149 | .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode, |
38b99173 | 12150 | .set_apic_access_page_addr = vmx_set_apic_access_page_addr, |
d62caabb AS |
12151 | .get_enable_apicv = vmx_get_enable_apicv, |
12152 | .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, | |
c7c9c56c | 12153 | .load_eoi_exitmap = vmx_load_eoi_exitmap, |
967235d3 | 12154 | .apicv_post_state_restore = vmx_apicv_post_state_restore, |
c7c9c56c YZ |
12155 | .hwapic_irr_update = vmx_hwapic_irr_update, |
12156 | .hwapic_isr_update = vmx_hwapic_isr_update, | |
a20ed54d YZ |
12157 | .sync_pir_to_irr = vmx_sync_pir_to_irr, |
12158 | .deliver_posted_interrupt = vmx_deliver_posted_interrupt, | |
95ba8273 | 12159 | |
cbc94022 | 12160 | .set_tss_addr = vmx_set_tss_addr, |
67253af5 | 12161 | .get_tdp_level = get_ept_level, |
4b12f0de | 12162 | .get_mt_mask = vmx_get_mt_mask, |
229456fc | 12163 | |
586f9607 | 12164 | .get_exit_info = vmx_get_exit_info, |
586f9607 | 12165 | |
17cc3935 | 12166 | .get_lpage_level = vmx_get_lpage_level, |
0e851880 SY |
12167 | |
12168 | .cpuid_update = vmx_cpuid_update, | |
4e47c7a6 SY |
12169 | |
12170 | .rdtscp_supported = vmx_rdtscp_supported, | |
ad756a16 | 12171 | .invpcid_supported = vmx_invpcid_supported, |
d4330ef2 JR |
12172 | |
12173 | .set_supported_cpuid = vmx_set_supported_cpuid, | |
f5f48ee1 SY |
12174 | |
12175 | .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, | |
99e3e30a ZA |
12176 | |
12177 | .write_tsc_offset = vmx_write_tsc_offset, | |
1c97f0a0 JR |
12178 | |
12179 | .set_tdp_cr3 = vmx_set_cr3, | |
8a76d7f2 JR |
12180 | |
12181 | .check_intercept = vmx_check_intercept, | |
a547c6db | 12182 | .handle_external_intr = vmx_handle_external_intr, |
da8999d3 | 12183 | .mpx_supported = vmx_mpx_supported, |
55412b2e | 12184 | .xsaves_supported = vmx_xsaves_supported, |
b6b8a145 JK |
12185 | |
12186 | .check_nested_events = vmx_check_nested_events, | |
ae97a3b8 RK |
12187 | |
12188 | .sched_in = vmx_sched_in, | |
843e4330 KH |
12189 | |
12190 | .slot_enable_log_dirty = vmx_slot_enable_log_dirty, | |
12191 | .slot_disable_log_dirty = vmx_slot_disable_log_dirty, | |
12192 | .flush_log_dirty = vmx_flush_log_dirty, | |
12193 | .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, | |
c5f983f6 | 12194 | .write_log_dirty = vmx_write_pml_buffer, |
25462f7f | 12195 | |
bf9f6ac8 FW |
12196 | .pre_block = vmx_pre_block, |
12197 | .post_block = vmx_post_block, | |
12198 | ||
25462f7f | 12199 | .pmu_ops = &intel_pmu_ops, |
efc64404 FW |
12200 | |
12201 | .update_pi_irte = vmx_update_pi_irte, | |
64672c95 YJ |
12202 | |
12203 | #ifdef CONFIG_X86_64 | |
12204 | .set_hv_timer = vmx_set_hv_timer, | |
12205 | .cancel_hv_timer = vmx_cancel_hv_timer, | |
12206 | #endif | |
c45dcc71 AR |
12207 | |
12208 | .setup_mce = vmx_setup_mce, | |
0234bf88 | 12209 | |
72d7b374 | 12210 | .smi_allowed = vmx_smi_allowed, |
0234bf88 LP |
12211 | .pre_enter_smm = vmx_pre_enter_smm, |
12212 | .pre_leave_smm = vmx_pre_leave_smm, | |
cc3d967f | 12213 | .enable_smi_window = enable_smi_window, |
6aa8b732 AK |
12214 | }; |
12215 | ||
12216 | static int __init vmx_init(void) | |
12217 | { | |
34a1cd60 TC |
12218 | int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), |
12219 | __alignof__(struct vcpu_vmx), THIS_MODULE); | |
fdef3ad1 | 12220 | if (r) |
34a1cd60 | 12221 | return r; |
25c5f225 | 12222 | |
2965faa5 | 12223 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
12224 | rcu_assign_pointer(crash_vmclear_loaded_vmcss, |
12225 | crash_vmclear_local_loaded_vmcss); | |
12226 | #endif | |
12227 | ||
fdef3ad1 | 12228 | return 0; |
6aa8b732 AK |
12229 | } |
12230 | ||
12231 | static void __exit vmx_exit(void) | |
12232 | { | |
2965faa5 | 12233 | #ifdef CONFIG_KEXEC_CORE |
3b63a43f | 12234 | RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); |
8f536b76 ZY |
12235 | synchronize_rcu(); |
12236 | #endif | |
12237 | ||
cb498ea2 | 12238 | kvm_exit(); |
6aa8b732 AK |
12239 | } |
12240 | ||
12241 | module_init(vmx_init) | |
12242 | module_exit(vmx_exit) |