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KVM: MMU: enable gbpages by increasing nr of pagesizes
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
aec51dc4
AK		 40#include <trace/events/kvm.h>
41#undef TRACE_INCLUDE_FILE
229456fc
MT		 42#define CREATE_TRACE_POINTS
43#include "trace.h"
043405e1
CO		 44
45#include <asm/uaccess.h>
d825ed0a 46#include <asm/msr.h>
a5f61300 47#include <asm/desc.h>
0bed3b56 48#include <asm/mtrr.h>
890ca9ae 49#include <asm/mce.h>
043405e1 50
313a3dc7 51#define MAX_IO_MSRS 256
a03490ed
CO		 52#define CR0_RESERVED_BITS \
53 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
54 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
55 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
56#define CR4_RESERVED_BITS \
57 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
58 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
59 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
60 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
61
62#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 63
64#define KVM_MAX_MCE_BANKS 32
65#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
66
50a37eb4
JR		 67/* EFER defaults:
68 * - enable syscall per default because its emulated by KVM
69 * - enable LME and LMA per default on 64 bit KVM
70 */
71#ifdef CONFIG_X86_64
72static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
73#else
74static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
75#endif
313a3dc7 76
ba1389b7
AK		 77#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
78#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 79
674eea0f
AK		 80static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
81 struct kvm_cpuid_entry2 __user *entries);
82
97896d04 83struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 84EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 85
ed85c068
AP		 86int ignore_msrs = 0;
87module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
88
417bc304 89struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 90 { "pf_fixed", VCPU_STAT(pf_fixed) },
91 { "pf_guest", VCPU_STAT(pf_guest) },
92 { "tlb_flush", VCPU_STAT(tlb_flush) },
93 { "invlpg", VCPU_STAT(invlpg) },
94 { "exits", VCPU_STAT(exits) },
95 { "io_exits", VCPU_STAT(io_exits) },
96 { "mmio_exits", VCPU_STAT(mmio_exits) },
97 { "signal_exits", VCPU_STAT(signal_exits) },
98 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 99 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 100 { "halt_exits", VCPU_STAT(halt_exits) },
101 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 102 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 103 { "request_irq", VCPU_STAT(request_irq_exits) },
104 { "irq_exits", VCPU_STAT(irq_exits) },
105 { "host_state_reload", VCPU_STAT(host_state_reload) },
106 { "efer_reload", VCPU_STAT(efer_reload) },
107 { "fpu_reload", VCPU_STAT(fpu_reload) },
108 { "insn_emulation", VCPU_STAT(insn_emulation) },
109 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 110 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 111 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 112 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
113 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
114 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
115 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
116 { "mmu_flooded", VM_STAT(mmu_flooded) },
117 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 118 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 119 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 120 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 121 { "largepages", VM_STAT(lpages) },
417bc304
HB		 122 { NULL }
123};
124
5fb76f9b
CO		 125unsigned long segment_base(u16 selector)
126{
127 struct descriptor_table gdt;
a5f61300 128 struct desc_struct *d;
5fb76f9b
CO		 129 unsigned long table_base;
130 unsigned long v;
131
132 if (selector == 0)
133 return 0;
134
b792c344 135 kvm_get_gdt(&gdt);
5fb76f9b
CO		 136 table_base = gdt.base;
137
138 if (selector & 4) { /* from ldt */
b792c344 139 u16 ldt_selector = kvm_read_ldt();
5fb76f9b 140
5fb76f9b
CO		 141 table_base = segment_base(ldt_selector);
142 }
a5f61300 143 d = (struct desc_struct *)(table_base + (selector & ~7));
46a359e7 144 v = get_desc_base(d);
5fb76f9b 145#ifdef CONFIG_X86_64
a5f61300
AK		 146 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
147 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 148#endif
149 return v;
150}
151EXPORT_SYMBOL_GPL(segment_base);
152
6866b83e
CO		 153u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
154{
155 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 156 return vcpu->arch.apic_base;
6866b83e 157 else
ad312c7c 158 return vcpu->arch.apic_base;
6866b83e
CO		 159}
160EXPORT_SYMBOL_GPL(kvm_get_apic_base);
161
162void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
163{
164 /* TODO: reserve bits check */
165 if (irqchip_in_kernel(vcpu->kvm))
166 kvm_lapic_set_base(vcpu, data);
167 else
ad312c7c 168 vcpu->arch.apic_base = data;
6866b83e
CO		 169}
170EXPORT_SYMBOL_GPL(kvm_set_apic_base);
171
298101da
AK		 172void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
173{
ad312c7c
ZX		 174 WARN_ON(vcpu->arch.exception.pending);
175 vcpu->arch.exception.pending = true;
176 vcpu->arch.exception.has_error_code = false;
177 vcpu->arch.exception.nr = nr;
298101da
AK		 178}
179EXPORT_SYMBOL_GPL(kvm_queue_exception);
180
c3c91fee
AK		 181void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
182 u32 error_code)
183{
184 ++vcpu->stat.pf_guest;
d8017474 185
71c4dfaf 186 if (vcpu->arch.exception.pending) {
6edf14d8
GN		 187 switch(vcpu->arch.exception.nr) {
188 case DF_VECTOR:
71c4dfaf
JR		 189 /* triple fault -> shutdown */
190 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
6edf14d8
GN		 191 return;
192 case PF_VECTOR:
193 vcpu->arch.exception.nr = DF_VECTOR;
194 vcpu->arch.exception.error_code = 0;
195 return;
196 default:
197 /* replace previous exception with a new one in a hope
198 that instruction re-execution will regenerate lost
199 exception */
200 vcpu->arch.exception.pending = false;
201 break;
71c4dfaf 202 }
c3c91fee 203 }
ad312c7c 204 vcpu->arch.cr2 = addr;
c3c91fee
AK		 205 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
206}
207
3419ffc8
SY		 208void kvm_inject_nmi(struct kvm_vcpu *vcpu)
209{
210 vcpu->arch.nmi_pending = 1;
211}
212EXPORT_SYMBOL_GPL(kvm_inject_nmi);
213
298101da
AK		 214void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
215{
ad312c7c
ZX		 216 WARN_ON(vcpu->arch.exception.pending);
217 vcpu->arch.exception.pending = true;
218 vcpu->arch.exception.has_error_code = true;
219 vcpu->arch.exception.nr = nr;
220 vcpu->arch.exception.error_code = error_code;
298101da
AK		 221}
222EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
223
a03490ed
CO		 224/*
225 * Load the pae pdptrs. Return true is they are all valid.
226 */
227int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
228{
229 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
230 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
231 int i;
232 int ret;
ad312c7c 233 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 234
a03490ed
CO		 235 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
236 offset * sizeof(u64), sizeof(pdpte));
237 if (ret < 0) {
238 ret = 0;
239 goto out;
240 }
241 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 242 if (is_present_gpte(pdpte[i]) &&
20c466b5 243 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 244 ret = 0;
245 goto out;
246 }
247 }
248 ret = 1;
249
ad312c7c 250 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 251 __set_bit(VCPU_EXREG_PDPTR,
252 (unsigned long *)&vcpu->arch.regs_avail);
253 __set_bit(VCPU_EXREG_PDPTR,
254 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 255out:
a03490ed
CO		 256
257 return ret;
258}
cc4b6871 259EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 260
d835dfec
AK		 261static bool pdptrs_changed(struct kvm_vcpu *vcpu)
262{
ad312c7c 263 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 264 bool changed = true;
265 int r;
266
267 if (is_long_mode(vcpu) || !is_pae(vcpu))
268 return false;
269
6de4f3ad
AK		 270 if (!test_bit(VCPU_EXREG_PDPTR,
271 (unsigned long *)&vcpu->arch.regs_avail))
272 return true;
273
ad312c7c 274 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 275 if (r < 0)
276 goto out;
ad312c7c 277 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 278out:
d835dfec
AK		 279
280 return changed;
281}
282
2d3ad1f4 283void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 284{
285 if (cr0 & CR0_RESERVED_BITS) {
286 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 287 cr0, vcpu->arch.cr0);
c1a5d4f9 288 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 289 return;
290 }
291
292 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
293 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 294 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 295 return;
296 }
297
298 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
299 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
300 "and a clear PE flag\n");
c1a5d4f9 301 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 302 return;
303 }
304
305 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
306#ifdef CONFIG_X86_64
ad312c7c 307 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 308 int cs_db, cs_l;
309
310 if (!is_pae(vcpu)) {
311 printk(KERN_DEBUG "set_cr0: #GP, start paging "
312 "in long mode while PAE is disabled\n");
c1a5d4f9 313 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 314 return;
315 }
316 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
317 if (cs_l) {
318 printk(KERN_DEBUG "set_cr0: #GP, start paging "
319 "in long mode while CS.L == 1\n");
c1a5d4f9 320 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 321 return;
322
323 }
324 } else
325#endif
ad312c7c 326 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 327 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
328 "reserved bits\n");
c1a5d4f9 329 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 330 return;
331 }
332
333 }
334
335 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 336 vcpu->arch.cr0 = cr0;
a03490ed 337
a03490ed 338 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 339 return;
340}
2d3ad1f4 341EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 342
2d3ad1f4 343void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 344{
2d3ad1f4 345 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
a03490ed 346}
2d3ad1f4 347EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 348
2d3ad1f4 349void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 350{
a2edf57f
AK		 351 unsigned long old_cr4 = vcpu->arch.cr4;
352 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
353
a03490ed
CO		 354 if (cr4 & CR4_RESERVED_BITS) {
355 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 356 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 357 return;
358 }
359
360 if (is_long_mode(vcpu)) {
361 if (!(cr4 & X86_CR4_PAE)) {
362 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
363 "in long mode\n");
c1a5d4f9 364 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 365 return;
366 }
a2edf57f
AK		 367 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
368 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 369 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 370 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 371 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 372 return;
373 }
374
375 if (cr4 & X86_CR4_VMXE) {
376 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 377 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 378 return;
379 }
380 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 381 vcpu->arch.cr4 = cr4;
5a41accd 382 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 383 kvm_mmu_reset_context(vcpu);
a03490ed 384}
2d3ad1f4 385EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 386
2d3ad1f4 387void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 388{
ad312c7c 389 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 390 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 391 kvm_mmu_flush_tlb(vcpu);
392 return;
393 }
394
a03490ed
CO		 395 if (is_long_mode(vcpu)) {
396 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
397 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 398 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 399 return;
400 }
401 } else {
402 if (is_pae(vcpu)) {
403 if (cr3 & CR3_PAE_RESERVED_BITS) {
404 printk(KERN_DEBUG
405 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 406 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 407 return;
408 }
409 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
410 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
411 "reserved bits\n");
c1a5d4f9 412 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 413 return;
414 }
415 }
416 /*
417 * We don't check reserved bits in nonpae mode, because
418 * this isn't enforced, and VMware depends on this.
419 */
420 }
421
a03490ed
CO		 422 /*
423 * Does the new cr3 value map to physical memory? (Note, we
424 * catch an invalid cr3 even in real-mode, because it would
425 * cause trouble later on when we turn on paging anyway.)
426 *
427 * A real CPU would silently accept an invalid cr3 and would
428 * attempt to use it - with largely undefined (and often hard
429 * to debug) behavior on the guest side.
430 */
431 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 432 kvm_inject_gp(vcpu, 0);
a03490ed 433 else {
ad312c7c
ZX		 434 vcpu->arch.cr3 = cr3;
435 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 436 }
a03490ed 437}
2d3ad1f4 438EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 439
2d3ad1f4 440void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 441{
442 if (cr8 & CR8_RESERVED_BITS) {
443 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 444 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 445 return;
446 }
447 if (irqchip_in_kernel(vcpu->kvm))
448 kvm_lapic_set_tpr(vcpu, cr8);
449 else
ad312c7c 450 vcpu->arch.cr8 = cr8;
a03490ed 451}
2d3ad1f4 452EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 453
2d3ad1f4 454unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 455{
456 if (irqchip_in_kernel(vcpu->kvm))
457 return kvm_lapic_get_cr8(vcpu);
458 else
ad312c7c 459 return vcpu->arch.cr8;
a03490ed 460}
2d3ad1f4 461EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 462
d8017474
AG		 463static inline u32 bit(int bitno)
464{
465 return 1 << (bitno & 31);
466}
467
043405e1
CO		 468/*
469 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
470 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
471 *
472 * This list is modified at module load time to reflect the
473 * capabilities of the host cpu.
474 */
475static u32 msrs_to_save[] = {
476 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
477 MSR_K6_STAR,
478#ifdef CONFIG_X86_64
479 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
480#endif
af24a4e4 481 MSR_IA32_TSC, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
b286d5d8 482 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 483};
484
485static unsigned num_msrs_to_save;
486
487static u32 emulated_msrs[] = {
488 MSR_IA32_MISC_ENABLE,
489};
490
15c4a640
CO		 491static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
492{
f2b4b7dd 493 if (efer & efer_reserved_bits) {
15c4a640
CO		 494 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
495 efer);
c1a5d4f9 496 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 497 return;
498 }
499
500 if (is_paging(vcpu)
ad312c7c 501 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 502 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 503 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 504 return;
505 }
506
1b2fd70c
AG		 507 if (efer & EFER_FFXSR) {
508 struct kvm_cpuid_entry2 *feat;
509
510 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
511 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
512 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
513 kvm_inject_gp(vcpu, 0);
514 return;
515 }
516 }
517
d8017474
AG		 518 if (efer & EFER_SVME) {
519 struct kvm_cpuid_entry2 *feat;
520
521 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
522 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
523 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
524 kvm_inject_gp(vcpu, 0);
525 return;
526 }
527 }
528
15c4a640
CO		 529 kvm_x86_ops->set_efer(vcpu, efer);
530
531 efer &= ~EFER_LMA;
ad312c7c 532 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 533
ad312c7c 534 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 535
536 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
537 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 538}
539
f2b4b7dd
JR		 540void kvm_enable_efer_bits(u64 mask)
541{
542 efer_reserved_bits &= ~mask;
543}
544EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
545
546
15c4a640
CO		 547/*
548 * Writes msr value into into the appropriate "register".
549 * Returns 0 on success, non-0 otherwise.
550 * Assumes vcpu_load() was already called.
551 */
552int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
553{
554 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
555}
556
313a3dc7
CO		 557/*
558 * Adapt set_msr() to msr_io()'s calling convention
559 */
560static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
561{
562 return kvm_set_msr(vcpu, index, *data);
563}
564
18068523
GOC		 565static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
566{
567 static int version;
50d0a0f9
GH		 568 struct pvclock_wall_clock wc;
569 struct timespec now, sys, boot;
18068523
GOC		 570
571 if (!wall_clock)
572 return;
573
574 version++;
575
18068523
GOC		 576 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
577
50d0a0f9
GH		 578 /*
579 * The guest calculates current wall clock time by adding
580 * system time (updated by kvm_write_guest_time below) to the
581 * wall clock specified here. guest system time equals host
582 * system time for us, thus we must fill in host boot time here.
583 */
584 now = current_kernel_time();
585 ktime_get_ts(&sys);
586 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
587
588 wc.sec = boot.tv_sec;
589 wc.nsec = boot.tv_nsec;
590 wc.version = version;
18068523
GOC		 591
592 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
593
594 version++;
595 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 596}
597
50d0a0f9
GH		 598static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
599{
600 uint32_t quotient, remainder;
601
602 /* Don't try to replace with do_div(), this one calculates
603 * "(dividend << 32) / divisor" */
604 __asm__ ( "divl %4"
605 : "=a" (quotient), "=d" (remainder)
606 : "0" (0), "1" (dividend), "r" (divisor) );
607 return quotient;
608}
609
610static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
611{
612 uint64_t nsecs = 1000000000LL;
613 int32_t shift = 0;
614 uint64_t tps64;
615 uint32_t tps32;
616
617 tps64 = tsc_khz * 1000LL;
618 while (tps64 > nsecs*2) {
619 tps64 >>= 1;
620 shift--;
621 }
622
623 tps32 = (uint32_t)tps64;
624 while (tps32 <= (uint32_t)nsecs) {
625 tps32 <<= 1;
626 shift++;
627 }
628
629 hv_clock->tsc_shift = shift;
630 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
631
632 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 633 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 634 hv_clock->tsc_to_system_mul);
635}
636
c8076604
GH		 637static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
638
18068523
GOC		 639static void kvm_write_guest_time(struct kvm_vcpu *v)
640{
641 struct timespec ts;
642 unsigned long flags;
643 struct kvm_vcpu_arch *vcpu = &v->arch;
644 void *shared_kaddr;
463656c0 645 unsigned long this_tsc_khz;
18068523
GOC		 646
647 if ((!vcpu->time_page))
648 return;
649
463656c0
AK		 650 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
651 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
652 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
653 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 654 }
463656c0 655 put_cpu_var(cpu_tsc_khz);
50d0a0f9 656
18068523
GOC		 657 /* Keep irq disabled to prevent changes to the clock */
658 local_irq_save(flags);
af24a4e4 659 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523
GOC		 660 ktime_get_ts(&ts);
661 local_irq_restore(flags);
662
663 /* With all the info we got, fill in the values */
664
665 vcpu->hv_clock.system_time = ts.tv_nsec +
666 (NSEC_PER_SEC * (u64)ts.tv_sec);
667 /*
668 * The interface expects us to write an even number signaling that the
669 * update is finished. Since the guest won't see the intermediate
50d0a0f9 670 * state, we just increase by 2 at the end.
18068523 671 */
50d0a0f9 672 vcpu->hv_clock.version += 2;
18068523
GOC		 673
674 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
675
676 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 677 sizeof(vcpu->hv_clock));
18068523
GOC		 678
679 kunmap_atomic(shared_kaddr, KM_USER0);
680
681 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
682}
683
c8076604
GH		 684static int kvm_request_guest_time_update(struct kvm_vcpu *v)
685{
686 struct kvm_vcpu_arch *vcpu = &v->arch;
687
688 if (!vcpu->time_page)
689 return 0;
690 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
691 return 1;
692}
693
9ba075a6
AK		 694static bool msr_mtrr_valid(unsigned msr)
695{
696 switch (msr) {
697 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
698 case MSR_MTRRfix64K_00000:
699 case MSR_MTRRfix16K_80000:
700 case MSR_MTRRfix16K_A0000:
701 case MSR_MTRRfix4K_C0000:
702 case MSR_MTRRfix4K_C8000:
703 case MSR_MTRRfix4K_D0000:
704 case MSR_MTRRfix4K_D8000:
705 case MSR_MTRRfix4K_E0000:
706 case MSR_MTRRfix4K_E8000:
707 case MSR_MTRRfix4K_F0000:
708 case MSR_MTRRfix4K_F8000:
709 case MSR_MTRRdefType:
710 case MSR_IA32_CR_PAT:
711 return true;
712 case 0x2f8:
713 return true;
714 }
715 return false;
716}
717
d6289b93
MT		 718static bool valid_pat_type(unsigned t)
719{
720 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
721}
722
723static bool valid_mtrr_type(unsigned t)
724{
725 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
726}
727
728static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
729{
730 int i;
731
732 if (!msr_mtrr_valid(msr))
733 return false;
734
735 if (msr == MSR_IA32_CR_PAT) {
736 for (i = 0; i < 8; i++)
737 if (!valid_pat_type((data >> (i * 8)) & 0xff))
738 return false;
739 return true;
740 } else if (msr == MSR_MTRRdefType) {
741 if (data & ~0xcff)
742 return false;
743 return valid_mtrr_type(data & 0xff);
744 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
745 for (i = 0; i < 8 ; i++)
746 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
747 return false;
748 return true;
749 }
750
751 /* variable MTRRs */
752 return valid_mtrr_type(data & 0xff);
753}
754
9ba075a6
AK		 755static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
756{
0bed3b56
SY		 757 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
758
d6289b93 759 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 760 return 1;
761
0bed3b56
SY		 762 if (msr == MSR_MTRRdefType) {
763 vcpu->arch.mtrr_state.def_type = data;
764 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
765 } else if (msr == MSR_MTRRfix64K_00000)
766 p[0] = data;
767 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
768 p[1 + msr - MSR_MTRRfix16K_80000] = data;
769 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
770 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
771 else if (msr == MSR_IA32_CR_PAT)
772 vcpu->arch.pat = data;
773 else { /* Variable MTRRs */
774 int idx, is_mtrr_mask;
775 u64 *pt;
776
777 idx = (msr - 0x200) / 2;
778 is_mtrr_mask = msr - 0x200 - 2 * idx;
779 if (!is_mtrr_mask)
780 pt =
781 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
782 else
783 pt =
784 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
785 *pt = data;
786 }
787
788 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 789 return 0;
790}
15c4a640 791
890ca9ae 792static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 793{
890ca9ae
HY		 794 u64 mcg_cap = vcpu->arch.mcg_cap;
795 unsigned bank_num = mcg_cap & 0xff;
796
15c4a640 797 switch (msr) {
15c4a640 798 case MSR_IA32_MCG_STATUS:
890ca9ae 799 vcpu->arch.mcg_status = data;
15c4a640 800 break;
c7ac679c 801 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 802 if (!(mcg_cap & MCG_CTL_P))
803 return 1;
804 if (data != 0 && data != ~(u64)0)
805 return -1;
806 vcpu->arch.mcg_ctl = data;
807 break;
808 default:
809 if (msr >= MSR_IA32_MC0_CTL &&
810 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
811 u32 offset = msr - MSR_IA32_MC0_CTL;
812 /* only 0 or all 1s can be written to IA32_MCi_CTL */
813 if ((offset & 0x3) == 0 &&
814 data != 0 && data != ~(u64)0)
815 return -1;
816 vcpu->arch.mce_banks[offset] = data;
817 break;
818 }
819 return 1;
820 }
821 return 0;
822}
823
824int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
825{
826 switch (msr) {
827 case MSR_EFER:
828 set_efer(vcpu, data);
c7ac679c 829 break;
8f1589d9
AP		 830 case MSR_K7_HWCR:
831 data &= ~(u64)0x40; /* ignore flush filter disable */
832 if (data != 0) {
833 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
834 data);
835 return 1;
836 }
837 break;
f7c6d140
AP		 838 case MSR_FAM10H_MMIO_CONF_BASE:
839 if (data != 0) {
840 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
841 "0x%llx\n", data);
842 return 1;
843 }
844 break;
c323c0e5
AP		 845 case MSR_AMD64_NB_CFG:
846 break;
b5e2fec0
AG		 847 case MSR_IA32_DEBUGCTLMSR:
848 if (!data) {
849 /* We support the non-activated case already */
850 break;
851 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
852 /* Values other than LBR and BTF are vendor-specific,
853 thus reserved and should throw a #GP */
854 return 1;
855 }
856 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
857 __func__, data);
858 break;
15c4a640
CO		 859 case MSR_IA32_UCODE_REV:
860 case MSR_IA32_UCODE_WRITE:
61a6bd67 861 case MSR_VM_HSAVE_PA:
6098ca93 862 case MSR_AMD64_PATCH_LOADER:
15c4a640 863 break;
9ba075a6
AK		 864 case 0x200 ... 0x2ff:
865 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 866 case MSR_IA32_APICBASE:
867 kvm_set_apic_base(vcpu, data);
868 break;
0105d1a5
GN		 869 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
870 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 871 case MSR_IA32_MISC_ENABLE:
ad312c7c 872 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 873 break;
18068523
GOC		 874 case MSR_KVM_WALL_CLOCK:
875 vcpu->kvm->arch.wall_clock = data;
876 kvm_write_wall_clock(vcpu->kvm, data);
877 break;
878 case MSR_KVM_SYSTEM_TIME: {
879 if (vcpu->arch.time_page) {
880 kvm_release_page_dirty(vcpu->arch.time_page);
881 vcpu->arch.time_page = NULL;
882 }
883
884 vcpu->arch.time = data;
885
886 /* we verify if the enable bit is set... */
887 if (!(data & 1))
888 break;
889
890 /* ...but clean it before doing the actual write */
891 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
892
18068523
GOC		 893 vcpu->arch.time_page =
894 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 895
896 if (is_error_page(vcpu->arch.time_page)) {
897 kvm_release_page_clean(vcpu->arch.time_page);
898 vcpu->arch.time_page = NULL;
899 }
900
c8076604 901 kvm_request_guest_time_update(vcpu);
18068523
GOC		 902 break;
903 }
890ca9ae
HY		 904 case MSR_IA32_MCG_CTL:
905 case MSR_IA32_MCG_STATUS:
906 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
907 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 908
909 /* Performance counters are not protected by a CPUID bit,
910 * so we should check all of them in the generic path for the sake of
911 * cross vendor migration.
912 * Writing a zero into the event select MSRs disables them,
913 * which we perfectly emulate ;-). Any other value should be at least
914 * reported, some guests depend on them.
915 */
916 case MSR_P6_EVNTSEL0:
917 case MSR_P6_EVNTSEL1:
918 case MSR_K7_EVNTSEL0:
919 case MSR_K7_EVNTSEL1:
920 case MSR_K7_EVNTSEL2:
921 case MSR_K7_EVNTSEL3:
922 if (data != 0)
923 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
924 "0x%x data 0x%llx\n", msr, data);
925 break;
926 /* at least RHEL 4 unconditionally writes to the perfctr registers,
927 * so we ignore writes to make it happy.
928 */
929 case MSR_P6_PERFCTR0:
930 case MSR_P6_PERFCTR1:
931 case MSR_K7_PERFCTR0:
932 case MSR_K7_PERFCTR1:
933 case MSR_K7_PERFCTR2:
934 case MSR_K7_PERFCTR3:
935 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
936 "0x%x data 0x%llx\n", msr, data);
937 break;
15c4a640 938 default:
ed85c068
AP		 939 if (!ignore_msrs) {
940 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
941 msr, data);
942 return 1;
943 } else {
944 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
945 msr, data);
946 break;
947 }
15c4a640
CO		 948 }
949 return 0;
950}
951EXPORT_SYMBOL_GPL(kvm_set_msr_common);
952
953
954/*
955 * Reads an msr value (of 'msr_index') into 'pdata'.
956 * Returns 0 on success, non-0 otherwise.
957 * Assumes vcpu_load() was already called.
958 */
959int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
960{
961 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
962}
963
9ba075a6
AK		 964static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
965{
0bed3b56
SY		 966 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
967
9ba075a6
AK		 968 if (!msr_mtrr_valid(msr))
969 return 1;
970
0bed3b56
SY		 971 if (msr == MSR_MTRRdefType)
972 *pdata = vcpu->arch.mtrr_state.def_type +
973 (vcpu->arch.mtrr_state.enabled << 10);
974 else if (msr == MSR_MTRRfix64K_00000)
975 *pdata = p[0];
976 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
977 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
978 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
979 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
980 else if (msr == MSR_IA32_CR_PAT)
981 *pdata = vcpu->arch.pat;
982 else { /* Variable MTRRs */
983 int idx, is_mtrr_mask;
984 u64 *pt;
985
986 idx = (msr - 0x200) / 2;
987 is_mtrr_mask = msr - 0x200 - 2 * idx;
988 if (!is_mtrr_mask)
989 pt =
990 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
991 else
992 pt =
993 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
994 *pdata = *pt;
995 }
996
9ba075a6
AK		 997 return 0;
998}
999
890ca9ae 1000static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1001{
1002 u64 data;
890ca9ae
HY		 1003 u64 mcg_cap = vcpu->arch.mcg_cap;
1004 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1005
1006 switch (msr) {
15c4a640
CO		 1007 case MSR_IA32_P5_MC_ADDR:
1008 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1009 data = 0;
1010 break;
15c4a640 1011 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1012 data = vcpu->arch.mcg_cap;
1013 break;
c7ac679c 1014 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1015 if (!(mcg_cap & MCG_CTL_P))
1016 return 1;
1017 data = vcpu->arch.mcg_ctl;
1018 break;
1019 case MSR_IA32_MCG_STATUS:
1020 data = vcpu->arch.mcg_status;
1021 break;
1022 default:
1023 if (msr >= MSR_IA32_MC0_CTL &&
1024 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1025 u32 offset = msr - MSR_IA32_MC0_CTL;
1026 data = vcpu->arch.mce_banks[offset];
1027 break;
1028 }
1029 return 1;
1030 }
1031 *pdata = data;
1032 return 0;
1033}
1034
1035int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1036{
1037 u64 data;
1038
1039 switch (msr) {
890ca9ae 1040 case MSR_IA32_PLATFORM_ID:
15c4a640 1041 case MSR_IA32_UCODE_REV:
15c4a640 1042 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1043 case MSR_IA32_DEBUGCTLMSR:
1044 case MSR_IA32_LASTBRANCHFROMIP:
1045 case MSR_IA32_LASTBRANCHTOIP:
1046 case MSR_IA32_LASTINTFROMIP:
1047 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1048 case MSR_K8_SYSCFG:
1049 case MSR_K7_HWCR:
61a6bd67 1050 case MSR_VM_HSAVE_PA:
7fe29e0f
AS		 1051 case MSR_P6_EVNTSEL0:
1052 case MSR_P6_EVNTSEL1:
9e699624 1053 case MSR_K7_EVNTSEL0:
1fdbd48c 1054 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1055 case MSR_AMD64_NB_CFG:
f7c6d140 1056 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1057 data = 0;
1058 break;
9ba075a6
AK		 1059 case MSR_MTRRcap:
1060 data = 0x500 | KVM_NR_VAR_MTRR;
1061 break;
1062 case 0x200 ... 0x2ff:
1063 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1064 case 0xcd: /* fsb frequency */
1065 data = 3;
1066 break;
1067 case MSR_IA32_APICBASE:
1068 data = kvm_get_apic_base(vcpu);
1069 break;
0105d1a5
GN		 1070 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1071 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1072 break;
15c4a640 1073 case MSR_IA32_MISC_ENABLE:
ad312c7c 1074 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1075 break;
847f0ad8
AG		 1076 case MSR_IA32_PERF_STATUS:
1077 /* TSC increment by tick */
1078 data = 1000ULL;
1079 /* CPU multiplier */
1080 data |= (((uint64_t)4ULL) << 40);
1081 break;
15c4a640 1082 case MSR_EFER:
ad312c7c 1083 data = vcpu->arch.shadow_efer;
15c4a640 1084 break;
18068523
GOC		 1085 case MSR_KVM_WALL_CLOCK:
1086 data = vcpu->kvm->arch.wall_clock;
1087 break;
1088 case MSR_KVM_SYSTEM_TIME:
1089 data = vcpu->arch.time;
1090 break;
890ca9ae
HY		 1091 case MSR_IA32_P5_MC_ADDR:
1092 case MSR_IA32_P5_MC_TYPE:
1093 case MSR_IA32_MCG_CAP:
1094 case MSR_IA32_MCG_CTL:
1095 case MSR_IA32_MCG_STATUS:
1096 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1097 return get_msr_mce(vcpu, msr, pdata);
15c4a640 1098 default:
ed85c068
AP		 1099 if (!ignore_msrs) {
1100 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1101 return 1;
1102 } else {
1103 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1104 data = 0;
1105 }
1106 break;
15c4a640
CO		 1107 }
1108 *pdata = data;
1109 return 0;
1110}
1111EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1112
313a3dc7
CO		 1113/*
1114 * Read or write a bunch of msrs. All parameters are kernel addresses.
1115 *
1116 * @return number of msrs set successfully.
1117 */
1118static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1119 struct kvm_msr_entry *entries,
1120 int (*do_msr)(struct kvm_vcpu *vcpu,
1121 unsigned index, u64 *data))
1122{
1123 int i;
1124
1125 vcpu_load(vcpu);
1126
3200f405 1127 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1128 for (i = 0; i < msrs->nmsrs; ++i)
1129 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1130 break;
3200f405 1131 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1132
1133 vcpu_put(vcpu);
1134
1135 return i;
1136}
1137
1138/*
1139 * Read or write a bunch of msrs. Parameters are user addresses.
1140 *
1141 * @return number of msrs set successfully.
1142 */
1143static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1144 int (*do_msr)(struct kvm_vcpu *vcpu,
1145 unsigned index, u64 *data),
1146 int writeback)
1147{
1148 struct kvm_msrs msrs;
1149 struct kvm_msr_entry *entries;
1150 int r, n;
1151 unsigned size;
1152
1153 r = -EFAULT;
1154 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1155 goto out;
1156
1157 r = -E2BIG;
1158 if (msrs.nmsrs >= MAX_IO_MSRS)
1159 goto out;
1160
1161 r = -ENOMEM;
1162 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1163 entries = vmalloc(size);
1164 if (!entries)
1165 goto out;
1166
1167 r = -EFAULT;
1168 if (copy_from_user(entries, user_msrs->entries, size))
1169 goto out_free;
1170
1171 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1172 if (r < 0)
1173 goto out_free;
1174
1175 r = -EFAULT;
1176 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1177 goto out_free;
1178
1179 r = n;
1180
1181out_free:
1182 vfree(entries);
1183out:
1184 return r;
1185}
1186
018d00d2
ZX		 1187int kvm_dev_ioctl_check_extension(long ext)
1188{
1189 int r;
1190
1191 switch (ext) {
1192 case KVM_CAP_IRQCHIP:
1193 case KVM_CAP_HLT:
1194 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1195 case KVM_CAP_SET_TSS_ADDR:
07716717 1196 case KVM_CAP_EXT_CPUID:
c8076604 1197 case KVM_CAP_CLOCKSOURCE:
7837699f 1198 case KVM_CAP_PIT:
a28e4f5a 1199 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1200 case KVM_CAP_MP_STATE:
ed848624 1201 case KVM_CAP_SYNC_MMU:
52d939a0 1202 case KVM_CAP_REINJECT_CONTROL:
4925663a 1203 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1204 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1205 case KVM_CAP_IRQFD:
d34e6b17 1206 case KVM_CAP_IOEVENTFD:
c5ff41ce 1207 case KVM_CAP_PIT2:
e9f42757 1208 case KVM_CAP_PIT_STATE2:
b927a3ce 1209 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
018d00d2
ZX		 1210 r = 1;
1211 break;
542472b5
LV		 1212 case KVM_CAP_COALESCED_MMIO:
1213 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1214 break;
774ead3a
AK		 1215 case KVM_CAP_VAPIC:
1216 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1217 break;
f725230a
AK		 1218 case KVM_CAP_NR_VCPUS:
1219 r = KVM_MAX_VCPUS;
1220 break;
a988b910
AK		 1221 case KVM_CAP_NR_MEMSLOTS:
1222 r = KVM_MEMORY_SLOTS;
1223 break;
2f333bcb
MT		 1224 case KVM_CAP_PV_MMU:
1225 r = !tdp_enabled;
1226 break;
62c476c7 1227 case KVM_CAP_IOMMU:
19de40a8 1228 r = iommu_found();
62c476c7 1229 break;
890ca9ae
HY		 1230 case KVM_CAP_MCE:
1231 r = KVM_MAX_MCE_BANKS;
1232 break;
018d00d2
ZX		 1233 default:
1234 r = 0;
1235 break;
1236 }
1237 return r;
1238
1239}
1240
043405e1
CO		 1241long kvm_arch_dev_ioctl(struct file *filp,
1242 unsigned int ioctl, unsigned long arg)
1243{
1244 void __user *argp = (void __user *)arg;
1245 long r;
1246
1247 switch (ioctl) {
1248 case KVM_GET_MSR_INDEX_LIST: {
1249 struct kvm_msr_list __user *user_msr_list = argp;
1250 struct kvm_msr_list msr_list;
1251 unsigned n;
1252
1253 r = -EFAULT;
1254 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1255 goto out;
1256 n = msr_list.nmsrs;
1257 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1258 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1259 goto out;
1260 r = -E2BIG;
e125e7b6 1261 if (n < msr_list.nmsrs)
043405e1
CO		 1262 goto out;
1263 r = -EFAULT;
1264 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1265 num_msrs_to_save * sizeof(u32)))
1266 goto out;
e125e7b6 1267 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1268 &emulated_msrs,
1269 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1270 goto out;
1271 r = 0;
1272 break;
1273 }
674eea0f
AK		 1274 case KVM_GET_SUPPORTED_CPUID: {
1275 struct kvm_cpuid2 __user *cpuid_arg = argp;
1276 struct kvm_cpuid2 cpuid;
1277
1278 r = -EFAULT;
1279 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1280 goto out;
1281 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1282 cpuid_arg->entries);
674eea0f
AK		 1283 if (r)
1284 goto out;
1285
1286 r = -EFAULT;
1287 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1288 goto out;
1289 r = 0;
1290 break;
1291 }
890ca9ae
HY		 1292 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1293 u64 mce_cap;
1294
1295 mce_cap = KVM_MCE_CAP_SUPPORTED;
1296 r = -EFAULT;
1297 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1298 goto out;
1299 r = 0;
1300 break;
1301 }
043405e1
CO		 1302 default:
1303 r = -EINVAL;
1304 }
1305out:
1306 return r;
1307}
1308
313a3dc7
CO		 1309void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1310{
1311 kvm_x86_ops->vcpu_load(vcpu, cpu);
c8076604 1312 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1313}
1314
1315void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1316{
1317 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1318 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1319}
1320
07716717 1321static int is_efer_nx(void)
313a3dc7 1322{
e286e86e 1323 unsigned long long efer = 0;
313a3dc7 1324
e286e86e 1325 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1326 return efer & EFER_NX;
1327}
1328
1329static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1330{
1331 int i;
1332 struct kvm_cpuid_entry2 *e, *entry;
1333
313a3dc7 1334 entry = NULL;
ad312c7c
ZX		 1335 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1336 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1337 if (e->function == 0x80000001) {
1338 entry = e;
1339 break;
1340 }
1341 }
07716717 1342 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1343 entry->edx &= ~(1 << 20);
1344 printk(KERN_INFO "kvm: guest NX capability removed\n");
1345 }
1346}
1347
07716717 1348/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1349static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1350 struct kvm_cpuid *cpuid,
1351 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1352{
1353 int r, i;
1354 struct kvm_cpuid_entry *cpuid_entries;
1355
1356 r = -E2BIG;
1357 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1358 goto out;
1359 r = -ENOMEM;
1360 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1361 if (!cpuid_entries)
1362 goto out;
1363 r = -EFAULT;
1364 if (copy_from_user(cpuid_entries, entries,
1365 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1366 goto out_free;
1367 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1368 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1369 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1370 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1371 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1372 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1373 vcpu->arch.cpuid_entries[i].index = 0;
1374 vcpu->arch.cpuid_entries[i].flags = 0;
1375 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1376 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1377 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1378 }
1379 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1380 cpuid_fix_nx_cap(vcpu);
1381 r = 0;
fc61b800 1382 kvm_apic_set_version(vcpu);
07716717
DK		 1383
1384out_free:
1385 vfree(cpuid_entries);
1386out:
1387 return r;
1388}
1389
1390static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1391 struct kvm_cpuid2 *cpuid,
1392 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1393{
1394 int r;
1395
1396 r = -E2BIG;
1397 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1398 goto out;
1399 r = -EFAULT;
ad312c7c 1400 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1401 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1402 goto out;
ad312c7c 1403 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1404 kvm_apic_set_version(vcpu);
313a3dc7
CO		 1405 return 0;
1406
1407out:
1408 return r;
1409}
1410
07716717 1411static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1412 struct kvm_cpuid2 *cpuid,
1413 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1414{
1415 int r;
1416
1417 r = -E2BIG;
ad312c7c 1418 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1419 goto out;
1420 r = -EFAULT;
ad312c7c 1421 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1422 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1423 goto out;
1424 return 0;
1425
1426out:
ad312c7c 1427 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1428 return r;
1429}
1430
07716717 1431static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1432 u32 index)
07716717
DK		 1433{
1434 entry->function = function;
1435 entry->index = index;
1436 cpuid_count(entry->function, entry->index,
19355475 1437 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1438 entry->flags = 0;
1439}
1440
7faa4ee1
AK		 1441#define F(x) bit(X86_FEATURE_##x)
1442
07716717
DK		 1443static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1444 u32 index, int *nent, int maxnent)
1445{
7faa4ee1 1446 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1447#ifdef CONFIG_X86_64
7faa4ee1
AK		 1448 unsigned f_lm = F(LM);
1449#else
1450 unsigned f_lm = 0;
07716717 1451#endif
7faa4ee1
AK		 1452
1453 /* cpuid 1.edx */
1454 const u32 kvm_supported_word0_x86_features =
1455 F(FPU) | F(VME) | F(DE) | F(PSE) |
1456 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1457 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1458 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1459 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1460 0 /* Reserved, DS, ACPI */ | F(MMX) |
1461 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1462 0 /* HTT, TM, Reserved, PBE */;
1463 /* cpuid 0x80000001.edx */
1464 const u32 kvm_supported_word1_x86_features =
1465 F(FPU) | F(VME) | F(DE) | F(PSE) |
1466 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1467 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1468 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1469 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1470 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
1471 F(FXSR) | F(FXSR_OPT) | 0 /* GBPAGES */ | 0 /* RDTSCP */ |
1472 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1473 /* cpuid 1.ecx */
1474 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1475 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1476 0 /* DS-CPL, VMX, SMX, EST */ |
1477 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1478 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1479 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1480 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1481 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1482 /* cpuid 0x80000001.ecx */
07716717 1483 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1484 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1485 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1486 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1487 0 /* SKINIT */ | 0 /* WDT */;
07716717 1488
19355475 1489 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1490 get_cpu();
1491 do_cpuid_1_ent(entry, function, index);
1492 ++*nent;
1493
1494 switch (function) {
1495 case 0:
1496 entry->eax = min(entry->eax, (u32)0xb);
1497 break;
1498 case 1:
1499 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1500 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1501 /* we support x2apic emulation even if host does not support
1502 * it since we emulate x2apic in software */
1503 entry->ecx |= F(X2APIC);
07716717
DK		 1504 break;
1505 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1506 * may return different values. This forces us to get_cpu() before
1507 * issuing the first command, and also to emulate this annoying behavior
1508 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1509 case 2: {
1510 int t, times = entry->eax & 0xff;
1511
1512 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1513 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1514 for (t = 1; t < times && *nent < maxnent; ++t) {
1515 do_cpuid_1_ent(&entry[t], function, 0);
1516 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1517 ++*nent;
1518 }
1519 break;
1520 }
1521 /* function 4 and 0xb have additional index. */
1522 case 4: {
14af3f3c 1523 int i, cache_type;
07716717
DK		 1524
1525 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1526 /* read more entries until cache_type is zero */
14af3f3c
HH		 1527 for (i = 1; *nent < maxnent; ++i) {
1528 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1529 if (!cache_type)
1530 break;
14af3f3c
HH		 1531 do_cpuid_1_ent(&entry[i], function, i);
1532 entry[i].flags |=
07716717
DK		 1533 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1534 ++*nent;
1535 }
1536 break;
1537 }
1538 case 0xb: {
14af3f3c 1539 int i, level_type;
07716717
DK		 1540
1541 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1542 /* read more entries until level_type is zero */
14af3f3c 1543 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1544 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1545 if (!level_type)
1546 break;
14af3f3c
HH		 1547 do_cpuid_1_ent(&entry[i], function, i);
1548 entry[i].flags |=
07716717
DK		 1549 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1550 ++*nent;
1551 }
1552 break;
1553 }
1554 case 0x80000000:
1555 entry->eax = min(entry->eax, 0x8000001a);
1556 break;
1557 case 0x80000001:
1558 entry->edx &= kvm_supported_word1_x86_features;
1559 entry->ecx &= kvm_supported_word6_x86_features;
1560 break;
1561 }
1562 put_cpu();
1563}
1564
7faa4ee1
AK		 1565#undef F
1566
674eea0f 1567static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1568 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1569{
1570 struct kvm_cpuid_entry2 *cpuid_entries;
1571 int limit, nent = 0, r = -E2BIG;
1572 u32 func;
1573
1574 if (cpuid->nent < 1)
1575 goto out;
1576 r = -ENOMEM;
1577 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1578 if (!cpuid_entries)
1579 goto out;
1580
1581 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1582 limit = cpuid_entries[0].eax;
1583 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1584 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1585 &nent, cpuid->nent);
07716717
DK		 1586 r = -E2BIG;
1587 if (nent >= cpuid->nent)
1588 goto out_free;
1589
1590 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1591 limit = cpuid_entries[nent - 1].eax;
1592 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1593 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1594 &nent, cpuid->nent);
cb007648
MM		 1595 r = -E2BIG;
1596 if (nent >= cpuid->nent)
1597 goto out_free;
1598
07716717
DK		 1599 r = -EFAULT;
1600 if (copy_to_user(entries, cpuid_entries,
19355475 1601 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1602 goto out_free;
1603 cpuid->nent = nent;
1604 r = 0;
1605
1606out_free:
1607 vfree(cpuid_entries);
1608out:
1609 return r;
1610}
1611
313a3dc7
CO		 1612static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1613 struct kvm_lapic_state *s)
1614{
1615 vcpu_load(vcpu);
ad312c7c 1616 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1617 vcpu_put(vcpu);
1618
1619 return 0;
1620}
1621
1622static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1623 struct kvm_lapic_state *s)
1624{
1625 vcpu_load(vcpu);
ad312c7c 1626 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1627 kvm_apic_post_state_restore(vcpu);
1628 vcpu_put(vcpu);
1629
1630 return 0;
1631}
1632
f77bc6a4
ZX		 1633static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1634 struct kvm_interrupt *irq)
1635{
1636 if (irq->irq < 0 || irq->irq >= 256)
1637 return -EINVAL;
1638 if (irqchip_in_kernel(vcpu->kvm))
1639 return -ENXIO;
1640 vcpu_load(vcpu);
1641
66fd3f7f 1642 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1643
1644 vcpu_put(vcpu);
1645
1646 return 0;
1647}
1648
c4abb7c9
JK		 1649static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1650{
1651 vcpu_load(vcpu);
1652 kvm_inject_nmi(vcpu);
1653 vcpu_put(vcpu);
1654
1655 return 0;
1656}
1657
b209749f
AK		 1658static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1659 struct kvm_tpr_access_ctl *tac)
1660{
1661 if (tac->flags)
1662 return -EINVAL;
1663 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1664 return 0;
1665}
1666
890ca9ae
HY		 1667static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1668 u64 mcg_cap)
1669{
1670 int r;
1671 unsigned bank_num = mcg_cap & 0xff, bank;
1672
1673 r = -EINVAL;
1674 if (!bank_num)
1675 goto out;
1676 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1677 goto out;
1678 r = 0;
1679 vcpu->arch.mcg_cap = mcg_cap;
1680 /* Init IA32_MCG_CTL to all 1s */
1681 if (mcg_cap & MCG_CTL_P)
1682 vcpu->arch.mcg_ctl = ~(u64)0;
1683 /* Init IA32_MCi_CTL to all 1s */
1684 for (bank = 0; bank < bank_num; bank++)
1685 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1686out:
1687 return r;
1688}
1689
1690static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1691 struct kvm_x86_mce *mce)
1692{
1693 u64 mcg_cap = vcpu->arch.mcg_cap;
1694 unsigned bank_num = mcg_cap & 0xff;
1695 u64 *banks = vcpu->arch.mce_banks;
1696
1697 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1698 return -EINVAL;
1699 /*
1700 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1701 * reporting is disabled
1702 */
1703 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1704 vcpu->arch.mcg_ctl != ~(u64)0)
1705 return 0;
1706 banks += 4 * mce->bank;
1707 /*
1708 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1709 * reporting is disabled for the bank
1710 */
1711 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1712 return 0;
1713 if (mce->status & MCI_STATUS_UC) {
1714 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
1715 !(vcpu->arch.cr4 & X86_CR4_MCE)) {
1716 printk(KERN_DEBUG "kvm: set_mce: "
1717 "injects mce exception while "
1718 "previous one is in progress!\n");
1719 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1720 return 0;
1721 }
1722 if (banks[1] & MCI_STATUS_VAL)
1723 mce->status |= MCI_STATUS_OVER;
1724 banks[2] = mce->addr;
1725 banks[3] = mce->misc;
1726 vcpu->arch.mcg_status = mce->mcg_status;
1727 banks[1] = mce->status;
1728 kvm_queue_exception(vcpu, MC_VECTOR);
1729 } else if (!(banks[1] & MCI_STATUS_VAL)
1730 || !(banks[1] & MCI_STATUS_UC)) {
1731 if (banks[1] & MCI_STATUS_VAL)
1732 mce->status |= MCI_STATUS_OVER;
1733 banks[2] = mce->addr;
1734 banks[3] = mce->misc;
1735 banks[1] = mce->status;
1736 } else
1737 banks[1] |= MCI_STATUS_OVER;
1738 return 0;
1739}
1740
313a3dc7
CO		 1741long kvm_arch_vcpu_ioctl(struct file *filp,
1742 unsigned int ioctl, unsigned long arg)
1743{
1744 struct kvm_vcpu *vcpu = filp->private_data;
1745 void __user *argp = (void __user *)arg;
1746 int r;
b772ff36 1747 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1748
1749 switch (ioctl) {
1750 case KVM_GET_LAPIC: {
b772ff36 1751 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1752
b772ff36
DH		 1753 r = -ENOMEM;
1754 if (!lapic)
1755 goto out;
1756 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1757 if (r)
1758 goto out;
1759 r = -EFAULT;
b772ff36 1760 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1761 goto out;
1762 r = 0;
1763 break;
1764 }
1765 case KVM_SET_LAPIC: {
b772ff36
DH		 1766 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1767 r = -ENOMEM;
1768 if (!lapic)
1769 goto out;
313a3dc7 1770 r = -EFAULT;
b772ff36 1771 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1772 goto out;
b772ff36 1773 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1774 if (r)
1775 goto out;
1776 r = 0;
1777 break;
1778 }
f77bc6a4
ZX		 1779 case KVM_INTERRUPT: {
1780 struct kvm_interrupt irq;
1781
1782 r = -EFAULT;
1783 if (copy_from_user(&irq, argp, sizeof irq))
1784 goto out;
1785 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1786 if (r)
1787 goto out;
1788 r = 0;
1789 break;
1790 }
c4abb7c9
JK		 1791 case KVM_NMI: {
1792 r = kvm_vcpu_ioctl_nmi(vcpu);
1793 if (r)
1794 goto out;
1795 r = 0;
1796 break;
1797 }
313a3dc7
CO		 1798 case KVM_SET_CPUID: {
1799 struct kvm_cpuid __user *cpuid_arg = argp;
1800 struct kvm_cpuid cpuid;
1801
1802 r = -EFAULT;
1803 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1804 goto out;
1805 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1806 if (r)
1807 goto out;
1808 break;
1809 }
07716717
DK		 1810 case KVM_SET_CPUID2: {
1811 struct kvm_cpuid2 __user *cpuid_arg = argp;
1812 struct kvm_cpuid2 cpuid;
1813
1814 r = -EFAULT;
1815 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1816 goto out;
1817 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 1818 cpuid_arg->entries);
07716717
DK		 1819 if (r)
1820 goto out;
1821 break;
1822 }
1823 case KVM_GET_CPUID2: {
1824 struct kvm_cpuid2 __user *cpuid_arg = argp;
1825 struct kvm_cpuid2 cpuid;
1826
1827 r = -EFAULT;
1828 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1829 goto out;
1830 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 1831 cpuid_arg->entries);
07716717
DK		 1832 if (r)
1833 goto out;
1834 r = -EFAULT;
1835 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1836 goto out;
1837 r = 0;
1838 break;
1839 }
313a3dc7
CO		 1840 case KVM_GET_MSRS:
1841 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1842 break;
1843 case KVM_SET_MSRS:
1844 r = msr_io(vcpu, argp, do_set_msr, 0);
1845 break;
b209749f
AK		 1846 case KVM_TPR_ACCESS_REPORTING: {
1847 struct kvm_tpr_access_ctl tac;
1848
1849 r = -EFAULT;
1850 if (copy_from_user(&tac, argp, sizeof tac))
1851 goto out;
1852 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1853 if (r)
1854 goto out;
1855 r = -EFAULT;
1856 if (copy_to_user(argp, &tac, sizeof tac))
1857 goto out;
1858 r = 0;
1859 break;
1860 };
b93463aa
AK		 1861 case KVM_SET_VAPIC_ADDR: {
1862 struct kvm_vapic_addr va;
1863
1864 r = -EINVAL;
1865 if (!irqchip_in_kernel(vcpu->kvm))
1866 goto out;
1867 r = -EFAULT;
1868 if (copy_from_user(&va, argp, sizeof va))
1869 goto out;
1870 r = 0;
1871 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1872 break;
1873 }
890ca9ae
HY		 1874 case KVM_X86_SETUP_MCE: {
1875 u64 mcg_cap;
1876
1877 r = -EFAULT;
1878 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
1879 goto out;
1880 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
1881 break;
1882 }
1883 case KVM_X86_SET_MCE: {
1884 struct kvm_x86_mce mce;
1885
1886 r = -EFAULT;
1887 if (copy_from_user(&mce, argp, sizeof mce))
1888 goto out;
1889 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
1890 break;
1891 }
313a3dc7
CO		 1892 default:
1893 r = -EINVAL;
1894 }
1895out:
7a6ce84c 1896 kfree(lapic);
313a3dc7
CO		 1897 return r;
1898}
1899
1fe779f8
CO		 1900static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1901{
1902 int ret;
1903
1904 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1905 return -1;
1906 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1907 return ret;
1908}
1909
b927a3ce
SY		 1910static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
1911 u64 ident_addr)
1912{
1913 kvm->arch.ept_identity_map_addr = ident_addr;
1914 return 0;
1915}
1916
1fe779f8
CO		 1917static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1918 u32 kvm_nr_mmu_pages)
1919{
1920 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1921 return -EINVAL;
1922
72dc67a6 1923 down_write(&kvm->slots_lock);
7c8a83b7 1924 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 1925
1926 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1927 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1928
7c8a83b7 1929 spin_unlock(&kvm->mmu_lock);
72dc67a6 1930 up_write(&kvm->slots_lock);
1fe779f8
CO		 1931 return 0;
1932}
1933
1934static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1935{
f05e70ac 1936 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1937}
1938
e9f85cde
ZX		 1939gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1940{
1941 int i;
1942 struct kvm_mem_alias *alias;
1943
d69fb81f
ZX		 1944 for (i = 0; i < kvm->arch.naliases; ++i) {
1945 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1946 if (gfn >= alias->base_gfn
1947 && gfn < alias->base_gfn + alias->npages)
1948 return alias->target_gfn + gfn - alias->base_gfn;
1949 }
1950 return gfn;
1951}
1952
1fe779f8
CO		 1953/*
1954 * Set a new alias region. Aliases map a portion of physical memory into
1955 * another portion. This is useful for memory windows, for example the PC
1956 * VGA region.
1957 */
1958static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1959 struct kvm_memory_alias *alias)
1960{
1961 int r, n;
1962 struct kvm_mem_alias *p;
1963
1964 r = -EINVAL;
1965 /* General sanity checks */
1966 if (alias->memory_size & (PAGE_SIZE - 1))
1967 goto out;
1968 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1969 goto out;
1970 if (alias->slot >= KVM_ALIAS_SLOTS)
1971 goto out;
1972 if (alias->guest_phys_addr + alias->memory_size
1973 < alias->guest_phys_addr)
1974 goto out;
1975 if (alias->target_phys_addr + alias->memory_size
1976 < alias->target_phys_addr)
1977 goto out;
1978
72dc67a6 1979 down_write(&kvm->slots_lock);
a1708ce8 1980 spin_lock(&kvm->mmu_lock);
1fe779f8 1981
d69fb81f 1982 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1983 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1984 p->npages = alias->memory_size >> PAGE_SHIFT;
1985 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1986
1987 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1988 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1989 break;
d69fb81f 1990 kvm->arch.naliases = n;
1fe779f8 1991
a1708ce8 1992 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1993 kvm_mmu_zap_all(kvm);
1994
72dc67a6 1995 up_write(&kvm->slots_lock);
1fe779f8
CO		 1996
1997 return 0;
1998
1999out:
2000 return r;
2001}
2002
2003static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2004{
2005 int r;
2006
2007 r = 0;
2008 switch (chip->chip_id) {
2009 case KVM_IRQCHIP_PIC_MASTER:
2010 memcpy(&chip->chip.pic,
2011 &pic_irqchip(kvm)->pics[0],
2012 sizeof(struct kvm_pic_state));
2013 break;
2014 case KVM_IRQCHIP_PIC_SLAVE:
2015 memcpy(&chip->chip.pic,
2016 &pic_irqchip(kvm)->pics[1],
2017 sizeof(struct kvm_pic_state));
2018 break;
2019 case KVM_IRQCHIP_IOAPIC:
2020 memcpy(&chip->chip.ioapic,
2021 ioapic_irqchip(kvm),
2022 sizeof(struct kvm_ioapic_state));
2023 break;
2024 default:
2025 r = -EINVAL;
2026 break;
2027 }
2028 return r;
2029}
2030
2031static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2032{
2033 int r;
2034
2035 r = 0;
2036 switch (chip->chip_id) {
2037 case KVM_IRQCHIP_PIC_MASTER:
894a9c55 2038 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2039 memcpy(&pic_irqchip(kvm)->pics[0],
2040 &chip->chip.pic,
2041 sizeof(struct kvm_pic_state));
894a9c55 2042 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2043 break;
2044 case KVM_IRQCHIP_PIC_SLAVE:
894a9c55 2045 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2046 memcpy(&pic_irqchip(kvm)->pics[1],
2047 &chip->chip.pic,
2048 sizeof(struct kvm_pic_state));
894a9c55 2049 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2050 break;
2051 case KVM_IRQCHIP_IOAPIC:
894a9c55 2052 mutex_lock(&kvm->irq_lock);
1fe779f8
CO		 2053 memcpy(ioapic_irqchip(kvm),
2054 &chip->chip.ioapic,
2055 sizeof(struct kvm_ioapic_state));
894a9c55 2056 mutex_unlock(&kvm->irq_lock);
1fe779f8
CO		 2057 break;
2058 default:
2059 r = -EINVAL;
2060 break;
2061 }
2062 kvm_pic_update_irq(pic_irqchip(kvm));
2063 return r;
2064}
2065
e0f63cb9
SY		 2066static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2067{
2068 int r = 0;
2069
894a9c55 2070 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2071 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2072 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2073 return r;
2074}
2075
2076static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2077{
2078 int r = 0;
2079
894a9c55 2080 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2081 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2082 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2083 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2084 return r;
2085}
2086
2087static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2088{
2089 int r = 0;
2090
2091 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2092 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2093 sizeof(ps->channels));
2094 ps->flags = kvm->arch.vpit->pit_state.flags;
2095 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2096 return r;
2097}
2098
2099static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2100{
2101 int r = 0, start = 0;
2102 u32 prev_legacy, cur_legacy;
2103 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2104 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2105 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2106 if (!prev_legacy && cur_legacy)
2107 start = 1;
2108 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2109 sizeof(kvm->arch.vpit->pit_state.channels));
2110 kvm->arch.vpit->pit_state.flags = ps->flags;
2111 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2112 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2113 return r;
2114}
2115
52d939a0
MT		 2116static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2117 struct kvm_reinject_control *control)
2118{
2119 if (!kvm->arch.vpit)
2120 return -ENXIO;
894a9c55 2121 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2122 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2123 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2124 return 0;
2125}
2126
5bb064dc
ZX		 2127/*
2128 * Get (and clear) the dirty memory log for a memory slot.
2129 */
2130int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2131 struct kvm_dirty_log *log)
2132{
2133 int r;
2134 int n;
2135 struct kvm_memory_slot *memslot;
2136 int is_dirty = 0;
2137
72dc67a6 2138 down_write(&kvm->slots_lock);
5bb064dc
ZX		 2139
2140 r = kvm_get_dirty_log(kvm, log, &is_dirty);
2141 if (r)
2142 goto out;
2143
2144 /* If nothing is dirty, don't bother messing with page tables. */
2145 if (is_dirty) {
7c8a83b7 2146 spin_lock(&kvm->mmu_lock);
5bb064dc 2147 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2148 spin_unlock(&kvm->mmu_lock);
5bb064dc
ZX		 2149 kvm_flush_remote_tlbs(kvm);
2150 memslot = &kvm->memslots[log->slot];
2151 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2152 memset(memslot->dirty_bitmap, 0, n);
2153 }
2154 r = 0;
2155out:
72dc67a6 2156 up_write(&kvm->slots_lock);
5bb064dc
ZX		 2157 return r;
2158}
2159
1fe779f8
CO		 2160long kvm_arch_vm_ioctl(struct file *filp,
2161 unsigned int ioctl, unsigned long arg)
2162{
2163 struct kvm *kvm = filp->private_data;
2164 void __user *argp = (void __user *)arg;
2165 int r = -EINVAL;
f0d66275
DH		 2166 /*
2167 * This union makes it completely explicit to gcc-3.x
2168 * that these two variables' stack usage should be
2169 * combined, not added together.
2170 */
2171 union {
2172 struct kvm_pit_state ps;
e9f42757 2173 struct kvm_pit_state2 ps2;
f0d66275 2174 struct kvm_memory_alias alias;
c5ff41ce 2175 struct kvm_pit_config pit_config;
f0d66275 2176 } u;
1fe779f8
CO		 2177
2178 switch (ioctl) {
2179 case KVM_SET_TSS_ADDR:
2180 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2181 if (r < 0)
2182 goto out;
2183 break;
b927a3ce
SY		 2184 case KVM_SET_IDENTITY_MAP_ADDR: {
2185 u64 ident_addr;
2186
2187 r = -EFAULT;
2188 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2189 goto out;
2190 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2191 if (r < 0)
2192 goto out;
2193 break;
2194 }
1fe779f8
CO		 2195 case KVM_SET_MEMORY_REGION: {
2196 struct kvm_memory_region kvm_mem;
2197 struct kvm_userspace_memory_region kvm_userspace_mem;
2198
2199 r = -EFAULT;
2200 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2201 goto out;
2202 kvm_userspace_mem.slot = kvm_mem.slot;
2203 kvm_userspace_mem.flags = kvm_mem.flags;
2204 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2205 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2206 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2207 if (r)
2208 goto out;
2209 break;
2210 }
2211 case KVM_SET_NR_MMU_PAGES:
2212 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2213 if (r)
2214 goto out;
2215 break;
2216 case KVM_GET_NR_MMU_PAGES:
2217 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2218 break;
f0d66275 2219 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2220 r = -EFAULT;
f0d66275 2221 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2222 goto out;
f0d66275 2223 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2224 if (r)
2225 goto out;
2226 break;
1fe779f8
CO		 2227 case KVM_CREATE_IRQCHIP:
2228 r = -ENOMEM;
d7deeeb0
ZX		 2229 kvm->arch.vpic = kvm_create_pic(kvm);
2230 if (kvm->arch.vpic) {
1fe779f8
CO		 2231 r = kvm_ioapic_init(kvm);
2232 if (r) {
d7deeeb0
ZX		 2233 kfree(kvm->arch.vpic);
2234 kvm->arch.vpic = NULL;
1fe779f8
CO		 2235 goto out;
2236 }
2237 } else
2238 goto out;
399ec807
AK		 2239 r = kvm_setup_default_irq_routing(kvm);
2240 if (r) {
2241 kfree(kvm->arch.vpic);
2242 kfree(kvm->arch.vioapic);
2243 goto out;
2244 }
1fe779f8 2245 break;
7837699f 2246 case KVM_CREATE_PIT:
c5ff41ce
JK		 2247 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2248 goto create_pit;
2249 case KVM_CREATE_PIT2:
2250 r = -EFAULT;
2251 if (copy_from_user(&u.pit_config, argp,
2252 sizeof(struct kvm_pit_config)))
2253 goto out;
2254 create_pit:
108b5669 2255 down_write(&kvm->slots_lock);
269e05e4
AK		 2256 r = -EEXIST;
2257 if (kvm->arch.vpit)
2258 goto create_pit_unlock;
7837699f 2259 r = -ENOMEM;
c5ff41ce 2260 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2261 if (kvm->arch.vpit)
2262 r = 0;
269e05e4 2263 create_pit_unlock:
108b5669 2264 up_write(&kvm->slots_lock);
7837699f 2265 break;
4925663a 2266 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2267 case KVM_IRQ_LINE: {
2268 struct kvm_irq_level irq_event;
2269
2270 r = -EFAULT;
2271 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2272 goto out;
2273 if (irqchip_in_kernel(kvm)) {
4925663a 2274 __s32 status;
fa40a821 2275 mutex_lock(&kvm->irq_lock);
4925663a
GN		 2276 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2277 irq_event.irq, irq_event.level);
fa40a821 2278 mutex_unlock(&kvm->irq_lock);
4925663a
GN		 2279 if (ioctl == KVM_IRQ_LINE_STATUS) {
2280 irq_event.status = status;
2281 if (copy_to_user(argp, &irq_event,
2282 sizeof irq_event))
2283 goto out;
2284 }
1fe779f8
CO		 2285 r = 0;
2286 }
2287 break;
2288 }
2289 case KVM_GET_IRQCHIP: {
2290 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2291 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2292
f0d66275
DH		 2293 r = -ENOMEM;
2294 if (!chip)
1fe779f8 2295 goto out;
f0d66275
DH		 2296 r = -EFAULT;
2297 if (copy_from_user(chip, argp, sizeof *chip))
2298 goto get_irqchip_out;
1fe779f8
CO		 2299 r = -ENXIO;
2300 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2301 goto get_irqchip_out;
2302 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2303 if (r)
f0d66275 2304 goto get_irqchip_out;
1fe779f8 2305 r = -EFAULT;
f0d66275
DH		 2306 if (copy_to_user(argp, chip, sizeof *chip))
2307 goto get_irqchip_out;
1fe779f8 2308 r = 0;
f0d66275
DH		 2309 get_irqchip_out:
2310 kfree(chip);
2311 if (r)
2312 goto out;
1fe779f8
CO		 2313 break;
2314 }
2315 case KVM_SET_IRQCHIP: {
2316 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2317 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2318
f0d66275
DH		 2319 r = -ENOMEM;
2320 if (!chip)
1fe779f8 2321 goto out;
f0d66275
DH		 2322 r = -EFAULT;
2323 if (copy_from_user(chip, argp, sizeof *chip))
2324 goto set_irqchip_out;
1fe779f8
CO		 2325 r = -ENXIO;
2326 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2327 goto set_irqchip_out;
2328 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2329 if (r)
f0d66275 2330 goto set_irqchip_out;
1fe779f8 2331 r = 0;
f0d66275
DH		 2332 set_irqchip_out:
2333 kfree(chip);
2334 if (r)
2335 goto out;
1fe779f8
CO		 2336 break;
2337 }
e0f63cb9 2338 case KVM_GET_PIT: {
e0f63cb9 2339 r = -EFAULT;
f0d66275 2340 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2341 goto out;
2342 r = -ENXIO;
2343 if (!kvm->arch.vpit)
2344 goto out;
f0d66275 2345 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2346 if (r)
2347 goto out;
2348 r = -EFAULT;
f0d66275 2349 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2350 goto out;
2351 r = 0;
2352 break;
2353 }
2354 case KVM_SET_PIT: {
e0f63cb9 2355 r = -EFAULT;
f0d66275 2356 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2357 goto out;
2358 r = -ENXIO;
2359 if (!kvm->arch.vpit)
2360 goto out;
f0d66275 2361 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2362 if (r)
2363 goto out;
2364 r = 0;
2365 break;
2366 }
e9f42757
BK		 2367 case KVM_GET_PIT2: {
2368 r = -ENXIO;
2369 if (!kvm->arch.vpit)
2370 goto out;
2371 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2372 if (r)
2373 goto out;
2374 r = -EFAULT;
2375 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2376 goto out;
2377 r = 0;
2378 break;
2379 }
2380 case KVM_SET_PIT2: {
2381 r = -EFAULT;
2382 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2383 goto out;
2384 r = -ENXIO;
2385 if (!kvm->arch.vpit)
2386 goto out;
2387 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2388 if (r)
2389 goto out;
2390 r = 0;
2391 break;
2392 }
52d939a0
MT		 2393 case KVM_REINJECT_CONTROL: {
2394 struct kvm_reinject_control control;
2395 r = -EFAULT;
2396 if (copy_from_user(&control, argp, sizeof(control)))
2397 goto out;
2398 r = kvm_vm_ioctl_reinject(kvm, &control);
2399 if (r)
2400 goto out;
2401 r = 0;
2402 break;
2403 }
1fe779f8
CO		 2404 default:
2405 ;
2406 }
2407out:
2408 return r;
2409}
2410
a16b043c 2411static void kvm_init_msr_list(void)
043405e1
CO		 2412{
2413 u32 dummy[2];
2414 unsigned i, j;
2415
2416 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2417 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2418 continue;
2419 if (j < i)
2420 msrs_to_save[j] = msrs_to_save[i];
2421 j++;
2422 }
2423 num_msrs_to_save = j;
2424}
2425
bda9020e
MT		 2426static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2427 const void *v)
bbd9b64e 2428{
bda9020e
MT		 2429 if (vcpu->arch.apic &&
2430 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
2431 return 0;
bbd9b64e 2432
bda9020e 2433 return kvm_io_bus_write(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2434}
2435
bda9020e 2436static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 2437{
bda9020e
MT		 2438 if (vcpu->arch.apic &&
2439 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
2440 return 0;
bbd9b64e 2441
bda9020e 2442 return kvm_io_bus_read(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2443}
2444
cded19f3
HE		 2445static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2446 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2447{
2448 void *data = val;
10589a46 2449 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2450
2451 while (bytes) {
ad312c7c 2452 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2453 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2454 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2455 int ret;
2456
10589a46
MT		 2457 if (gpa == UNMAPPED_GVA) {
2458 r = X86EMUL_PROPAGATE_FAULT;
2459 goto out;
2460 }
77c2002e 2461 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2462 if (ret < 0) {
2463 r = X86EMUL_UNHANDLEABLE;
2464 goto out;
2465 }
bbd9b64e 2466
77c2002e
IE		 2467 bytes -= toread;
2468 data += toread;
2469 addr += toread;
bbd9b64e 2470 }
10589a46 2471out:
10589a46 2472 return r;
bbd9b64e 2473}
77c2002e 2474
cded19f3
HE		 2475static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2476 struct kvm_vcpu *vcpu)
77c2002e
IE		 2477{
2478 void *data = val;
2479 int r = X86EMUL_CONTINUE;
2480
2481 while (bytes) {
2482 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2483 unsigned offset = addr & (PAGE_SIZE-1);
2484 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2485 int ret;
2486
2487 if (gpa == UNMAPPED_GVA) {
2488 r = X86EMUL_PROPAGATE_FAULT;
2489 goto out;
2490 }
2491 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2492 if (ret < 0) {
2493 r = X86EMUL_UNHANDLEABLE;
2494 goto out;
2495 }
2496
2497 bytes -= towrite;
2498 data += towrite;
2499 addr += towrite;
2500 }
2501out:
2502 return r;
2503}
2504
bbd9b64e 2505
bbd9b64e
CO		 2506static int emulator_read_emulated(unsigned long addr,
2507 void *val,
2508 unsigned int bytes,
2509 struct kvm_vcpu *vcpu)
2510{
bbd9b64e
CO		 2511 gpa_t gpa;
2512
2513 if (vcpu->mmio_read_completed) {
2514 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 2515 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
2516 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 2517 vcpu->mmio_read_completed = 0;
2518 return X86EMUL_CONTINUE;
2519 }
2520
ad312c7c 2521 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2522
2523 /* For APIC access vmexit */
2524 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2525 goto mmio;
2526
77c2002e
IE		 2527 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2528 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2529 return X86EMUL_CONTINUE;
2530 if (gpa == UNMAPPED_GVA)
2531 return X86EMUL_PROPAGATE_FAULT;
2532
2533mmio:
2534 /*
2535 * Is this MMIO handled locally?
2536 */
aec51dc4
AK		 2537 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
2538 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e 2539 return X86EMUL_CONTINUE;
aec51dc4
AK		 2540 }
2541
2542 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 2543
2544 vcpu->mmio_needed = 1;
2545 vcpu->mmio_phys_addr = gpa;
2546 vcpu->mmio_size = bytes;
2547 vcpu->mmio_is_write = 0;
2548
2549 return X86EMUL_UNHANDLEABLE;
2550}
2551
3200f405 2552int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2553 const void *val, int bytes)
bbd9b64e
CO		 2554{
2555 int ret;
2556
2557 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2558 if (ret < 0)
bbd9b64e 2559 return 0;
ad218f85 2560 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2561 return 1;
2562}
2563
2564static int emulator_write_emulated_onepage(unsigned long addr,
2565 const void *val,
2566 unsigned int bytes,
2567 struct kvm_vcpu *vcpu)
2568{
10589a46
MT		 2569 gpa_t gpa;
2570
10589a46 2571 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2572
2573 if (gpa == UNMAPPED_GVA) {
c3c91fee 2574 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2575 return X86EMUL_PROPAGATE_FAULT;
2576 }
2577
2578 /* For APIC access vmexit */
2579 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2580 goto mmio;
2581
2582 if (emulator_write_phys(vcpu, gpa, val, bytes))
2583 return X86EMUL_CONTINUE;
2584
2585mmio:
aec51dc4 2586 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 2587 /*
2588 * Is this MMIO handled locally?
2589 */
bda9020e 2590 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 2591 return X86EMUL_CONTINUE;
bbd9b64e
CO		 2592
2593 vcpu->mmio_needed = 1;
2594 vcpu->mmio_phys_addr = gpa;
2595 vcpu->mmio_size = bytes;
2596 vcpu->mmio_is_write = 1;
2597 memcpy(vcpu->mmio_data, val, bytes);
2598
2599 return X86EMUL_CONTINUE;
2600}
2601
2602int emulator_write_emulated(unsigned long addr,
2603 const void *val,
2604 unsigned int bytes,
2605 struct kvm_vcpu *vcpu)
2606{
2607 /* Crossing a page boundary? */
2608 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2609 int rc, now;
2610
2611 now = -addr & ~PAGE_MASK;
2612 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2613 if (rc != X86EMUL_CONTINUE)
2614 return rc;
2615 addr += now;
2616 val += now;
2617 bytes -= now;
2618 }
2619 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2620}
2621EXPORT_SYMBOL_GPL(emulator_write_emulated);
2622
2623static int emulator_cmpxchg_emulated(unsigned long addr,
2624 const void *old,
2625 const void *new,
2626 unsigned int bytes,
2627 struct kvm_vcpu *vcpu)
2628{
2629 static int reported;
2630
2631 if (!reported) {
2632 reported = 1;
2633 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2634 }
2bacc55c
MT		 2635#ifndef CONFIG_X86_64
2636 /* guests cmpxchg8b have to be emulated atomically */
2637 if (bytes == 8) {
10589a46 2638 gpa_t gpa;
2bacc55c 2639 struct page *page;
c0b49b0d 2640 char *kaddr;
2bacc55c
MT		 2641 u64 val;
2642
10589a46
MT		 2643 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2644
2bacc55c
MT		 2645 if (gpa == UNMAPPED_GVA ||
2646 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2647 goto emul_write;
2648
2649 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2650 goto emul_write;
2651
2652 val = *(u64 *)new;
72dc67a6 2653
2bacc55c 2654 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2655
c0b49b0d
AM		 2656 kaddr = kmap_atomic(page, KM_USER0);
2657 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2658 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2659 kvm_release_page_dirty(page);
2660 }
3200f405 2661emul_write:
2bacc55c
MT		 2662#endif
2663
bbd9b64e
CO		 2664 return emulator_write_emulated(addr, new, bytes, vcpu);
2665}
2666
2667static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2668{
2669 return kvm_x86_ops->get_segment_base(vcpu, seg);
2670}
2671
2672int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2673{
a7052897 2674 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2675 return X86EMUL_CONTINUE;
2676}
2677
2678int emulate_clts(struct kvm_vcpu *vcpu)
2679{
ad312c7c 2680 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2681 return X86EMUL_CONTINUE;
2682}
2683
2684int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2685{
2686 struct kvm_vcpu *vcpu = ctxt->vcpu;
2687
2688 switch (dr) {
2689 case 0 ... 3:
2690 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2691 return X86EMUL_CONTINUE;
2692 default:
b8688d51 2693 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2694 return X86EMUL_UNHANDLEABLE;
2695 }
2696}
2697
2698int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2699{
2700 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2701 int exception;
2702
2703 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2704 if (exception) {
2705 /* FIXME: better handling */
2706 return X86EMUL_UNHANDLEABLE;
2707 }
2708 return X86EMUL_CONTINUE;
2709}
2710
2711void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2712{
bbd9b64e 2713 u8 opcodes[4];
5fdbf976 2714 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2715 unsigned long rip_linear;
2716
f76c710d 2717 if (!printk_ratelimit())
bbd9b64e
CO		 2718 return;
2719
25be4608
GC		 2720 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2721
77c2002e 2722 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 2723
2724 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2725 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2726}
2727EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2728
14af3f3c 2729static struct x86_emulate_ops emulate_ops = {
77c2002e 2730 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 2731 .read_emulated = emulator_read_emulated,
2732 .write_emulated = emulator_write_emulated,
2733 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2734};
2735
5fdbf976
MT		 2736static void cache_all_regs(struct kvm_vcpu *vcpu)
2737{
2738 kvm_register_read(vcpu, VCPU_REGS_RAX);
2739 kvm_register_read(vcpu, VCPU_REGS_RSP);
2740 kvm_register_read(vcpu, VCPU_REGS_RIP);
2741 vcpu->arch.regs_dirty = ~0;
2742}
2743
bbd9b64e
CO		 2744int emulate_instruction(struct kvm_vcpu *vcpu,
2745 struct kvm_run *run,
2746 unsigned long cr2,
2747 u16 error_code,
571008da 2748 int emulation_type)
bbd9b64e 2749{
310b5d30 2750 int r, shadow_mask;
571008da 2751 struct decode_cache *c;
bbd9b64e 2752
26eef70c 2753 kvm_clear_exception_queue(vcpu);
ad312c7c 2754 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2755 /*
2756 * TODO: fix x86_emulate.c to use guest_read/write_register
2757 * instead of direct ->regs accesses, can save hundred cycles
2758 * on Intel for instructions that don't read/change RSP, for
2759 * for example.
2760 */
2761 cache_all_regs(vcpu);
bbd9b64e
CO		 2762
2763 vcpu->mmio_is_write = 0;
ad312c7c 2764 vcpu->arch.pio.string = 0;
bbd9b64e 2765
571008da 2766 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2767 int cs_db, cs_l;
2768 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2769
ad312c7c
ZX		 2770 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2771 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2772 vcpu->arch.emulate_ctxt.mode =
2773 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2774 ? X86EMUL_MODE_REAL : cs_l
2775 ? X86EMUL_MODE_PROT64 : cs_db
2776 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2777
ad312c7c 2778 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 2779
0cb5762e
AP		 2780 /* Only allow emulation of specific instructions on #UD
2781 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 2782 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 2783 if (emulation_type & EMULTYPE_TRAP_UD) {
2784 if (!c->twobyte)
2785 return EMULATE_FAIL;
2786 switch (c->b) {
2787 case 0x01: /* VMMCALL */
2788 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2789 return EMULATE_FAIL;
2790 break;
2791 case 0x34: /* sysenter */
2792 case 0x35: /* sysexit */
2793 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2794 return EMULATE_FAIL;
2795 break;
2796 case 0x05: /* syscall */
2797 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2798 return EMULATE_FAIL;
2799 break;
2800 default:
2801 return EMULATE_FAIL;
2802 }
2803
2804 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
2805 return EMULATE_FAIL;
2806 }
571008da 2807
f2b5756b 2808 ++vcpu->stat.insn_emulation;
bbd9b64e 2809 if (r) {
f2b5756b 2810 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2811 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2812 return EMULATE_DONE;
2813 return EMULATE_FAIL;
2814 }
2815 }
2816
ba8afb6b
GN		 2817 if (emulation_type & EMULTYPE_SKIP) {
2818 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
2819 return EMULATE_DONE;
2820 }
2821
ad312c7c 2822 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 2823 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
2824
2825 if (r == 0)
2826 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 2827
ad312c7c 2828 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2829 return EMULATE_DO_MMIO;
2830
2831 if ((r || vcpu->mmio_is_write) && run) {
2832 run->exit_reason = KVM_EXIT_MMIO;
2833 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2834 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2835 run->mmio.len = vcpu->mmio_size;
2836 run->mmio.is_write = vcpu->mmio_is_write;
2837 }
2838
2839 if (r) {
2840 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2841 return EMULATE_DONE;
2842 if (!vcpu->mmio_needed) {
2843 kvm_report_emulation_failure(vcpu, "mmio");
2844 return EMULATE_FAIL;
2845 }
2846 return EMULATE_DO_MMIO;
2847 }
2848
ad312c7c 2849 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2850
2851 if (vcpu->mmio_is_write) {
2852 vcpu->mmio_needed = 0;
2853 return EMULATE_DO_MMIO;
2854 }
2855
2856 return EMULATE_DONE;
2857}
2858EXPORT_SYMBOL_GPL(emulate_instruction);
2859
de7d789a
CO		 2860static int pio_copy_data(struct kvm_vcpu *vcpu)
2861{
ad312c7c 2862 void *p = vcpu->arch.pio_data;
0f346074 2863 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 2864 unsigned bytes;
0f346074 2865 int ret;
de7d789a 2866
ad312c7c
ZX		 2867 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2868 if (vcpu->arch.pio.in)
0f346074 2869 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 2870 else
0f346074
IE		 2871 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2872 return ret;
de7d789a
CO		 2873}
2874
2875int complete_pio(struct kvm_vcpu *vcpu)
2876{
ad312c7c 2877 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2878 long delta;
2879 int r;
5fdbf976 2880 unsigned long val;
de7d789a
CO		 2881
2882 if (!io->string) {
5fdbf976
MT		 2883 if (io->in) {
2884 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2885 memcpy(&val, vcpu->arch.pio_data, io->size);
2886 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2887 }
de7d789a
CO		 2888 } else {
2889 if (io->in) {
2890 r = pio_copy_data(vcpu);
5fdbf976 2891 if (r)
de7d789a 2892 return r;
de7d789a
CO		 2893 }
2894
2895 delta = 1;
2896 if (io->rep) {
2897 delta *= io->cur_count;
2898 /*
2899 * The size of the register should really depend on
2900 * current address size.
2901 */
5fdbf976
MT		 2902 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2903 val -= delta;
2904 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2905 }
2906 if (io->down)
2907 delta = -delta;
2908 delta *= io->size;
5fdbf976
MT		 2909 if (io->in) {
2910 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2911 val += delta;
2912 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2913 } else {
2914 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2915 val += delta;
2916 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2917 }
de7d789a
CO		 2918 }
2919
de7d789a
CO		 2920 io->count -= io->cur_count;
2921 io->cur_count = 0;
2922
2923 return 0;
2924}
2925
bda9020e 2926static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 2927{
2928 /* TODO: String I/O for in kernel device */
bda9020e 2929 int r;
de7d789a 2930
ad312c7c 2931 if (vcpu->arch.pio.in)
bda9020e
MT		 2932 r = kvm_io_bus_read(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2933 vcpu->arch.pio.size, pd);
de7d789a 2934 else
bda9020e
MT		 2935 r = kvm_io_bus_write(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2936 vcpu->arch.pio.size, pd);
2937 return r;
de7d789a
CO		 2938}
2939
bda9020e 2940static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 2941{
ad312c7c
ZX		 2942 struct kvm_pio_request *io = &vcpu->arch.pio;
2943 void *pd = vcpu->arch.pio_data;
bda9020e 2944 int i, r = 0;
de7d789a 2945
de7d789a 2946 for (i = 0; i < io->cur_count; i++) {
bda9020e
MT		 2947 if (kvm_io_bus_write(&vcpu->kvm->pio_bus,
2948 io->port, io->size, pd)) {
2949 r = -EOPNOTSUPP;
2950 break;
2951 }
de7d789a
CO		 2952 pd += io->size;
2953 }
bda9020e 2954 return r;
de7d789a
CO		 2955}
2956
2957int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2958 int size, unsigned port)
2959{
5fdbf976 2960 unsigned long val;
de7d789a
CO		 2961
2962 vcpu->run->exit_reason = KVM_EXIT_IO;
2963 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2964 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2965 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2966 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2967 vcpu->run->io.port = vcpu->arch.pio.port = port;
2968 vcpu->arch.pio.in = in;
2969 vcpu->arch.pio.string = 0;
2970 vcpu->arch.pio.down = 0;
ad312c7c 2971 vcpu->arch.pio.rep = 0;
de7d789a 2972
229456fc
MT		 2973 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2974 size, 1);
2714d1d3 2975
5fdbf976
MT		 2976 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2977 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2978
bda9020e 2979 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 2980 complete_pio(vcpu);
2981 return 1;
2982 }
2983 return 0;
2984}
2985EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2986
2987int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2988 int size, unsigned long count, int down,
2989 gva_t address, int rep, unsigned port)
2990{
2991 unsigned now, in_page;
0f346074 2992 int ret = 0;
de7d789a
CO		 2993
2994 vcpu->run->exit_reason = KVM_EXIT_IO;
2995 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2996 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2997 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2998 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2999 vcpu->run->io.port = vcpu->arch.pio.port = port;
3000 vcpu->arch.pio.in = in;
3001 vcpu->arch.pio.string = 1;
3002 vcpu->arch.pio.down = down;
ad312c7c 3003 vcpu->arch.pio.rep = rep;
de7d789a 3004
229456fc
MT		 3005 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3006 size, count);
2714d1d3 3007
de7d789a
CO		 3008 if (!count) {
3009 kvm_x86_ops->skip_emulated_instruction(vcpu);
3010 return 1;
3011 }
3012
3013 if (!down)
3014 in_page = PAGE_SIZE - offset_in_page(address);
3015 else
3016 in_page = offset_in_page(address) + size;
3017 now = min(count, (unsigned long)in_page / size);
0f346074 3018 if (!now)
de7d789a 3019 now = 1;
de7d789a
CO		 3020 if (down) {
3021 /*
3022 * String I/O in reverse. Yuck. Kill the guest, fix later.
3023 */
3024 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 3025 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 3026 return 1;
3027 }
3028 vcpu->run->io.count = now;
ad312c7c 3029 vcpu->arch.pio.cur_count = now;
de7d789a 3030
ad312c7c 3031 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 3032 kvm_x86_ops->skip_emulated_instruction(vcpu);
3033
0f346074 3034 vcpu->arch.pio.guest_gva = address;
de7d789a 3035
ad312c7c 3036 if (!vcpu->arch.pio.in) {
de7d789a
CO		 3037 /* string PIO write */
3038 ret = pio_copy_data(vcpu);
0f346074
IE		 3039 if (ret == X86EMUL_PROPAGATE_FAULT) {
3040 kvm_inject_gp(vcpu, 0);
3041 return 1;
3042 }
bda9020e 3043 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 3044 complete_pio(vcpu);
ad312c7c 3045 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 3046 ret = 1;
3047 }
bda9020e
MT		 3048 }
3049 /* no string PIO read support yet */
de7d789a
CO		 3050
3051 return ret;
3052}
3053EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3054
c8076604
GH		 3055static void bounce_off(void *info)
3056{
3057 /* nothing */
3058}
3059
3060static unsigned int ref_freq;
3061static unsigned long tsc_khz_ref;
3062
3063static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3064 void *data)
3065{
3066 struct cpufreq_freqs *freq = data;
3067 struct kvm *kvm;
3068 struct kvm_vcpu *vcpu;
3069 int i, send_ipi = 0;
3070
3071 if (!ref_freq)
3072 ref_freq = freq->old;
3073
3074 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3075 return 0;
3076 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3077 return 0;
3078 per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
3079
3080 spin_lock(&kvm_lock);
3081 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3082 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3083 if (vcpu->cpu != freq->cpu)
3084 continue;
3085 if (!kvm_request_guest_time_update(vcpu))
3086 continue;
3087 if (vcpu->cpu != smp_processor_id())
3088 send_ipi++;
3089 }
3090 }
3091 spin_unlock(&kvm_lock);
3092
3093 if (freq->old < freq->new && send_ipi) {
3094 /*
3095 * We upscale the frequency. Must make the guest
3096 * doesn't see old kvmclock values while running with
3097 * the new frequency, otherwise we risk the guest sees
3098 * time go backwards.
3099 *
3100 * In case we update the frequency for another cpu
3101 * (which might be in guest context) send an interrupt
3102 * to kick the cpu out of guest context. Next time
3103 * guest context is entered kvmclock will be updated,
3104 * so the guest will not see stale values.
3105 */
3106 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3107 }
3108 return 0;
3109}
3110
3111static struct notifier_block kvmclock_cpufreq_notifier_block = {
3112 .notifier_call = kvmclock_cpufreq_notifier
3113};
3114
f8c16bba 3115int kvm_arch_init(void *opaque)
043405e1 3116{
c8076604 3117 int r, cpu;
f8c16bba
ZX		 3118 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3119
f8c16bba
ZX		 3120 if (kvm_x86_ops) {
3121 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3122 r = -EEXIST;
3123 goto out;
f8c16bba
ZX		 3124 }
3125
3126 if (!ops->cpu_has_kvm_support()) {
3127 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3128 r = -EOPNOTSUPP;
3129 goto out;
f8c16bba
ZX		 3130 }
3131 if (ops->disabled_by_bios()) {
3132 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3133 r = -EOPNOTSUPP;
3134 goto out;
f8c16bba
ZX		 3135 }
3136
97db56ce
AK		 3137 r = kvm_mmu_module_init();
3138 if (r)
3139 goto out;
3140
3141 kvm_init_msr_list();
3142
f8c16bba 3143 kvm_x86_ops = ops;
56c6d28a 3144 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3145 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3146 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3147 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604
GH		 3148
3149 for_each_possible_cpu(cpu)
3150 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
3151 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
3152 tsc_khz_ref = tsc_khz;
3153 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3154 CPUFREQ_TRANSITION_NOTIFIER);
3155 }
3156
f8c16bba 3157 return 0;
56c6d28a
ZX		 3158
3159out:
56c6d28a 3160 return r;
043405e1 3161}
8776e519 3162
f8c16bba
ZX		 3163void kvm_arch_exit(void)
3164{
888d256e
JK		 3165 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3166 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3167 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3168 kvm_x86_ops = NULL;
56c6d28a
ZX		 3169 kvm_mmu_module_exit();
3170}
f8c16bba 3171
8776e519
HB		 3172int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3173{
3174 ++vcpu->stat.halt_exits;
3175 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3176 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3177 return 1;
3178 } else {
3179 vcpu->run->exit_reason = KVM_EXIT_HLT;
3180 return 0;
3181 }
3182}
3183EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3184
2f333bcb
MT		 3185static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3186 unsigned long a1)
3187{
3188 if (is_long_mode(vcpu))
3189 return a0;
3190 else
3191 return a0 | ((gpa_t)a1 << 32);
3192}
3193
8776e519
HB		 3194int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3195{
3196 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3197 int r = 1;
8776e519 3198
5fdbf976
MT		 3199 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3200 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3201 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3202 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3203 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3204
229456fc 3205 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3206
8776e519
HB		 3207 if (!is_long_mode(vcpu)) {
3208 nr &= 0xFFFFFFFF;
3209 a0 &= 0xFFFFFFFF;
3210 a1 &= 0xFFFFFFFF;
3211 a2 &= 0xFFFFFFFF;
3212 a3 &= 0xFFFFFFFF;
3213 }
3214
3215 switch (nr) {
b93463aa
AK		 3216 case KVM_HC_VAPIC_POLL_IRQ:
3217 ret = 0;
3218 break;
2f333bcb
MT		 3219 case KVM_HC_MMU_OP:
3220 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3221 break;
8776e519
HB		 3222 default:
3223 ret = -KVM_ENOSYS;
3224 break;
3225 }
5fdbf976 3226 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3227 ++vcpu->stat.hypercalls;
2f333bcb 3228 return r;
8776e519
HB		 3229}
3230EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3231
3232int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3233{
3234 char instruction[3];
3235 int ret = 0;
5fdbf976 3236 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3237
8776e519
HB		 3238
3239 /*
3240 * Blow out the MMU to ensure that no other VCPU has an active mapping
3241 * to ensure that the updated hypercall appears atomically across all
3242 * VCPUs.
3243 */
3244 kvm_mmu_zap_all(vcpu->kvm);
3245
8776e519 3246 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 3247 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 3248 != X86EMUL_CONTINUE)
3249 ret = -EFAULT;
3250
8776e519
HB		 3251 return ret;
3252}
3253
3254static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3255{
3256 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3257}
3258
3259void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3260{
3261 struct descriptor_table dt = { limit, base };
3262
3263 kvm_x86_ops->set_gdt(vcpu, &dt);
3264}
3265
3266void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3267{
3268 struct descriptor_table dt = { limit, base };
3269
3270 kvm_x86_ops->set_idt(vcpu, &dt);
3271}
3272
3273void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3274 unsigned long *rflags)
3275{
2d3ad1f4 3276 kvm_lmsw(vcpu, msw);
8776e519
HB		 3277 *rflags = kvm_x86_ops->get_rflags(vcpu);
3278}
3279
3280unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3281{
54e445ca
JR		 3282 unsigned long value;
3283
8776e519
HB		 3284 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3285 switch (cr) {
3286 case 0:
54e445ca
JR		 3287 value = vcpu->arch.cr0;
3288 break;
8776e519 3289 case 2:
54e445ca
JR		 3290 value = vcpu->arch.cr2;
3291 break;
8776e519 3292 case 3:
54e445ca
JR		 3293 value = vcpu->arch.cr3;
3294 break;
8776e519 3295 case 4:
54e445ca
JR		 3296 value = vcpu->arch.cr4;
3297 break;
152ff9be 3298 case 8:
54e445ca
JR		 3299 value = kvm_get_cr8(vcpu);
3300 break;
8776e519 3301 default:
b8688d51 3302 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3303 return 0;
3304 }
54e445ca
JR		 3305
3306 return value;
8776e519
HB		 3307}
3308
3309void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3310 unsigned long *rflags)
3311{
3312 switch (cr) {
3313 case 0:
2d3ad1f4 3314 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 3315 *rflags = kvm_x86_ops->get_rflags(vcpu);
3316 break;
3317 case 2:
ad312c7c 3318 vcpu->arch.cr2 = val;
8776e519
HB		 3319 break;
3320 case 3:
2d3ad1f4 3321 kvm_set_cr3(vcpu, val);
8776e519
HB		 3322 break;
3323 case 4:
2d3ad1f4 3324 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 3325 break;
152ff9be 3326 case 8:
2d3ad1f4 3327 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 3328 break;
8776e519 3329 default:
b8688d51 3330 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3331 }
3332}
3333
07716717
DK		 3334static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3335{
ad312c7c
ZX		 3336 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3337 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 3338
3339 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3340 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 3341 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 3342 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 3343 if (ej->function == e->function) {
3344 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3345 return j;
3346 }
3347 }
3348 return 0; /* silence gcc, even though control never reaches here */
3349}
3350
3351/* find an entry with matching function, matching index (if needed), and that
3352 * should be read next (if it's stateful) */
3353static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3354 u32 function, u32 index)
3355{
3356 if (e->function != function)
3357 return 0;
3358 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3359 return 0;
3360 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 3361 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 3362 return 0;
3363 return 1;
3364}
3365
d8017474
AG		 3366struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3367 u32 function, u32 index)
8776e519
HB		 3368{
3369 int i;
d8017474 3370 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3371
ad312c7c 3372 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3373 struct kvm_cpuid_entry2 *e;
3374
ad312c7c 3375 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3376 if (is_matching_cpuid_entry(e, function, index)) {
3377 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3378 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3379 best = e;
3380 break;
3381 }
3382 /*
3383 * Both basic or both extended?
3384 */
3385 if (((e->function ^ function) & 0x80000000) == 0)
3386 if (!best || e->function > best->function)
3387 best = e;
3388 }
d8017474
AG		 3389 return best;
3390}
3391
82725b20
DE		 3392int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3393{
3394 struct kvm_cpuid_entry2 *best;
3395
3396 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3397 if (best)
3398 return best->eax & 0xff;
3399 return 36;
3400}
3401
d8017474
AG		 3402void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3403{
3404 u32 function, index;
3405 struct kvm_cpuid_entry2 *best;
3406
3407 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3408 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3409 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3410 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3411 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3412 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3413 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3414 if (best) {
5fdbf976
MT		 3415 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3416 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3417 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3418 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3419 }
8776e519 3420 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 3421 trace_kvm_cpuid(function,
3422 kvm_register_read(vcpu, VCPU_REGS_RAX),
3423 kvm_register_read(vcpu, VCPU_REGS_RBX),
3424 kvm_register_read(vcpu, VCPU_REGS_RCX),
3425 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 3426}
3427EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3428
b6c7a5dc
HB		 3429/*
3430 * Check if userspace requested an interrupt window, and that the
3431 * interrupt window is open.
3432 *
3433 * No need to exit to userspace if we already have an interrupt queued.
3434 */
3435static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3436 struct kvm_run *kvm_run)
3437{
8061823a 3438 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
b6c7a5dc 3439 kvm_run->request_interrupt_window &&
5df56646 3440 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 3441}
3442
3443static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3444 struct kvm_run *kvm_run)
3445{
3446 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3447 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3448 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3449 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3450 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3451 else
b6c7a5dc 3452 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 3453 kvm_arch_interrupt_allowed(vcpu) &&
3454 !kvm_cpu_has_interrupt(vcpu) &&
3455 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 3456}
3457
b93463aa
AK		 3458static void vapic_enter(struct kvm_vcpu *vcpu)
3459{
3460 struct kvm_lapic *apic = vcpu->arch.apic;
3461 struct page *page;
3462
3463 if (!apic || !apic->vapic_addr)
3464 return;
3465
3466 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3467
3468 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3469}
3470
3471static void vapic_exit(struct kvm_vcpu *vcpu)
3472{
3473 struct kvm_lapic *apic = vcpu->arch.apic;
3474
3475 if (!apic || !apic->vapic_addr)
3476 return;
3477
f8b78fa3 3478 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3479 kvm_release_page_dirty(apic->vapic_page);
3480 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3481 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3482}
3483
95ba8273
GN		 3484static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3485{
3486 int max_irr, tpr;
3487
3488 if (!kvm_x86_ops->update_cr8_intercept)
3489 return;
3490
8db3baa2
GN		 3491 if (!vcpu->arch.apic->vapic_addr)
3492 max_irr = kvm_lapic_find_highest_irr(vcpu);
3493 else
3494 max_irr = -1;
95ba8273
GN		 3495
3496 if (max_irr != -1)
3497 max_irr >>= 4;
3498
3499 tpr = kvm_lapic_get_cr8(vcpu);
3500
3501 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3502}
3503
b59bb7bd 3504static void inject_pending_event(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
95ba8273
GN		 3505{
3506 /* try to reinject previous events if any */
b59bb7bd
GN		 3507 if (vcpu->arch.exception.pending) {
3508 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
3509 vcpu->arch.exception.has_error_code,
3510 vcpu->arch.exception.error_code);
3511 return;
3512 }
3513
95ba8273
GN		 3514 if (vcpu->arch.nmi_injected) {
3515 kvm_x86_ops->set_nmi(vcpu);
3516 return;
3517 }
3518
3519 if (vcpu->arch.interrupt.pending) {
66fd3f7f 3520 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3521 return;
3522 }
3523
3524 /* try to inject new event if pending */
3525 if (vcpu->arch.nmi_pending) {
3526 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3527 vcpu->arch.nmi_pending = false;
3528 vcpu->arch.nmi_injected = true;
3529 kvm_x86_ops->set_nmi(vcpu);
3530 }
3531 } else if (kvm_cpu_has_interrupt(vcpu)) {
3532 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 3533 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3534 false);
3535 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3536 }
3537 }
3538}
3539
d7690175 3540static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 3541{
3542 int r;
6a8b1d13
GN		 3543 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
3544 kvm_run->request_interrupt_window;
b6c7a5dc 3545
2e53d63a
MT		 3546 if (vcpu->requests)
3547 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3548 kvm_mmu_unload(vcpu);
3549
b6c7a5dc
HB		 3550 r = kvm_mmu_reload(vcpu);
3551 if (unlikely(r))
3552 goto out;
3553
2f52d58c
AK		 3554 if (vcpu->requests) {
3555 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3556 __kvm_migrate_timers(vcpu);
c8076604
GH		 3557 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3558 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3559 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3560 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3561 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3562 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3563 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3564 &vcpu->requests)) {
3565 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3566 r = 0;
3567 goto out;
3568 }
71c4dfaf
JR		 3569 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3570 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3571 r = 0;
3572 goto out;
3573 }
2f52d58c 3574 }
b93463aa 3575
b6c7a5dc
HB		 3576 preempt_disable();
3577
3578 kvm_x86_ops->prepare_guest_switch(vcpu);
3579 kvm_load_guest_fpu(vcpu);
3580
3581 local_irq_disable();
3582
32f88400
MT		 3583 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3584 smp_mb__after_clear_bit();
3585
d7690175 3586 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 3587 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 3588 local_irq_enable();
3589 preempt_enable();
3590 r = 1;
3591 goto out;
3592 }
3593
b59bb7bd 3594 inject_pending_event(vcpu, kvm_run);
b6c7a5dc 3595
6a8b1d13
GN		 3596 /* enable NMI/IRQ window open exits if needed */
3597 if (vcpu->arch.nmi_pending)
3598 kvm_x86_ops->enable_nmi_window(vcpu);
3599 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3600 kvm_x86_ops->enable_irq_window(vcpu);
3601
95ba8273 3602 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 3603 update_cr8_intercept(vcpu);
3604 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 3605 }
b93463aa 3606
3200f405
MT		 3607 up_read(&vcpu->kvm->slots_lock);
3608
b6c7a5dc
HB		 3609 kvm_guest_enter();
3610
42dbaa5a
JK		 3611 get_debugreg(vcpu->arch.host_dr6, 6);
3612 get_debugreg(vcpu->arch.host_dr7, 7);
3613 if (unlikely(vcpu->arch.switch_db_regs)) {
3614 get_debugreg(vcpu->arch.host_db[0], 0);
3615 get_debugreg(vcpu->arch.host_db[1], 1);
3616 get_debugreg(vcpu->arch.host_db[2], 2);
3617 get_debugreg(vcpu->arch.host_db[3], 3);
3618
3619 set_debugreg(0, 7);
3620 set_debugreg(vcpu->arch.eff_db[0], 0);
3621 set_debugreg(vcpu->arch.eff_db[1], 1);
3622 set_debugreg(vcpu->arch.eff_db[2], 2);
3623 set_debugreg(vcpu->arch.eff_db[3], 3);
3624 }
b6c7a5dc 3625
229456fc 3626 trace_kvm_entry(vcpu->vcpu_id);
b6c7a5dc
HB		 3627 kvm_x86_ops->run(vcpu, kvm_run);
3628
42dbaa5a
JK		 3629 if (unlikely(vcpu->arch.switch_db_regs)) {
3630 set_debugreg(0, 7);
3631 set_debugreg(vcpu->arch.host_db[0], 0);
3632 set_debugreg(vcpu->arch.host_db[1], 1);
3633 set_debugreg(vcpu->arch.host_db[2], 2);
3634 set_debugreg(vcpu->arch.host_db[3], 3);
3635 }
3636 set_debugreg(vcpu->arch.host_dr6, 6);
3637 set_debugreg(vcpu->arch.host_dr7, 7);
3638
32f88400 3639 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 3640 local_irq_enable();
3641
3642 ++vcpu->stat.exits;
3643
3644 /*
3645 * We must have an instruction between local_irq_enable() and
3646 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3647 * the interrupt shadow. The stat.exits increment will do nicely.
3648 * But we need to prevent reordering, hence this barrier():
3649 */
3650 barrier();
3651
3652 kvm_guest_exit();
3653
3654 preempt_enable();
3655
3200f405
MT		 3656 down_read(&vcpu->kvm->slots_lock);
3657
b6c7a5dc
HB		 3658 /*
3659 * Profile KVM exit RIPs:
3660 */
3661 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3662 unsigned long rip = kvm_rip_read(vcpu);
3663 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3664 }
3665
298101da 3666
b93463aa
AK		 3667 kvm_lapic_sync_from_vapic(vcpu);
3668
b6c7a5dc 3669 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3670out:
3671 return r;
3672}
b6c7a5dc 3673
09cec754 3674
d7690175
MT		 3675static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3676{
3677 int r;
3678
3679 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3680 pr_debug("vcpu %d received sipi with vector # %x\n",
3681 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3682 kvm_lapic_reset(vcpu);
5f179287 3683 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3684 if (r)
3685 return r;
3686 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3687 }
3688
d7690175
MT		 3689 down_read(&vcpu->kvm->slots_lock);
3690 vapic_enter(vcpu);
3691
3692 r = 1;
3693 while (r > 0) {
af2152f5 3694 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3695 r = vcpu_enter_guest(vcpu, kvm_run);
3696 else {
3697 up_read(&vcpu->kvm->slots_lock);
3698 kvm_vcpu_block(vcpu);
3699 down_read(&vcpu->kvm->slots_lock);
3700 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 3701 {
3702 switch(vcpu->arch.mp_state) {
3703 case KVM_MP_STATE_HALTED:
d7690175 3704 vcpu->arch.mp_state =
09cec754
GN		 3705 KVM_MP_STATE_RUNNABLE;
3706 case KVM_MP_STATE_RUNNABLE:
3707 break;
3708 case KVM_MP_STATE_SIPI_RECEIVED:
3709 default:
3710 r = -EINTR;
3711 break;
3712 }
3713 }
d7690175
MT		 3714 }
3715
09cec754
GN		 3716 if (r <= 0)
3717 break;
3718
3719 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
3720 if (kvm_cpu_has_pending_timer(vcpu))
3721 kvm_inject_pending_timer_irqs(vcpu);
3722
3723 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3724 r = -EINTR;
3725 kvm_run->exit_reason = KVM_EXIT_INTR;
3726 ++vcpu->stat.request_irq_exits;
3727 }
3728 if (signal_pending(current)) {
3729 r = -EINTR;
3730 kvm_run->exit_reason = KVM_EXIT_INTR;
3731 ++vcpu->stat.signal_exits;
3732 }
3733 if (need_resched()) {
3734 up_read(&vcpu->kvm->slots_lock);
3735 kvm_resched(vcpu);
3736 down_read(&vcpu->kvm->slots_lock);
d7690175 3737 }
b6c7a5dc
HB		 3738 }
3739
d7690175 3740 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3741 post_kvm_run_save(vcpu, kvm_run);
3742
b93463aa
AK		 3743 vapic_exit(vcpu);
3744
b6c7a5dc
HB		 3745 return r;
3746}
3747
3748int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3749{
3750 int r;
3751 sigset_t sigsaved;
3752
3753 vcpu_load(vcpu);
3754
ac9f6dc0
AK		 3755 if (vcpu->sigset_active)
3756 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3757
a4535290 3758 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3759 kvm_vcpu_block(vcpu);
d7690175 3760 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3761 r = -EAGAIN;
3762 goto out;
b6c7a5dc
HB		 3763 }
3764
b6c7a5dc
HB		 3765 /* re-sync apic's tpr */
3766 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3767 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3768
ad312c7c 3769 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3770 r = complete_pio(vcpu);
3771 if (r)
3772 goto out;
3773 }
3774#if CONFIG_HAS_IOMEM
3775 if (vcpu->mmio_needed) {
3776 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3777 vcpu->mmio_read_completed = 1;
3778 vcpu->mmio_needed = 0;
3200f405
MT		 3779
3780 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3781 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3782 vcpu->arch.mmio_fault_cr2, 0,
3783 EMULTYPE_NO_DECODE);
3200f405 3784 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3785 if (r == EMULATE_DO_MMIO) {
3786 /*
3787 * Read-modify-write. Back to userspace.
3788 */
3789 r = 0;
3790 goto out;
3791 }
3792 }
3793#endif
5fdbf976
MT		 3794 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3795 kvm_register_write(vcpu, VCPU_REGS_RAX,
3796 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3797
3798 r = __vcpu_run(vcpu, kvm_run);
3799
3800out:
3801 if (vcpu->sigset_active)
3802 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3803
3804 vcpu_put(vcpu);
3805 return r;
3806}
3807
3808int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3809{
3810 vcpu_load(vcpu);
3811
5fdbf976
MT		 3812 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3813 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3814 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3815 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3816 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3817 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3818 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3819 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3820#ifdef CONFIG_X86_64
5fdbf976
MT		 3821 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3822 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3823 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3824 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3825 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3826 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3827 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3828 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3829#endif
3830
5fdbf976 3831 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3832 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3833
3834 /*
3835 * Don't leak debug flags in case they were set for guest debugging
3836 */
d0bfb940 3837 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
b6c7a5dc
HB		 3838 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3839
3840 vcpu_put(vcpu);
3841
3842 return 0;
3843}
3844
3845int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3846{
3847 vcpu_load(vcpu);
3848
5fdbf976
MT		 3849 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3850 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3851 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3852 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3853 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3854 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3855 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3856 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3857#ifdef CONFIG_X86_64
5fdbf976
MT		 3858 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3859 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3860 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3861 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3862 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3863 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3864 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3865 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3866
b6c7a5dc
HB		 3867#endif
3868
5fdbf976 3869 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3870 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3871
b6c7a5dc 3872
b4f14abd
JK		 3873 vcpu->arch.exception.pending = false;
3874
b6c7a5dc
HB		 3875 vcpu_put(vcpu);
3876
3877 return 0;
3878}
3879
3e6e0aab
GT		 3880void kvm_get_segment(struct kvm_vcpu *vcpu,
3881 struct kvm_segment *var, int seg)
b6c7a5dc 3882{
14af3f3c 3883 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3884}
3885
3886void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3887{
3888 struct kvm_segment cs;
3889
3e6e0aab 3890 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3891 *db = cs.db;
3892 *l = cs.l;
3893}
3894EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3895
3896int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3897 struct kvm_sregs *sregs)
3898{
3899 struct descriptor_table dt;
b6c7a5dc
HB		 3900
3901 vcpu_load(vcpu);
3902
3e6e0aab
GT		 3903 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3904 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3905 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3906 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3907 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3908 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3909
3e6e0aab
GT		 3910 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3911 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3912
3913 kvm_x86_ops->get_idt(vcpu, &dt);
3914 sregs->idt.limit = dt.limit;
3915 sregs->idt.base = dt.base;
3916 kvm_x86_ops->get_gdt(vcpu, &dt);
3917 sregs->gdt.limit = dt.limit;
3918 sregs->gdt.base = dt.base;
3919
3920 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3921 sregs->cr0 = vcpu->arch.cr0;
3922 sregs->cr2 = vcpu->arch.cr2;
3923 sregs->cr3 = vcpu->arch.cr3;
3924 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3925 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3926 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3927 sregs->apic_base = kvm_get_apic_base(vcpu);
3928
923c61bb 3929 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 3930
36752c9b 3931 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 3932 set_bit(vcpu->arch.interrupt.nr,
3933 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 3934
b6c7a5dc
HB		 3935 vcpu_put(vcpu);
3936
3937 return 0;
3938}
3939
62d9f0db
MT		 3940int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3941 struct kvm_mp_state *mp_state)
3942{
3943 vcpu_load(vcpu);
3944 mp_state->mp_state = vcpu->arch.mp_state;
3945 vcpu_put(vcpu);
3946 return 0;
3947}
3948
3949int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3950 struct kvm_mp_state *mp_state)
3951{
3952 vcpu_load(vcpu);
3953 vcpu->arch.mp_state = mp_state->mp_state;
3954 vcpu_put(vcpu);
3955 return 0;
3956}
3957
3e6e0aab 3958static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3959 struct kvm_segment *var, int seg)
3960{
14af3f3c 3961 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3962}
3963
37817f29
IE		 3964static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3965 struct kvm_segment *kvm_desct)
3966{
46a359e7
AM		 3967 kvm_desct->base = get_desc_base(seg_desc);
3968 kvm_desct->limit = get_desc_limit(seg_desc);
c93cd3a5
MT		 3969 if (seg_desc->g) {
3970 kvm_desct->limit <<= 12;
3971 kvm_desct->limit |= 0xfff;
3972 }
37817f29
IE		 3973 kvm_desct->selector = selector;
3974 kvm_desct->type = seg_desc->type;
3975 kvm_desct->present = seg_desc->p;
3976 kvm_desct->dpl = seg_desc->dpl;
3977 kvm_desct->db = seg_desc->d;
3978 kvm_desct->s = seg_desc->s;
3979 kvm_desct->l = seg_desc->l;
3980 kvm_desct->g = seg_desc->g;
3981 kvm_desct->avl = seg_desc->avl;
3982 if (!selector)
3983 kvm_desct->unusable = 1;
3984 else
3985 kvm_desct->unusable = 0;
3986 kvm_desct->padding = 0;
3987}
3988
b8222ad2
AS		 3989static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3990 u16 selector,
3991 struct descriptor_table *dtable)
37817f29
IE		 3992{
3993 if (selector & 1 << 2) {
3994 struct kvm_segment kvm_seg;
3995
3e6e0aab 3996 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3997
3998 if (kvm_seg.unusable)
3999 dtable->limit = 0;
4000 else
4001 dtable->limit = kvm_seg.limit;
4002 dtable->base = kvm_seg.base;
4003 }
4004 else
4005 kvm_x86_ops->get_gdt(vcpu, dtable);
4006}
4007
4008/* allowed just for 8 bytes segments */
4009static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4010 struct desc_struct *seg_desc)
4011{
98899aa0 4012 gpa_t gpa;
37817f29
IE		 4013 struct descriptor_table dtable;
4014 u16 index = selector >> 3;
4015
b8222ad2 4016 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4017
4018 if (dtable.limit < index * 8 + 7) {
4019 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
4020 return 1;
4021 }
98899aa0
MT		 4022 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
4023 gpa += index * 8;
4024 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 4025}
4026
4027/* allowed just for 8 bytes segments */
4028static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4029 struct desc_struct *seg_desc)
4030{
98899aa0 4031 gpa_t gpa;
37817f29
IE		 4032 struct descriptor_table dtable;
4033 u16 index = selector >> 3;
4034
b8222ad2 4035 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4036
4037 if (dtable.limit < index * 8 + 7)
4038 return 1;
98899aa0
MT		 4039 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
4040 gpa += index * 8;
4041 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 4042}
4043
4044static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
4045 struct desc_struct *seg_desc)
4046{
46a359e7 4047 u32 base_addr = get_desc_base(seg_desc);
37817f29 4048
98899aa0 4049 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 4050}
4051
37817f29
IE		 4052static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4053{
4054 struct kvm_segment kvm_seg;
4055
3e6e0aab 4056 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4057 return kvm_seg.selector;
4058}
4059
4060static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
4061 u16 selector,
4062 struct kvm_segment *kvm_seg)
4063{
4064 struct desc_struct seg_desc;
4065
4066 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
4067 return 1;
4068 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
4069 return 0;
4070}
4071
2259e3a7 4072static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4073{
4074 struct kvm_segment segvar = {
4075 .base = selector << 4,
4076 .limit = 0xffff,
4077 .selector = selector,
4078 .type = 3,
4079 .present = 1,
4080 .dpl = 3,
4081 .db = 0,
4082 .s = 1,
4083 .l = 0,
4084 .g = 0,
4085 .avl = 0,
4086 .unusable = 0,
4087 };
4088 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4089 return 0;
4090}
4091
3e6e0aab
GT		 4092int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4093 int type_bits, int seg)
37817f29
IE		 4094{
4095 struct kvm_segment kvm_seg;
4096
f4bbd9aa
AK		 4097 if (!(vcpu->arch.cr0 & X86_CR0_PE))
4098 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 4099 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4100 return 1;
4101 kvm_seg.type |= type_bits;
4102
4103 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4104 seg != VCPU_SREG_LDTR)
4105 if (!kvm_seg.s)
4106 kvm_seg.unusable = 1;
4107
3e6e0aab 4108 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4109 return 0;
4110}
4111
4112static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4113 struct tss_segment_32 *tss)
4114{
4115 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4116 tss->eip = kvm_rip_read(vcpu);
37817f29 4117 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4118 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4119 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4120 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4121 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4122 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4123 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4124 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4125 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4126 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4127 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4128 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4129 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4130 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4131 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4132 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4133}
4134
4135static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4136 struct tss_segment_32 *tss)
4137{
4138 kvm_set_cr3(vcpu, tss->cr3);
4139
5fdbf976 4140 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 4141 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
4142
5fdbf976
MT		 4143 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4144 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4145 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4146 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4147 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4148 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4149 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4150 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4151
3e6e0aab 4152 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 4153 return 1;
4154
3e6e0aab 4155 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4156 return 1;
4157
3e6e0aab 4158 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4159 return 1;
4160
3e6e0aab 4161 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4162 return 1;
4163
3e6e0aab 4164 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4165 return 1;
4166
3e6e0aab 4167 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 4168 return 1;
4169
3e6e0aab 4170 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 4171 return 1;
4172 return 0;
4173}
4174
4175static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4176 struct tss_segment_16 *tss)
4177{
5fdbf976 4178 tss->ip = kvm_rip_read(vcpu);
37817f29 4179 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4180 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4181 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4182 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4183 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4184 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4185 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4186 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4187 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4188
4189 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4190 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4191 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4192 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4193 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4194 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
4195}
4196
4197static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4198 struct tss_segment_16 *tss)
4199{
5fdbf976 4200 kvm_rip_write(vcpu, tss->ip);
37817f29 4201 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 4202 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4203 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4204 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4205 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4206 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4207 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4208 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4209 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 4210
3e6e0aab 4211 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 4212 return 1;
4213
3e6e0aab 4214 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4215 return 1;
4216
3e6e0aab 4217 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4218 return 1;
4219
3e6e0aab 4220 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4221 return 1;
4222
3e6e0aab 4223 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4224 return 1;
4225 return 0;
4226}
4227
8b2cf73c 4228static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 4229 u16 old_tss_sel, u32 old_tss_base,
4230 struct desc_struct *nseg_desc)
37817f29
IE		 4231{
4232 struct tss_segment_16 tss_segment_16;
4233 int ret = 0;
4234
34198bf8
MT		 4235 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4236 sizeof tss_segment_16))
37817f29
IE		 4237 goto out;
4238
4239 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 4240
34198bf8
MT		 4241 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4242 sizeof tss_segment_16))
37817f29 4243 goto out;
34198bf8
MT		 4244
4245 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4246 &tss_segment_16, sizeof tss_segment_16))
4247 goto out;
4248
b237ac37
GN		 4249 if (old_tss_sel != 0xffff) {
4250 tss_segment_16.prev_task_link = old_tss_sel;
4251
4252 if (kvm_write_guest(vcpu->kvm,
4253 get_tss_base_addr(vcpu, nseg_desc),
4254 &tss_segment_16.prev_task_link,
4255 sizeof tss_segment_16.prev_task_link))
4256 goto out;
4257 }
4258
37817f29
IE		 4259 if (load_state_from_tss16(vcpu, &tss_segment_16))
4260 goto out;
4261
4262 ret = 1;
4263out:
4264 return ret;
4265}
4266
8b2cf73c 4267static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 4268 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 4269 struct desc_struct *nseg_desc)
4270{
4271 struct tss_segment_32 tss_segment_32;
4272 int ret = 0;
4273
34198bf8
MT		 4274 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4275 sizeof tss_segment_32))
37817f29
IE		 4276 goto out;
4277
4278 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 4279
34198bf8
MT		 4280 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4281 sizeof tss_segment_32))
4282 goto out;
4283
4284 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4285 &tss_segment_32, sizeof tss_segment_32))
37817f29 4286 goto out;
34198bf8 4287
b237ac37
GN		 4288 if (old_tss_sel != 0xffff) {
4289 tss_segment_32.prev_task_link = old_tss_sel;
4290
4291 if (kvm_write_guest(vcpu->kvm,
4292 get_tss_base_addr(vcpu, nseg_desc),
4293 &tss_segment_32.prev_task_link,
4294 sizeof tss_segment_32.prev_task_link))
4295 goto out;
4296 }
4297
37817f29
IE		 4298 if (load_state_from_tss32(vcpu, &tss_segment_32))
4299 goto out;
4300
4301 ret = 1;
4302out:
4303 return ret;
4304}
4305
4306int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4307{
4308 struct kvm_segment tr_seg;
4309 struct desc_struct cseg_desc;
4310 struct desc_struct nseg_desc;
4311 int ret = 0;
34198bf8
MT		 4312 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4313 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 4314
34198bf8 4315 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 4316
34198bf8
MT		 4317 /* FIXME: Handle errors. Failure to read either TSS or their
4318 * descriptors should generate a pagefault.
4319 */
37817f29
IE		 4320 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4321 goto out;
4322
34198bf8 4323 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 4324 goto out;
4325
37817f29
IE		 4326 if (reason != TASK_SWITCH_IRET) {
4327 int cpl;
4328
4329 cpl = kvm_x86_ops->get_cpl(vcpu);
4330 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4331 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4332 return 1;
4333 }
4334 }
4335
46a359e7 4336 if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) {
37817f29
IE		 4337 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4338 return 1;
4339 }
4340
4341 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 4342 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 4343 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 4344 }
4345
4346 if (reason == TASK_SWITCH_IRET) {
4347 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4348 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
4349 }
4350
64a7ec06
GN		 4351 /* set back link to prev task only if NT bit is set in eflags
4352 note that old_tss_sel is not used afetr this point */
4353 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4354 old_tss_sel = 0xffff;
37817f29 4355
b237ac37
GN		 4356 /* set back link to prev task only if NT bit is set in eflags
4357 note that old_tss_sel is not used afetr this point */
4358 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4359 old_tss_sel = 0xffff;
4360
37817f29 4361 if (nseg_desc.type & 8)
b237ac37
GN		 4362 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4363 old_tss_base, &nseg_desc);
37817f29 4364 else
b237ac37
GN		 4365 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4366 old_tss_base, &nseg_desc);
37817f29
IE		 4367
4368 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
4369 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4370 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
4371 }
4372
4373 if (reason != TASK_SWITCH_IRET) {
3fe913e7 4374 nseg_desc.type |= (1 << 1);
37817f29
IE		 4375 save_guest_segment_descriptor(vcpu, tss_selector,
4376 &nseg_desc);
4377 }
4378
4379 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4380 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4381 tr_seg.type = 11;
3e6e0aab 4382 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 4383out:
37817f29
IE		 4384 return ret;
4385}
4386EXPORT_SYMBOL_GPL(kvm_task_switch);
4387
b6c7a5dc
HB		 4388int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4389 struct kvm_sregs *sregs)
4390{
4391 int mmu_reset_needed = 0;
923c61bb 4392 int pending_vec, max_bits;
b6c7a5dc
HB		 4393 struct descriptor_table dt;
4394
4395 vcpu_load(vcpu);
4396
4397 dt.limit = sregs->idt.limit;
4398 dt.base = sregs->idt.base;
4399 kvm_x86_ops->set_idt(vcpu, &dt);
4400 dt.limit = sregs->gdt.limit;
4401 dt.base = sregs->gdt.base;
4402 kvm_x86_ops->set_gdt(vcpu, &dt);
4403
ad312c7c
ZX		 4404 vcpu->arch.cr2 = sregs->cr2;
4405 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4406 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4407
2d3ad1f4 4408 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4409
ad312c7c 4410 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 4411 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4412 kvm_set_apic_base(vcpu, sregs->apic_base);
4413
4414 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4415
ad312c7c 4416 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 4417 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4418 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4419
ad312c7c 4420 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 4421 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4422 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 4423 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 4424
4425 if (mmu_reset_needed)
4426 kvm_mmu_reset_context(vcpu);
4427
923c61bb
GN		 4428 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4429 pending_vec = find_first_bit(
4430 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4431 if (pending_vec < max_bits) {
66fd3f7f 4432 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4433 pr_debug("Set back pending irq %d\n", pending_vec);
4434 if (irqchip_in_kernel(vcpu->kvm))
4435 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4436 }
4437
3e6e0aab
GT		 4438 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4439 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4440 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4441 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4442 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4443 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4444
3e6e0aab
GT		 4445 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4446 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4447
5f0269f5
ME		 4448 update_cr8_intercept(vcpu);
4449
9c3e4aab 4450 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4451 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab
MT		 4452 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4453 !(vcpu->arch.cr0 & X86_CR0_PE))
4454 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4455
b6c7a5dc
HB		 4456 vcpu_put(vcpu);
4457
4458 return 0;
4459}
4460
d0bfb940
JK		 4461int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4462 struct kvm_guest_debug *dbg)
b6c7a5dc 4463{
ae675ef0 4464 int i, r;
b6c7a5dc
HB		 4465
4466 vcpu_load(vcpu);
4467
ae675ef0
JK		 4468 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
4469 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
4470 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4471 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4472 vcpu->arch.switch_db_regs =
4473 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4474 } else {
4475 for (i = 0; i < KVM_NR_DB_REGS; i++)
4476 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4477 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4478 }
4479
b6c7a5dc
HB		 4480 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
4481
d0bfb940
JK		 4482 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4483 kvm_queue_exception(vcpu, DB_VECTOR);
4484 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
4485 kvm_queue_exception(vcpu, BP_VECTOR);
4486
b6c7a5dc
HB		 4487 vcpu_put(vcpu);
4488
4489 return r;
4490}
4491
d0752060
HB		 4492/*
4493 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4494 * we have asm/x86/processor.h
4495 */
4496struct fxsave {
4497 u16 cwd;
4498 u16 swd;
4499 u16 twd;
4500 u16 fop;
4501 u64 rip;
4502 u64 rdp;
4503 u32 mxcsr;
4504 u32 mxcsr_mask;
4505 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4506#ifdef CONFIG_X86_64
4507 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4508#else
4509 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4510#endif
4511};
4512
8b006791
ZX		 4513/*
4514 * Translate a guest virtual address to a guest physical address.
4515 */
4516int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4517 struct kvm_translation *tr)
4518{
4519 unsigned long vaddr = tr->linear_address;
4520 gpa_t gpa;
4521
4522 vcpu_load(vcpu);
72dc67a6 4523 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4524 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4525 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4526 tr->physical_address = gpa;
4527 tr->valid = gpa != UNMAPPED_GVA;
4528 tr->writeable = 1;
4529 tr->usermode = 0;
8b006791
ZX		 4530 vcpu_put(vcpu);
4531
4532 return 0;
4533}
4534
d0752060
HB		 4535int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4536{
ad312c7c 4537 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4538
4539 vcpu_load(vcpu);
4540
4541 memcpy(fpu->fpr, fxsave->st_space, 128);
4542 fpu->fcw = fxsave->cwd;
4543 fpu->fsw = fxsave->swd;
4544 fpu->ftwx = fxsave->twd;
4545 fpu->last_opcode = fxsave->fop;
4546 fpu->last_ip = fxsave->rip;
4547 fpu->last_dp = fxsave->rdp;
4548 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4549
4550 vcpu_put(vcpu);
4551
4552 return 0;
4553}
4554
4555int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4556{
ad312c7c 4557 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4558
4559 vcpu_load(vcpu);
4560
4561 memcpy(fxsave->st_space, fpu->fpr, 128);
4562 fxsave->cwd = fpu->fcw;
4563 fxsave->swd = fpu->fsw;
4564 fxsave->twd = fpu->ftwx;
4565 fxsave->fop = fpu->last_opcode;
4566 fxsave->rip = fpu->last_ip;
4567 fxsave->rdp = fpu->last_dp;
4568 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4569
4570 vcpu_put(vcpu);
4571
4572 return 0;
4573}
4574
4575void fx_init(struct kvm_vcpu *vcpu)
4576{
4577 unsigned after_mxcsr_mask;
4578
bc1a34f1
AA		 4579 /*
4580 * Touch the fpu the first time in non atomic context as if
4581 * this is the first fpu instruction the exception handler
4582 * will fire before the instruction returns and it'll have to
4583 * allocate ram with GFP_KERNEL.
4584 */
4585 if (!used_math())
d6e88aec 4586 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4587
d0752060
HB		 4588 /* Initialize guest FPU by resetting ours and saving into guest's */
4589 preempt_disable();
d6e88aec
AK		 4590 kvm_fx_save(&vcpu->arch.host_fx_image);
4591 kvm_fx_finit();
4592 kvm_fx_save(&vcpu->arch.guest_fx_image);
4593 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4594 preempt_enable();
4595
ad312c7c 4596 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4597 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4598 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4599 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4600 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4601}
4602EXPORT_SYMBOL_GPL(fx_init);
4603
4604void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4605{
4606 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4607 return;
4608
4609 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4610 kvm_fx_save(&vcpu->arch.host_fx_image);
4611 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4612}
4613EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4614
4615void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4616{
4617 if (!vcpu->guest_fpu_loaded)
4618 return;
4619
4620 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4621 kvm_fx_save(&vcpu->arch.guest_fx_image);
4622 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4623 ++vcpu->stat.fpu_reload;
d0752060
HB		 4624}
4625EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4626
4627void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4628{
7f1ea208
JR		 4629 if (vcpu->arch.time_page) {
4630 kvm_release_page_dirty(vcpu->arch.time_page);
4631 vcpu->arch.time_page = NULL;
4632 }
4633
e9b11c17
ZX		 4634 kvm_x86_ops->vcpu_free(vcpu);
4635}
4636
4637struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4638 unsigned int id)
4639{
26e5215f
AK		 4640 return kvm_x86_ops->vcpu_create(kvm, id);
4641}
e9b11c17 4642
26e5215f
AK		 4643int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4644{
4645 int r;
e9b11c17
ZX		 4646
4647 /* We do fxsave: this must be aligned. */
ad312c7c 4648 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4649
0bed3b56 4650 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4651 vcpu_load(vcpu);
4652 r = kvm_arch_vcpu_reset(vcpu);
4653 if (r == 0)
4654 r = kvm_mmu_setup(vcpu);
4655 vcpu_put(vcpu);
4656 if (r < 0)
4657 goto free_vcpu;
4658
26e5215f 4659 return 0;
e9b11c17
ZX		 4660free_vcpu:
4661 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4662 return r;
e9b11c17
ZX		 4663}
4664
d40ccc62 4665void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4666{
4667 vcpu_load(vcpu);
4668 kvm_mmu_unload(vcpu);
4669 vcpu_put(vcpu);
4670
4671 kvm_x86_ops->vcpu_free(vcpu);
4672}
4673
4674int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4675{
448fa4a9
JK		 4676 vcpu->arch.nmi_pending = false;
4677 vcpu->arch.nmi_injected = false;
4678
42dbaa5a
JK		 4679 vcpu->arch.switch_db_regs = 0;
4680 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4681 vcpu->arch.dr6 = DR6_FIXED_1;
4682 vcpu->arch.dr7 = DR7_FIXED_1;
4683
e9b11c17
ZX		 4684 return kvm_x86_ops->vcpu_reset(vcpu);
4685}
4686
4687void kvm_arch_hardware_enable(void *garbage)
4688{
4689 kvm_x86_ops->hardware_enable(garbage);
4690}
4691
4692void kvm_arch_hardware_disable(void *garbage)
4693{
4694 kvm_x86_ops->hardware_disable(garbage);
4695}
4696
4697int kvm_arch_hardware_setup(void)
4698{
4699 return kvm_x86_ops->hardware_setup();
4700}
4701
4702void kvm_arch_hardware_unsetup(void)
4703{
4704 kvm_x86_ops->hardware_unsetup();
4705}
4706
4707void kvm_arch_check_processor_compat(void *rtn)
4708{
4709 kvm_x86_ops->check_processor_compatibility(rtn);
4710}
4711
4712int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4713{
4714 struct page *page;
4715 struct kvm *kvm;
4716 int r;
4717
4718 BUG_ON(vcpu->kvm == NULL);
4719 kvm = vcpu->kvm;
4720
ad312c7c 4721 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 4722 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 4723 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4724 else
a4535290 4725 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4726
4727 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4728 if (!page) {
4729 r = -ENOMEM;
4730 goto fail;
4731 }
ad312c7c 4732 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4733
4734 r = kvm_mmu_create(vcpu);
4735 if (r < 0)
4736 goto fail_free_pio_data;
4737
4738 if (irqchip_in_kernel(kvm)) {
4739 r = kvm_create_lapic(vcpu);
4740 if (r < 0)
4741 goto fail_mmu_destroy;
4742 }
4743
890ca9ae
HY		 4744 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
4745 GFP_KERNEL);
4746 if (!vcpu->arch.mce_banks) {
4747 r = -ENOMEM;
4748 goto fail_mmu_destroy;
4749 }
4750 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
4751
e9b11c17
ZX		 4752 return 0;
4753
4754fail_mmu_destroy:
4755 kvm_mmu_destroy(vcpu);
4756fail_free_pio_data:
ad312c7c 4757 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4758fail:
4759 return r;
4760}
4761
4762void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4763{
4764 kvm_free_lapic(vcpu);
3200f405 4765 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4766 kvm_mmu_destroy(vcpu);
3200f405 4767 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4768 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4769}
d19a9cd2
ZX		 4770
4771struct kvm *kvm_arch_create_vm(void)
4772{
4773 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4774
4775 if (!kvm)
4776 return ERR_PTR(-ENOMEM);
4777
f05e70ac 4778 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 4779 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4780
5550af4d
SY		 4781 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4782 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4783
53f658b3
MT		 4784 rdtscll(kvm->arch.vm_init_tsc);
4785
d19a9cd2
ZX		 4786 return kvm;
4787}
4788
4789static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4790{
4791 vcpu_load(vcpu);
4792 kvm_mmu_unload(vcpu);
4793 vcpu_put(vcpu);
4794}
4795
4796static void kvm_free_vcpus(struct kvm *kvm)
4797{
4798 unsigned int i;
988a2cae 4799 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 4800
4801 /*
4802 * Unpin any mmu pages first.
4803 */
988a2cae
GN		 4804 kvm_for_each_vcpu(i, vcpu, kvm)
4805 kvm_unload_vcpu_mmu(vcpu);
4806 kvm_for_each_vcpu(i, vcpu, kvm)
4807 kvm_arch_vcpu_free(vcpu);
4808
4809 mutex_lock(&kvm->lock);
4810 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
4811 kvm->vcpus[i] = NULL;
d19a9cd2 4812
988a2cae
GN		 4813 atomic_set(&kvm->online_vcpus, 0);
4814 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 4815}
4816
ad8ba2cd
SY		 4817void kvm_arch_sync_events(struct kvm *kvm)
4818{
ba4cef31 4819 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4820}
4821
d19a9cd2
ZX		 4822void kvm_arch_destroy_vm(struct kvm *kvm)
4823{
6eb55818 4824 kvm_iommu_unmap_guest(kvm);
7837699f 4825 kvm_free_pit(kvm);
d7deeeb0
ZX		 4826 kfree(kvm->arch.vpic);
4827 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4828 kvm_free_vcpus(kvm);
4829 kvm_free_physmem(kvm);
3d45830c
AK		 4830 if (kvm->arch.apic_access_page)
4831 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4832 if (kvm->arch.ept_identity_pagetable)
4833 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4834 kfree(kvm);
4835}
0de10343
ZX		 4836
4837int kvm_arch_set_memory_region(struct kvm *kvm,
4838 struct kvm_userspace_memory_region *mem,
4839 struct kvm_memory_slot old,
4840 int user_alloc)
4841{
4842 int npages = mem->memory_size >> PAGE_SHIFT;
4843 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4844
4845 /*To keep backward compatibility with older userspace,
4846 *x86 needs to hanlde !user_alloc case.
4847 */
4848 if (!user_alloc) {
4849 if (npages && !old.rmap) {
604b38ac
AA		 4850 unsigned long userspace_addr;
4851
72dc67a6 4852 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4853 userspace_addr = do_mmap(NULL, 0,
4854 npages * PAGE_SIZE,
4855 PROT_READ | PROT_WRITE,
acee3c04 4856 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4857 0);
72dc67a6 4858 up_write(&current->mm->mmap_sem);
0de10343 4859
604b38ac
AA		 4860 if (IS_ERR((void *)userspace_addr))
4861 return PTR_ERR((void *)userspace_addr);
4862
4863 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4864 spin_lock(&kvm->mmu_lock);
4865 memslot->userspace_addr = userspace_addr;
4866 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4867 } else {
4868 if (!old.user_alloc && old.rmap) {
4869 int ret;
4870
72dc67a6 4871 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4872 ret = do_munmap(current->mm, old.userspace_addr,
4873 old.npages * PAGE_SIZE);
72dc67a6 4874 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4875 if (ret < 0)
4876 printk(KERN_WARNING
4877 "kvm_vm_ioctl_set_memory_region: "
4878 "failed to munmap memory\n");
4879 }
4880 }
4881 }
4882
7c8a83b7 4883 spin_lock(&kvm->mmu_lock);
f05e70ac 4884 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4885 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4886 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4887 }
4888
4889 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 4890 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4891 kvm_flush_remote_tlbs(kvm);
4892
4893 return 0;
4894}
1d737c8a 4895
34d4cb8f
MT		 4896void kvm_arch_flush_shadow(struct kvm *kvm)
4897{
4898 kvm_mmu_zap_all(kvm);
8986ecc0 4899 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 4900}
4901
1d737c8a
ZX		 4902int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4903{
a4535290 4904 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 4905 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4906 || vcpu->arch.nmi_pending ||
4907 (kvm_arch_interrupt_allowed(vcpu) &&
4908 kvm_cpu_has_interrupt(vcpu));
1d737c8a 4909}
5736199a 4910
5736199a
ZX		 4911void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4912{
32f88400
MT		 4913 int me;
4914 int cpu = vcpu->cpu;
5736199a
ZX		 4915
4916 if (waitqueue_active(&vcpu->wq)) {
4917 wake_up_interruptible(&vcpu->wq);
4918 ++vcpu->stat.halt_wakeup;
4919 }
32f88400
MT		 4920
4921 me = get_cpu();
4922 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
4923 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
4924 smp_send_reschedule(cpu);
e9571ed5 4925 put_cpu();
5736199a 4926}
78646121
GN		 4927
4928int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
4929{
4930 return kvm_x86_ops->interrupt_allowed(vcpu);
4931}
229456fc
MT		 4932
4933EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
4934EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
4935EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
4936EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
4937EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
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