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KVM: MMU: Use different shadows when EFER.NXE changes
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
043405e1
CO		 40
41#include <asm/uaccess.h>
d825ed0a 42#include <asm/msr.h>
a5f61300 43#include <asm/desc.h>
0bed3b56 44#include <asm/mtrr.h>
043405e1 45
313a3dc7 46#define MAX_IO_MSRS 256
a03490ed
CO		 47#define CR0_RESERVED_BITS \
48 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
49 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
50 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
51#define CR4_RESERVED_BITS \
52 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
53 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
54 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
55 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
56
57#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
50a37eb4
JR		 58/* EFER defaults:
59 * - enable syscall per default because its emulated by KVM
60 * - enable LME and LMA per default on 64 bit KVM
61 */
62#ifdef CONFIG_X86_64
63static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
64#else
65static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
66#endif
313a3dc7 67
ba1389b7
AK		 68#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
69#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 70
674eea0f
AK		 71static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
72 struct kvm_cpuid_entry2 __user *entries);
d8017474
AG		 73struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
74 u32 function, u32 index);
674eea0f 75
97896d04 76struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 77EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 78
417bc304 79struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 80 { "pf_fixed", VCPU_STAT(pf_fixed) },
81 { "pf_guest", VCPU_STAT(pf_guest) },
82 { "tlb_flush", VCPU_STAT(tlb_flush) },
83 { "invlpg", VCPU_STAT(invlpg) },
84 { "exits", VCPU_STAT(exits) },
85 { "io_exits", VCPU_STAT(io_exits) },
86 { "mmio_exits", VCPU_STAT(mmio_exits) },
87 { "signal_exits", VCPU_STAT(signal_exits) },
88 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 89 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 90 { "halt_exits", VCPU_STAT(halt_exits) },
91 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 92 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7 93 { "request_irq", VCPU_STAT(request_irq_exits) },
c4abb7c9 94 { "request_nmi", VCPU_STAT(request_nmi_exits) },
ba1389b7
AK		 95 { "irq_exits", VCPU_STAT(irq_exits) },
96 { "host_state_reload", VCPU_STAT(host_state_reload) },
97 { "efer_reload", VCPU_STAT(efer_reload) },
98 { "fpu_reload", VCPU_STAT(fpu_reload) },
99 { "insn_emulation", VCPU_STAT(insn_emulation) },
100 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 101 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 102 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 103 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
104 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
105 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
106 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
107 { "mmu_flooded", VM_STAT(mmu_flooded) },
108 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 109 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 110 { "mmu_unsync", VM_STAT(mmu_unsync) },
6cffe8ca 111 { "mmu_unsync_global", VM_STAT(mmu_unsync_global) },
0f74a24c 112 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 113 { "largepages", VM_STAT(lpages) },
417bc304
HB		 114 { NULL }
115};
116
5fb76f9b
CO		 117unsigned long segment_base(u16 selector)
118{
119 struct descriptor_table gdt;
a5f61300 120 struct desc_struct *d;
5fb76f9b
CO		 121 unsigned long table_base;
122 unsigned long v;
123
124 if (selector == 0)
125 return 0;
126
127 asm("sgdt %0" : "=m"(gdt));
128 table_base = gdt.base;
129
130 if (selector & 4) { /* from ldt */
131 u16 ldt_selector;
132
133 asm("sldt %0" : "=g"(ldt_selector));
134 table_base = segment_base(ldt_selector);
135 }
a5f61300
AK		 136 d = (struct desc_struct *)(table_base + (selector & ~7));
137 v = d->base0 | ((unsigned long)d->base1 << 16) |
138 ((unsigned long)d->base2 << 24);
5fb76f9b 139#ifdef CONFIG_X86_64
a5f61300
AK		 140 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
141 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 142#endif
143 return v;
144}
145EXPORT_SYMBOL_GPL(segment_base);
146
6866b83e
CO		 147u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
148{
149 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 150 return vcpu->arch.apic_base;
6866b83e 151 else
ad312c7c 152 return vcpu->arch.apic_base;
6866b83e
CO		 153}
154EXPORT_SYMBOL_GPL(kvm_get_apic_base);
155
156void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
157{
158 /* TODO: reserve bits check */
159 if (irqchip_in_kernel(vcpu->kvm))
160 kvm_lapic_set_base(vcpu, data);
161 else
ad312c7c 162 vcpu->arch.apic_base = data;
6866b83e
CO		 163}
164EXPORT_SYMBOL_GPL(kvm_set_apic_base);
165
298101da
AK		 166void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
167{
ad312c7c
ZX		 168 WARN_ON(vcpu->arch.exception.pending);
169 vcpu->arch.exception.pending = true;
170 vcpu->arch.exception.has_error_code = false;
171 vcpu->arch.exception.nr = nr;
298101da
AK		 172}
173EXPORT_SYMBOL_GPL(kvm_queue_exception);
174
c3c91fee
AK		 175void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
176 u32 error_code)
177{
178 ++vcpu->stat.pf_guest;
d8017474 179
71c4dfaf
JR		 180 if (vcpu->arch.exception.pending) {
181 if (vcpu->arch.exception.nr == PF_VECTOR) {
182 printk(KERN_DEBUG "kvm: inject_page_fault:"
183 " double fault 0x%lx\n", addr);
184 vcpu->arch.exception.nr = DF_VECTOR;
185 vcpu->arch.exception.error_code = 0;
186 } else if (vcpu->arch.exception.nr == DF_VECTOR) {
187 /* triple fault -> shutdown */
188 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
189 }
c3c91fee
AK		 190 return;
191 }
ad312c7c 192 vcpu->arch.cr2 = addr;
c3c91fee
AK		 193 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
194}
195
3419ffc8
SY		 196void kvm_inject_nmi(struct kvm_vcpu *vcpu)
197{
198 vcpu->arch.nmi_pending = 1;
199}
200EXPORT_SYMBOL_GPL(kvm_inject_nmi);
201
298101da
AK		 202void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
203{
ad312c7c
ZX		 204 WARN_ON(vcpu->arch.exception.pending);
205 vcpu->arch.exception.pending = true;
206 vcpu->arch.exception.has_error_code = true;
207 vcpu->arch.exception.nr = nr;
208 vcpu->arch.exception.error_code = error_code;
298101da
AK		 209}
210EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
211
212static void __queue_exception(struct kvm_vcpu *vcpu)
213{
ad312c7c
ZX		 214 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
215 vcpu->arch.exception.has_error_code,
216 vcpu->arch.exception.error_code);
298101da
AK		 217}
218
a03490ed
CO		 219/*
220 * Load the pae pdptrs. Return true is they are all valid.
221 */
222int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
223{
224 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
225 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
226 int i;
227 int ret;
ad312c7c 228 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 229
a03490ed
CO		 230 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
231 offset * sizeof(u64), sizeof(pdpte));
232 if (ret < 0) {
233 ret = 0;
234 goto out;
235 }
236 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
237 if ((pdpte[i] & 1) && (pdpte[i] & 0xfffffff0000001e6ull)) {
238 ret = 0;
239 goto out;
240 }
241 }
242 ret = 1;
243
ad312c7c 244 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
a03490ed 245out:
a03490ed
CO		 246
247 return ret;
248}
cc4b6871 249EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 250
d835dfec
AK		 251static bool pdptrs_changed(struct kvm_vcpu *vcpu)
252{
ad312c7c 253 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 254 bool changed = true;
255 int r;
256
257 if (is_long_mode(vcpu) || !is_pae(vcpu))
258 return false;
259
ad312c7c 260 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 261 if (r < 0)
262 goto out;
ad312c7c 263 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 264out:
d835dfec
AK		 265
266 return changed;
267}
268
2d3ad1f4 269void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 270{
271 if (cr0 & CR0_RESERVED_BITS) {
272 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 273 cr0, vcpu->arch.cr0);
c1a5d4f9 274 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 275 return;
276 }
277
278 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
279 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 280 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 281 return;
282 }
283
284 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
285 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
286 "and a clear PE flag\n");
c1a5d4f9 287 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 288 return;
289 }
290
291 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
292#ifdef CONFIG_X86_64
ad312c7c 293 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 294 int cs_db, cs_l;
295
296 if (!is_pae(vcpu)) {
297 printk(KERN_DEBUG "set_cr0: #GP, start paging "
298 "in long mode while PAE is disabled\n");
c1a5d4f9 299 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 300 return;
301 }
302 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
303 if (cs_l) {
304 printk(KERN_DEBUG "set_cr0: #GP, start paging "
305 "in long mode while CS.L == 1\n");
c1a5d4f9 306 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 307 return;
308
309 }
310 } else
311#endif
ad312c7c 312 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 313 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
314 "reserved bits\n");
c1a5d4f9 315 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 316 return;
317 }
318
319 }
320
321 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 322 vcpu->arch.cr0 = cr0;
a03490ed 323
6cffe8ca 324 kvm_mmu_sync_global(vcpu);
a03490ed 325 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 326 return;
327}
2d3ad1f4 328EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 329
2d3ad1f4 330void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 331{
2d3ad1f4 332 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
2714d1d3
FEL		 333 KVMTRACE_1D(LMSW, vcpu,
334 (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)),
335 handler);
a03490ed 336}
2d3ad1f4 337EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 338
2d3ad1f4 339void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 340{
a2edf57f
AK		 341 unsigned long old_cr4 = vcpu->arch.cr4;
342 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
343
a03490ed
CO		 344 if (cr4 & CR4_RESERVED_BITS) {
345 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 346 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 347 return;
348 }
349
350 if (is_long_mode(vcpu)) {
351 if (!(cr4 & X86_CR4_PAE)) {
352 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
353 "in long mode\n");
c1a5d4f9 354 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 355 return;
356 }
a2edf57f
AK		 357 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
358 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 359 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 360 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 361 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 362 return;
363 }
364
365 if (cr4 & X86_CR4_VMXE) {
366 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 367 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 368 return;
369 }
370 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 371 vcpu->arch.cr4 = cr4;
5a41accd 372 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
6cffe8ca 373 kvm_mmu_sync_global(vcpu);
a03490ed 374 kvm_mmu_reset_context(vcpu);
a03490ed 375}
2d3ad1f4 376EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 377
2d3ad1f4 378void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 379{
ad312c7c 380 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 381 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 382 kvm_mmu_flush_tlb(vcpu);
383 return;
384 }
385
a03490ed
CO		 386 if (is_long_mode(vcpu)) {
387 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
388 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 389 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 390 return;
391 }
392 } else {
393 if (is_pae(vcpu)) {
394 if (cr3 & CR3_PAE_RESERVED_BITS) {
395 printk(KERN_DEBUG
396 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 397 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 398 return;
399 }
400 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
401 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
402 "reserved bits\n");
c1a5d4f9 403 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 404 return;
405 }
406 }
407 /*
408 * We don't check reserved bits in nonpae mode, because
409 * this isn't enforced, and VMware depends on this.
410 */
411 }
412
a03490ed
CO		 413 /*
414 * Does the new cr3 value map to physical memory? (Note, we
415 * catch an invalid cr3 even in real-mode, because it would
416 * cause trouble later on when we turn on paging anyway.)
417 *
418 * A real CPU would silently accept an invalid cr3 and would
419 * attempt to use it - with largely undefined (and often hard
420 * to debug) behavior on the guest side.
421 */
422 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 423 kvm_inject_gp(vcpu, 0);
a03490ed 424 else {
ad312c7c
ZX		 425 vcpu->arch.cr3 = cr3;
426 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 427 }
a03490ed 428}
2d3ad1f4 429EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 430
2d3ad1f4 431void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 432{
433 if (cr8 & CR8_RESERVED_BITS) {
434 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 435 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 436 return;
437 }
438 if (irqchip_in_kernel(vcpu->kvm))
439 kvm_lapic_set_tpr(vcpu, cr8);
440 else
ad312c7c 441 vcpu->arch.cr8 = cr8;
a03490ed 442}
2d3ad1f4 443EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 444
2d3ad1f4 445unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 446{
447 if (irqchip_in_kernel(vcpu->kvm))
448 return kvm_lapic_get_cr8(vcpu);
449 else
ad312c7c 450 return vcpu->arch.cr8;
a03490ed 451}
2d3ad1f4 452EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 453
d8017474
AG		 454static inline u32 bit(int bitno)
455{
456 return 1 << (bitno & 31);
457}
458
043405e1
CO		 459/*
460 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
461 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
462 *
463 * This list is modified at module load time to reflect the
464 * capabilities of the host cpu.
465 */
466static u32 msrs_to_save[] = {
467 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
468 MSR_K6_STAR,
469#ifdef CONFIG_X86_64
470 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
471#endif
18068523 472 MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
b286d5d8 473 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 474};
475
476static unsigned num_msrs_to_save;
477
478static u32 emulated_msrs[] = {
479 MSR_IA32_MISC_ENABLE,
480};
481
15c4a640
CO		 482static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
483{
f2b4b7dd 484 if (efer & efer_reserved_bits) {
15c4a640
CO		 485 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
486 efer);
c1a5d4f9 487 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 488 return;
489 }
490
491 if (is_paging(vcpu)
ad312c7c 492 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 493 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 494 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 495 return;
496 }
497
1b2fd70c
AG		 498 if (efer & EFER_FFXSR) {
499 struct kvm_cpuid_entry2 *feat;
500
501 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
502 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
503 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
504 kvm_inject_gp(vcpu, 0);
505 return;
506 }
507 }
508
d8017474
AG		 509 if (efer & EFER_SVME) {
510 struct kvm_cpuid_entry2 *feat;
511
512 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
513 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
514 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
515 kvm_inject_gp(vcpu, 0);
516 return;
517 }
518 }
519
15c4a640
CO		 520 kvm_x86_ops->set_efer(vcpu, efer);
521
522 efer &= ~EFER_LMA;
ad312c7c 523 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 524
ad312c7c 525 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 526
527 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
528 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 529}
530
f2b4b7dd
JR		 531void kvm_enable_efer_bits(u64 mask)
532{
533 efer_reserved_bits &= ~mask;
534}
535EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
536
537
15c4a640
CO		 538/*
539 * Writes msr value into into the appropriate "register".
540 * Returns 0 on success, non-0 otherwise.
541 * Assumes vcpu_load() was already called.
542 */
543int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
544{
545 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
546}
547
313a3dc7
CO		 548/*
549 * Adapt set_msr() to msr_io()'s calling convention
550 */
551static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
552{
553 return kvm_set_msr(vcpu, index, *data);
554}
555
18068523
GOC		 556static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
557{
558 static int version;
50d0a0f9
GH		 559 struct pvclock_wall_clock wc;
560 struct timespec now, sys, boot;
18068523
GOC		 561
562 if (!wall_clock)
563 return;
564
565 version++;
566
18068523
GOC		 567 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
568
50d0a0f9
GH		 569 /*
570 * The guest calculates current wall clock time by adding
571 * system time (updated by kvm_write_guest_time below) to the
572 * wall clock specified here. guest system time equals host
573 * system time for us, thus we must fill in host boot time here.
574 */
575 now = current_kernel_time();
576 ktime_get_ts(&sys);
577 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
578
579 wc.sec = boot.tv_sec;
580 wc.nsec = boot.tv_nsec;
581 wc.version = version;
18068523
GOC		 582
583 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
584
585 version++;
586 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 587}
588
50d0a0f9
GH		 589static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
590{
591 uint32_t quotient, remainder;
592
593 /* Don't try to replace with do_div(), this one calculates
594 * "(dividend << 32) / divisor" */
595 __asm__ ( "divl %4"
596 : "=a" (quotient), "=d" (remainder)
597 : "0" (0), "1" (dividend), "r" (divisor) );
598 return quotient;
599}
600
601static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
602{
603 uint64_t nsecs = 1000000000LL;
604 int32_t shift = 0;
605 uint64_t tps64;
606 uint32_t tps32;
607
608 tps64 = tsc_khz * 1000LL;
609 while (tps64 > nsecs*2) {
610 tps64 >>= 1;
611 shift--;
612 }
613
614 tps32 = (uint32_t)tps64;
615 while (tps32 <= (uint32_t)nsecs) {
616 tps32 <<= 1;
617 shift++;
618 }
619
620 hv_clock->tsc_shift = shift;
621 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
622
623 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 624 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 625 hv_clock->tsc_to_system_mul);
626}
627
c8076604
GH		 628static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
629
18068523
GOC		 630static void kvm_write_guest_time(struct kvm_vcpu *v)
631{
632 struct timespec ts;
633 unsigned long flags;
634 struct kvm_vcpu_arch *vcpu = &v->arch;
635 void *shared_kaddr;
636
637 if ((!vcpu->time_page))
638 return;
639
2dea4c84 640 preempt_disable();
c8076604
GH		 641 if (unlikely(vcpu->hv_clock_tsc_khz != __get_cpu_var(cpu_tsc_khz))) {
642 kvm_set_time_scale(__get_cpu_var(cpu_tsc_khz), &vcpu->hv_clock);
643 vcpu->hv_clock_tsc_khz = __get_cpu_var(cpu_tsc_khz);
50d0a0f9 644 }
2dea4c84 645 preempt_enable();
50d0a0f9 646
18068523
GOC		 647 /* Keep irq disabled to prevent changes to the clock */
648 local_irq_save(flags);
649 kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER,
650 &vcpu->hv_clock.tsc_timestamp);
651 ktime_get_ts(&ts);
652 local_irq_restore(flags);
653
654 /* With all the info we got, fill in the values */
655
656 vcpu->hv_clock.system_time = ts.tv_nsec +
657 (NSEC_PER_SEC * (u64)ts.tv_sec);
658 /*
659 * The interface expects us to write an even number signaling that the
660 * update is finished. Since the guest won't see the intermediate
50d0a0f9 661 * state, we just increase by 2 at the end.
18068523 662 */
50d0a0f9 663 vcpu->hv_clock.version += 2;
18068523
GOC		 664
665 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
666
667 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 668 sizeof(vcpu->hv_clock));
18068523
GOC		 669
670 kunmap_atomic(shared_kaddr, KM_USER0);
671
672 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
673}
674
c8076604
GH		 675static int kvm_request_guest_time_update(struct kvm_vcpu *v)
676{
677 struct kvm_vcpu_arch *vcpu = &v->arch;
678
679 if (!vcpu->time_page)
680 return 0;
681 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
682 return 1;
683}
684
9ba075a6
AK		 685static bool msr_mtrr_valid(unsigned msr)
686{
687 switch (msr) {
688 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
689 case MSR_MTRRfix64K_00000:
690 case MSR_MTRRfix16K_80000:
691 case MSR_MTRRfix16K_A0000:
692 case MSR_MTRRfix4K_C0000:
693 case MSR_MTRRfix4K_C8000:
694 case MSR_MTRRfix4K_D0000:
695 case MSR_MTRRfix4K_D8000:
696 case MSR_MTRRfix4K_E0000:
697 case MSR_MTRRfix4K_E8000:
698 case MSR_MTRRfix4K_F0000:
699 case MSR_MTRRfix4K_F8000:
700 case MSR_MTRRdefType:
701 case MSR_IA32_CR_PAT:
702 return true;
703 case 0x2f8:
704 return true;
705 }
706 return false;
707}
708
709static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
710{
0bed3b56
SY		 711 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
712
9ba075a6
AK		 713 if (!msr_mtrr_valid(msr))
714 return 1;
715
0bed3b56
SY		 716 if (msr == MSR_MTRRdefType) {
717 vcpu->arch.mtrr_state.def_type = data;
718 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
719 } else if (msr == MSR_MTRRfix64K_00000)
720 p[0] = data;
721 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
722 p[1 + msr - MSR_MTRRfix16K_80000] = data;
723 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
724 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
725 else if (msr == MSR_IA32_CR_PAT)
726 vcpu->arch.pat = data;
727 else { /* Variable MTRRs */
728 int idx, is_mtrr_mask;
729 u64 *pt;
730
731 idx = (msr - 0x200) / 2;
732 is_mtrr_mask = msr - 0x200 - 2 * idx;
733 if (!is_mtrr_mask)
734 pt =
735 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
736 else
737 pt =
738 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
739 *pt = data;
740 }
741
742 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 743 return 0;
744}
15c4a640
CO		 745
746int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
747{
748 switch (msr) {
15c4a640
CO		 749 case MSR_EFER:
750 set_efer(vcpu, data);
751 break;
15c4a640
CO		 752 case MSR_IA32_MC0_STATUS:
753 pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
b8688d51 754 __func__, data);
15c4a640
CO		 755 break;
756 case MSR_IA32_MCG_STATUS:
757 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
b8688d51 758 __func__, data);
15c4a640 759 break;
c7ac679c
JR		 760 case MSR_IA32_MCG_CTL:
761 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
b8688d51 762 __func__, data);
c7ac679c 763 break;
b5e2fec0
AG		 764 case MSR_IA32_DEBUGCTLMSR:
765 if (!data) {
766 /* We support the non-activated case already */
767 break;
768 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
769 /* Values other than LBR and BTF are vendor-specific,
770 thus reserved and should throw a #GP */
771 return 1;
772 }
773 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
774 __func__, data);
775 break;
15c4a640
CO		 776 case MSR_IA32_UCODE_REV:
777 case MSR_IA32_UCODE_WRITE:
61a6bd67 778 case MSR_VM_HSAVE_PA:
15c4a640 779 break;
9ba075a6
AK		 780 case 0x200 ... 0x2ff:
781 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 782 case MSR_IA32_APICBASE:
783 kvm_set_apic_base(vcpu, data);
784 break;
785 case MSR_IA32_MISC_ENABLE:
ad312c7c 786 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 787 break;
18068523
GOC		 788 case MSR_KVM_WALL_CLOCK:
789 vcpu->kvm->arch.wall_clock = data;
790 kvm_write_wall_clock(vcpu->kvm, data);
791 break;
792 case MSR_KVM_SYSTEM_TIME: {
793 if (vcpu->arch.time_page) {
794 kvm_release_page_dirty(vcpu->arch.time_page);
795 vcpu->arch.time_page = NULL;
796 }
797
798 vcpu->arch.time = data;
799
800 /* we verify if the enable bit is set... */
801 if (!(data & 1))
802 break;
803
804 /* ...but clean it before doing the actual write */
805 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
806
18068523
GOC		 807 vcpu->arch.time_page =
808 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 809
810 if (is_error_page(vcpu->arch.time_page)) {
811 kvm_release_page_clean(vcpu->arch.time_page);
812 vcpu->arch.time_page = NULL;
813 }
814
c8076604 815 kvm_request_guest_time_update(vcpu);
18068523
GOC		 816 break;
817 }
15c4a640 818 default:
565f1fbd 819 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 820 return 1;
821 }
822 return 0;
823}
824EXPORT_SYMBOL_GPL(kvm_set_msr_common);
825
826
827/*
828 * Reads an msr value (of 'msr_index') into 'pdata'.
829 * Returns 0 on success, non-0 otherwise.
830 * Assumes vcpu_load() was already called.
831 */
832int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
833{
834 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
835}
836
9ba075a6
AK		 837static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
838{
0bed3b56
SY		 839 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
840
9ba075a6
AK		 841 if (!msr_mtrr_valid(msr))
842 return 1;
843
0bed3b56
SY		 844 if (msr == MSR_MTRRdefType)
845 *pdata = vcpu->arch.mtrr_state.def_type +
846 (vcpu->arch.mtrr_state.enabled << 10);
847 else if (msr == MSR_MTRRfix64K_00000)
848 *pdata = p[0];
849 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
850 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
851 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
852 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
853 else if (msr == MSR_IA32_CR_PAT)
854 *pdata = vcpu->arch.pat;
855 else { /* Variable MTRRs */
856 int idx, is_mtrr_mask;
857 u64 *pt;
858
859 idx = (msr - 0x200) / 2;
860 is_mtrr_mask = msr - 0x200 - 2 * idx;
861 if (!is_mtrr_mask)
862 pt =
863 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
864 else
865 pt =
866 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
867 *pdata = *pt;
868 }
869
9ba075a6
AK		 870 return 0;
871}
872
15c4a640
CO		 873int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
874{
875 u64 data;
876
877 switch (msr) {
878 case 0xc0010010: /* SYSCFG */
879 case 0xc0010015: /* HWCR */
880 case MSR_IA32_PLATFORM_ID:
881 case MSR_IA32_P5_MC_ADDR:
882 case MSR_IA32_P5_MC_TYPE:
883 case MSR_IA32_MC0_CTL:
884 case MSR_IA32_MCG_STATUS:
885 case MSR_IA32_MCG_CAP:
c7ac679c 886 case MSR_IA32_MCG_CTL:
15c4a640
CO		 887 case MSR_IA32_MC0_MISC:
888 case MSR_IA32_MC0_MISC+4:
889 case MSR_IA32_MC0_MISC+8:
890 case MSR_IA32_MC0_MISC+12:
891 case MSR_IA32_MC0_MISC+16:
a89c1ad2 892 case MSR_IA32_MC0_MISC+20:
15c4a640 893 case MSR_IA32_UCODE_REV:
15c4a640 894 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 895 case MSR_IA32_DEBUGCTLMSR:
896 case MSR_IA32_LASTBRANCHFROMIP:
897 case MSR_IA32_LASTBRANCHTOIP:
898 case MSR_IA32_LASTINTFROMIP:
899 case MSR_IA32_LASTINTTOIP:
61a6bd67 900 case MSR_VM_HSAVE_PA:
7fe29e0f
AS		 901 case MSR_P6_EVNTSEL0:
902 case MSR_P6_EVNTSEL1:
15c4a640
CO		 903 data = 0;
904 break;
9ba075a6
AK		 905 case MSR_MTRRcap:
906 data = 0x500 | KVM_NR_VAR_MTRR;
907 break;
908 case 0x200 ... 0x2ff:
909 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 910 case 0xcd: /* fsb frequency */
911 data = 3;
912 break;
913 case MSR_IA32_APICBASE:
914 data = kvm_get_apic_base(vcpu);
915 break;
916 case MSR_IA32_MISC_ENABLE:
ad312c7c 917 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 918 break;
847f0ad8
AG		 919 case MSR_IA32_PERF_STATUS:
920 /* TSC increment by tick */
921 data = 1000ULL;
922 /* CPU multiplier */
923 data |= (((uint64_t)4ULL) << 40);
924 break;
15c4a640 925 case MSR_EFER:
ad312c7c 926 data = vcpu->arch.shadow_efer;
15c4a640 927 break;
18068523
GOC		 928 case MSR_KVM_WALL_CLOCK:
929 data = vcpu->kvm->arch.wall_clock;
930 break;
931 case MSR_KVM_SYSTEM_TIME:
932 data = vcpu->arch.time;
933 break;
15c4a640
CO		 934 default:
935 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
936 return 1;
937 }
938 *pdata = data;
939 return 0;
940}
941EXPORT_SYMBOL_GPL(kvm_get_msr_common);
942
313a3dc7
CO		 943/*
944 * Read or write a bunch of msrs. All parameters are kernel addresses.
945 *
946 * @return number of msrs set successfully.
947 */
948static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
949 struct kvm_msr_entry *entries,
950 int (*do_msr)(struct kvm_vcpu *vcpu,
951 unsigned index, u64 *data))
952{
953 int i;
954
955 vcpu_load(vcpu);
956
3200f405 957 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 958 for (i = 0; i < msrs->nmsrs; ++i)
959 if (do_msr(vcpu, entries[i].index, &entries[i].data))
960 break;
3200f405 961 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 962
963 vcpu_put(vcpu);
964
965 return i;
966}
967
968/*
969 * Read or write a bunch of msrs. Parameters are user addresses.
970 *
971 * @return number of msrs set successfully.
972 */
973static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
974 int (*do_msr)(struct kvm_vcpu *vcpu,
975 unsigned index, u64 *data),
976 int writeback)
977{
978 struct kvm_msrs msrs;
979 struct kvm_msr_entry *entries;
980 int r, n;
981 unsigned size;
982
983 r = -EFAULT;
984 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
985 goto out;
986
987 r = -E2BIG;
988 if (msrs.nmsrs >= MAX_IO_MSRS)
989 goto out;
990
991 r = -ENOMEM;
992 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
993 entries = vmalloc(size);
994 if (!entries)
995 goto out;
996
997 r = -EFAULT;
998 if (copy_from_user(entries, user_msrs->entries, size))
999 goto out_free;
1000
1001 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1002 if (r < 0)
1003 goto out_free;
1004
1005 r = -EFAULT;
1006 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1007 goto out_free;
1008
1009 r = n;
1010
1011out_free:
1012 vfree(entries);
1013out:
1014 return r;
1015}
1016
018d00d2
ZX		 1017int kvm_dev_ioctl_check_extension(long ext)
1018{
1019 int r;
1020
1021 switch (ext) {
1022 case KVM_CAP_IRQCHIP:
1023 case KVM_CAP_HLT:
1024 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1025 case KVM_CAP_SET_TSS_ADDR:
07716717 1026 case KVM_CAP_EXT_CPUID:
c8076604 1027 case KVM_CAP_CLOCKSOURCE:
7837699f 1028 case KVM_CAP_PIT:
a28e4f5a 1029 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1030 case KVM_CAP_MP_STATE:
ed848624 1031 case KVM_CAP_SYNC_MMU:
52d939a0 1032 case KVM_CAP_REINJECT_CONTROL:
4925663a 1033 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1034 case KVM_CAP_ASSIGN_DEV_IRQ:
018d00d2
ZX		 1035 r = 1;
1036 break;
542472b5
LV		 1037 case KVM_CAP_COALESCED_MMIO:
1038 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1039 break;
774ead3a
AK		 1040 case KVM_CAP_VAPIC:
1041 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1042 break;
f725230a
AK		 1043 case KVM_CAP_NR_VCPUS:
1044 r = KVM_MAX_VCPUS;
1045 break;
a988b910
AK		 1046 case KVM_CAP_NR_MEMSLOTS:
1047 r = KVM_MEMORY_SLOTS;
1048 break;
2f333bcb
MT		 1049 case KVM_CAP_PV_MMU:
1050 r = !tdp_enabled;
1051 break;
62c476c7 1052 case KVM_CAP_IOMMU:
19de40a8 1053 r = iommu_found();
62c476c7 1054 break;
018d00d2
ZX		 1055 default:
1056 r = 0;
1057 break;
1058 }
1059 return r;
1060
1061}
1062
043405e1
CO		 1063long kvm_arch_dev_ioctl(struct file *filp,
1064 unsigned int ioctl, unsigned long arg)
1065{
1066 void __user *argp = (void __user *)arg;
1067 long r;
1068
1069 switch (ioctl) {
1070 case KVM_GET_MSR_INDEX_LIST: {
1071 struct kvm_msr_list __user *user_msr_list = argp;
1072 struct kvm_msr_list msr_list;
1073 unsigned n;
1074
1075 r = -EFAULT;
1076 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1077 goto out;
1078 n = msr_list.nmsrs;
1079 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1080 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1081 goto out;
1082 r = -E2BIG;
1083 if (n < num_msrs_to_save)
1084 goto out;
1085 r = -EFAULT;
1086 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1087 num_msrs_to_save * sizeof(u32)))
1088 goto out;
1089 if (copy_to_user(user_msr_list->indices
1090 + num_msrs_to_save * sizeof(u32),
1091 &emulated_msrs,
1092 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1093 goto out;
1094 r = 0;
1095 break;
1096 }
674eea0f
AK		 1097 case KVM_GET_SUPPORTED_CPUID: {
1098 struct kvm_cpuid2 __user *cpuid_arg = argp;
1099 struct kvm_cpuid2 cpuid;
1100
1101 r = -EFAULT;
1102 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1103 goto out;
1104 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1105 cpuid_arg->entries);
674eea0f
AK		 1106 if (r)
1107 goto out;
1108
1109 r = -EFAULT;
1110 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1111 goto out;
1112 r = 0;
1113 break;
1114 }
043405e1
CO		 1115 default:
1116 r = -EINVAL;
1117 }
1118out:
1119 return r;
1120}
1121
313a3dc7
CO		 1122void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1123{
1124 kvm_x86_ops->vcpu_load(vcpu, cpu);
c8076604 1125 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1126}
1127
1128void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1129{
1130 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1131 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1132}
1133
07716717 1134static int is_efer_nx(void)
313a3dc7 1135{
e286e86e 1136 unsigned long long efer = 0;
313a3dc7 1137
e286e86e 1138 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1139 return efer & EFER_NX;
1140}
1141
1142static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1143{
1144 int i;
1145 struct kvm_cpuid_entry2 *e, *entry;
1146
313a3dc7 1147 entry = NULL;
ad312c7c
ZX		 1148 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1149 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1150 if (e->function == 0x80000001) {
1151 entry = e;
1152 break;
1153 }
1154 }
07716717 1155 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1156 entry->edx &= ~(1 << 20);
1157 printk(KERN_INFO "kvm: guest NX capability removed\n");
1158 }
1159}
1160
07716717 1161/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1162static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1163 struct kvm_cpuid *cpuid,
1164 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1165{
1166 int r, i;
1167 struct kvm_cpuid_entry *cpuid_entries;
1168
1169 r = -E2BIG;
1170 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1171 goto out;
1172 r = -ENOMEM;
1173 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1174 if (!cpuid_entries)
1175 goto out;
1176 r = -EFAULT;
1177 if (copy_from_user(cpuid_entries, entries,
1178 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1179 goto out_free;
1180 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1181 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1182 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1183 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1184 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1185 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1186 vcpu->arch.cpuid_entries[i].index = 0;
1187 vcpu->arch.cpuid_entries[i].flags = 0;
1188 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1189 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1190 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1191 }
1192 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1193 cpuid_fix_nx_cap(vcpu);
1194 r = 0;
1195
1196out_free:
1197 vfree(cpuid_entries);
1198out:
1199 return r;
1200}
1201
1202static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1203 struct kvm_cpuid2 *cpuid,
1204 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1205{
1206 int r;
1207
1208 r = -E2BIG;
1209 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1210 goto out;
1211 r = -EFAULT;
ad312c7c 1212 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1213 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1214 goto out;
ad312c7c 1215 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1216 return 0;
1217
1218out:
1219 return r;
1220}
1221
07716717 1222static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1223 struct kvm_cpuid2 *cpuid,
1224 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1225{
1226 int r;
1227
1228 r = -E2BIG;
ad312c7c 1229 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1230 goto out;
1231 r = -EFAULT;
ad312c7c 1232 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1233 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1234 goto out;
1235 return 0;
1236
1237out:
ad312c7c 1238 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1239 return r;
1240}
1241
07716717 1242static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1243 u32 index)
07716717
DK		 1244{
1245 entry->function = function;
1246 entry->index = index;
1247 cpuid_count(entry->function, entry->index,
19355475 1248 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1249 entry->flags = 0;
1250}
1251
1252static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1253 u32 index, int *nent, int maxnent)
1254{
1255 const u32 kvm_supported_word0_x86_features = bit(X86_FEATURE_FPU) |
1256 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1257 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1258 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1259 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1260 bit(X86_FEATURE_SEP) | bit(X86_FEATURE_PGE) |
1261 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1262 bit(X86_FEATURE_CLFLSH) | bit(X86_FEATURE_MMX) |
1263 bit(X86_FEATURE_FXSR) | bit(X86_FEATURE_XMM) |
1264 bit(X86_FEATURE_XMM2) | bit(X86_FEATURE_SELFSNOOP);
1265 const u32 kvm_supported_word1_x86_features = bit(X86_FEATURE_FPU) |
1266 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1267 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1268 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1269 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1270 bit(X86_FEATURE_PGE) |
1271 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1272 bit(X86_FEATURE_MMX) | bit(X86_FEATURE_FXSR) |
1273 bit(X86_FEATURE_SYSCALL) |
334b8ad7 1274 (is_efer_nx() ? bit(X86_FEATURE_NX) : 0) |
07716717
DK		 1275#ifdef CONFIG_X86_64
1276 bit(X86_FEATURE_LM) |
1277#endif
1b2fd70c 1278 bit(X86_FEATURE_FXSR_OPT) |
07716717
DK		 1279 bit(X86_FEATURE_MMXEXT) |
1280 bit(X86_FEATURE_3DNOWEXT) |
1281 bit(X86_FEATURE_3DNOW);
1282 const u32 kvm_supported_word3_x86_features =
1283 bit(X86_FEATURE_XMM3) | bit(X86_FEATURE_CX16);
1284 const u32 kvm_supported_word6_x86_features =
d8017474
AG		 1285 bit(X86_FEATURE_LAHF_LM) | bit(X86_FEATURE_CMP_LEGACY) |
1286 bit(X86_FEATURE_SVM);
07716717 1287
19355475 1288 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1289 get_cpu();
1290 do_cpuid_1_ent(entry, function, index);
1291 ++*nent;
1292
1293 switch (function) {
1294 case 0:
1295 entry->eax = min(entry->eax, (u32)0xb);
1296 break;
1297 case 1:
1298 entry->edx &= kvm_supported_word0_x86_features;
1299 entry->ecx &= kvm_supported_word3_x86_features;
1300 break;
1301 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1302 * may return different values. This forces us to get_cpu() before
1303 * issuing the first command, and also to emulate this annoying behavior
1304 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1305 case 2: {
1306 int t, times = entry->eax & 0xff;
1307
1308 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1309 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1310 for (t = 1; t < times && *nent < maxnent; ++t) {
1311 do_cpuid_1_ent(&entry[t], function, 0);
1312 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1313 ++*nent;
1314 }
1315 break;
1316 }
1317 /* function 4 and 0xb have additional index. */
1318 case 4: {
14af3f3c 1319 int i, cache_type;
07716717
DK		 1320
1321 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1322 /* read more entries until cache_type is zero */
14af3f3c
HH		 1323 for (i = 1; *nent < maxnent; ++i) {
1324 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1325 if (!cache_type)
1326 break;
14af3f3c
HH		 1327 do_cpuid_1_ent(&entry[i], function, i);
1328 entry[i].flags |=
07716717
DK		 1329 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1330 ++*nent;
1331 }
1332 break;
1333 }
1334 case 0xb: {
14af3f3c 1335 int i, level_type;
07716717
DK		 1336
1337 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1338 /* read more entries until level_type is zero */
14af3f3c 1339 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1340 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1341 if (!level_type)
1342 break;
14af3f3c
HH		 1343 do_cpuid_1_ent(&entry[i], function, i);
1344 entry[i].flags |=
07716717
DK		 1345 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1346 ++*nent;
1347 }
1348 break;
1349 }
1350 case 0x80000000:
1351 entry->eax = min(entry->eax, 0x8000001a);
1352 break;
1353 case 0x80000001:
1354 entry->edx &= kvm_supported_word1_x86_features;
1355 entry->ecx &= kvm_supported_word6_x86_features;
1356 break;
1357 }
1358 put_cpu();
1359}
1360
674eea0f 1361static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1362 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1363{
1364 struct kvm_cpuid_entry2 *cpuid_entries;
1365 int limit, nent = 0, r = -E2BIG;
1366 u32 func;
1367
1368 if (cpuid->nent < 1)
1369 goto out;
1370 r = -ENOMEM;
1371 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1372 if (!cpuid_entries)
1373 goto out;
1374
1375 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1376 limit = cpuid_entries[0].eax;
1377 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1378 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1379 &nent, cpuid->nent);
07716717
DK		 1380 r = -E2BIG;
1381 if (nent >= cpuid->nent)
1382 goto out_free;
1383
1384 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1385 limit = cpuid_entries[nent - 1].eax;
1386 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1387 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1388 &nent, cpuid->nent);
07716717
DK		 1389 r = -EFAULT;
1390 if (copy_to_user(entries, cpuid_entries,
19355475 1391 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1392 goto out_free;
1393 cpuid->nent = nent;
1394 r = 0;
1395
1396out_free:
1397 vfree(cpuid_entries);
1398out:
1399 return r;
1400}
1401
313a3dc7
CO		 1402static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1403 struct kvm_lapic_state *s)
1404{
1405 vcpu_load(vcpu);
ad312c7c 1406 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1407 vcpu_put(vcpu);
1408
1409 return 0;
1410}
1411
1412static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1413 struct kvm_lapic_state *s)
1414{
1415 vcpu_load(vcpu);
ad312c7c 1416 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1417 kvm_apic_post_state_restore(vcpu);
1418 vcpu_put(vcpu);
1419
1420 return 0;
1421}
1422
f77bc6a4
ZX		 1423static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1424 struct kvm_interrupt *irq)
1425{
1426 if (irq->irq < 0 || irq->irq >= 256)
1427 return -EINVAL;
1428 if (irqchip_in_kernel(vcpu->kvm))
1429 return -ENXIO;
1430 vcpu_load(vcpu);
1431
ad312c7c
ZX		 1432 set_bit(irq->irq, vcpu->arch.irq_pending);
1433 set_bit(irq->irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
f77bc6a4
ZX		 1434
1435 vcpu_put(vcpu);
1436
1437 return 0;
1438}
1439
c4abb7c9
JK		 1440static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1441{
1442 vcpu_load(vcpu);
1443 kvm_inject_nmi(vcpu);
1444 vcpu_put(vcpu);
1445
1446 return 0;
1447}
1448
b209749f
AK		 1449static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1450 struct kvm_tpr_access_ctl *tac)
1451{
1452 if (tac->flags)
1453 return -EINVAL;
1454 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1455 return 0;
1456}
1457
313a3dc7
CO		 1458long kvm_arch_vcpu_ioctl(struct file *filp,
1459 unsigned int ioctl, unsigned long arg)
1460{
1461 struct kvm_vcpu *vcpu = filp->private_data;
1462 void __user *argp = (void __user *)arg;
1463 int r;
b772ff36 1464 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1465
1466 switch (ioctl) {
1467 case KVM_GET_LAPIC: {
b772ff36 1468 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1469
b772ff36
DH		 1470 r = -ENOMEM;
1471 if (!lapic)
1472 goto out;
1473 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1474 if (r)
1475 goto out;
1476 r = -EFAULT;
b772ff36 1477 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1478 goto out;
1479 r = 0;
1480 break;
1481 }
1482 case KVM_SET_LAPIC: {
b772ff36
DH		 1483 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1484 r = -ENOMEM;
1485 if (!lapic)
1486 goto out;
313a3dc7 1487 r = -EFAULT;
b772ff36 1488 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1489 goto out;
b772ff36 1490 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1491 if (r)
1492 goto out;
1493 r = 0;
1494 break;
1495 }
f77bc6a4
ZX		 1496 case KVM_INTERRUPT: {
1497 struct kvm_interrupt irq;
1498
1499 r = -EFAULT;
1500 if (copy_from_user(&irq, argp, sizeof irq))
1501 goto out;
1502 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1503 if (r)
1504 goto out;
1505 r = 0;
1506 break;
1507 }
c4abb7c9
JK		 1508 case KVM_NMI: {
1509 r = kvm_vcpu_ioctl_nmi(vcpu);
1510 if (r)
1511 goto out;
1512 r = 0;
1513 break;
1514 }
313a3dc7
CO		 1515 case KVM_SET_CPUID: {
1516 struct kvm_cpuid __user *cpuid_arg = argp;
1517 struct kvm_cpuid cpuid;
1518
1519 r = -EFAULT;
1520 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1521 goto out;
1522 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1523 if (r)
1524 goto out;
1525 break;
1526 }
07716717
DK		 1527 case KVM_SET_CPUID2: {
1528 struct kvm_cpuid2 __user *cpuid_arg = argp;
1529 struct kvm_cpuid2 cpuid;
1530
1531 r = -EFAULT;
1532 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1533 goto out;
1534 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 1535 cpuid_arg->entries);
07716717
DK		 1536 if (r)
1537 goto out;
1538 break;
1539 }
1540 case KVM_GET_CPUID2: {
1541 struct kvm_cpuid2 __user *cpuid_arg = argp;
1542 struct kvm_cpuid2 cpuid;
1543
1544 r = -EFAULT;
1545 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1546 goto out;
1547 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 1548 cpuid_arg->entries);
07716717
DK		 1549 if (r)
1550 goto out;
1551 r = -EFAULT;
1552 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1553 goto out;
1554 r = 0;
1555 break;
1556 }
313a3dc7
CO		 1557 case KVM_GET_MSRS:
1558 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1559 break;
1560 case KVM_SET_MSRS:
1561 r = msr_io(vcpu, argp, do_set_msr, 0);
1562 break;
b209749f
AK		 1563 case KVM_TPR_ACCESS_REPORTING: {
1564 struct kvm_tpr_access_ctl tac;
1565
1566 r = -EFAULT;
1567 if (copy_from_user(&tac, argp, sizeof tac))
1568 goto out;
1569 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1570 if (r)
1571 goto out;
1572 r = -EFAULT;
1573 if (copy_to_user(argp, &tac, sizeof tac))
1574 goto out;
1575 r = 0;
1576 break;
1577 };
b93463aa
AK		 1578 case KVM_SET_VAPIC_ADDR: {
1579 struct kvm_vapic_addr va;
1580
1581 r = -EINVAL;
1582 if (!irqchip_in_kernel(vcpu->kvm))
1583 goto out;
1584 r = -EFAULT;
1585 if (copy_from_user(&va, argp, sizeof va))
1586 goto out;
1587 r = 0;
1588 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1589 break;
1590 }
313a3dc7
CO		 1591 default:
1592 r = -EINVAL;
1593 }
1594out:
b772ff36
DH		 1595 if (lapic)
1596 kfree(lapic);
313a3dc7
CO		 1597 return r;
1598}
1599
1fe779f8
CO		 1600static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1601{
1602 int ret;
1603
1604 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1605 return -1;
1606 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1607 return ret;
1608}
1609
1610static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1611 u32 kvm_nr_mmu_pages)
1612{
1613 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1614 return -EINVAL;
1615
72dc67a6 1616 down_write(&kvm->slots_lock);
1fe779f8
CO		 1617
1618 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1619 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1620
72dc67a6 1621 up_write(&kvm->slots_lock);
1fe779f8
CO		 1622 return 0;
1623}
1624
1625static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1626{
f05e70ac 1627 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1628}
1629
e9f85cde
ZX		 1630gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1631{
1632 int i;
1633 struct kvm_mem_alias *alias;
1634
d69fb81f
ZX		 1635 for (i = 0; i < kvm->arch.naliases; ++i) {
1636 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1637 if (gfn >= alias->base_gfn
1638 && gfn < alias->base_gfn + alias->npages)
1639 return alias->target_gfn + gfn - alias->base_gfn;
1640 }
1641 return gfn;
1642}
1643
1fe779f8
CO		 1644/*
1645 * Set a new alias region. Aliases map a portion of physical memory into
1646 * another portion. This is useful for memory windows, for example the PC
1647 * VGA region.
1648 */
1649static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1650 struct kvm_memory_alias *alias)
1651{
1652 int r, n;
1653 struct kvm_mem_alias *p;
1654
1655 r = -EINVAL;
1656 /* General sanity checks */
1657 if (alias->memory_size & (PAGE_SIZE - 1))
1658 goto out;
1659 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1660 goto out;
1661 if (alias->slot >= KVM_ALIAS_SLOTS)
1662 goto out;
1663 if (alias->guest_phys_addr + alias->memory_size
1664 < alias->guest_phys_addr)
1665 goto out;
1666 if (alias->target_phys_addr + alias->memory_size
1667 < alias->target_phys_addr)
1668 goto out;
1669
72dc67a6 1670 down_write(&kvm->slots_lock);
a1708ce8 1671 spin_lock(&kvm->mmu_lock);
1fe779f8 1672
d69fb81f 1673 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1674 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1675 p->npages = alias->memory_size >> PAGE_SHIFT;
1676 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1677
1678 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1679 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1680 break;
d69fb81f 1681 kvm->arch.naliases = n;
1fe779f8 1682
a1708ce8 1683 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1684 kvm_mmu_zap_all(kvm);
1685
72dc67a6 1686 up_write(&kvm->slots_lock);
1fe779f8
CO		 1687
1688 return 0;
1689
1690out:
1691 return r;
1692}
1693
1694static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1695{
1696 int r;
1697
1698 r = 0;
1699 switch (chip->chip_id) {
1700 case KVM_IRQCHIP_PIC_MASTER:
1701 memcpy(&chip->chip.pic,
1702 &pic_irqchip(kvm)->pics[0],
1703 sizeof(struct kvm_pic_state));
1704 break;
1705 case KVM_IRQCHIP_PIC_SLAVE:
1706 memcpy(&chip->chip.pic,
1707 &pic_irqchip(kvm)->pics[1],
1708 sizeof(struct kvm_pic_state));
1709 break;
1710 case KVM_IRQCHIP_IOAPIC:
1711 memcpy(&chip->chip.ioapic,
1712 ioapic_irqchip(kvm),
1713 sizeof(struct kvm_ioapic_state));
1714 break;
1715 default:
1716 r = -EINVAL;
1717 break;
1718 }
1719 return r;
1720}
1721
1722static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1723{
1724 int r;
1725
1726 r = 0;
1727 switch (chip->chip_id) {
1728 case KVM_IRQCHIP_PIC_MASTER:
1729 memcpy(&pic_irqchip(kvm)->pics[0],
1730 &chip->chip.pic,
1731 sizeof(struct kvm_pic_state));
1732 break;
1733 case KVM_IRQCHIP_PIC_SLAVE:
1734 memcpy(&pic_irqchip(kvm)->pics[1],
1735 &chip->chip.pic,
1736 sizeof(struct kvm_pic_state));
1737 break;
1738 case KVM_IRQCHIP_IOAPIC:
1739 memcpy(ioapic_irqchip(kvm),
1740 &chip->chip.ioapic,
1741 sizeof(struct kvm_ioapic_state));
1742 break;
1743 default:
1744 r = -EINVAL;
1745 break;
1746 }
1747 kvm_pic_update_irq(pic_irqchip(kvm));
1748 return r;
1749}
1750
e0f63cb9
SY		 1751static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1752{
1753 int r = 0;
1754
1755 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
1756 return r;
1757}
1758
1759static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1760{
1761 int r = 0;
1762
1763 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
1764 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
1765 return r;
1766}
1767
52d939a0
MT		 1768static int kvm_vm_ioctl_reinject(struct kvm *kvm,
1769 struct kvm_reinject_control *control)
1770{
1771 if (!kvm->arch.vpit)
1772 return -ENXIO;
1773 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
1774 return 0;
1775}
1776
5bb064dc
ZX		 1777/*
1778 * Get (and clear) the dirty memory log for a memory slot.
1779 */
1780int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
1781 struct kvm_dirty_log *log)
1782{
1783 int r;
1784 int n;
1785 struct kvm_memory_slot *memslot;
1786 int is_dirty = 0;
1787
72dc67a6 1788 down_write(&kvm->slots_lock);
5bb064dc
ZX		 1789
1790 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1791 if (r)
1792 goto out;
1793
1794 /* If nothing is dirty, don't bother messing with page tables. */
1795 if (is_dirty) {
1796 kvm_mmu_slot_remove_write_access(kvm, log->slot);
1797 kvm_flush_remote_tlbs(kvm);
1798 memslot = &kvm->memslots[log->slot];
1799 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
1800 memset(memslot->dirty_bitmap, 0, n);
1801 }
1802 r = 0;
1803out:
72dc67a6 1804 up_write(&kvm->slots_lock);
5bb064dc
ZX		 1805 return r;
1806}
1807
1fe779f8
CO		 1808long kvm_arch_vm_ioctl(struct file *filp,
1809 unsigned int ioctl, unsigned long arg)
1810{
1811 struct kvm *kvm = filp->private_data;
1812 void __user *argp = (void __user *)arg;
1813 int r = -EINVAL;
f0d66275
DH		 1814 /*
1815 * This union makes it completely explicit to gcc-3.x
1816 * that these two variables' stack usage should be
1817 * combined, not added together.
1818 */
1819 union {
1820 struct kvm_pit_state ps;
1821 struct kvm_memory_alias alias;
1822 } u;
1fe779f8
CO		 1823
1824 switch (ioctl) {
1825 case KVM_SET_TSS_ADDR:
1826 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1827 if (r < 0)
1828 goto out;
1829 break;
1830 case KVM_SET_MEMORY_REGION: {
1831 struct kvm_memory_region kvm_mem;
1832 struct kvm_userspace_memory_region kvm_userspace_mem;
1833
1834 r = -EFAULT;
1835 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
1836 goto out;
1837 kvm_userspace_mem.slot = kvm_mem.slot;
1838 kvm_userspace_mem.flags = kvm_mem.flags;
1839 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
1840 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
1841 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
1842 if (r)
1843 goto out;
1844 break;
1845 }
1846 case KVM_SET_NR_MMU_PAGES:
1847 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1848 if (r)
1849 goto out;
1850 break;
1851 case KVM_GET_NR_MMU_PAGES:
1852 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
1853 break;
f0d66275 1854 case KVM_SET_MEMORY_ALIAS:
1fe779f8 1855 r = -EFAULT;
f0d66275 1856 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 1857 goto out;
f0d66275 1858 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 1859 if (r)
1860 goto out;
1861 break;
1fe779f8
CO		 1862 case KVM_CREATE_IRQCHIP:
1863 r = -ENOMEM;
d7deeeb0
ZX		 1864 kvm->arch.vpic = kvm_create_pic(kvm);
1865 if (kvm->arch.vpic) {
1fe779f8
CO		 1866 r = kvm_ioapic_init(kvm);
1867 if (r) {
d7deeeb0
ZX		 1868 kfree(kvm->arch.vpic);
1869 kvm->arch.vpic = NULL;
1fe779f8
CO		 1870 goto out;
1871 }
1872 } else
1873 goto out;
399ec807
AK		 1874 r = kvm_setup_default_irq_routing(kvm);
1875 if (r) {
1876 kfree(kvm->arch.vpic);
1877 kfree(kvm->arch.vioapic);
1878 goto out;
1879 }
1fe779f8 1880 break;
7837699f 1881 case KVM_CREATE_PIT:
269e05e4
AK		 1882 mutex_lock(&kvm->lock);
1883 r = -EEXIST;
1884 if (kvm->arch.vpit)
1885 goto create_pit_unlock;
7837699f
SY		 1886 r = -ENOMEM;
1887 kvm->arch.vpit = kvm_create_pit(kvm);
1888 if (kvm->arch.vpit)
1889 r = 0;
269e05e4
AK		 1890 create_pit_unlock:
1891 mutex_unlock(&kvm->lock);
7837699f 1892 break;
4925663a 1893 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 1894 case KVM_IRQ_LINE: {
1895 struct kvm_irq_level irq_event;
1896
1897 r = -EFAULT;
1898 if (copy_from_user(&irq_event, argp, sizeof irq_event))
1899 goto out;
1900 if (irqchip_in_kernel(kvm)) {
4925663a 1901 __s32 status;
1fe779f8 1902 mutex_lock(&kvm->lock);
4925663a
GN		 1903 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
1904 irq_event.irq, irq_event.level);
1fe779f8 1905 mutex_unlock(&kvm->lock);
4925663a
GN		 1906 if (ioctl == KVM_IRQ_LINE_STATUS) {
1907 irq_event.status = status;
1908 if (copy_to_user(argp, &irq_event,
1909 sizeof irq_event))
1910 goto out;
1911 }
1fe779f8
CO		 1912 r = 0;
1913 }
1914 break;
1915 }
1916 case KVM_GET_IRQCHIP: {
1917 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1918 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1919
f0d66275
DH		 1920 r = -ENOMEM;
1921 if (!chip)
1fe779f8 1922 goto out;
f0d66275
DH		 1923 r = -EFAULT;
1924 if (copy_from_user(chip, argp, sizeof *chip))
1925 goto get_irqchip_out;
1fe779f8
CO		 1926 r = -ENXIO;
1927 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1928 goto get_irqchip_out;
1929 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 1930 if (r)
f0d66275 1931 goto get_irqchip_out;
1fe779f8 1932 r = -EFAULT;
f0d66275
DH		 1933 if (copy_to_user(argp, chip, sizeof *chip))
1934 goto get_irqchip_out;
1fe779f8 1935 r = 0;
f0d66275
DH		 1936 get_irqchip_out:
1937 kfree(chip);
1938 if (r)
1939 goto out;
1fe779f8
CO		 1940 break;
1941 }
1942 case KVM_SET_IRQCHIP: {
1943 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1944 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1945
f0d66275
DH		 1946 r = -ENOMEM;
1947 if (!chip)
1fe779f8 1948 goto out;
f0d66275
DH		 1949 r = -EFAULT;
1950 if (copy_from_user(chip, argp, sizeof *chip))
1951 goto set_irqchip_out;
1fe779f8
CO		 1952 r = -ENXIO;
1953 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1954 goto set_irqchip_out;
1955 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 1956 if (r)
f0d66275 1957 goto set_irqchip_out;
1fe779f8 1958 r = 0;
f0d66275
DH		 1959 set_irqchip_out:
1960 kfree(chip);
1961 if (r)
1962 goto out;
1fe779f8
CO		 1963 break;
1964 }
e0f63cb9 1965 case KVM_GET_PIT: {
e0f63cb9 1966 r = -EFAULT;
f0d66275 1967 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 1968 goto out;
1969 r = -ENXIO;
1970 if (!kvm->arch.vpit)
1971 goto out;
f0d66275 1972 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 1973 if (r)
1974 goto out;
1975 r = -EFAULT;
f0d66275 1976 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 1977 goto out;
1978 r = 0;
1979 break;
1980 }
1981 case KVM_SET_PIT: {
e0f63cb9 1982 r = -EFAULT;
f0d66275 1983 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 1984 goto out;
1985 r = -ENXIO;
1986 if (!kvm->arch.vpit)
1987 goto out;
f0d66275 1988 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 1989 if (r)
1990 goto out;
1991 r = 0;
1992 break;
1993 }
52d939a0
MT		 1994 case KVM_REINJECT_CONTROL: {
1995 struct kvm_reinject_control control;
1996 r = -EFAULT;
1997 if (copy_from_user(&control, argp, sizeof(control)))
1998 goto out;
1999 r = kvm_vm_ioctl_reinject(kvm, &control);
2000 if (r)
2001 goto out;
2002 r = 0;
2003 break;
2004 }
1fe779f8
CO		 2005 default:
2006 ;
2007 }
2008out:
2009 return r;
2010}
2011
a16b043c 2012static void kvm_init_msr_list(void)
043405e1
CO		 2013{
2014 u32 dummy[2];
2015 unsigned i, j;
2016
2017 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2018 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2019 continue;
2020 if (j < i)
2021 msrs_to_save[j] = msrs_to_save[i];
2022 j++;
2023 }
2024 num_msrs_to_save = j;
2025}
2026
bbd9b64e
CO		 2027/*
2028 * Only apic need an MMIO device hook, so shortcut now..
2029 */
2030static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2031 gpa_t addr, int len,
2032 int is_write)
bbd9b64e
CO		 2033{
2034 struct kvm_io_device *dev;
2035
ad312c7c
ZX		 2036 if (vcpu->arch.apic) {
2037 dev = &vcpu->arch.apic->dev;
92760499 2038 if (dev->in_range(dev, addr, len, is_write))
bbd9b64e
CO		 2039 return dev;
2040 }
2041 return NULL;
2042}
2043
2044
2045static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2046 gpa_t addr, int len,
2047 int is_write)
bbd9b64e
CO		 2048{
2049 struct kvm_io_device *dev;
2050
92760499 2051 dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
bbd9b64e 2052 if (dev == NULL)
92760499
LV		 2053 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
2054 is_write);
bbd9b64e
CO		 2055 return dev;
2056}
2057
cded19f3
HE		 2058static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2059 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2060{
2061 void *data = val;
10589a46 2062 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2063
2064 while (bytes) {
ad312c7c 2065 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2066 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2067 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2068 int ret;
2069
10589a46
MT		 2070 if (gpa == UNMAPPED_GVA) {
2071 r = X86EMUL_PROPAGATE_FAULT;
2072 goto out;
2073 }
77c2002e 2074 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2075 if (ret < 0) {
2076 r = X86EMUL_UNHANDLEABLE;
2077 goto out;
2078 }
bbd9b64e 2079
77c2002e
IE		 2080 bytes -= toread;
2081 data += toread;
2082 addr += toread;
bbd9b64e 2083 }
10589a46 2084out:
10589a46 2085 return r;
bbd9b64e 2086}
77c2002e 2087
cded19f3
HE		 2088static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2089 struct kvm_vcpu *vcpu)
77c2002e
IE		 2090{
2091 void *data = val;
2092 int r = X86EMUL_CONTINUE;
2093
2094 while (bytes) {
2095 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2096 unsigned offset = addr & (PAGE_SIZE-1);
2097 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2098 int ret;
2099
2100 if (gpa == UNMAPPED_GVA) {
2101 r = X86EMUL_PROPAGATE_FAULT;
2102 goto out;
2103 }
2104 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2105 if (ret < 0) {
2106 r = X86EMUL_UNHANDLEABLE;
2107 goto out;
2108 }
2109
2110 bytes -= towrite;
2111 data += towrite;
2112 addr += towrite;
2113 }
2114out:
2115 return r;
2116}
2117
bbd9b64e 2118
bbd9b64e
CO		 2119static int emulator_read_emulated(unsigned long addr,
2120 void *val,
2121 unsigned int bytes,
2122 struct kvm_vcpu *vcpu)
2123{
2124 struct kvm_io_device *mmio_dev;
2125 gpa_t gpa;
2126
2127 if (vcpu->mmio_read_completed) {
2128 memcpy(val, vcpu->mmio_data, bytes);
2129 vcpu->mmio_read_completed = 0;
2130 return X86EMUL_CONTINUE;
2131 }
2132
ad312c7c 2133 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2134
2135 /* For APIC access vmexit */
2136 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2137 goto mmio;
2138
77c2002e
IE		 2139 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2140 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2141 return X86EMUL_CONTINUE;
2142 if (gpa == UNMAPPED_GVA)
2143 return X86EMUL_PROPAGATE_FAULT;
2144
2145mmio:
2146 /*
2147 * Is this MMIO handled locally?
2148 */
10589a46 2149 mutex_lock(&vcpu->kvm->lock);
92760499 2150 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
bbd9b64e
CO		 2151 if (mmio_dev) {
2152 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
10589a46 2153 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2154 return X86EMUL_CONTINUE;
2155 }
10589a46 2156 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2157
2158 vcpu->mmio_needed = 1;
2159 vcpu->mmio_phys_addr = gpa;
2160 vcpu->mmio_size = bytes;
2161 vcpu->mmio_is_write = 0;
2162
2163 return X86EMUL_UNHANDLEABLE;
2164}
2165
3200f405 2166int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2167 const void *val, int bytes)
bbd9b64e
CO		 2168{
2169 int ret;
2170
2171 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2172 if (ret < 0)
bbd9b64e 2173 return 0;
ad218f85 2174 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2175 return 1;
2176}
2177
2178static int emulator_write_emulated_onepage(unsigned long addr,
2179 const void *val,
2180 unsigned int bytes,
2181 struct kvm_vcpu *vcpu)
2182{
2183 struct kvm_io_device *mmio_dev;
10589a46
MT		 2184 gpa_t gpa;
2185
10589a46 2186 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2187
2188 if (gpa == UNMAPPED_GVA) {
c3c91fee 2189 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2190 return X86EMUL_PROPAGATE_FAULT;
2191 }
2192
2193 /* For APIC access vmexit */
2194 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2195 goto mmio;
2196
2197 if (emulator_write_phys(vcpu, gpa, val, bytes))
2198 return X86EMUL_CONTINUE;
2199
2200mmio:
2201 /*
2202 * Is this MMIO handled locally?
2203 */
10589a46 2204 mutex_lock(&vcpu->kvm->lock);
92760499 2205 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
bbd9b64e
CO		 2206 if (mmio_dev) {
2207 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
10589a46 2208 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2209 return X86EMUL_CONTINUE;
2210 }
10589a46 2211 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2212
2213 vcpu->mmio_needed = 1;
2214 vcpu->mmio_phys_addr = gpa;
2215 vcpu->mmio_size = bytes;
2216 vcpu->mmio_is_write = 1;
2217 memcpy(vcpu->mmio_data, val, bytes);
2218
2219 return X86EMUL_CONTINUE;
2220}
2221
2222int emulator_write_emulated(unsigned long addr,
2223 const void *val,
2224 unsigned int bytes,
2225 struct kvm_vcpu *vcpu)
2226{
2227 /* Crossing a page boundary? */
2228 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2229 int rc, now;
2230
2231 now = -addr & ~PAGE_MASK;
2232 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2233 if (rc != X86EMUL_CONTINUE)
2234 return rc;
2235 addr += now;
2236 val += now;
2237 bytes -= now;
2238 }
2239 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2240}
2241EXPORT_SYMBOL_GPL(emulator_write_emulated);
2242
2243static int emulator_cmpxchg_emulated(unsigned long addr,
2244 const void *old,
2245 const void *new,
2246 unsigned int bytes,
2247 struct kvm_vcpu *vcpu)
2248{
2249 static int reported;
2250
2251 if (!reported) {
2252 reported = 1;
2253 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2254 }
2bacc55c
MT		 2255#ifndef CONFIG_X86_64
2256 /* guests cmpxchg8b have to be emulated atomically */
2257 if (bytes == 8) {
10589a46 2258 gpa_t gpa;
2bacc55c 2259 struct page *page;
c0b49b0d 2260 char *kaddr;
2bacc55c
MT		 2261 u64 val;
2262
10589a46
MT		 2263 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2264
2bacc55c
MT		 2265 if (gpa == UNMAPPED_GVA ||
2266 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2267 goto emul_write;
2268
2269 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2270 goto emul_write;
2271
2272 val = *(u64 *)new;
72dc67a6 2273
2bacc55c 2274 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2275
c0b49b0d
AM		 2276 kaddr = kmap_atomic(page, KM_USER0);
2277 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2278 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2279 kvm_release_page_dirty(page);
2280 }
3200f405 2281emul_write:
2bacc55c
MT		 2282#endif
2283
bbd9b64e
CO		 2284 return emulator_write_emulated(addr, new, bytes, vcpu);
2285}
2286
2287static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2288{
2289 return kvm_x86_ops->get_segment_base(vcpu, seg);
2290}
2291
2292int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2293{
a7052897 2294 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2295 return X86EMUL_CONTINUE;
2296}
2297
2298int emulate_clts(struct kvm_vcpu *vcpu)
2299{
54e445ca 2300 KVMTRACE_0D(CLTS, vcpu, handler);
ad312c7c 2301 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2302 return X86EMUL_CONTINUE;
2303}
2304
2305int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2306{
2307 struct kvm_vcpu *vcpu = ctxt->vcpu;
2308
2309 switch (dr) {
2310 case 0 ... 3:
2311 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2312 return X86EMUL_CONTINUE;
2313 default:
b8688d51 2314 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2315 return X86EMUL_UNHANDLEABLE;
2316 }
2317}
2318
2319int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2320{
2321 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2322 int exception;
2323
2324 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2325 if (exception) {
2326 /* FIXME: better handling */
2327 return X86EMUL_UNHANDLEABLE;
2328 }
2329 return X86EMUL_CONTINUE;
2330}
2331
2332void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2333{
bbd9b64e 2334 u8 opcodes[4];
5fdbf976 2335 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2336 unsigned long rip_linear;
2337
f76c710d 2338 if (!printk_ratelimit())
bbd9b64e
CO		 2339 return;
2340
25be4608
GC		 2341 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2342
77c2002e 2343 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 2344
2345 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2346 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2347}
2348EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2349
14af3f3c 2350static struct x86_emulate_ops emulate_ops = {
77c2002e 2351 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 2352 .read_emulated = emulator_read_emulated,
2353 .write_emulated = emulator_write_emulated,
2354 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2355};
2356
5fdbf976
MT		 2357static void cache_all_regs(struct kvm_vcpu *vcpu)
2358{
2359 kvm_register_read(vcpu, VCPU_REGS_RAX);
2360 kvm_register_read(vcpu, VCPU_REGS_RSP);
2361 kvm_register_read(vcpu, VCPU_REGS_RIP);
2362 vcpu->arch.regs_dirty = ~0;
2363}
2364
bbd9b64e
CO		 2365int emulate_instruction(struct kvm_vcpu *vcpu,
2366 struct kvm_run *run,
2367 unsigned long cr2,
2368 u16 error_code,
571008da 2369 int emulation_type)
bbd9b64e
CO		 2370{
2371 int r;
571008da 2372 struct decode_cache *c;
bbd9b64e 2373
26eef70c 2374 kvm_clear_exception_queue(vcpu);
ad312c7c 2375 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2376 /*
2377 * TODO: fix x86_emulate.c to use guest_read/write_register
2378 * instead of direct ->regs accesses, can save hundred cycles
2379 * on Intel for instructions that don't read/change RSP, for
2380 * for example.
2381 */
2382 cache_all_regs(vcpu);
bbd9b64e
CO		 2383
2384 vcpu->mmio_is_write = 0;
ad312c7c 2385 vcpu->arch.pio.string = 0;
bbd9b64e 2386
571008da 2387 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2388 int cs_db, cs_l;
2389 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2390
ad312c7c
ZX		 2391 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2392 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2393 vcpu->arch.emulate_ctxt.mode =
2394 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2395 ? X86EMUL_MODE_REAL : cs_l
2396 ? X86EMUL_MODE_PROT64 : cs_db
2397 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2398
ad312c7c 2399 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da
SY		 2400
2401 /* Reject the instructions other than VMCALL/VMMCALL when
2402 * try to emulate invalid opcode */
2403 c = &vcpu->arch.emulate_ctxt.decode;
2404 if ((emulation_type & EMULTYPE_TRAP_UD) &&
2405 (!(c->twobyte && c->b == 0x01 &&
2406 (c->modrm_reg == 0 || c->modrm_reg == 3) &&
2407 c->modrm_mod == 3 && c->modrm_rm == 1)))
2408 return EMULATE_FAIL;
2409
f2b5756b 2410 ++vcpu->stat.insn_emulation;
bbd9b64e 2411 if (r) {
f2b5756b 2412 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2413 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2414 return EMULATE_DONE;
2415 return EMULATE_FAIL;
2416 }
2417 }
2418
ad312c7c 2419 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 2420
ad312c7c 2421 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2422 return EMULATE_DO_MMIO;
2423
2424 if ((r || vcpu->mmio_is_write) && run) {
2425 run->exit_reason = KVM_EXIT_MMIO;
2426 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2427 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2428 run->mmio.len = vcpu->mmio_size;
2429 run->mmio.is_write = vcpu->mmio_is_write;
2430 }
2431
2432 if (r) {
2433 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2434 return EMULATE_DONE;
2435 if (!vcpu->mmio_needed) {
2436 kvm_report_emulation_failure(vcpu, "mmio");
2437 return EMULATE_FAIL;
2438 }
2439 return EMULATE_DO_MMIO;
2440 }
2441
ad312c7c 2442 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2443
2444 if (vcpu->mmio_is_write) {
2445 vcpu->mmio_needed = 0;
2446 return EMULATE_DO_MMIO;
2447 }
2448
2449 return EMULATE_DONE;
2450}
2451EXPORT_SYMBOL_GPL(emulate_instruction);
2452
de7d789a
CO		 2453static int pio_copy_data(struct kvm_vcpu *vcpu)
2454{
ad312c7c 2455 void *p = vcpu->arch.pio_data;
0f346074 2456 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 2457 unsigned bytes;
0f346074 2458 int ret;
de7d789a 2459
ad312c7c
ZX		 2460 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2461 if (vcpu->arch.pio.in)
0f346074 2462 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 2463 else
0f346074
IE		 2464 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2465 return ret;
de7d789a
CO		 2466}
2467
2468int complete_pio(struct kvm_vcpu *vcpu)
2469{
ad312c7c 2470 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2471 long delta;
2472 int r;
5fdbf976 2473 unsigned long val;
de7d789a
CO		 2474
2475 if (!io->string) {
5fdbf976
MT		 2476 if (io->in) {
2477 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2478 memcpy(&val, vcpu->arch.pio_data, io->size);
2479 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2480 }
de7d789a
CO		 2481 } else {
2482 if (io->in) {
2483 r = pio_copy_data(vcpu);
5fdbf976 2484 if (r)
de7d789a 2485 return r;
de7d789a
CO		 2486 }
2487
2488 delta = 1;
2489 if (io->rep) {
2490 delta *= io->cur_count;
2491 /*
2492 * The size of the register should really depend on
2493 * current address size.
2494 */
5fdbf976
MT		 2495 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2496 val -= delta;
2497 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2498 }
2499 if (io->down)
2500 delta = -delta;
2501 delta *= io->size;
5fdbf976
MT		 2502 if (io->in) {
2503 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2504 val += delta;
2505 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2506 } else {
2507 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2508 val += delta;
2509 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2510 }
de7d789a
CO		 2511 }
2512
de7d789a
CO		 2513 io->count -= io->cur_count;
2514 io->cur_count = 0;
2515
2516 return 0;
2517}
2518
2519static void kernel_pio(struct kvm_io_device *pio_dev,
2520 struct kvm_vcpu *vcpu,
2521 void *pd)
2522{
2523 /* TODO: String I/O for in kernel device */
2524
2525 mutex_lock(&vcpu->kvm->lock);
ad312c7c
ZX		 2526 if (vcpu->arch.pio.in)
2527 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2528 vcpu->arch.pio.size,
de7d789a
CO		 2529 pd);
2530 else
ad312c7c
ZX		 2531 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2532 vcpu->arch.pio.size,
de7d789a
CO		 2533 pd);
2534 mutex_unlock(&vcpu->kvm->lock);
2535}
2536
2537static void pio_string_write(struct kvm_io_device *pio_dev,
2538 struct kvm_vcpu *vcpu)
2539{
ad312c7c
ZX		 2540 struct kvm_pio_request *io = &vcpu->arch.pio;
2541 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2542 int i;
2543
2544 mutex_lock(&vcpu->kvm->lock);
2545 for (i = 0; i < io->cur_count; i++) {
2546 kvm_iodevice_write(pio_dev, io->port,
2547 io->size,
2548 pd);
2549 pd += io->size;
2550 }
2551 mutex_unlock(&vcpu->kvm->lock);
2552}
2553
2554static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2555 gpa_t addr, int len,
2556 int is_write)
de7d789a 2557{
92760499 2558 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
de7d789a
CO		 2559}
2560
2561int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2562 int size, unsigned port)
2563{
2564 struct kvm_io_device *pio_dev;
5fdbf976 2565 unsigned long val;
de7d789a
CO		 2566
2567 vcpu->run->exit_reason = KVM_EXIT_IO;
2568 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2569 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2570 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2571 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2572 vcpu->run->io.port = vcpu->arch.pio.port = port;
2573 vcpu->arch.pio.in = in;
2574 vcpu->arch.pio.string = 0;
2575 vcpu->arch.pio.down = 0;
ad312c7c 2576 vcpu->arch.pio.rep = 0;
de7d789a 2577
2714d1d3
FEL		 2578 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2579 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2580 handler);
2581 else
2582 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2583 handler);
2584
5fdbf976
MT		 2585 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2586 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2587
92760499 2588 pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
de7d789a 2589 if (pio_dev) {
ad312c7c 2590 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2591 complete_pio(vcpu);
2592 return 1;
2593 }
2594 return 0;
2595}
2596EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2597
2598int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2599 int size, unsigned long count, int down,
2600 gva_t address, int rep, unsigned port)
2601{
2602 unsigned now, in_page;
0f346074 2603 int ret = 0;
de7d789a
CO		 2604 struct kvm_io_device *pio_dev;
2605
2606 vcpu->run->exit_reason = KVM_EXIT_IO;
2607 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2608 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2609 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2610 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2611 vcpu->run->io.port = vcpu->arch.pio.port = port;
2612 vcpu->arch.pio.in = in;
2613 vcpu->arch.pio.string = 1;
2614 vcpu->arch.pio.down = down;
ad312c7c 2615 vcpu->arch.pio.rep = rep;
de7d789a 2616
2714d1d3
FEL		 2617 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2618 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2619 handler);
2620 else
2621 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2622 handler);
2623
de7d789a
CO		 2624 if (!count) {
2625 kvm_x86_ops->skip_emulated_instruction(vcpu);
2626 return 1;
2627 }
2628
2629 if (!down)
2630 in_page = PAGE_SIZE - offset_in_page(address);
2631 else
2632 in_page = offset_in_page(address) + size;
2633 now = min(count, (unsigned long)in_page / size);
0f346074 2634 if (!now)
de7d789a 2635 now = 1;
de7d789a
CO		 2636 if (down) {
2637 /*
2638 * String I/O in reverse. Yuck. Kill the guest, fix later.
2639 */
2640 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2641 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2642 return 1;
2643 }
2644 vcpu->run->io.count = now;
ad312c7c 2645 vcpu->arch.pio.cur_count = now;
de7d789a 2646
ad312c7c 2647 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2648 kvm_x86_ops->skip_emulated_instruction(vcpu);
2649
0f346074 2650 vcpu->arch.pio.guest_gva = address;
de7d789a 2651
92760499
LV		 2652 pio_dev = vcpu_find_pio_dev(vcpu, port,
2653 vcpu->arch.pio.cur_count,
2654 !vcpu->arch.pio.in);
ad312c7c 2655 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2656 /* string PIO write */
2657 ret = pio_copy_data(vcpu);
0f346074
IE		 2658 if (ret == X86EMUL_PROPAGATE_FAULT) {
2659 kvm_inject_gp(vcpu, 0);
2660 return 1;
2661 }
2662 if (ret == 0 && pio_dev) {
de7d789a
CO		 2663 pio_string_write(pio_dev, vcpu);
2664 complete_pio(vcpu);
ad312c7c 2665 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2666 ret = 1;
2667 }
2668 } else if (pio_dev)
2669 pr_unimpl(vcpu, "no string pio read support yet, "
2670 "port %x size %d count %ld\n",
2671 port, size, count);
2672
2673 return ret;
2674}
2675EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2676
c8076604
GH		 2677static void bounce_off(void *info)
2678{
2679 /* nothing */
2680}
2681
2682static unsigned int ref_freq;
2683static unsigned long tsc_khz_ref;
2684
2685static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
2686 void *data)
2687{
2688 struct cpufreq_freqs *freq = data;
2689 struct kvm *kvm;
2690 struct kvm_vcpu *vcpu;
2691 int i, send_ipi = 0;
2692
2693 if (!ref_freq)
2694 ref_freq = freq->old;
2695
2696 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
2697 return 0;
2698 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
2699 return 0;
2700 per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
2701
2702 spin_lock(&kvm_lock);
2703 list_for_each_entry(kvm, &vm_list, vm_list) {
2704 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
2705 vcpu = kvm->vcpus[i];
2706 if (!vcpu)
2707 continue;
2708 if (vcpu->cpu != freq->cpu)
2709 continue;
2710 if (!kvm_request_guest_time_update(vcpu))
2711 continue;
2712 if (vcpu->cpu != smp_processor_id())
2713 send_ipi++;
2714 }
2715 }
2716 spin_unlock(&kvm_lock);
2717
2718 if (freq->old < freq->new && send_ipi) {
2719 /*
2720 * We upscale the frequency. Must make the guest
2721 * doesn't see old kvmclock values while running with
2722 * the new frequency, otherwise we risk the guest sees
2723 * time go backwards.
2724 *
2725 * In case we update the frequency for another cpu
2726 * (which might be in guest context) send an interrupt
2727 * to kick the cpu out of guest context. Next time
2728 * guest context is entered kvmclock will be updated,
2729 * so the guest will not see stale values.
2730 */
2731 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
2732 }
2733 return 0;
2734}
2735
2736static struct notifier_block kvmclock_cpufreq_notifier_block = {
2737 .notifier_call = kvmclock_cpufreq_notifier
2738};
2739
f8c16bba 2740int kvm_arch_init(void *opaque)
043405e1 2741{
c8076604 2742 int r, cpu;
f8c16bba
ZX		 2743 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
2744
f8c16bba
ZX		 2745 if (kvm_x86_ops) {
2746 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 2747 r = -EEXIST;
2748 goto out;
f8c16bba
ZX		 2749 }
2750
2751 if (!ops->cpu_has_kvm_support()) {
2752 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 2753 r = -EOPNOTSUPP;
2754 goto out;
f8c16bba
ZX		 2755 }
2756 if (ops->disabled_by_bios()) {
2757 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 2758 r = -EOPNOTSUPP;
2759 goto out;
f8c16bba
ZX		 2760 }
2761
97db56ce
AK		 2762 r = kvm_mmu_module_init();
2763 if (r)
2764 goto out;
2765
2766 kvm_init_msr_list();
2767
f8c16bba 2768 kvm_x86_ops = ops;
56c6d28a 2769 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 2770 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
2771 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
64d4d521 2772 PT_DIRTY_MASK, PT64_NX_MASK, 0, 0);
c8076604
GH		 2773
2774 for_each_possible_cpu(cpu)
2775 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
2776 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
2777 tsc_khz_ref = tsc_khz;
2778 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
2779 CPUFREQ_TRANSITION_NOTIFIER);
2780 }
2781
f8c16bba 2782 return 0;
56c6d28a
ZX		 2783
2784out:
56c6d28a 2785 return r;
043405e1 2786}
8776e519 2787
f8c16bba
ZX		 2788void kvm_arch_exit(void)
2789{
888d256e
JK		 2790 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
2791 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
2792 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 2793 kvm_x86_ops = NULL;
56c6d28a
ZX		 2794 kvm_mmu_module_exit();
2795}
f8c16bba 2796
8776e519
HB		 2797int kvm_emulate_halt(struct kvm_vcpu *vcpu)
2798{
2799 ++vcpu->stat.halt_exits;
2714d1d3 2800 KVMTRACE_0D(HLT, vcpu, handler);
8776e519 2801 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 2802 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 2803 return 1;
2804 } else {
2805 vcpu->run->exit_reason = KVM_EXIT_HLT;
2806 return 0;
2807 }
2808}
2809EXPORT_SYMBOL_GPL(kvm_emulate_halt);
2810
2f333bcb
MT		 2811static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
2812 unsigned long a1)
2813{
2814 if (is_long_mode(vcpu))
2815 return a0;
2816 else
2817 return a0 | ((gpa_t)a1 << 32);
2818}
2819
8776e519
HB		 2820int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
2821{
2822 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 2823 int r = 1;
8776e519 2824
5fdbf976
MT		 2825 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
2826 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
2827 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
2828 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
2829 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 2830
2714d1d3
FEL		 2831 KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler);
2832
8776e519
HB		 2833 if (!is_long_mode(vcpu)) {
2834 nr &= 0xFFFFFFFF;
2835 a0 &= 0xFFFFFFFF;
2836 a1 &= 0xFFFFFFFF;
2837 a2 &= 0xFFFFFFFF;
2838 a3 &= 0xFFFFFFFF;
2839 }
2840
2841 switch (nr) {
b93463aa
AK		 2842 case KVM_HC_VAPIC_POLL_IRQ:
2843 ret = 0;
2844 break;
2f333bcb
MT		 2845 case KVM_HC_MMU_OP:
2846 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
2847 break;
8776e519
HB		 2848 default:
2849 ret = -KVM_ENOSYS;
2850 break;
2851 }
5fdbf976 2852 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 2853 ++vcpu->stat.hypercalls;
2f333bcb 2854 return r;
8776e519
HB		 2855}
2856EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
2857
2858int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
2859{
2860 char instruction[3];
2861 int ret = 0;
5fdbf976 2862 unsigned long rip = kvm_rip_read(vcpu);
8776e519 2863
8776e519
HB		 2864
2865 /*
2866 * Blow out the MMU to ensure that no other VCPU has an active mapping
2867 * to ensure that the updated hypercall appears atomically across all
2868 * VCPUs.
2869 */
2870 kvm_mmu_zap_all(vcpu->kvm);
2871
8776e519 2872 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 2873 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 2874 != X86EMUL_CONTINUE)
2875 ret = -EFAULT;
2876
8776e519
HB		 2877 return ret;
2878}
2879
2880static u64 mk_cr_64(u64 curr_cr, u32 new_val)
2881{
2882 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
2883}
2884
2885void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2886{
2887 struct descriptor_table dt = { limit, base };
2888
2889 kvm_x86_ops->set_gdt(vcpu, &dt);
2890}
2891
2892void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2893{
2894 struct descriptor_table dt = { limit, base };
2895
2896 kvm_x86_ops->set_idt(vcpu, &dt);
2897}
2898
2899void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
2900 unsigned long *rflags)
2901{
2d3ad1f4 2902 kvm_lmsw(vcpu, msw);
8776e519
HB		 2903 *rflags = kvm_x86_ops->get_rflags(vcpu);
2904}
2905
2906unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
2907{
54e445ca
JR		 2908 unsigned long value;
2909
8776e519
HB		 2910 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
2911 switch (cr) {
2912 case 0:
54e445ca
JR		 2913 value = vcpu->arch.cr0;
2914 break;
8776e519 2915 case 2:
54e445ca
JR		 2916 value = vcpu->arch.cr2;
2917 break;
8776e519 2918 case 3:
54e445ca
JR		 2919 value = vcpu->arch.cr3;
2920 break;
8776e519 2921 case 4:
54e445ca
JR		 2922 value = vcpu->arch.cr4;
2923 break;
152ff9be 2924 case 8:
54e445ca
JR		 2925 value = kvm_get_cr8(vcpu);
2926 break;
8776e519 2927 default:
b8688d51 2928 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2929 return 0;
2930 }
54e445ca
JR		 2931 KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value,
2932 (u32)((u64)value >> 32), handler);
2933
2934 return value;
8776e519
HB		 2935}
2936
2937void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
2938 unsigned long *rflags)
2939{
54e445ca
JR		 2940 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val,
2941 (u32)((u64)val >> 32), handler);
2942
8776e519
HB		 2943 switch (cr) {
2944 case 0:
2d3ad1f4 2945 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 2946 *rflags = kvm_x86_ops->get_rflags(vcpu);
2947 break;
2948 case 2:
ad312c7c 2949 vcpu->arch.cr2 = val;
8776e519
HB		 2950 break;
2951 case 3:
2d3ad1f4 2952 kvm_set_cr3(vcpu, val);
8776e519
HB		 2953 break;
2954 case 4:
2d3ad1f4 2955 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 2956 break;
152ff9be 2957 case 8:
2d3ad1f4 2958 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 2959 break;
8776e519 2960 default:
b8688d51 2961 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2962 }
2963}
2964
07716717
DK		 2965static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
2966{
ad312c7c
ZX		 2967 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
2968 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 2969
2970 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
2971 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 2972 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 2973 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 2974 if (ej->function == e->function) {
2975 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2976 return j;
2977 }
2978 }
2979 return 0; /* silence gcc, even though control never reaches here */
2980}
2981
2982/* find an entry with matching function, matching index (if needed), and that
2983 * should be read next (if it's stateful) */
2984static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
2985 u32 function, u32 index)
2986{
2987 if (e->function != function)
2988 return 0;
2989 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
2990 return 0;
2991 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 2992 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 2993 return 0;
2994 return 1;
2995}
2996
d8017474
AG		 2997struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
2998 u32 function, u32 index)
8776e519
HB		 2999{
3000 int i;
d8017474 3001 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3002
ad312c7c 3003 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3004 struct kvm_cpuid_entry2 *e;
3005
ad312c7c 3006 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3007 if (is_matching_cpuid_entry(e, function, index)) {
3008 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3009 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3010 best = e;
3011 break;
3012 }
3013 /*
3014 * Both basic or both extended?
3015 */
3016 if (((e->function ^ function) & 0x80000000) == 0)
3017 if (!best || e->function > best->function)
3018 best = e;
3019 }
d8017474
AG		 3020 return best;
3021}
3022
82725b20
DE		 3023int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3024{
3025 struct kvm_cpuid_entry2 *best;
3026
3027 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3028 if (best)
3029 return best->eax & 0xff;
3030 return 36;
3031}
3032
d8017474
AG		 3033void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3034{
3035 u32 function, index;
3036 struct kvm_cpuid_entry2 *best;
3037
3038 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3039 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3040 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3041 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3042 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3043 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3044 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3045 if (best) {
5fdbf976
MT		 3046 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3047 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3048 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3049 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3050 }
8776e519 3051 kvm_x86_ops->skip_emulated_instruction(vcpu);
2714d1d3 3052 KVMTRACE_5D(CPUID, vcpu, function,
5fdbf976
MT		 3053 (u32)kvm_register_read(vcpu, VCPU_REGS_RAX),
3054 (u32)kvm_register_read(vcpu, VCPU_REGS_RBX),
3055 (u32)kvm_register_read(vcpu, VCPU_REGS_RCX),
3056 (u32)kvm_register_read(vcpu, VCPU_REGS_RDX), handler);
8776e519
HB		 3057}
3058EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3059
b6c7a5dc
HB		 3060/*
3061 * Check if userspace requested an interrupt window, and that the
3062 * interrupt window is open.
3063 *
3064 * No need to exit to userspace if we already have an interrupt queued.
3065 */
3066static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3067 struct kvm_run *kvm_run)
3068{
ad312c7c 3069 return (!vcpu->arch.irq_summary &&
b6c7a5dc 3070 kvm_run->request_interrupt_window &&
ad312c7c 3071 vcpu->arch.interrupt_window_open &&
b6c7a5dc
HB		 3072 (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF));
3073}
3074
3075static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3076 struct kvm_run *kvm_run)
3077{
3078 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3079 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3080 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3081 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3082 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3083 else
b6c7a5dc 3084 kvm_run->ready_for_interrupt_injection =
ad312c7c
ZX		 3085 (vcpu->arch.interrupt_window_open &&
3086 vcpu->arch.irq_summary == 0);
b6c7a5dc
HB		 3087}
3088
b93463aa
AK		 3089static void vapic_enter(struct kvm_vcpu *vcpu)
3090{
3091 struct kvm_lapic *apic = vcpu->arch.apic;
3092 struct page *page;
3093
3094 if (!apic || !apic->vapic_addr)
3095 return;
3096
3097 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3098
3099 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3100}
3101
3102static void vapic_exit(struct kvm_vcpu *vcpu)
3103{
3104 struct kvm_lapic *apic = vcpu->arch.apic;
3105
3106 if (!apic || !apic->vapic_addr)
3107 return;
3108
f8b78fa3 3109 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3110 kvm_release_page_dirty(apic->vapic_page);
3111 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3112 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3113}
3114
d7690175 3115static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 3116{
3117 int r;
3118
2e53d63a
MT		 3119 if (vcpu->requests)
3120 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3121 kvm_mmu_unload(vcpu);
3122
b6c7a5dc
HB		 3123 r = kvm_mmu_reload(vcpu);
3124 if (unlikely(r))
3125 goto out;
3126
2f52d58c
AK		 3127 if (vcpu->requests) {
3128 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3129 __kvm_migrate_timers(vcpu);
c8076604
GH		 3130 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3131 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3132 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3133 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3134 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3135 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3136 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3137 &vcpu->requests)) {
3138 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3139 r = 0;
3140 goto out;
3141 }
71c4dfaf
JR		 3142 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3143 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3144 r = 0;
3145 goto out;
3146 }
2f52d58c 3147 }
b93463aa 3148
b6c7a5dc
HB		 3149 preempt_disable();
3150
3151 kvm_x86_ops->prepare_guest_switch(vcpu);
3152 kvm_load_guest_fpu(vcpu);
3153
3154 local_irq_disable();
3155
d7690175 3156 if (vcpu->requests || need_resched() || signal_pending(current)) {
6c142801
AK		 3157 local_irq_enable();
3158 preempt_enable();
3159 r = 1;
3160 goto out;
3161 }
3162
e9571ed5
MT		 3163 vcpu->guest_mode = 1;
3164 /*
3165 * Make sure that guest_mode assignment won't happen after
3166 * testing the pending IRQ vector bitmap.
3167 */
3168 smp_wmb();
3169
ad312c7c 3170 if (vcpu->arch.exception.pending)
298101da
AK		 3171 __queue_exception(vcpu);
3172 else if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3173 kvm_x86_ops->inject_pending_irq(vcpu);
eb9774f0 3174 else
b6c7a5dc
HB		 3175 kvm_x86_ops->inject_pending_vectors(vcpu, kvm_run);
3176
b93463aa
AK		 3177 kvm_lapic_sync_to_vapic(vcpu);
3178
3200f405
MT		 3179 up_read(&vcpu->kvm->slots_lock);
3180
b6c7a5dc
HB		 3181 kvm_guest_enter();
3182
42dbaa5a
JK		 3183 get_debugreg(vcpu->arch.host_dr6, 6);
3184 get_debugreg(vcpu->arch.host_dr7, 7);
3185 if (unlikely(vcpu->arch.switch_db_regs)) {
3186 get_debugreg(vcpu->arch.host_db[0], 0);
3187 get_debugreg(vcpu->arch.host_db[1], 1);
3188 get_debugreg(vcpu->arch.host_db[2], 2);
3189 get_debugreg(vcpu->arch.host_db[3], 3);
3190
3191 set_debugreg(0, 7);
3192 set_debugreg(vcpu->arch.eff_db[0], 0);
3193 set_debugreg(vcpu->arch.eff_db[1], 1);
3194 set_debugreg(vcpu->arch.eff_db[2], 2);
3195 set_debugreg(vcpu->arch.eff_db[3], 3);
3196 }
b6c7a5dc 3197
2714d1d3 3198 KVMTRACE_0D(VMENTRY, vcpu, entryexit);
b6c7a5dc
HB		 3199 kvm_x86_ops->run(vcpu, kvm_run);
3200
42dbaa5a
JK		 3201 if (unlikely(vcpu->arch.switch_db_regs)) {
3202 set_debugreg(0, 7);
3203 set_debugreg(vcpu->arch.host_db[0], 0);
3204 set_debugreg(vcpu->arch.host_db[1], 1);
3205 set_debugreg(vcpu->arch.host_db[2], 2);
3206 set_debugreg(vcpu->arch.host_db[3], 3);
3207 }
3208 set_debugreg(vcpu->arch.host_dr6, 6);
3209 set_debugreg(vcpu->arch.host_dr7, 7);
3210
b6c7a5dc
HB		 3211 vcpu->guest_mode = 0;
3212 local_irq_enable();
3213
3214 ++vcpu->stat.exits;
3215
3216 /*
3217 * We must have an instruction between local_irq_enable() and
3218 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3219 * the interrupt shadow. The stat.exits increment will do nicely.
3220 * But we need to prevent reordering, hence this barrier():
3221 */
3222 barrier();
3223
3224 kvm_guest_exit();
3225
3226 preempt_enable();
3227
3200f405
MT		 3228 down_read(&vcpu->kvm->slots_lock);
3229
b6c7a5dc
HB		 3230 /*
3231 * Profile KVM exit RIPs:
3232 */
3233 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3234 unsigned long rip = kvm_rip_read(vcpu);
3235 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3236 }
3237
ad312c7c
ZX		 3238 if (vcpu->arch.exception.pending && kvm_x86_ops->exception_injected(vcpu))
3239 vcpu->arch.exception.pending = false;
298101da 3240
b93463aa
AK		 3241 kvm_lapic_sync_from_vapic(vcpu);
3242
b6c7a5dc 3243 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3244out:
3245 return r;
3246}
b6c7a5dc 3247
09cec754 3248
d7690175
MT		 3249static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3250{
3251 int r;
3252
3253 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3254 pr_debug("vcpu %d received sipi with vector # %x\n",
3255 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3256 kvm_lapic_reset(vcpu);
5f179287 3257 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3258 if (r)
3259 return r;
3260 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3261 }
3262
d7690175
MT		 3263 down_read(&vcpu->kvm->slots_lock);
3264 vapic_enter(vcpu);
3265
3266 r = 1;
3267 while (r > 0) {
af2152f5 3268 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3269 r = vcpu_enter_guest(vcpu, kvm_run);
3270 else {
3271 up_read(&vcpu->kvm->slots_lock);
3272 kvm_vcpu_block(vcpu);
3273 down_read(&vcpu->kvm->slots_lock);
3274 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 3275 {
3276 switch(vcpu->arch.mp_state) {
3277 case KVM_MP_STATE_HALTED:
d7690175 3278 vcpu->arch.mp_state =
09cec754
GN		 3279 KVM_MP_STATE_RUNNABLE;
3280 case KVM_MP_STATE_RUNNABLE:
3281 break;
3282 case KVM_MP_STATE_SIPI_RECEIVED:
3283 default:
3284 r = -EINTR;
3285 break;
3286 }
3287 }
d7690175
MT		 3288 }
3289
09cec754
GN		 3290 if (r <= 0)
3291 break;
3292
3293 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
3294 if (kvm_cpu_has_pending_timer(vcpu))
3295 kvm_inject_pending_timer_irqs(vcpu);
3296
3297 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3298 r = -EINTR;
3299 kvm_run->exit_reason = KVM_EXIT_INTR;
3300 ++vcpu->stat.request_irq_exits;
3301 }
3302 if (signal_pending(current)) {
3303 r = -EINTR;
3304 kvm_run->exit_reason = KVM_EXIT_INTR;
3305 ++vcpu->stat.signal_exits;
3306 }
3307 if (need_resched()) {
3308 up_read(&vcpu->kvm->slots_lock);
3309 kvm_resched(vcpu);
3310 down_read(&vcpu->kvm->slots_lock);
d7690175 3311 }
b6c7a5dc
HB		 3312 }
3313
d7690175 3314 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3315 post_kvm_run_save(vcpu, kvm_run);
3316
b93463aa
AK		 3317 vapic_exit(vcpu);
3318
b6c7a5dc
HB		 3319 return r;
3320}
3321
3322int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3323{
3324 int r;
3325 sigset_t sigsaved;
3326
3327 vcpu_load(vcpu);
3328
ac9f6dc0
AK		 3329 if (vcpu->sigset_active)
3330 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3331
a4535290 3332 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3333 kvm_vcpu_block(vcpu);
d7690175 3334 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3335 r = -EAGAIN;
3336 goto out;
b6c7a5dc
HB		 3337 }
3338
b6c7a5dc
HB		 3339 /* re-sync apic's tpr */
3340 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3341 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3342
ad312c7c 3343 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3344 r = complete_pio(vcpu);
3345 if (r)
3346 goto out;
3347 }
3348#if CONFIG_HAS_IOMEM
3349 if (vcpu->mmio_needed) {
3350 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3351 vcpu->mmio_read_completed = 1;
3352 vcpu->mmio_needed = 0;
3200f405
MT		 3353
3354 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3355 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3356 vcpu->arch.mmio_fault_cr2, 0,
3357 EMULTYPE_NO_DECODE);
3200f405 3358 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3359 if (r == EMULATE_DO_MMIO) {
3360 /*
3361 * Read-modify-write. Back to userspace.
3362 */
3363 r = 0;
3364 goto out;
3365 }
3366 }
3367#endif
5fdbf976
MT		 3368 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3369 kvm_register_write(vcpu, VCPU_REGS_RAX,
3370 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3371
3372 r = __vcpu_run(vcpu, kvm_run);
3373
3374out:
3375 if (vcpu->sigset_active)
3376 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3377
3378 vcpu_put(vcpu);
3379 return r;
3380}
3381
3382int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3383{
3384 vcpu_load(vcpu);
3385
5fdbf976
MT		 3386 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3387 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3388 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3389 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3390 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3391 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3392 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3393 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3394#ifdef CONFIG_X86_64
5fdbf976
MT		 3395 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3396 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3397 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3398 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3399 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3400 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3401 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3402 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3403#endif
3404
5fdbf976 3405 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3406 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3407
3408 /*
3409 * Don't leak debug flags in case they were set for guest debugging
3410 */
d0bfb940 3411 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
b6c7a5dc
HB		 3412 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3413
3414 vcpu_put(vcpu);
3415
3416 return 0;
3417}
3418
3419int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3420{
3421 vcpu_load(vcpu);
3422
5fdbf976
MT		 3423 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3424 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3425 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3426 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3427 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3428 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3429 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3430 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3431#ifdef CONFIG_X86_64
5fdbf976
MT		 3432 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3433 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3434 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3435 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3436 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3437 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3438 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3439 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3440
b6c7a5dc
HB		 3441#endif
3442
5fdbf976 3443 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3444 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3445
b6c7a5dc 3446
b4f14abd
JK		 3447 vcpu->arch.exception.pending = false;
3448
b6c7a5dc
HB		 3449 vcpu_put(vcpu);
3450
3451 return 0;
3452}
3453
3e6e0aab
GT		 3454void kvm_get_segment(struct kvm_vcpu *vcpu,
3455 struct kvm_segment *var, int seg)
b6c7a5dc 3456{
14af3f3c 3457 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3458}
3459
3460void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3461{
3462 struct kvm_segment cs;
3463
3e6e0aab 3464 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3465 *db = cs.db;
3466 *l = cs.l;
3467}
3468EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3469
3470int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3471 struct kvm_sregs *sregs)
3472{
3473 struct descriptor_table dt;
3474 int pending_vec;
3475
3476 vcpu_load(vcpu);
3477
3e6e0aab
GT		 3478 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3479 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3480 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3481 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3482 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3483 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3484
3e6e0aab
GT		 3485 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3486 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3487
3488 kvm_x86_ops->get_idt(vcpu, &dt);
3489 sregs->idt.limit = dt.limit;
3490 sregs->idt.base = dt.base;
3491 kvm_x86_ops->get_gdt(vcpu, &dt);
3492 sregs->gdt.limit = dt.limit;
3493 sregs->gdt.base = dt.base;
3494
3495 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3496 sregs->cr0 = vcpu->arch.cr0;
3497 sregs->cr2 = vcpu->arch.cr2;
3498 sregs->cr3 = vcpu->arch.cr3;
3499 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3500 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3501 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3502 sregs->apic_base = kvm_get_apic_base(vcpu);
3503
3504 if (irqchip_in_kernel(vcpu->kvm)) {
3505 memset(sregs->interrupt_bitmap, 0,
3506 sizeof sregs->interrupt_bitmap);
3507 pending_vec = kvm_x86_ops->get_irq(vcpu);
3508 if (pending_vec >= 0)
3509 set_bit(pending_vec,
3510 (unsigned long *)sregs->interrupt_bitmap);
3511 } else
ad312c7c 3512 memcpy(sregs->interrupt_bitmap, vcpu->arch.irq_pending,
b6c7a5dc
HB		 3513 sizeof sregs->interrupt_bitmap);
3514
3515 vcpu_put(vcpu);
3516
3517 return 0;
3518}
3519
62d9f0db
MT		 3520int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3521 struct kvm_mp_state *mp_state)
3522{
3523 vcpu_load(vcpu);
3524 mp_state->mp_state = vcpu->arch.mp_state;
3525 vcpu_put(vcpu);
3526 return 0;
3527}
3528
3529int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3530 struct kvm_mp_state *mp_state)
3531{
3532 vcpu_load(vcpu);
3533 vcpu->arch.mp_state = mp_state->mp_state;
3534 vcpu_put(vcpu);
3535 return 0;
3536}
3537
3e6e0aab 3538static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3539 struct kvm_segment *var, int seg)
3540{
14af3f3c 3541 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3542}
3543
37817f29
IE		 3544static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3545 struct kvm_segment *kvm_desct)
3546{
3547 kvm_desct->base = seg_desc->base0;
3548 kvm_desct->base |= seg_desc->base1 << 16;
3549 kvm_desct->base |= seg_desc->base2 << 24;
3550 kvm_desct->limit = seg_desc->limit0;
3551 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3552 if (seg_desc->g) {
3553 kvm_desct->limit <<= 12;
3554 kvm_desct->limit |= 0xfff;
3555 }
37817f29
IE		 3556 kvm_desct->selector = selector;
3557 kvm_desct->type = seg_desc->type;
3558 kvm_desct->present = seg_desc->p;
3559 kvm_desct->dpl = seg_desc->dpl;
3560 kvm_desct->db = seg_desc->d;
3561 kvm_desct->s = seg_desc->s;
3562 kvm_desct->l = seg_desc->l;
3563 kvm_desct->g = seg_desc->g;
3564 kvm_desct->avl = seg_desc->avl;
3565 if (!selector)
3566 kvm_desct->unusable = 1;
3567 else
3568 kvm_desct->unusable = 0;
3569 kvm_desct->padding = 0;
3570}
3571
b8222ad2
AS		 3572static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3573 u16 selector,
3574 struct descriptor_table *dtable)
37817f29
IE		 3575{
3576 if (selector & 1 << 2) {
3577 struct kvm_segment kvm_seg;
3578
3e6e0aab 3579 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3580
3581 if (kvm_seg.unusable)
3582 dtable->limit = 0;
3583 else
3584 dtable->limit = kvm_seg.limit;
3585 dtable->base = kvm_seg.base;
3586 }
3587 else
3588 kvm_x86_ops->get_gdt(vcpu, dtable);
3589}
3590
3591/* allowed just for 8 bytes segments */
3592static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3593 struct desc_struct *seg_desc)
3594{
98899aa0 3595 gpa_t gpa;
37817f29
IE		 3596 struct descriptor_table dtable;
3597 u16 index = selector >> 3;
3598
b8222ad2 3599 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3600
3601 if (dtable.limit < index * 8 + 7) {
3602 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3603 return 1;
3604 }
98899aa0
MT		 3605 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3606 gpa += index * 8;
3607 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3608}
3609
3610/* allowed just for 8 bytes segments */
3611static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3612 struct desc_struct *seg_desc)
3613{
98899aa0 3614 gpa_t gpa;
37817f29
IE		 3615 struct descriptor_table dtable;
3616 u16 index = selector >> 3;
3617
b8222ad2 3618 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3619
3620 if (dtable.limit < index * 8 + 7)
3621 return 1;
98899aa0
MT		 3622 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3623 gpa += index * 8;
3624 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3625}
3626
3627static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3628 struct desc_struct *seg_desc)
3629{
3630 u32 base_addr;
3631
3632 base_addr = seg_desc->base0;
3633 base_addr |= (seg_desc->base1 << 16);
3634 base_addr |= (seg_desc->base2 << 24);
3635
98899aa0 3636 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3637}
3638
37817f29
IE		 3639static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3640{
3641 struct kvm_segment kvm_seg;
3642
3e6e0aab 3643 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3644 return kvm_seg.selector;
3645}
3646
3647static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3648 u16 selector,
3649 struct kvm_segment *kvm_seg)
3650{
3651 struct desc_struct seg_desc;
3652
3653 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3654 return 1;
3655 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3656 return 0;
3657}
3658
2259e3a7 3659static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 3660{
3661 struct kvm_segment segvar = {
3662 .base = selector << 4,
3663 .limit = 0xffff,
3664 .selector = selector,
3665 .type = 3,
3666 .present = 1,
3667 .dpl = 3,
3668 .db = 0,
3669 .s = 1,
3670 .l = 0,
3671 .g = 0,
3672 .avl = 0,
3673 .unusable = 0,
3674 };
3675 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
3676 return 0;
3677}
3678
3e6e0aab
GT		 3679int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3680 int type_bits, int seg)
37817f29
IE		 3681{
3682 struct kvm_segment kvm_seg;
3683
f4bbd9aa
AK		 3684 if (!(vcpu->arch.cr0 & X86_CR0_PE))
3685 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 3686 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
3687 return 1;
3688 kvm_seg.type |= type_bits;
3689
3690 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
3691 seg != VCPU_SREG_LDTR)
3692 if (!kvm_seg.s)
3693 kvm_seg.unusable = 1;
3694
3e6e0aab 3695 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3696 return 0;
3697}
3698
3699static void save_state_to_tss32(struct kvm_vcpu *vcpu,
3700 struct tss_segment_32 *tss)
3701{
3702 tss->cr3 = vcpu->arch.cr3;
5fdbf976 3703 tss->eip = kvm_rip_read(vcpu);
37817f29 3704 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3705 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3706 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3707 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3708 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3709 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3710 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3711 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3712 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3713 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3714 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3715 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3716 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3717 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
3718 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
3719 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3720 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3721}
3722
3723static int load_state_from_tss32(struct kvm_vcpu *vcpu,
3724 struct tss_segment_32 *tss)
3725{
3726 kvm_set_cr3(vcpu, tss->cr3);
3727
5fdbf976 3728 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 3729 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
3730
5fdbf976
MT		 3731 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
3732 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
3733 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
3734 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
3735 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
3736 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
3737 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
3738 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 3739
3e6e0aab 3740 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 3741 return 1;
3742
3e6e0aab 3743 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3744 return 1;
3745
3e6e0aab 3746 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3747 return 1;
3748
3e6e0aab 3749 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3750 return 1;
3751
3e6e0aab 3752 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3753 return 1;
3754
3e6e0aab 3755 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 3756 return 1;
3757
3e6e0aab 3758 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 3759 return 1;
3760 return 0;
3761}
3762
3763static void save_state_to_tss16(struct kvm_vcpu *vcpu,
3764 struct tss_segment_16 *tss)
3765{
5fdbf976 3766 tss->ip = kvm_rip_read(vcpu);
37817f29 3767 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3768 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3769 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3770 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3771 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3772 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3773 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3774 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
3775 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3776
3777 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3778 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3779 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3780 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3781 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3782 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3783}
3784
3785static int load_state_from_tss16(struct kvm_vcpu *vcpu,
3786 struct tss_segment_16 *tss)
3787{
5fdbf976 3788 kvm_rip_write(vcpu, tss->ip);
37817f29 3789 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 3790 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
3791 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
3792 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
3793 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
3794 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
3795 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
3796 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
3797 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 3798
3e6e0aab 3799 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 3800 return 1;
3801
3e6e0aab 3802 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3803 return 1;
3804
3e6e0aab 3805 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3806 return 1;
3807
3e6e0aab 3808 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3809 return 1;
3810
3e6e0aab 3811 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3812 return 1;
3813 return 0;
3814}
3815
8b2cf73c 3816static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3817 u32 old_tss_base,
37817f29
IE		 3818 struct desc_struct *nseg_desc)
3819{
3820 struct tss_segment_16 tss_segment_16;
3821 int ret = 0;
3822
34198bf8
MT		 3823 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3824 sizeof tss_segment_16))
37817f29
IE		 3825 goto out;
3826
3827 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 3828
34198bf8
MT		 3829 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3830 sizeof tss_segment_16))
37817f29 3831 goto out;
34198bf8
MT		 3832
3833 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3834 &tss_segment_16, sizeof tss_segment_16))
3835 goto out;
3836
37817f29
IE		 3837 if (load_state_from_tss16(vcpu, &tss_segment_16))
3838 goto out;
3839
3840 ret = 1;
3841out:
3842 return ret;
3843}
3844
8b2cf73c 3845static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3846 u32 old_tss_base,
37817f29
IE		 3847 struct desc_struct *nseg_desc)
3848{
3849 struct tss_segment_32 tss_segment_32;
3850 int ret = 0;
3851
34198bf8
MT		 3852 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3853 sizeof tss_segment_32))
37817f29
IE		 3854 goto out;
3855
3856 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 3857
34198bf8
MT		 3858 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3859 sizeof tss_segment_32))
3860 goto out;
3861
3862 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3863 &tss_segment_32, sizeof tss_segment_32))
37817f29 3864 goto out;
34198bf8 3865
37817f29
IE		 3866 if (load_state_from_tss32(vcpu, &tss_segment_32))
3867 goto out;
3868
3869 ret = 1;
3870out:
3871 return ret;
3872}
3873
3874int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
3875{
3876 struct kvm_segment tr_seg;
3877 struct desc_struct cseg_desc;
3878 struct desc_struct nseg_desc;
3879 int ret = 0;
34198bf8
MT		 3880 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
3881 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 3882
34198bf8 3883 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 3884
34198bf8
MT		 3885 /* FIXME: Handle errors. Failure to read either TSS or their
3886 * descriptors should generate a pagefault.
3887 */
37817f29
IE		 3888 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
3889 goto out;
3890
34198bf8 3891 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 3892 goto out;
3893
37817f29
IE		 3894 if (reason != TASK_SWITCH_IRET) {
3895 int cpl;
3896
3897 cpl = kvm_x86_ops->get_cpl(vcpu);
3898 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
3899 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
3900 return 1;
3901 }
3902 }
3903
3904 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
3905 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
3906 return 1;
3907 }
3908
3909 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 3910 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 3911 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 3912 }
3913
3914 if (reason == TASK_SWITCH_IRET) {
3915 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3916 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
3917 }
3918
3919 kvm_x86_ops->skip_emulated_instruction(vcpu);
37817f29
IE		 3920
3921 if (nseg_desc.type & 8)
34198bf8 3922 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3923 &nseg_desc);
3924 else
34198bf8 3925 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3926 &nseg_desc);
3927
3928 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
3929 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3930 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
3931 }
3932
3933 if (reason != TASK_SWITCH_IRET) {
3fe913e7 3934 nseg_desc.type |= (1 << 1);
37817f29
IE		 3935 save_guest_segment_descriptor(vcpu, tss_selector,
3936 &nseg_desc);
3937 }
3938
3939 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
3940 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
3941 tr_seg.type = 11;
3e6e0aab 3942 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 3943out:
37817f29
IE		 3944 return ret;
3945}
3946EXPORT_SYMBOL_GPL(kvm_task_switch);
3947
b6c7a5dc
HB		 3948int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
3949 struct kvm_sregs *sregs)
3950{
3951 int mmu_reset_needed = 0;
3952 int i, pending_vec, max_bits;
3953 struct descriptor_table dt;
3954
3955 vcpu_load(vcpu);
3956
3957 dt.limit = sregs->idt.limit;
3958 dt.base = sregs->idt.base;
3959 kvm_x86_ops->set_idt(vcpu, &dt);
3960 dt.limit = sregs->gdt.limit;
3961 dt.base = sregs->gdt.base;
3962 kvm_x86_ops->set_gdt(vcpu, &dt);
3963
ad312c7c
ZX		 3964 vcpu->arch.cr2 = sregs->cr2;
3965 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
3966 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 3967
2d3ad1f4 3968 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 3969
ad312c7c 3970 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 3971 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 3972 kvm_set_apic_base(vcpu, sregs->apic_base);
3973
3974 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3975
ad312c7c 3976 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 3977 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 3978 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 3979
ad312c7c 3980 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 3981 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3982 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 3983 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 3984
3985 if (mmu_reset_needed)
3986 kvm_mmu_reset_context(vcpu);
3987
3988 if (!irqchip_in_kernel(vcpu->kvm)) {
ad312c7c
ZX		 3989 memcpy(vcpu->arch.irq_pending, sregs->interrupt_bitmap,
3990 sizeof vcpu->arch.irq_pending);
3991 vcpu->arch.irq_summary = 0;
3992 for (i = 0; i < ARRAY_SIZE(vcpu->arch.irq_pending); ++i)
3993 if (vcpu->arch.irq_pending[i])
3994 __set_bit(i, &vcpu->arch.irq_summary);
b6c7a5dc
HB		 3995 } else {
3996 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
3997 pending_vec = find_first_bit(
3998 (const unsigned long *)sregs->interrupt_bitmap,
3999 max_bits);
4000 /* Only pending external irq is handled here */
4001 if (pending_vec < max_bits) {
4002 kvm_x86_ops->set_irq(vcpu, pending_vec);
4003 pr_debug("Set back pending irq %d\n",
4004 pending_vec);
4005 }
e4825800 4006 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4007 }
4008
3e6e0aab
GT		 4009 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4010 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4011 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4012 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4013 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4014 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4015
3e6e0aab
GT		 4016 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4017 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4018
9c3e4aab
MT		 4019 /* Older userspace won't unhalt the vcpu on reset. */
4020 if (vcpu->vcpu_id == 0 && kvm_rip_read(vcpu) == 0xfff0 &&
4021 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4022 !(vcpu->arch.cr0 & X86_CR0_PE))
4023 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4024
b6c7a5dc
HB		 4025 vcpu_put(vcpu);
4026
4027 return 0;
4028}
4029
d0bfb940
JK		 4030int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4031 struct kvm_guest_debug *dbg)
b6c7a5dc 4032{
ae675ef0 4033 int i, r;
b6c7a5dc
HB		 4034
4035 vcpu_load(vcpu);
4036
ae675ef0
JK		 4037 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
4038 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
4039 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4040 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4041 vcpu->arch.switch_db_regs =
4042 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4043 } else {
4044 for (i = 0; i < KVM_NR_DB_REGS; i++)
4045 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4046 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4047 }
4048
b6c7a5dc
HB		 4049 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
4050
d0bfb940
JK		 4051 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4052 kvm_queue_exception(vcpu, DB_VECTOR);
4053 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
4054 kvm_queue_exception(vcpu, BP_VECTOR);
4055
b6c7a5dc
HB		 4056 vcpu_put(vcpu);
4057
4058 return r;
4059}
4060
d0752060
HB		 4061/*
4062 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4063 * we have asm/x86/processor.h
4064 */
4065struct fxsave {
4066 u16 cwd;
4067 u16 swd;
4068 u16 twd;
4069 u16 fop;
4070 u64 rip;
4071 u64 rdp;
4072 u32 mxcsr;
4073 u32 mxcsr_mask;
4074 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4075#ifdef CONFIG_X86_64
4076 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4077#else
4078 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4079#endif
4080};
4081
8b006791
ZX		 4082/*
4083 * Translate a guest virtual address to a guest physical address.
4084 */
4085int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4086 struct kvm_translation *tr)
4087{
4088 unsigned long vaddr = tr->linear_address;
4089 gpa_t gpa;
4090
4091 vcpu_load(vcpu);
72dc67a6 4092 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4093 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4094 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4095 tr->physical_address = gpa;
4096 tr->valid = gpa != UNMAPPED_GVA;
4097 tr->writeable = 1;
4098 tr->usermode = 0;
8b006791
ZX		 4099 vcpu_put(vcpu);
4100
4101 return 0;
4102}
4103
d0752060
HB		 4104int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4105{
ad312c7c 4106 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4107
4108 vcpu_load(vcpu);
4109
4110 memcpy(fpu->fpr, fxsave->st_space, 128);
4111 fpu->fcw = fxsave->cwd;
4112 fpu->fsw = fxsave->swd;
4113 fpu->ftwx = fxsave->twd;
4114 fpu->last_opcode = fxsave->fop;
4115 fpu->last_ip = fxsave->rip;
4116 fpu->last_dp = fxsave->rdp;
4117 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4118
4119 vcpu_put(vcpu);
4120
4121 return 0;
4122}
4123
4124int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4125{
ad312c7c 4126 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4127
4128 vcpu_load(vcpu);
4129
4130 memcpy(fxsave->st_space, fpu->fpr, 128);
4131 fxsave->cwd = fpu->fcw;
4132 fxsave->swd = fpu->fsw;
4133 fxsave->twd = fpu->ftwx;
4134 fxsave->fop = fpu->last_opcode;
4135 fxsave->rip = fpu->last_ip;
4136 fxsave->rdp = fpu->last_dp;
4137 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4138
4139 vcpu_put(vcpu);
4140
4141 return 0;
4142}
4143
4144void fx_init(struct kvm_vcpu *vcpu)
4145{
4146 unsigned after_mxcsr_mask;
4147
bc1a34f1
AA		 4148 /*
4149 * Touch the fpu the first time in non atomic context as if
4150 * this is the first fpu instruction the exception handler
4151 * will fire before the instruction returns and it'll have to
4152 * allocate ram with GFP_KERNEL.
4153 */
4154 if (!used_math())
d6e88aec 4155 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4156
d0752060
HB		 4157 /* Initialize guest FPU by resetting ours and saving into guest's */
4158 preempt_disable();
d6e88aec
AK		 4159 kvm_fx_save(&vcpu->arch.host_fx_image);
4160 kvm_fx_finit();
4161 kvm_fx_save(&vcpu->arch.guest_fx_image);
4162 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4163 preempt_enable();
4164
ad312c7c 4165 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4166 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4167 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4168 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4169 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4170}
4171EXPORT_SYMBOL_GPL(fx_init);
4172
4173void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4174{
4175 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4176 return;
4177
4178 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4179 kvm_fx_save(&vcpu->arch.host_fx_image);
4180 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4181}
4182EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4183
4184void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4185{
4186 if (!vcpu->guest_fpu_loaded)
4187 return;
4188
4189 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4190 kvm_fx_save(&vcpu->arch.guest_fx_image);
4191 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4192 ++vcpu->stat.fpu_reload;
d0752060
HB		 4193}
4194EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4195
4196void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4197{
7f1ea208
JR		 4198 if (vcpu->arch.time_page) {
4199 kvm_release_page_dirty(vcpu->arch.time_page);
4200 vcpu->arch.time_page = NULL;
4201 }
4202
e9b11c17
ZX		 4203 kvm_x86_ops->vcpu_free(vcpu);
4204}
4205
4206struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4207 unsigned int id)
4208{
26e5215f
AK		 4209 return kvm_x86_ops->vcpu_create(kvm, id);
4210}
e9b11c17 4211
26e5215f
AK		 4212int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4213{
4214 int r;
e9b11c17
ZX		 4215
4216 /* We do fxsave: this must be aligned. */
ad312c7c 4217 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4218
0bed3b56 4219 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4220 vcpu_load(vcpu);
4221 r = kvm_arch_vcpu_reset(vcpu);
4222 if (r == 0)
4223 r = kvm_mmu_setup(vcpu);
4224 vcpu_put(vcpu);
4225 if (r < 0)
4226 goto free_vcpu;
4227
26e5215f 4228 return 0;
e9b11c17
ZX		 4229free_vcpu:
4230 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4231 return r;
e9b11c17
ZX		 4232}
4233
d40ccc62 4234void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4235{
4236 vcpu_load(vcpu);
4237 kvm_mmu_unload(vcpu);
4238 vcpu_put(vcpu);
4239
4240 kvm_x86_ops->vcpu_free(vcpu);
4241}
4242
4243int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4244{
448fa4a9
JK		 4245 vcpu->arch.nmi_pending = false;
4246 vcpu->arch.nmi_injected = false;
4247
42dbaa5a
JK		 4248 vcpu->arch.switch_db_regs = 0;
4249 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4250 vcpu->arch.dr6 = DR6_FIXED_1;
4251 vcpu->arch.dr7 = DR7_FIXED_1;
4252
e9b11c17
ZX		 4253 return kvm_x86_ops->vcpu_reset(vcpu);
4254}
4255
4256void kvm_arch_hardware_enable(void *garbage)
4257{
4258 kvm_x86_ops->hardware_enable(garbage);
4259}
4260
4261void kvm_arch_hardware_disable(void *garbage)
4262{
4263 kvm_x86_ops->hardware_disable(garbage);
4264}
4265
4266int kvm_arch_hardware_setup(void)
4267{
4268 return kvm_x86_ops->hardware_setup();
4269}
4270
4271void kvm_arch_hardware_unsetup(void)
4272{
4273 kvm_x86_ops->hardware_unsetup();
4274}
4275
4276void kvm_arch_check_processor_compat(void *rtn)
4277{
4278 kvm_x86_ops->check_processor_compatibility(rtn);
4279}
4280
4281int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4282{
4283 struct page *page;
4284 struct kvm *kvm;
4285 int r;
4286
4287 BUG_ON(vcpu->kvm == NULL);
4288 kvm = vcpu->kvm;
4289
ad312c7c 4290 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
e9b11c17 4291 if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0)
a4535290 4292 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4293 else
a4535290 4294 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4295
4296 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4297 if (!page) {
4298 r = -ENOMEM;
4299 goto fail;
4300 }
ad312c7c 4301 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4302
4303 r = kvm_mmu_create(vcpu);
4304 if (r < 0)
4305 goto fail_free_pio_data;
4306
4307 if (irqchip_in_kernel(kvm)) {
4308 r = kvm_create_lapic(vcpu);
4309 if (r < 0)
4310 goto fail_mmu_destroy;
4311 }
4312
4313 return 0;
4314
4315fail_mmu_destroy:
4316 kvm_mmu_destroy(vcpu);
4317fail_free_pio_data:
ad312c7c 4318 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4319fail:
4320 return r;
4321}
4322
4323void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4324{
4325 kvm_free_lapic(vcpu);
3200f405 4326 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4327 kvm_mmu_destroy(vcpu);
3200f405 4328 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4329 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4330}
d19a9cd2
ZX		 4331
4332struct kvm *kvm_arch_create_vm(void)
4333{
4334 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4335
4336 if (!kvm)
4337 return ERR_PTR(-ENOMEM);
4338
f05e70ac 4339 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6cffe8ca 4340 INIT_LIST_HEAD(&kvm->arch.oos_global_pages);
4d5c5d0f 4341 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4342
5550af4d
SY		 4343 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4344 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4345
53f658b3
MT		 4346 rdtscll(kvm->arch.vm_init_tsc);
4347
d19a9cd2
ZX		 4348 return kvm;
4349}
4350
4351static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4352{
4353 vcpu_load(vcpu);
4354 kvm_mmu_unload(vcpu);
4355 vcpu_put(vcpu);
4356}
4357
4358static void kvm_free_vcpus(struct kvm *kvm)
4359{
4360 unsigned int i;
4361
4362 /*
4363 * Unpin any mmu pages first.
4364 */
4365 for (i = 0; i < KVM_MAX_VCPUS; ++i)
4366 if (kvm->vcpus[i])
4367 kvm_unload_vcpu_mmu(kvm->vcpus[i]);
4368 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
4369 if (kvm->vcpus[i]) {
4370 kvm_arch_vcpu_free(kvm->vcpus[i]);
4371 kvm->vcpus[i] = NULL;
4372 }
4373 }
4374
4375}
4376
ad8ba2cd
SY		 4377void kvm_arch_sync_events(struct kvm *kvm)
4378{
ba4cef31 4379 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4380}
4381
d19a9cd2
ZX		 4382void kvm_arch_destroy_vm(struct kvm *kvm)
4383{
6eb55818 4384 kvm_iommu_unmap_guest(kvm);
7837699f 4385 kvm_free_pit(kvm);
d7deeeb0
ZX		 4386 kfree(kvm->arch.vpic);
4387 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4388 kvm_free_vcpus(kvm);
4389 kvm_free_physmem(kvm);
3d45830c
AK		 4390 if (kvm->arch.apic_access_page)
4391 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4392 if (kvm->arch.ept_identity_pagetable)
4393 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4394 kfree(kvm);
4395}
0de10343
ZX		 4396
4397int kvm_arch_set_memory_region(struct kvm *kvm,
4398 struct kvm_userspace_memory_region *mem,
4399 struct kvm_memory_slot old,
4400 int user_alloc)
4401{
4402 int npages = mem->memory_size >> PAGE_SHIFT;
4403 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4404
4405 /*To keep backward compatibility with older userspace,
4406 *x86 needs to hanlde !user_alloc case.
4407 */
4408 if (!user_alloc) {
4409 if (npages && !old.rmap) {
604b38ac
AA		 4410 unsigned long userspace_addr;
4411
72dc67a6 4412 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4413 userspace_addr = do_mmap(NULL, 0,
4414 npages * PAGE_SIZE,
4415 PROT_READ | PROT_WRITE,
acee3c04 4416 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4417 0);
72dc67a6 4418 up_write(&current->mm->mmap_sem);
0de10343 4419
604b38ac
AA		 4420 if (IS_ERR((void *)userspace_addr))
4421 return PTR_ERR((void *)userspace_addr);
4422
4423 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4424 spin_lock(&kvm->mmu_lock);
4425 memslot->userspace_addr = userspace_addr;
4426 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4427 } else {
4428 if (!old.user_alloc && old.rmap) {
4429 int ret;
4430
72dc67a6 4431 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4432 ret = do_munmap(current->mm, old.userspace_addr,
4433 old.npages * PAGE_SIZE);
72dc67a6 4434 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4435 if (ret < 0)
4436 printk(KERN_WARNING
4437 "kvm_vm_ioctl_set_memory_region: "
4438 "failed to munmap memory\n");
4439 }
4440 }
4441 }
4442
f05e70ac 4443 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4444 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4445 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4446 }
4447
4448 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
4449 kvm_flush_remote_tlbs(kvm);
4450
4451 return 0;
4452}
1d737c8a 4453
34d4cb8f
MT		 4454void kvm_arch_flush_shadow(struct kvm *kvm)
4455{
4456 kvm_mmu_zap_all(kvm);
4457}
4458
1d737c8a
ZX		 4459int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4460{
a4535290 4461 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
0496fbb9
JK		 4462 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4463 || vcpu->arch.nmi_pending;
1d737c8a 4464}
5736199a
ZX		 4465
4466static void vcpu_kick_intr(void *info)
4467{
4468#ifdef DEBUG
4469 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)info;
4470 printk(KERN_DEBUG "vcpu_kick_intr %p \n", vcpu);
4471#endif
4472}
4473
4474void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4475{
4476 int ipi_pcpu = vcpu->cpu;
e9571ed5 4477 int cpu = get_cpu();
5736199a
ZX		 4478
4479 if (waitqueue_active(&vcpu->wq)) {
4480 wake_up_interruptible(&vcpu->wq);
4481 ++vcpu->stat.halt_wakeup;
4482 }
e9571ed5
MT		 4483 /*
4484 * We may be called synchronously with irqs disabled in guest mode,
4485 * So need not to call smp_call_function_single() in that case.
4486 */
4487 if (vcpu->guest_mode && vcpu->cpu != cpu)
8691e5a8 4488 smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0);
e9571ed5 4489 put_cpu();
5736199a 4490}
78646121
GN		 4491
4492int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
4493{
4494 return kvm_x86_ops->interrupt_allowed(vcpu);
4495}
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