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KVM: introduce kvm->srcu and convert kvm_set_memory_region to SRCU update
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
aec51dc4
AK		 41#include <trace/events/kvm.h>
42#undef TRACE_INCLUDE_FILE
229456fc
MT		 43#define CREATE_TRACE_POINTS
44#include "trace.h"
043405e1 45
24f1e32c 46#include <asm/debugreg.h>
043405e1 47#include <asm/uaccess.h>
d825ed0a 48#include <asm/msr.h>
a5f61300 49#include <asm/desc.h>
0bed3b56 50#include <asm/mtrr.h>
890ca9ae 51#include <asm/mce.h>
043405e1 52
313a3dc7 53#define MAX_IO_MSRS 256
a03490ed
CO		 54#define CR0_RESERVED_BITS \
55 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
56 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
57 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
58#define CR4_RESERVED_BITS \
59 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
60 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
61 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
62 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
63
64#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 65
66#define KVM_MAX_MCE_BANKS 32
67#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
68
50a37eb4
JR		 69/* EFER defaults:
70 * - enable syscall per default because its emulated by KVM
71 * - enable LME and LMA per default on 64 bit KVM
72 */
73#ifdef CONFIG_X86_64
74static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
75#else
76static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
77#endif
313a3dc7 78
ba1389b7
AK		 79#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
80#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 81
cb142eb7 82static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 83static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
84 struct kvm_cpuid_entry2 __user *entries);
85
97896d04 86struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 87EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 88
ed85c068
AP		 89int ignore_msrs = 0;
90module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
91
18863bdd
AK		 92#define KVM_NR_SHARED_MSRS 16
93
94struct kvm_shared_msrs_global {
95 int nr;
2bf78fa7 96 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 97};
98
99struct kvm_shared_msrs {
100 struct user_return_notifier urn;
101 bool registered;
2bf78fa7
SY		 102 struct kvm_shared_msr_values {
103 u64 host;
104 u64 curr;
105 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 106};
107
108static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
109static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
110
417bc304 111struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 112 { "pf_fixed", VCPU_STAT(pf_fixed) },
113 { "pf_guest", VCPU_STAT(pf_guest) },
114 { "tlb_flush", VCPU_STAT(tlb_flush) },
115 { "invlpg", VCPU_STAT(invlpg) },
116 { "exits", VCPU_STAT(exits) },
117 { "io_exits", VCPU_STAT(io_exits) },
118 { "mmio_exits", VCPU_STAT(mmio_exits) },
119 { "signal_exits", VCPU_STAT(signal_exits) },
120 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 121 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 122 { "halt_exits", VCPU_STAT(halt_exits) },
123 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 124 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 125 { "request_irq", VCPU_STAT(request_irq_exits) },
126 { "irq_exits", VCPU_STAT(irq_exits) },
127 { "host_state_reload", VCPU_STAT(host_state_reload) },
128 { "efer_reload", VCPU_STAT(efer_reload) },
129 { "fpu_reload", VCPU_STAT(fpu_reload) },
130 { "insn_emulation", VCPU_STAT(insn_emulation) },
131 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 132 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 133 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 134 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
135 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
136 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
137 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
138 { "mmu_flooded", VM_STAT(mmu_flooded) },
139 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 140 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 141 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 142 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 143 { "largepages", VM_STAT(lpages) },
417bc304
HB		 144 { NULL }
145};
146
18863bdd
AK		 147static void kvm_on_user_return(struct user_return_notifier *urn)
148{
149 unsigned slot;
18863bdd
AK		 150 struct kvm_shared_msrs *locals
151 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 152 struct kvm_shared_msr_values *values;
18863bdd
AK		 153
154 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 155 values = &locals->values[slot];
156 if (values->host != values->curr) {
157 wrmsrl(shared_msrs_global.msrs[slot], values->host);
158 values->curr = values->host;
18863bdd
AK		 159 }
160 }
161 locals->registered = false;
162 user_return_notifier_unregister(urn);
163}
164
2bf78fa7 165static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 166{
2bf78fa7 167 struct kvm_shared_msrs *smsr;
18863bdd
AK		 168 u64 value;
169
2bf78fa7
SY		 170 smsr = &__get_cpu_var(shared_msrs);
171 /* only read, and nobody should modify it at this time,
172 * so don't need lock */
173 if (slot >= shared_msrs_global.nr) {
174 printk(KERN_ERR "kvm: invalid MSR slot!");
175 return;
176 }
177 rdmsrl_safe(msr, &value);
178 smsr->values[slot].host = value;
179 smsr->values[slot].curr = value;
180}
181
182void kvm_define_shared_msr(unsigned slot, u32 msr)
183{
18863bdd
AK		 184 if (slot >= shared_msrs_global.nr)
185 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 186 shared_msrs_global.msrs[slot] = msr;
187 /* we need ensured the shared_msr_global have been updated */
188 smp_wmb();
18863bdd
AK		 189}
190EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
191
192static void kvm_shared_msr_cpu_online(void)
193{
194 unsigned i;
18863bdd
AK		 195
196 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 197 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 198}
199
d5696725 200void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 201{
202 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
203
2bf78fa7 204 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 205 return;
2bf78fa7
SY		 206 smsr->values[slot].curr = value;
207 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 208 if (!smsr->registered) {
209 smsr->urn.on_user_return = kvm_on_user_return;
210 user_return_notifier_register(&smsr->urn);
211 smsr->registered = true;
212 }
213}
214EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
215
3548bab5
AK		 216static void drop_user_return_notifiers(void *ignore)
217{
218 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
219
220 if (smsr->registered)
221 kvm_on_user_return(&smsr->urn);
222}
223
5fb76f9b
CO		 224unsigned long segment_base(u16 selector)
225{
226 struct descriptor_table gdt;
a5f61300 227 struct desc_struct *d;
5fb76f9b
CO		 228 unsigned long table_base;
229 unsigned long v;
230
231 if (selector == 0)
232 return 0;
233
b792c344 234 kvm_get_gdt(&gdt);
5fb76f9b
CO		 235 table_base = gdt.base;
236
237 if (selector & 4) { /* from ldt */
b792c344 238 u16 ldt_selector = kvm_read_ldt();
5fb76f9b 239
5fb76f9b
CO		 240 table_base = segment_base(ldt_selector);
241 }
a5f61300 242 d = (struct desc_struct *)(table_base + (selector & ~7));
46a359e7 243 v = get_desc_base(d);
5fb76f9b 244#ifdef CONFIG_X86_64
a5f61300
AK		 245 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
246 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 247#endif
248 return v;
249}
250EXPORT_SYMBOL_GPL(segment_base);
251
6866b83e
CO		 252u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
253{
254 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 255 return vcpu->arch.apic_base;
6866b83e 256 else
ad312c7c 257 return vcpu->arch.apic_base;
6866b83e
CO		 258}
259EXPORT_SYMBOL_GPL(kvm_get_apic_base);
260
261void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
262{
263 /* TODO: reserve bits check */
264 if (irqchip_in_kernel(vcpu->kvm))
265 kvm_lapic_set_base(vcpu, data);
266 else
ad312c7c 267 vcpu->arch.apic_base = data;
6866b83e
CO		 268}
269EXPORT_SYMBOL_GPL(kvm_set_apic_base);
270
3fd28fce
ED		 271#define EXCPT_BENIGN 0
272#define EXCPT_CONTRIBUTORY 1
273#define EXCPT_PF 2
274
275static int exception_class(int vector)
276{
277 switch (vector) {
278 case PF_VECTOR:
279 return EXCPT_PF;
280 case DE_VECTOR:
281 case TS_VECTOR:
282 case NP_VECTOR:
283 case SS_VECTOR:
284 case GP_VECTOR:
285 return EXCPT_CONTRIBUTORY;
286 default:
287 break;
288 }
289 return EXCPT_BENIGN;
290}
291
292static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
293 unsigned nr, bool has_error, u32 error_code)
294{
295 u32 prev_nr;
296 int class1, class2;
297
298 if (!vcpu->arch.exception.pending) {
299 queue:
300 vcpu->arch.exception.pending = true;
301 vcpu->arch.exception.has_error_code = has_error;
302 vcpu->arch.exception.nr = nr;
303 vcpu->arch.exception.error_code = error_code;
304 return;
305 }
306
307 /* to check exception */
308 prev_nr = vcpu->arch.exception.nr;
309 if (prev_nr == DF_VECTOR) {
310 /* triple fault -> shutdown */
311 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
312 return;
313 }
314 class1 = exception_class(prev_nr);
315 class2 = exception_class(nr);
316 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
317 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
318 /* generate double fault per SDM Table 5-5 */
319 vcpu->arch.exception.pending = true;
320 vcpu->arch.exception.has_error_code = true;
321 vcpu->arch.exception.nr = DF_VECTOR;
322 vcpu->arch.exception.error_code = 0;
323 } else
324 /* replace previous exception with a new one in a hope
325 that instruction re-execution will regenerate lost
326 exception */
327 goto queue;
328}
329
298101da
AK		 330void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
331{
3fd28fce 332 kvm_multiple_exception(vcpu, nr, false, 0);
298101da
AK		 333}
334EXPORT_SYMBOL_GPL(kvm_queue_exception);
335
c3c91fee
AK		 336void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
337 u32 error_code)
338{
339 ++vcpu->stat.pf_guest;
ad312c7c 340 vcpu->arch.cr2 = addr;
c3c91fee
AK		 341 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
342}
343
3419ffc8
SY		 344void kvm_inject_nmi(struct kvm_vcpu *vcpu)
345{
346 vcpu->arch.nmi_pending = 1;
347}
348EXPORT_SYMBOL_GPL(kvm_inject_nmi);
349
298101da
AK		 350void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
351{
3fd28fce 352 kvm_multiple_exception(vcpu, nr, true, error_code);
298101da
AK		 353}
354EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
355
0a79b009
AK		 356/*
357 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
358 * a #GP and return false.
359 */
360bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 361{
0a79b009
AK		 362 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
363 return true;
364 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
365 return false;
298101da 366}
0a79b009 367EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 368
a03490ed
CO		 369/*
370 * Load the pae pdptrs. Return true is they are all valid.
371 */
372int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
373{
374 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
375 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
376 int i;
377 int ret;
ad312c7c 378 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 379
a03490ed
CO		 380 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
381 offset * sizeof(u64), sizeof(pdpte));
382 if (ret < 0) {
383 ret = 0;
384 goto out;
385 }
386 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 387 if (is_present_gpte(pdpte[i]) &&
20c466b5 388 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 389 ret = 0;
390 goto out;
391 }
392 }
393 ret = 1;
394
ad312c7c 395 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 396 __set_bit(VCPU_EXREG_PDPTR,
397 (unsigned long *)&vcpu->arch.regs_avail);
398 __set_bit(VCPU_EXREG_PDPTR,
399 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 400out:
a03490ed
CO		 401
402 return ret;
403}
cc4b6871 404EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 405
d835dfec
AK		 406static bool pdptrs_changed(struct kvm_vcpu *vcpu)
407{
ad312c7c 408 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 409 bool changed = true;
410 int r;
411
412 if (is_long_mode(vcpu) || !is_pae(vcpu))
413 return false;
414
6de4f3ad
AK		 415 if (!test_bit(VCPU_EXREG_PDPTR,
416 (unsigned long *)&vcpu->arch.regs_avail))
417 return true;
418
ad312c7c 419 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 420 if (r < 0)
421 goto out;
ad312c7c 422 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 423out:
d835dfec
AK		 424
425 return changed;
426}
427
2d3ad1f4 428void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 429{
430 if (cr0 & CR0_RESERVED_BITS) {
431 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 432 cr0, vcpu->arch.cr0);
c1a5d4f9 433 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 434 return;
435 }
436
437 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
438 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 439 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 440 return;
441 }
442
443 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
444 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
445 "and a clear PE flag\n");
c1a5d4f9 446 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 447 return;
448 }
449
450 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
451#ifdef CONFIG_X86_64
ad312c7c 452 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 453 int cs_db, cs_l;
454
455 if (!is_pae(vcpu)) {
456 printk(KERN_DEBUG "set_cr0: #GP, start paging "
457 "in long mode while PAE is disabled\n");
c1a5d4f9 458 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 459 return;
460 }
461 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
462 if (cs_l) {
463 printk(KERN_DEBUG "set_cr0: #GP, start paging "
464 "in long mode while CS.L == 1\n");
c1a5d4f9 465 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 466 return;
467
468 }
469 } else
470#endif
ad312c7c 471 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 472 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
473 "reserved bits\n");
c1a5d4f9 474 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 475 return;
476 }
477
478 }
479
480 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 481 vcpu->arch.cr0 = cr0;
a03490ed 482
a03490ed 483 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 484 return;
485}
2d3ad1f4 486EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 487
2d3ad1f4 488void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 489{
2d3ad1f4 490 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
a03490ed 491}
2d3ad1f4 492EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 493
2d3ad1f4 494void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 495{
fc78f519 496 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 497 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
498
a03490ed
CO		 499 if (cr4 & CR4_RESERVED_BITS) {
500 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 501 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 502 return;
503 }
504
505 if (is_long_mode(vcpu)) {
506 if (!(cr4 & X86_CR4_PAE)) {
507 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
508 "in long mode\n");
c1a5d4f9 509 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 510 return;
511 }
a2edf57f
AK		 512 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
513 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 514 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 515 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 516 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 517 return;
518 }
519
520 if (cr4 & X86_CR4_VMXE) {
521 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 522 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 523 return;
524 }
525 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 526 vcpu->arch.cr4 = cr4;
5a41accd 527 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 528 kvm_mmu_reset_context(vcpu);
a03490ed 529}
2d3ad1f4 530EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 531
2d3ad1f4 532void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 533{
ad312c7c 534 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 535 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 536 kvm_mmu_flush_tlb(vcpu);
537 return;
538 }
539
a03490ed
CO		 540 if (is_long_mode(vcpu)) {
541 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
542 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 543 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 544 return;
545 }
546 } else {
547 if (is_pae(vcpu)) {
548 if (cr3 & CR3_PAE_RESERVED_BITS) {
549 printk(KERN_DEBUG
550 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 551 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 552 return;
553 }
554 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
555 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
556 "reserved bits\n");
c1a5d4f9 557 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 558 return;
559 }
560 }
561 /*
562 * We don't check reserved bits in nonpae mode, because
563 * this isn't enforced, and VMware depends on this.
564 */
565 }
566
a03490ed
CO		 567 /*
568 * Does the new cr3 value map to physical memory? (Note, we
569 * catch an invalid cr3 even in real-mode, because it would
570 * cause trouble later on when we turn on paging anyway.)
571 *
572 * A real CPU would silently accept an invalid cr3 and would
573 * attempt to use it - with largely undefined (and often hard
574 * to debug) behavior on the guest side.
575 */
576 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 577 kvm_inject_gp(vcpu, 0);
a03490ed 578 else {
ad312c7c
ZX		 579 vcpu->arch.cr3 = cr3;
580 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 581 }
a03490ed 582}
2d3ad1f4 583EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 584
2d3ad1f4 585void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 586{
587 if (cr8 & CR8_RESERVED_BITS) {
588 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 589 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 590 return;
591 }
592 if (irqchip_in_kernel(vcpu->kvm))
593 kvm_lapic_set_tpr(vcpu, cr8);
594 else
ad312c7c 595 vcpu->arch.cr8 = cr8;
a03490ed 596}
2d3ad1f4 597EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 598
2d3ad1f4 599unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 600{
601 if (irqchip_in_kernel(vcpu->kvm))
602 return kvm_lapic_get_cr8(vcpu);
603 else
ad312c7c 604 return vcpu->arch.cr8;
a03490ed 605}
2d3ad1f4 606EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 607
d8017474
AG		 608static inline u32 bit(int bitno)
609{
610 return 1 << (bitno & 31);
611}
612
043405e1
CO		 613/*
614 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
615 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
616 *
617 * This list is modified at module load time to reflect the
e3267cbb
GC		 618 * capabilities of the host cpu. This capabilities test skips MSRs that are
619 * kvm-specific. Those are put in the beginning of the list.
043405e1 620 */
e3267cbb
GC		 621
622#define KVM_SAVE_MSRS_BEGIN 2
043405e1 623static u32 msrs_to_save[] = {
e3267cbb 624 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
043405e1
CO		 625 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
626 MSR_K6_STAR,
627#ifdef CONFIG_X86_64
628 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
629#endif
e3267cbb 630 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 631};
632
633static unsigned num_msrs_to_save;
634
635static u32 emulated_msrs[] = {
636 MSR_IA32_MISC_ENABLE,
637};
638
15c4a640
CO		 639static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
640{
f2b4b7dd 641 if (efer & efer_reserved_bits) {
15c4a640
CO		 642 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
643 efer);
c1a5d4f9 644 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 645 return;
646 }
647
648 if (is_paging(vcpu)
ad312c7c 649 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 650 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 651 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 652 return;
653 }
654
1b2fd70c
AG		 655 if (efer & EFER_FFXSR) {
656 struct kvm_cpuid_entry2 *feat;
657
658 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
659 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
660 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
661 kvm_inject_gp(vcpu, 0);
662 return;
663 }
664 }
665
d8017474
AG		 666 if (efer & EFER_SVME) {
667 struct kvm_cpuid_entry2 *feat;
668
669 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
670 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
671 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
672 kvm_inject_gp(vcpu, 0);
673 return;
674 }
675 }
676
15c4a640
CO		 677 kvm_x86_ops->set_efer(vcpu, efer);
678
679 efer &= ~EFER_LMA;
ad312c7c 680 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 681
ad312c7c 682 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 683
684 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
685 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 686}
687
f2b4b7dd
JR		 688void kvm_enable_efer_bits(u64 mask)
689{
690 efer_reserved_bits &= ~mask;
691}
692EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
693
694
15c4a640
CO		 695/*
696 * Writes msr value into into the appropriate "register".
697 * Returns 0 on success, non-0 otherwise.
698 * Assumes vcpu_load() was already called.
699 */
700int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
701{
702 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
703}
704
313a3dc7
CO		 705/*
706 * Adapt set_msr() to msr_io()'s calling convention
707 */
708static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
709{
710 return kvm_set_msr(vcpu, index, *data);
711}
712
18068523
GOC		 713static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
714{
715 static int version;
50d0a0f9 716 struct pvclock_wall_clock wc;
923de3cf 717 struct timespec boot;
18068523
GOC		 718
719 if (!wall_clock)
720 return;
721
722 version++;
723
18068523
GOC		 724 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
725
50d0a0f9
GH		 726 /*
727 * The guest calculates current wall clock time by adding
728 * system time (updated by kvm_write_guest_time below) to the
729 * wall clock specified here. guest system time equals host
730 * system time for us, thus we must fill in host boot time here.
731 */
923de3cf 732 getboottime(&boot);
50d0a0f9
GH		 733
734 wc.sec = boot.tv_sec;
735 wc.nsec = boot.tv_nsec;
736 wc.version = version;
18068523
GOC		 737
738 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
739
740 version++;
741 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 742}
743
50d0a0f9
GH		 744static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
745{
746 uint32_t quotient, remainder;
747
748 /* Don't try to replace with do_div(), this one calculates
749 * "(dividend << 32) / divisor" */
750 __asm__ ( "divl %4"
751 : "=a" (quotient), "=d" (remainder)
752 : "0" (0), "1" (dividend), "r" (divisor) );
753 return quotient;
754}
755
756static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
757{
758 uint64_t nsecs = 1000000000LL;
759 int32_t shift = 0;
760 uint64_t tps64;
761 uint32_t tps32;
762
763 tps64 = tsc_khz * 1000LL;
764 while (tps64 > nsecs*2) {
765 tps64 >>= 1;
766 shift--;
767 }
768
769 tps32 = (uint32_t)tps64;
770 while (tps32 <= (uint32_t)nsecs) {
771 tps32 <<= 1;
772 shift++;
773 }
774
775 hv_clock->tsc_shift = shift;
776 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
777
778 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 779 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 780 hv_clock->tsc_to_system_mul);
781}
782
c8076604
GH		 783static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
784
18068523
GOC		 785static void kvm_write_guest_time(struct kvm_vcpu *v)
786{
787 struct timespec ts;
788 unsigned long flags;
789 struct kvm_vcpu_arch *vcpu = &v->arch;
790 void *shared_kaddr;
463656c0 791 unsigned long this_tsc_khz;
18068523
GOC		 792
793 if ((!vcpu->time_page))
794 return;
795
463656c0
AK		 796 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
797 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
798 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
799 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 800 }
463656c0 801 put_cpu_var(cpu_tsc_khz);
50d0a0f9 802
18068523
GOC		 803 /* Keep irq disabled to prevent changes to the clock */
804 local_irq_save(flags);
af24a4e4 805 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 806 ktime_get_ts(&ts);
923de3cf 807 monotonic_to_bootbased(&ts);
18068523
GOC		 808 local_irq_restore(flags);
809
810 /* With all the info we got, fill in the values */
811
812 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 813 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
814
18068523
GOC		 815 /*
816 * The interface expects us to write an even number signaling that the
817 * update is finished. Since the guest won't see the intermediate
50d0a0f9 818 * state, we just increase by 2 at the end.
18068523 819 */
50d0a0f9 820 vcpu->hv_clock.version += 2;
18068523
GOC		 821
822 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
823
824 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 825 sizeof(vcpu->hv_clock));
18068523
GOC		 826
827 kunmap_atomic(shared_kaddr, KM_USER0);
828
829 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
830}
831
c8076604
GH		 832static int kvm_request_guest_time_update(struct kvm_vcpu *v)
833{
834 struct kvm_vcpu_arch *vcpu = &v->arch;
835
836 if (!vcpu->time_page)
837 return 0;
838 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
839 return 1;
840}
841
9ba075a6
AK		 842static bool msr_mtrr_valid(unsigned msr)
843{
844 switch (msr) {
845 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
846 case MSR_MTRRfix64K_00000:
847 case MSR_MTRRfix16K_80000:
848 case MSR_MTRRfix16K_A0000:
849 case MSR_MTRRfix4K_C0000:
850 case MSR_MTRRfix4K_C8000:
851 case MSR_MTRRfix4K_D0000:
852 case MSR_MTRRfix4K_D8000:
853 case MSR_MTRRfix4K_E0000:
854 case MSR_MTRRfix4K_E8000:
855 case MSR_MTRRfix4K_F0000:
856 case MSR_MTRRfix4K_F8000:
857 case MSR_MTRRdefType:
858 case MSR_IA32_CR_PAT:
859 return true;
860 case 0x2f8:
861 return true;
862 }
863 return false;
864}
865
d6289b93
MT		 866static bool valid_pat_type(unsigned t)
867{
868 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
869}
870
871static bool valid_mtrr_type(unsigned t)
872{
873 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
874}
875
876static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
877{
878 int i;
879
880 if (!msr_mtrr_valid(msr))
881 return false;
882
883 if (msr == MSR_IA32_CR_PAT) {
884 for (i = 0; i < 8; i++)
885 if (!valid_pat_type((data >> (i * 8)) & 0xff))
886 return false;
887 return true;
888 } else if (msr == MSR_MTRRdefType) {
889 if (data & ~0xcff)
890 return false;
891 return valid_mtrr_type(data & 0xff);
892 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
893 for (i = 0; i < 8 ; i++)
894 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
895 return false;
896 return true;
897 }
898
899 /* variable MTRRs */
900 return valid_mtrr_type(data & 0xff);
901}
902
9ba075a6
AK		 903static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
904{
0bed3b56
SY		 905 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
906
d6289b93 907 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 908 return 1;
909
0bed3b56
SY		 910 if (msr == MSR_MTRRdefType) {
911 vcpu->arch.mtrr_state.def_type = data;
912 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
913 } else if (msr == MSR_MTRRfix64K_00000)
914 p[0] = data;
915 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
916 p[1 + msr - MSR_MTRRfix16K_80000] = data;
917 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
918 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
919 else if (msr == MSR_IA32_CR_PAT)
920 vcpu->arch.pat = data;
921 else { /* Variable MTRRs */
922 int idx, is_mtrr_mask;
923 u64 *pt;
924
925 idx = (msr - 0x200) / 2;
926 is_mtrr_mask = msr - 0x200 - 2 * idx;
927 if (!is_mtrr_mask)
928 pt =
929 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
930 else
931 pt =
932 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
933 *pt = data;
934 }
935
936 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 937 return 0;
938}
15c4a640 939
890ca9ae 940static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 941{
890ca9ae
HY		 942 u64 mcg_cap = vcpu->arch.mcg_cap;
943 unsigned bank_num = mcg_cap & 0xff;
944
15c4a640 945 switch (msr) {
15c4a640 946 case MSR_IA32_MCG_STATUS:
890ca9ae 947 vcpu->arch.mcg_status = data;
15c4a640 948 break;
c7ac679c 949 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 950 if (!(mcg_cap & MCG_CTL_P))
951 return 1;
952 if (data != 0 && data != ~(u64)0)
953 return -1;
954 vcpu->arch.mcg_ctl = data;
955 break;
956 default:
957 if (msr >= MSR_IA32_MC0_CTL &&
958 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
959 u32 offset = msr - MSR_IA32_MC0_CTL;
960 /* only 0 or all 1s can be written to IA32_MCi_CTL */
961 if ((offset & 0x3) == 0 &&
962 data != 0 && data != ~(u64)0)
963 return -1;
964 vcpu->arch.mce_banks[offset] = data;
965 break;
966 }
967 return 1;
968 }
969 return 0;
970}
971
ffde22ac
ES		 972static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
973{
974 struct kvm *kvm = vcpu->kvm;
975 int lm = is_long_mode(vcpu);
976 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
977 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
978 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
979 : kvm->arch.xen_hvm_config.blob_size_32;
980 u32 page_num = data & ~PAGE_MASK;
981 u64 page_addr = data & PAGE_MASK;
982 u8 *page;
983 int r;
984
985 r = -E2BIG;
986 if (page_num >= blob_size)
987 goto out;
988 r = -ENOMEM;
989 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
990 if (!page)
991 goto out;
992 r = -EFAULT;
993 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
994 goto out_free;
995 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
996 goto out_free;
997 r = 0;
998out_free:
999 kfree(page);
1000out:
1001 return r;
1002}
1003
15c4a640
CO		 1004int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1005{
1006 switch (msr) {
15c4a640
CO		 1007 case MSR_EFER:
1008 set_efer(vcpu, data);
1009 break;
8f1589d9
AP		 1010 case MSR_K7_HWCR:
1011 data &= ~(u64)0x40; /* ignore flush filter disable */
1012 if (data != 0) {
1013 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1014 data);
1015 return 1;
1016 }
15c4a640 1017 break;
f7c6d140
AP		 1018 case MSR_FAM10H_MMIO_CONF_BASE:
1019 if (data != 0) {
1020 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1021 "0x%llx\n", data);
1022 return 1;
1023 }
15c4a640 1024 break;
c323c0e5 1025 case MSR_AMD64_NB_CFG:
c7ac679c 1026 break;
b5e2fec0
AG		 1027 case MSR_IA32_DEBUGCTLMSR:
1028 if (!data) {
1029 /* We support the non-activated case already */
1030 break;
1031 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1032 /* Values other than LBR and BTF are vendor-specific,
1033 thus reserved and should throw a #GP */
1034 return 1;
1035 }
1036 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1037 __func__, data);
1038 break;
15c4a640
CO		 1039 case MSR_IA32_UCODE_REV:
1040 case MSR_IA32_UCODE_WRITE:
61a6bd67 1041 case MSR_VM_HSAVE_PA:
6098ca93 1042 case MSR_AMD64_PATCH_LOADER:
15c4a640 1043 break;
9ba075a6
AK		 1044 case 0x200 ... 0x2ff:
1045 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1046 case MSR_IA32_APICBASE:
1047 kvm_set_apic_base(vcpu, data);
1048 break;
0105d1a5
GN		 1049 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1050 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1051 case MSR_IA32_MISC_ENABLE:
ad312c7c 1052 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1053 break;
18068523
GOC		 1054 case MSR_KVM_WALL_CLOCK:
1055 vcpu->kvm->arch.wall_clock = data;
1056 kvm_write_wall_clock(vcpu->kvm, data);
1057 break;
1058 case MSR_KVM_SYSTEM_TIME: {
1059 if (vcpu->arch.time_page) {
1060 kvm_release_page_dirty(vcpu->arch.time_page);
1061 vcpu->arch.time_page = NULL;
1062 }
1063
1064 vcpu->arch.time = data;
1065
1066 /* we verify if the enable bit is set... */
1067 if (!(data & 1))
1068 break;
1069
1070 /* ...but clean it before doing the actual write */
1071 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1072
18068523
GOC		 1073 vcpu->arch.time_page =
1074 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1075
1076 if (is_error_page(vcpu->arch.time_page)) {
1077 kvm_release_page_clean(vcpu->arch.time_page);
1078 vcpu->arch.time_page = NULL;
1079 }
1080
c8076604 1081 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1082 break;
1083 }
890ca9ae
HY		 1084 case MSR_IA32_MCG_CTL:
1085 case MSR_IA32_MCG_STATUS:
1086 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1087 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1088
1089 /* Performance counters are not protected by a CPUID bit,
1090 * so we should check all of them in the generic path for the sake of
1091 * cross vendor migration.
1092 * Writing a zero into the event select MSRs disables them,
1093 * which we perfectly emulate ;-). Any other value should be at least
1094 * reported, some guests depend on them.
1095 */
1096 case MSR_P6_EVNTSEL0:
1097 case MSR_P6_EVNTSEL1:
1098 case MSR_K7_EVNTSEL0:
1099 case MSR_K7_EVNTSEL1:
1100 case MSR_K7_EVNTSEL2:
1101 case MSR_K7_EVNTSEL3:
1102 if (data != 0)
1103 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1104 "0x%x data 0x%llx\n", msr, data);
1105 break;
1106 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1107 * so we ignore writes to make it happy.
1108 */
1109 case MSR_P6_PERFCTR0:
1110 case MSR_P6_PERFCTR1:
1111 case MSR_K7_PERFCTR0:
1112 case MSR_K7_PERFCTR1:
1113 case MSR_K7_PERFCTR2:
1114 case MSR_K7_PERFCTR3:
1115 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1116 "0x%x data 0x%llx\n", msr, data);
1117 break;
15c4a640 1118 default:
ffde22ac
ES		 1119 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1120 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1121 if (!ignore_msrs) {
1122 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1123 msr, data);
1124 return 1;
1125 } else {
1126 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1127 msr, data);
1128 break;
1129 }
15c4a640
CO		 1130 }
1131 return 0;
1132}
1133EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1134
1135
1136/*
1137 * Reads an msr value (of 'msr_index') into 'pdata'.
1138 * Returns 0 on success, non-0 otherwise.
1139 * Assumes vcpu_load() was already called.
1140 */
1141int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1142{
1143 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1144}
1145
9ba075a6
AK		 1146static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1147{
0bed3b56
SY		 1148 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1149
9ba075a6
AK		 1150 if (!msr_mtrr_valid(msr))
1151 return 1;
1152
0bed3b56
SY		 1153 if (msr == MSR_MTRRdefType)
1154 *pdata = vcpu->arch.mtrr_state.def_type +
1155 (vcpu->arch.mtrr_state.enabled << 10);
1156 else if (msr == MSR_MTRRfix64K_00000)
1157 *pdata = p[0];
1158 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1159 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1160 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1161 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1162 else if (msr == MSR_IA32_CR_PAT)
1163 *pdata = vcpu->arch.pat;
1164 else { /* Variable MTRRs */
1165 int idx, is_mtrr_mask;
1166 u64 *pt;
1167
1168 idx = (msr - 0x200) / 2;
1169 is_mtrr_mask = msr - 0x200 - 2 * idx;
1170 if (!is_mtrr_mask)
1171 pt =
1172 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1173 else
1174 pt =
1175 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1176 *pdata = *pt;
1177 }
1178
9ba075a6
AK		 1179 return 0;
1180}
1181
890ca9ae 1182static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1183{
1184 u64 data;
890ca9ae
HY		 1185 u64 mcg_cap = vcpu->arch.mcg_cap;
1186 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1187
1188 switch (msr) {
15c4a640
CO		 1189 case MSR_IA32_P5_MC_ADDR:
1190 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1191 data = 0;
1192 break;
15c4a640 1193 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1194 data = vcpu->arch.mcg_cap;
1195 break;
c7ac679c 1196 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1197 if (!(mcg_cap & MCG_CTL_P))
1198 return 1;
1199 data = vcpu->arch.mcg_ctl;
1200 break;
1201 case MSR_IA32_MCG_STATUS:
1202 data = vcpu->arch.mcg_status;
1203 break;
1204 default:
1205 if (msr >= MSR_IA32_MC0_CTL &&
1206 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1207 u32 offset = msr - MSR_IA32_MC0_CTL;
1208 data = vcpu->arch.mce_banks[offset];
1209 break;
1210 }
1211 return 1;
1212 }
1213 *pdata = data;
1214 return 0;
1215}
1216
1217int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1218{
1219 u64 data;
1220
1221 switch (msr) {
890ca9ae 1222 case MSR_IA32_PLATFORM_ID:
15c4a640 1223 case MSR_IA32_UCODE_REV:
15c4a640 1224 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1225 case MSR_IA32_DEBUGCTLMSR:
1226 case MSR_IA32_LASTBRANCHFROMIP:
1227 case MSR_IA32_LASTBRANCHTOIP:
1228 case MSR_IA32_LASTINTFROMIP:
1229 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1230 case MSR_K8_SYSCFG:
1231 case MSR_K7_HWCR:
61a6bd67 1232 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1233 case MSR_P6_PERFCTR0:
1234 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1235 case MSR_P6_EVNTSEL0:
1236 case MSR_P6_EVNTSEL1:
9e699624 1237 case MSR_K7_EVNTSEL0:
1f3ee616 1238 case MSR_K7_PERFCTR0:
1fdbd48c 1239 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1240 case MSR_AMD64_NB_CFG:
f7c6d140 1241 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1242 data = 0;
1243 break;
9ba075a6
AK		 1244 case MSR_MTRRcap:
1245 data = 0x500 | KVM_NR_VAR_MTRR;
1246 break;
1247 case 0x200 ... 0x2ff:
1248 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1249 case 0xcd: /* fsb frequency */
1250 data = 3;
1251 break;
1252 case MSR_IA32_APICBASE:
1253 data = kvm_get_apic_base(vcpu);
1254 break;
0105d1a5
GN		 1255 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1256 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1257 break;
15c4a640 1258 case MSR_IA32_MISC_ENABLE:
ad312c7c 1259 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1260 break;
847f0ad8
AG		 1261 case MSR_IA32_PERF_STATUS:
1262 /* TSC increment by tick */
1263 data = 1000ULL;
1264 /* CPU multiplier */
1265 data |= (((uint64_t)4ULL) << 40);
1266 break;
15c4a640 1267 case MSR_EFER:
ad312c7c 1268 data = vcpu->arch.shadow_efer;
15c4a640 1269 break;
18068523
GOC		 1270 case MSR_KVM_WALL_CLOCK:
1271 data = vcpu->kvm->arch.wall_clock;
1272 break;
1273 case MSR_KVM_SYSTEM_TIME:
1274 data = vcpu->arch.time;
1275 break;
890ca9ae
HY		 1276 case MSR_IA32_P5_MC_ADDR:
1277 case MSR_IA32_P5_MC_TYPE:
1278 case MSR_IA32_MCG_CAP:
1279 case MSR_IA32_MCG_CTL:
1280 case MSR_IA32_MCG_STATUS:
1281 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1282 return get_msr_mce(vcpu, msr, pdata);
15c4a640 1283 default:
ed85c068
AP		 1284 if (!ignore_msrs) {
1285 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1286 return 1;
1287 } else {
1288 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1289 data = 0;
1290 }
1291 break;
15c4a640
CO		 1292 }
1293 *pdata = data;
1294 return 0;
1295}
1296EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1297
313a3dc7
CO		 1298/*
1299 * Read or write a bunch of msrs. All parameters are kernel addresses.
1300 *
1301 * @return number of msrs set successfully.
1302 */
1303static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1304 struct kvm_msr_entry *entries,
1305 int (*do_msr)(struct kvm_vcpu *vcpu,
1306 unsigned index, u64 *data))
1307{
1308 int i;
1309
1310 vcpu_load(vcpu);
1311
3200f405 1312 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1313 for (i = 0; i < msrs->nmsrs; ++i)
1314 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1315 break;
3200f405 1316 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1317
1318 vcpu_put(vcpu);
1319
1320 return i;
1321}
1322
1323/*
1324 * Read or write a bunch of msrs. Parameters are user addresses.
1325 *
1326 * @return number of msrs set successfully.
1327 */
1328static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1329 int (*do_msr)(struct kvm_vcpu *vcpu,
1330 unsigned index, u64 *data),
1331 int writeback)
1332{
1333 struct kvm_msrs msrs;
1334 struct kvm_msr_entry *entries;
1335 int r, n;
1336 unsigned size;
1337
1338 r = -EFAULT;
1339 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1340 goto out;
1341
1342 r = -E2BIG;
1343 if (msrs.nmsrs >= MAX_IO_MSRS)
1344 goto out;
1345
1346 r = -ENOMEM;
1347 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1348 entries = vmalloc(size);
1349 if (!entries)
1350 goto out;
1351
1352 r = -EFAULT;
1353 if (copy_from_user(entries, user_msrs->entries, size))
1354 goto out_free;
1355
1356 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1357 if (r < 0)
1358 goto out_free;
1359
1360 r = -EFAULT;
1361 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1362 goto out_free;
1363
1364 r = n;
1365
1366out_free:
1367 vfree(entries);
1368out:
1369 return r;
1370}
1371
018d00d2
ZX		 1372int kvm_dev_ioctl_check_extension(long ext)
1373{
1374 int r;
1375
1376 switch (ext) {
1377 case KVM_CAP_IRQCHIP:
1378 case KVM_CAP_HLT:
1379 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1380 case KVM_CAP_SET_TSS_ADDR:
07716717 1381 case KVM_CAP_EXT_CPUID:
c8076604 1382 case KVM_CAP_CLOCKSOURCE:
7837699f 1383 case KVM_CAP_PIT:
a28e4f5a 1384 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1385 case KVM_CAP_MP_STATE:
ed848624 1386 case KVM_CAP_SYNC_MMU:
52d939a0 1387 case KVM_CAP_REINJECT_CONTROL:
4925663a 1388 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1389 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1390 case KVM_CAP_IRQFD:
d34e6b17 1391 case KVM_CAP_IOEVENTFD:
c5ff41ce 1392 case KVM_CAP_PIT2:
e9f42757 1393 case KVM_CAP_PIT_STATE2:
b927a3ce 1394 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1395 case KVM_CAP_XEN_HVM:
afbcf7ab 1396 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1397 case KVM_CAP_VCPU_EVENTS:
018d00d2
ZX		 1398 r = 1;
1399 break;
542472b5
LV		 1400 case KVM_CAP_COALESCED_MMIO:
1401 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1402 break;
774ead3a
AK		 1403 case KVM_CAP_VAPIC:
1404 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1405 break;
f725230a
AK		 1406 case KVM_CAP_NR_VCPUS:
1407 r = KVM_MAX_VCPUS;
1408 break;
a988b910
AK		 1409 case KVM_CAP_NR_MEMSLOTS:
1410 r = KVM_MEMORY_SLOTS;
1411 break;
a68a6a72
MT		 1412 case KVM_CAP_PV_MMU: /* obsolete */
1413 r = 0;
2f333bcb 1414 break;
62c476c7 1415 case KVM_CAP_IOMMU:
19de40a8 1416 r = iommu_found();
62c476c7 1417 break;
890ca9ae
HY		 1418 case KVM_CAP_MCE:
1419 r = KVM_MAX_MCE_BANKS;
1420 break;
018d00d2
ZX		 1421 default:
1422 r = 0;
1423 break;
1424 }
1425 return r;
1426
1427}
1428
043405e1
CO		 1429long kvm_arch_dev_ioctl(struct file *filp,
1430 unsigned int ioctl, unsigned long arg)
1431{
1432 void __user *argp = (void __user *)arg;
1433 long r;
1434
1435 switch (ioctl) {
1436 case KVM_GET_MSR_INDEX_LIST: {
1437 struct kvm_msr_list __user *user_msr_list = argp;
1438 struct kvm_msr_list msr_list;
1439 unsigned n;
1440
1441 r = -EFAULT;
1442 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1443 goto out;
1444 n = msr_list.nmsrs;
1445 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1446 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1447 goto out;
1448 r = -E2BIG;
e125e7b6 1449 if (n < msr_list.nmsrs)
043405e1
CO		 1450 goto out;
1451 r = -EFAULT;
1452 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1453 num_msrs_to_save * sizeof(u32)))
1454 goto out;
e125e7b6 1455 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1456 &emulated_msrs,
1457 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1458 goto out;
1459 r = 0;
1460 break;
1461 }
674eea0f
AK		 1462 case KVM_GET_SUPPORTED_CPUID: {
1463 struct kvm_cpuid2 __user *cpuid_arg = argp;
1464 struct kvm_cpuid2 cpuid;
1465
1466 r = -EFAULT;
1467 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1468 goto out;
1469 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1470 cpuid_arg->entries);
674eea0f
AK		 1471 if (r)
1472 goto out;
1473
1474 r = -EFAULT;
1475 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1476 goto out;
1477 r = 0;
1478 break;
1479 }
890ca9ae
HY		 1480 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1481 u64 mce_cap;
1482
1483 mce_cap = KVM_MCE_CAP_SUPPORTED;
1484 r = -EFAULT;
1485 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1486 goto out;
1487 r = 0;
1488 break;
1489 }
043405e1
CO		 1490 default:
1491 r = -EINVAL;
1492 }
1493out:
1494 return r;
1495}
1496
313a3dc7
CO		 1497void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1498{
1499 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1500 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1501 unsigned long khz = cpufreq_quick_get(cpu);
1502 if (!khz)
1503 khz = tsc_khz;
1504 per_cpu(cpu_tsc_khz, cpu) = khz;
1505 }
c8076604 1506 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1507}
1508
1509void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1510{
1511 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1512 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1513}
1514
07716717 1515static int is_efer_nx(void)
313a3dc7 1516{
e286e86e 1517 unsigned long long efer = 0;
313a3dc7 1518
e286e86e 1519 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1520 return efer & EFER_NX;
1521}
1522
1523static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1524{
1525 int i;
1526 struct kvm_cpuid_entry2 *e, *entry;
1527
313a3dc7 1528 entry = NULL;
ad312c7c
ZX		 1529 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1530 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1531 if (e->function == 0x80000001) {
1532 entry = e;
1533 break;
1534 }
1535 }
07716717 1536 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1537 entry->edx &= ~(1 << 20);
1538 printk(KERN_INFO "kvm: guest NX capability removed\n");
1539 }
1540}
1541
07716717 1542/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1543static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1544 struct kvm_cpuid *cpuid,
1545 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1546{
1547 int r, i;
1548 struct kvm_cpuid_entry *cpuid_entries;
1549
1550 r = -E2BIG;
1551 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1552 goto out;
1553 r = -ENOMEM;
1554 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1555 if (!cpuid_entries)
1556 goto out;
1557 r = -EFAULT;
1558 if (copy_from_user(cpuid_entries, entries,
1559 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1560 goto out_free;
1561 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1562 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1563 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1564 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1565 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1566 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1567 vcpu->arch.cpuid_entries[i].index = 0;
1568 vcpu->arch.cpuid_entries[i].flags = 0;
1569 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1570 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1571 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1572 }
1573 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1574 cpuid_fix_nx_cap(vcpu);
1575 r = 0;
fc61b800 1576 kvm_apic_set_version(vcpu);
0e851880 1577 kvm_x86_ops->cpuid_update(vcpu);
07716717
DK		 1578
1579out_free:
1580 vfree(cpuid_entries);
1581out:
1582 return r;
1583}
1584
1585static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1586 struct kvm_cpuid2 *cpuid,
1587 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1588{
1589 int r;
1590
1591 r = -E2BIG;
1592 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1593 goto out;
1594 r = -EFAULT;
ad312c7c 1595 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1596 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1597 goto out;
ad312c7c 1598 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1599 kvm_apic_set_version(vcpu);
0e851880 1600 kvm_x86_ops->cpuid_update(vcpu);
313a3dc7
CO		 1601 return 0;
1602
1603out:
1604 return r;
1605}
1606
07716717 1607static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1608 struct kvm_cpuid2 *cpuid,
1609 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1610{
1611 int r;
1612
1613 r = -E2BIG;
ad312c7c 1614 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1615 goto out;
1616 r = -EFAULT;
ad312c7c 1617 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1618 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1619 goto out;
1620 return 0;
1621
1622out:
ad312c7c 1623 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1624 return r;
1625}
1626
07716717 1627static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1628 u32 index)
07716717
DK		 1629{
1630 entry->function = function;
1631 entry->index = index;
1632 cpuid_count(entry->function, entry->index,
19355475 1633 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1634 entry->flags = 0;
1635}
1636
7faa4ee1
AK		 1637#define F(x) bit(X86_FEATURE_##x)
1638
07716717
DK		 1639static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1640 u32 index, int *nent, int maxnent)
1641{
7faa4ee1 1642 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
344f414f 1643 unsigned f_gbpages = kvm_x86_ops->gb_page_enable() ? F(GBPAGES) : 0;
07716717 1644#ifdef CONFIG_X86_64
7faa4ee1
AK		 1645 unsigned f_lm = F(LM);
1646#else
1647 unsigned f_lm = 0;
07716717 1648#endif
4e47c7a6 1649 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1650
1651 /* cpuid 1.edx */
1652 const u32 kvm_supported_word0_x86_features =
1653 F(FPU) | F(VME) | F(DE) | F(PSE) |
1654 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1655 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1656 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1657 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1658 0 /* Reserved, DS, ACPI */ | F(MMX) |
1659 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1660 0 /* HTT, TM, Reserved, PBE */;
1661 /* cpuid 0x80000001.edx */
1662 const u32 kvm_supported_word1_x86_features =
1663 F(FPU) | F(VME) | F(DE) | F(PSE) |
1664 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1665 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1666 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1667 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1668 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1669 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1670 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1671 /* cpuid 1.ecx */
1672 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1673 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1674 0 /* DS-CPL, VMX, SMX, EST */ |
1675 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1676 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1677 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1678 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1679 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1680 /* cpuid 0x80000001.ecx */
07716717 1681 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1682 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1683 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1684 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1685 0 /* SKINIT */ | 0 /* WDT */;
07716717 1686
19355475 1687 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1688 get_cpu();
1689 do_cpuid_1_ent(entry, function, index);
1690 ++*nent;
1691
1692 switch (function) {
1693 case 0:
1694 entry->eax = min(entry->eax, (u32)0xb);
1695 break;
1696 case 1:
1697 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1698 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1699 /* we support x2apic emulation even if host does not support
1700 * it since we emulate x2apic in software */
1701 entry->ecx |= F(X2APIC);
07716717
DK		 1702 break;
1703 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1704 * may return different values. This forces us to get_cpu() before
1705 * issuing the first command, and also to emulate this annoying behavior
1706 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1707 case 2: {
1708 int t, times = entry->eax & 0xff;
1709
1710 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1711 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1712 for (t = 1; t < times && *nent < maxnent; ++t) {
1713 do_cpuid_1_ent(&entry[t], function, 0);
1714 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1715 ++*nent;
1716 }
1717 break;
1718 }
1719 /* function 4 and 0xb have additional index. */
1720 case 4: {
14af3f3c 1721 int i, cache_type;
07716717
DK		 1722
1723 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1724 /* read more entries until cache_type is zero */
14af3f3c
HH		 1725 for (i = 1; *nent < maxnent; ++i) {
1726 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1727 if (!cache_type)
1728 break;
14af3f3c
HH		 1729 do_cpuid_1_ent(&entry[i], function, i);
1730 entry[i].flags |=
07716717
DK		 1731 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1732 ++*nent;
1733 }
1734 break;
1735 }
1736 case 0xb: {
14af3f3c 1737 int i, level_type;
07716717
DK		 1738
1739 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1740 /* read more entries until level_type is zero */
14af3f3c 1741 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1742 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1743 if (!level_type)
1744 break;
14af3f3c
HH		 1745 do_cpuid_1_ent(&entry[i], function, i);
1746 entry[i].flags |=
07716717
DK		 1747 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1748 ++*nent;
1749 }
1750 break;
1751 }
1752 case 0x80000000:
1753 entry->eax = min(entry->eax, 0x8000001a);
1754 break;
1755 case 0x80000001:
1756 entry->edx &= kvm_supported_word1_x86_features;
1757 entry->ecx &= kvm_supported_word6_x86_features;
1758 break;
1759 }
1760 put_cpu();
1761}
1762
7faa4ee1
AK		 1763#undef F
1764
674eea0f 1765static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1766 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1767{
1768 struct kvm_cpuid_entry2 *cpuid_entries;
1769 int limit, nent = 0, r = -E2BIG;
1770 u32 func;
1771
1772 if (cpuid->nent < 1)
1773 goto out;
6a544355
AK		 1774 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1775 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 1776 r = -ENOMEM;
1777 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1778 if (!cpuid_entries)
1779 goto out;
1780
1781 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1782 limit = cpuid_entries[0].eax;
1783 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1784 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1785 &nent, cpuid->nent);
07716717
DK		 1786 r = -E2BIG;
1787 if (nent >= cpuid->nent)
1788 goto out_free;
1789
1790 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1791 limit = cpuid_entries[nent - 1].eax;
1792 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1793 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1794 &nent, cpuid->nent);
cb007648
MM		 1795 r = -E2BIG;
1796 if (nent >= cpuid->nent)
1797 goto out_free;
1798
07716717
DK		 1799 r = -EFAULT;
1800 if (copy_to_user(entries, cpuid_entries,
19355475 1801 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1802 goto out_free;
1803 cpuid->nent = nent;
1804 r = 0;
1805
1806out_free:
1807 vfree(cpuid_entries);
1808out:
1809 return r;
1810}
1811
313a3dc7
CO		 1812static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1813 struct kvm_lapic_state *s)
1814{
1815 vcpu_load(vcpu);
ad312c7c 1816 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1817 vcpu_put(vcpu);
1818
1819 return 0;
1820}
1821
1822static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1823 struct kvm_lapic_state *s)
1824{
1825 vcpu_load(vcpu);
ad312c7c 1826 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 1827 kvm_apic_post_state_restore(vcpu);
cb142eb7 1828 update_cr8_intercept(vcpu);
313a3dc7
CO		 1829 vcpu_put(vcpu);
1830
1831 return 0;
1832}
1833
f77bc6a4
ZX		 1834static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1835 struct kvm_interrupt *irq)
1836{
1837 if (irq->irq < 0 || irq->irq >= 256)
1838 return -EINVAL;
1839 if (irqchip_in_kernel(vcpu->kvm))
1840 return -ENXIO;
1841 vcpu_load(vcpu);
1842
66fd3f7f 1843 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1844
1845 vcpu_put(vcpu);
1846
1847 return 0;
1848}
1849
c4abb7c9
JK		 1850static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1851{
1852 vcpu_load(vcpu);
1853 kvm_inject_nmi(vcpu);
1854 vcpu_put(vcpu);
1855
1856 return 0;
1857}
1858
b209749f
AK		 1859static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1860 struct kvm_tpr_access_ctl *tac)
1861{
1862 if (tac->flags)
1863 return -EINVAL;
1864 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1865 return 0;
1866}
1867
890ca9ae
HY		 1868static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1869 u64 mcg_cap)
1870{
1871 int r;
1872 unsigned bank_num = mcg_cap & 0xff, bank;
1873
1874 r = -EINVAL;
a9e38c3e 1875 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 1876 goto out;
1877 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1878 goto out;
1879 r = 0;
1880 vcpu->arch.mcg_cap = mcg_cap;
1881 /* Init IA32_MCG_CTL to all 1s */
1882 if (mcg_cap & MCG_CTL_P)
1883 vcpu->arch.mcg_ctl = ~(u64)0;
1884 /* Init IA32_MCi_CTL to all 1s */
1885 for (bank = 0; bank < bank_num; bank++)
1886 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1887out:
1888 return r;
1889}
1890
1891static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1892 struct kvm_x86_mce *mce)
1893{
1894 u64 mcg_cap = vcpu->arch.mcg_cap;
1895 unsigned bank_num = mcg_cap & 0xff;
1896 u64 *banks = vcpu->arch.mce_banks;
1897
1898 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1899 return -EINVAL;
1900 /*
1901 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1902 * reporting is disabled
1903 */
1904 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1905 vcpu->arch.mcg_ctl != ~(u64)0)
1906 return 0;
1907 banks += 4 * mce->bank;
1908 /*
1909 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1910 * reporting is disabled for the bank
1911 */
1912 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1913 return 0;
1914 if (mce->status & MCI_STATUS_UC) {
1915 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 1916 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 1917 printk(KERN_DEBUG "kvm: set_mce: "
1918 "injects mce exception while "
1919 "previous one is in progress!\n");
1920 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1921 return 0;
1922 }
1923 if (banks[1] & MCI_STATUS_VAL)
1924 mce->status |= MCI_STATUS_OVER;
1925 banks[2] = mce->addr;
1926 banks[3] = mce->misc;
1927 vcpu->arch.mcg_status = mce->mcg_status;
1928 banks[1] = mce->status;
1929 kvm_queue_exception(vcpu, MC_VECTOR);
1930 } else if (!(banks[1] & MCI_STATUS_VAL)
1931 || !(banks[1] & MCI_STATUS_UC)) {
1932 if (banks[1] & MCI_STATUS_VAL)
1933 mce->status |= MCI_STATUS_OVER;
1934 banks[2] = mce->addr;
1935 banks[3] = mce->misc;
1936 banks[1] = mce->status;
1937 } else
1938 banks[1] |= MCI_STATUS_OVER;
1939 return 0;
1940}
1941
3cfc3092
JK		 1942static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
1943 struct kvm_vcpu_events *events)
1944{
1945 vcpu_load(vcpu);
1946
1947 events->exception.injected = vcpu->arch.exception.pending;
1948 events->exception.nr = vcpu->arch.exception.nr;
1949 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
1950 events->exception.error_code = vcpu->arch.exception.error_code;
1951
1952 events->interrupt.injected = vcpu->arch.interrupt.pending;
1953 events->interrupt.nr = vcpu->arch.interrupt.nr;
1954 events->interrupt.soft = vcpu->arch.interrupt.soft;
1955
1956 events->nmi.injected = vcpu->arch.nmi_injected;
1957 events->nmi.pending = vcpu->arch.nmi_pending;
1958 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
1959
1960 events->sipi_vector = vcpu->arch.sipi_vector;
1961
dab4b911
JK		 1962 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
1963 | KVM_VCPUEVENT_VALID_SIPI_VECTOR);
3cfc3092
JK		 1964
1965 vcpu_put(vcpu);
1966}
1967
1968static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
1969 struct kvm_vcpu_events *events)
1970{
dab4b911
JK		 1971 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
1972 | KVM_VCPUEVENT_VALID_SIPI_VECTOR))
3cfc3092
JK		 1973 return -EINVAL;
1974
1975 vcpu_load(vcpu);
1976
1977 vcpu->arch.exception.pending = events->exception.injected;
1978 vcpu->arch.exception.nr = events->exception.nr;
1979 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
1980 vcpu->arch.exception.error_code = events->exception.error_code;
1981
1982 vcpu->arch.interrupt.pending = events->interrupt.injected;
1983 vcpu->arch.interrupt.nr = events->interrupt.nr;
1984 vcpu->arch.interrupt.soft = events->interrupt.soft;
1985 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
1986 kvm_pic_clear_isr_ack(vcpu->kvm);
1987
1988 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 1989 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
1990 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 1991 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
1992
dab4b911
JK		 1993 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
1994 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 1995
1996 vcpu_put(vcpu);
1997
1998 return 0;
1999}
2000
313a3dc7
CO		 2001long kvm_arch_vcpu_ioctl(struct file *filp,
2002 unsigned int ioctl, unsigned long arg)
2003{
2004 struct kvm_vcpu *vcpu = filp->private_data;
2005 void __user *argp = (void __user *)arg;
2006 int r;
b772ff36 2007 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2008
2009 switch (ioctl) {
2010 case KVM_GET_LAPIC: {
2204ae3c
MT		 2011 r = -EINVAL;
2012 if (!vcpu->arch.apic)
2013 goto out;
b772ff36 2014 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2015
b772ff36
DH		 2016 r = -ENOMEM;
2017 if (!lapic)
2018 goto out;
2019 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2020 if (r)
2021 goto out;
2022 r = -EFAULT;
b772ff36 2023 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2024 goto out;
2025 r = 0;
2026 break;
2027 }
2028 case KVM_SET_LAPIC: {
2204ae3c
MT		 2029 r = -EINVAL;
2030 if (!vcpu->arch.apic)
2031 goto out;
b772ff36
DH		 2032 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2033 r = -ENOMEM;
2034 if (!lapic)
2035 goto out;
313a3dc7 2036 r = -EFAULT;
b772ff36 2037 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2038 goto out;
b772ff36 2039 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2040 if (r)
2041 goto out;
2042 r = 0;
2043 break;
2044 }
f77bc6a4
ZX		 2045 case KVM_INTERRUPT: {
2046 struct kvm_interrupt irq;
2047
2048 r = -EFAULT;
2049 if (copy_from_user(&irq, argp, sizeof irq))
2050 goto out;
2051 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2052 if (r)
2053 goto out;
2054 r = 0;
2055 break;
2056 }
c4abb7c9
JK		 2057 case KVM_NMI: {
2058 r = kvm_vcpu_ioctl_nmi(vcpu);
2059 if (r)
2060 goto out;
2061 r = 0;
2062 break;
2063 }
313a3dc7
CO		 2064 case KVM_SET_CPUID: {
2065 struct kvm_cpuid __user *cpuid_arg = argp;
2066 struct kvm_cpuid cpuid;
2067
2068 r = -EFAULT;
2069 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2070 goto out;
2071 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2072 if (r)
2073 goto out;
2074 break;
2075 }
07716717
DK		 2076 case KVM_SET_CPUID2: {
2077 struct kvm_cpuid2 __user *cpuid_arg = argp;
2078 struct kvm_cpuid2 cpuid;
2079
2080 r = -EFAULT;
2081 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2082 goto out;
2083 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2084 cpuid_arg->entries);
07716717
DK		 2085 if (r)
2086 goto out;
2087 break;
2088 }
2089 case KVM_GET_CPUID2: {
2090 struct kvm_cpuid2 __user *cpuid_arg = argp;
2091 struct kvm_cpuid2 cpuid;
2092
2093 r = -EFAULT;
2094 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2095 goto out;
2096 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2097 cpuid_arg->entries);
07716717
DK		 2098 if (r)
2099 goto out;
2100 r = -EFAULT;
2101 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2102 goto out;
2103 r = 0;
2104 break;
2105 }
313a3dc7
CO		 2106 case KVM_GET_MSRS:
2107 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2108 break;
2109 case KVM_SET_MSRS:
2110 r = msr_io(vcpu, argp, do_set_msr, 0);
2111 break;
b209749f
AK		 2112 case KVM_TPR_ACCESS_REPORTING: {
2113 struct kvm_tpr_access_ctl tac;
2114
2115 r = -EFAULT;
2116 if (copy_from_user(&tac, argp, sizeof tac))
2117 goto out;
2118 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2119 if (r)
2120 goto out;
2121 r = -EFAULT;
2122 if (copy_to_user(argp, &tac, sizeof tac))
2123 goto out;
2124 r = 0;
2125 break;
2126 };
b93463aa
AK		 2127 case KVM_SET_VAPIC_ADDR: {
2128 struct kvm_vapic_addr va;
2129
2130 r = -EINVAL;
2131 if (!irqchip_in_kernel(vcpu->kvm))
2132 goto out;
2133 r = -EFAULT;
2134 if (copy_from_user(&va, argp, sizeof va))
2135 goto out;
2136 r = 0;
2137 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2138 break;
2139 }
890ca9ae
HY		 2140 case KVM_X86_SETUP_MCE: {
2141 u64 mcg_cap;
2142
2143 r = -EFAULT;
2144 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2145 goto out;
2146 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2147 break;
2148 }
2149 case KVM_X86_SET_MCE: {
2150 struct kvm_x86_mce mce;
2151
2152 r = -EFAULT;
2153 if (copy_from_user(&mce, argp, sizeof mce))
2154 goto out;
2155 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2156 break;
2157 }
3cfc3092
JK		 2158 case KVM_GET_VCPU_EVENTS: {
2159 struct kvm_vcpu_events events;
2160
2161 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2162
2163 r = -EFAULT;
2164 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2165 break;
2166 r = 0;
2167 break;
2168 }
2169 case KVM_SET_VCPU_EVENTS: {
2170 struct kvm_vcpu_events events;
2171
2172 r = -EFAULT;
2173 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2174 break;
2175
2176 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2177 break;
2178 }
313a3dc7
CO		 2179 default:
2180 r = -EINVAL;
2181 }
2182out:
7a6ce84c 2183 kfree(lapic);
313a3dc7
CO		 2184 return r;
2185}
2186
1fe779f8
CO		 2187static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2188{
2189 int ret;
2190
2191 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2192 return -1;
2193 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2194 return ret;
2195}
2196
b927a3ce
SY		 2197static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2198 u64 ident_addr)
2199{
2200 kvm->arch.ept_identity_map_addr = ident_addr;
2201 return 0;
2202}
2203
1fe779f8
CO		 2204static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2205 u32 kvm_nr_mmu_pages)
2206{
2207 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2208 return -EINVAL;
2209
72dc67a6 2210 down_write(&kvm->slots_lock);
7c8a83b7 2211 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2212
2213 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2214 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2215
7c8a83b7 2216 spin_unlock(&kvm->mmu_lock);
72dc67a6 2217 up_write(&kvm->slots_lock);
1fe779f8
CO		 2218 return 0;
2219}
2220
2221static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2222{
f05e70ac 2223 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2224}
2225
e9f85cde
ZX		 2226gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2227{
2228 int i;
2229 struct kvm_mem_alias *alias;
fef9cce0 2230 struct kvm_mem_aliases *aliases = kvm->arch.aliases;
e9f85cde 2231
fef9cce0
MT		 2232 for (i = 0; i < aliases->naliases; ++i) {
2233 alias = &aliases->aliases[i];
e9f85cde
ZX		 2234 if (gfn >= alias->base_gfn
2235 && gfn < alias->base_gfn + alias->npages)
2236 return alias->target_gfn + gfn - alias->base_gfn;
2237 }
2238 return gfn;
2239}
2240
1fe779f8
CO		 2241/*
2242 * Set a new alias region. Aliases map a portion of physical memory into
2243 * another portion. This is useful for memory windows, for example the PC
2244 * VGA region.
2245 */
2246static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2247 struct kvm_memory_alias *alias)
2248{
2249 int r, n;
2250 struct kvm_mem_alias *p;
fef9cce0 2251 struct kvm_mem_aliases *aliases;
1fe779f8
CO		 2252
2253 r = -EINVAL;
2254 /* General sanity checks */
2255 if (alias->memory_size & (PAGE_SIZE - 1))
2256 goto out;
2257 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2258 goto out;
2259 if (alias->slot >= KVM_ALIAS_SLOTS)
2260 goto out;
2261 if (alias->guest_phys_addr + alias->memory_size
2262 < alias->guest_phys_addr)
2263 goto out;
2264 if (alias->target_phys_addr + alias->memory_size
2265 < alias->target_phys_addr)
2266 goto out;
2267
72dc67a6 2268 down_write(&kvm->slots_lock);
a1708ce8 2269 spin_lock(&kvm->mmu_lock);
1fe779f8 2270
fef9cce0
MT		 2271 aliases = kvm->arch.aliases;
2272
2273 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2274 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2275 p->npages = alias->memory_size >> PAGE_SHIFT;
2276 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
2277
2278 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2279 if (aliases->aliases[n - 1].npages)
1fe779f8 2280 break;
fef9cce0 2281 aliases->naliases = n;
1fe779f8 2282
a1708ce8 2283 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 2284 kvm_mmu_zap_all(kvm);
2285
72dc67a6 2286 up_write(&kvm->slots_lock);
1fe779f8
CO		 2287
2288 return 0;
2289
2290out:
2291 return r;
2292}
2293
2294static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2295{
2296 int r;
2297
2298 r = 0;
2299 switch (chip->chip_id) {
2300 case KVM_IRQCHIP_PIC_MASTER:
2301 memcpy(&chip->chip.pic,
2302 &pic_irqchip(kvm)->pics[0],
2303 sizeof(struct kvm_pic_state));
2304 break;
2305 case KVM_IRQCHIP_PIC_SLAVE:
2306 memcpy(&chip->chip.pic,
2307 &pic_irqchip(kvm)->pics[1],
2308 sizeof(struct kvm_pic_state));
2309 break;
2310 case KVM_IRQCHIP_IOAPIC:
eba0226b 2311 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2312 break;
2313 default:
2314 r = -EINVAL;
2315 break;
2316 }
2317 return r;
2318}
2319
2320static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2321{
2322 int r;
2323
2324 r = 0;
2325 switch (chip->chip_id) {
2326 case KVM_IRQCHIP_PIC_MASTER:
894a9c55 2327 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2328 memcpy(&pic_irqchip(kvm)->pics[0],
2329 &chip->chip.pic,
2330 sizeof(struct kvm_pic_state));
894a9c55 2331 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2332 break;
2333 case KVM_IRQCHIP_PIC_SLAVE:
894a9c55 2334 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2335 memcpy(&pic_irqchip(kvm)->pics[1],
2336 &chip->chip.pic,
2337 sizeof(struct kvm_pic_state));
894a9c55 2338 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2339 break;
2340 case KVM_IRQCHIP_IOAPIC:
eba0226b 2341 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2342 break;
2343 default:
2344 r = -EINVAL;
2345 break;
2346 }
2347 kvm_pic_update_irq(pic_irqchip(kvm));
2348 return r;
2349}
2350
e0f63cb9
SY		 2351static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2352{
2353 int r = 0;
2354
894a9c55 2355 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2356 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2357 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2358 return r;
2359}
2360
2361static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2362{
2363 int r = 0;
2364
894a9c55 2365 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2366 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2367 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2368 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2369 return r;
2370}
2371
2372static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2373{
2374 int r = 0;
2375
2376 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2377 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2378 sizeof(ps->channels));
2379 ps->flags = kvm->arch.vpit->pit_state.flags;
2380 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2381 return r;
2382}
2383
2384static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2385{
2386 int r = 0, start = 0;
2387 u32 prev_legacy, cur_legacy;
2388 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2389 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2390 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2391 if (!prev_legacy && cur_legacy)
2392 start = 1;
2393 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2394 sizeof(kvm->arch.vpit->pit_state.channels));
2395 kvm->arch.vpit->pit_state.flags = ps->flags;
2396 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2397 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2398 return r;
2399}
2400
52d939a0
MT		 2401static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2402 struct kvm_reinject_control *control)
2403{
2404 if (!kvm->arch.vpit)
2405 return -ENXIO;
894a9c55 2406 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2407 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2408 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2409 return 0;
2410}
2411
5bb064dc
ZX		 2412/*
2413 * Get (and clear) the dirty memory log for a memory slot.
2414 */
2415int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2416 struct kvm_dirty_log *log)
2417{
2418 int r;
2419 int n;
2420 struct kvm_memory_slot *memslot;
2421 int is_dirty = 0;
2422
72dc67a6 2423 down_write(&kvm->slots_lock);
5bb064dc
ZX		 2424
2425 r = kvm_get_dirty_log(kvm, log, &is_dirty);
2426 if (r)
2427 goto out;
2428
2429 /* If nothing is dirty, don't bother messing with page tables. */
2430 if (is_dirty) {
7c8a83b7 2431 spin_lock(&kvm->mmu_lock);
5bb064dc 2432 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2433 spin_unlock(&kvm->mmu_lock);
46a26bf5 2434 memslot = &kvm->memslots->memslots[log->slot];
5bb064dc
ZX		 2435 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2436 memset(memslot->dirty_bitmap, 0, n);
2437 }
2438 r = 0;
2439out:
72dc67a6 2440 up_write(&kvm->slots_lock);
5bb064dc
ZX		 2441 return r;
2442}
2443
1fe779f8
CO		 2444long kvm_arch_vm_ioctl(struct file *filp,
2445 unsigned int ioctl, unsigned long arg)
2446{
2447 struct kvm *kvm = filp->private_data;
2448 void __user *argp = (void __user *)arg;
367e1319 2449 int r = -ENOTTY;
f0d66275
DH		 2450 /*
2451 * This union makes it completely explicit to gcc-3.x
2452 * that these two variables' stack usage should be
2453 * combined, not added together.
2454 */
2455 union {
2456 struct kvm_pit_state ps;
e9f42757 2457 struct kvm_pit_state2 ps2;
f0d66275 2458 struct kvm_memory_alias alias;
c5ff41ce 2459 struct kvm_pit_config pit_config;
f0d66275 2460 } u;
1fe779f8
CO		 2461
2462 switch (ioctl) {
2463 case KVM_SET_TSS_ADDR:
2464 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2465 if (r < 0)
2466 goto out;
2467 break;
b927a3ce
SY		 2468 case KVM_SET_IDENTITY_MAP_ADDR: {
2469 u64 ident_addr;
2470
2471 r = -EFAULT;
2472 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2473 goto out;
2474 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2475 if (r < 0)
2476 goto out;
2477 break;
2478 }
1fe779f8
CO		 2479 case KVM_SET_MEMORY_REGION: {
2480 struct kvm_memory_region kvm_mem;
2481 struct kvm_userspace_memory_region kvm_userspace_mem;
2482
2483 r = -EFAULT;
2484 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2485 goto out;
2486 kvm_userspace_mem.slot = kvm_mem.slot;
2487 kvm_userspace_mem.flags = kvm_mem.flags;
2488 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2489 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2490 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2491 if (r)
2492 goto out;
2493 break;
2494 }
2495 case KVM_SET_NR_MMU_PAGES:
2496 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2497 if (r)
2498 goto out;
2499 break;
2500 case KVM_GET_NR_MMU_PAGES:
2501 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2502 break;
f0d66275 2503 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2504 r = -EFAULT;
f0d66275 2505 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2506 goto out;
f0d66275 2507 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2508 if (r)
2509 goto out;
2510 break;
3ddea128
MT		 2511 case KVM_CREATE_IRQCHIP: {
2512 struct kvm_pic *vpic;
2513
2514 mutex_lock(&kvm->lock);
2515 r = -EEXIST;
2516 if (kvm->arch.vpic)
2517 goto create_irqchip_unlock;
1fe779f8 2518 r = -ENOMEM;
3ddea128
MT		 2519 vpic = kvm_create_pic(kvm);
2520 if (vpic) {
1fe779f8
CO		 2521 r = kvm_ioapic_init(kvm);
2522 if (r) {
3ddea128
MT		 2523 kfree(vpic);
2524 goto create_irqchip_unlock;
1fe779f8
CO		 2525 }
2526 } else
3ddea128
MT		 2527 goto create_irqchip_unlock;
2528 smp_wmb();
2529 kvm->arch.vpic = vpic;
2530 smp_wmb();
399ec807
AK		 2531 r = kvm_setup_default_irq_routing(kvm);
2532 if (r) {
3ddea128 2533 mutex_lock(&kvm->irq_lock);
399ec807
AK		 2534 kfree(kvm->arch.vpic);
2535 kfree(kvm->arch.vioapic);
3ddea128
MT		 2536 kvm->arch.vpic = NULL;
2537 kvm->arch.vioapic = NULL;
2538 mutex_unlock(&kvm->irq_lock);
399ec807 2539 }
3ddea128
MT		 2540 create_irqchip_unlock:
2541 mutex_unlock(&kvm->lock);
1fe779f8 2542 break;
3ddea128 2543 }
7837699f 2544 case KVM_CREATE_PIT:
c5ff41ce
JK		 2545 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2546 goto create_pit;
2547 case KVM_CREATE_PIT2:
2548 r = -EFAULT;
2549 if (copy_from_user(&u.pit_config, argp,
2550 sizeof(struct kvm_pit_config)))
2551 goto out;
2552 create_pit:
108b5669 2553 down_write(&kvm->slots_lock);
269e05e4
AK		 2554 r = -EEXIST;
2555 if (kvm->arch.vpit)
2556 goto create_pit_unlock;
7837699f 2557 r = -ENOMEM;
c5ff41ce 2558 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2559 if (kvm->arch.vpit)
2560 r = 0;
269e05e4 2561 create_pit_unlock:
108b5669 2562 up_write(&kvm->slots_lock);
7837699f 2563 break;
4925663a 2564 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2565 case KVM_IRQ_LINE: {
2566 struct kvm_irq_level irq_event;
2567
2568 r = -EFAULT;
2569 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2570 goto out;
2571 if (irqchip_in_kernel(kvm)) {
4925663a 2572 __s32 status;
4925663a
GN		 2573 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2574 irq_event.irq, irq_event.level);
4925663a
GN		 2575 if (ioctl == KVM_IRQ_LINE_STATUS) {
2576 irq_event.status = status;
2577 if (copy_to_user(argp, &irq_event,
2578 sizeof irq_event))
2579 goto out;
2580 }
1fe779f8
CO		 2581 r = 0;
2582 }
2583 break;
2584 }
2585 case KVM_GET_IRQCHIP: {
2586 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2587 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2588
f0d66275
DH		 2589 r = -ENOMEM;
2590 if (!chip)
1fe779f8 2591 goto out;
f0d66275
DH		 2592 r = -EFAULT;
2593 if (copy_from_user(chip, argp, sizeof *chip))
2594 goto get_irqchip_out;
1fe779f8
CO		 2595 r = -ENXIO;
2596 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2597 goto get_irqchip_out;
2598 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2599 if (r)
f0d66275 2600 goto get_irqchip_out;
1fe779f8 2601 r = -EFAULT;
f0d66275
DH		 2602 if (copy_to_user(argp, chip, sizeof *chip))
2603 goto get_irqchip_out;
1fe779f8 2604 r = 0;
f0d66275
DH		 2605 get_irqchip_out:
2606 kfree(chip);
2607 if (r)
2608 goto out;
1fe779f8
CO		 2609 break;
2610 }
2611 case KVM_SET_IRQCHIP: {
2612 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2613 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2614
f0d66275
DH		 2615 r = -ENOMEM;
2616 if (!chip)
1fe779f8 2617 goto out;
f0d66275
DH		 2618 r = -EFAULT;
2619 if (copy_from_user(chip, argp, sizeof *chip))
2620 goto set_irqchip_out;
1fe779f8
CO		 2621 r = -ENXIO;
2622 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2623 goto set_irqchip_out;
2624 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2625 if (r)
f0d66275 2626 goto set_irqchip_out;
1fe779f8 2627 r = 0;
f0d66275
DH		 2628 set_irqchip_out:
2629 kfree(chip);
2630 if (r)
2631 goto out;
1fe779f8
CO		 2632 break;
2633 }
e0f63cb9 2634 case KVM_GET_PIT: {
e0f63cb9 2635 r = -EFAULT;
f0d66275 2636 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2637 goto out;
2638 r = -ENXIO;
2639 if (!kvm->arch.vpit)
2640 goto out;
f0d66275 2641 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2642 if (r)
2643 goto out;
2644 r = -EFAULT;
f0d66275 2645 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2646 goto out;
2647 r = 0;
2648 break;
2649 }
2650 case KVM_SET_PIT: {
e0f63cb9 2651 r = -EFAULT;
f0d66275 2652 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2653 goto out;
2654 r = -ENXIO;
2655 if (!kvm->arch.vpit)
2656 goto out;
f0d66275 2657 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2658 if (r)
2659 goto out;
2660 r = 0;
2661 break;
2662 }
e9f42757
BK		 2663 case KVM_GET_PIT2: {
2664 r = -ENXIO;
2665 if (!kvm->arch.vpit)
2666 goto out;
2667 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2668 if (r)
2669 goto out;
2670 r = -EFAULT;
2671 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2672 goto out;
2673 r = 0;
2674 break;
2675 }
2676 case KVM_SET_PIT2: {
2677 r = -EFAULT;
2678 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2679 goto out;
2680 r = -ENXIO;
2681 if (!kvm->arch.vpit)
2682 goto out;
2683 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2684 if (r)
2685 goto out;
2686 r = 0;
2687 break;
2688 }
52d939a0
MT		 2689 case KVM_REINJECT_CONTROL: {
2690 struct kvm_reinject_control control;
2691 r = -EFAULT;
2692 if (copy_from_user(&control, argp, sizeof(control)))
2693 goto out;
2694 r = kvm_vm_ioctl_reinject(kvm, &control);
2695 if (r)
2696 goto out;
2697 r = 0;
2698 break;
2699 }
ffde22ac
ES		 2700 case KVM_XEN_HVM_CONFIG: {
2701 r = -EFAULT;
2702 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
2703 sizeof(struct kvm_xen_hvm_config)))
2704 goto out;
2705 r = -EINVAL;
2706 if (kvm->arch.xen_hvm_config.flags)
2707 goto out;
2708 r = 0;
2709 break;
2710 }
afbcf7ab
GC		 2711 case KVM_SET_CLOCK: {
2712 struct timespec now;
2713 struct kvm_clock_data user_ns;
2714 u64 now_ns;
2715 s64 delta;
2716
2717 r = -EFAULT;
2718 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
2719 goto out;
2720
2721 r = -EINVAL;
2722 if (user_ns.flags)
2723 goto out;
2724
2725 r = 0;
2726 ktime_get_ts(&now);
2727 now_ns = timespec_to_ns(&now);
2728 delta = user_ns.clock - now_ns;
2729 kvm->arch.kvmclock_offset = delta;
2730 break;
2731 }
2732 case KVM_GET_CLOCK: {
2733 struct timespec now;
2734 struct kvm_clock_data user_ns;
2735 u64 now_ns;
2736
2737 ktime_get_ts(&now);
2738 now_ns = timespec_to_ns(&now);
2739 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
2740 user_ns.flags = 0;
2741
2742 r = -EFAULT;
2743 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
2744 goto out;
2745 r = 0;
2746 break;
2747 }
2748
1fe779f8
CO		 2749 default:
2750 ;
2751 }
2752out:
2753 return r;
2754}
2755
a16b043c 2756static void kvm_init_msr_list(void)
043405e1
CO		 2757{
2758 u32 dummy[2];
2759 unsigned i, j;
2760
e3267cbb
GC		 2761 /* skip the first msrs in the list. KVM-specific */
2762 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 2763 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2764 continue;
2765 if (j < i)
2766 msrs_to_save[j] = msrs_to_save[i];
2767 j++;
2768 }
2769 num_msrs_to_save = j;
2770}
2771
bda9020e
MT		 2772static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2773 const void *v)
bbd9b64e 2774{
bda9020e
MT		 2775 if (vcpu->arch.apic &&
2776 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
2777 return 0;
bbd9b64e 2778
bda9020e 2779 return kvm_io_bus_write(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2780}
2781
bda9020e 2782static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 2783{
bda9020e
MT		 2784 if (vcpu->arch.apic &&
2785 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
2786 return 0;
bbd9b64e 2787
bda9020e 2788 return kvm_io_bus_read(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2789}
2790
cded19f3
HE		 2791static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2792 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2793{
2794 void *data = val;
10589a46 2795 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2796
2797 while (bytes) {
ad312c7c 2798 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2799 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2800 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2801 int ret;
2802
10589a46
MT		 2803 if (gpa == UNMAPPED_GVA) {
2804 r = X86EMUL_PROPAGATE_FAULT;
2805 goto out;
2806 }
77c2002e 2807 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2808 if (ret < 0) {
2809 r = X86EMUL_UNHANDLEABLE;
2810 goto out;
2811 }
bbd9b64e 2812
77c2002e
IE		 2813 bytes -= toread;
2814 data += toread;
2815 addr += toread;
bbd9b64e 2816 }
10589a46 2817out:
10589a46 2818 return r;
bbd9b64e 2819}
77c2002e 2820
cded19f3
HE		 2821static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2822 struct kvm_vcpu *vcpu)
77c2002e
IE		 2823{
2824 void *data = val;
2825 int r = X86EMUL_CONTINUE;
2826
2827 while (bytes) {
2828 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2829 unsigned offset = addr & (PAGE_SIZE-1);
2830 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2831 int ret;
2832
2833 if (gpa == UNMAPPED_GVA) {
2834 r = X86EMUL_PROPAGATE_FAULT;
2835 goto out;
2836 }
2837 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2838 if (ret < 0) {
2839 r = X86EMUL_UNHANDLEABLE;
2840 goto out;
2841 }
2842
2843 bytes -= towrite;
2844 data += towrite;
2845 addr += towrite;
2846 }
2847out:
2848 return r;
2849}
2850
bbd9b64e 2851
bbd9b64e
CO		 2852static int emulator_read_emulated(unsigned long addr,
2853 void *val,
2854 unsigned int bytes,
2855 struct kvm_vcpu *vcpu)
2856{
bbd9b64e
CO		 2857 gpa_t gpa;
2858
2859 if (vcpu->mmio_read_completed) {
2860 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 2861 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
2862 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 2863 vcpu->mmio_read_completed = 0;
2864 return X86EMUL_CONTINUE;
2865 }
2866
ad312c7c 2867 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2868
2869 /* For APIC access vmexit */
2870 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2871 goto mmio;
2872
77c2002e
IE		 2873 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2874 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2875 return X86EMUL_CONTINUE;
2876 if (gpa == UNMAPPED_GVA)
2877 return X86EMUL_PROPAGATE_FAULT;
2878
2879mmio:
2880 /*
2881 * Is this MMIO handled locally?
2882 */
aec51dc4
AK		 2883 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
2884 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 2885 return X86EMUL_CONTINUE;
2886 }
aec51dc4
AK		 2887
2888 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 2889
2890 vcpu->mmio_needed = 1;
2891 vcpu->mmio_phys_addr = gpa;
2892 vcpu->mmio_size = bytes;
2893 vcpu->mmio_is_write = 0;
2894
2895 return X86EMUL_UNHANDLEABLE;
2896}
2897
3200f405 2898int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2899 const void *val, int bytes)
bbd9b64e
CO		 2900{
2901 int ret;
2902
2903 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2904 if (ret < 0)
bbd9b64e 2905 return 0;
ad218f85 2906 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2907 return 1;
2908}
2909
2910static int emulator_write_emulated_onepage(unsigned long addr,
2911 const void *val,
2912 unsigned int bytes,
2913 struct kvm_vcpu *vcpu)
2914{
10589a46
MT		 2915 gpa_t gpa;
2916
10589a46 2917 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2918
2919 if (gpa == UNMAPPED_GVA) {
c3c91fee 2920 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2921 return X86EMUL_PROPAGATE_FAULT;
2922 }
2923
2924 /* For APIC access vmexit */
2925 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2926 goto mmio;
2927
2928 if (emulator_write_phys(vcpu, gpa, val, bytes))
2929 return X86EMUL_CONTINUE;
2930
2931mmio:
aec51dc4 2932 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 2933 /*
2934 * Is this MMIO handled locally?
2935 */
bda9020e 2936 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 2937 return X86EMUL_CONTINUE;
bbd9b64e
CO		 2938
2939 vcpu->mmio_needed = 1;
2940 vcpu->mmio_phys_addr = gpa;
2941 vcpu->mmio_size = bytes;
2942 vcpu->mmio_is_write = 1;
2943 memcpy(vcpu->mmio_data, val, bytes);
2944
2945 return X86EMUL_CONTINUE;
2946}
2947
2948int emulator_write_emulated(unsigned long addr,
2949 const void *val,
2950 unsigned int bytes,
2951 struct kvm_vcpu *vcpu)
2952{
2953 /* Crossing a page boundary? */
2954 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2955 int rc, now;
2956
2957 now = -addr & ~PAGE_MASK;
2958 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2959 if (rc != X86EMUL_CONTINUE)
2960 return rc;
2961 addr += now;
2962 val += now;
2963 bytes -= now;
2964 }
2965 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2966}
2967EXPORT_SYMBOL_GPL(emulator_write_emulated);
2968
2969static int emulator_cmpxchg_emulated(unsigned long addr,
2970 const void *old,
2971 const void *new,
2972 unsigned int bytes,
2973 struct kvm_vcpu *vcpu)
2974{
9f51e24e 2975 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c
MT		 2976#ifndef CONFIG_X86_64
2977 /* guests cmpxchg8b have to be emulated atomically */
2978 if (bytes == 8) {
10589a46 2979 gpa_t gpa;
2bacc55c 2980 struct page *page;
c0b49b0d 2981 char *kaddr;
2bacc55c
MT		 2982 u64 val;
2983
10589a46
MT		 2984 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2985
2bacc55c
MT		 2986 if (gpa == UNMAPPED_GVA ||
2987 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2988 goto emul_write;
2989
2990 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2991 goto emul_write;
2992
2993 val = *(u64 *)new;
72dc67a6 2994
2bacc55c 2995 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2996
c0b49b0d
AM		 2997 kaddr = kmap_atomic(page, KM_USER0);
2998 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2999 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 3000 kvm_release_page_dirty(page);
3001 }
3200f405 3002emul_write:
2bacc55c
MT		 3003#endif
3004
bbd9b64e
CO		 3005 return emulator_write_emulated(addr, new, bytes, vcpu);
3006}
3007
3008static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3009{
3010 return kvm_x86_ops->get_segment_base(vcpu, seg);
3011}
3012
3013int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3014{
a7052897 3015 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3016 return X86EMUL_CONTINUE;
3017}
3018
3019int emulate_clts(struct kvm_vcpu *vcpu)
3020{
ad312c7c 3021 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 3022 return X86EMUL_CONTINUE;
3023}
3024
3025int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
3026{
3027 struct kvm_vcpu *vcpu = ctxt->vcpu;
3028
3029 switch (dr) {
3030 case 0 ... 3:
3031 *dest = kvm_x86_ops->get_dr(vcpu, dr);
3032 return X86EMUL_CONTINUE;
3033 default:
b8688d51 3034 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 3035 return X86EMUL_UNHANDLEABLE;
3036 }
3037}
3038
3039int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
3040{
3041 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
3042 int exception;
3043
3044 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
3045 if (exception) {
3046 /* FIXME: better handling */
3047 return X86EMUL_UNHANDLEABLE;
3048 }
3049 return X86EMUL_CONTINUE;
3050}
3051
3052void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
3053{
bbd9b64e 3054 u8 opcodes[4];
5fdbf976 3055 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 3056 unsigned long rip_linear;
3057
f76c710d 3058 if (!printk_ratelimit())
bbd9b64e
CO		 3059 return;
3060
25be4608
GC		 3061 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
3062
77c2002e 3063 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 3064
3065 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
3066 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 3067}
3068EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
3069
14af3f3c 3070static struct x86_emulate_ops emulate_ops = {
77c2002e 3071 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 3072 .read_emulated = emulator_read_emulated,
3073 .write_emulated = emulator_write_emulated,
3074 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3075};
3076
5fdbf976
MT		 3077static void cache_all_regs(struct kvm_vcpu *vcpu)
3078{
3079 kvm_register_read(vcpu, VCPU_REGS_RAX);
3080 kvm_register_read(vcpu, VCPU_REGS_RSP);
3081 kvm_register_read(vcpu, VCPU_REGS_RIP);
3082 vcpu->arch.regs_dirty = ~0;
3083}
3084
bbd9b64e 3085int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3086 unsigned long cr2,
3087 u16 error_code,
571008da 3088 int emulation_type)
bbd9b64e 3089{
310b5d30 3090 int r, shadow_mask;
571008da 3091 struct decode_cache *c;
851ba692 3092 struct kvm_run *run = vcpu->run;
bbd9b64e 3093
26eef70c 3094 kvm_clear_exception_queue(vcpu);
ad312c7c 3095 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3096 /*
56e82318 3097 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3098 * instead of direct ->regs accesses, can save hundred cycles
3099 * on Intel for instructions that don't read/change RSP, for
3100 * for example.
3101 */
3102 cache_all_regs(vcpu);
bbd9b64e
CO		 3103
3104 vcpu->mmio_is_write = 0;
ad312c7c 3105 vcpu->arch.pio.string = 0;
bbd9b64e 3106
571008da 3107 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3108 int cs_db, cs_l;
3109 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3110
ad312c7c 3111 vcpu->arch.emulate_ctxt.vcpu = vcpu;
91586a3b 3112 vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu);
ad312c7c
ZX		 3113 vcpu->arch.emulate_ctxt.mode =
3114 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 3115 ? X86EMUL_MODE_REAL : cs_l
3116 ? X86EMUL_MODE_PROT64 : cs_db
3117 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3118
ad312c7c 3119 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 3120
0cb5762e
AP		 3121 /* Only allow emulation of specific instructions on #UD
3122 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 3123 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 3124 if (emulation_type & EMULTYPE_TRAP_UD) {
3125 if (!c->twobyte)
3126 return EMULATE_FAIL;
3127 switch (c->b) {
3128 case 0x01: /* VMMCALL */
3129 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3130 return EMULATE_FAIL;
3131 break;
3132 case 0x34: /* sysenter */
3133 case 0x35: /* sysexit */
3134 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3135 return EMULATE_FAIL;
3136 break;
3137 case 0x05: /* syscall */
3138 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3139 return EMULATE_FAIL;
3140 break;
3141 default:
3142 return EMULATE_FAIL;
3143 }
3144
3145 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3146 return EMULATE_FAIL;
3147 }
571008da 3148
f2b5756b 3149 ++vcpu->stat.insn_emulation;
bbd9b64e 3150 if (r) {
f2b5756b 3151 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 3152 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3153 return EMULATE_DONE;
3154 return EMULATE_FAIL;
3155 }
3156 }
3157
ba8afb6b
GN		 3158 if (emulation_type & EMULTYPE_SKIP) {
3159 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3160 return EMULATE_DONE;
3161 }
3162
ad312c7c 3163 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 3164 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3165
3166 if (r == 0)
3167 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 3168
ad312c7c 3169 if (vcpu->arch.pio.string)
bbd9b64e
CO		 3170 return EMULATE_DO_MMIO;
3171
3172 if ((r || vcpu->mmio_is_write) && run) {
3173 run->exit_reason = KVM_EXIT_MMIO;
3174 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3175 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3176 run->mmio.len = vcpu->mmio_size;
3177 run->mmio.is_write = vcpu->mmio_is_write;
3178 }
3179
3180 if (r) {
3181 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3182 return EMULATE_DONE;
3183 if (!vcpu->mmio_needed) {
3184 kvm_report_emulation_failure(vcpu, "mmio");
3185 return EMULATE_FAIL;
3186 }
3187 return EMULATE_DO_MMIO;
3188 }
3189
91586a3b 3190 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 3191
3192 if (vcpu->mmio_is_write) {
3193 vcpu->mmio_needed = 0;
3194 return EMULATE_DO_MMIO;
3195 }
3196
3197 return EMULATE_DONE;
3198}
3199EXPORT_SYMBOL_GPL(emulate_instruction);
3200
de7d789a
CO		 3201static int pio_copy_data(struct kvm_vcpu *vcpu)
3202{
ad312c7c 3203 void *p = vcpu->arch.pio_data;
0f346074 3204 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 3205 unsigned bytes;
0f346074 3206 int ret;
de7d789a 3207
ad312c7c
ZX		 3208 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
3209 if (vcpu->arch.pio.in)
0f346074 3210 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 3211 else
0f346074
IE		 3212 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
3213 return ret;
de7d789a
CO		 3214}
3215
3216int complete_pio(struct kvm_vcpu *vcpu)
3217{
ad312c7c 3218 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 3219 long delta;
3220 int r;
5fdbf976 3221 unsigned long val;
de7d789a
CO		 3222
3223 if (!io->string) {
5fdbf976
MT		 3224 if (io->in) {
3225 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3226 memcpy(&val, vcpu->arch.pio_data, io->size);
3227 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
3228 }
de7d789a
CO		 3229 } else {
3230 if (io->in) {
3231 r = pio_copy_data(vcpu);
5fdbf976 3232 if (r)
de7d789a 3233 return r;
de7d789a
CO		 3234 }
3235
3236 delta = 1;
3237 if (io->rep) {
3238 delta *= io->cur_count;
3239 /*
3240 * The size of the register should really depend on
3241 * current address size.
3242 */
5fdbf976
MT		 3243 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
3244 val -= delta;
3245 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 3246 }
3247 if (io->down)
3248 delta = -delta;
3249 delta *= io->size;
5fdbf976
MT		 3250 if (io->in) {
3251 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
3252 val += delta;
3253 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
3254 } else {
3255 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
3256 val += delta;
3257 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
3258 }
de7d789a
CO		 3259 }
3260
de7d789a
CO		 3261 io->count -= io->cur_count;
3262 io->cur_count = 0;
3263
3264 return 0;
3265}
3266
bda9020e 3267static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 3268{
3269 /* TODO: String I/O for in kernel device */
bda9020e 3270 int r;
de7d789a 3271
ad312c7c 3272 if (vcpu->arch.pio.in)
bda9020e
MT		 3273 r = kvm_io_bus_read(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
3274 vcpu->arch.pio.size, pd);
de7d789a 3275 else
bda9020e
MT		 3276 r = kvm_io_bus_write(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
3277 vcpu->arch.pio.size, pd);
3278 return r;
de7d789a
CO		 3279}
3280
bda9020e 3281static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 3282{
ad312c7c
ZX		 3283 struct kvm_pio_request *io = &vcpu->arch.pio;
3284 void *pd = vcpu->arch.pio_data;
bda9020e 3285 int i, r = 0;
de7d789a 3286
de7d789a 3287 for (i = 0; i < io->cur_count; i++) {
bda9020e
MT		 3288 if (kvm_io_bus_write(&vcpu->kvm->pio_bus,
3289 io->port, io->size, pd)) {
3290 r = -EOPNOTSUPP;
3291 break;
3292 }
de7d789a
CO		 3293 pd += io->size;
3294 }
bda9020e 3295 return r;
de7d789a
CO		 3296}
3297
851ba692 3298int kvm_emulate_pio(struct kvm_vcpu *vcpu, int in, int size, unsigned port)
de7d789a 3299{
5fdbf976 3300 unsigned long val;
de7d789a
CO		 3301
3302 vcpu->run->exit_reason = KVM_EXIT_IO;
3303 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3304 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3305 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3306 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
3307 vcpu->run->io.port = vcpu->arch.pio.port = port;
3308 vcpu->arch.pio.in = in;
3309 vcpu->arch.pio.string = 0;
3310 vcpu->arch.pio.down = 0;
ad312c7c 3311 vcpu->arch.pio.rep = 0;
de7d789a 3312
229456fc
MT		 3313 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3314 size, 1);
2714d1d3 3315
5fdbf976
MT		 3316 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3317 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 3318
bda9020e 3319 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 3320 complete_pio(vcpu);
3321 return 1;
3322 }
3323 return 0;
3324}
3325EXPORT_SYMBOL_GPL(kvm_emulate_pio);
3326
851ba692 3327int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, int in,
de7d789a
CO		 3328 int size, unsigned long count, int down,
3329 gva_t address, int rep, unsigned port)
3330{
3331 unsigned now, in_page;
0f346074 3332 int ret = 0;
de7d789a
CO		 3333
3334 vcpu->run->exit_reason = KVM_EXIT_IO;
3335 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3336 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3337 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3338 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
3339 vcpu->run->io.port = vcpu->arch.pio.port = port;
3340 vcpu->arch.pio.in = in;
3341 vcpu->arch.pio.string = 1;
3342 vcpu->arch.pio.down = down;
ad312c7c 3343 vcpu->arch.pio.rep = rep;
de7d789a 3344
229456fc
MT		 3345 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3346 size, count);
2714d1d3 3347
de7d789a
CO		 3348 if (!count) {
3349 kvm_x86_ops->skip_emulated_instruction(vcpu);
3350 return 1;
3351 }
3352
3353 if (!down)
3354 in_page = PAGE_SIZE - offset_in_page(address);
3355 else
3356 in_page = offset_in_page(address) + size;
3357 now = min(count, (unsigned long)in_page / size);
0f346074 3358 if (!now)
de7d789a 3359 now = 1;
de7d789a
CO		 3360 if (down) {
3361 /*
3362 * String I/O in reverse. Yuck. Kill the guest, fix later.
3363 */
3364 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 3365 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 3366 return 1;
3367 }
3368 vcpu->run->io.count = now;
ad312c7c 3369 vcpu->arch.pio.cur_count = now;
de7d789a 3370
ad312c7c 3371 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 3372 kvm_x86_ops->skip_emulated_instruction(vcpu);
3373
0f346074 3374 vcpu->arch.pio.guest_gva = address;
de7d789a 3375
ad312c7c 3376 if (!vcpu->arch.pio.in) {
de7d789a
CO		 3377 /* string PIO write */
3378 ret = pio_copy_data(vcpu);
0f346074
IE		 3379 if (ret == X86EMUL_PROPAGATE_FAULT) {
3380 kvm_inject_gp(vcpu, 0);
3381 return 1;
3382 }
bda9020e 3383 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 3384 complete_pio(vcpu);
ad312c7c 3385 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 3386 ret = 1;
3387 }
bda9020e
MT		 3388 }
3389 /* no string PIO read support yet */
de7d789a
CO		 3390
3391 return ret;
3392}
3393EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3394
c8076604
GH		 3395static void bounce_off(void *info)
3396{
3397 /* nothing */
3398}
3399
c8076604
GH		 3400static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3401 void *data)
3402{
3403 struct cpufreq_freqs *freq = data;
3404 struct kvm *kvm;
3405 struct kvm_vcpu *vcpu;
3406 int i, send_ipi = 0;
3407
c8076604
GH		 3408 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3409 return 0;
3410 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3411 return 0;
0cca7907 3412 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3413
3414 spin_lock(&kvm_lock);
3415 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3416 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3417 if (vcpu->cpu != freq->cpu)
3418 continue;
3419 if (!kvm_request_guest_time_update(vcpu))
3420 continue;
3421 if (vcpu->cpu != smp_processor_id())
3422 send_ipi++;
3423 }
3424 }
3425 spin_unlock(&kvm_lock);
3426
3427 if (freq->old < freq->new && send_ipi) {
3428 /*
3429 * We upscale the frequency. Must make the guest
3430 * doesn't see old kvmclock values while running with
3431 * the new frequency, otherwise we risk the guest sees
3432 * time go backwards.
3433 *
3434 * In case we update the frequency for another cpu
3435 * (which might be in guest context) send an interrupt
3436 * to kick the cpu out of guest context. Next time
3437 * guest context is entered kvmclock will be updated,
3438 * so the guest will not see stale values.
3439 */
3440 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3441 }
3442 return 0;
3443}
3444
3445static struct notifier_block kvmclock_cpufreq_notifier_block = {
3446 .notifier_call = kvmclock_cpufreq_notifier
3447};
3448
b820cc0c
ZA		 3449static void kvm_timer_init(void)
3450{
3451 int cpu;
3452
b820cc0c 3453 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 3454 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3455 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 3456 for_each_online_cpu(cpu) {
3457 unsigned long khz = cpufreq_get(cpu);
3458 if (!khz)
3459 khz = tsc_khz;
3460 per_cpu(cpu_tsc_khz, cpu) = khz;
3461 }
0cca7907
ZA		 3462 } else {
3463 for_each_possible_cpu(cpu)
3464 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 3465 }
3466}
3467
f8c16bba 3468int kvm_arch_init(void *opaque)
043405e1 3469{
b820cc0c 3470 int r;
f8c16bba
ZX		 3471 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3472
f8c16bba
ZX		 3473 if (kvm_x86_ops) {
3474 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3475 r = -EEXIST;
3476 goto out;
f8c16bba
ZX		 3477 }
3478
3479 if (!ops->cpu_has_kvm_support()) {
3480 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3481 r = -EOPNOTSUPP;
3482 goto out;
f8c16bba
ZX		 3483 }
3484 if (ops->disabled_by_bios()) {
3485 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3486 r = -EOPNOTSUPP;
3487 goto out;
f8c16bba
ZX		 3488 }
3489
97db56ce
AK		 3490 r = kvm_mmu_module_init();
3491 if (r)
3492 goto out;
3493
3494 kvm_init_msr_list();
3495
f8c16bba 3496 kvm_x86_ops = ops;
56c6d28a 3497 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3498 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3499 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3500 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 3501
b820cc0c 3502 kvm_timer_init();
c8076604 3503
f8c16bba 3504 return 0;
56c6d28a
ZX		 3505
3506out:
56c6d28a 3507 return r;
043405e1 3508}
8776e519 3509
f8c16bba
ZX		 3510void kvm_arch_exit(void)
3511{
888d256e
JK		 3512 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3513 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3514 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3515 kvm_x86_ops = NULL;
56c6d28a
ZX		 3516 kvm_mmu_module_exit();
3517}
f8c16bba 3518
8776e519
HB		 3519int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3520{
3521 ++vcpu->stat.halt_exits;
3522 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3523 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3524 return 1;
3525 } else {
3526 vcpu->run->exit_reason = KVM_EXIT_HLT;
3527 return 0;
3528 }
3529}
3530EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3531
2f333bcb
MT		 3532static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3533 unsigned long a1)
3534{
3535 if (is_long_mode(vcpu))
3536 return a0;
3537 else
3538 return a0 | ((gpa_t)a1 << 32);
3539}
3540
8776e519
HB		 3541int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3542{
3543 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3544 int r = 1;
8776e519 3545
5fdbf976
MT		 3546 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3547 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3548 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3549 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3550 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3551
229456fc 3552 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3553
8776e519
HB		 3554 if (!is_long_mode(vcpu)) {
3555 nr &= 0xFFFFFFFF;
3556 a0 &= 0xFFFFFFFF;
3557 a1 &= 0xFFFFFFFF;
3558 a2 &= 0xFFFFFFFF;
3559 a3 &= 0xFFFFFFFF;
3560 }
3561
07708c4a
JK		 3562 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
3563 ret = -KVM_EPERM;
3564 goto out;
3565 }
3566
8776e519 3567 switch (nr) {
b93463aa
AK		 3568 case KVM_HC_VAPIC_POLL_IRQ:
3569 ret = 0;
3570 break;
2f333bcb
MT		 3571 case KVM_HC_MMU_OP:
3572 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3573 break;
8776e519
HB		 3574 default:
3575 ret = -KVM_ENOSYS;
3576 break;
3577 }
07708c4a 3578out:
5fdbf976 3579 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3580 ++vcpu->stat.hypercalls;
2f333bcb 3581 return r;
8776e519
HB		 3582}
3583EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3584
3585int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3586{
3587 char instruction[3];
3588 int ret = 0;
5fdbf976 3589 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3590
8776e519
HB		 3591
3592 /*
3593 * Blow out the MMU to ensure that no other VCPU has an active mapping
3594 * to ensure that the updated hypercall appears atomically across all
3595 * VCPUs.
3596 */
3597 kvm_mmu_zap_all(vcpu->kvm);
3598
8776e519 3599 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 3600 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 3601 != X86EMUL_CONTINUE)
3602 ret = -EFAULT;
3603
8776e519
HB		 3604 return ret;
3605}
3606
3607static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3608{
3609 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3610}
3611
3612void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3613{
3614 struct descriptor_table dt = { limit, base };
3615
3616 kvm_x86_ops->set_gdt(vcpu, &dt);
3617}
3618
3619void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3620{
3621 struct descriptor_table dt = { limit, base };
3622
3623 kvm_x86_ops->set_idt(vcpu, &dt);
3624}
3625
3626void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3627 unsigned long *rflags)
3628{
2d3ad1f4 3629 kvm_lmsw(vcpu, msw);
91586a3b 3630 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 3631}
3632
3633unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3634{
54e445ca
JR		 3635 unsigned long value;
3636
8776e519
HB		 3637 switch (cr) {
3638 case 0:
54e445ca
JR		 3639 value = vcpu->arch.cr0;
3640 break;
8776e519 3641 case 2:
54e445ca
JR		 3642 value = vcpu->arch.cr2;
3643 break;
8776e519 3644 case 3:
54e445ca
JR		 3645 value = vcpu->arch.cr3;
3646 break;
8776e519 3647 case 4:
fc78f519 3648 value = kvm_read_cr4(vcpu);
54e445ca 3649 break;
152ff9be 3650 case 8:
54e445ca
JR		 3651 value = kvm_get_cr8(vcpu);
3652 break;
8776e519 3653 default:
b8688d51 3654 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3655 return 0;
3656 }
54e445ca
JR		 3657
3658 return value;
8776e519
HB		 3659}
3660
3661void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3662 unsigned long *rflags)
3663{
3664 switch (cr) {
3665 case 0:
2d3ad1f4 3666 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
91586a3b 3667 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 3668 break;
3669 case 2:
ad312c7c 3670 vcpu->arch.cr2 = val;
8776e519
HB		 3671 break;
3672 case 3:
2d3ad1f4 3673 kvm_set_cr3(vcpu, val);
8776e519
HB		 3674 break;
3675 case 4:
fc78f519 3676 kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
8776e519 3677 break;
152ff9be 3678 case 8:
2d3ad1f4 3679 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 3680 break;
8776e519 3681 default:
b8688d51 3682 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3683 }
3684}
3685
07716717
DK		 3686static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3687{
ad312c7c
ZX		 3688 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3689 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 3690
3691 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3692 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 3693 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 3694 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 3695 if (ej->function == e->function) {
3696 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3697 return j;
3698 }
3699 }
3700 return 0; /* silence gcc, even though control never reaches here */
3701}
3702
3703/* find an entry with matching function, matching index (if needed), and that
3704 * should be read next (if it's stateful) */
3705static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3706 u32 function, u32 index)
3707{
3708 if (e->function != function)
3709 return 0;
3710 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3711 return 0;
3712 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 3713 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 3714 return 0;
3715 return 1;
3716}
3717
d8017474
AG		 3718struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3719 u32 function, u32 index)
8776e519
HB		 3720{
3721 int i;
d8017474 3722 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3723
ad312c7c 3724 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3725 struct kvm_cpuid_entry2 *e;
3726
ad312c7c 3727 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3728 if (is_matching_cpuid_entry(e, function, index)) {
3729 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3730 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3731 best = e;
3732 break;
3733 }
3734 /*
3735 * Both basic or both extended?
3736 */
3737 if (((e->function ^ function) & 0x80000000) == 0)
3738 if (!best || e->function > best->function)
3739 best = e;
3740 }
d8017474
AG		 3741 return best;
3742}
0e851880 3743EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 3744
82725b20
DE		 3745int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3746{
3747 struct kvm_cpuid_entry2 *best;
3748
3749 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3750 if (best)
3751 return best->eax & 0xff;
3752 return 36;
3753}
3754
d8017474
AG		 3755void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3756{
3757 u32 function, index;
3758 struct kvm_cpuid_entry2 *best;
3759
3760 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3761 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3762 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3763 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3764 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3765 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3766 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3767 if (best) {
5fdbf976
MT		 3768 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3769 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3770 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3771 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3772 }
8776e519 3773 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 3774 trace_kvm_cpuid(function,
3775 kvm_register_read(vcpu, VCPU_REGS_RAX),
3776 kvm_register_read(vcpu, VCPU_REGS_RBX),
3777 kvm_register_read(vcpu, VCPU_REGS_RCX),
3778 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 3779}
3780EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3781
b6c7a5dc
HB		 3782/*
3783 * Check if userspace requested an interrupt window, and that the
3784 * interrupt window is open.
3785 *
3786 * No need to exit to userspace if we already have an interrupt queued.
3787 */
851ba692 3788static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 3789{
8061823a 3790 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 3791 vcpu->run->request_interrupt_window &&
5df56646 3792 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 3793}
3794
851ba692 3795static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 3796{
851ba692
AK		 3797 struct kvm_run *kvm_run = vcpu->run;
3798
91586a3b 3799 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3800 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3801 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3802 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3803 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3804 else
b6c7a5dc 3805 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 3806 kvm_arch_interrupt_allowed(vcpu) &&
3807 !kvm_cpu_has_interrupt(vcpu) &&
3808 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 3809}
3810
b93463aa
AK		 3811static void vapic_enter(struct kvm_vcpu *vcpu)
3812{
3813 struct kvm_lapic *apic = vcpu->arch.apic;
3814 struct page *page;
3815
3816 if (!apic || !apic->vapic_addr)
3817 return;
3818
3819 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3820
3821 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3822}
3823
3824static void vapic_exit(struct kvm_vcpu *vcpu)
3825{
3826 struct kvm_lapic *apic = vcpu->arch.apic;
3827
3828 if (!apic || !apic->vapic_addr)
3829 return;
3830
f8b78fa3 3831 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3832 kvm_release_page_dirty(apic->vapic_page);
3833 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3834 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3835}
3836
95ba8273
GN		 3837static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3838{
3839 int max_irr, tpr;
3840
3841 if (!kvm_x86_ops->update_cr8_intercept)
3842 return;
3843
88c808fd
AK		 3844 if (!vcpu->arch.apic)
3845 return;
3846
8db3baa2
GN		 3847 if (!vcpu->arch.apic->vapic_addr)
3848 max_irr = kvm_lapic_find_highest_irr(vcpu);
3849 else
3850 max_irr = -1;
95ba8273
GN		 3851
3852 if (max_irr != -1)
3853 max_irr >>= 4;
3854
3855 tpr = kvm_lapic_get_cr8(vcpu);
3856
3857 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3858}
3859
851ba692 3860static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 3861{
3862 /* try to reinject previous events if any */
b59bb7bd
GN		 3863 if (vcpu->arch.exception.pending) {
3864 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
3865 vcpu->arch.exception.has_error_code,
3866 vcpu->arch.exception.error_code);
3867 return;
3868 }
3869
95ba8273
GN		 3870 if (vcpu->arch.nmi_injected) {
3871 kvm_x86_ops->set_nmi(vcpu);
3872 return;
3873 }
3874
3875 if (vcpu->arch.interrupt.pending) {
66fd3f7f 3876 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3877 return;
3878 }
3879
3880 /* try to inject new event if pending */
3881 if (vcpu->arch.nmi_pending) {
3882 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3883 vcpu->arch.nmi_pending = false;
3884 vcpu->arch.nmi_injected = true;
3885 kvm_x86_ops->set_nmi(vcpu);
3886 }
3887 } else if (kvm_cpu_has_interrupt(vcpu)) {
3888 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 3889 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3890 false);
3891 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3892 }
3893 }
3894}
3895
851ba692 3896static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 3897{
3898 int r;
6a8b1d13 3899 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 3900 vcpu->run->request_interrupt_window;
b6c7a5dc 3901
2e53d63a
MT		 3902 if (vcpu->requests)
3903 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3904 kvm_mmu_unload(vcpu);
3905
b6c7a5dc
HB		 3906 r = kvm_mmu_reload(vcpu);
3907 if (unlikely(r))
3908 goto out;
3909
2f52d58c
AK		 3910 if (vcpu->requests) {
3911 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3912 __kvm_migrate_timers(vcpu);
c8076604
GH		 3913 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3914 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3915 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3916 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3917 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3918 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3919 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3920 &vcpu->requests)) {
851ba692 3921 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 3922 r = 0;
3923 goto out;
3924 }
71c4dfaf 3925 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 3926 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 3927 r = 0;
3928 goto out;
3929 }
2f52d58c 3930 }
b93463aa 3931
b6c7a5dc
HB		 3932 preempt_disable();
3933
3934 kvm_x86_ops->prepare_guest_switch(vcpu);
3935 kvm_load_guest_fpu(vcpu);
3936
3937 local_irq_disable();
3938
32f88400
MT		 3939 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3940 smp_mb__after_clear_bit();
3941
d7690175 3942 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 3943 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 3944 local_irq_enable();
3945 preempt_enable();
3946 r = 1;
3947 goto out;
3948 }
3949
851ba692 3950 inject_pending_event(vcpu);
b6c7a5dc 3951
6a8b1d13
GN		 3952 /* enable NMI/IRQ window open exits if needed */
3953 if (vcpu->arch.nmi_pending)
3954 kvm_x86_ops->enable_nmi_window(vcpu);
3955 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3956 kvm_x86_ops->enable_irq_window(vcpu);
3957
95ba8273 3958 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 3959 update_cr8_intercept(vcpu);
3960 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 3961 }
b93463aa 3962
3200f405
MT		 3963 up_read(&vcpu->kvm->slots_lock);
3964
b6c7a5dc
HB		 3965 kvm_guest_enter();
3966
42dbaa5a 3967 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 3968 set_debugreg(0, 7);
3969 set_debugreg(vcpu->arch.eff_db[0], 0);
3970 set_debugreg(vcpu->arch.eff_db[1], 1);
3971 set_debugreg(vcpu->arch.eff_db[2], 2);
3972 set_debugreg(vcpu->arch.eff_db[3], 3);
3973 }
b6c7a5dc 3974
229456fc 3975 trace_kvm_entry(vcpu->vcpu_id);
851ba692 3976 kvm_x86_ops->run(vcpu);
b6c7a5dc 3977
24f1e32c
FW		 3978 /*
3979 * If the guest has used debug registers, at least dr7
3980 * will be disabled while returning to the host.
3981 * If we don't have active breakpoints in the host, we don't
3982 * care about the messed up debug address registers. But if
3983 * we have some of them active, restore the old state.
3984 */
59d8eb53 3985 if (hw_breakpoint_active())
24f1e32c 3986 hw_breakpoint_restore();
42dbaa5a 3987
32f88400 3988 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 3989 local_irq_enable();
3990
3991 ++vcpu->stat.exits;
3992
3993 /*
3994 * We must have an instruction between local_irq_enable() and
3995 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3996 * the interrupt shadow. The stat.exits increment will do nicely.
3997 * But we need to prevent reordering, hence this barrier():
3998 */
3999 barrier();
4000
4001 kvm_guest_exit();
4002
4003 preempt_enable();
4004
3200f405
MT		 4005 down_read(&vcpu->kvm->slots_lock);
4006
b6c7a5dc
HB		 4007 /*
4008 * Profile KVM exit RIPs:
4009 */
4010 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4011 unsigned long rip = kvm_rip_read(vcpu);
4012 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4013 }
4014
298101da 4015
b93463aa
AK		 4016 kvm_lapic_sync_from_vapic(vcpu);
4017
851ba692 4018 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4019out:
4020 return r;
4021}
b6c7a5dc 4022
09cec754 4023
851ba692 4024static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4025{
4026 int r;
4027
4028 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4029 pr_debug("vcpu %d received sipi with vector # %x\n",
4030 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4031 kvm_lapic_reset(vcpu);
5f179287 4032 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4033 if (r)
4034 return r;
4035 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4036 }
4037
d7690175
MT		 4038 down_read(&vcpu->kvm->slots_lock);
4039 vapic_enter(vcpu);
4040
4041 r = 1;
4042 while (r > 0) {
af2152f5 4043 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4044 r = vcpu_enter_guest(vcpu);
d7690175
MT		 4045 else {
4046 up_read(&vcpu->kvm->slots_lock);
4047 kvm_vcpu_block(vcpu);
4048 down_read(&vcpu->kvm->slots_lock);
4049 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4050 {
4051 switch(vcpu->arch.mp_state) {
4052 case KVM_MP_STATE_HALTED:
d7690175 4053 vcpu->arch.mp_state =
09cec754
GN		 4054 KVM_MP_STATE_RUNNABLE;
4055 case KVM_MP_STATE_RUNNABLE:
4056 break;
4057 case KVM_MP_STATE_SIPI_RECEIVED:
4058 default:
4059 r = -EINTR;
4060 break;
4061 }
4062 }
d7690175
MT		 4063 }
4064
09cec754
GN		 4065 if (r <= 0)
4066 break;
4067
4068 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4069 if (kvm_cpu_has_pending_timer(vcpu))
4070 kvm_inject_pending_timer_irqs(vcpu);
4071
851ba692 4072 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4073 r = -EINTR;
851ba692 4074 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4075 ++vcpu->stat.request_irq_exits;
4076 }
4077 if (signal_pending(current)) {
4078 r = -EINTR;
851ba692 4079 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4080 ++vcpu->stat.signal_exits;
4081 }
4082 if (need_resched()) {
4083 up_read(&vcpu->kvm->slots_lock);
4084 kvm_resched(vcpu);
4085 down_read(&vcpu->kvm->slots_lock);
d7690175 4086 }
b6c7a5dc
HB		 4087 }
4088
d7690175 4089 up_read(&vcpu->kvm->slots_lock);
851ba692 4090 post_kvm_run_save(vcpu);
b6c7a5dc 4091
b93463aa
AK		 4092 vapic_exit(vcpu);
4093
b6c7a5dc
HB		 4094 return r;
4095}
4096
4097int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4098{
4099 int r;
4100 sigset_t sigsaved;
4101
4102 vcpu_load(vcpu);
4103
ac9f6dc0
AK		 4104 if (vcpu->sigset_active)
4105 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4106
a4535290 4107 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4108 kvm_vcpu_block(vcpu);
d7690175 4109 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4110 r = -EAGAIN;
4111 goto out;
b6c7a5dc
HB		 4112 }
4113
b6c7a5dc
HB		 4114 /* re-sync apic's tpr */
4115 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4116 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4117
ad312c7c 4118 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 4119 r = complete_pio(vcpu);
4120 if (r)
4121 goto out;
4122 }
b6c7a5dc
HB		 4123 if (vcpu->mmio_needed) {
4124 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4125 vcpu->mmio_read_completed = 1;
4126 vcpu->mmio_needed = 0;
3200f405
MT		 4127
4128 down_read(&vcpu->kvm->slots_lock);
851ba692 4129 r = emulate_instruction(vcpu, vcpu->arch.mmio_fault_cr2, 0,
571008da 4130 EMULTYPE_NO_DECODE);
3200f405 4131 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 4132 if (r == EMULATE_DO_MMIO) {
4133 /*
4134 * Read-modify-write. Back to userspace.
4135 */
4136 r = 0;
4137 goto out;
4138 }
4139 }
5fdbf976
MT		 4140 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4141 kvm_register_write(vcpu, VCPU_REGS_RAX,
4142 kvm_run->hypercall.ret);
b6c7a5dc 4143
851ba692 4144 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4145
4146out:
4147 if (vcpu->sigset_active)
4148 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4149
4150 vcpu_put(vcpu);
4151 return r;
4152}
4153
4154int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4155{
4156 vcpu_load(vcpu);
4157
5fdbf976
MT		 4158 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4159 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4160 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4161 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4162 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4163 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4164 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4165 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4166#ifdef CONFIG_X86_64
5fdbf976
MT		 4167 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4168 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4169 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4170 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4171 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4172 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4173 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4174 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4175#endif
4176
5fdbf976 4177 regs->rip = kvm_rip_read(vcpu);
91586a3b 4178 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4179
4180 vcpu_put(vcpu);
4181
4182 return 0;
4183}
4184
4185int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4186{
4187 vcpu_load(vcpu);
4188
5fdbf976
MT		 4189 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4190 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4191 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4192 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4193 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4194 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4195 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4196 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4197#ifdef CONFIG_X86_64
5fdbf976
MT		 4198 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4199 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4200 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4201 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4202 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4203 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4204 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4205 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4206#endif
4207
5fdbf976 4208 kvm_rip_write(vcpu, regs->rip);
91586a3b 4209 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4210
b4f14abd
JK		 4211 vcpu->arch.exception.pending = false;
4212
b6c7a5dc
HB		 4213 vcpu_put(vcpu);
4214
4215 return 0;
4216}
4217
3e6e0aab
GT		 4218void kvm_get_segment(struct kvm_vcpu *vcpu,
4219 struct kvm_segment *var, int seg)
b6c7a5dc 4220{
14af3f3c 4221 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 4222}
4223
4224void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4225{
4226 struct kvm_segment cs;
4227
3e6e0aab 4228 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4229 *db = cs.db;
4230 *l = cs.l;
4231}
4232EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4233
4234int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4235 struct kvm_sregs *sregs)
4236{
4237 struct descriptor_table dt;
b6c7a5dc
HB		 4238
4239 vcpu_load(vcpu);
4240
3e6e0aab
GT		 4241 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4242 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4243 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4244 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4245 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4246 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4247
3e6e0aab
GT		 4248 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4249 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4250
4251 kvm_x86_ops->get_idt(vcpu, &dt);
4252 sregs->idt.limit = dt.limit;
4253 sregs->idt.base = dt.base;
4254 kvm_x86_ops->get_gdt(vcpu, &dt);
4255 sregs->gdt.limit = dt.limit;
4256 sregs->gdt.base = dt.base;
4257
ad312c7c
ZX		 4258 sregs->cr0 = vcpu->arch.cr0;
4259 sregs->cr2 = vcpu->arch.cr2;
4260 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4261 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4262 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 4263 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 4264 sregs->apic_base = kvm_get_apic_base(vcpu);
4265
923c61bb 4266 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4267
36752c9b 4268 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4269 set_bit(vcpu->arch.interrupt.nr,
4270 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4271
b6c7a5dc
HB		 4272 vcpu_put(vcpu);
4273
4274 return 0;
4275}
4276
62d9f0db
MT		 4277int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4278 struct kvm_mp_state *mp_state)
4279{
4280 vcpu_load(vcpu);
4281 mp_state->mp_state = vcpu->arch.mp_state;
4282 vcpu_put(vcpu);
4283 return 0;
4284}
4285
4286int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4287 struct kvm_mp_state *mp_state)
4288{
4289 vcpu_load(vcpu);
4290 vcpu->arch.mp_state = mp_state->mp_state;
4291 vcpu_put(vcpu);
4292 return 0;
4293}
4294
3e6e0aab 4295static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 4296 struct kvm_segment *var, int seg)
4297{
14af3f3c 4298 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 4299}
4300
37817f29
IE		 4301static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
4302 struct kvm_segment *kvm_desct)
4303{
46a359e7
AM		 4304 kvm_desct->base = get_desc_base(seg_desc);
4305 kvm_desct->limit = get_desc_limit(seg_desc);
c93cd3a5
MT		 4306 if (seg_desc->g) {
4307 kvm_desct->limit <<= 12;
4308 kvm_desct->limit |= 0xfff;
4309 }
37817f29
IE		 4310 kvm_desct->selector = selector;
4311 kvm_desct->type = seg_desc->type;
4312 kvm_desct->present = seg_desc->p;
4313 kvm_desct->dpl = seg_desc->dpl;
4314 kvm_desct->db = seg_desc->d;
4315 kvm_desct->s = seg_desc->s;
4316 kvm_desct->l = seg_desc->l;
4317 kvm_desct->g = seg_desc->g;
4318 kvm_desct->avl = seg_desc->avl;
4319 if (!selector)
4320 kvm_desct->unusable = 1;
4321 else
4322 kvm_desct->unusable = 0;
4323 kvm_desct->padding = 0;
4324}
4325
b8222ad2
AS		 4326static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
4327 u16 selector,
4328 struct descriptor_table *dtable)
37817f29
IE		 4329{
4330 if (selector & 1 << 2) {
4331 struct kvm_segment kvm_seg;
4332
3e6e0aab 4333 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 4334
4335 if (kvm_seg.unusable)
4336 dtable->limit = 0;
4337 else
4338 dtable->limit = kvm_seg.limit;
4339 dtable->base = kvm_seg.base;
4340 }
4341 else
4342 kvm_x86_ops->get_gdt(vcpu, dtable);
4343}
4344
4345/* allowed just for 8 bytes segments */
4346static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4347 struct desc_struct *seg_desc)
4348{
4349 struct descriptor_table dtable;
4350 u16 index = selector >> 3;
4351
b8222ad2 4352 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4353
4354 if (dtable.limit < index * 8 + 7) {
4355 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
4356 return 1;
4357 }
d9048d32 4358 return kvm_read_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
37817f29
IE		 4359}
4360
4361/* allowed just for 8 bytes segments */
4362static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4363 struct desc_struct *seg_desc)
4364{
4365 struct descriptor_table dtable;
4366 u16 index = selector >> 3;
4367
b8222ad2 4368 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4369
4370 if (dtable.limit < index * 8 + 7)
4371 return 1;
d9048d32 4372 return kvm_write_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
37817f29
IE		 4373}
4374
abb39119 4375static gpa_t get_tss_base_addr(struct kvm_vcpu *vcpu,
37817f29
IE		 4376 struct desc_struct *seg_desc)
4377{
46a359e7 4378 u32 base_addr = get_desc_base(seg_desc);
37817f29 4379
98899aa0 4380 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 4381}
4382
37817f29
IE		 4383static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4384{
4385 struct kvm_segment kvm_seg;
4386
3e6e0aab 4387 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4388 return kvm_seg.selector;
4389}
4390
4391static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
4392 u16 selector,
4393 struct kvm_segment *kvm_seg)
4394{
4395 struct desc_struct seg_desc;
4396
4397 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
4398 return 1;
4399 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
4400 return 0;
4401}
4402
2259e3a7 4403static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4404{
4405 struct kvm_segment segvar = {
4406 .base = selector << 4,
4407 .limit = 0xffff,
4408 .selector = selector,
4409 .type = 3,
4410 .present = 1,
4411 .dpl = 3,
4412 .db = 0,
4413 .s = 1,
4414 .l = 0,
4415 .g = 0,
4416 .avl = 0,
4417 .unusable = 0,
4418 };
4419 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4420 return 0;
4421}
4422
c0c7c04b
AL		 4423static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg)
4424{
4425 return (seg != VCPU_SREG_LDTR) &&
4426 (seg != VCPU_SREG_TR) &&
91586a3b 4427 (kvm_get_rflags(vcpu) & X86_EFLAGS_VM);
c0c7c04b
AL		 4428}
4429
cb84b55f
MT		 4430static void kvm_check_segment_descriptor(struct kvm_vcpu *vcpu, int seg,
4431 u16 selector)
4432{
4433 /* NULL selector is not valid for CS and SS */
4434 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4435 if (!selector)
4436 kvm_queue_exception_e(vcpu, TS_VECTOR, selector >> 3);
4437}
4438
3e6e0aab
GT		 4439int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4440 int type_bits, int seg)
37817f29
IE		 4441{
4442 struct kvm_segment kvm_seg;
4443
c0c7c04b 4444 if (is_vm86_segment(vcpu, seg) || !(vcpu->arch.cr0 & X86_CR0_PE))
f4bbd9aa 4445 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 4446 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4447 return 1;
cb84b55f
MT		 4448
4449 kvm_check_segment_descriptor(vcpu, seg, selector);
37817f29
IE		 4450 kvm_seg.type |= type_bits;
4451
4452 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4453 seg != VCPU_SREG_LDTR)
4454 if (!kvm_seg.s)
4455 kvm_seg.unusable = 1;
4456
3e6e0aab 4457 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4458 return 0;
4459}
4460
4461static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4462 struct tss_segment_32 *tss)
4463{
4464 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4465 tss->eip = kvm_rip_read(vcpu);
91586a3b 4466 tss->eflags = kvm_get_rflags(vcpu);
5fdbf976
MT		 4467 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4468 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4469 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4470 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4471 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4472 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4473 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4474 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4475 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4476 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4477 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4478 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4479 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4480 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4481 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4482}
4483
4484static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4485 struct tss_segment_32 *tss)
4486{
4487 kvm_set_cr3(vcpu, tss->cr3);
4488
5fdbf976 4489 kvm_rip_write(vcpu, tss->eip);
91586a3b 4490 kvm_set_rflags(vcpu, tss->eflags | 2);
37817f29 4491
5fdbf976
MT		 4492 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4493 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4494 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4495 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4496 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4497 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4498 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4499 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4500
3e6e0aab 4501 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 4502 return 1;
4503
3e6e0aab 4504 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4505 return 1;
4506
3e6e0aab 4507 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4508 return 1;
4509
3e6e0aab 4510 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4511 return 1;
4512
3e6e0aab 4513 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4514 return 1;
4515
3e6e0aab 4516 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 4517 return 1;
4518
3e6e0aab 4519 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 4520 return 1;
4521 return 0;
4522}
4523
4524static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4525 struct tss_segment_16 *tss)
4526{
5fdbf976 4527 tss->ip = kvm_rip_read(vcpu);
91586a3b 4528 tss->flag = kvm_get_rflags(vcpu);
5fdbf976
MT		 4529 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4530 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4531 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4532 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4533 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4534 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4535 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4536 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4537
4538 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4539 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4540 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4541 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4542 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4543}
4544
4545static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4546 struct tss_segment_16 *tss)
4547{
5fdbf976 4548 kvm_rip_write(vcpu, tss->ip);
91586a3b 4549 kvm_set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 4550 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4551 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4552 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4553 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4554 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4555 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4556 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4557 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 4558
3e6e0aab 4559 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 4560 return 1;
4561
3e6e0aab 4562 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4563 return 1;
4564
3e6e0aab 4565 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4566 return 1;
4567
3e6e0aab 4568 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4569 return 1;
4570
3e6e0aab 4571 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4572 return 1;
4573 return 0;
4574}
4575
8b2cf73c 4576static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 4577 u16 old_tss_sel, u32 old_tss_base,
4578 struct desc_struct *nseg_desc)
37817f29
IE		 4579{
4580 struct tss_segment_16 tss_segment_16;
4581 int ret = 0;
4582
34198bf8
MT		 4583 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4584 sizeof tss_segment_16))
37817f29
IE		 4585 goto out;
4586
4587 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 4588
34198bf8
MT		 4589 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4590 sizeof tss_segment_16))
37817f29 4591 goto out;
34198bf8
MT		 4592
4593 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4594 &tss_segment_16, sizeof tss_segment_16))
4595 goto out;
4596
b237ac37
GN		 4597 if (old_tss_sel != 0xffff) {
4598 tss_segment_16.prev_task_link = old_tss_sel;
4599
4600 if (kvm_write_guest(vcpu->kvm,
4601 get_tss_base_addr(vcpu, nseg_desc),
4602 &tss_segment_16.prev_task_link,
4603 sizeof tss_segment_16.prev_task_link))
4604 goto out;
4605 }
4606
37817f29
IE		 4607 if (load_state_from_tss16(vcpu, &tss_segment_16))
4608 goto out;
4609
4610 ret = 1;
4611out:
4612 return ret;
4613}
4614
8b2cf73c 4615static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 4616 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 4617 struct desc_struct *nseg_desc)
4618{
4619 struct tss_segment_32 tss_segment_32;
4620 int ret = 0;
4621
34198bf8
MT		 4622 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4623 sizeof tss_segment_32))
37817f29
IE		 4624 goto out;
4625
4626 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 4627
34198bf8
MT		 4628 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4629 sizeof tss_segment_32))
4630 goto out;
4631
4632 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4633 &tss_segment_32, sizeof tss_segment_32))
37817f29 4634 goto out;
34198bf8 4635
b237ac37
GN		 4636 if (old_tss_sel != 0xffff) {
4637 tss_segment_32.prev_task_link = old_tss_sel;
4638
4639 if (kvm_write_guest(vcpu->kvm,
4640 get_tss_base_addr(vcpu, nseg_desc),
4641 &tss_segment_32.prev_task_link,
4642 sizeof tss_segment_32.prev_task_link))
4643 goto out;
4644 }
4645
37817f29
IE		 4646 if (load_state_from_tss32(vcpu, &tss_segment_32))
4647 goto out;
4648
4649 ret = 1;
4650out:
4651 return ret;
4652}
4653
4654int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4655{
4656 struct kvm_segment tr_seg;
4657 struct desc_struct cseg_desc;
4658 struct desc_struct nseg_desc;
4659 int ret = 0;
34198bf8
MT		 4660 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4661 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 4662
34198bf8 4663 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 4664
34198bf8
MT		 4665 /* FIXME: Handle errors. Failure to read either TSS or their
4666 * descriptors should generate a pagefault.
4667 */
37817f29
IE		 4668 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4669 goto out;
4670
34198bf8 4671 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 4672 goto out;
4673
37817f29
IE		 4674 if (reason != TASK_SWITCH_IRET) {
4675 int cpl;
4676
4677 cpl = kvm_x86_ops->get_cpl(vcpu);
4678 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4679 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4680 return 1;
4681 }
4682 }
4683
46a359e7 4684 if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) {
37817f29
IE		 4685 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4686 return 1;
4687 }
4688
4689 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 4690 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 4691 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 4692 }
4693
4694 if (reason == TASK_SWITCH_IRET) {
91586a3b
JK		 4695 u32 eflags = kvm_get_rflags(vcpu);
4696 kvm_set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
37817f29
IE		 4697 }
4698
b237ac37
GN		 4699 /* set back link to prev task only if NT bit is set in eflags
4700 note that old_tss_sel is not used afetr this point */
4701 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4702 old_tss_sel = 0xffff;
4703
37817f29 4704 if (nseg_desc.type & 8)
b237ac37
GN		 4705 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4706 old_tss_base, &nseg_desc);
37817f29 4707 else
b237ac37
GN		 4708 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4709 old_tss_base, &nseg_desc);
37817f29
IE		 4710
4711 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
91586a3b
JK		 4712 u32 eflags = kvm_get_rflags(vcpu);
4713 kvm_set_rflags(vcpu, eflags | X86_EFLAGS_NT);
37817f29
IE		 4714 }
4715
4716 if (reason != TASK_SWITCH_IRET) {
3fe913e7 4717 nseg_desc.type |= (1 << 1);
37817f29
IE		 4718 save_guest_segment_descriptor(vcpu, tss_selector,
4719 &nseg_desc);
4720 }
4721
4722 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4723 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4724 tr_seg.type = 11;
3e6e0aab 4725 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 4726out:
37817f29
IE		 4727 return ret;
4728}
4729EXPORT_SYMBOL_GPL(kvm_task_switch);
4730
b6c7a5dc
HB		 4731int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4732 struct kvm_sregs *sregs)
4733{
4734 int mmu_reset_needed = 0;
923c61bb 4735 int pending_vec, max_bits;
b6c7a5dc
HB		 4736 struct descriptor_table dt;
4737
4738 vcpu_load(vcpu);
4739
4740 dt.limit = sregs->idt.limit;
4741 dt.base = sregs->idt.base;
4742 kvm_x86_ops->set_idt(vcpu, &dt);
4743 dt.limit = sregs->gdt.limit;
4744 dt.base = sregs->gdt.base;
4745 kvm_x86_ops->set_gdt(vcpu, &dt);
4746
ad312c7c
ZX		 4747 vcpu->arch.cr2 = sregs->cr2;
4748 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4749 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4750
2d3ad1f4 4751 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4752
ad312c7c 4753 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 4754 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4755 kvm_set_apic_base(vcpu, sregs->apic_base);
4756
ad312c7c 4757 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 4758 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4759 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4760
fc78f519 4761 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 4762 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 4763 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 4764 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 4765 mmu_reset_needed = 1;
4766 }
b6c7a5dc
HB		 4767
4768 if (mmu_reset_needed)
4769 kvm_mmu_reset_context(vcpu);
4770
923c61bb
GN		 4771 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4772 pending_vec = find_first_bit(
4773 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4774 if (pending_vec < max_bits) {
66fd3f7f 4775 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4776 pr_debug("Set back pending irq %d\n", pending_vec);
4777 if (irqchip_in_kernel(vcpu->kvm))
4778 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4779 }
4780
3e6e0aab
GT		 4781 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4782 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4783 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4784 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4785 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4786 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4787
3e6e0aab
GT		 4788 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4789 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4790
5f0269f5
ME		 4791 update_cr8_intercept(vcpu);
4792
9c3e4aab 4793 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4794 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab
MT		 4795 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4796 !(vcpu->arch.cr0 & X86_CR0_PE))
4797 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4798
b6c7a5dc
HB		 4799 vcpu_put(vcpu);
4800
4801 return 0;
4802}
4803
d0bfb940
JK		 4804int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4805 struct kvm_guest_debug *dbg)
b6c7a5dc 4806{
355be0b9 4807 unsigned long rflags;
ae675ef0 4808 int i, r;
b6c7a5dc
HB		 4809
4810 vcpu_load(vcpu);
4811
4f926bf2
JK		 4812 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
4813 r = -EBUSY;
4814 if (vcpu->arch.exception.pending)
4815 goto unlock_out;
4816 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4817 kvm_queue_exception(vcpu, DB_VECTOR);
4818 else
4819 kvm_queue_exception(vcpu, BP_VECTOR);
4820 }
4821
91586a3b
JK		 4822 /*
4823 * Read rflags as long as potentially injected trace flags are still
4824 * filtered out.
4825 */
4826 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 4827
4828 vcpu->guest_debug = dbg->control;
4829 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
4830 vcpu->guest_debug = 0;
4831
4832 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 4833 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4834 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4835 vcpu->arch.switch_db_regs =
4836 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4837 } else {
4838 for (i = 0; i < KVM_NR_DB_REGS; i++)
4839 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4840 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4841 }
4842
94fe45da
JK		 4843 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
4844 vcpu->arch.singlestep_cs =
4845 get_segment_selector(vcpu, VCPU_SREG_CS);
4846 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu);
4847 }
4848
91586a3b
JK		 4849 /*
4850 * Trigger an rflags update that will inject or remove the trace
4851 * flags.
4852 */
4853 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 4854
355be0b9 4855 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 4856
4f926bf2 4857 r = 0;
d0bfb940 4858
4f926bf2 4859unlock_out:
b6c7a5dc
HB		 4860 vcpu_put(vcpu);
4861
4862 return r;
4863}
4864
d0752060
HB		 4865/*
4866 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4867 * we have asm/x86/processor.h
4868 */
4869struct fxsave {
4870 u16 cwd;
4871 u16 swd;
4872 u16 twd;
4873 u16 fop;
4874 u64 rip;
4875 u64 rdp;
4876 u32 mxcsr;
4877 u32 mxcsr_mask;
4878 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4879#ifdef CONFIG_X86_64
4880 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4881#else
4882 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4883#endif
4884};
4885
8b006791
ZX		 4886/*
4887 * Translate a guest virtual address to a guest physical address.
4888 */
4889int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4890 struct kvm_translation *tr)
4891{
4892 unsigned long vaddr = tr->linear_address;
4893 gpa_t gpa;
4894
4895 vcpu_load(vcpu);
72dc67a6 4896 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4897 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4898 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4899 tr->physical_address = gpa;
4900 tr->valid = gpa != UNMAPPED_GVA;
4901 tr->writeable = 1;
4902 tr->usermode = 0;
8b006791
ZX		 4903 vcpu_put(vcpu);
4904
4905 return 0;
4906}
4907
d0752060
HB		 4908int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4909{
ad312c7c 4910 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4911
4912 vcpu_load(vcpu);
4913
4914 memcpy(fpu->fpr, fxsave->st_space, 128);
4915 fpu->fcw = fxsave->cwd;
4916 fpu->fsw = fxsave->swd;
4917 fpu->ftwx = fxsave->twd;
4918 fpu->last_opcode = fxsave->fop;
4919 fpu->last_ip = fxsave->rip;
4920 fpu->last_dp = fxsave->rdp;
4921 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4922
4923 vcpu_put(vcpu);
4924
4925 return 0;
4926}
4927
4928int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4929{
ad312c7c 4930 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4931
4932 vcpu_load(vcpu);
4933
4934 memcpy(fxsave->st_space, fpu->fpr, 128);
4935 fxsave->cwd = fpu->fcw;
4936 fxsave->swd = fpu->fsw;
4937 fxsave->twd = fpu->ftwx;
4938 fxsave->fop = fpu->last_opcode;
4939 fxsave->rip = fpu->last_ip;
4940 fxsave->rdp = fpu->last_dp;
4941 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4942
4943 vcpu_put(vcpu);
4944
4945 return 0;
4946}
4947
4948void fx_init(struct kvm_vcpu *vcpu)
4949{
4950 unsigned after_mxcsr_mask;
4951
bc1a34f1
AA		 4952 /*
4953 * Touch the fpu the first time in non atomic context as if
4954 * this is the first fpu instruction the exception handler
4955 * will fire before the instruction returns and it'll have to
4956 * allocate ram with GFP_KERNEL.
4957 */
4958 if (!used_math())
d6e88aec 4959 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4960
d0752060
HB		 4961 /* Initialize guest FPU by resetting ours and saving into guest's */
4962 preempt_disable();
d6e88aec
AK		 4963 kvm_fx_save(&vcpu->arch.host_fx_image);
4964 kvm_fx_finit();
4965 kvm_fx_save(&vcpu->arch.guest_fx_image);
4966 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4967 preempt_enable();
4968
ad312c7c 4969 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4970 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4971 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4972 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4973 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4974}
4975EXPORT_SYMBOL_GPL(fx_init);
4976
4977void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4978{
4979 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4980 return;
4981
4982 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4983 kvm_fx_save(&vcpu->arch.host_fx_image);
4984 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4985}
4986EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4987
4988void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4989{
4990 if (!vcpu->guest_fpu_loaded)
4991 return;
4992
4993 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4994 kvm_fx_save(&vcpu->arch.guest_fx_image);
4995 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4996 ++vcpu->stat.fpu_reload;
d0752060
HB		 4997}
4998EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4999
5000void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5001{
7f1ea208
JR		 5002 if (vcpu->arch.time_page) {
5003 kvm_release_page_dirty(vcpu->arch.time_page);
5004 vcpu->arch.time_page = NULL;
5005 }
5006
e9b11c17
ZX		 5007 kvm_x86_ops->vcpu_free(vcpu);
5008}
5009
5010struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5011 unsigned int id)
5012{
26e5215f
AK		 5013 return kvm_x86_ops->vcpu_create(kvm, id);
5014}
e9b11c17 5015
26e5215f
AK		 5016int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5017{
5018 int r;
e9b11c17
ZX		 5019
5020 /* We do fxsave: this must be aligned. */
ad312c7c 5021 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5022
0bed3b56 5023 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5024 vcpu_load(vcpu);
5025 r = kvm_arch_vcpu_reset(vcpu);
5026 if (r == 0)
5027 r = kvm_mmu_setup(vcpu);
5028 vcpu_put(vcpu);
5029 if (r < 0)
5030 goto free_vcpu;
5031
26e5215f 5032 return 0;
e9b11c17
ZX		 5033free_vcpu:
5034 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5035 return r;
e9b11c17
ZX		 5036}
5037
d40ccc62 5038void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5039{
5040 vcpu_load(vcpu);
5041 kvm_mmu_unload(vcpu);
5042 vcpu_put(vcpu);
5043
5044 kvm_x86_ops->vcpu_free(vcpu);
5045}
5046
5047int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5048{
448fa4a9
JK		 5049 vcpu->arch.nmi_pending = false;
5050 vcpu->arch.nmi_injected = false;
5051
42dbaa5a
JK		 5052 vcpu->arch.switch_db_regs = 0;
5053 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5054 vcpu->arch.dr6 = DR6_FIXED_1;
5055 vcpu->arch.dr7 = DR7_FIXED_1;
5056
e9b11c17
ZX		 5057 return kvm_x86_ops->vcpu_reset(vcpu);
5058}
5059
10474ae8 5060int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5061{
0cca7907
ZA		 5062 /*
5063 * Since this may be called from a hotplug notifcation,
5064 * we can't get the CPU frequency directly.
5065 */
5066 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5067 int cpu = raw_smp_processor_id();
5068 per_cpu(cpu_tsc_khz, cpu) = 0;
5069 }
18863bdd
AK		 5070
5071 kvm_shared_msr_cpu_online();
5072
10474ae8 5073 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5074}
5075
5076void kvm_arch_hardware_disable(void *garbage)
5077{
5078 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5079 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5080}
5081
5082int kvm_arch_hardware_setup(void)
5083{
5084 return kvm_x86_ops->hardware_setup();
5085}
5086
5087void kvm_arch_hardware_unsetup(void)
5088{
5089 kvm_x86_ops->hardware_unsetup();
5090}
5091
5092void kvm_arch_check_processor_compat(void *rtn)
5093{
5094 kvm_x86_ops->check_processor_compatibility(rtn);
5095}
5096
5097int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5098{
5099 struct page *page;
5100 struct kvm *kvm;
5101 int r;
5102
5103 BUG_ON(vcpu->kvm == NULL);
5104 kvm = vcpu->kvm;
5105
ad312c7c 5106 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5107 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5108 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5109 else
a4535290 5110 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5111
5112 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5113 if (!page) {
5114 r = -ENOMEM;
5115 goto fail;
5116 }
ad312c7c 5117 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5118
5119 r = kvm_mmu_create(vcpu);
5120 if (r < 0)
5121 goto fail_free_pio_data;
5122
5123 if (irqchip_in_kernel(kvm)) {
5124 r = kvm_create_lapic(vcpu);
5125 if (r < 0)
5126 goto fail_mmu_destroy;
5127 }
5128
890ca9ae
HY		 5129 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5130 GFP_KERNEL);
5131 if (!vcpu->arch.mce_banks) {
5132 r = -ENOMEM;
443c39bc 5133 goto fail_free_lapic;
890ca9ae
HY		 5134 }
5135 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5136
e9b11c17 5137 return 0;
443c39bc
WY		 5138fail_free_lapic:
5139 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5140fail_mmu_destroy:
5141 kvm_mmu_destroy(vcpu);
5142fail_free_pio_data:
ad312c7c 5143 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5144fail:
5145 return r;
5146}
5147
5148void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5149{
36cb93fd 5150 kfree(vcpu->arch.mce_banks);
e9b11c17 5151 kvm_free_lapic(vcpu);
3200f405 5152 down_read(&vcpu->kvm->slots_lock);
e9b11c17 5153 kvm_mmu_destroy(vcpu);
3200f405 5154 up_read(&vcpu->kvm->slots_lock);
ad312c7c 5155 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5156}
d19a9cd2
ZX		 5157
5158struct kvm *kvm_arch_create_vm(void)
5159{
5160 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5161
5162 if (!kvm)
5163 return ERR_PTR(-ENOMEM);
5164
fef9cce0
MT		 5165 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5166 if (!kvm->arch.aliases) {
5167 kfree(kvm);
5168 return ERR_PTR(-ENOMEM);
5169 }
5170
f05e70ac 5171 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5172 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5173
5550af4d
SY		 5174 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5175 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5176
53f658b3
MT		 5177 rdtscll(kvm->arch.vm_init_tsc);
5178
d19a9cd2
ZX		 5179 return kvm;
5180}
5181
5182static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5183{
5184 vcpu_load(vcpu);
5185 kvm_mmu_unload(vcpu);
5186 vcpu_put(vcpu);
5187}
5188
5189static void kvm_free_vcpus(struct kvm *kvm)
5190{
5191 unsigned int i;
988a2cae 5192 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5193
5194 /*
5195 * Unpin any mmu pages first.
5196 */
988a2cae
GN		 5197 kvm_for_each_vcpu(i, vcpu, kvm)
5198 kvm_unload_vcpu_mmu(vcpu);
5199 kvm_for_each_vcpu(i, vcpu, kvm)
5200 kvm_arch_vcpu_free(vcpu);
5201
5202 mutex_lock(&kvm->lock);
5203 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5204 kvm->vcpus[i] = NULL;
d19a9cd2 5205
988a2cae
GN		 5206 atomic_set(&kvm->online_vcpus, 0);
5207 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5208}
5209
ad8ba2cd
SY		 5210void kvm_arch_sync_events(struct kvm *kvm)
5211{
ba4cef31 5212 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5213}
5214
d19a9cd2
ZX		 5215void kvm_arch_destroy_vm(struct kvm *kvm)
5216{
6eb55818 5217 kvm_iommu_unmap_guest(kvm);
7837699f 5218 kvm_free_pit(kvm);
d7deeeb0
ZX		 5219 kfree(kvm->arch.vpic);
5220 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5221 kvm_free_vcpus(kvm);
5222 kvm_free_physmem(kvm);
3d45830c
AK		 5223 if (kvm->arch.apic_access_page)
5224 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5225 if (kvm->arch.ept_identity_pagetable)
5226 put_page(kvm->arch.ept_identity_pagetable);
fef9cce0 5227 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5228 kfree(kvm);
5229}
0de10343 5230
f7784b8e
MT		 5231int kvm_arch_prepare_memory_region(struct kvm *kvm,
5232 struct kvm_memory_slot *memslot,
0de10343 5233 struct kvm_memory_slot old,
f7784b8e 5234 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5235 int user_alloc)
5236{
f7784b8e 5237 int npages = memslot->npages;
0de10343
ZX		 5238
5239 /*To keep backward compatibility with older userspace,
5240 *x86 needs to hanlde !user_alloc case.
5241 */
5242 if (!user_alloc) {
5243 if (npages && !old.rmap) {
604b38ac
AA		 5244 unsigned long userspace_addr;
5245
72dc67a6 5246 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5247 userspace_addr = do_mmap(NULL, 0,
5248 npages * PAGE_SIZE,
5249 PROT_READ | PROT_WRITE,
acee3c04 5250 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5251 0);
72dc67a6 5252 up_write(&current->mm->mmap_sem);
0de10343 5253
604b38ac
AA		 5254 if (IS_ERR((void *)userspace_addr))
5255 return PTR_ERR((void *)userspace_addr);
5256
604b38ac 5257 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5258 }
5259 }
5260
f7784b8e
MT		 5261
5262 return 0;
5263}
5264
5265void kvm_arch_commit_memory_region(struct kvm *kvm,
5266 struct kvm_userspace_memory_region *mem,
5267 struct kvm_memory_slot old,
5268 int user_alloc)
5269{
5270
5271 int npages = mem->memory_size >> PAGE_SHIFT;
5272
5273 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5274 int ret;
5275
5276 down_write(&current->mm->mmap_sem);
5277 ret = do_munmap(current->mm, old.userspace_addr,
5278 old.npages * PAGE_SIZE);
5279 up_write(&current->mm->mmap_sem);
5280 if (ret < 0)
5281 printk(KERN_WARNING
5282 "kvm_vm_ioctl_set_memory_region: "
5283 "failed to munmap memory\n");
5284 }
5285
7c8a83b7 5286 spin_lock(&kvm->mmu_lock);
f05e70ac 5287 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5288 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5289 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5290 }
5291
5292 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5293 spin_unlock(&kvm->mmu_lock);
0de10343 5294}
1d737c8a 5295
34d4cb8f
MT		 5296void kvm_arch_flush_shadow(struct kvm *kvm)
5297{
5298 kvm_mmu_zap_all(kvm);
8986ecc0 5299 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5300}
5301
1d737c8a
ZX		 5302int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5303{
a4535290 5304 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5305 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5306 || vcpu->arch.nmi_pending ||
5307 (kvm_arch_interrupt_allowed(vcpu) &&
5308 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5309}
5736199a 5310
5736199a
ZX		 5311void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5312{
32f88400
MT		 5313 int me;
5314 int cpu = vcpu->cpu;
5736199a
ZX		 5315
5316 if (waitqueue_active(&vcpu->wq)) {
5317 wake_up_interruptible(&vcpu->wq);
5318 ++vcpu->stat.halt_wakeup;
5319 }
32f88400
MT		 5320
5321 me = get_cpu();
5322 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5323 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5324 smp_send_reschedule(cpu);
e9571ed5 5325 put_cpu();
5736199a 5326}
78646121
GN		 5327
5328int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5329{
5330 return kvm_x86_ops->interrupt_allowed(vcpu);
5331}
229456fc 5332
94fe45da
JK		 5333unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5334{
5335 unsigned long rflags;
5336
5337 rflags = kvm_x86_ops->get_rflags(vcpu);
5338 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5339 rflags &= ~(unsigned long)(X86_EFLAGS_TF | X86_EFLAGS_RF);
5340 return rflags;
5341}
5342EXPORT_SYMBOL_GPL(kvm_get_rflags);
5343
5344void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5345{
5346 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
5347 vcpu->arch.singlestep_cs ==
5348 get_segment_selector(vcpu, VCPU_SREG_CS) &&
5349 vcpu->arch.singlestep_rip == kvm_rip_read(vcpu))
5350 rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
5351 kvm_x86_ops->set_rflags(vcpu, rflags);
5352}
5353EXPORT_SYMBOL_GPL(kvm_set_rflags);
5354
229456fc
MT		 5355EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5356EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5357EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5358EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5359EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5360EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5361EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5362EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5363EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5364EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5365EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
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