[ceph.git] / ceph / src / crypto / isa-l / isa-l_crypto / sha1_mb / sha1_mb_mgr_flush_avx512_ni.asm

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;  Copyright(c) 2011-2017 Intel Corporation All rights reserved.
;
;  Redistribution and use in source and binary forms, with or without
;  modification, are permitted provided that the following conditions
;  are met:
;    * Redistributions of source code must retain the above copyright
;      notice, this list of conditions and the following disclaimer.
;    * Redistributions in binary form must reproduce the above copyright
;      notice, this list of conditions and the following disclaimer in
;      the documentation and/or other materials provided with the
;      distribution.
;    * Neither the name of Intel Corporation nor the names of its
;      contributors may be used to endorse or promote products derived
;      from this software without specific prior written permission.
;
;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
;  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
;  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
;  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
;  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
;  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
;  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
;  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
;  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
;  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

%include "sha1_job.asm"
%include "sha1_mb_mgr_datastruct.asm"
%include "reg_sizes.asm"

%ifdef HAVE_AS_KNOWS_AVX512
 %ifdef HAVE_AS_KNOWS_SHANI

extern sha1_mb_x16_avx512
extern sha1_ni_x1

[bits 64]
default rel
section .text

%ifidn __OUTPUT_FORMAT__, elf64
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; LINUX register definitions
%define arg1    rdi ; rcx
%define arg2    rsi ; rdx
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
%else
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; WINDOWS register definitions
%define arg1    rcx
%define arg2    rdx
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
%endif

; Common definitions and latter-state(unused,covered,unchanged)
%define state   arg1	; unchanged
%define job     arg2	; unused
%define len2    arg2	; unused

; idx must be a register not clobberred by sha1_mb_x16_avx512
%define idx             rbp	; unchanged

%define unused_lanes    rbx	; covered
%define lane_data       rbx	; covered
%define tmp2            rbx	; covered

%define num_lanes_inuse r9	; covered

%define job_rax         rax	; covered
%define tmp             rax	; unused

; STACK_SPACE needs to be an odd multiple of 8
_XMM_SAVE_SIZE  equ 10*16
_GPR_SAVE_SIZE  equ 8*8
_ALIGN_SIZE     equ 8

_XMM_SAVE       equ 0
_GPR_SAVE       equ _XMM_SAVE + _XMM_SAVE_SIZE
STACK_SPACE     equ _GPR_SAVE + _GPR_SAVE_SIZE + _ALIGN_SIZE

%define APPEND(a,b) a %+ b

; SHA1_JOB* sha1_mb_mgr_flush_avx512(SHA1_MB_JOB_MGR *state)
; arg 1 : rcx : state
mk_global sha1_mb_mgr_flush_avx512_ni, function
sha1_mb_mgr_flush_avx512_ni:
	endbranch
	sub     rsp, STACK_SPACE
	mov     [rsp + _GPR_SAVE + 8*0], rbx
	mov     [rsp + _GPR_SAVE + 8*3], rbp
	mov     [rsp + _GPR_SAVE + 8*4], r12
	mov     [rsp + _GPR_SAVE + 8*5], r13
	mov     [rsp + _GPR_SAVE + 8*6], r14
	mov     [rsp + _GPR_SAVE + 8*7], r15
%ifidn __OUTPUT_FORMAT__, win64
	mov     [rsp + _GPR_SAVE + 8*1], rsi
	mov     [rsp + _GPR_SAVE + 8*2], rdi
	vmovdqa  [rsp + _XMM_SAVE + 16*0], xmm6
	vmovdqa  [rsp + _XMM_SAVE + 16*1], xmm7
	vmovdqa  [rsp + _XMM_SAVE + 16*2], xmm8
	vmovdqa  [rsp + _XMM_SAVE + 16*3], xmm9
	vmovdqa  [rsp + _XMM_SAVE + 16*4], xmm10
	vmovdqa  [rsp + _XMM_SAVE + 16*5], xmm11
	vmovdqa  [rsp + _XMM_SAVE + 16*6], xmm12
	vmovdqa  [rsp + _XMM_SAVE + 16*7], xmm13
	vmovdqa  [rsp + _XMM_SAVE + 16*8], xmm14
	vmovdqa  [rsp + _XMM_SAVE + 16*9], xmm15
%endif

	mov	DWORD(num_lanes_inuse), [state + _num_lanes_inuse]
	cmp	num_lanes_inuse, 0
	jz	return_null

	; find a lane with a non-null job
	xor	idx, idx
%assign I 1
%rep 15
	cmp	qword [state + _ldata + I * _LANE_DATA_size + _job_in_lane], 0
	cmovne	idx, [APPEND(lane_,I)]
%assign I (I+1)
%endrep

	; copy idx to empty lanes
copy_lane_data:
	mov	tmp, [state + _args + _data_ptr + 8*idx]

%assign I 0
%rep 16
	cmp	qword [state + _ldata + I * _LANE_DATA_size + _job_in_lane], 0
	jne	APPEND(skip_,I)
	mov	[state + _args + _data_ptr + 8*I], tmp
	mov 	dword [state + _lens + 4*I], 0xFFFFFFFF
APPEND(skip_,I):
%assign I (I+1)
%endrep

	; Find min length
	vmovdqu ymm0, [state + _lens + 0*32]
	vmovdqu ymm1, [state + _lens + 1*32]

	vpminud ymm2, ymm0, ymm1        ; ymm2 has {H1,G1,F1,E1,D1,C1,B1,A1}
	vpalignr ymm3, ymm3, ymm2, 8    ; ymm3 has {x,x,H1,G1,x,x,D1,C1}
	vpminud ymm2, ymm2, ymm3        ; ymm2 has {x,x,H2,G2,x,x,D2,C2}
	vpalignr ymm3, ymm3, ymm2, 4    ; ymm3 has {x,x, x,H2,x,x, x,D2}
	vpminud ymm2, ymm2, ymm3        ; ymm2 has {x,x, x,G3,x,x, x,C3}
	vperm2i128 ymm3, ymm2, ymm2, 1	; ymm3 has {x,x, x, x,x,x, x,C3}
        vpminud ymm2, ymm2, ymm3        ; ymm2 has min value in low dword

	vmovd   DWORD(idx), xmm2
	mov	len2, idx
	and	idx, 0xF
	shr	len2, 4
	jz	len_is_0

	; compare with shani-sb threshold, if num_lanes_inuse <= threshold, using shani func
	cmp	dword [state + _num_lanes_inuse], SHA1_NI_SB_THRESHOLD_AVX512
	ja	mb_processing

	; lensN-len2=idx
	mov     [state + _lens + idx*4], DWORD(idx)
	mov	r10, idx
	or	r10, 0x4000	; avx2 has 8 lanes *4, r10b is idx, r10b2 is 32
	; "state" and "args" are the same address, arg1
	; len is arg2, idx and nlane in r10
	call    sha1_ni_x1
	; state and idx are intact
	jmp	len_is_0

mb_processing:

	vpand   ymm2, ymm2, [rel clear_low_nibble]
        vpshufd ymm2, ymm2, 0

        vpsubd  ymm0, ymm0, ymm2
        vpsubd  ymm1, ymm1, ymm2

        vmovdqu [state + _lens + 0*32], ymm0
        vmovdqu [state + _lens + 1*32], ymm1


	; "state" and "args" are the same address, arg1
	; len is arg2
	call	sha1_mb_x16_avx512
	; state and idx are intact

len_is_0:
	; process completed job "idx"
	imul	lane_data, idx, _LANE_DATA_size
	lea	lane_data, [state + _ldata + lane_data]

	mov	job_rax, [lane_data + _job_in_lane]
	mov	qword [lane_data + _job_in_lane], 0
	mov	dword [job_rax + _status], STS_COMPLETED
	mov	unused_lanes, [state + _unused_lanes]
	shl	unused_lanes, 4
	or	unused_lanes, idx
	mov	[state + _unused_lanes], unused_lanes

        mov     DWORD(num_lanes_inuse), [state + _num_lanes_inuse]
        sub     num_lanes_inuse, 1
        mov     [state + _num_lanes_inuse], DWORD(num_lanes_inuse)

	vmovd	xmm0, [state + _args_digest + 4*idx + 0*64]
	vpinsrd	xmm0, [state + _args_digest + 4*idx + 1*64], 1
	vpinsrd	xmm0, [state + _args_digest + 4*idx + 2*64], 2
	vpinsrd	xmm0, [state + _args_digest + 4*idx + 3*64], 3
	mov	DWORD(tmp2),  [state + _args_digest + 4*idx + 4*64]

	vmovdqa	[job_rax + _result_digest + 0*16], xmm0
	mov	[job_rax + _result_digest + 1*16], DWORD(tmp2)

return:

%ifidn __OUTPUT_FORMAT__, win64
	vmovdqa  xmm6, [rsp + _XMM_SAVE + 16*0]
	vmovdqa  xmm7, [rsp + _XMM_SAVE + 16*1]
	vmovdqa  xmm8, [rsp + _XMM_SAVE + 16*2]
	vmovdqa  xmm9, [rsp + _XMM_SAVE + 16*3]
	vmovdqa  xmm10, [rsp + _XMM_SAVE + 16*4]
	vmovdqa  xmm11, [rsp + _XMM_SAVE + 16*5]
	vmovdqa  xmm12, [rsp + _XMM_SAVE + 16*6]
	vmovdqa  xmm13, [rsp + _XMM_SAVE + 16*7]
	vmovdqa  xmm14, [rsp + _XMM_SAVE + 16*8]
	vmovdqa  xmm15, [rsp + _XMM_SAVE + 16*9]
	mov     rsi, [rsp + _GPR_SAVE + 8*1]
	mov     rdi, [rsp + _GPR_SAVE + 8*2]
%endif
	mov     rbx, [rsp + _GPR_SAVE + 8*0]
	mov     rbp, [rsp + _GPR_SAVE + 8*3]
	mov     r12, [rsp + _GPR_SAVE + 8*4]
	mov     r13, [rsp + _GPR_SAVE + 8*5]
	mov     r14, [rsp + _GPR_SAVE + 8*6]
	mov     r15, [rsp + _GPR_SAVE + 8*7]
	add     rsp, STACK_SPACE

	ret

return_null:
	xor	job_rax, job_rax
	jmp	return

section .data align=16

align 16
clear_low_nibble:
	dq 0x00000000FFFFFFF0, 0x0000000000000000
	dq 0x00000000FFFFFFF0, 0x0000000000000000
lane_1:     dq  1
lane_2:     dq  2
lane_3:     dq  3
lane_4:     dq  4
lane_5:     dq  5
lane_6:     dq  6
lane_7:     dq  7
lane_8:     dq  8
lane_9:     dq  9
lane_10:    dq  10
lane_11:    dq  11
lane_12:    dq  12
lane_13:    dq  13
lane_14:    dq  14
lane_15:    dq  15

 %else
  %ifidn __OUTPUT_FORMAT__, win64
   global no_sha1_mb_mgr_flush_avx512_ni
   no_sha1_mb_mgr_flush_avx512_ni:
  %endif
 %endif ; HAVE_AS_KNOWS_SHANI
%else
%ifidn __OUTPUT_FORMAT__, win64
 global no_sha1_mb_mgr_flush_avx512_ni
  no_sha1_mb_mgr_flush_avx512_ni:
 %endif
%endif ; HAVE_AS_KNOWS_AVX512
Commit	Line	Data
1e59de90 TL	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	2	; Copyright(c) 2011-2017 Intel Corporation All rights reserved.
	3	;
	4	; Redistribution and use in source and binary forms, with or without
	5	; modification, are permitted provided that the following conditions
	6	; are met:
	7	; * Redistributions of source code must retain the above copyright
	8	; notice, this list of conditions and the following disclaimer.
	9	; * Redistributions in binary form must reproduce the above copyright
	10	; notice, this list of conditions and the following disclaimer in
	11	; the documentation and/or other materials provided with the
	12	; distribution.
	13	; * Neither the name of Intel Corporation nor the names of its
	14	; contributors may be used to endorse or promote products derived
	15	; from this software without specific prior written permission.
	16	;
	17	; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	18	; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	19	; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	20	; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	21	; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	22	; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	23	; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	24	; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	25	; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	26	; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	27	; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	28	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	29
	30	%include "sha1_job.asm"
	31	%include "sha1_mb_mgr_datastruct.asm"
	32	%include "reg_sizes.asm"
	33
	34	%ifdef HAVE_AS_KNOWS_AVX512
	35	%ifdef HAVE_AS_KNOWS_SHANI
	36
	37	extern sha1_mb_x16_avx512
	38	extern sha1_ni_x1
	39
	40	[bits 64]
	41	default rel
	42	section .text
	43
	44	%ifidn __OUTPUT_FORMAT__, elf64
	45	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	46	; LINUX register definitions
	47	%define arg1 rdi ; rcx
	48	%define arg2 rsi ; rdx
	49	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	50	%else
	51	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	52	; WINDOWS register definitions
	53	%define arg1 rcx
	54	%define arg2 rdx
	55	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	56	%endif
	57
	58	; Common definitions and latter-state(unused,covered,unchanged)
	59	%define state arg1 ; unchanged
	60	%define job arg2 ; unused
	61	%define len2 arg2 ; unused
	62
	63	; idx must be a register not clobberred by sha1_mb_x16_avx512
	64	%define idx rbp ; unchanged
65
66	%define unused_lanes rbx ; covered
67	%define lane_data rbx ; covered
68	%define tmp2 rbx ; covered
69
70	%define num_lanes_inuse r9 ; covered
71
72	%define job_rax rax ; covered
73	%define tmp rax ; unused
74
75	; STACK_SPACE needs to be an odd multiple of 8
76	_XMM_SAVE_SIZE equ 10*16
77	_GPR_SAVE_SIZE equ 8*8
78	_ALIGN_SIZE equ 8
79
80	_XMM_SAVE equ 0
81	_GPR_SAVE equ _XMM_SAVE + _XMM_SAVE_SIZE
82	STACK_SPACE equ _GPR_SAVE + _GPR_SAVE_SIZE + _ALIGN_SIZE
83
84	%define APPEND(a,b) a %+ b
85
86	; SHA1_JOB* sha1_mb_mgr_flush_avx512(SHA1_MB_JOB_MGR *state)
87	; arg 1 : rcx : state
88	mk_global sha1_mb_mgr_flush_avx512_ni, function
89	sha1_mb_mgr_flush_avx512_ni:
90	endbranch
91	sub rsp, STACK_SPACE
92	mov [rsp + _GPR_SAVE + 8*0], rbx
93	mov [rsp + _GPR_SAVE + 8*3], rbp
94	mov [rsp + _GPR_SAVE + 8*4], r12
95	mov [rsp + _GPR_SAVE + 8*5], r13
96	mov [rsp + _GPR_SAVE + 8*6], r14
97	mov [rsp + _GPR_SAVE + 8*7], r15
98	%ifidn __OUTPUT_FORMAT__, win64
99	mov [rsp + _GPR_SAVE + 8*1], rsi
100	mov [rsp + _GPR_SAVE + 8*2], rdi
101	vmovdqa [rsp + _XMM_SAVE + 16*0], xmm6
102	vmovdqa [rsp + _XMM_SAVE + 16*1], xmm7
103	vmovdqa [rsp + _XMM_SAVE + 16*2], xmm8
104	vmovdqa [rsp + _XMM_SAVE + 16*3], xmm9
105	vmovdqa [rsp + _XMM_SAVE + 16*4], xmm10
106	vmovdqa [rsp + _XMM_SAVE + 16*5], xmm11
107	vmovdqa [rsp + _XMM_SAVE + 16*6], xmm12
108	vmovdqa [rsp + _XMM_SAVE + 16*7], xmm13
109	vmovdqa [rsp + _XMM_SAVE + 16*8], xmm14
110	vmovdqa [rsp + _XMM_SAVE + 16*9], xmm15
111	%endif
112
113	mov DWORD(num_lanes_inuse), [state + _num_lanes_inuse]
114	cmp num_lanes_inuse, 0
115	jz return_null
116
117	; find a lane with a non-null job
118	xor idx, idx
119	%assign I 1
120	%rep 15
121	cmp qword [state + _ldata + I * _LANE_DATA_size + _job_in_lane], 0
122	cmovne idx, [APPEND(lane_,I)]
123	%assign I (I+1)
124	%endrep
125
126	; copy idx to empty lanes
127	copy_lane_data:
128	mov tmp, [state + _args + _data_ptr + 8*idx]
129
130	%assign I 0
131	%rep 16
132	cmp qword [state + _ldata + I * _LANE_DATA_size + _job_in_lane], 0
133	jne APPEND(skip_,I)
134	mov [state + _args + _data_ptr + 8*I], tmp
135	mov dword [state + _lens + 4*I], 0xFFFFFFFF
136	APPEND(skip_,I):
137	%assign I (I+1)
138	%endrep
139
140	; Find min length
141	vmovdqu ymm0, [state + _lens + 0*32]
142	vmovdqu ymm1, [state + _lens + 1*32]
143
144	vpminud ymm2, ymm0, ymm1 ; ymm2 has {H1,G1,F1,E1,D1,C1,B1,A1}
145	vpalignr ymm3, ymm3, ymm2, 8 ; ymm3 has {x,x,H1,G1,x,x,D1,C1}
146	vpminud ymm2, ymm2, ymm3 ; ymm2 has {x,x,H2,G2,x,x,D2,C2}
147	vpalignr ymm3, ymm3, ymm2, 4 ; ymm3 has {x,x, x,H2,x,x, x,D2}
148	vpminud ymm2, ymm2, ymm3 ; ymm2 has {x,x, x,G3,x,x, x,C3}
149	vperm2i128 ymm3, ymm2, ymm2, 1 ; ymm3 has {x,x, x, x,x,x, x,C3}
150	vpminud ymm2, ymm2, ymm3 ; ymm2 has min value in low dword
151
152	vmovd DWORD(idx), xmm2
153	mov len2, idx
154	and idx, 0xF
155	shr len2, 4
156	jz len_is_0
157
158	; compare with shani-sb threshold, if num_lanes_inuse <= threshold, using shani func
159	cmp dword [state + _num_lanes_inuse], SHA1_NI_SB_THRESHOLD_AVX512
160	ja mb_processing
161
162	; lensN-len2=idx
163	mov [state + _lens + idx*4], DWORD(idx)
164	mov r10, idx
165	or r10, 0x4000 ; avx2 has 8 lanes *4, r10b is idx, r10b2 is 32
166	; "state" and "args" are the same address, arg1
167	; len is arg2, idx and nlane in r10
168	call sha1_ni_x1
169	; state and idx are intact
170	jmp len_is_0
171
172	mb_processing:
173
174	vpand ymm2, ymm2, [rel clear_low_nibble]
175	vpshufd ymm2, ymm2, 0
176
177	vpsubd ymm0, ymm0, ymm2
178	vpsubd ymm1, ymm1, ymm2
179
180	vmovdqu [state + _lens + 0*32], ymm0
181	vmovdqu [state + _lens + 1*32], ymm1
182
183
184	; "state" and "args" are the same address, arg1
185	; len is arg2
186	call sha1_mb_x16_avx512
187	; state and idx are intact
188
189	len_is_0:
190	; process completed job "idx"
191	imul lane_data, idx, _LANE_DATA_size
192	lea lane_data, [state + _ldata + lane_data]
193
194	mov job_rax, [lane_data + _job_in_lane]
195	mov qword [lane_data + _job_in_lane], 0
196	mov dword [job_rax + _status], STS_COMPLETED
197	mov unused_lanes, [state + _unused_lanes]
198	shl unused_lanes, 4
199	or unused_lanes, idx
200	mov [state + _unused_lanes], unused_lanes
201
202	mov DWORD(num_lanes_inuse), [state + _num_lanes_inuse]
203	sub num_lanes_inuse, 1
204	mov [state + _num_lanes_inuse], DWORD(num_lanes_inuse)
205
206	vmovd xmm0, [state + _args_digest + 4idx + 064]
207	vpinsrd xmm0, [state + _args_digest + 4idx + 164], 1
208	vpinsrd xmm0, [state + _args_digest + 4idx + 264], 2
209	vpinsrd xmm0, [state + _args_digest + 4idx + 364], 3
210	mov DWORD(tmp2), [state + _args_digest + 4idx + 464]
211
212	vmovdqa [job_rax + _result_digest + 0*16], xmm0
213	mov [job_rax + _result_digest + 1*16], DWORD(tmp2)
214
215	return:
216
217	%ifidn __OUTPUT_FORMAT__, win64
218	vmovdqa xmm6, [rsp + _XMM_SAVE + 16*0]
219	vmovdqa xmm7, [rsp + _XMM_SAVE + 16*1]
220	vmovdqa xmm8, [rsp + _XMM_SAVE + 16*2]
221	vmovdqa xmm9, [rsp + _XMM_SAVE + 16*3]
222	vmovdqa xmm10, [rsp + _XMM_SAVE + 16*4]
223	vmovdqa xmm11, [rsp + _XMM_SAVE + 16*5]
224	vmovdqa xmm12, [rsp + _XMM_SAVE + 16*6]
225	vmovdqa xmm13, [rsp + _XMM_SAVE + 16*7]
226	vmovdqa xmm14, [rsp + _XMM_SAVE + 16*8]
227	vmovdqa xmm15, [rsp + _XMM_SAVE + 16*9]
228	mov rsi, [rsp + _GPR_SAVE + 8*1]
229	mov rdi, [rsp + _GPR_SAVE + 8*2]
230	%endif
231	mov rbx, [rsp + _GPR_SAVE + 8*0]
232	mov rbp, [rsp + _GPR_SAVE + 8*3]
233	mov r12, [rsp + _GPR_SAVE + 8*4]
234	mov r13, [rsp + _GPR_SAVE + 8*5]
235	mov r14, [rsp + _GPR_SAVE + 8*6]
236	mov r15, [rsp + _GPR_SAVE + 8*7]
237	add rsp, STACK_SPACE
238
239	ret
240
241	return_null:
242	xor job_rax, job_rax
243	jmp return
244
245	section .data align=16
246
247	align 16
248	clear_low_nibble:
249	dq 0x00000000FFFFFFF0, 0x0000000000000000
250	dq 0x00000000FFFFFFF0, 0x0000000000000000
251	lane_1: dq 1
252	lane_2: dq 2
253	lane_3: dq 3
254	lane_4: dq 4
255	lane_5: dq 5
256	lane_6: dq 6
257	lane_7: dq 7
258	lane_8: dq 8
259	lane_9: dq 9
260	lane_10: dq 10
261	lane_11: dq 11
262	lane_12: dq 12
263	lane_13: dq 13
264	lane_14: dq 14
265	lane_15: dq 15
266
267	%else
268	%ifidn __OUTPUT_FORMAT__, win64
269	global no_sha1_mb_mgr_flush_avx512_ni
270	no_sha1_mb_mgr_flush_avx512_ni:
271	%endif
272	%endif ; HAVE_AS_KNOWS_SHANI
273	%else
274	%ifidn __OUTPUT_FORMAT__, win64
275	global no_sha1_mb_mgr_flush_avx512_ni
276	no_sha1_mb_mgr_flush_avx512_ni:
277	%endif
278	%endif ; HAVE_AS_KNOWS_AVX512