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1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
2 | ; Copyright(c) 2011-2016 Intel Corporation All rights reserved. | |
3 | ; | |
4 | ; Redistribution and use in source and binary forms, with or without | |
1e59de90 | 5 | ; modification, are permitted provided that the following conditions |
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6 | ; are met: |
7 | ; * Redistributions of source code must retain the above copyright | |
8 | ; notice, this list of conditions and the following disclaimer. | |
9 | ; * Redistributions in binary form must reproduce the above copyright | |
10 | ; notice, this list of conditions and the following disclaimer in | |
11 | ; the documentation and/or other materials provided with the | |
12 | ; distribution. | |
13 | ; * Neither the name of Intel Corporation nor the names of its | |
14 | ; contributors may be used to endorse or promote products derived | |
15 | ; from this software without specific prior written permission. | |
16 | ; | |
17 | ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
18 | ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
19 | ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
20 | ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
21 | ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
22 | ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
23 | ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
24 | ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
25 | ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
26 | ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
27 | ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
28 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | |
29 | ||
30 | %include "sha512_job.asm" | |
31 | %include "sha512_mb_mgr_datastruct.asm" | |
32 | ||
33 | %include "reg_sizes.asm" | |
34 | ||
35 | extern sha512_mb_x2_avx | |
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36 | |
37 | [bits 64] | |
7c673cae | 38 | default rel |
1e59de90 | 39 | section .text |
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40 | |
41 | %ifidn __OUTPUT_FORMAT__, elf64 | |
42 | ; LINUX register definitions | |
43 | %define arg1 rdi ; rcx | |
44 | %define arg2 rsi ; rdx | |
45 | ||
46 | ; idx needs to be other than arg1, arg2, rbx, r12 | |
47 | %define idx rdx ; rsi | |
48 | %else | |
49 | ; WINDOWS register definitions | |
50 | %define arg1 rcx | |
51 | %define arg2 rdx | |
52 | ||
53 | ; idx needs to be other than arg1, arg2, rbx, r12 | |
54 | %define idx rsi | |
55 | %endif | |
56 | ||
57 | ; Common definitions | |
58 | %define state arg1 | |
59 | %define job arg2 | |
60 | %define len2 arg2 | |
61 | ||
62 | %define unused_lanes rbx | |
63 | %define lane_data rbx | |
64 | %define tmp2 rbx | |
1e59de90 | 65 | |
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66 | %define job_rax rax |
67 | %define tmp1 rax | |
68 | %define size_offset rax | |
69 | %define tmp rax | |
70 | %define start_offset rax | |
1e59de90 | 71 | |
7c673cae | 72 | %define tmp3 arg1 |
1e59de90 | 73 | |
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74 | %define extra_blocks arg2 |
75 | %define p arg2 | |
76 | ||
77 | %define tmp4 r8 | |
78 | %define lens0 r8 | |
79 | ||
80 | %define lens1 r9 | |
81 | %define lens2 r10 | |
82 | %define lens3 r11 | |
83 | ||
84 | ; STACK_SPACE needs to be an odd multiple of 8 | |
85 | _XMM_SAVE_SIZE equ 10*16 | |
86 | _GPR_SAVE_SIZE equ 8*3 | |
87 | _ALIGN_SIZE equ 0 | |
88 | ||
89 | _XMM_SAVE equ 0 | |
90 | _GPR_SAVE equ _XMM_SAVE + _XMM_SAVE_SIZE | |
91 | STACK_SPACE equ _GPR_SAVE + _GPR_SAVE_SIZE + _ALIGN_SIZE | |
92 | ||
93 | %define APPEND(a,b) a %+ b | |
94 | ||
95 | ; SHA512_JOB* sha512_mb_mgr_flush_avx(SHA512_MB_JOB_MGR *state) | |
96 | ; arg 1 : rcx : state | |
1e59de90 | 97 | mk_global sha512_mb_mgr_flush_avx, function |
7c673cae | 98 | sha512_mb_mgr_flush_avx: |
1e59de90 | 99 | endbranch |
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100 | |
101 | sub rsp, STACK_SPACE | |
102 | mov [rsp + _GPR_SAVE + 8*0], rbx | |
103 | mov [rsp + _GPR_SAVE + 8*1], r12 | |
104 | %ifidn __OUTPUT_FORMAT__, win64 | |
105 | mov [rsp + _GPR_SAVE + 8*2], rsi | |
106 | vmovdqa [rsp + _XMM_SAVE + 16*0], xmm6 | |
107 | vmovdqa [rsp + _XMM_SAVE + 16*1], xmm7 | |
108 | vmovdqa [rsp + _XMM_SAVE + 16*2], xmm8 | |
109 | vmovdqa [rsp + _XMM_SAVE + 16*3], xmm9 | |
110 | vmovdqa [rsp + _XMM_SAVE + 16*4], xmm10 | |
111 | vmovdqa [rsp + _XMM_SAVE + 16*5], xmm11 | |
112 | vmovdqa [rsp + _XMM_SAVE + 16*6], xmm12 | |
113 | vmovdqa [rsp + _XMM_SAVE + 16*7], xmm13 | |
114 | vmovdqa [rsp + _XMM_SAVE + 16*8], xmm14 | |
115 | vmovdqa [rsp + _XMM_SAVE + 16*9], xmm15 | |
116 | %endif | |
117 | ||
118 | mov unused_lanes, [state + _unused_lanes] | |
119 | bt unused_lanes, 16+7 | |
120 | jc return_null | |
121 | ||
122 | ; find a lane with a non-null job | |
123 | xor idx, idx | |
124 | cmp qword [state + _ldata + 1 * _LANE_DATA_size + _job_in_lane], 0 | |
125 | cmovne idx, [one] | |
126 | ||
127 | ; copy idx to empty lanes | |
128 | copy_lane_data: | |
129 | mov tmp, [state + _args + _data_ptr + 8*idx] | |
130 | ||
131 | %assign I 0 | |
132 | %rep 2 | |
133 | cmp qword [state + _ldata + I * _LANE_DATA_size + _job_in_lane], 0 | |
134 | jne APPEND(skip_,I) | |
135 | mov [state + _args + _data_ptr + 8*I], tmp | |
136 | mov dword [state + _lens + 4 + 8*I], 0xFFFFFFFF | |
137 | APPEND(skip_,I): | |
138 | %assign I (I+1) | |
139 | %endrep | |
140 | ||
141 | ; Find min length | |
142 | mov lens0, [state + _lens + 0*8] | |
143 | mov idx, lens0 | |
144 | mov lens1, [state + _lens + 1*8] | |
145 | cmp lens1, idx | |
146 | cmovb idx, lens1 | |
147 | ||
148 | mov len2, idx | |
149 | and idx, 0xF | |
150 | and len2, ~0xFF | |
1e59de90 | 151 | jz len_is_0 |
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152 | |
153 | sub lens0, len2 | |
154 | sub lens1, len2 | |
155 | shr len2, 32 | |
156 | mov [state + _lens + 0*8], lens0 | |
157 | mov [state + _lens + 1*8], lens1 | |
158 | ||
159 | ; "state" and "args" are the same address, arg1 | |
160 | ; len is arg2 | |
161 | call sha512_mb_x2_avx | |
162 | ; state and idx are intact | |
163 | ||
164 | len_is_0: | |
165 | ; process completed job "idx" | |
166 | imul lane_data, idx, _LANE_DATA_size | |
167 | lea lane_data, [state + _ldata + lane_data] | |
168 | ||
169 | mov job_rax, [lane_data + _job_in_lane] | |
170 | mov qword [lane_data + _job_in_lane], 0 | |
171 | mov dword [job_rax + _status], STS_COMPLETED | |
172 | mov unused_lanes, [state + _unused_lanes] | |
173 | shl unused_lanes, 8 | |
174 | or unused_lanes, idx | |
175 | mov [state + _unused_lanes], unused_lanes | |
176 | ||
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177 | sub dword [state + _num_lanes_inuse], 1 |
178 | ||
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179 | vmovq xmm0, [state + _args_digest + 8*idx + 0*32] |
180 | vpinsrq xmm0, [state + _args_digest + 8*idx + 1*32], 1 | |
181 | vmovq xmm1, [state + _args_digest + 8*idx + 2*32] | |
182 | vpinsrq xmm1, [state + _args_digest + 8*idx + 3*32], 1 | |
183 | vmovq xmm2, [state + _args_digest + 8*idx + 4*32] | |
184 | vpinsrq xmm2, [state + _args_digest + 8*idx + 5*32], 1 | |
185 | vmovq xmm3, [state + _args_digest + 8*idx + 6*32] | |
186 | vpinsrq xmm3, [state + _args_digest + 8*idx + 7*32], 1 | |
187 | ||
188 | vmovdqa [job_rax + _result_digest + 0*16], xmm0 | |
189 | vmovdqa [job_rax + _result_digest + 1*16], xmm1 | |
190 | vmovdqa [job_rax + _result_digest + 2*16], xmm2 | |
191 | vmovdqa [job_rax + _result_digest + 3*16], xmm3 | |
192 | ||
193 | return: | |
194 | ||
195 | %ifidn __OUTPUT_FORMAT__, win64 | |
196 | vmovdqa xmm6, [rsp + _XMM_SAVE + 16*0] | |
197 | vmovdqa xmm7, [rsp + _XMM_SAVE + 16*1] | |
198 | vmovdqa xmm8, [rsp + _XMM_SAVE + 16*2] | |
199 | vmovdqa xmm9, [rsp + _XMM_SAVE + 16*3] | |
200 | vmovdqa xmm10, [rsp + _XMM_SAVE + 16*4] | |
201 | vmovdqa xmm11, [rsp + _XMM_SAVE + 16*5] | |
202 | vmovdqa xmm12, [rsp + _XMM_SAVE + 16*6] | |
203 | vmovdqa xmm13, [rsp + _XMM_SAVE + 16*7] | |
204 | vmovdqa xmm14, [rsp + _XMM_SAVE + 16*8] | |
205 | vmovdqa xmm15, [rsp + _XMM_SAVE + 16*9] | |
206 | mov rsi, [rsp + _GPR_SAVE + 8*2] | |
207 | %endif | |
208 | mov rbx, [rsp + _GPR_SAVE + 8*0] | |
209 | mov r12, [rsp + _GPR_SAVE + 8*1] | |
210 | add rsp, STACK_SPACE | |
211 | ||
212 | ret | |
213 | ||
214 | return_null: | |
215 | xor job_rax, job_rax | |
216 | jmp return | |
1e59de90 | 217 | |
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218 | section .data align=16 |
219 | ||
220 | align 16 | |
221 | one: dq 1 | |
222 | two: dq 2 | |
223 | three: dq 3 | |
224 |