[ceph.git] / ceph / src / crypto / isa-l / isa-l_crypto / sha512_mb / sha512_mb_mgr_submit_sse.asm

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;  Copyright(c) 2011-2016 Intel Corporation All rights reserved.
;
;  Redistribution and use in source and binary forms, with or without
;  modification, are permitted provided that the following conditions
;  are met:
;    * Redistributions of source code must retain the above copyright
;      notice, this list of conditions and the following disclaimer.
;    * Redistributions in binary form must reproduce the above copyright
;      notice, this list of conditions and the following disclaimer in
;      the documentation and/or other materials provided with the
;      distribution.
;    * Neither the name of Intel Corporation nor the names of its
;      contributors may be used to endorse or promote products derived
;      from this software without specific prior written permission.
;
;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
;  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
;  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
;  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
;  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
;  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
;  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
;  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
;  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
;  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

%include "sha512_job.asm"
%include "sha512_mb_mgr_datastruct.asm"

%include "reg_sizes.asm"

extern sha512_mb_x2_sse

%ifidn __OUTPUT_FORMAT__, elf64
; Linux register definitions
%define arg1    rdi ; rcx
%define arg2    rsi ; rdx

; idx needs to be other than arg1, arg2, rbx, r12
%define idx             rdx ; rsi
%define last_len        rdx ; rsi

%define size_offset     rcx ; rdi
%define tmp2            rcx ; rdi

%else
; WINDOWS register definitions
%define arg1    rcx
%define arg2    rdx

; idx needs to be other than arg1, arg2, rbx, r12
%define last_len        rsi
%define idx             rsi

%define size_offset     rdi
%define tmp2            rdi

%endif

; Common definitions
%define state   arg1
%define job     arg2
%define len2    arg2
%define p2      arg2

%define p               r11
%define start_offset    r11

%define unused_lanes    rbx

%define job_rax         rax
%define len             rax

%define lane            rbp
%define tmp3            rbp
%define lens3           rbp

%define extra_blocks    r8
%define lens0           r8

%define tmp             r9
%define lens1           r9

%define lane_data       r10
%define lens2           r10

struc stack_frame
	.xmm: resb 16*10
	.gpr: resb 8*5
	.rsp: resb 8
endstruc

; STACK_SPACE needs to be an odd multiple of 8
%define _XMM_SAVE       stack_frame.gpr
%define _GPR_SAVE       stack_frame.rsp
%define STACK_SPACE     stack_frame_size

; SHA512_JOB* sha512_mb_mgr_submit_sse(SHA512_MB_JOB_MGR *state, SHA256_JOB *job)
; arg 1 : rcx : state
; arg 2 : rdx : job
mk_global sha512_mb_mgr_submit_sse, function
sha512_mb_mgr_submit_sse:
	endbranch

	mov	rax, rsp

	sub     rsp, STACK_SPACE
	and	rsp, ~31

	mov	[rsp + stack_frame.rsp], rax

	mov     [rsp + _XMM_SAVE + 8*0], rbx
	mov     [rsp + _XMM_SAVE + 8*1], rbp
	mov     [rsp + _XMM_SAVE + 8*2], r12
%ifidn __OUTPUT_FORMAT__, win64
	mov     [rsp + _XMM_SAVE + 8*3], rsi
	mov     [rsp + _XMM_SAVE + 8*4], rdi
	movdqa  [rsp + 16*0], xmm6
	movdqa  [rsp + 16*1], xmm7
	movdqa  [rsp + 16*2], xmm8
	movdqa  [rsp + 16*3], xmm9
	movdqa  [rsp + 16*4], xmm10
	movdqa  [rsp + 16*5], xmm11
	movdqa  [rsp + 16*6], xmm12
	movdqa  [rsp + 16*7], xmm13
	movdqa  [rsp + 16*8], xmm14
	movdqa  [rsp + 16*9], xmm15
%endif

	mov     unused_lanes, [state + _unused_lanes]
	movzx   lane, BYTE(unused_lanes)
	shr     unused_lanes, 8
	imul    lane_data, lane, _LANE_DATA_size
	mov     dword [job + _status], STS_BEING_PROCESSED
	lea     lane_data, [state + _ldata + lane_data]
	mov     [state + _unused_lanes], unused_lanes
	mov     DWORD(len), [job + _len]

	mov     [lane_data + _job_in_lane], job
	mov     [state + _lens + 4 + 8*lane], DWORD(len)

	; Load digest words from result_digest
	movdqa	xmm0, [job + _result_digest + 0*16]
	movdqa	xmm1, [job + _result_digest + 1*16]
	movdqa	xmm2, [job + _result_digest + 2*16]
	movdqa	xmm3, [job + _result_digest + 3*16]
	movq    [state + _args_digest + 8*lane + 0*32], xmm0
	pextrq  [state + _args_digest + 8*lane + 1*32], xmm0, 1
	movq    [state + _args_digest + 8*lane + 2*32], xmm1
	pextrq  [state + _args_digest + 8*lane + 3*32], xmm1, 1
	movq    [state + _args_digest + 8*lane + 4*32], xmm2
	pextrq  [state + _args_digest + 8*lane + 5*32], xmm2, 1
	movq    [state + _args_digest + 8*lane + 6*32], xmm3
	pextrq  [state + _args_digest + 8*lane + 7*32], xmm3, 1

	mov     p, [job + _buffer]
	mov     [state + _args_data_ptr + 8*lane], p

	add     dword [state + _num_lanes_inuse], 1
	cmp     unused_lanes, 0xff
	jne     return_null

start_loop:

	; Find min length
	mov     lens0, [state + _lens + 0*8]
	mov     idx, lens0
	mov     lens1, [state + _lens + 1*8]
	cmp     lens1, idx
	cmovb   idx, lens1

	mov     len2, idx
	and     idx, 0xF
	and     len2, ~0xFF
	jz      len_is_0

	sub     lens0, len2
	sub     lens1, len2
	shr     len2, 32
	mov     [state + _lens + 0*8], lens0
	mov     [state + _lens + 1*8], lens1

	; "state" and "args" are the same address, arg1
	; len is arg2
	call    sha512_mb_x2_sse
	; state and idx are intact

len_is_0:

	; process completed job "idx"
	imul    lane_data, idx, _LANE_DATA_size
	lea     lane_data, [state + _ldata + lane_data]

	mov     job_rax, [lane_data + _job_in_lane]

	mov     unused_lanes, [state + _unused_lanes]
	mov     qword [lane_data + _job_in_lane], 0
	mov     dword [job_rax + _status], STS_COMPLETED
	shl     unused_lanes, 8
	or      unused_lanes, idx
	mov     [state + _unused_lanes], unused_lanes

	sub     dword [state + _num_lanes_inuse], 1

	movq    xmm0, [state + _args_digest + 8*idx + 0*32]
	pinsrq  xmm0, [state + _args_digest + 8*idx + 1*32], 1
	movq    xmm1, [state + _args_digest + 8*idx + 2*32]
	pinsrq  xmm1, [state + _args_digest + 8*idx + 3*32], 1
	movq    xmm2, [state + _args_digest + 8*idx + 4*32]
	pinsrq  xmm2, [state + _args_digest + 8*idx + 5*32], 1
	movq    xmm3, [state + _args_digest + 8*idx + 6*32]
	pinsrq  xmm3, [state + _args_digest + 8*idx + 7*32], 1

	movdqa  [job_rax + _result_digest + 0*16], xmm0
	movdqa  [job_rax + _result_digest + 1*16], xmm1
	movdqa  [job_rax + _result_digest + 2*16], xmm2
	movdqa  [job_rax + _result_digest + 3*16], xmm3

return:

%ifidn __OUTPUT_FORMAT__, win64
	movdqa  xmm6,  [rsp + 16*0]
	movdqa  xmm7,  [rsp + 16*1]
	movdqa  xmm8,  [rsp + 16*2]
	movdqa  xmm9,  [rsp + 16*3]
	movdqa  xmm10, [rsp + 16*4]
	movdqa  xmm11, [rsp + 16*5]
	movdqa  xmm12, [rsp + 16*6]
	movdqa  xmm13, [rsp + 16*7]
	movdqa  xmm14, [rsp + 16*8]
	movdqa  xmm15, [rsp + 16*9]
	mov     rsi, [rsp + _XMM_SAVE + 8*3]
	mov     rdi, [rsp + _XMM_SAVE + 8*4]
%endif
	mov     rbx, [rsp + _XMM_SAVE + 8*0]
	mov     rbp, [rsp + _XMM_SAVE + 8*1]
	mov     r12, [rsp + _XMM_SAVE + 8*2]
	mov	rsp, [rsp + stack_frame.rsp]

	ret

return_null:
	xor     job_rax, job_rax
	jmp     return

section .data align=16

align 16
H0:     dd  0x6a09e667
H1:     dd  0xbb67ae85
H2:     dd  0x3c6ef372
H3:     dd  0xa54ff53a
H4:     dd  0x510e527f
H5:     dd  0x9b05688c
H6:     dd  0x1f83d9ab
H7:     dd  0x5be0cd19
Commit	Line	Data
7c673cae FG	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	2	; Copyright(c) 2011-2016 Intel Corporation All rights reserved.
	3	;
	4	; Redistribution and use in source and binary forms, with or without
1e59de90	5	; modification, are permitted provided that the following conditions
7c673cae FG	6	; are met:
	7	; * Redistributions of source code must retain the above copyright
	8	; notice, this list of conditions and the following disclaimer.
	9	; * Redistributions in binary form must reproduce the above copyright
	10	; notice, this list of conditions and the following disclaimer in
	11	; the documentation and/or other materials provided with the
	12	; distribution.
	13	; * Neither the name of Intel Corporation nor the names of its
	14	; contributors may be used to endorse or promote products derived
	15	; from this software without specific prior written permission.
	16	;
	17	; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	18	; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	19	; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	20	; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	21	; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	22	; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	23	; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	24	; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	25	; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	26	; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	27	; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	28	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	29
	30	%include "sha512_job.asm"
	31	%include "sha512_mb_mgr_datastruct.asm"
	32
	33	%include "reg_sizes.asm"
	34
	35	extern sha512_mb_x2_sse
	36
	37	%ifidn __OUTPUT_FORMAT__, elf64
	38	; Linux register definitions
	39	%define arg1 rdi ; rcx
	40	%define arg2 rsi ; rdx
	41
	42	; idx needs to be other than arg1, arg2, rbx, r12
	43	%define idx rdx ; rsi
	44	%define last_len rdx ; rsi
1e59de90	45
7c673cae FG	46	%define size_offset rcx ; rdi
	47	%define tmp2 rcx ; rdi
	48
	49	%else
	50	; WINDOWS register definitions
	51	%define arg1 rcx
	52	%define arg2 rdx
	53
	54	; idx needs to be other than arg1, arg2, rbx, r12
	55	%define last_len rsi
	56	%define idx rsi
1e59de90	57
7c673cae FG	58	%define size_offset rdi
7c673cae FG	59	%define tmp2 rdi
1e59de90	60
7c673cae FG	61	%endif
	62
	63	; Common definitions
	64	%define state arg1
	65	%define job arg2
	66	%define len2 arg2
	67	%define p2 arg2
	68
	69	%define p r11
	70	%define start_offset r11
	71
	72	%define unused_lanes rbx
1e59de90	73
7c673cae FG	74	%define job_rax rax
	75	%define len rax
	76
	77	%define lane rbp
	78	%define tmp3 rbp
	79	%define lens3 rbp
1e59de90	80
7c673cae FG	81	%define extra_blocks r8
7c673cae FG	82	%define lens0 r8
1e59de90	83
7c673cae FG	84	%define tmp r9
7c673cae FG	85	%define lens1 r9
1e59de90	86
7c673cae FG	87	%define lane_data r10
	88	%define lens2 r10
	89
1e59de90	90	struc stack_frame
7c673cae FG	91	.xmm: resb 16*10
	92	.gpr: resb 8*5
	93	.rsp: resb 8
	94	endstruc
	95
	96	; STACK_SPACE needs to be an odd multiple of 8
	97	%define _XMM_SAVE stack_frame.gpr
	98	%define _GPR_SAVE stack_frame.rsp
	99	%define STACK_SPACE stack_frame_size
	100
	101	; SHA512_JOB* sha512_mb_mgr_submit_sse(SHA512_MB_JOB_MGR state, SHA256_JOB job)
	102	; arg 1 : rcx : state
	103	; arg 2 : rdx : job
1e59de90	104	mk_global sha512_mb_mgr_submit_sse, function
7c673cae	105	sha512_mb_mgr_submit_sse:
1e59de90	106	endbranch
7c673cae FG	107
7c673cae FG	108	mov rax, rsp
1e59de90	109
7c673cae FG	110	sub rsp, STACK_SPACE
	111	and rsp, ~31
	112
	113	mov [rsp + stack_frame.rsp], rax
	114
	115	mov [rsp + _XMM_SAVE + 8*0], rbx
	116	mov [rsp + _XMM_SAVE + 8*1], rbp
	117	mov [rsp + _XMM_SAVE + 8*2], r12
	118	%ifidn __OUTPUT_FORMAT__, win64
	119	mov [rsp + _XMM_SAVE + 8*3], rsi
	120	mov [rsp + _XMM_SAVE + 8*4], rdi
	121	movdqa [rsp + 16*0], xmm6
	122	movdqa [rsp + 16*1], xmm7
	123	movdqa [rsp + 16*2], xmm8
	124	movdqa [rsp + 16*3], xmm9
	125	movdqa [rsp + 16*4], xmm10
	126	movdqa [rsp + 16*5], xmm11
	127	movdqa [rsp + 16*6], xmm12
	128	movdqa [rsp + 16*7], xmm13
	129	movdqa [rsp + 16*8], xmm14
	130	movdqa [rsp + 16*9], xmm15
	131	%endif
	132
	133	mov unused_lanes, [state + _unused_lanes]
	134	movzx lane, BYTE(unused_lanes)
	135	shr unused_lanes, 8
	136	imul lane_data, lane, _LANE_DATA_size
	137	mov dword [job + _status], STS_BEING_PROCESSED
	138	lea lane_data, [state + _ldata + lane_data]
	139	mov [state + _unused_lanes], unused_lanes
	140	mov DWORD(len), [job + _len]
	141
	142	mov [lane_data + _job_in_lane], job
	143	mov [state + _lens + 4 + 8*lane], DWORD(len)
	144
	145	; Load digest words from result_digest
	146	movdqa xmm0, [job + _result_digest + 0*16]
	147	movdqa xmm1, [job + _result_digest + 1*16]
	148	movdqa xmm2, [job + _result_digest + 2*16]
	149	movdqa xmm3, [job + _result_digest + 3*16]
	150	movq [state + _args_digest + 8lane + 032], xmm0
	151	pextrq [state + _args_digest + 8lane + 132], xmm0, 1
	152	movq [state + _args_digest + 8lane + 232], xmm1
	153	pextrq [state + _args_digest + 8lane + 332], xmm1, 1
	154	movq [state + _args_digest + 8lane + 432], xmm2
	155	pextrq [state + _args_digest + 8lane + 532], xmm2, 1
	156	movq [state + _args_digest + 8lane + 632], xmm3
	157	pextrq [state + _args_digest + 8lane + 732], xmm3, 1
	158
	159	mov p, [job + _buffer]
	160	mov [state + _args_data_ptr + 8*lane], p
	161
1e59de90	162	add dword [state + _num_lanes_inuse], 1
7c673cae FG	163	cmp unused_lanes, 0xff
	164	jne return_null
	165
	166	start_loop:
	167
	168	; Find min length
	169	mov lens0, [state + _lens + 0*8]
	170	mov idx, lens0
	171	mov lens1, [state + _lens + 1*8]
	172	cmp lens1, idx
	173	cmovb idx, lens1
1e59de90	174
7c673cae FG	175	mov len2, idx
	176	and idx, 0xF
	177	and len2, ~0xFF
	178	jz len_is_0
	179
	180	sub lens0, len2
	181	sub lens1, len2
	182	shr len2, 32
	183	mov [state + _lens + 0*8], lens0
	184	mov [state + _lens + 1*8], lens1
	185
	186	; "state" and "args" are the same address, arg1
	187	; len is arg2
	188	call sha512_mb_x2_sse
	189	; state and idx are intact
	190
	191	len_is_0:
	192
	193	; process completed job "idx"
	194	imul lane_data, idx, _LANE_DATA_size
	195	lea lane_data, [state + _ldata + lane_data]
1e59de90	196
7c673cae FG	197	mov job_rax, [lane_data + _job_in_lane]
	198
	199	mov unused_lanes, [state + _unused_lanes]
	200	mov qword [lane_data + _job_in_lane], 0
	201	mov dword [job_rax + _status], STS_COMPLETED
	202	shl unused_lanes, 8
	203	or unused_lanes, idx
	204	mov [state + _unused_lanes], unused_lanes
	205
1e59de90 TL	206	sub dword [state + _num_lanes_inuse], 1
1e59de90 TL	207
7c673cae FG	208	movq xmm0, [state + _args_digest + 8idx + 032]
	209	pinsrq xmm0, [state + _args_digest + 8idx + 132], 1
	210	movq xmm1, [state + _args_digest + 8idx + 232]
	211	pinsrq xmm1, [state + _args_digest + 8idx + 332], 1
	212	movq xmm2, [state + _args_digest + 8idx + 432]
	213	pinsrq xmm2, [state + _args_digest + 8idx + 532], 1
	214	movq xmm3, [state + _args_digest + 8idx + 632]
	215	pinsrq xmm3, [state + _args_digest + 8idx + 732], 1
	216
	217	movdqa [job_rax + _result_digest + 0*16], xmm0
	218	movdqa [job_rax + _result_digest + 1*16], xmm1
	219	movdqa [job_rax + _result_digest + 2*16], xmm2
	220	movdqa [job_rax + _result_digest + 3*16], xmm3
	221
	222	return:
	223
	224	%ifidn __OUTPUT_FORMAT__, win64
	225	movdqa xmm6, [rsp + 16*0]
	226	movdqa xmm7, [rsp + 16*1]
	227	movdqa xmm8, [rsp + 16*2]
	228	movdqa xmm9, [rsp + 16*3]
	229	movdqa xmm10, [rsp + 16*4]
	230	movdqa xmm11, [rsp + 16*5]
	231	movdqa xmm12, [rsp + 16*6]
	232	movdqa xmm13, [rsp + 16*7]
	233	movdqa xmm14, [rsp + 16*8]
	234	movdqa xmm15, [rsp + 16*9]
	235	mov rsi, [rsp + _XMM_SAVE + 8*3]
	236	mov rdi, [rsp + _XMM_SAVE + 8*4]
	237	%endif
	238	mov rbx, [rsp + _XMM_SAVE + 8*0]
	239	mov rbp, [rsp + _XMM_SAVE + 8*1]
	240	mov r12, [rsp + _XMM_SAVE + 8*2]
	241	mov rsp, [rsp + stack_frame.rsp]
	242
	243	ret
	244
	245	return_null:
	246	xor job_rax, job_rax
	247	jmp return
	248
	249	section .data align=16
	250
	251	align 16
	252	H0: dd 0x6a09e667
	253	H1: dd 0xbb67ae85
	254	H2: dd 0x3c6ef372
	255	H3: dd 0xa54ff53a
	256	H4: dd 0x510e527f
	257	H5: dd 0x9b05688c
	258	H6: dd 0x1f83d9ab
	259	H7: dd 0x5be0cd19
	260