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1 | .. BSD LICENSE |
2 | Copyright(c) 2010-2014 Intel Corporation. All rights reserved. | |
3 | All rights reserved. | |
4 | ||
5 | Redistribution and use in source and binary forms, with or without | |
6 | modification, are permitted provided that the following conditions | |
7 | are met: | |
8 | ||
9 | * Redistributions of source code must retain the above copyright | |
10 | notice, this list of conditions and the following disclaimer. | |
11 | * Redistributions in binary form must reproduce the above copyright | |
12 | notice, this list of conditions and the following disclaimer in | |
13 | the documentation and/or other materials provided with the | |
14 | distribution. | |
15 | * Neither the name of Intel Corporation nor the names of its | |
16 | contributors may be used to endorse or promote products derived | |
17 | from this software without specific prior written permission. | |
18 | ||
19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
20 | "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
21 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
22 | A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
23 | OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
24 | SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
25 | LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
26 | DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
27 | THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
28 | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
29 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
30 | ||
31 | Profile Your Application | |
32 | ======================== | |
33 | ||
34 | The following sections describe methods of profiling DPDK applications on | |
35 | different architectures. | |
36 | ||
37 | ||
38 | Profiling on x86 | |
39 | ---------------- | |
40 | ||
41 | Intel processors provide performance counters to monitor events. | |
42 | Some tools provided by Intel, such as VTune, can be used to profile and benchmark an application. | |
43 | See the *VTune Performance Analyzer Essentials* publication from Intel Press for more information. | |
44 | ||
45 | For a DPDK application, this can be done in a Linux* application environment only. | |
46 | ||
47 | The main situations that should be monitored through event counters are: | |
48 | ||
49 | * Cache misses | |
50 | ||
51 | * Branch mis-predicts | |
52 | ||
53 | * DTLB misses | |
54 | ||
55 | * Long latency instructions and exceptions | |
56 | ||
57 | Refer to the | |
58 | `Intel Performance Analysis Guide <http://software.intel.com/sites/products/collateral/hpc/vtune/performance_analysis_guide.pdf>`_ | |
59 | for details about application profiling. | |
60 | ||
61 | ||
62 | Profiling on ARM64 | |
63 | ------------------ | |
64 | ||
65 | Using Linux perf | |
66 | ~~~~~~~~~~~~~~~~ | |
67 | ||
68 | The ARM64 architecture provide performance counters to monitor events. The | |
69 | Linux ``perf`` tool can be used to profile and benchmark an application. In | |
70 | addition to the standard events, ``perf`` can be used to profile arm64 | |
71 | specific PMU (Performance Monitor Unit) events through raw events (``-e`` | |
72 | ``-rXX``). | |
73 | ||
74 | For more derails refer to the | |
75 | `ARM64 specific PMU events enumeration <http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100095_0002_04_en/way1382543438508.html>`_. | |
76 | ||
77 | ||
78 | High-resolution cycle counter | |
79 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
80 | ||
81 | The default ``cntvct_el0`` based ``rte_rdtsc()`` provides a portable means to | |
82 | get a wall clock counter in user space. Typically it runs at <= 100MHz. | |
83 | ||
84 | The alternative method to enable ``rte_rdtsc()`` for a high resolution wall | |
85 | clock counter is through the armv8 PMU subsystem. The PMU cycle counter runs | |
86 | at CPU frequency. However, access to the PMU cycle counter from user space is | |
87 | not enabled by default in the arm64 linux kernel. It is possible to enable | |
88 | cycle counter for user space access by configuring the PMU from the privileged | |
89 | mode (kernel space). | |
90 | ||
91 | By default the ``rte_rdtsc()`` implementation uses a portable ``cntvct_el0`` | |
92 | scheme. Application can choose the PMU based implementation with | |
93 | ``CONFIG_RTE_ARM_EAL_RDTSC_USE_PMU``. | |
94 | ||
95 | The example below shows the steps to configure the PMU based cycle counter on | |
96 | an armv8 machine. | |
97 | ||
98 | .. code-block:: console | |
99 | ||
100 | git clone https://github.com/jerinjacobk/armv8_pmu_cycle_counter_el0 | |
101 | cd armv8_pmu_cycle_counter_el0 | |
102 | make | |
103 | sudo insmod pmu_el0_cycle_counter.ko | |
104 | cd $DPDK_DIR | |
105 | make config T=arm64-armv8a-linuxapp-gcc | |
106 | echo "CONFIG_RTE_ARM_EAL_RDTSC_USE_PMU=y" >> build/.config | |
107 | make | |
108 | ||
109 | .. warning:: | |
110 | ||
111 | The PMU based scheme is useful for high accuracy performance profiling with | |
112 | ``rte_rdtsc()``. However, this method can not be used in conjunction with | |
113 | Linux userspace profiling tools like ``perf`` as this scheme alters the PMU | |
114 | registers state. |