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bump version to 12.2.12-pve1
[ceph.git] / ceph / src / dpdk / drivers / net / bnx2x / ecore_mfw_req.h
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1/*-
2 * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.
3 *
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
7 *
8 * Copyright (c) 2014-2015 QLogic Corporation.
9 * All rights reserved.
10 * www.qlogic.com
11 *
12 * See LICENSE.bnx2x_pmd for copyright and licensing details.
13 */
14
15#ifndef ECORE_MFW_REQ_H
16#define ECORE_MFW_REQ_H
17
18
19
20#define PORT_0 0
21#define PORT_1 1
22#define PORT_MAX 2
23#define NVM_PATH_MAX 2
24
25/* FCoE capabilities required from the driver */
26struct fcoe_capabilities {
27 uint32_t capability1;
28 /* Maximum number of I/Os per connection */
29 #define FCOE_IOS_PER_CONNECTION_MASK 0x0000ffff
30 #define FCOE_IOS_PER_CONNECTION_SHIFT 0
31 /* Maximum number of Logins per port */
32 #define FCOE_LOGINS_PER_PORT_MASK 0xffff0000
33 #define FCOE_LOGINS_PER_PORT_SHIFT 16
34
35 uint32_t capability2;
36 /* Maximum number of exchanges */
37 #define FCOE_NUMBER_OF_EXCHANGES_MASK 0x0000ffff
38 #define FCOE_NUMBER_OF_EXCHANGES_SHIFT 0
39 /* Maximum NPIV WWN per port */
40 #define FCOE_NPIV_WWN_PER_PORT_MASK 0xffff0000
41 #define FCOE_NPIV_WWN_PER_PORT_SHIFT 16
42
43 uint32_t capability3;
44 /* Maximum number of targets supported */
45 #define FCOE_TARGETS_SUPPORTED_MASK 0x0000ffff
46 #define FCOE_TARGETS_SUPPORTED_SHIFT 0
47 /* Maximum number of outstanding commands across all connections */
48 #define FCOE_OUTSTANDING_COMMANDS_MASK 0xffff0000
49 #define FCOE_OUTSTANDING_COMMANDS_SHIFT 16
50
51 uint32_t capability4;
52 #define FCOE_CAPABILITY4_STATEFUL 0x00000001
53 #define FCOE_CAPABILITY4_STATELESS 0x00000002
54 #define FCOE_CAPABILITY4_CAPABILITIES_REPORTED_VALID 0x00000004
55};
56
57struct glob_ncsi_oem_data
58{
59 uint32_t driver_version;
60 uint32_t unused[3];
61 struct fcoe_capabilities fcoe_features[NVM_PATH_MAX][PORT_MAX];
62};
63
64/* current drv_info version */
65#define DRV_INFO_CUR_VER 2
66
67/* drv_info op codes supported */
68enum drv_info_opcode {
69 ETH_STATS_OPCODE,
70 FCOE_STATS_OPCODE,
71 ISCSI_STATS_OPCODE
72};
73
74#define ETH_STAT_INFO_VERSION_LEN 12
75/* Per PCI Function Ethernet Statistics required from the driver */
76struct eth_stats_info {
77 /* Function's Driver Version. padded to 12 */
78 char version[ETH_STAT_INFO_VERSION_LEN];
79 /* Locally Admin Addr. BigEndian EIU48. Actual size is 6 bytes */
80 uint8_t mac_local[8];
81 uint8_t mac_add1[8]; /* Additional Programmed MAC Addr 1. */
82 uint8_t mac_add2[8]; /* Additional Programmed MAC Addr 2. */
83 uint32_t mtu_size; /* MTU Size. Note : Negotiated MTU */
84 uint32_t feature_flags; /* Feature_Flags. */
85#define FEATURE_ETH_CHKSUM_OFFLOAD_MASK 0x01
86#define FEATURE_ETH_LSO_MASK 0x02
87#define FEATURE_ETH_BOOTMODE_MASK 0x1C
88#define FEATURE_ETH_BOOTMODE_SHIFT 2
89#define FEATURE_ETH_BOOTMODE_NONE (0x0 << 2)
90#define FEATURE_ETH_BOOTMODE_PXE (0x1 << 2)
91#define FEATURE_ETH_BOOTMODE_ISCSI (0x2 << 2)
92#define FEATURE_ETH_BOOTMODE_FCOE (0x3 << 2)
93#define FEATURE_ETH_TOE_MASK 0x20
94 uint32_t lso_max_size; /* LSO MaxOffloadSize. */
95 uint32_t lso_min_seg_cnt; /* LSO MinSegmentCount. */
96 /* Num Offloaded Connections TCP_IPv4. */
97 uint32_t ipv4_ofld_cnt;
98 /* Num Offloaded Connections TCP_IPv6. */
99 uint32_t ipv6_ofld_cnt;
100 uint32_t promiscuous_mode; /* Promiscuous Mode. non-zero true */
101 uint32_t txq_size; /* TX Descriptors Queue Size */
102 uint32_t rxq_size; /* RX Descriptors Queue Size */
103 /* TX Descriptor Queue Avg Depth. % Avg Queue Depth since last poll */
104 uint32_t txq_avg_depth;
105 /* RX Descriptors Queue Avg Depth. % Avg Queue Depth since last poll */
106 uint32_t rxq_avg_depth;
107 /* IOV_Offload. 0=none; 1=MultiQueue, 2=VEB 3= VEPA*/
108 uint32_t iov_offload;
109 /* Number of NetQueue/VMQ Config'd. */
110 uint32_t netq_cnt;
111 uint32_t vf_cnt; /* Num VF assigned to this PF. */
112};
113
114/* Per PCI Function FCOE Statistics required from the driver */
115struct fcoe_stats_info {
116 uint8_t version[12]; /* Function's Driver Version. */
117 uint8_t mac_local[8]; /* Locally Admin Addr. */
118 uint8_t mac_add1[8]; /* Additional Programmed MAC Addr 1. */
119 uint8_t mac_add2[8]; /* Additional Programmed MAC Addr 2. */
120 /* QoS Priority (per 802.1p). 0-7255 */
121 uint32_t qos_priority;
122 uint32_t txq_size; /* FCoE TX Descriptors Queue Size. */
123 uint32_t rxq_size; /* FCoE RX Descriptors Queue Size. */
124 /* FCoE TX Descriptor Queue Avg Depth. */
125 uint32_t txq_avg_depth;
126 /* FCoE RX Descriptors Queue Avg Depth. */
127 uint32_t rxq_avg_depth;
128 uint32_t rx_frames_lo; /* FCoE RX Frames received. */
129 uint32_t rx_frames_hi; /* FCoE RX Frames received. */
130 uint32_t rx_bytes_lo; /* FCoE RX Bytes received. */
131 uint32_t rx_bytes_hi; /* FCoE RX Bytes received. */
132 uint32_t tx_frames_lo; /* FCoE TX Frames sent. */
133 uint32_t tx_frames_hi; /* FCoE TX Frames sent. */
134 uint32_t tx_bytes_lo; /* FCoE TX Bytes sent. */
135 uint32_t tx_bytes_hi; /* FCoE TX Bytes sent. */
136 uint32_t rx_fcs_errors; /* number of receive packets with FCS errors */
137 uint32_t rx_fc_crc_errors; /* number of FC frames with CRC errors*/
138 uint32_t fip_login_failures; /* number of FCoE/FIP Login failures */
139};
140
141/* Per PCI Function iSCSI Statistics required from the driver*/
142struct iscsi_stats_info {
143 uint8_t version[12]; /* Function's Driver Version. */
144 uint8_t mac_local[8]; /* Locally Admin iSCSI MAC Addr. */
145 uint8_t mac_add1[8]; /* Additional Programmed MAC Addr 1. */
146 /* QoS Priority (per 802.1p). 0-7255 */
147 uint32_t qos_priority;
148
149 uint8_t initiator_name[64]; /* iSCSI Boot Initiator Node name. */
150
151 uint8_t ww_port_name[64]; /* iSCSI World wide port name */
152
153 uint8_t boot_target_name[64];/* iSCSI Boot Target Name. */
154
155 uint8_t boot_target_ip[16]; /* iSCSI Boot Target IP. */
156 uint32_t boot_target_portal; /* iSCSI Boot Target Portal. */
157 uint8_t boot_init_ip[16]; /* iSCSI Boot Initiator IP Address. */
158 uint32_t max_frame_size; /* Max Frame Size. bytes */
159 uint32_t txq_size; /* PDU TX Descriptors Queue Size. */
160 uint32_t rxq_size; /* PDU RX Descriptors Queue Size. */
161
162 uint32_t txq_avg_depth; /*PDU TX Descriptor Queue Avg Depth. */
163 uint32_t rxq_avg_depth; /*PDU RX Descriptors Queue Avg Depth. */
164 uint32_t rx_pdus_lo; /* iSCSI PDUs received. */
165 uint32_t rx_pdus_hi; /* iSCSI PDUs received. */
166
167 uint32_t rx_bytes_lo; /* iSCSI RX Bytes received. */
168 uint32_t rx_bytes_hi; /* iSCSI RX Bytes received. */
169 uint32_t tx_pdus_lo; /* iSCSI PDUs sent. */
170 uint32_t tx_pdus_hi; /* iSCSI PDUs sent. */
171
172 uint32_t tx_bytes_lo; /* iSCSI PDU TX Bytes sent. */
173 uint32_t tx_bytes_hi; /* iSCSI PDU TX Bytes sent. */
174 uint32_t pcp_prior_map_tbl; /*C-PCP to S-PCP Priority MapTable.
175 9 nibbles, the position of each nibble
176 represents the C-PCP value, the value
177 of the nibble = S-PCP value.*/
178};
179
180union drv_info_to_mcp {
181 struct eth_stats_info ether_stat;
182 struct fcoe_stats_info fcoe_stat;
183 struct iscsi_stats_info iscsi_stat;
184};
185
186
187#endif /* ECORE_MFW_REQ_H */