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[ceph.git] / ceph / src / dpdk / drivers / net / bnx2x / ecore_reg.h
CommitLineData
7c673cae
FG		 1/*-
2 * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.
3 *
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
7 *
8 * Copyright (c) 2014-2015 QLogic Corporation.
9 * All rights reserved.
10 * www.qlogic.com
11 *
12 * See LICENSE.bnx2x_pmd for copyright and licensing details.
13 */
14
15#ifndef ECORE_REG_H
16#define ECORE_REG_H
17
18
19#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR \
20 (0x1<<0)
21#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS \
22 (0x1<<2)
23#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU \
24 (0x1<<5)
25#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT \
26 (0x1<<3)
27#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR \
28 (0x1<<4)
29#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND \
30 (0x1<<1)
31#define ATC_REG_ATC_INIT_DONE \
32 0x1100bcUL
33#define ATC_REG_ATC_INT_STS_CLR \
34 0x1101c0UL
35#define ATC_REG_ATC_PRTY_MASK \
36 0x1101d8UL
37#define ATC_REG_ATC_PRTY_STS_CLR \
38 0x1101d0UL
39#define BRB1_REG_BRB1_INT_MASK \
40 0x60128UL
41#define BRB1_REG_BRB1_PRTY_MASK \
42 0x60138UL
43#define BRB1_REG_BRB1_PRTY_STS_CLR \
44 0x60130UL
45#define BRB1_REG_MAC_GUARANTIED_0 \
46 0x601e8UL
47#define BRB1_REG_MAC_GUARANTIED_1 \
48 0x60240UL
49#define BRB1_REG_NUM_OF_FULL_BLOCKS \
50 0x60090UL
51#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 \
52 0x60078UL
53#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 \
54 0x60068UL
55#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 \
56 0x60094UL
57#define CCM_REG_CCM_INT_MASK \
58 0xd01e4UL
59#define CCM_REG_CCM_PRTY_MASK \
60 0xd01f4UL
61#define CCM_REG_CCM_PRTY_STS_CLR \
62 0xd01ecUL
63#define CDU_REG_CDU_GLOBAL_PARAMS \
64 0x101020UL
65#define CDU_REG_CDU_INT_MASK \
66 0x10103cUL
67#define CDU_REG_CDU_PRTY_MASK \
68 0x10104cUL
69#define CDU_REG_CDU_PRTY_STS_CLR \
70 0x101044UL
71#define CFC_REG_AC_INIT_DONE \
72 0x104078UL
73#define CFC_REG_CAM_INIT_DONE \
74 0x10407cUL
75#define CFC_REG_CFC_INT_MASK \
76 0x104108UL
77#define CFC_REG_CFC_INT_STS_CLR \
78 0x104100UL
79#define CFC_REG_CFC_PRTY_MASK \
80 0x104118UL
81#define CFC_REG_CFC_PRTY_STS_CLR \
82 0x104110UL
83#define CFC_REG_DEBUG0 \
84 0x104050UL
85#define CFC_REG_INIT_REG \
86 0x10404cUL
87#define CFC_REG_LL_INIT_DONE \
88 0x104074UL
89#define CFC_REG_NUM_LCIDS_INSIDE_PF \
90 0x104120UL
91#define CFC_REG_STRONG_ENABLE_PF \
92 0x104128UL
93#define CFC_REG_WEAK_ENABLE_PF \
94 0x104124UL
95#define CSDM_REG_CSDM_INT_MASK_0 \
96 0xc229cUL
97#define CSDM_REG_CSDM_INT_MASK_1 \
98 0xc22acUL
99#define CSDM_REG_CSDM_PRTY_MASK \
100 0xc22bcUL
101#define CSDM_REG_CSDM_PRTY_STS_CLR \
102 0xc22b4UL
103#define CSEM_REG_CSEM_INT_MASK_0 \
104 0x200110UL
105#define CSEM_REG_CSEM_INT_MASK_1 \
106 0x200120UL
107#define CSEM_REG_CSEM_PRTY_MASK_0 \
108 0x200130UL
109#define CSEM_REG_CSEM_PRTY_MASK_1 \
110 0x200140UL
111#define CSEM_REG_CSEM_PRTY_STS_CLR_0 \
112 0x200128UL
113#define CSEM_REG_CSEM_PRTY_STS_CLR_1 \
114 0x200138UL
115#define CSEM_REG_FAST_MEMORY \
116 0x220000UL
117#define CSEM_REG_INT_TABLE \
118 0x200400UL
119#define CSEM_REG_PASSIVE_BUFFER \
120 0x202000UL
121#define CSEM_REG_PRAM \
122 0x240000UL
123#define CSEM_REG_VFPF_ERR_NUM \
124 0x200380UL
125#define DBG_REG_DBG_PRTY_MASK \
126 0xc0a8UL
127#define DBG_REG_DBG_PRTY_STS_CLR \
128 0xc0a0UL
129#define DMAE_REG_BACKWARD_COMP_EN \
130 0x10207cUL
131#define DMAE_REG_CMD_MEM \
132 0x102400UL
133#define DMAE_REG_DMAE_INT_MASK \
134 0x102054UL
135#define DMAE_REG_DMAE_PRTY_MASK \
136 0x102064UL
137#define DMAE_REG_DMAE_PRTY_STS_CLR \
138 0x10205cUL
139#define DMAE_REG_GO_C0 \
140 0x102080UL
141#define DMAE_REG_GO_C1 \
142 0x102084UL
143#define DMAE_REG_GO_C10 \
144 0x102088UL
145#define DMAE_REG_GO_C11 \
146 0x10208cUL
147#define DMAE_REG_GO_C12 \
148 0x102090UL
149#define DMAE_REG_GO_C13 \
150 0x102094UL
151#define DMAE_REG_GO_C14 \
152 0x102098UL
153#define DMAE_REG_GO_C15 \
154 0x10209cUL
155#define DMAE_REG_GO_C2 \
156 0x1020a0UL
157#define DMAE_REG_GO_C3 \
158 0x1020a4UL
159#define DMAE_REG_GO_C4 \
160 0x1020a8UL
161#define DMAE_REG_GO_C5 \
162 0x1020acUL
163#define DMAE_REG_GO_C6 \
164 0x1020b0UL
165#define DMAE_REG_GO_C7 \
166 0x1020b4UL
167#define DMAE_REG_GO_C8 \
168 0x1020b8UL
169#define DMAE_REG_GO_C9 \
170 0x1020bcUL
171#define DORQ_REG_DORQ_INT_MASK \
172 0x170180UL
173#define DORQ_REG_DORQ_INT_STS_CLR \
174 0x170178UL
175#define DORQ_REG_DORQ_PRTY_MASK \
176 0x170190UL
177#define DORQ_REG_DORQ_PRTY_STS_CLR \
178 0x170188UL
179#define DORQ_REG_DPM_CID_OFST \
180 0x170030UL
181#define DORQ_REG_MAX_RVFID_SIZE \
182 0x1701ecUL
183#define DORQ_REG_NORM_CID_OFST \
184 0x17002cUL
185#define DORQ_REG_PF_USAGE_CNT \
186 0x1701d0UL
187#define DORQ_REG_VF_NORM_CID_BASE \
188 0x1701a0UL
189#define DORQ_REG_VF_NORM_CID_OFST \
190 0x1701f4UL
191#define DORQ_REG_VF_NORM_CID_WND_SIZE \
192 0x1701a4UL
193#define DORQ_REG_VF_NORM_MAX_CID_COUNT \
194 0x1701e4UL
195#define DORQ_REG_VF_NORM_VF_BASE \
196 0x1701a8UL
197#define DORQ_REG_VF_TYPE_MASK_0 \
198 0x170218UL
199#define DORQ_REG_VF_TYPE_MAX_MCID_0 \
200 0x1702d8UL
201#define DORQ_REG_VF_TYPE_MIN_MCID_0 \
202 0x170298UL
203#define DORQ_REG_VF_TYPE_VALUE_0 \
204 0x170258UL
205#define DORQ_REG_VF_USAGE_CNT \
206 0x170320UL
207#define DORQ_REG_VF_USAGE_CT_LIMIT \
208 0x170340UL
209#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 \
210 (0x1<<4)
211#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 \
212 (0x1<<0)
213#define HC_CONFIG_0_REG_INT_LINE_EN_0 \
214 (0x1<<3)
215#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 \
216 (0x1<<7)
217#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 \
218 (0x1<<2)
219#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 \
220 (0x1<<1)
221#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 \
222 (0x1<<0)
223#define HC_REG_ATTN_MSG0_ADDR_L \
224 0x108018UL
225#define HC_REG_ATTN_MSG1_ADDR_L \
226 0x108020UL
227#define HC_REG_COMMAND_REG \
228 0x108180UL
229#define HC_REG_CONFIG_0 \
230 0x108000UL
231#define HC_REG_CONFIG_1 \
232 0x108004UL
233#define HC_REG_HC_PRTY_MASK \
234 0x1080a0UL
235#define HC_REG_HC_PRTY_STS_CLR \
236 0x108098UL
237#define HC_REG_INT_MASK \
238 0x108108UL
239#define HC_REG_LEADING_EDGE_0 \
240 0x108040UL
241#define HC_REG_MAIN_MEMORY \
242 0x108800UL
243#define HC_REG_MAIN_MEMORY_SIZE \
244 152
245#define HC_REG_TRAILING_EDGE_0 \
246 0x108044UL
247#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN \
248 (0x1<<1)
249#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE \
250 (0x1<<0)
251#define IGU_REG_ATTENTION_ACK_BITS \
252 0x130108UL
253#define IGU_REG_ATTN_MSG_ADDR_H \
254 0x13011cUL
255#define IGU_REG_ATTN_MSG_ADDR_L \
256 0x130120UL
257#define IGU_REG_BLOCK_CONFIGURATION \
258 0x130000UL
259#define IGU_REG_COMMAND_REG_32LSB_DATA \
260 0x130124UL
261#define IGU_REG_COMMAND_REG_CTRL \
262 0x13012cUL
263#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP \
264 0x130200UL
265#define IGU_REG_IGU_PRTY_MASK \
266 0x1300a8UL
267#define IGU_REG_IGU_PRTY_STS_CLR \
268 0x1300a0UL
269#define IGU_REG_LEADING_EDGE_LATCH \
270 0x130134UL
271#define IGU_REG_MAPPING_MEMORY \
272 0x131000UL
273#define IGU_REG_MAPPING_MEMORY_SIZE \
274 136
275#define IGU_REG_PBA_STATUS_LSB \
276 0x130138UL
277#define IGU_REG_PBA_STATUS_MSB \
278 0x13013cUL
279#define IGU_REG_PCI_PF_MSIX_EN \
280 0x130144UL
281#define IGU_REG_PCI_PF_MSIX_FUNC_MASK \
282 0x130148UL
283#define IGU_REG_PCI_PF_MSI_EN \
284 0x130140UL
285#define IGU_REG_PENDING_BITS_STATUS \
286 0x130300UL
287#define IGU_REG_PF_CONFIGURATION \
288 0x130154UL
289#define IGU_REG_PROD_CONS_MEMORY \
290 0x132000UL
291#define IGU_REG_RESET_MEMORIES \
292 0x130158UL
293#define IGU_REG_SB_INT_BEFORE_MASK_LSB \
294 0x13015cUL
295#define IGU_REG_SB_INT_BEFORE_MASK_MSB \
296 0x130160UL
297#define IGU_REG_SB_MASK_LSB \
298 0x130164UL
299#define IGU_REG_SB_MASK_MSB \
300 0x130168UL
301#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT \
302 0x130800UL
303#define IGU_REG_TRAILING_EDGE_LATCH \
304 0x130104UL
305#define IGU_REG_VF_CONFIGURATION \
306 0x130170UL
307#define MCP_REG_MCPR_ACCESS_LOCK \
308 0x8009c
309#define MCP_REG_MCPR_GP_INPUTS \
310 0x800c0
311#define MCP_REG_MCPR_GP_OENABLE \
312 0x800c8
313#define MCP_REG_MCPR_GP_OUTPUTS \
314 0x800c4
315#define MCP_REG_MCPR_IMC_COMMAND \
316 0x85900
317#define MCP_REG_MCPR_IMC_DATAREG0 \
318 0x85920
319#define MCP_REG_MCPR_IMC_SLAVE_CONTROL \
320 0x85904
321#define MCP_REG_MCPR_NVM_ACCESS_ENABLE \
322 0x86424
323#define MCP_REG_MCPR_NVM_ADDR \
324 0x8640c
325#define MCP_REG_MCPR_NVM_CFG4 \
326 0x8642c
327#define MCP_REG_MCPR_NVM_COMMAND \
328 0x86400
329#define MCP_REG_MCPR_NVM_READ \
330 0x86410
331#define MCP_REG_MCPR_NVM_SW_ARB \
332 0x86420
333#define MCP_REG_MCPR_NVM_WRITE \
334 0x86408
335#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK \
336 (0x1<<1)
337#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK \
338 (0x1<<0)
339#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 \
340 0xa42cUL
341#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 \
342 0xa438UL
343#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 \
344 0xa444UL
345#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 \
346 0xa450UL
347#define MISC_REG_AEU_AFTER_INVERT_4_MCP \
348 0xa458UL
349#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 \
350 0xa700UL
351#define MISC_REG_AEU_CLR_LATCH_SIGNAL \
352 0xa45cUL
353#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 \
354 0xa06cUL
355#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 \
356 0xa07cUL
357#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 \
358 0xa08cUL
359#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 \
360 0xa10cUL
361#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 \
362 0xa11cUL
363#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 \
364 0xa12cUL
365#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 \
366 0xa078UL
367#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 \
368 0xa118UL
369#define MISC_REG_AEU_ENABLE4_NIG_0 \
370 0xa0f8UL
371#define MISC_REG_AEU_ENABLE4_NIG_1 \
372 0xa198UL
373#define MISC_REG_AEU_ENABLE4_PXP_0 \
374 0xa108UL
375#define MISC_REG_AEU_ENABLE4_PXP_1 \
376 0xa1a8UL
377#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 \
378 0xa688UL
379#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 \
380 0xa6b0UL
381#define MISC_REG_AEU_GENERAL_ATTN_0 \
382 0xa000UL
383#define MISC_REG_AEU_GENERAL_ATTN_1 \
384 0xa004UL
385#define MISC_REG_AEU_GENERAL_ATTN_10 \
386 0xa028UL
387#define MISC_REG_AEU_GENERAL_ATTN_11 \
388 0xa02cUL
389#define MISC_REG_AEU_GENERAL_ATTN_12 \
390 0xa030UL
391#define MISC_REG_AEU_GENERAL_ATTN_2 \
392 0xa008UL
393#define MISC_REG_AEU_GENERAL_ATTN_3 \
394 0xa00cUL
395#define MISC_REG_AEU_GENERAL_ATTN_4 \
396 0xa010UL
397#define MISC_REG_AEU_GENERAL_ATTN_5 \
398 0xa014UL
399#define MISC_REG_AEU_GENERAL_ATTN_6 \
400 0xa018UL
401#define MISC_REG_AEU_GENERAL_ATTN_7 \
402 0xa01cUL
403#define MISC_REG_AEU_GENERAL_ATTN_8 \
404 0xa020UL
405#define MISC_REG_AEU_GENERAL_ATTN_9 \
406 0xa024UL
407#define MISC_REG_AEU_GENERAL_MASK \
408 0xa61cUL
409#define MISC_REG_AEU_MASK_ATTN_FUNC_0 \
410 0xa060UL
411#define MISC_REG_AEU_MASK_ATTN_FUNC_1 \
412 0xa064UL
413#define MISC_REG_BOND_ID \
414 0xa400UL
415#define MISC_REG_CHIP_NUM \
416 0xa408UL
417#define MISC_REG_CHIP_REV \
418 0xa40cUL
419#define MISC_REG_CHIP_TYPE \
420 0xac60UL
421#define MISC_REG_CHIP_TYPE_57811_MASK \
422 (1<<1)
423#define MISC_REG_CPMU_LP_DR_ENABLE \
424 0xa858UL
425#define MISC_REG_CPMU_LP_FW_ENABLE_P0 \
426 0xa84cUL
427#define MISC_REG_CPMU_LP_IDLE_THR_P0 \
428 0xa8a0UL
429#define MISC_REG_CPMU_LP_MASK_ENT_P0 \
430 0xa880UL
431#define MISC_REG_CPMU_LP_MASK_EXT_P0 \
432 0xa888UL
433#define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 \
434 0xa8b8UL
435#define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 \
436 0xa8bcUL
437#define MISC_REG_DRIVER_CONTROL_1 \
438 0xa510UL
439#define MISC_REG_DRIVER_CONTROL_7 \
440 0xa3c8UL
441#define MISC_REG_FOUR_PORT_PATH_SWAP \
442 0xa75cUL
443#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR \
444 0xa738UL
445#define MISC_REG_FOUR_PORT_PORT_SWAP \
446 0xa754UL
447#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR \
448 0xa734UL
449#define MISC_REG_GENERIC_CR_0 \
450 0xa460UL
451#define MISC_REG_GENERIC_CR_1 \
452 0xa464UL
453#define MISC_REG_GENERIC_POR_1 \
454 0xa474UL
455#define MISC_REG_GEN_PURP_HWG \
456 0xa9a0UL
457#define MISC_REG_GPIO \
458 0xa490UL
459#define MISC_REG_GPIO_EVENT_EN \
460 0xa2bcUL
461#define MISC_REG_GPIO_INT \
462 0xa494UL
463#define MISC_REG_GRC_RSV_ATTN \
464 0xa3c0UL
465#define MISC_REG_GRC_TIMEOUT_ATTN \
466 0xa3c4UL
467#define MISC_REG_LCPLL_E40_PWRDWN \
468 0xaa74UL
469#define MISC_REG_LCPLL_E40_RESETB_ANA \
470 0xaa78UL
471#define MISC_REG_LCPLL_E40_RESETB_DIG \
472 0xaa7cUL
473#define MISC_REG_MISC_INT_MASK \
474 0xa388UL
475#define MISC_REG_MISC_PRTY_MASK \
476 0xa398UL
477#define MISC_REG_MISC_PRTY_STS_CLR \
478 0xa390UL
479#define MISC_REG_PORT4MODE_EN \
480 0xa750UL
481#define MISC_REG_PORT4MODE_EN_OVWR \
482 0xa720UL
483#define MISC_REG_RESET_REG_1 \
484 0xa580UL
485#define MISC_REG_RESET_REG_2 \
486 0xa590UL
487#define MISC_REG_SHARED_MEM_ADDR \
488 0xa2b4UL
489#define MISC_REG_SPIO \
490 0xa4fcUL
491#define MISC_REG_SPIO_EVENT_EN \
492 0xa2b8UL
493#define MISC_REG_SPIO_INT \
494 0xa500UL
495#define MISC_REG_TWO_PORT_PATH_SWAP \
496 0xa758UL
497#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR \
498 0xa72cUL
499#define MISC_REG_UNPREPARED \
500 0xa424UL
501#define MISC_REG_WC0_CTRL_PHY_ADDR \
502 0xa9ccUL
503#define MISC_REG_WC0_RESET \
504 0xac30UL
505#define MISC_REG_XMAC_CORE_PORT_MODE \
506 0xa964UL
507#define MISC_REG_XMAC_PHY_PORT_MODE \
508 0xa960UL
509#define MSTAT_REG_RX_STAT_GR64_LO \
510 0x200UL
511#define MSTAT_REG_TX_STAT_GTXPOK_LO \
512 0UL
513#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN \
514 (0x1<<0)
515#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN \
516 (0x1<<0)
517#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT \
518 (0x1<<0)
519#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS \
520 (0x1<<9)
521#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G \
522 (0x1<<15)
523#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS \
524 (0xf<<18)
525#define NIG_REG_BMAC0_IN_EN \
526 0x100acUL
527#define NIG_REG_BMAC0_OUT_EN \
528 0x100e0UL
529#define NIG_REG_BMAC0_PAUSE_OUT_EN \
530 0x10110UL
531#define NIG_REG_BMAC0_REGS_OUT_EN \
532 0x100e8UL
533#define NIG_REG_BRB0_PAUSE_IN_EN \
534 0x100c4UL
535#define NIG_REG_BRB1_PAUSE_IN_EN \
536 0x100c8UL
537#define NIG_REG_DEBUG_PACKET_LB \
538 0x10800UL
539#define NIG_REG_EGRESS_DRAIN0_MODE \
540 0x10060UL
541#define NIG_REG_EGRESS_EMAC0_OUT_EN \
542 0x10120UL
543#define NIG_REG_EGRESS_EMAC0_PORT \
544 0x10058UL
545#define NIG_REG_EMAC0_IN_EN \
546 0x100a4UL
547#define NIG_REG_EMAC0_PAUSE_OUT_EN \
548 0x10118UL
549#define NIG_REG_EMAC0_STATUS_MISC_MI_INT \
550 0x10494UL
551#define NIG_REG_INGRESS_BMAC0_MEM \
552 0x10c00UL
553#define NIG_REG_INGRESS_BMAC1_MEM \
554 0x11000UL
555#define NIG_REG_INGRESS_EOP_LB_EMPTY \
556 0x104e0UL
557#define NIG_REG_INGRESS_EOP_LB_FIFO \
558 0x104e4UL
559#define NIG_REG_LATCH_BC_0 \
560 0x16210UL
561#define NIG_REG_LATCH_STATUS_0 \
562 0x18000UL
563#define NIG_REG_LED_10G_P0 \
564 0x10320UL
565#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 \
566 0x10318UL
567#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 \
568 0x10310UL
569#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 \
570 0x10308UL
571#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 \
572 0x102f8UL
573#define NIG_REG_LED_CONTROL_TRAFFIC_P0 \
574 0x10300UL
575#define NIG_REG_LED_MODE_P0 \
576 0x102f0UL
577#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 \
578 0x16070UL
579#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 \
580 0x16074UL
581#define NIG_REG_LLFC_ENABLE_0 \
582 0x16208UL
583#define NIG_REG_LLFC_ENABLE_1 \
584 0x1620cUL
585#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 \
586 0x16058UL
587#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 \
588 0x1605cUL
589#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 \
590 0x16060UL
591#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 \
592 0x16064UL
593#define NIG_REG_LLFC_OUT_EN_0 \
594 0x160c8UL
595#define NIG_REG_LLFC_OUT_EN_1 \
596 0x160ccUL
597#define NIG_REG_LLH0_BRB1_DRV_MASK \
598 0x10244UL
599#define NIG_REG_LLH0_BRB1_DRV_MASK_MF \
600 0x16048UL
601#define NIG_REG_LLH0_BRB1_NOT_MCP \
602 0x1025cUL
603#define NIG_REG_LLH0_CLS_TYPE \
604 0x16080UL
605#define NIG_REG_LLH0_FUNC_EN \
606 0x160fcUL
607#define NIG_REG_LLH0_FUNC_MEM \
608 0x16180UL
609#define NIG_REG_LLH0_FUNC_MEM_ENABLE \
610 0x16140UL
611#define NIG_REG_LLH0_FUNC_VLAN_ID \
612 0x16100UL
613#define NIG_REG_LLH0_XCM_MASK \
614 0x10130UL
615#define NIG_REG_LLH1_BRB1_NOT_MCP \
616 0x102dcUL
617#define NIG_REG_LLH1_CLS_TYPE \
618 0x16084UL
619#define NIG_REG_LLH1_FUNC_MEM \
620 0x161c0UL
621#define NIG_REG_LLH1_FUNC_MEM_ENABLE \
622 0x16160UL
623#define NIG_REG_LLH1_FUNC_MEM_SIZE \
624 16
625#define NIG_REG_LLH1_MF_MODE \
626 0x18614UL
627#define NIG_REG_LLH1_XCM_MASK \
628 0x10134UL
629#define NIG_REG_LLH_E1HOV_MODE \
630 0x160d8UL
631#define NIG_REG_LLH_MF_MODE \
632 0x16024UL
633#define NIG_REG_MASK_INTERRUPT_PORT0 \
634 0x10330UL
635#define NIG_REG_MASK_INTERRUPT_PORT1 \
636 0x10334UL
637#define NIG_REG_NIG_EMAC0_EN \
638 0x1003cUL
639#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC \
640 0x10044UL
641#define NIG_REG_NIG_INT_STS_CLR_0 \
642 0x103b4UL
643#define NIG_REG_NIG_PRTY_MASK \
644 0x103dcUL
645#define NIG_REG_NIG_PRTY_MASK_0 \
646 0x183c8UL
647#define NIG_REG_NIG_PRTY_MASK_1 \
648 0x183d8UL
649#define NIG_REG_NIG_PRTY_STS_CLR \
650 0x103d4UL
651#define NIG_REG_NIG_PRTY_STS_CLR_0 \
652 0x183c0UL
653#define NIG_REG_NIG_PRTY_STS_CLR_1 \
654 0x183d0UL
655#define NIG_REG_P0_HDRS_AFTER_BASIC \
656 0x18038UL
657#define NIG_REG_P0_HWPFC_ENABLE \
658 0x18078UL
659#define NIG_REG_P0_LLH_FUNC_MEM2 \
660 0x18480UL
661#define NIG_REG_P0_MAC_IN_EN \
662 0x185acUL
663#define NIG_REG_P0_MAC_OUT_EN \
664 0x185b0UL
665#define NIG_REG_P0_MAC_PAUSE_OUT_EN \
666 0x185b4UL
667#define NIG_REG_P0_PKT_PRIORITY_TO_COS \
668 0x18054UL
669#define NIG_REG_P0_RX_COS0_PRIORITY_MASK \
670 0x18058UL
671#define NIG_REG_P0_RX_COS1_PRIORITY_MASK \
672 0x1805cUL
673#define NIG_REG_P0_RX_COS2_PRIORITY_MASK \
674 0x186b0UL
675#define NIG_REG_P0_RX_COS3_PRIORITY_MASK \
676 0x186b4UL
677#define NIG_REG_P0_RX_COS4_PRIORITY_MASK \
678 0x186b8UL
679#define NIG_REG_P0_RX_COS5_PRIORITY_MASK \
680 0x186bcUL
681#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP \
682 0x180f0UL
683#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB \
684 0x18688UL
685#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB \
686 0x1868cUL
687#define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT \
688 0x180e8UL
689#define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ \
690 0x180ecUL
691#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 \
692 0x1810cUL
693#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 \
694 0x18110UL
695#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 \
696 0x18114UL
697#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 \
698 0x18118UL
699#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 \
700 0x1811cUL
701#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 \
702 0x186a0UL
703#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 \
704 0x186a4UL
705#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 \
706 0x186a8UL
707#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 \
708 0x186acUL
709#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 \
710 0x180f8UL
711#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 \
712 0x180fcUL
713#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 \
714 0x18100UL
715#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 \
716 0x18104UL
717#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 \
718 0x18108UL
719#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 \
720 0x18690UL
721#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 \
722 0x18694UL
723#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 \
724 0x18698UL
725#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 \
726 0x1869cUL
727#define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS \
728 0x180f4UL
729#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT \
730 0x180e4UL
731#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB \
732 0x18680UL
733#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB \
734 0x18684UL
735#define NIG_REG_P1_HDRS_AFTER_BASIC \
736 0x1818cUL
737#define NIG_REG_P1_HWPFC_ENABLE \
738 0x181d0UL
739#define NIG_REG_P1_LLH_FUNC_MEM2 \
740 0x184c0UL
741#define NIG_REG_P1_MAC_IN_EN \
742 0x185c0UL
743#define NIG_REG_P1_MAC_OUT_EN \
744 0x185c4UL
745#define NIG_REG_P1_MAC_PAUSE_OUT_EN \
746 0x185c8UL
747#define NIG_REG_P1_PKT_PRIORITY_TO_COS \
748 0x181a8UL
749#define NIG_REG_P1_RX_COS0_PRIORITY_MASK \
750 0x181acUL
751#define NIG_REG_P1_RX_COS1_PRIORITY_MASK \
752 0x181b0UL
753#define NIG_REG_P1_RX_COS2_PRIORITY_MASK \
754 0x186f8UL
755#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB \
756 0x186e8UL
757#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB \
758 0x186ecUL
759#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT \
760 0x18234UL
761#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ \
762 0x18238UL
763#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 \
764 0x18258UL
765#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 \
766 0x1825cUL
767#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 \
768 0x18260UL
769#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 \
770 0x18264UL
771#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 \
772 0x18268UL
773#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 \
774 0x186f4UL
775#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 \
776 0x18244UL
777#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 \
778 0x18248UL
779#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 \
780 0x1824cUL
781#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 \
782 0x18250UL
783#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 \
784 0x18254UL
785#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 \
786 0x186f0UL
787#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS \
788 0x18240UL
789#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB \
790 0x186e0UL
791#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB \
792 0x186e4UL
793#define NIG_REG_PAUSE_ENABLE_0 \
794 0x160c0UL
795#define NIG_REG_PAUSE_ENABLE_1 \
796 0x160c4UL
797#define NIG_REG_PORT_SWAP \
798 0x10394UL
799#define NIG_REG_PPP_ENABLE_0 \
800 0x160b0UL
801#define NIG_REG_PPP_ENABLE_1 \
802 0x160b4UL
803#define NIG_REG_PRS_REQ_IN_EN \
804 0x100b8UL
805#define NIG_REG_SERDES0_CTRL_MD_DEVAD \
806 0x10370UL
807#define NIG_REG_SERDES0_CTRL_MD_ST \
808 0x1036cUL
809#define NIG_REG_SERDES0_CTRL_PHY_ADDR \
810 0x10374UL
811#define NIG_REG_SERDES0_STATUS_LINK_STATUS \
812 0x10578UL
813#define NIG_REG_STAT0_BRB_DISCARD \
814 0x105f0UL
815#define NIG_REG_STAT0_BRB_TRUNCATE \
816 0x105f8UL
817#define NIG_REG_STAT0_EGRESS_MAC_PKT0 \
818 0x10750UL
819#define NIG_REG_STAT0_EGRESS_MAC_PKT1 \
820 0x10760UL
821#define NIG_REG_STAT1_BRB_DISCARD \
822 0x10628UL
823#define NIG_REG_STAT1_EGRESS_MAC_PKT0 \
824 0x107a0UL
825#define NIG_REG_STAT1_EGRESS_MAC_PKT1 \
826 0x107b0UL
827#define NIG_REG_STAT2_BRB_OCTET \
828 0x107e0UL
829#define NIG_REG_STATUS_INTERRUPT_PORT0 \
830 0x10328UL
831#define NIG_REG_STRAP_OVERRIDE \
832 0x10398UL
833#define NIG_REG_XCM0_OUT_EN \
834 0x100f0UL
835#define NIG_REG_XCM1_OUT_EN \
836 0x100f4UL
837#define NIG_REG_XGXS0_CTRL_MD_DEVAD \
838 0x1033cUL
839#define NIG_REG_XGXS0_CTRL_MD_ST \
840 0x10338UL
841#define NIG_REG_XGXS0_CTRL_PHY_ADDR \
842 0x10340UL
843#define NIG_REG_XGXS0_STATUS_LINK10G \
844 0x10680UL
845#define NIG_REG_XGXS0_STATUS_LINK_STATUS \
846 0x10684UL
847#define NIG_REG_XGXS_LANE_SEL_P0 \
848 0x102e8UL
849#define NIG_REG_XGXS_SERDES0_MODE_SEL \
850 0x102e0UL
851#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT \
852 (0x1<<0)
853#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS \
854 (0x1<<9)
855#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G \
856 (0x1<<15)
857#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS \
858 (0xf<<18)
859#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE \
860 18
861#define PBF_REG_COS0_UPPER_BOUND \
862 0x15c05cUL
863#define PBF_REG_COS0_UPPER_BOUND_P0 \
864 0x15c2ccUL
865#define PBF_REG_COS0_UPPER_BOUND_P1 \
866 0x15c2e4UL
867#define PBF_REG_COS0_WEIGHT \
868 0x15c054UL
869#define PBF_REG_COS0_WEIGHT_P0 \
870 0x15c2a8UL
871#define PBF_REG_COS0_WEIGHT_P1 \
872 0x15c2c0UL
873#define PBF_REG_COS1_UPPER_BOUND \
874 0x15c060UL
875#define PBF_REG_COS1_WEIGHT \
876 0x15c058UL
877#define PBF_REG_COS1_WEIGHT_P0 \
878 0x15c2acUL
879#define PBF_REG_COS1_WEIGHT_P1 \
880 0x15c2c4UL
881#define PBF_REG_COS2_WEIGHT_P0 \
882 0x15c2b0UL
883#define PBF_REG_COS2_WEIGHT_P1 \
884 0x15c2c8UL
885#define PBF_REG_COS3_WEIGHT_P0 \
886 0x15c2b4UL
887#define PBF_REG_COS4_WEIGHT_P0 \
888 0x15c2b8UL
889#define PBF_REG_COS5_WEIGHT_P0 \
890 0x15c2bcUL
891#define PBF_REG_CREDIT_LB_Q \
892 0x140338UL
893#define PBF_REG_CREDIT_Q0 \
894 0x14033cUL
895#define PBF_REG_CREDIT_Q1 \
896 0x140340UL
897#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 \
898 0x14005cUL
899#define PBF_REG_DISABLE_PF \
900 0x1402e8UL
901#define PBF_REG_DISABLE_VF \
902 0x1402ecUL
903#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 \
904 0x15c288UL
905#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 \
906 0x15c28cUL
907#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 \
908 0x15c278UL
909#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 \
910 0x15c27cUL
911#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 \
912 0x15c280UL
913#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 \
914 0x15c284UL
915#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 \
916 0x15c2a0UL
917#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 \
918 0x15c2a4UL
919#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 \
920 0x15c270UL
921#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 \
922 0x15c274UL
923#define PBF_REG_ETS_ENABLED \
924 0x15c050UL
925#define PBF_REG_HDRS_AFTER_BASIC \
926 0x15c0a8UL
927#define PBF_REG_HDRS_AFTER_TAG_0 \
928 0x15c0b8UL
929#define PBF_REG_HIGH_PRIORITY_COS_NUM \
930 0x15c04cUL
931#define PBF_REG_INIT_CRD_LB_Q \
932 0x15c248UL
933#define PBF_REG_INIT_CRD_Q0 \
934 0x15c230UL
935#define PBF_REG_INIT_CRD_Q1 \
936 0x15c234UL
937#define PBF_REG_INIT_P0 \
938 0x140004UL
939#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q \
940 0x140354UL
941#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 \
942 0x140358UL
943#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 \
944 0x14035cUL
945#define PBF_REG_MUST_HAVE_HDRS \
946 0x15c0c4UL
947#define PBF_REG_NUM_STRICT_ARB_SLOTS \
948 0x15c064UL
949#define PBF_REG_P0_ARB_THRSH \
950 0x1400e4UL
951#define PBF_REG_P0_CREDIT \
952 0x140200UL
953#define PBF_REG_P0_INIT_CRD \
954 0x1400d0UL
955#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT \
956 0x140308UL
957#define PBF_REG_P0_PAUSE_ENABLE \
958 0x140014UL
959#define PBF_REG_P0_TQ_LINES_FREED_CNT \
960 0x1402f0UL
961#define PBF_REG_P0_TQ_OCCUPANCY \
962 0x1402fcUL
963#define PBF_REG_P1_CREDIT \
964 0x140208UL
965#define PBF_REG_P1_INIT_CRD \
966 0x1400d4UL
967#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT \
968 0x14030cUL
969#define PBF_REG_P1_TQ_LINES_FREED_CNT \
970 0x1402f4UL
971#define PBF_REG_P1_TQ_OCCUPANCY \
972 0x140300UL
973#define PBF_REG_P4_CREDIT \
974 0x140210UL
975#define PBF_REG_P4_INIT_CRD \
976 0x1400e0UL
977#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT \
978 0x140310UL
979#define PBF_REG_P4_TQ_LINES_FREED_CNT \
980 0x1402f8UL
981#define PBF_REG_P4_TQ_OCCUPANCY \
982 0x140304UL
983#define PBF_REG_PBF_INT_MASK \
984 0x1401d4UL
985#define PBF_REG_PBF_PRTY_MASK \
986 0x1401e4UL
987#define PBF_REG_PBF_PRTY_STS_CLR \
988 0x1401dcUL
989#define PBF_REG_TAG_ETHERTYPE_0 \
990 0x15c090UL
991#define PBF_REG_TAG_LEN_0 \
992 0x15c09cUL
993#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q \
994 0x14038cUL
995#define PBF_REG_TQ_LINES_FREED_CNT_Q0 \
996 0x140390UL
997#define PBF_REG_TQ_LINES_FREED_CNT_Q1 \
998 0x140394UL
999#define PBF_REG_TQ_OCCUPANCY_LB_Q \
1000 0x1403a8UL
1001#define PBF_REG_TQ_OCCUPANCY_Q0 \
1002 0x1403acUL
1003#define PBF_REG_TQ_OCCUPANCY_Q1 \
1004 0x1403b0UL
1005#define PB_REG_PB_INT_MASK \
1006 0x28UL
1007#define PB_REG_PB_PRTY_MASK \
1008 0x38UL
1009#define PB_REG_PB_PRTY_STS_CLR \
1010 0x30UL
1011#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR \
1012 (0x1<<0)
1013#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW \
1014 (0x1<<8)
1015#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR \
1016 (0x1<<1)
1017#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN \
1018 (0x1<<6)
1019#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN \
1020 (0x1<<7)
1021#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN \
1022 (0x1<<4)
1023#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN \
1024 (0x1<<3)
1025#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN \
1026 (0x1<<5)
1027#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN \
1028 (0x1<<2)
1029#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR \
1030 0x9418UL
1031#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \
1032 0x9478UL
1033#define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR \
1034 0x947cUL
1035#define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR \
1036 0x9480UL
1037#define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR \
1038 0x9474UL
1039#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \
1040 0x942cUL
1041#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
1042 0x9430UL
1043#define PGLUE_B_REG_INTERNAL_VFID_ENABLE \
1044 0x9438UL
1045#define PGLUE_B_REG_PGLUE_B_INT_STS \
1046 0x9298UL
1047#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR \
1048 0x929cUL
1049#define PGLUE_B_REG_PGLUE_B_PRTY_MASK \
1050 0x92b4UL
1051#define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR \
1052 0x92acUL
1053#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR \
1054 0x9458UL
1055#define PGLUE_B_REG_TAGS_63_32 \
1056 0x9244UL
1057#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR \
1058 0x9470UL
1059#define PRS_REG_A_PRSU_20 \
1060 0x40134UL
1061#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT \
1062 0x4011cUL
1063#define PRS_REG_E1HOV_MODE \
1064 0x401c8UL
1065#define PRS_REG_HDRS_AFTER_BASIC \
1066 0x40238UL
1067#define PRS_REG_HDRS_AFTER_BASIC_PORT_0 \
1068 0x40270UL
1069#define PRS_REG_HDRS_AFTER_BASIC_PORT_1 \
1070 0x40290UL
1071#define PRS_REG_HDRS_AFTER_TAG_0 \
1072 0x40248UL
1073#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 \
1074 0x40280UL
1075#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 \
1076 0x402a0UL
1077#define PRS_REG_MUST_HAVE_HDRS \
1078 0x40254UL
1079#define PRS_REG_MUST_HAVE_HDRS_PORT_0 \
1080 0x4028cUL
1081#define PRS_REG_MUST_HAVE_HDRS_PORT_1 \
1082 0x402acUL
1083#define PRS_REG_NIC_MODE \
1084 0x40138UL
1085#define PRS_REG_NUM_OF_PACKETS \
1086 0x40124UL
1087#define PRS_REG_PRS_PRTY_MASK \
1088 0x401a4UL
1089#define PRS_REG_PRS_PRTY_STS_CLR \
1090 0x4019cUL
1091#define PRS_REG_TAG_ETHERTYPE_0 \
1092 0x401d4UL
1093#define PRS_REG_TAG_LEN_0 \
1094 0x4022cUL
1095#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT \
1096 (0x1<<19)
1097#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF \
1098 (0x1<<20)
1099#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN \
1100 (0x1<<22)
1101#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED \
1102 (0x1<<23)
1103#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED \
1104 (0x1<<24)
1105#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR \
1106 (0x1<<7)
1107#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR \
1108 (0x1<<7)
1109#define PXP2_REG_PGL_ADDR_88_F0 \
1110 0x120534UL
1111#define PXP2_REG_PGL_ADDR_88_F1 \
1112 0x120544UL
1113#define PXP2_REG_PGL_ADDR_8C_F0 \
1114 0x120538UL
1115#define PXP2_REG_PGL_ADDR_8C_F1 \
1116 0x120548UL
1117#define PXP2_REG_PGL_ADDR_90_F0 \
1118 0x12053cUL
1119#define PXP2_REG_PGL_ADDR_90_F1 \
1120 0x12054cUL
1121#define PXP2_REG_PGL_ADDR_94_F0 \
1122 0x120540UL
1123#define PXP2_REG_PGL_ADDR_94_F1 \
1124 0x120550UL
1125#define PXP2_REG_PGL_EXP_ROM2 \
1126 0x120808UL
1127#define PXP2_REG_PGL_PRETEND_FUNC_F0 \
1128 0x120674UL
1129#define PXP2_REG_PGL_PRETEND_FUNC_F1 \
1130 0x120678UL
1131#define PXP2_REG_PGL_TAGS_LIMIT \
1132 0x1205a8UL
1133#define PXP2_REG_PSWRQ_BW_ADD1 \
1134 0x1201c0UL
1135#define PXP2_REG_PSWRQ_BW_ADD10 \
1136 0x1201e4UL
1137#define PXP2_REG_PSWRQ_BW_ADD11 \
1138 0x1201e8UL
1139#define PXP2_REG_PSWRQ_BW_ADD2 \
1140 0x1201c4UL
1141#define PXP2_REG_PSWRQ_BW_ADD28 \
1142 0x120228UL
1143#define PXP2_REG_PSWRQ_BW_ADD3 \
1144 0x1201c8UL
1145#define PXP2_REG_PSWRQ_BW_ADD6 \
1146 0x1201d4UL
1147#define PXP2_REG_PSWRQ_BW_ADD7 \
1148 0x1201d8UL
1149#define PXP2_REG_PSWRQ_BW_ADD8 \
1150 0x1201dcUL
1151#define PXP2_REG_PSWRQ_BW_ADD9 \
1152 0x1201e0UL
1153#define PXP2_REG_PSWRQ_BW_L1 \
1154 0x1202b0UL
1155#define PXP2_REG_PSWRQ_BW_L10 \
1156 0x1202d4UL
1157#define PXP2_REG_PSWRQ_BW_L11 \
1158 0x1202d8UL
1159#define PXP2_REG_PSWRQ_BW_L2 \
1160 0x1202b4UL
1161#define PXP2_REG_PSWRQ_BW_L28 \
1162 0x120318UL
1163#define PXP2_REG_PSWRQ_BW_L3 \
1164 0x1202b8UL
1165#define PXP2_REG_PSWRQ_BW_L6 \
1166 0x1202c4UL
1167#define PXP2_REG_PSWRQ_BW_L7 \
1168 0x1202c8UL
1169#define PXP2_REG_PSWRQ_BW_L8 \
1170 0x1202ccUL
1171#define PXP2_REG_PSWRQ_BW_L9 \
1172 0x1202d0UL
1173#define PXP2_REG_PSWRQ_BW_RD \
1174 0x120324UL
1175#define PXP2_REG_PSWRQ_BW_UB1 \
1176 0x120238UL
1177#define PXP2_REG_PSWRQ_BW_UB10 \
1178 0x12025cUL
1179#define PXP2_REG_PSWRQ_BW_UB11 \
1180 0x120260UL
1181#define PXP2_REG_PSWRQ_BW_UB2 \
1182 0x12023cUL
1183#define PXP2_REG_PSWRQ_BW_UB28 \
1184 0x1202a0UL
1185#define PXP2_REG_PSWRQ_BW_UB3 \
1186 0x120240UL
1187#define PXP2_REG_PSWRQ_BW_UB6 \
1188 0x12024cUL
1189#define PXP2_REG_PSWRQ_BW_UB7 \
1190 0x120250UL
1191#define PXP2_REG_PSWRQ_BW_UB8 \
1192 0x120254UL
1193#define PXP2_REG_PSWRQ_BW_UB9 \
1194 0x120258UL
1195#define PXP2_REG_PSWRQ_BW_WR \
1196 0x120328UL
1197#define PXP2_REG_PSWRQ_CDU0_L2P \
1198 0x120000UL
1199#define PXP2_REG_PSWRQ_QM0_L2P \
1200 0x120038UL
1201#define PXP2_REG_PSWRQ_SRC0_L2P \
1202 0x120054UL
1203#define PXP2_REG_PSWRQ_TM0_L2P \
1204 0x12001cUL
1205#define PXP2_REG_PXP2_INT_MASK_0 \
1206 0x120578UL
1207#define PXP2_REG_PXP2_INT_MASK_1 \
1208 0x120614UL
1209#define PXP2_REG_PXP2_INT_STS_0 \
1210 0x12056cUL
1211#define PXP2_REG_PXP2_INT_STS_1 \
1212 0x120608UL
1213#define PXP2_REG_PXP2_INT_STS_CLR_0 \
1214 0x120570UL
1215#define PXP2_REG_PXP2_PRTY_MASK_0 \
1216 0x120588UL
1217#define PXP2_REG_PXP2_PRTY_MASK_1 \
1218 0x120598UL
1219#define PXP2_REG_PXP2_PRTY_STS_CLR_0 \
1220 0x120580UL
1221#define PXP2_REG_PXP2_PRTY_STS_CLR_1 \
1222 0x120590UL
1223#define PXP2_REG_RD_BLK_CNT \
1224 0x120418UL
1225#define PXP2_REG_RD_CDURD_SWAP_MODE \
1226 0x120404UL
1227#define PXP2_REG_RD_DISABLE_INPUTS \
1228 0x120374UL
1229#define PXP2_REG_RD_INIT_DONE \
1230 0x120370UL
1231#define PXP2_REG_RD_PBF_SWAP_MODE \
1232 0x1203f4UL
1233#define PXP2_REG_RD_PORT_IS_IDLE_0 \
1234 0x12041cUL
1235#define PXP2_REG_RD_PORT_IS_IDLE_1 \
1236 0x120420UL
1237#define PXP2_REG_RD_QM_SWAP_MODE \
1238 0x1203f8UL
1239#define PXP2_REG_RD_SRC_SWAP_MODE \
1240 0x120400UL
1241#define PXP2_REG_RD_SR_CNT \
1242 0x120414UL
1243#define PXP2_REG_RD_START_INIT \
1244 0x12036cUL
1245#define PXP2_REG_RD_TM_SWAP_MODE \
1246 0x1203fcUL
1247#define PXP2_REG_RQ_BW_RD_ADD0 \
1248 0x1201bcUL
1249#define PXP2_REG_RQ_BW_RD_ADD12 \
1250 0x1201ecUL
1251#define PXP2_REG_RQ_BW_RD_ADD13 \
1252 0x1201f0UL
1253#define PXP2_REG_RQ_BW_RD_ADD14 \
1254 0x1201f4UL
1255#define PXP2_REG_RQ_BW_RD_ADD15 \
1256 0x1201f8UL
1257#define PXP2_REG_RQ_BW_RD_ADD16 \
1258 0x1201fcUL
1259#define PXP2_REG_RQ_BW_RD_ADD17 \
1260 0x120200UL
1261#define PXP2_REG_RQ_BW_RD_ADD18 \
1262 0x120204UL
1263#define PXP2_REG_RQ_BW_RD_ADD19 \
1264 0x120208UL
1265#define PXP2_REG_RQ_BW_RD_ADD20 \
1266 0x12020cUL
1267#define PXP2_REG_RQ_BW_RD_ADD22 \
1268 0x120210UL
1269#define PXP2_REG_RQ_BW_RD_ADD23 \
1270 0x120214UL
1271#define PXP2_REG_RQ_BW_RD_ADD24 \
1272 0x120218UL
1273#define PXP2_REG_RQ_BW_RD_ADD25 \
1274 0x12021cUL
1275#define PXP2_REG_RQ_BW_RD_ADD26 \
1276 0x120220UL
1277#define PXP2_REG_RQ_BW_RD_ADD27 \
1278 0x120224UL
1279#define PXP2_REG_RQ_BW_RD_ADD4 \
1280 0x1201ccUL
1281#define PXP2_REG_RQ_BW_RD_ADD5 \
1282 0x1201d0UL
1283#define PXP2_REG_RQ_BW_RD_L0 \
1284 0x1202acUL
1285#define PXP2_REG_RQ_BW_RD_L12 \
1286 0x1202dcUL
1287#define PXP2_REG_RQ_BW_RD_L13 \
1288 0x1202e0UL
1289#define PXP2_REG_RQ_BW_RD_L14 \
1290 0x1202e4UL
1291#define PXP2_REG_RQ_BW_RD_L15 \
1292 0x1202e8UL
1293#define PXP2_REG_RQ_BW_RD_L16 \
1294 0x1202ecUL
1295#define PXP2_REG_RQ_BW_RD_L17 \
1296 0x1202f0UL
1297#define PXP2_REG_RQ_BW_RD_L18 \
1298 0x1202f4UL
1299#define PXP2_REG_RQ_BW_RD_L19 \
1300 0x1202f8UL
1301#define PXP2_REG_RQ_BW_RD_L20 \
1302 0x1202fcUL
1303#define PXP2_REG_RQ_BW_RD_L22 \
1304 0x120300UL
1305#define PXP2_REG_RQ_BW_RD_L23 \
1306 0x120304UL
1307#define PXP2_REG_RQ_BW_RD_L24 \
1308 0x120308UL
1309#define PXP2_REG_RQ_BW_RD_L25 \
1310 0x12030cUL
1311#define PXP2_REG_RQ_BW_RD_L26 \
1312 0x120310UL
1313#define PXP2_REG_RQ_BW_RD_L27 \
1314 0x120314UL
1315#define PXP2_REG_RQ_BW_RD_L4 \
1316 0x1202bcUL
1317#define PXP2_REG_RQ_BW_RD_L5 \
1318 0x1202c0UL
1319#define PXP2_REG_RQ_BW_RD_UBOUND0 \
1320 0x120234UL
1321#define PXP2_REG_RQ_BW_RD_UBOUND12 \
1322 0x120264UL
1323#define PXP2_REG_RQ_BW_RD_UBOUND13 \
1324 0x120268UL
1325#define PXP2_REG_RQ_BW_RD_UBOUND14 \
1326 0x12026cUL
1327#define PXP2_REG_RQ_BW_RD_UBOUND15 \
1328 0x120270UL
1329#define PXP2_REG_RQ_BW_RD_UBOUND16 \
1330 0x120274UL
1331#define PXP2_REG_RQ_BW_RD_UBOUND17 \
1332 0x120278UL
1333#define PXP2_REG_RQ_BW_RD_UBOUND18 \
1334 0x12027cUL
1335#define PXP2_REG_RQ_BW_RD_UBOUND19 \
1336 0x120280UL
1337#define PXP2_REG_RQ_BW_RD_UBOUND20 \
1338 0x120284UL
1339#define PXP2_REG_RQ_BW_RD_UBOUND22 \
1340 0x120288UL
1341#define PXP2_REG_RQ_BW_RD_UBOUND23 \
1342 0x12028cUL
1343#define PXP2_REG_RQ_BW_RD_UBOUND24 \
1344 0x120290UL
1345#define PXP2_REG_RQ_BW_RD_UBOUND25 \
1346 0x120294UL
1347#define PXP2_REG_RQ_BW_RD_UBOUND26 \
1348 0x120298UL
1349#define PXP2_REG_RQ_BW_RD_UBOUND27 \
1350 0x12029cUL
1351#define PXP2_REG_RQ_BW_RD_UBOUND4 \
1352 0x120244UL
1353#define PXP2_REG_RQ_BW_RD_UBOUND5 \
1354 0x120248UL
1355#define PXP2_REG_RQ_BW_WR_ADD29 \
1356 0x12022cUL
1357#define PXP2_REG_RQ_BW_WR_ADD30 \
1358 0x120230UL
1359#define PXP2_REG_RQ_BW_WR_L29 \
1360 0x12031cUL
1361#define PXP2_REG_RQ_BW_WR_L30 \
1362 0x120320UL
1363#define PXP2_REG_RQ_BW_WR_UBOUND29 \
1364 0x1202a4UL
1365#define PXP2_REG_RQ_BW_WR_UBOUND30 \
1366 0x1202a8UL
1367#define PXP2_REG_RQ_CDU_ENDIAN_M \
1368 0x1201a0UL
1369#define PXP2_REG_RQ_CDU_FIRST_ILT \
1370 0x12061cUL
1371#define PXP2_REG_RQ_CDU_LAST_ILT \
1372 0x120620UL
1373#define PXP2_REG_RQ_CDU_P_SIZE \
1374 0x120018UL
1375#define PXP2_REG_RQ_CFG_DONE \
1376 0x1201b4UL
1377#define PXP2_REG_RQ_DBG_ENDIAN_M \
1378 0x1201a4UL
1379#define PXP2_REG_RQ_DISABLE_INPUTS \
1380 0x120330UL
1381#define PXP2_REG_RQ_DRAM_ALIGN \
1382 0x1205b0UL
1383#define PXP2_REG_RQ_DRAM_ALIGN_RD \
1384 0x12092cUL
1385#define PXP2_REG_RQ_DRAM_ALIGN_SEL \
1386 0x120930UL
1387#define PXP2_REG_RQ_HC_ENDIAN_M \
1388 0x1201a8UL
1389#define PXP2_REG_RQ_ONCHIP_AT \
1390 0x122000UL
1391#define PXP2_REG_RQ_ONCHIP_AT_B0 \
1392 0x128000UL
1393#define PXP2_REG_RQ_PDR_LIMIT \
1394 0x12033cUL
1395#define PXP2_REG_RQ_QM_ENDIAN_M \
1396 0x120194UL
1397#define PXP2_REG_RQ_QM_FIRST_ILT \
1398 0x120634UL
1399#define PXP2_REG_RQ_QM_LAST_ILT \
1400 0x120638UL
1401#define PXP2_REG_RQ_QM_P_SIZE \
1402 0x120050UL
1403#define PXP2_REG_RQ_RBC_DONE \
1404 0x1201b0UL
1405#define PXP2_REG_RQ_RD_MBS0 \
1406 0x120160UL
1407#define PXP2_REG_RQ_RD_MBS1 \
1408 0x120168UL
1409#define PXP2_REG_RQ_SRC_ENDIAN_M \
1410 0x12019cUL
1411#define PXP2_REG_RQ_SRC_FIRST_ILT \
1412 0x12063cUL
1413#define PXP2_REG_RQ_SRC_LAST_ILT \
1414 0x120640UL
1415#define PXP2_REG_RQ_SRC_P_SIZE \
1416 0x12006cUL
1417#define PXP2_REG_RQ_TM_ENDIAN_M \
1418 0x120198UL
1419#define PXP2_REG_RQ_TM_FIRST_ILT \
1420 0x120644UL
1421#define PXP2_REG_RQ_TM_LAST_ILT \
1422 0x120648UL
1423#define PXP2_REG_RQ_TM_P_SIZE \
1424 0x120034UL
1425#define PXP2_REG_RQ_WR_MBS0 \
1426 0x12015cUL
1427#define PXP2_REG_RQ_WR_MBS1 \
1428 0x120164UL
1429#define PXP2_REG_WR_CDU_MPS \
1430 0x1205f0UL
1431#define PXP2_REG_WR_CSDM_MPS \
1432 0x1205d0UL
1433#define PXP2_REG_WR_DBG_MPS \
1434 0x1205e8UL
1435#define PXP2_REG_WR_DMAE_MPS \
1436 0x1205ecUL
1437#define PXP2_REG_WR_HC_MPS \
1438 0x1205c8UL
1439#define PXP2_REG_WR_QM_MPS \
1440 0x1205dcUL
1441#define PXP2_REG_WR_SRC_MPS \
1442 0x1205e4UL
1443#define PXP2_REG_WR_TM_MPS \
1444 0x1205e0UL
1445#define PXP2_REG_WR_TSDM_MPS \
1446 0x1205d4UL
1447#define PXP2_REG_WR_USDMDP_TH \
1448 0x120348UL
1449#define PXP2_REG_WR_USDM_MPS \
1450 0x1205ccUL
1451#define PXP2_REG_WR_XSDM_MPS \
1452 0x1205d8UL
1453#define PXP_REG_HST_DISCARD_DOORBELLS \
1454 0x1030a4UL
1455#define PXP_REG_HST_DISCARD_INTERNAL_WRITES \
1456 0x1030a8UL
1457#define PXP_REG_HST_ZONE_PERMISSION_TABLE \
1458 0x103400UL
1459#define PXP_REG_PXP_INT_MASK_0 \
1460 0x103074UL
1461#define PXP_REG_PXP_INT_MASK_1 \
1462 0x103084UL
1463#define PXP_REG_PXP_INT_STS_CLR_0 \
1464 0x10306cUL
1465#define PXP_REG_PXP_INT_STS_CLR_1 \
1466 0x10307cUL
1467#define PXP_REG_PXP_PRTY_MASK \
1468 0x103094UL
1469#define PXP_REG_PXP_PRTY_STS_CLR \
1470 0x10308cUL
1471#define QM_REG_BASEADDR \
1472 0x168900UL
1473#define QM_REG_BASEADDR_EXT_A \
1474 0x16e100UL
1475#define QM_REG_BYTECRDCMDQ_0 \
1476 0x16e6e8UL
1477#define QM_REG_CONNNUM_0 \
1478 0x168020UL
1479#define QM_REG_PF_EN \
1480 0x16e70cUL
1481#define QM_REG_PF_USG_CNT_0 \
1482 0x16e040UL
1483#define QM_REG_PTRTBL \
1484 0x168a00UL
1485#define QM_REG_PTRTBL_EXT_A \
1486 0x16e200UL
1487#define QM_REG_QM_INT_MASK \
1488 0x168444UL
1489#define QM_REG_QM_PRTY_MASK \
1490 0x168454UL
1491#define QM_REG_QM_PRTY_STS_CLR \
1492 0x16844cUL
1493#define QM_REG_QVOQIDX_0 \
1494 0x1680f4UL
1495#define QM_REG_SOFT_RESET \
1496 0x168428UL
1497#define QM_REG_VOQQMASK_0_LSB \
1498 0x168240UL
1499#define SEM_FAST_REG_PARITY_RST \
1500 0x18840UL
1501#define SRC_REG_COUNTFREE0 \
1502 0x40500UL
1503#define SRC_REG_FIRSTFREE0 \
1504 0x40510UL
1505#define SRC_REG_KEYSEARCH_0 \
1506 0x40458UL
1507#define SRC_REG_KEYSEARCH_1 \
1508 0x4045cUL
1509#define SRC_REG_KEYSEARCH_2 \
1510 0x40460UL
1511#define SRC_REG_KEYSEARCH_3 \
1512 0x40464UL
1513#define SRC_REG_KEYSEARCH_4 \
1514 0x40468UL
1515#define SRC_REG_KEYSEARCH_5 \
1516 0x4046cUL
1517#define SRC_REG_KEYSEARCH_6 \
1518 0x40470UL
1519#define SRC_REG_KEYSEARCH_7 \
1520 0x40474UL
1521#define SRC_REG_KEYSEARCH_8 \
1522 0x40478UL
1523#define SRC_REG_KEYSEARCH_9 \
1524 0x4047cUL
1525#define SRC_REG_LASTFREE0 \
1526 0x40530UL
1527#define SRC_REG_NUMBER_HASH_BITS0 \
1528 0x40400UL
1529#define SRC_REG_SOFT_RST \
1530 0x4049cUL
1531#define SRC_REG_SRC_PRTY_MASK \
1532 0x404c8UL
1533#define SRC_REG_SRC_PRTY_STS_CLR \
1534 0x404c0UL
1535#define TCM_REG_PRS_IFEN \
1536 0x50020UL
1537#define TCM_REG_TCM_INT_MASK \
1538 0x501dcUL
1539#define TCM_REG_TCM_PRTY_MASK \
1540 0x501ecUL
1541#define TCM_REG_TCM_PRTY_STS_CLR \
1542 0x501e4UL
1543#define TM_REG_EN_LINEAR0_TIMER \
1544 0x164014UL
1545#define TM_REG_LIN0_MAX_ACTIVE_CID \
1546 0x164048UL
1547#define TM_REG_LIN0_NUM_SCANS \
1548 0x1640a0UL
1549#define TM_REG_LIN0_SCAN_ON \
1550 0x1640d0UL
1551#define TM_REG_LIN0_SCAN_TIME \
1552 0x16403cUL
1553#define TM_REG_LIN0_VNIC_UC \
1554 0x164128UL
1555#define TM_REG_TM_INT_MASK \
1556 0x1640fcUL
1557#define TM_REG_TM_PRTY_MASK \
1558 0x16410cUL
1559#define TM_REG_TM_PRTY_STS_CLR \
1560 0x164104UL
1561#define TSDM_REG_ENABLE_IN1 \
1562 0x42238UL
1563#define TSDM_REG_TSDM_INT_MASK_0 \
1564 0x4229cUL
1565#define TSDM_REG_TSDM_INT_MASK_1 \
1566 0x422acUL
1567#define TSDM_REG_TSDM_PRTY_MASK \
1568 0x422bcUL
1569#define TSDM_REG_TSDM_PRTY_STS_CLR \
1570 0x422b4UL
1571#define TSEM_REG_FAST_MEMORY \
1572 0x1a0000UL
1573#define TSEM_REG_INT_TABLE \
1574 0x180400UL
1575#define TSEM_REG_PASSIVE_BUFFER \
1576 0x181000UL
1577#define TSEM_REG_PRAM \
1578 0x1c0000UL
1579#define TSEM_REG_TSEM_INT_MASK_0 \
1580 0x180100UL
1581#define TSEM_REG_TSEM_INT_MASK_1 \
1582 0x180110UL
1583#define TSEM_REG_TSEM_PRTY_MASK_0 \
1584 0x180120UL
1585#define TSEM_REG_TSEM_PRTY_MASK_1 \
1586 0x180130UL
1587#define TSEM_REG_TSEM_PRTY_STS_CLR_0 \
1588 0x180118UL
1589#define TSEM_REG_TSEM_PRTY_STS_CLR_1 \
1590 0x180128UL
1591#define TSEM_REG_VFPF_ERR_NUM \
1592 0x180380UL
1593#define UCM_REG_UCM_INT_MASK \
1594 0xe01d4UL
1595#define UCM_REG_UCM_PRTY_MASK \
1596 0xe01e4UL
1597#define UCM_REG_UCM_PRTY_STS_CLR \
1598 0xe01dcUL
1599#define UMAC_COMMAND_CONFIG_REG_HD_ENA \
1600 (0x1<<10)
1601#define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE \
1602 (0x1<<28)
1603#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA \
1604 (0x1<<15)
1605#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK \
1606 (0x1<<24)
1607#define UMAC_COMMAND_CONFIG_REG_PAD_EN \
1608 (0x1<<5)
1609#define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE \
1610 (0x1<<8)
1611#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN \
1612 (0x1<<4)
1613#define UMAC_COMMAND_CONFIG_REG_RX_ENA \
1614 (0x1<<1)
1615#define UMAC_COMMAND_CONFIG_REG_SW_RESET \
1616 (0x1<<13)
1617#define UMAC_COMMAND_CONFIG_REG_TX_ENA \
1618 (0x1<<0)
1619#define UMAC_REG_COMMAND_CONFIG \
1620 0x8UL
1621#define UMAC_REG_EEE_WAKE_TIMER \
1622 0x6cUL
1623#define UMAC_REG_MAC_ADDR0 \
1624 0xcUL
1625#define UMAC_REG_MAC_ADDR1 \
1626 0x10UL
1627#define UMAC_REG_MAXFR \
1628 0x14UL
1629#define UMAC_REG_UMAC_EEE_CTRL \
1630 0x64UL
1631#define UMAC_UMAC_EEE_CTRL_REG_EEE_EN \
1632 (0x1<<3)
1633#define USDM_REG_USDM_INT_MASK_0 \
1634 0xc42a0UL
1635#define USDM_REG_USDM_INT_MASK_1 \
1636 0xc42b0UL
1637#define USDM_REG_USDM_PRTY_MASK \
1638 0xc42c0UL
1639#define USDM_REG_USDM_PRTY_STS_CLR \
1640 0xc42b8UL
1641#define USEM_REG_FAST_MEMORY \
1642 0x320000UL
1643#define USEM_REG_INT_TABLE \
1644 0x300400UL
1645#define USEM_REG_PASSIVE_BUFFER \
1646 0x302000UL
1647#define USEM_REG_PRAM \
1648 0x340000UL
1649#define USEM_REG_USEM_INT_MASK_0 \
1650 0x300110UL
1651#define USEM_REG_USEM_INT_MASK_1 \
1652 0x300120UL
1653#define USEM_REG_USEM_PRTY_MASK_0 \
1654 0x300130UL
1655#define USEM_REG_USEM_PRTY_MASK_1 \
1656 0x300140UL
1657#define USEM_REG_USEM_PRTY_STS_CLR_0 \
1658 0x300128UL
1659#define USEM_REG_USEM_PRTY_STS_CLR_1 \
1660 0x300138UL
1661#define USEM_REG_VFPF_ERR_NUM \
1662 0x300380UL
1663#define VFC_MEMORIES_RST_REG_CAM_RST \
1664 (0x1<<0)
1665#define VFC_MEMORIES_RST_REG_RAM_RST \
1666 (0x1<<1)
1667#define VFC_REG_MEMORIES_RST \
1668 0x1943cUL
1669#define XCM_REG_XCM_INT_MASK \
1670 0x202b4UL
1671#define XCM_REG_XCM_PRTY_MASK \
1672 0x202c4UL
1673#define XCM_REG_XCM_PRTY_STS_CLR \
1674 0x202bcUL
1675#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS \
1676 (0x1<<0)
1677#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS \
1678 (0x1<<1)
1679#define XMAC_CTRL_REG_LINE_LOCAL_LPBK \
1680 (0x1<<2)
1681#define XMAC_CTRL_REG_RX_EN \
1682 (0x1<<1)
1683#define XMAC_CTRL_REG_SOFT_RESET \
1684 (0x1<<6)
1685#define XMAC_CTRL_REG_TX_EN \
1686 (0x1<<0)
1687#define XMAC_CTRL_REG_XLGMII_ALIGN_ENB \
1688 (0x1<<7)
1689#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN \
1690 (0x1<<18)
1691#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN \
1692 (0x1<<17)
1693#define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON \
1694 (0x1<<1)
1695#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN \
1696 (0x1<<0)
1697#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN \
1698 (0x1<<3)
1699#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN \
1700 (0x1<<4)
1701#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN \
1702 (0x1<<5)
1703#define XMAC_REG_CLEAR_RX_LSS_STATUS \
1704 0x60UL
1705#define XMAC_REG_CTRL \
1706 0UL
1707#define XMAC_REG_CTRL_SA_HI \
1708 0x2cUL
1709#define XMAC_REG_CTRL_SA_LO \
1710 0x28UL
1711#define XMAC_REG_EEE_CTRL \
1712 0xd8UL
1713#define XMAC_REG_EEE_TIMERS_HI \
1714 0xe4UL
1715#define XMAC_REG_PAUSE_CTRL \
1716 0x68UL
1717#define XMAC_REG_PFC_CTRL \
1718 0x70UL
1719#define XMAC_REG_PFC_CTRL_HI \
1720 0x74UL
1721#define XMAC_REG_RX_LSS_CTRL \
1722 0x50UL
1723#define XMAC_REG_RX_LSS_STATUS \
1724 0x58UL
1725#define XMAC_REG_RX_MAX_SIZE \
1726 0x40UL
1727#define XMAC_REG_TX_CTRL \
1728 0x20UL
1729#define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE \
1730 (0x1<<0)
1731#define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE \
1732 (0x1<<1)
1733#define XSDM_REG_OPERATION_GEN \
1734 0x1664c4UL
1735#define XSDM_REG_XSDM_INT_MASK_0 \
1736 0x16629cUL
1737#define XSDM_REG_XSDM_INT_MASK_1 \
1738 0x1662acUL
1739#define XSDM_REG_XSDM_PRTY_MASK \
1740 0x1662bcUL
1741#define XSDM_REG_XSDM_PRTY_STS_CLR \
1742 0x1662b4UL
1743#define XSEM_REG_FAST_MEMORY \
1744 0x2a0000UL
1745#define XSEM_REG_INT_TABLE \
1746 0x280400UL
1747#define XSEM_REG_PASSIVE_BUFFER \
1748 0x282000UL
1749#define XSEM_REG_PRAM \
1750 0x2c0000UL
1751#define XSEM_REG_VFPF_ERR_NUM \
1752 0x280380UL
1753#define XSEM_REG_XSEM_INT_MASK_0 \
1754 0x280110UL
1755#define XSEM_REG_XSEM_INT_MASK_1 \
1756 0x280120UL
1757#define XSEM_REG_XSEM_PRTY_MASK_0 \
1758 0x280130UL
1759#define XSEM_REG_XSEM_PRTY_MASK_1 \
1760 0x280140UL
1761#define XSEM_REG_XSEM_PRTY_STS_CLR_0 \
1762 0x280128UL
1763#define XSEM_REG_XSEM_PRTY_STS_CLR_1 \
1764 0x280138UL
1765#define MCPR_ACCESS_LOCK_LOCK (1L<<31)
1766#define MCPR_IMC_COMMAND_ENABLE (1L<<31)
1767#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16
1768#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28
1769#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8
1770#define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
1771#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
1772#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
1773#define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
1774#define MCPR_NVM_COMMAND_DOIT (1L<<4)
1775#define MCPR_NVM_COMMAND_DONE (1L<<3)
1776#define MCPR_NVM_COMMAND_FIRST (1L<<7)
1777#define MCPR_NVM_COMMAND_LAST (1L<<8)
1778#define MCPR_NVM_COMMAND_WR (1L<<5)
1779#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
1780#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
1781#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
1782
1783
1784#define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
1785#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
1786#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
1787#define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
1788#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
1789#define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3)
1790#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
1791#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
1792#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
1793#define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
1794#define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
1795#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
1796#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
1797#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
1798#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
1799#define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3)
1800#define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
1801#define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3)
1802#define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3)
1803#define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3)
1804#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3)
1805#define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3)
1806#define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3)
1807#define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3)
1808#define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3)
1809#define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3)
1810#define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3)
1811#define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3)
1812#define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3)
1813#define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3)
1814#define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3)
1815
1816
1817#define EMAC_LED_1000MB_OVERRIDE (1L<<1)
1818#define EMAC_LED_100MB_OVERRIDE (1L<<2)
1819#define EMAC_LED_10MB_OVERRIDE (1L<<3)
1820#define EMAC_LED_OVERRIDE (1L<<0)
1821#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
1822#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
1823#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
1824#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
1825#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
1826#define EMAC_MDIO_COMM_DATA (0xffffL<<0)
1827#define EMAC_MDIO_COMM_START_BUSY (1L<<29)
1828#define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
1829#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
1830#define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL<<16)
1831#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
1832#define EMAC_MDIO_STATUS_10MB (1L<<1)
1833#define EMAC_MODE_25G_MODE (1L<<5)
1834#define EMAC_MODE_HALF_DUPLEX (1L<<1)
1835#define EMAC_MODE_PORT_GMII (2L<<2)
1836#define EMAC_MODE_PORT_MII (1L<<2)
1837#define EMAC_MODE_PORT_MII_10M (3L<<2)
1838#define EMAC_MODE_RESET (1L<<0)
1839#define EMAC_REG_EMAC_LED 0xc
1840#define EMAC_REG_EMAC_MAC_MATCH 0x10
1841#define EMAC_REG_EMAC_MDIO_COMM 0xac
1842#define EMAC_REG_EMAC_MDIO_MODE 0xb4
1843#define EMAC_REG_EMAC_MDIO_STATUS 0xb0
1844#define EMAC_REG_EMAC_MODE 0x0
1845#define EMAC_REG_EMAC_RX_MODE 0xc8
1846#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
1847#define EMAC_REG_EMAC_RX_STAT_AC 0x180
1848#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
1849#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
1850#define EMAC_REG_EMAC_TX_MODE 0xbc
1851#define EMAC_REG_EMAC_TX_STAT_AC 0x280
1852#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
1853#define EMAC_REG_RX_PFC_MODE 0x320
1854#define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2)
1855#define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1)
1856#define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0)
1857#define EMAC_REG_RX_PFC_PARAM 0x324
1858#define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0
1859#define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16
1860#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328
1861#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0)
1862#define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330
1863#define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0)
1864#define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c
1865#define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0)
1866#define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334
1867#define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0)
1868#define EMAC_RX_MODE_FLOW_EN (1L<<2)
1869#define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
1870#define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
1871#define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
1872#define EMAC_RX_MODE_RESET (1L<<0)
1873#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
1874#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
1875#define EMAC_TX_MODE_FLOW_EN (1L<<4)
1876#define EMAC_TX_MODE_RESET (1L<<0)
1877
1878
1879#define MISC_REGISTERS_GPIO_0 0
1880#define MISC_REGISTERS_GPIO_1 1
1881#define MISC_REGISTERS_GPIO_2 2
1882#define MISC_REGISTERS_GPIO_3 3
1883#define MISC_REGISTERS_GPIO_CLR_POS 16
1884#define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
1885#define MISC_REGISTERS_GPIO_FLOAT_POS 24
1886#define MISC_REGISTERS_GPIO_HIGH 1
1887#define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
1888#define MISC_REGISTERS_GPIO_INT_CLR_POS 24
1889#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
1890#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1
1891#define MISC_REGISTERS_GPIO_INT_SET_POS 16
1892#define MISC_REGISTERS_GPIO_LOW 0
1893#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
1894#define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
1895#define MISC_REGISTERS_GPIO_PORT_SHIFT 4
1896#define MISC_REGISTERS_GPIO_SET_POS 8
1897#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
1898#define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0)
1899#define MISC_REGISTERS_RESET_REG_1_RST_DORQ \
1900 (0x1<<19)
1901#define MISC_REGISTERS_RESET_REG_1_RST_HC \
1902 (0x1<<29)
1903#define MISC_REGISTERS_RESET_REG_1_RST_PXP \
1904 (0x1<<26)
1905#define MISC_REGISTERS_RESET_REG_1_RST_PXPV \
1906 (0x1<<27)
1907#define MISC_REGISTERS_RESET_REG_1_RST_QM \
1908 (0x1<<17)
1909#define MISC_REGISTERS_RESET_REG_1_SET 0x584
1910#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
1911#define MISC_REGISTERS_RESET_REG_2_MSTAT0 \
1912 (0x1<<24)
1913#define MISC_REGISTERS_RESET_REG_2_MSTAT1 \
1914 (0x1<<25)
1915#define MISC_REGISTERS_RESET_REG_2_PGLC \
1916 (0x1<<19)
1917#define MISC_REGISTERS_RESET_REG_2_RST_ATC \
1918 (0x1<<17)
1919#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
1920#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1)
1921#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2)
1922#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE \
1923 (0x1<<14)
1924#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3)
1925#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE \
1926 (0x1<<15)
1927#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
1928#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
1929#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8)
1930#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7)
1931#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
1932#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE \
1933 (0x1<<11)
1934#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO \
1935 (0x1<<13)
1936#define MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR \
1937 (0x1<<16)
1938#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
1939#define MISC_REGISTERS_RESET_REG_2_SET 0x594
1940#define MISC_REGISTERS_RESET_REG_2_UMAC0 \
1941 (0x1<<20)
1942#define MISC_REGISTERS_RESET_REG_2_UMAC1 \
1943 (0x1<<21)
1944#define MISC_REGISTERS_RESET_REG_2_XMAC \
1945 (0x1<<22)
1946#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT \
1947 (0x1<<23)
1948#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
1949#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
1950#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
1951#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
1952#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
1953#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
1954#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
1955#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
1956#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
1957#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
1958#define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
1959#define MISC_SPIO_CLR_POS 16
1960#define MISC_SPIO_FLOAT (0xffL<<24)
1961#define MISC_SPIO_FLOAT_POS 24
1962#define MISC_SPIO_INPUT_HI_Z 2
1963#define MISC_SPIO_INT_OLD_SET_POS 16
1964#define MISC_SPIO_OUTPUT_HIGH 1
1965#define MISC_SPIO_OUTPUT_LOW 0
1966#define MISC_SPIO_SET_POS 8
1967#define MISC_SPIO_SPIO4 0x10
1968#define MISC_SPIO_SPIO5 0x20
1969#define HW_LOCK_MAX_RESOURCE_VALUE 31
1970#define HW_LOCK_RESOURCE_DRV_FLAGS 10
1971#define HW_LOCK_RESOURCE_GPIO 1
1972#define HW_LOCK_RESOURCE_NVRAM 12
1973#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
1974#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8
1975#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9
1976#define HW_LOCK_RESOURCE_RECOVERY_REG 11
1977#define HW_LOCK_RESOURCE_RESET 5
1978#define HW_LOCK_RESOURCE_SPIO 2
1979
1980
1981#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)
1982#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)
1983#define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT (0x1<<19)
1984#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18)
1985#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31)
1986#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30)
1987#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9)
1988#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8)
1989#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7)
1990#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6)
1991#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29)
1992#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28)
1993#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1)
1994#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0)
1995#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18)
1996#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11)
1997#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10)
1998#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13)
1999#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12)
2000#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2)
2001#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12)
2002#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28)
2003#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1UL<<31)
2004#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29)
2005#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30)
2006#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15)
2007#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14)
2008#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14)
2009#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20)
2010#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1UL<<31)
2011#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30)
2012#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0)
2013#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2)
2014#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)
2015#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5)
2016#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4)
2017#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3)
2018#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2)
2019#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3)
2020#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2)
2021#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22)
2022#define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15)
2023#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27)
2024#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26)
2025#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5)
2026#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4)
2027#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25)
2028#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24)
2029#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29)
2030#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28)
2031#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23)
2032#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22)
2033#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27)
2034#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26)
2035#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21)
2036#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20)
2037#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25)
2038#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24)
2039#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16)
2040#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9)
2041#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8)
2042#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7)
2043#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6)
2044#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11)
2045#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10)
2046#define HW_PRTY_ASSERT_SET_0 \
2047(AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR |\
2048 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR |\
2049 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR |\
2050 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
2051 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
2052 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
2053 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
2054#define HW_PRTY_ASSERT_SET_1 \
2055(AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
2056 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR |\
2057 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
2058 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR |\
2059 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
2060 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR |\
2061 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
2062 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
2063 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
2064 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR |\
2065 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR |\
2066 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
2067 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR |\
2068 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR |\
2069 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
2070 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
2071#define HW_PRTY_ASSERT_SET_2 \
2072(AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR |\
2073 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR |\
2074 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
2075 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR |\
2076 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR |\
2077 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
2078 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR |\
2079 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
2080#define HW_PRTY_ASSERT_SET_3 \
2081(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
2082 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
2083 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
2084 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
2085#define HW_PRTY_ASSERT_SET_4 \
2086(AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |\
2087 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
2088#define HW_INTERRUT_ASSERT_SET_0 \
2089(AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT |\
2090 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT |\
2091 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT |\
2092 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT |\
2093 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
2094#define HW_INTERRUT_ASSERT_SET_1 \
2095(AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT |\
2096 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT |\
2097 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT |\
2098 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT |\
2099 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT |\
2100 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT |\
2101 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT |\
2102 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT |\
2103 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT |\
2104 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT |\
2105 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
2106#define HW_INTERRUT_ASSERT_SET_2 \
2107(AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT |\
2108 AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT |\
2109 AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT |\
2110 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT |\
2111 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT |\
2112 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
2113 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
2114
2115
2116#define RESERVED_GENERAL_ATTENTION_BIT_0 0
2117
2118#define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0
2119#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
2120
2121#define RESERVED_GENERAL_ATTENTION_BIT_6 6
2122#define RESERVED_GENERAL_ATTENTION_BIT_7 7
2123#define RESERVED_GENERAL_ATTENTION_BIT_8 8
2124#define RESERVED_GENERAL_ATTENTION_BIT_9 9
2125#define RESERVED_GENERAL_ATTENTION_BIT_10 10
2126#define RESERVED_GENERAL_ATTENTION_BIT_11 11
2127#define RESERVED_GENERAL_ATTENTION_BIT_12 12
2128#define RESERVED_GENERAL_ATTENTION_BIT_13 13
2129#define RESERVED_GENERAL_ATTENTION_BIT_14 14
2130#define RESERVED_GENERAL_ATTENTION_BIT_15 15
2131#define RESERVED_GENERAL_ATTENTION_BIT_16 16
2132#define RESERVED_GENERAL_ATTENTION_BIT_17 17
2133#define RESERVED_GENERAL_ATTENTION_BIT_18 18
2134#define RESERVED_GENERAL_ATTENTION_BIT_19 19
2135#define RESERVED_GENERAL_ATTENTION_BIT_20 20
2136#define RESERVED_GENERAL_ATTENTION_BIT_21 21
2137
2138/* storm asserts attention bits */
2139#define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7
2140#define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8
2141#define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9
2142#define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10
2143
2144/* mcp error attention bit */
2145#define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
2146
2147/*E1H NIG status sync attention mapped to group 4-7*/
2148#define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12
2149#define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13
2150#define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14
2151#define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15
2152#define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16
2153#define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17
2154#define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18
2155#define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19
2156
2157 /* Used For Error Recovery: changing this will require more \
2158 changes in code that assume
2159 * error recovery uses general attn bit20 ! */
2160#define ERROR_RECOVERY_ATTENTION_BIT \
2161 RESERVED_GENERAL_ATTENTION_BIT_20
2162#define RESERVED_ATTENTION_BIT \
2163 RESERVED_GENERAL_ATTENTION_BIT_21
2164
2165#define LATCHED_ATTN_RBCR 23
2166#define LATCHED_ATTN_RBCT 24
2167#define LATCHED_ATTN_RBCN 25
2168#define LATCHED_ATTN_RBCU 26
2169#define LATCHED_ATTN_RBCP 27
2170#define LATCHED_ATTN_TIMEOUT_GRC 28
2171#define LATCHED_ATTN_RSVD_GRC 29
2172#define LATCHED_ATTN_ROM_PARITY_MCP 30
2173#define LATCHED_ATTN_UM_RX_PARITY_MCP 31
2174#define LATCHED_ATTN_UM_TX_PARITY_MCP 32
2175#define LATCHED_ATTN_SCPAD_PARITY_MCP 33
2176
2177#define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
2178#define GENERAL_ATTEN_OFFSET(atten_name) (1UL << ((94 + atten_name) % 32))
2179
2180
2181/*
2182 * This file defines GRC base address for every block.
2183 * This file is included by chipsim, asm microcode and cpp microcode.
2184 * These values are used in Design.xml on regBase attribute
2185 * Use the base with the generated offsets of specific registers.
2186 */
2187
2188#define GRCBASE_PXPCS 0x000000
2189#define GRCBASE_PCICONFIG 0x002000
2190#define GRCBASE_PCIREG 0x002400
2191#define GRCBASE_EMAC0 0x008000
2192#define GRCBASE_EMAC1 0x008400
2193#define GRCBASE_DBU 0x008800
2194#define GRCBASE_PGLUE_B 0x009000
2195#define GRCBASE_MISC 0x00A000
2196#define GRCBASE_DBG 0x00C000
2197#define GRCBASE_NIG 0x010000
2198#define GRCBASE_XCM 0x020000
2199#define GRCBASE_PRS 0x040000
2200#define GRCBASE_SRCH 0x040400
2201#define GRCBASE_TSDM 0x042000
2202#define GRCBASE_TCM 0x050000
2203#define GRCBASE_BRB1 0x060000
2204#define GRCBASE_MCP 0x080000
2205#define GRCBASE_UPB 0x0C1000
2206#define GRCBASE_CSDM 0x0C2000
2207#define GRCBASE_USDM 0x0C4000
2208#define GRCBASE_CCM 0x0D0000
2209#define GRCBASE_UCM 0x0E0000
2210#define GRCBASE_CDU 0x101000
2211#define GRCBASE_DMAE 0x102000
2212#define GRCBASE_PXP 0x103000
2213#define GRCBASE_CFC 0x104000
2214#define GRCBASE_HC 0x108000
2215#define GRCBASE_ATC 0x110000
2216#define GRCBASE_PXP2 0x120000
2217#define GRCBASE_IGU 0x130000
2218#define GRCBASE_PBF 0x140000
2219#define GRCBASE_UMAC0 0x160000
2220#define GRCBASE_UMAC1 0x160400
2221#define GRCBASE_XPB 0x161000
2222#define GRCBASE_MSTAT0 0x162000
2223#define GRCBASE_MSTAT1 0x162800
2224#define GRCBASE_XMAC0 0x163000
2225#define GRCBASE_XMAC1 0x163800
2226#define GRCBASE_TIMERS 0x164000
2227#define GRCBASE_XSDM 0x166000
2228#define GRCBASE_QM 0x168000
2229#define GRCBASE_QM_4PORT 0x168000
2230#define GRCBASE_DQ 0x170000
2231#define GRCBASE_TSEM 0x180000
2232#define GRCBASE_CSEM 0x200000
2233#define GRCBASE_XSEM 0x280000
2234#define GRCBASE_XSEM_4PORT 0x280000
2235#define GRCBASE_USEM 0x300000
2236#define GRCBASE_MCP_A 0x380000
2237#define GRCBASE_MISC_AEU GRCBASE_MISC
2238#define GRCBASE_Tstorm GRCBASE_TSEM
2239#define GRCBASE_Cstorm GRCBASE_CSEM
2240#define GRCBASE_Xstorm GRCBASE_XSEM
2241#define GRCBASE_Ustorm GRCBASE_USEM
2242
2243
2244/* offset of configuration space in the pci core register */
2245#define PCICFG_OFFSET 0x2000
2246#define PCICFG_VENDOR_ID_OFFSET 0x00
2247#define PCICFG_DEVICE_ID_OFFSET 0x02
2248#define PCICFG_COMMAND_OFFSET 0x04
2249#define PCICFG_COMMAND_IO_SPACE (1<<0)
2250#define PCICFG_COMMAND_MEM_SPACE (1<<1)
2251#define PCICFG_COMMAND_BUS_MASTER (1<<2)
2252#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
2253#define PCICFG_COMMAND_MWI_CYCLES (1<<4)
2254#define PCICFG_COMMAND_VGA_SNOOP (1<<5)
2255#define PCICFG_COMMAND_PERR_ENA (1<<6)
2256#define PCICFG_COMMAND_STEPPING (1<<7)
2257#define PCICFG_COMMAND_SERR_ENA (1<<8)
2258#define PCICFG_COMMAND_FAST_B2B (1<<9)
2259#define PCICFG_COMMAND_INT_DISABLE (1<<10)
2260#define PCICFG_COMMAND_RESERVED (0x1f<<11)
2261#define PCICFG_STATUS_OFFSET 0x06
2262#define PCICFG_REVISION_ID_OFFSET 0x08
2263#define PCICFG_REVESION_ID_MASK 0xff
2264#define PCICFG_REVESION_ID_ERROR_VAL 0xff
2265#define PCICFG_CACHE_LINE_SIZE 0x0c
2266#define PCICFG_LATENCY_TIMER 0x0d
2267#define PCICFG_HEADER_TYPE 0x0e
2268#define PCICFG_HEADER_TYPE_NORMAL 0
2269#define PCICFG_HEADER_TYPE_BRIDGE 1
2270#define PCICFG_HEADER_TYPE_CARDBUS 2
2271#define PCICFG_BAR_1_LOW 0x10
2272#define PCICFG_BAR_1_HIGH 0x14
2273#define PCICFG_BAR_2_LOW 0x18
2274#define PCICFG_BAR_2_HIGH 0x1c
2275#define PCICFG_BAR_3_LOW 0x20
2276#define PCICFG_BAR_3_HIGH 0x24
2277#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
2278#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
2279#define PCICFG_INT_LINE 0x3c
2280#define PCICFG_INT_PIN 0x3d
2281#define PCICFG_PM_CAPABILITY 0x48
2282#define PCICFG_PM_CAPABILITY_VERSION (0x3<<16)
2283#define PCICFG_PM_CAPABILITY_CLOCK (1<<19)
2284#define PCICFG_PM_CAPABILITY_RESERVED (1<<20)
2285#define PCICFG_PM_CAPABILITY_DSI (1<<21)
2286#define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)
2287#define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25)
2288#define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26)
2289#define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27)
2290#define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28)
2291#define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29)
2292#define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30)
2293#define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31)
2294#define PCICFG_PM_CSR_OFFSET 0x4c
2295#define PCICFG_PM_CSR_STATE (0x3<<0)
2296#define PCICFG_PM_CSR_PME_ENABLE (1<<8)
2297#define PCICFG_PM_CSR_PME_STATUS (1<<15)
2298#define PCICFG_VPD_FLAG_ADDR_OFFSET 0x50
2299#define PCICFG_VPD_DATA_OFFSET 0x54
2300#define PCICFG_MSI_CAP_ID_OFFSET 0x58
2301#define PCICFG_MSI_CONTROL_ENABLE (0x1<<16)
2302#define PCICFG_MSI_CONTROL_MCAP (0x7<<17)
2303#define PCICFG_MSI_CONTROL_MENA (0x7<<20)
2304#define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23)
2305#define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24)
2306#define PCICFG_MSI_ADDR_LOW_OFFSET 0x5c
2307#define PCICFG_MSI_ADDR_HIGH_OFFSET 0x60
2308#define PCICFG_MSI_DATA_OFFSET 0x64
2309#define PCICFG_GRC_ADDRESS 0x78
2310#define PCICFG_GRC_DATA 0x80
2311#define PCICFG_ME_REGISTER 0x98
2312#define PCICFG_MSIX_CAP_ID_OFFSET 0xa0
2313#define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16)
2314#define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27)
2315#define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30)
2316#define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31)
2317
2318#define PCICFG_DEVICE_CONTROL 0xb4
2319#define PCICFG_DEVICE_CONTROL_NP_TRANSACTION_PEND (1<<21)
2320#define PCICFG_DEVICE_STATUS 0xb6
2321#define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0)
2322#define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1)
2323#define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2)
2324#define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3)
2325#define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4)
2326#define PCICFG_DEVICE_STATUS_NO_PEND (1<<5)
2327#define PCICFG_LINK_CONTROL 0xbc
2328
2329
2330/* config_2 offset */
2331#define GRC_CONFIG_2_SIZE_REG 0x408
2332#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
2333#define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
2334#define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
2335#define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
2336#define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
2337#define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
2338#define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
2339#define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
2340#define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
2341#define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
2342#define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
2343#define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
2344#define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
2345#define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
2346#define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
2347#define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
2348#define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
2349#define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
2350#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
2351#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
2352#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
2353#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
2354#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
2355#define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
2356#define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
2357#define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
2358#define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)
2359#define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)
2360#define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)
2361#define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)
2362#define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)
2363#define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)
2364#define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)
2365#define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)
2366#define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)
2367#define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
2368#define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
2369#define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
2370#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
2371#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
2372
2373/* config_3 offset */
2374#define GRC_CONFIG_3_SIZE_REG 0x40c
2375#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
2376#define PCI_CONFIG_3_FORCE_PME (1L<<24)
2377#define PCI_CONFIG_3_PME_STATUS (1L<<25)
2378#define PCI_CONFIG_3_PME_ENABLE (1L<<26)
2379#define PCI_CONFIG_3_PM_STATE (0x3L<<27)
2380#define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
2381#define PCI_CONFIG_3_PCI_POWER (1L<<31)
2382
2383#define GRC_REG_DEVICE_CONTROL 0x4d8
2384#define PCIE_SRIOV_DISABLE_IN_PROGRESS \
2385 (1 << 29) /*When VF Enable is cleared(after it was previously set),
2386 this register will read a value of 1, indicating that all the
2387 VFs that belong to this PF should be flushed.
2388 Software should clear this bit within 1 second of VF Enable
2389 being set by writing a 1 to it, so that VFs are visible to the system again.
2390 WC */
2391#define PCIE_FLR_IN_PROGRESS \
2392 (1 << 27) /*When FLR is initiated, this register will read a \
2393 value of 1 indicating that the
2394 Function is in FLR state. Func can be brought out of FLR state either by
2395 writing 1 to this register (at least 50 ms after FLR was initiated),
2396 or it can also be cleared automatically after 55 ms if auto_clear bit
2397 in private reg space is set. This bit also exists in VF register space
2398 WC */
2399
2400#define GRC_BAR2_CONFIG 0x4e0
2401#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
2402#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
2403#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
2404#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
2405#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
2406#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
2407#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
2408#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
2409#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
2410#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
2411#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
2412#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
2413#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
2414#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
2415#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
2416#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
2417#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
2418#define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
2419
2420#define GRC_BAR3_CONFIG 0x4f4
2421#define PCI_CONFIG_2_BAR3_SIZE (0xfL<<0)
2422#define PCI_CONFIG_2_BAR3_SIZE_DISABLED (0L<<0)
2423#define PCI_CONFIG_2_BAR3_SIZE_64K (1L<<0)
2424#define PCI_CONFIG_2_BAR3_SIZE_128K (2L<<0)
2425#define PCI_CONFIG_2_BAR3_SIZE_256K (3L<<0)
2426#define PCI_CONFIG_2_BAR3_SIZE_512K (4L<<0)
2427#define PCI_CONFIG_2_BAR3_SIZE_1M (5L<<0)
2428#define PCI_CONFIG_2_BAR3_SIZE_2M (6L<<0)
2429#define PCI_CONFIG_2_BAR3_SIZE_4M (7L<<0)
2430#define PCI_CONFIG_2_BAR3_SIZE_8M (8L<<0)
2431#define PCI_CONFIG_2_BAR3_SIZE_16M (9L<<0)
2432#define PCI_CONFIG_2_BAR3_SIZE_32M (10L<<0)
2433#define PCI_CONFIG_2_BAR3_SIZE_64M (11L<<0)
2434#define PCI_CONFIG_2_BAR3_SIZE_128M (12L<<0)
2435#define PCI_CONFIG_2_BAR3_SIZE_256M (13L<<0)
2436#define PCI_CONFIG_2_BAR3_SIZE_512M (14L<<0)
2437#define PCI_CONFIG_2_BAR3_SIZE_1G (15L<<0)
2438#define PCI_CONFIG_2_BAR3_64ENA (1L<<4)
2439
2440#define PCI_PM_DATA_A 0x410
2441#define PCI_PM_DATA_B 0x414
2442#define PCI_ID_VAL1 0x434
2443#define PCI_ID_VAL2 0x438
2444#define PCI_ID_VAL3 0x43c
2445#define PCI_ID_VAL3_REVISION_ID_ERROR (0xffL<<24)
2446
2447
2448#define GRC_CONFIG_REG_VF_BAR_REG_1 0x608
2449#define GRC_CONFIG_REG_VF_BAR_REG_BAR0_SIZE 0xf
2450
2451#define GRC_CONFIG_REG_VF_MSIX_CONTROL 0x61C
2452#define GRC_CR_VF_MSIX_CTRL_VF_MSIX_TBL_SIZE_MASK \
2453 0x3F /*This field resides in VF only and does not exist in PF.
2454 This register controls the read value of the MSIX_CONTROL[10:0] register
2455 in the VF configuration space. A value of "00000000011" indicates
2456 a table size of 4. The value is controlled by IOV_MSIX_TBL_SIZ
2457 define in version.v */
2458
2459#define GRC_CONFIG_REG_PF_INIT_VF 0x624
2460#define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK \
2461 0xf /*First VF_NUM for PF is encoded in this register.
2462 The number of VFs assigned to a PF is assumed to be a multiple of 8.
2463 Software should program these bits based on Total Number of VFs \
2464 programmed for each PF.
2465 Since registers from 0x000-0x7ff are spilt across functions, each PF will have
2466 the same location for the same 4 bits*/
2467
2468#define PXPCS_TL_CONTROL_5 0x814
2469#define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/
2470#define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/
2471#define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/
2472#define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/
2473#define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/
2474#define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/
2475#define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/
2476#define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/
2477#define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/
2478#define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/
2479#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/
2480#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/
2481#define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/
2482#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/
2483#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/
2484#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/
2485#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/
2486#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/
2487#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/
2488#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/
2489#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/
2490#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/
2491#define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/
2492#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/
2493#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/
2494#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/
2495#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/
2496#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/
2497#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/
2498#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/
2499
2500
2501#define PXPCS_TL_FUNC345_STAT 0x854
2502#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */
2503#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 \
2504 (1 << 28) /* Unsupported Request Error Status in function4, if \
2505 set, generate pcie_err_attn output when this error is seen. WC */
2506#define PXPCS_TL_FUNC345_STAT_ERR_ECRC4 \
2507 (1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \
2508 generate pcie_err_attn output when this error is seen.. WC */
2509#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4 \
2510 (1 << 26) /* Malformed TLP Status Status in function 4, if set, \
2511 generate pcie_err_attn output when this error is seen.. WC */
2512#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4 \
2513 (1 << 25) /* Receiver Overflow Status Status in function 4, if \
2514 set, generate pcie_err_attn output when this error is seen.. WC \
2515 */
2516#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4 \
2517 (1 << 24) /* Unexpected Completion Status Status in function 4, \
2518 if set, generate pcie_err_attn output when this error is seen. WC \
2519 */
2520#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4 \
2521 (1 << 23) /* Receive UR Statusin function 4. If set, generate \
2522 pcie_err_attn output when this error is seen. WC */
2523#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4 \
2524 (1 << 22) /* Completer Timeout Status Status in function 4, if \
2525 set, generate pcie_err_attn output when this error is seen. WC */
2526#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4 \
2527 (1 << 21) /* Flow Control Protocol Error Status Status in \
2528 function 4, if set, generate pcie_err_attn output when this error \
2529 is seen. WC */
2530#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4 \
2531 (1 << 20) /* Poisoned Error Status Status in function 4, if set, \
2532 generate pcie_err_attn output when this error is seen.. WC */
2533#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */
2534#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 \
2535 (1 << 18) /* Unsupported Request Error Status in function3, if \
2536 set, generate pcie_err_attn output when this error is seen. WC */
2537#define PXPCS_TL_FUNC345_STAT_ERR_ECRC3 \
2538 (1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \
2539 generate pcie_err_attn output when this error is seen.. WC */
2540#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3 \
2541 (1 << 16) /* Malformed TLP Status Status in function 3, if set, \
2542 generate pcie_err_attn output when this error is seen.. WC */
2543#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3 \
2544 (1 << 15) /* Receiver Overflow Status Status in function 3, if \
2545 set, generate pcie_err_attn output when this error is seen.. WC \
2546 */
2547#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3 \
2548 (1 << 14) /* Unexpected Completion Status Status in function 3, \
2549 if set, generate pcie_err_attn output when this error is seen. WC \
2550 */
2551#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3 \
2552 (1 << 13) /* Receive UR Statusin function 3. If set, generate \
2553 pcie_err_attn output when this error is seen. WC */
2554#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3 \
2555 (1 << 12) /* Completer Timeout Status Status in function 3, if \
2556 set, generate pcie_err_attn output when this error is seen. WC */
2557#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3 \
2558 (1 << 11) /* Flow Control Protocol Error Status Status in \
2559 function 3, if set, generate pcie_err_attn output when this error \
2560 is seen. WC */
2561#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3 \
2562 (1 << 10) /* Poisoned Error Status Status in function 3, if set, \
2563 generate pcie_err_attn output when this error is seen.. WC */
2564#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */
2565#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2 \
2566 (1 << 8) /* Unsupported Request Error Status for Function 2, if \
2567 set, generate pcie_err_attn output when this error is seen. WC */
2568#define PXPCS_TL_FUNC345_STAT_ERR_ECRC2 \
2569 (1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \
2570 generate pcie_err_attn output when this error is seen.. WC */
2571#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2 \
2572 (1 << 6) /* Malformed TLP Status Status for Function 2, if set, \
2573 generate pcie_err_attn output when this error is seen.. WC */
2574#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2 \
2575 (1 << 5) /* Receiver Overflow Status Status for Function 2, if \
2576 set, generate pcie_err_attn output when this error is seen.. WC \
2577 */
2578#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2 \
2579 (1 << 4) /* Unexpected Completion Status Status for Function 2, \
2580 if set, generate pcie_err_attn output when this error is seen. WC \
2581 */
2582#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2 \
2583 (1 << 3) /* Receive UR Statusfor Function 2. If set, generate \
2584 pcie_err_attn output when this error is seen. WC */
2585#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2 \
2586 (1 << 2) /* Completer Timeout Status Status for Function 2, if \
2587 set, generate pcie_err_attn output when this error is seen. WC */
2588#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2 \
2589 (1 << 1) /* Flow Control Protocol Error Status Status for \
2590 Function 2, if set, generate pcie_err_attn output when this error \
2591 is seen. WC */
2592#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2 \
2593 (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \
2594 generate pcie_err_attn output when this error is seen.. WC */
2595
2596
2597#define PXPCS_TL_FUNC678_STAT 0x85C
2598#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */
2599#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 \
2600 (1 << 28) /* Unsupported Request Error Status in function7, if \
2601 set, generate pcie_err_attn output when this error is seen. WC */
2602#define PXPCS_TL_FUNC678_STAT_ERR_ECRC7 \
2603 (1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \
2604 generate pcie_err_attn output when this error is seen.. WC */
2605#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7 \
2606 (1 << 26) /* Malformed TLP Status Status in function 7, if set, \
2607 generate pcie_err_attn output when this error is seen.. WC */
2608#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7 \
2609 (1 << 25) /* Receiver Overflow Status Status in function 7, if \
2610 set, generate pcie_err_attn output when this error is seen.. WC \
2611 */
2612#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7 \
2613 (1 << 24) /* Unexpected Completion Status Status in function 7, \
2614 if set, generate pcie_err_attn output when this error is seen. WC \
2615 */
2616#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7 \
2617 (1 << 23) /* Receive UR Statusin function 7. If set, generate \
2618 pcie_err_attn output when this error is seen. WC */
2619#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7 \
2620 (1 << 22) /* Completer Timeout Status Status in function 7, if \
2621 set, generate pcie_err_attn output when this error is seen. WC */
2622#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7 \
2623 (1 << 21) /* Flow Control Protocol Error Status Status in \
2624 function 7, if set, generate pcie_err_attn output when this error \
2625 is seen. WC */
2626#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7 \
2627 (1 << 20) /* Poisoned Error Status Status in function 7, if set, \
2628 generate pcie_err_attn output when this error is seen.. WC */
2629#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */
2630#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 \
2631 (1 << 18) /* Unsupported Request Error Status in function6, if \
2632 set, generate pcie_err_attn output when this error is seen. WC */
2633#define PXPCS_TL_FUNC678_STAT_ERR_ECRC6 \
2634 (1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \
2635 generate pcie_err_attn output when this error is seen.. WC */
2636#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6 \
2637 (1 << 16) /* Malformed TLP Status Status in function 6, if set, \
2638 generate pcie_err_attn output when this error is seen.. WC */
2639#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6 \
2640 (1 << 15) /* Receiver Overflow Status Status in function 6, if \
2641 set, generate pcie_err_attn output when this error is seen.. WC \
2642 */
2643#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6 \
2644 (1 << 14) /* Unexpected Completion Status Status in function 6, \
2645 if set, generate pcie_err_attn output when this error is seen. WC \
2646 */
2647#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6 \
2648 (1 << 13) /* Receive UR Statusin function 6. If set, generate \
2649 pcie_err_attn output when this error is seen. WC */
2650#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6 \
2651 (1 << 12) /* Completer Timeout Status Status in function 6, if \
2652 set, generate pcie_err_attn output when this error is seen. WC */
2653#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6 \
2654 (1 << 11) /* Flow Control Protocol Error Status Status in \
2655 function 6, if set, generate pcie_err_attn output when this error \
2656 is seen. WC */
2657#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6 \
2658 (1 << 10) /* Poisoned Error Status Status in function 6, if set, \
2659 generate pcie_err_attn output when this error is seen.. WC */
2660#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */
2661#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5 \
2662 (1 << 8) /* Unsupported Request Error Status for Function 5, if \
2663 set, generate pcie_err_attn output when this error is seen. WC */
2664#define PXPCS_TL_FUNC678_STAT_ERR_ECRC5 \
2665 (1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \
2666 generate pcie_err_attn output when this error is seen.. WC */
2667#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5 \
2668 (1 << 6) /* Malformed TLP Status Status for Function 5, if set, \
2669 generate pcie_err_attn output when this error is seen.. WC */
2670#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5 \
2671 (1 << 5) /* Receiver Overflow Status Status for Function 5, if \
2672 set, generate pcie_err_attn output when this error is seen.. WC \
2673 */
2674#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5 \
2675 (1 << 4) /* Unexpected Completion Status Status for Function 5, \
2676 if set, generate pcie_err_attn output when this error is seen. WC \
2677 */
2678#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5 \
2679 (1 << 3) /* Receive UR Statusfor Function 5. If set, generate \
2680 pcie_err_attn output when this error is seen. WC */
2681#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5 \
2682 (1 << 2) /* Completer Timeout Status Status for Function 5, if \
2683 set, generate pcie_err_attn output when this error is seen. WC */
2684#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5 \
2685 (1 << 1) /* Flow Control Protocol Error Status Status for \
2686 Function 5, if set, generate pcie_err_attn output when this error \
2687 is seen. WC */
2688#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5 \
2689 (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \
2690 generate pcie_err_attn output when this error is seen.. WC */
2691
2692
2693#define BAR_USTRORM_INTMEM 0x400000
2694#define BAR_CSTRORM_INTMEM 0x410000
2695#define BAR_XSTRORM_INTMEM 0x420000
2696#define BAR_TSTRORM_INTMEM 0x430000
2697
2698/* for accessing the IGU in case of status block ACK */
2699#define BAR_IGU_INTMEM 0x440000
2700
2701#define BAR_DOORBELL_OFFSET 0x800000
2702
2703#define BAR_ME_REGISTER 0x450000
2704#define ME_REG_PF_NUM_SHIFT 0
2705#define ME_REG_PF_NUM \
2706 (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */
2707#define ME_REG_VF_VALID (1<<8)
2708#define ME_REG_VF_NUM_SHIFT 9
2709#define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT)
2710#define VF_ID(x) ((x & ME_REG_VF_NUM_MASK) >> ME_REG_VF_NUM_SHIFT)
2711#define ME_REG_VF_ERR (0x1<<3)
2712#define ME_REG_ABS_PF_NUM_SHIFT 16
2713#define ME_REG_ABS_PF_NUM \
2714 (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */
2715
2716
2717#define PXP_VF_ADRR_NUM_QUEUES 136
2718#define PXP_ADDR_QUEUE_SIZE 32
2719#define PXP_ADDR_REG_SIZE 512
2720
2721
2722#define PXP_VF_ADDR_IGU_START 0
2723#define PXP_VF_ADDR_IGU_SIZE (0x3000)
2724#define PXP_VF_ADDR_IGU_END \
2725 ((PXP_VF_ADDR_IGU_START) + (PXP_VF_ADDR_IGU_SIZE) - 1)
2726
2727#define PXP_VF_ADDR_USDM_QUEUES_START 0x3000
2728#define PXP_VF_ADDR_USDM_QUEUES_SIZE \
2729 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE)
2730#define PXP_VF_ADDR_USDM_QUEUES_END \
2731 ((PXP_VF_ADDR_USDM_QUEUES_START) + (PXP_VF_ADDR_USDM_QUEUES_SIZE) - 1)
2732
2733#define PXP_VF_ADDR_CSDM_QUEUES_START 0x4100
2734#define PXP_VF_ADDR_CSDM_QUEUES_SIZE \
2735 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE)
2736#define PXP_VF_ADDR_CSDM_QUEUES_END \
2737 ((PXP_VF_ADDR_CSDM_QUEUES_START) + (PXP_VF_ADDR_CSDM_QUEUES_SIZE) - 1)
2738
2739#define PXP_VF_ADDR_XSDM_QUEUES_START 0x5200
2740#define PXP_VF_ADDR_XSDM_QUEUES_SIZE \
2741 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE)
2742#define PXP_VF_ADDR_XSDM_QUEUES_END \
2743 ((PXP_VF_ADDR_XSDM_QUEUES_START) + (PXP_VF_ADDR_XSDM_QUEUES_SIZE) - 1)
2744
2745#define PXP_VF_ADDR_TSDM_QUEUES_START 0x6300
2746#define PXP_VF_ADDR_TSDM_QUEUES_SIZE \
2747 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE)
2748#define PXP_VF_ADDR_TSDM_QUEUES_END \
2749 ((PXP_VF_ADDR_TSDM_QUEUES_START) + (PXP_VF_ADDR_TSDM_QUEUES_SIZE) - 1)
2750
2751#define PXP_VF_ADDR_USDM_GLOBAL_START 0x7400
2752#define PXP_VF_ADDR_USDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE)
2753#define PXP_VF_ADDR_USDM_GLOBAL_END \
2754 ((PXP_VF_ADDR_USDM_GLOBAL_START) + (PXP_VF_ADDR_USDM_GLOBAL_SIZE) - 1)
2755
2756#define PXP_VF_ADDR_CSDM_GLOBAL_START 0x7600
2757#define PXP_VF_ADDR_CSDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE)
2758#define PXP_VF_ADDR_CSDM_GLOBAL_END \
2759 ((PXP_VF_ADDR_CSDM_GLOBAL_START) + (PXP_VF_ADDR_CSDM_GLOBAL_SIZE) - 1)
2760
2761#define PXP_VF_ADDR_XSDM_GLOBAL_START 0x7800
2762#define PXP_VF_ADDR_XSDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE)
2763#define PXP_VF_ADDR_XSDM_GLOBAL_END \
2764 ((PXP_VF_ADDR_XSDM_GLOBAL_START) + (PXP_VF_ADDR_XSDM_GLOBAL_SIZE) - 1)
2765
2766#define PXP_VF_ADDR_TSDM_GLOBAL_START 0x7a00
2767#define PXP_VF_ADDR_TSDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE)
2768#define PXP_VF_ADDR_TSDM_GLOBAL_END \
2769 ((PXP_VF_ADDR_TSDM_GLOBAL_START) + (PXP_VF_ADDR_TSDM_GLOBAL_SIZE) - 1)
2770
2771#define PXP_VF_ADDR_DB_START 0x7c00
2772#define PXP_VF_ADDR_DB_SIZE (0x200)
2773#define PXP_VF_ADDR_DB_END \
2774 ((PXP_VF_ADDR_DB_START) + (PXP_VF_ADDR_DB_SIZE) - 1)
2775
2776#define PXP_VF_ADDR_GRC_START 0x7e00
2777#define PXP_VF_ADDR_GRC_SIZE (0x200)
2778#define PXP_VF_ADDR_GRC_END \
2779 ((PXP_VF_ADDR_GRC_START) + (PXP_VF_ADDR_GRC_SIZE) - 1)
2780
2781#define PXP_VF_ADDR_DORQ_START (0x0)
2782#define PXP_VF_ADDR_DORQ_SIZE (0xffffffff)
2783#define PXP_VF_ADDR_DORQ_END (0xffffffff)
2784
2785#define PXP_BAR_GRC 0
2786#define PXP_BAR_TSDM 0
2787#define PXP_BAR_USDM 0
2788#define PXP_BAR_XSDM 0
2789#define PXP_BAR_CSDM 0
2790#define PXP_BAR_IGU 0
2791#define PXP_BAR_DQ 1
2792
2793#define PXP_VF_BAR_IGU 0
2794#define PXP_VF_BAR_USDM_QUEUES 0
2795#define PXP_VF_BAR_TSDM_QUEUES 0
2796#define PXP_VF_BAR_XSDM_QUEUES 0
2797#define PXP_VF_BAR_CSDM_QUEUES 0
2798#define PXP_VF_BAR_USDM_GLOBAL 0
2799#define PXP_VF_BAR_TSDM_GLOBAL 0
2800#define PXP_VF_BAR_XSDM_GLOBAL 0
2801#define PXP_VF_BAR_CSDM_GLOBAL 0
2802#define PXP_VF_BAR_DB 0
2803#define PXP_VF_BAR_GRC 0
2804#define PXP_VF_BAR_DORQ 1
2805
2806/* PCI CAPABILITIES*/
2807
2808#define PCI_CAP_PCIE 0x10 /*PCIe capability ID*/
2809
2810#define PCIE_DEV_CAPS 0x04
2811
2812#define PCIE_DEV_CTRL 0x08
2813#define PCIE_DEV_CTRL_FLR 0x8000;
2814
2815#define PCIE_DEV_STATUS 0x0A
2816
2817#define PCI_CAP_MSIX 0x11 /*MSI-X capability ID*/
2818#define PCI_MSIX_CONTROL_SHIFT 16
2819#define PCI_MSIX_TABLE_SIZE_MASK 0x07FF
2820#define PCI_MSIX_TABLE_ENABLE_MASK 0x8000
2821
2822
2823#define MDIO_REG_BANK_CL73_IEEEB0 0x0
2824#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
2825#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
2826#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
2827#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
2828
2829#define MDIO_REG_BANK_CL73_IEEEB1 0x10
2830#define MDIO_CL73_IEEEB1_AN_ADV1 0x00
2831#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
2832#define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
2833#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
2834#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
2835#define MDIO_CL73_IEEEB1_AN_ADV2 0x01
2836#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
2837#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
2838#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
2839#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
2840#define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
2841#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
2842#define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
2843#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
2844#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
2845#define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04
2846
2847#define MDIO_REG_BANK_RX0 0x80b0
2848#define MDIO_RX0_RX_STATUS 0x10
2849#define MDIO_RX0_RX_STATUS_SIGDET 0x8000
2850#define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
2851#define MDIO_RX0_RX_EQ_BOOST 0x1c
2852#define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
2853#define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
2854
2855#define MDIO_REG_BANK_RX1 0x80c0
2856#define MDIO_RX1_RX_EQ_BOOST 0x1c
2857#define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
2858#define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
2859
2860#define MDIO_REG_BANK_RX2 0x80d0
2861#define MDIO_RX2_RX_EQ_BOOST 0x1c
2862#define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
2863#define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
2864
2865#define MDIO_REG_BANK_RX3 0x80e0
2866#define MDIO_RX3_RX_EQ_BOOST 0x1c
2867#define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
2868#define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
2869
2870#define MDIO_REG_BANK_RX_ALL 0x80f0
2871#define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
2872#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
2873#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
2874
2875#define MDIO_REG_BANK_TX0 0x8060
2876#define MDIO_TX0_TX_DRIVER 0x17
2877#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
2878#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
2879#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
2880#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
2881#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
2882#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
2883#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
2884#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
2885#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
2886
2887#define MDIO_REG_BANK_TX1 0x8070
2888#define MDIO_TX1_TX_DRIVER 0x17
2889#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
2890#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
2891#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
2892#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
2893#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
2894#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
2895#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
2896#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
2897#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
2898
2899#define MDIO_REG_BANK_TX2 0x8080
2900#define MDIO_TX2_TX_DRIVER 0x17
2901#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
2902#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
2903#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
2904#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
2905#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
2906#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
2907#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
2908#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
2909#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
2910
2911#define MDIO_REG_BANK_TX3 0x8090
2912#define MDIO_TX3_TX_DRIVER 0x17
2913#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
2914#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
2915#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
2916#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
2917#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
2918#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
2919#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
2920#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
2921#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
2922
2923#define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
2924#define MDIO_BLOCK0_XGXS_CONTROL 0x10
2925
2926#define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
2927#define MDIO_BLOCK1_LANE_CTRL0 0x15
2928#define MDIO_BLOCK1_LANE_CTRL1 0x16
2929#define MDIO_BLOCK1_LANE_CTRL2 0x17
2930#define MDIO_BLOCK1_LANE_PRBS 0x19
2931
2932#define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
2933#define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
2934#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
2935#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
2936#define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
2937#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
2938#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
2939#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
2940#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
2941#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
2942
2943#define MDIO_REG_BANK_GP_STATUS 0x8120
2944#define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
2945#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
2946#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
2947#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
2948#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
2949#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
2950#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
2951#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
2952#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
2953#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
2954#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
2955#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
2956#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
2957#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
2958#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
2959#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
2960#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
2961#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
2962#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
2963#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
2964#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
2965#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
2966#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
2967#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
2968#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
2969#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
2970#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
2971#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
2972#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
2973#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900
2974
2975
2976#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
2977#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
2978#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
2979#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
2980#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
2981#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
2982#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
2983
2984#define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
2985#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
2986#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
2987#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
2988#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
2989#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
2990#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
2991#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
2992#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
2993#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
2994#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
2995#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
2996#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
2997#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
2998#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
2999#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
3000#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
3001#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
3002#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
3003#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
3004#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
3005#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
3006#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
3007#define MDIO_SERDES_DIGITAL_MISC1 0x18
3008#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
3009#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
3010#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
3011#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
3012#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
3013#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
3014#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
3015#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
3016#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
3017#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
3018#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
3019#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
3020#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
3021#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
3022#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
3023#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
3024#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
3025#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
3026
3027#define MDIO_REG_BANK_OVER_1G 0x8320
3028#define MDIO_OVER_1G_DIGCTL_3_4 0x14
3029#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
3030#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
3031#define MDIO_OVER_1G_UP1 0x19
3032#define MDIO_OVER_1G_UP1_2_5G 0x0001
3033#define MDIO_OVER_1G_UP1_5G 0x0002
3034#define MDIO_OVER_1G_UP1_6G 0x0004
3035#define MDIO_OVER_1G_UP1_10G 0x0010
3036#define MDIO_OVER_1G_UP1_10GH 0x0008
3037#define MDIO_OVER_1G_UP1_12G 0x0020
3038#define MDIO_OVER_1G_UP1_12_5G 0x0040
3039#define MDIO_OVER_1G_UP1_13G 0x0080
3040#define MDIO_OVER_1G_UP1_15G 0x0100
3041#define MDIO_OVER_1G_UP1_16G 0x0200
3042#define MDIO_OVER_1G_UP2 0x1A
3043#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
3044#define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
3045#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
3046#define MDIO_OVER_1G_UP3 0x1B
3047#define MDIO_OVER_1G_UP3_HIGIG2 0x0001
3048#define MDIO_OVER_1G_LP_UP1 0x1C
3049#define MDIO_OVER_1G_LP_UP2 0x1D
3050#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
3051#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
3052#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
3053#define MDIO_OVER_1G_LP_UP3 0x1E
3054
3055#define MDIO_REG_BANK_REMOTE_PHY 0x8330
3056#define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
3057#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
3058#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
3059
3060#define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
3061#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
3062#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
3063#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
3064
3065#define MDIO_REG_BANK_CL73_USERB0 0x8370
3066#define MDIO_CL73_USERB0_CL73_UCTRL 0x10
3067#define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
3068#define MDIO_CL73_USERB0_CL73_USTAT1 0x11
3069#define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
3070#define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
3071#define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
3072#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
3073#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
3074#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
3075#define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
3076#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
3077
3078#define MDIO_REG_BANK_AER_BLOCK 0xFFD0
3079#define MDIO_AER_BLOCK_AER_REG 0x1E
3080
3081#define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
3082#define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
3083#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
3084#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
3085#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
3086#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
3087#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
3088#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
3089#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
3090#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
3091#define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
3092#define MDIO_COMBO_IEEE0_MII_STATUS 0x11
3093#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
3094#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
3095#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
3096#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
3097#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
3098#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
3099#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
3100#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
3101#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
3102#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
3103#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
3104#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
3105#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
3106#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
3107#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
3108#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
3109#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
3110#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
3111#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
3112/*WhenthelinkpartnerisinSGMIImode(bit0=1), then
3113bit15=link, bit12=duplex, bits11:10=speed, bit14=acknowledge.
3114Theotherbitsarereservedandshouldbezero*/
3115#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
3116
3117
3118#define MDIO_PMA_DEVAD 0x1
3119/*ieee*/
3120#define MDIO_PMA_REG_CTRL 0x0
3121#define MDIO_PMA_REG_STATUS 0x1
3122#define MDIO_PMA_REG_10G_CTRL2 0x7
3123#define MDIO_PMA_REG_TX_DISABLE 0x0009
3124#define MDIO_PMA_REG_RX_SD 0xa
3125/*bnx2x*/
3126#define MDIO_PMA_REG_BNX2X_CTRL 0x0096
3127#define MDIO_PMA_REG_FEC_CTRL 0x00ab
3128#define MDIO_PMA_LASI_RXCTRL 0x9000
3129#define MDIO_PMA_LASI_TXCTRL 0x9001
3130#define MDIO_PMA_LASI_CTRL 0x9002
3131#define MDIO_PMA_LASI_RXSTAT 0x9003
3132#define MDIO_PMA_LASI_TXSTAT 0x9004
3133#define MDIO_PMA_LASI_STAT 0x9005
3134#define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
3135#define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
3136#define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
3137#define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
3138#define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
3139#define MDIO_PMA_REG_MISC_CTRL 0xca0a
3140#define MDIO_PMA_REG_GEN_CTRL 0xca10
3141#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
3142#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
3143#define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
3144#define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
3145#define MDIO_PMA_REG_ROM_VER1 0xca19
3146#define MDIO_PMA_REG_ROM_VER2 0xca1a
3147#define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
3148#define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
3149#define MDIO_PMA_REG_PLL_CTRL 0xca1e
3150#define MDIO_PMA_REG_MISC_CTRL0 0xca23
3151#define MDIO_PMA_REG_LRM_MODE 0xca3f
3152#define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
3153#define MDIO_PMA_REG_MISC_CTRL1 0xca85
3154
3155#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
3156#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
3157#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
3158#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
3159#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
3160#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
3161#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
3162#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
3163#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
3164#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
3165#define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
3166#define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
3167
3168#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
3169#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
3170#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
3171#define MDIO_PMA_REG_8727_MISC_CTRL 0x8309
3172#define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
3173#define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
3174#define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
3175#define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
3176#define MDIO_PMA_REG_8727_PCS_GP 0xc842
3177#define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
3178
3179#define MDIO_AN_REG_8727_MISC_CTRL 0x8309
3180#define MDIO_PMA_REG_8073_CHIP_REV 0xc801
3181#define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
3182#define MDIO_PMA_REG_8073_XAUI_WA 0xc841
3183#define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
3184
3185#define MDIO_PMA_REG_7101_RESET 0xc000
3186#define MDIO_PMA_REG_7107_LED_CNTL 0xc007
3187#define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
3188#define MDIO_PMA_REG_7101_VER1 0xc026
3189#define MDIO_PMA_REG_7101_VER2 0xc027
3190
3191#define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
3192#define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
3193#define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
3194#define MDIO_PMA_REG_8481_LED3_MASK 0xa832
3195#define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
3196#define MDIO_PMA_REG_8481_LED5_MASK 0xa838
3197#define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
3198#define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
3199#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
3200#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
3201
3202
3203#define MDIO_WIS_DEVAD 0x2
3204/*bnx2x*/
3205#define MDIO_WIS_REG_LASI_CNTL 0x9002
3206#define MDIO_WIS_REG_LASI_STATUS 0x9005
3207
3208#define MDIO_PCS_DEVAD 0x3
3209#define MDIO_PCS_REG_STATUS 0x0020
3210#define MDIO_PCS_REG_LASI_STATUS 0x9005
3211#define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
3212#define MDIO_PCS_REG_7101_SPI_MUX 0xD008
3213#define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
3214#define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
3215#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
3216#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
3217#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
3218#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
3219#define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
3220
3221
3222#define MDIO_XS_DEVAD 0x4
3223#define MDIO_XS_REG_STATUS 0x0001
3224#define MDIO_XS_PLL_SEQUENCER 0x8000
3225#define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
3226
3227#define MDIO_XS_8706_REG_BANK_RX0 0x80bc
3228#define MDIO_XS_8706_REG_BANK_RX1 0x80cc
3229#define MDIO_XS_8706_REG_BANK_RX2 0x80dc
3230#define MDIO_XS_8706_REG_BANK_RX3 0x80ec
3231#define MDIO_XS_8706_REG_BANK_RXA 0x80fc
3232
3233#define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
3234
3235#define MDIO_AN_DEVAD 0x7
3236/*ieee*/
3237#define MDIO_AN_REG_CTRL 0x0000
3238#define MDIO_AN_REG_STATUS 0x0001
3239#define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
3240#define MDIO_AN_REG_ADV_PAUSE 0x0010
3241#define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
3242#define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
3243#define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
3244#define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
3245#define MDIO_AN_REG_ADV 0x0011
3246#define MDIO_AN_REG_ADV2 0x0012
3247#define MDIO_AN_REG_LP_AUTO_NEG 0x0013
3248#define MDIO_AN_REG_LP_AUTO_NEG2 0x0014
3249#define MDIO_AN_REG_MASTER_STATUS 0x0021
3250#define MDIO_AN_REG_EEE_ADV 0x003c
3251#define MDIO_AN_REG_LP_EEE_ADV 0x003d
3252/*bnx2x*/
3253#define MDIO_AN_REG_LINK_STATUS 0x8304
3254#define MDIO_AN_REG_CL37_CL73 0x8370
3255#define MDIO_AN_REG_CL37_AN 0xffe0
3256#define MDIO_AN_REG_CL37_FC_LD 0xffe4
3257#define MDIO_AN_REG_CL37_FC_LP 0xffe5
3258#define MDIO_AN_REG_1000T_STATUS 0xffea
3259
3260#define MDIO_AN_REG_8073_2_5G 0x8329
3261#define MDIO_AN_REG_8073_BAM 0x8350
3262
3263#define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
3264#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
3265#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
3266#define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
3267#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
3268#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
3269#define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
3270#define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0
3271#define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008
3272#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
3273#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
3274#define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
3275#define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
3276
3277/* BNX2X84823 only */
3278#define MDIO_CTL_DEVAD 0x1e
3279#define MDIO_CTL_REG_84823_MEDIA 0x401a
3280#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
3281 /* These pins configure the BNX2X84823 interface to MAC after reset. */
3282#define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
3283#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
3284 /* These pins configure the BNX2X84823 interface to Line after reset. */
3285#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
3286#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
3287#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
3288 /* When this pin is active high during reset, 10GBASE-T core is power
3289 * down, When it is active low the 10GBASE-T is power up
3290 */
3291#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
3292#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
3293#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
3294#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
3295#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
3296#define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
3297#define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
3298#define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b
3299#define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f
3300#define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
3301#define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
3302#define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
3303
3304/* BNX2X84833 only */
3305#define MDIO_84833_TOP_CFG_FW_REV 0x400f
3306#define MDIO_84833_TOP_CFG_FW_EEE 0x10b1
3307#define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
3308#define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
3309#define MDIO_84833_SUPER_ISOLATE 0x8000
3310/* These are mailbox register set used by 84833. */
3311#define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
3312#define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
3313#define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
3314#define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
3315#define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
3316#define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037
3317#define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038
3318#define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039
3319#define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a
3320#define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b
3321#define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c
3322#define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0
3323#define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26
3324#define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27
3325#define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28
3326#define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29
3327#define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30
3328#define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31
3329
3330/* Mailbox command set used by 84833. */
3331#define PHY84833_CMD_SET_PAIR_SWAP 0x8001
3332#define PHY84833_CMD_GET_EEE_MODE 0x8008
3333#define PHY84833_CMD_SET_EEE_MODE 0x8009
3334#define PHY84833_CMD_GET_CURRENT_TEMP 0x8031
3335/* Mailbox status set used by 84833. */
3336#define PHY84833_STATUS_CMD_RECEIVED 0x0001
3337#define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
3338#define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
3339#define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008
3340#define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010
3341#define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020
3342#define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
3343#define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
3344#define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
3345
3346
3347/* Warpcore clause 45 addressing */
3348#define MDIO_WC_DEVAD 0x3
3349#define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0
3350#define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7
3351#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
3352#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
3353#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12
3354#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000
3355#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000
3356#define MDIO_WC_REG_PCS_STATUS2 0x0021
3357#define MDIO_WC_REG_PMD_KR_CONTROL 0x0096
3358#define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
3359#define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e
3360#define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010
3361#define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015
3362#define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016
3363#define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017
3364#define MDIO_WC_REG_XGXSBLK1_LANECTRL3 0x8018
3365#define MDIO_WC_REG_XGXSBLK1_LANETEST0 0x801a
3366#define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061
3367#define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071
3368#define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
3369#define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
3370#define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
3371#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
3372#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
3373#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
3374#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
3375#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c
3376#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000
3377#define MDIO_WC_REG_TX1_TX_DRIVER 0x8077
3378#define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
3379#define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
3380#define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
3381#define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
3382#define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
3383#define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
3384#define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
3385#define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
3386#define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
3387#define MDIO_WC_REG_XGXS_STATUS3 0x8129
3388#define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
3389#define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
3390#define MDIO_WC_REG_XGXS_STATUS4 0x813c
3391#define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
3392#define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142
3393#define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B
3394#define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169
3395#define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0
3396#define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1
3397#define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
3398#define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
3399#define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
3400#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
3401#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
3402#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
3403#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
3404#define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
3405#define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
3406#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
3407#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
3408#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
3409#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
3410#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
3411#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
3412#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
3413#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
3414#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
3415#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
3416#define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
3417#define MDIO_WC_REG_DSC1B0_UC_CTRL 0x820e
3418#define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD (1<<7)
3419#define MDIO_WC_REG_DSC_SMC 0x8213
3420#define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
3421#define MDIO_WC_REG_TX_FIR_TAP 0x82e2
3422#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
3423#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
3424#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
3425#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
3426#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
3427#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
3428#define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
3429#define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2
3430#define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
3431#define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
3432#define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7
3433#define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
3434#define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
3435#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
3436#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
3437#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
3438#define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
3439#define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
3440#define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309
3441#define MDIO_WC_REG_DIGITAL3_UP1 0x8329
3442#define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c
3443#define MDIO_WC_REG_DIGITAL4_MISC3 0x833c
3444#define MDIO_WC_REG_DIGITAL4_MISC5 0x833e
3445#define MDIO_WC_REG_DIGITAL5_MISC6 0x8345
3446#define MDIO_WC_REG_DIGITAL5_MISC7 0x8349
3447#define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d
3448#define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e
3449#define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350
3450#define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368
3451#define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370
3452#define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371
3453#define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372
3454#define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373
3455#define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374
3456#define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b
3457#define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390
3458#define MDIO_WC_REG_TX66_CONTROL 0x83b0
3459#define MDIO_WC_REG_RX66_CONTROL 0x83c0
3460#define MDIO_WC_REG_RX66_SCW0 0x83c2
3461#define MDIO_WC_REG_RX66_SCW1 0x83c3
3462#define MDIO_WC_REG_RX66_SCW2 0x83c4
3463#define MDIO_WC_REG_RX66_SCW3 0x83c5
3464#define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6
3465#define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7
3466#define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8
3467#define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9
3468#define MDIO_WC_REG_FX100_CTRL1 0x8400
3469#define MDIO_WC_REG_FX100_CTRL3 0x8402
3470#define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436
3471#define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437
3472#define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438
3473#define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439
3474#define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a
3475#define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b
3476#define MDIO_WC_REG_ETA_CL73_OUI1 0x8453
3477#define MDIO_WC_REG_ETA_CL73_OUI2 0x8454
3478#define MDIO_WC_REG_ETA_CL73_OUI3 0x8455
3479#define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456
3480#define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457
3481#define MDIO_WC_REG_MICROBLK_CMD 0xffc2
3482#define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5
3483#define MDIO_WC_REG_MICROBLK_CMD3 0xffcc
3484
3485#define MDIO_WC_REG_AERBLK_AER 0xffde
3486#define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0
3487#define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
3488
3489#define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
3490#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
3491#define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
3492
3493#define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
3494
3495#define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
3496
3497/* 54618se */
3498#define MDIO_REG_GPHY_MII_STATUS 0x1
3499#define MDIO_REG_GPHY_PHYID_LSB 0x3
3500#define MDIO_REG_GPHY_CL45_ADDR_REG 0xd
3501#define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000
3502#define MDIO_REG_GPHY_CL45_REG_READ 0xc000
3503#define MDIO_REG_GPHY_CL45_DATA_REG 0xe
3504#define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
3505#define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15
3506#define MDIO_REG_GPHY_EXP_ACCESS 0x17
3507#define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
3508#define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
3509#define MDIO_REG_GPHY_AUX_STATUS 0x19
3510#define MDIO_REG_INTR_STATUS 0x1a
3511#define MDIO_REG_INTR_MASK 0x1b
3512#define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
3513#define MDIO_REG_GPHY_SHADOW 0x1c
3514#define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)
3515#define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
3516#define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
3517#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
3518#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
3519
3520
3521#define IGU_FUNC_BASE 0x0400
3522
3523#define IGU_ADDR_MSIX 0x0000
3524#define IGU_ADDR_INT_ACK 0x0200
3525#define IGU_ADDR_PROD_UPD 0x0201
3526#define IGU_ADDR_ATTN_BITS_UPD 0x0202
3527#define IGU_ADDR_ATTN_BITS_SET 0x0203
3528#define IGU_ADDR_ATTN_BITS_CLR 0x0204
3529#define IGU_ADDR_COALESCE_NOW 0x0205
3530#define IGU_ADDR_SIMD_MASK 0x0206
3531#define IGU_ADDR_SIMD_NOMASK 0x0207
3532#define IGU_ADDR_MSI_CTL 0x0210
3533#define IGU_ADDR_MSI_ADDR_LO 0x0211
3534#define IGU_ADDR_MSI_ADDR_HI 0x0212
3535#define IGU_ADDR_MSI_DATA 0x0213
3536
3537
3538#define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0
3539#define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 1
3540#define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 2
3541#define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup 3
3542
3543#define COMMAND_REG_INT_ACK 0x0
3544#define COMMAND_REG_PROD_UPD 0x4
3545#define COMMAND_REG_ATTN_BITS_UPD 0x8
3546#define COMMAND_REG_ATTN_BITS_SET 0xc
3547#define COMMAND_REG_ATTN_BITS_CLR 0x10
3548#define COMMAND_REG_COALESCE_NOW 0x14
3549#define COMMAND_REG_SIMD_MASK 0x18
3550#define COMMAND_REG_SIMD_NOMASK 0x1c
3551
3552
3553#define IGU_MEM_BASE 0x0000
3554
3555#define IGU_MEM_MSIX_BASE 0x0000
3556#define IGU_MEM_MSIX_UPPER 0x007f
3557#define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
3558
3559#define IGU_MEM_PBA_MSIX_BASE 0x0200
3560#define IGU_MEM_PBA_MSIX_UPPER 0x0200
3561
3562#define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201
3563#define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
3564
3565#define IGU_CMD_INT_ACK_BASE 0x0400
3566#define IGU_CMD_INT_ACK_UPPER \
3567 (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PATH - 1)
3568#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff
3569
3570#define IGU_CMD_E2_PROD_UPD_BASE 0x0500
3571#define IGU_CMD_E2_PROD_UPD_UPPER \
3572 (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PATH - 1)
3573#define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f
3574
3575#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0
3576#define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1
3577#define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2
3578
3579#define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3
3580#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4
3581#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5
3582#define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6
3583
3584
3585#define IGU_REG_RESERVED_UPPER 0x05ff
3586
3587#define IGU_SEG_IDX_ATTN 2
3588#define IGU_SEG_IDX_DEFAULT 1
3589/* Fields of IGU PF CONFIGRATION REGISTER */
3590#define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */
3591#define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
3592#define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */
3593#define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */
3594#define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
3595#define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */
3596
3597/* Fields of IGU VF CONFIGRATION REGISTER */
3598#define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */
3599#define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
3600#define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */
3601#define IGU_VF_CONF_PARENT_SHIFT 2 /* Parent PF */
3602#define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
3603
3604
3605#define IGU_BC_DSB_NUM_SEGS 5
3606#define IGU_BC_NDSB_NUM_SEGS 2
3607#define IGU_NORM_DSB_NUM_SEGS 2
3608#define IGU_NORM_NDSB_NUM_SEGS 1
3609#define IGU_BC_BASE_DSB_PROD 128
3610#define IGU_NORM_BASE_DSB_PROD 136
3611
3612 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \
3613 [5:2] = 0; [1:0] = PF number) */
3614#define IGU_FID_ENCODE_IS_PF (0x1<<6)
3615#define IGU_FID_ENCODE_IS_PF_SHIFT 6
3616#define IGU_FID_VF_NUM_MASK (0x3f)
3617#define IGU_FID_PF_NUM_MASK (0x7)
3618
3619#define IGU_REG_MAPPING_MEMORY_VALID (1<<0)
3620#define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1)
3621#define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT 1
3622#define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7)
3623#define IGU_REG_MAPPING_MEMORY_FID_SHIFT 7
3624
3625
3626#define CDU_REGION_NUMBER_XCM_AG 2
3627#define CDU_REGION_NUMBER_UCM_AG 4
3628
3629
3630/* String-to-compress [31:8] = CID (all 24 bits)
3631 * String-to-compress [7:4] = Region
3632 * String-to-compress [3:0] = Type
3633 */
3634#define CDU_VALID_DATA(_cid, _region, _type) \
3635 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
3636#define CDU_CRC8(_cid, _region, _type) \
3637 (ecore_calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
3638#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \
3639 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
3640#define CDU_RSRVD_VALUE_TYPE_B(_crc, _type) \
3641 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
3642#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
3643
3644#endif /* ECORE_REG_H */
Ceph