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1 | /* |
2 | * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved. | |
3 | * | |
4 | * Eric Davis <edavis@broadcom.com> | |
5 | * David Christensen <davidch@broadcom.com> | |
6 | * Gary Zambrano <zambrano@broadcom.com> | |
7 | * | |
8 | * Copyright (c) 2013-2015 Brocade Communications Systems, Inc. | |
9 | * Copyright (c) 2015 QLogic Corporation. | |
10 | * All rights reserved. | |
11 | * www.qlogic.com | |
12 | * | |
13 | * See LICENSE.bnx2x_pmd for copyright and licensing details. | |
14 | */ | |
15 | ||
16 | #include "bnx2x.h" | |
17 | #include "elink.h" | |
18 | #include "ecore_mfw_req.h" | |
19 | #include "ecore_fw_defs.h" | |
20 | #include "ecore_hsi.h" | |
21 | #include "ecore_reg.h" | |
22 | ||
23 | static elink_status_t elink_link_reset(struct elink_params *params, | |
24 | struct elink_vars *vars, | |
25 | uint8_t reset_ext_phy); | |
26 | static elink_status_t elink_check_half_open_conn(struct elink_params *params, | |
27 | struct elink_vars *vars, | |
28 | uint8_t notify); | |
29 | static elink_status_t elink_sfp_module_detection(struct elink_phy *phy, | |
30 | struct elink_params *params); | |
31 | ||
32 | #define MDIO_REG_BANK_CL73_IEEEB0 0x0 | |
33 | #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0 | |
34 | #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200 | |
35 | #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000 | |
36 | #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000 | |
37 | ||
38 | #define MDIO_REG_BANK_CL73_IEEEB1 0x10 | |
39 | #define MDIO_CL73_IEEEB1_AN_ADV1 0x00 | |
40 | #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400 | |
41 | #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800 | |
42 | #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00 | |
43 | #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00 | |
44 | #define MDIO_CL73_IEEEB1_AN_ADV2 0x01 | |
45 | #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000 | |
46 | #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020 | |
47 | #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040 | |
48 | #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080 | |
49 | #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03 | |
50 | #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400 | |
51 | #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800 | |
52 | #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00 | |
53 | #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00 | |
54 | #define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04 | |
55 | ||
56 | #define MDIO_REG_BANK_RX0 0x80b0 | |
57 | #define MDIO_RX0_RX_STATUS 0x10 | |
58 | #define MDIO_RX0_RX_STATUS_SIGDET 0x8000 | |
59 | #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000 | |
60 | #define MDIO_RX0_RX_EQ_BOOST 0x1c | |
61 | #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 | |
62 | #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10 | |
63 | ||
64 | #define MDIO_REG_BANK_RX1 0x80c0 | |
65 | #define MDIO_RX1_RX_EQ_BOOST 0x1c | |
66 | #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 | |
67 | #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10 | |
68 | ||
69 | #define MDIO_REG_BANK_RX2 0x80d0 | |
70 | #define MDIO_RX2_RX_EQ_BOOST 0x1c | |
71 | #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 | |
72 | #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10 | |
73 | ||
74 | #define MDIO_REG_BANK_RX3 0x80e0 | |
75 | #define MDIO_RX3_RX_EQ_BOOST 0x1c | |
76 | #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 | |
77 | #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10 | |
78 | ||
79 | #define MDIO_REG_BANK_RX_ALL 0x80f0 | |
80 | #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c | |
81 | #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 | |
82 | #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10 | |
83 | ||
84 | #define MDIO_REG_BANK_TX0 0x8060 | |
85 | #define MDIO_TX0_TX_DRIVER 0x17 | |
86 | #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 | |
87 | #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 | |
88 | #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 | |
89 | #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 | |
90 | #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 | |
91 | #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 | |
92 | #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e | |
93 | #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 | |
94 | #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 | |
95 | ||
96 | #define MDIO_REG_BANK_TX1 0x8070 | |
97 | #define MDIO_TX1_TX_DRIVER 0x17 | |
98 | #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 | |
99 | #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 | |
100 | #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 | |
101 | #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 | |
102 | #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 | |
103 | #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 | |
104 | #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e | |
105 | #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 | |
106 | #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 | |
107 | ||
108 | #define MDIO_REG_BANK_TX2 0x8080 | |
109 | #define MDIO_TX2_TX_DRIVER 0x17 | |
110 | #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 | |
111 | #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 | |
112 | #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 | |
113 | #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 | |
114 | #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 | |
115 | #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 | |
116 | #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e | |
117 | #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 | |
118 | #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 | |
119 | ||
120 | #define MDIO_REG_BANK_TX3 0x8090 | |
121 | #define MDIO_TX3_TX_DRIVER 0x17 | |
122 | #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 | |
123 | #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 | |
124 | #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 | |
125 | #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 | |
126 | #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 | |
127 | #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 | |
128 | #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e | |
129 | #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 | |
130 | #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 | |
131 | ||
132 | #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000 | |
133 | #define MDIO_BLOCK0_XGXS_CONTROL 0x10 | |
134 | ||
135 | #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010 | |
136 | #define MDIO_BLOCK1_LANE_CTRL0 0x15 | |
137 | #define MDIO_BLOCK1_LANE_CTRL1 0x16 | |
138 | #define MDIO_BLOCK1_LANE_CTRL2 0x17 | |
139 | #define MDIO_BLOCK1_LANE_PRBS 0x19 | |
140 | ||
141 | #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100 | |
142 | #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10 | |
143 | #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000 | |
144 | #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000 | |
145 | #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11 | |
146 | #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000 | |
147 | #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14 | |
148 | #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001 | |
149 | #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010 | |
150 | #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15 | |
151 | ||
152 | #define MDIO_REG_BANK_GP_STATUS 0x8120 | |
153 | #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B | |
154 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001 | |
155 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002 | |
156 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004 | |
157 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008 | |
158 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010 | |
159 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020 | |
160 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040 | |
161 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080 | |
162 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00 | |
163 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000 | |
164 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100 | |
165 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200 | |
166 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300 | |
167 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400 | |
168 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500 | |
169 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600 | |
170 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700 | |
171 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800 | |
172 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900 | |
173 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00 | |
174 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00 | |
175 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00 | |
176 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00 | |
177 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00 | |
178 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00 | |
179 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00 | |
180 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00 | |
181 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00 | |
182 | #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900 | |
183 | ||
184 | #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130 | |
185 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10 | |
186 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000 | |
187 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11 | |
188 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1 | |
189 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13 | |
190 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1) | |
191 | ||
192 | #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300 | |
193 | #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10 | |
194 | #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001 | |
195 | #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002 | |
196 | #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004 | |
197 | #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008 | |
198 | #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010 | |
199 | #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020 | |
200 | #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11 | |
201 | #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001 | |
202 | #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040 | |
203 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14 | |
204 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001 | |
205 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002 | |
206 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004 | |
207 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018 | |
208 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3 | |
209 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018 | |
210 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010 | |
211 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008 | |
212 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000 | |
213 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15 | |
214 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002 | |
215 | #define MDIO_SERDES_DIGITAL_MISC1 0x18 | |
216 | #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000 | |
217 | #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000 | |
218 | #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000 | |
219 | #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000 | |
220 | #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000 | |
221 | #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000 | |
222 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010 | |
223 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f | |
224 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000 | |
225 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001 | |
226 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002 | |
227 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003 | |
228 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004 | |
229 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005 | |
230 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006 | |
231 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007 | |
232 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008 | |
233 | #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009 | |
234 | ||
235 | #define MDIO_REG_BANK_OVER_1G 0x8320 | |
236 | #define MDIO_OVER_1G_DIGCTL_3_4 0x14 | |
237 | #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0 | |
238 | #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5 | |
239 | #define MDIO_OVER_1G_UP1 0x19 | |
240 | #define MDIO_OVER_1G_UP1_2_5G 0x0001 | |
241 | #define MDIO_OVER_1G_UP1_5G 0x0002 | |
242 | #define MDIO_OVER_1G_UP1_6G 0x0004 | |
243 | #define MDIO_OVER_1G_UP1_10G 0x0010 | |
244 | #define MDIO_OVER_1G_UP1_10GH 0x0008 | |
245 | #define MDIO_OVER_1G_UP1_12G 0x0020 | |
246 | #define MDIO_OVER_1G_UP1_12_5G 0x0040 | |
247 | #define MDIO_OVER_1G_UP1_13G 0x0080 | |
248 | #define MDIO_OVER_1G_UP1_15G 0x0100 | |
249 | #define MDIO_OVER_1G_UP1_16G 0x0200 | |
250 | #define MDIO_OVER_1G_UP2 0x1A | |
251 | #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007 | |
252 | #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038 | |
253 | #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0 | |
254 | #define MDIO_OVER_1G_UP3 0x1B | |
255 | #define MDIO_OVER_1G_UP3_HIGIG2 0x0001 | |
256 | #define MDIO_OVER_1G_LP_UP1 0x1C | |
257 | #define MDIO_OVER_1G_LP_UP2 0x1D | |
258 | #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff | |
259 | #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780 | |
260 | #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7 | |
261 | #define MDIO_OVER_1G_LP_UP3 0x1E | |
262 | ||
263 | #define MDIO_REG_BANK_REMOTE_PHY 0x8330 | |
264 | #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10 | |
265 | #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010 | |
266 | #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600 | |
267 | ||
268 | #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350 | |
269 | #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10 | |
270 | #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001 | |
271 | #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002 | |
272 | ||
273 | #define MDIO_REG_BANK_CL73_USERB0 0x8370 | |
274 | #define MDIO_CL73_USERB0_CL73_UCTRL 0x10 | |
275 | #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002 | |
276 | #define MDIO_CL73_USERB0_CL73_USTAT1 0x11 | |
277 | #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100 | |
278 | #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400 | |
279 | #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12 | |
280 | #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000 | |
281 | #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000 | |
282 | #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000 | |
283 | #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14 | |
284 | #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001 | |
285 | ||
286 | #define MDIO_REG_BANK_AER_BLOCK 0xFFD0 | |
287 | #define MDIO_AER_BLOCK_AER_REG 0x1E | |
288 | ||
289 | #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0 | |
290 | #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10 | |
291 | #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040 | |
292 | #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000 | |
293 | #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000 | |
294 | #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040 | |
295 | #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100 | |
296 | #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200 | |
297 | #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000 | |
298 | #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000 | |
299 | #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000 | |
300 | #define MDIO_COMBO_IEEE0_MII_STATUS 0x11 | |
301 | #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004 | |
302 | #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020 | |
303 | #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14 | |
304 | #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020 | |
305 | #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040 | |
306 | #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180 | |
307 | #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000 | |
308 | #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080 | |
309 | #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100 | |
310 | #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180 | |
311 | #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000 | |
312 | #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15 | |
313 | #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000 | |
314 | #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000 | |
315 | #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180 | |
316 | #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000 | |
317 | #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180 | |
318 | #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040 | |
319 | #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020 | |
320 | /*WhenthelinkpartnerisinSGMIImode(bit0=1),then | |
321 | bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge. | |
322 | Theotherbitsarereservedandshouldbezero*/ | |
323 | #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001 | |
324 | ||
325 | #define MDIO_PMA_DEVAD 0x1 | |
326 | /*ieee*/ | |
327 | #define MDIO_PMA_REG_CTRL 0x0 | |
328 | #define MDIO_PMA_REG_STATUS 0x1 | |
329 | #define MDIO_PMA_REG_10G_CTRL2 0x7 | |
330 | #define MDIO_PMA_REG_TX_DISABLE 0x0009 | |
331 | #define MDIO_PMA_REG_RX_SD 0xa | |
332 | /*bnx2x*/ | |
333 | #define MDIO_PMA_REG_BNX2X_CTRL 0x0096 | |
334 | #define MDIO_PMA_REG_FEC_CTRL 0x00ab | |
335 | #define MDIO_PMA_LASI_RXCTRL 0x9000 | |
336 | #define MDIO_PMA_LASI_TXCTRL 0x9001 | |
337 | #define MDIO_PMA_LASI_CTRL 0x9002 | |
338 | #define MDIO_PMA_LASI_RXSTAT 0x9003 | |
339 | #define MDIO_PMA_LASI_TXSTAT 0x9004 | |
340 | #define MDIO_PMA_LASI_STAT 0x9005 | |
341 | #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800 | |
342 | #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808 | |
343 | #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809 | |
344 | #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02 | |
345 | #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09 | |
346 | #define MDIO_PMA_REG_MISC_CTRL 0xca0a | |
347 | #define MDIO_PMA_REG_GEN_CTRL 0xca10 | |
348 | #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188 | |
349 | #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a | |
350 | #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12 | |
351 | #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13 | |
352 | #define MDIO_PMA_REG_ROM_VER1 0xca19 | |
353 | #define MDIO_PMA_REG_ROM_VER2 0xca1a | |
354 | #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b | |
355 | #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d | |
356 | #define MDIO_PMA_REG_PLL_CTRL 0xca1e | |
357 | #define MDIO_PMA_REG_MISC_CTRL0 0xca23 | |
358 | #define MDIO_PMA_REG_LRM_MODE 0xca3f | |
359 | #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46 | |
360 | #define MDIO_PMA_REG_MISC_CTRL1 0xca85 | |
361 | ||
362 | #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000 | |
363 | #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c | |
364 | #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000 | |
365 | #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004 | |
366 | #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008 | |
367 | #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c | |
368 | #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002 | |
369 | #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003 | |
370 | #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820 | |
371 | #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff | |
372 | #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01 | |
373 | #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05 | |
374 | ||
375 | #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005 | |
376 | #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007 | |
377 | #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff | |
378 | #define MDIO_PMA_REG_8727_MISC_CTRL 0x8309 | |
379 | #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02 | |
380 | #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05 | |
381 | #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808 | |
382 | #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e | |
383 | #define MDIO_PMA_REG_8727_PCS_GP 0xc842 | |
384 | #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4 | |
385 | ||
386 | #define MDIO_AN_REG_8727_MISC_CTRL 0x8309 | |
387 | #define MDIO_PMA_REG_8073_CHIP_REV 0xc801 | |
388 | #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820 | |
389 | #define MDIO_PMA_REG_8073_XAUI_WA 0xc841 | |
390 | #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08 | |
391 | ||
392 | #define MDIO_PMA_REG_7101_RESET 0xc000 | |
393 | #define MDIO_PMA_REG_7107_LED_CNTL 0xc007 | |
394 | #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009 | |
395 | #define MDIO_PMA_REG_7101_VER1 0xc026 | |
396 | #define MDIO_PMA_REG_7101_VER2 0xc027 | |
397 | ||
398 | #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811 | |
399 | #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c | |
400 | #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f | |
401 | #define MDIO_PMA_REG_8481_LED3_MASK 0xa832 | |
402 | #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834 | |
403 | #define MDIO_PMA_REG_8481_LED5_MASK 0xa838 | |
404 | #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835 | |
405 | #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b | |
406 | #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800 | |
407 | #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11 | |
408 | ||
409 | #define MDIO_WIS_DEVAD 0x2 | |
410 | /*bnx2x*/ | |
411 | #define MDIO_WIS_REG_LASI_CNTL 0x9002 | |
412 | #define MDIO_WIS_REG_LASI_STATUS 0x9005 | |
413 | ||
414 | #define MDIO_PCS_DEVAD 0x3 | |
415 | #define MDIO_PCS_REG_STATUS 0x0020 | |
416 | #define MDIO_PCS_REG_LASI_STATUS 0x9005 | |
417 | #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000 | |
418 | #define MDIO_PCS_REG_7101_SPI_MUX 0xD008 | |
419 | #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A | |
420 | #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5) | |
421 | #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A | |
422 | #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6) | |
423 | #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7) | |
424 | #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2) | |
425 | #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028 | |
426 | ||
427 | #define MDIO_XS_DEVAD 0x4 | |
428 | #define MDIO_XS_REG_STATUS 0x0001 | |
429 | #define MDIO_XS_PLL_SEQUENCER 0x8000 | |
430 | #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a | |
431 | ||
432 | #define MDIO_XS_8706_REG_BANK_RX0 0x80bc | |
433 | #define MDIO_XS_8706_REG_BANK_RX1 0x80cc | |
434 | #define MDIO_XS_8706_REG_BANK_RX2 0x80dc | |
435 | #define MDIO_XS_8706_REG_BANK_RX3 0x80ec | |
436 | #define MDIO_XS_8706_REG_BANK_RXA 0x80fc | |
437 | ||
438 | #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA | |
439 | ||
440 | #define MDIO_AN_DEVAD 0x7 | |
441 | /*ieee*/ | |
442 | #define MDIO_AN_REG_CTRL 0x0000 | |
443 | #define MDIO_AN_REG_STATUS 0x0001 | |
444 | #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020 | |
445 | #define MDIO_AN_REG_ADV_PAUSE 0x0010 | |
446 | #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400 | |
447 | #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800 | |
448 | #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00 | |
449 | #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00 | |
450 | #define MDIO_AN_REG_ADV 0x0011 | |
451 | #define MDIO_AN_REG_ADV2 0x0012 | |
452 | #define MDIO_AN_REG_LP_AUTO_NEG 0x0013 | |
453 | #define MDIO_AN_REG_LP_AUTO_NEG2 0x0014 | |
454 | #define MDIO_AN_REG_MASTER_STATUS 0x0021 | |
455 | #define MDIO_AN_REG_EEE_ADV 0x003c | |
456 | #define MDIO_AN_REG_LP_EEE_ADV 0x003d | |
457 | /*bnx2x*/ | |
458 | #define MDIO_AN_REG_LINK_STATUS 0x8304 | |
459 | #define MDIO_AN_REG_CL37_CL73 0x8370 | |
460 | #define MDIO_AN_REG_CL37_AN 0xffe0 | |
461 | #define MDIO_AN_REG_CL37_FC_LD 0xffe4 | |
462 | #define MDIO_AN_REG_CL37_FC_LP 0xffe5 | |
463 | #define MDIO_AN_REG_1000T_STATUS 0xffea | |
464 | ||
465 | #define MDIO_AN_REG_8073_2_5G 0x8329 | |
466 | #define MDIO_AN_REG_8073_BAM 0x8350 | |
467 | ||
468 | #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020 | |
469 | #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0 | |
470 | #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40 | |
471 | #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1 | |
472 | #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4 | |
473 | #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6 | |
474 | #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9 | |
475 | #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0 | |
476 | #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008 | |
477 | #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5 | |
478 | #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7 | |
479 | #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8 | |
480 | #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc | |
481 | ||
482 | /* BNX2X84823 only */ | |
483 | #define MDIO_CTL_DEVAD 0x1e | |
484 | #define MDIO_CTL_REG_84823_MEDIA 0x401a | |
485 | #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018 | |
486 | /* These pins configure the BNX2X84823 interface to MAC after reset. */ | |
487 | #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008 | |
488 | #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010 | |
489 | /* These pins configure the BNX2X84823 interface to Line after reset. */ | |
490 | #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060 | |
491 | #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020 | |
492 | #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040 | |
493 | /* When this pin is active high during reset, 10GBASE-T core is power | |
494 | * down, When it is active low the 10GBASE-T is power up | |
495 | */ | |
496 | #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080 | |
497 | #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100 | |
498 | #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000 | |
499 | #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100 | |
500 | #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000 | |
501 | #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005 | |
502 | #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080 | |
503 | #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b | |
504 | #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f | |
505 | #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3 | |
506 | #define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec | |
507 | #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080 | |
508 | ||
509 | /* BNX2X84833 only */ | |
510 | #define MDIO_84833_TOP_CFG_FW_REV 0x400f | |
511 | #define MDIO_84833_TOP_CFG_FW_EEE 0x10b1 | |
512 | #define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81 | |
513 | #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a | |
514 | #define MDIO_84833_SUPER_ISOLATE 0x8000 | |
515 | /* These are mailbox register set used by 84833. */ | |
516 | #define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005 | |
517 | #define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006 | |
518 | #define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007 | |
519 | #define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008 | |
520 | #define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009 | |
521 | #define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037 | |
522 | #define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038 | |
523 | #define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039 | |
524 | #define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a | |
525 | #define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b | |
526 | #define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c | |
527 | #define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0 | |
528 | #define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26 | |
529 | #define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27 | |
530 | #define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28 | |
531 | #define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29 | |
532 | #define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30 | |
533 | #define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31 | |
534 | ||
535 | /* Mailbox command set used by 84833. */ | |
536 | #define PHY84833_CMD_SET_PAIR_SWAP 0x8001 | |
537 | #define PHY84833_CMD_GET_EEE_MODE 0x8008 | |
538 | #define PHY84833_CMD_SET_EEE_MODE 0x8009 | |
539 | #define PHY84833_CMD_GET_CURRENT_TEMP 0x8031 | |
540 | /* Mailbox status set used by 84833. */ | |
541 | #define PHY84833_STATUS_CMD_RECEIVED 0x0001 | |
542 | #define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002 | |
543 | #define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004 | |
544 | #define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008 | |
545 | #define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010 | |
546 | #define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020 | |
547 | #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040 | |
548 | #define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080 | |
549 | #define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5 | |
550 | ||
551 | /* Warpcore clause 45 addressing */ | |
552 | #define MDIO_WC_DEVAD 0x3 | |
553 | #define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0 | |
554 | #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7 | |
555 | #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10 | |
556 | #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11 | |
557 | #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12 | |
558 | #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000 | |
559 | #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000 | |
560 | #define MDIO_WC_REG_PCS_STATUS2 0x0021 | |
561 | #define MDIO_WC_REG_PMD_KR_CONTROL 0x0096 | |
562 | #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000 | |
563 | #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e | |
564 | #define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010 | |
565 | #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015 | |
566 | #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016 | |
567 | #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017 | |
568 | #define MDIO_WC_REG_XGXSBLK1_LANECTRL3 0x8018 | |
569 | #define MDIO_WC_REG_XGXSBLK1_LANETEST0 0x801a | |
570 | #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061 | |
571 | #define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071 | |
572 | #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081 | |
573 | #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091 | |
574 | #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067 | |
575 | #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04 | |
576 | #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0 | |
577 | #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08 | |
578 | #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 | |
579 | #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c | |
580 | #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000 | |
581 | #define MDIO_WC_REG_TX1_TX_DRIVER 0x8077 | |
582 | #define MDIO_WC_REG_TX2_TX_DRIVER 0x8087 | |
583 | #define MDIO_WC_REG_TX3_TX_DRIVER 0x8097 | |
584 | #define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9 | |
585 | #define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9 | |
586 | #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba | |
587 | #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca | |
588 | #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da | |
589 | #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea | |
590 | #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104 | |
591 | #define MDIO_WC_REG_XGXS_STATUS3 0x8129 | |
592 | #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130 | |
593 | #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131 | |
594 | #define MDIO_WC_REG_XGXS_STATUS4 0x813c | |
595 | #define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141 | |
596 | #define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142 | |
597 | #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B | |
598 | #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169 | |
599 | #define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0 | |
600 | #define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1 | |
601 | #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2 | |
602 | #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3 | |
603 | #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4 | |
604 | #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000 | |
605 | #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100 | |
606 | #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010 | |
607 | #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1 | |
608 | #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE | |
609 | #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0 | |
610 | #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2 | |
611 | #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0 | |
612 | #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0 | |
613 | #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1 | |
614 | #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2 | |
615 | #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3 | |
616 | #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4 | |
617 | #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4 | |
618 | #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8 | |
619 | #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc | |
620 | #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE | |
621 | #define MDIO_WC_REG_DSC1B0_UC_CTRL 0x820e | |
622 | #define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD (1<<7) | |
623 | #define MDIO_WC_REG_DSC_SMC 0x8213 | |
624 | #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e | |
625 | #define MDIO_WC_REG_TX_FIR_TAP 0x82e2 | |
626 | #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00 | |
627 | #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f | |
628 | #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04 | |
629 | #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0 | |
630 | #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a | |
631 | #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00 | |
632 | #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000 | |
633 | #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2 | |
634 | #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3 | |
635 | #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6 | |
636 | #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7 | |
637 | #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8 | |
638 | #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec | |
639 | #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300 | |
640 | #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301 | |
641 | #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302 | |
642 | #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304 | |
643 | #define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308 | |
644 | #define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309 | |
645 | #define MDIO_WC_REG_DIGITAL3_UP1 0x8329 | |
646 | #define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c | |
647 | #define MDIO_WC_REG_DIGITAL4_MISC3 0x833c | |
648 | #define MDIO_WC_REG_DIGITAL4_MISC5 0x833e | |
649 | #define MDIO_WC_REG_DIGITAL5_MISC6 0x8345 | |
650 | #define MDIO_WC_REG_DIGITAL5_MISC7 0x8349 | |
651 | #define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d | |
652 | #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e | |
653 | #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350 | |
654 | #define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368 | |
655 | #define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370 | |
656 | #define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371 | |
657 | #define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372 | |
658 | #define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373 | |
659 | #define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374 | |
660 | #define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b | |
661 | #define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390 | |
662 | #define MDIO_WC_REG_TX66_CONTROL 0x83b0 | |
663 | #define MDIO_WC_REG_RX66_CONTROL 0x83c0 | |
664 | #define MDIO_WC_REG_RX66_SCW0 0x83c2 | |
665 | #define MDIO_WC_REG_RX66_SCW1 0x83c3 | |
666 | #define MDIO_WC_REG_RX66_SCW2 0x83c4 | |
667 | #define MDIO_WC_REG_RX66_SCW3 0x83c5 | |
668 | #define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6 | |
669 | #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7 | |
670 | #define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8 | |
671 | #define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9 | |
672 | #define MDIO_WC_REG_FX100_CTRL1 0x8400 | |
673 | #define MDIO_WC_REG_FX100_CTRL3 0x8402 | |
674 | #define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436 | |
675 | #define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437 | |
676 | #define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438 | |
677 | #define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439 | |
678 | #define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a | |
679 | #define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b | |
680 | #define MDIO_WC_REG_ETA_CL73_OUI1 0x8453 | |
681 | #define MDIO_WC_REG_ETA_CL73_OUI2 0x8454 | |
682 | #define MDIO_WC_REG_ETA_CL73_OUI3 0x8455 | |
683 | #define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456 | |
684 | #define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457 | |
685 | #define MDIO_WC_REG_MICROBLK_CMD 0xffc2 | |
686 | #define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5 | |
687 | #define MDIO_WC_REG_MICROBLK_CMD3 0xffcc | |
688 | ||
689 | #define MDIO_WC_REG_AERBLK_AER 0xffde | |
690 | #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0 | |
691 | #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1 | |
692 | ||
693 | #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A | |
694 | #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0 | |
695 | #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4 | |
696 | ||
697 | #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141 | |
698 | ||
699 | #define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f | |
700 | ||
701 | /* 54618se */ | |
702 | #define MDIO_REG_GPHY_MII_STATUS 0x1 | |
703 | #define MDIO_REG_GPHY_PHYID_LSB 0x3 | |
704 | #define MDIO_REG_GPHY_CL45_ADDR_REG 0xd | |
705 | #define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000 | |
706 | #define MDIO_REG_GPHY_CL45_REG_READ 0xc000 | |
707 | #define MDIO_REG_GPHY_CL45_DATA_REG 0xe | |
708 | #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e | |
709 | #define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15 | |
710 | #define MDIO_REG_GPHY_EXP_ACCESS 0x17 | |
711 | #define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00 | |
712 | #define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40 | |
713 | #define MDIO_REG_GPHY_AUX_STATUS 0x19 | |
714 | #define MDIO_REG_INTR_STATUS 0x1a | |
715 | #define MDIO_REG_INTR_MASK 0x1b | |
716 | #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1) | |
717 | #define MDIO_REG_GPHY_SHADOW 0x1c | |
718 | #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10) | |
719 | #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10) | |
720 | #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15) | |
721 | #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10) | |
722 | #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8) | |
723 | ||
724 | typedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy, | |
725 | struct elink_params * | |
726 | params, | |
727 | uint8_t dev_addr, | |
728 | uint16_t addr, | |
729 | uint8_t byte_cnt, | |
730 | uint8_t * o_buf, | |
731 | uint8_t); | |
732 | /********************************************************/ | |
733 | #define ELINK_ETH_HLEN 14 | |
734 | /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ | |
735 | #define ELINK_ETH_OVREHEAD (ELINK_ETH_HLEN + 8 + 8) | |
736 | #define ELINK_ETH_MIN_PACKET_SIZE 60 | |
737 | #define ELINK_ETH_MAX_PACKET_SIZE 1500 | |
738 | #define ELINK_ETH_MAX_JUMBO_PACKET_SIZE 9600 | |
739 | #define ELINK_MDIO_ACCESS_TIMEOUT 1000 | |
740 | #define WC_LANE_MAX 4 | |
741 | #define I2C_SWITCH_WIDTH 2 | |
742 | #define I2C_BSC0 0 | |
743 | #define I2C_BSC1 1 | |
744 | #define I2C_WA_RETRY_CNT 3 | |
745 | #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) | |
746 | #define MCPR_IMC_COMMAND_READ_OP 1 | |
747 | #define MCPR_IMC_COMMAND_WRITE_OP 2 | |
748 | ||
749 | /* LED Blink rate that will achieve ~15.9Hz */ | |
750 | #define LED_BLINK_RATE_VAL_E3 354 | |
751 | #define LED_BLINK_RATE_VAL_E1X_E2 480 | |
752 | /***********************************************************/ | |
753 | /* Shortcut definitions */ | |
754 | /***********************************************************/ | |
755 | ||
756 | #define ELINK_NIG_LATCH_BC_ENABLE_MI_INT 0 | |
757 | ||
758 | #define ELINK_NIG_STATUS_EMAC0_MI_INT \ | |
759 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT | |
760 | #define ELINK_NIG_STATUS_XGXS0_LINK10G \ | |
761 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G | |
762 | #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS \ | |
763 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS | |
764 | #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ | |
765 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE | |
766 | #define ELINK_NIG_STATUS_SERDES0_LINK_STATUS \ | |
767 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS | |
768 | #define ELINK_NIG_MASK_MI_INT \ | |
769 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT | |
770 | #define ELINK_NIG_MASK_XGXS0_LINK10G \ | |
771 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G | |
772 | #define ELINK_NIG_MASK_XGXS0_LINK_STATUS \ | |
773 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS | |
774 | #define ELINK_NIG_MASK_SERDES0_LINK_STATUS \ | |
775 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS | |
776 | ||
777 | #define ELINK_MDIO_AN_CL73_OR_37_COMPLETE \ | |
778 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \ | |
779 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE) | |
780 | ||
781 | #define ELINK_XGXS_RESET_BITS \ | |
782 | (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \ | |
783 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \ | |
784 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \ | |
785 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \ | |
786 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB) | |
787 | ||
788 | #define ELINK_SERDES_RESET_BITS \ | |
789 | (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \ | |
790 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \ | |
791 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \ | |
792 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD) | |
793 | ||
794 | #define ELINK_AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 | |
795 | #define ELINK_AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 | |
796 | #define ELINK_AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM | |
797 | #define ELINK_AUTONEG_PARALLEL \ | |
798 | SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION | |
799 | #define ELINK_AUTONEG_SGMII_FIBER_AUTODET \ | |
800 | SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT | |
801 | #define ELINK_AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY | |
802 | ||
803 | #define ELINK_GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ | |
804 | MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE | |
805 | #define ELINK_GP_STATUS_PAUSE_RSOLUTION_RXSIDE \ | |
806 | MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE | |
807 | #define ELINK_GP_STATUS_SPEED_MASK \ | |
808 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK | |
809 | #define ELINK_GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M | |
810 | #define ELINK_GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M | |
811 | #define ELINK_GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G | |
812 | #define ELINK_GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G | |
813 | #define ELINK_GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G | |
814 | #define ELINK_GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G | |
815 | #define ELINK_GP_STATUS_10G_HIG \ | |
816 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG | |
817 | #define ELINK_GP_STATUS_10G_CX4 \ | |
818 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 | |
819 | #define ELINK_GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX | |
820 | #define ELINK_GP_STATUS_10G_KX4 \ | |
821 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 | |
822 | #define ELINK_GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR | |
823 | #define ELINK_GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI | |
824 | #define ELINK_GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS | |
825 | #define ELINK_GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI | |
826 | #define ELINK_GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 | |
827 | #define ELINK_LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD | |
828 | #define ELINK_LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD | |
829 | #define ELINK_LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD | |
830 | #define ELINK_LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 | |
831 | #define ELINK_LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD | |
832 | #define ELINK_LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD | |
833 | #define ELINK_LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD | |
834 | #define ELINK_LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD | |
835 | #define ELINK_LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD | |
836 | #define ELINK_LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD | |
837 | #define ELINK_LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD | |
838 | #define ELINK_LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD | |
839 | #define ELINK_LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD | |
840 | #define ELINK_LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD | |
841 | #define ELINK_LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD | |
842 | ||
843 | #define ELINK_LINK_UPDATE_MASK \ | |
844 | (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \ | |
845 | LINK_STATUS_LINK_UP | \ | |
846 | LINK_STATUS_PHYSICAL_LINK_FLAG | \ | |
847 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \ | |
848 | LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \ | |
849 | LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \ | |
850 | LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \ | |
851 | LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \ | |
852 | LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) | |
853 | ||
854 | #define ELINK_SFP_EEPROM_CON_TYPE_ADDR 0x2 | |
855 | #define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7 | |
856 | #define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 | |
857 | #define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22 | |
858 | ||
859 | #define ELINK_SFP_EEPROM_COMP_CODE_ADDR 0x3 | |
860 | #define ELINK_SFP_EEPROM_COMP_CODE_SR_MASK (1<<4) | |
861 | #define ELINK_SFP_EEPROM_COMP_CODE_LR_MASK (1<<5) | |
862 | #define ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6) | |
863 | ||
864 | #define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR 0x8 | |
865 | #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 | |
866 | #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 | |
867 | ||
868 | #define ELINK_SFP_EEPROM_OPTIONS_ADDR 0x40 | |
869 | #define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 | |
870 | #define ELINK_SFP_EEPROM_OPTIONS_SIZE 2 | |
871 | ||
872 | #define ELINK_EDC_MODE_LINEAR 0x0022 | |
873 | #define ELINK_EDC_MODE_LIMITING 0x0044 | |
874 | #define ELINK_EDC_MODE_PASSIVE_DAC 0x0055 | |
875 | #define ELINK_EDC_MODE_ACTIVE_DAC 0x0066 | |
876 | ||
877 | /* ETS defines*/ | |
878 | #define DCBX_INVALID_COS (0xFF) | |
879 | ||
880 | #define ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000) | |
881 | #define ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000) | |
882 | #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360) | |
883 | #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720) | |
884 | #define ELINK_ETS_E3B0_PBF_MIN_W_VAL (10000) | |
885 | ||
886 | #define ELINK_MAX_PACKET_SIZE (9700) | |
887 | #define MAX_KR_LINK_RETRY 4 | |
888 | ||
889 | /**********************************************************/ | |
890 | /* INTERFACE */ | |
891 | /**********************************************************/ | |
892 | ||
893 | #define CL22_WR_OVER_CL45(_sc, _phy, _bank, _addr, _val) \ | |
894 | elink_cl45_write(_sc, _phy, \ | |
895 | (_phy)->def_md_devad, \ | |
896 | (_bank + (_addr & 0xf)), \ | |
897 | _val) | |
898 | ||
899 | #define CL22_RD_OVER_CL45(_sc, _phy, _bank, _addr, _val) \ | |
900 | elink_cl45_read(_sc, _phy, \ | |
901 | (_phy)->def_md_devad, \ | |
902 | (_bank + (_addr & 0xf)), \ | |
903 | _val) | |
904 | ||
905 | static uint32_t elink_bits_en(struct bnx2x_softc *sc, uint32_t reg, uint32_t bits) | |
906 | { | |
907 | uint32_t val = REG_RD(sc, reg); | |
908 | ||
909 | val |= bits; | |
910 | REG_WR(sc, reg, val); | |
911 | return val; | |
912 | } | |
913 | ||
914 | static uint32_t elink_bits_dis(struct bnx2x_softc *sc, uint32_t reg, | |
915 | uint32_t bits) | |
916 | { | |
917 | uint32_t val = REG_RD(sc, reg); | |
918 | ||
919 | val &= ~bits; | |
920 | REG_WR(sc, reg, val); | |
921 | return val; | |
922 | } | |
923 | ||
924 | /* | |
925 | * elink_check_lfa - This function checks if link reinitialization is required, | |
926 | * or link flap can be avoided. | |
927 | * | |
928 | * @params: link parameters | |
929 | * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed | |
930 | * condition code. | |
931 | */ | |
932 | static int elink_check_lfa(struct elink_params *params) | |
933 | { | |
934 | uint32_t link_status, cfg_idx, lfa_mask, cfg_size; | |
935 | uint32_t cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config; | |
936 | uint32_t saved_val, req_val, eee_status; | |
937 | struct bnx2x_softc *sc = params->sc; | |
938 | ||
939 | additional_config = | |
940 | REG_RD(sc, params->lfa_base + | |
941 | offsetof(struct shmem_lfa, additional_config)); | |
942 | ||
943 | /* NOTE: must be first condition checked - | |
944 | * to verify DCC bit is cleared in any case! | |
945 | */ | |
946 | if (additional_config & NO_LFA_DUE_TO_DCC_MASK) { | |
947 | PMD_DRV_LOG(DEBUG, "No LFA due to DCC flap after clp exit"); | |
948 | REG_WR(sc, params->lfa_base + | |
949 | offsetof(struct shmem_lfa, additional_config), | |
950 | additional_config & ~NO_LFA_DUE_TO_DCC_MASK); | |
951 | return LFA_DCC_LFA_DISABLED; | |
952 | } | |
953 | ||
954 | /* Verify that link is up */ | |
955 | link_status = REG_RD(sc, params->shmem_base + | |
956 | offsetof(struct shmem_region, | |
957 | port_mb[params->port].link_status)); | |
958 | if (!(link_status & LINK_STATUS_LINK_UP)) | |
959 | return LFA_LINK_DOWN; | |
960 | ||
961 | /* if loaded after BOOT from SAN, don't flap the link in any case and | |
962 | * rely on link set by preboot driver | |
963 | */ | |
964 | if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BOOT_FROM_SAN) | |
965 | return 0; | |
966 | ||
967 | /* Verify that loopback mode is not set */ | |
968 | if (params->loopback_mode) | |
969 | return LFA_LOOPBACK_ENABLED; | |
970 | ||
971 | /* Verify that MFW supports LFA */ | |
972 | if (!params->lfa_base) | |
973 | return LFA_MFW_IS_TOO_OLD; | |
974 | ||
975 | if (params->num_phys == 3) { | |
976 | cfg_size = 2; | |
977 | lfa_mask = 0xffffffff; | |
978 | } else { | |
979 | cfg_size = 1; | |
980 | lfa_mask = 0xffff; | |
981 | } | |
982 | ||
983 | /* Compare Duplex */ | |
984 | saved_val = REG_RD(sc, params->lfa_base + | |
985 | offsetof(struct shmem_lfa, req_duplex)); | |
986 | req_val = params->req_duplex[0] | (params->req_duplex[1] << 16); | |
987 | if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { | |
988 | PMD_DRV_LOG(INFO, "Duplex mismatch %x vs. %x", | |
989 | (saved_val & lfa_mask), (req_val & lfa_mask)); | |
990 | return LFA_DUPLEX_MISMATCH; | |
991 | } | |
992 | /* Compare Flow Control */ | |
993 | saved_val = REG_RD(sc, params->lfa_base + | |
994 | offsetof(struct shmem_lfa, req_flow_ctrl)); | |
995 | req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16); | |
996 | if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { | |
997 | PMD_DRV_LOG(DEBUG, "Flow control mismatch %x vs. %x", | |
998 | (saved_val & lfa_mask), (req_val & lfa_mask)); | |
999 | return LFA_FLOW_CTRL_MISMATCH; | |
1000 | } | |
1001 | /* Compare Link Speed */ | |
1002 | saved_val = REG_RD(sc, params->lfa_base + | |
1003 | offsetof(struct shmem_lfa, req_line_speed)); | |
1004 | req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16); | |
1005 | if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { | |
1006 | PMD_DRV_LOG(DEBUG, "Link speed mismatch %x vs. %x", | |
1007 | (saved_val & lfa_mask), (req_val & lfa_mask)); | |
1008 | return LFA_LINK_SPEED_MISMATCH; | |
1009 | } | |
1010 | ||
1011 | for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) { | |
1012 | cur_speed_cap_mask = REG_RD(sc, params->lfa_base + | |
1013 | offsetof(struct shmem_lfa, | |
1014 | speed_cap_mask[cfg_idx])); | |
1015 | ||
1016 | if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) { | |
1017 | PMD_DRV_LOG(DEBUG, "Speed Cap mismatch %x vs. %x", | |
1018 | cur_speed_cap_mask, | |
1019 | params->speed_cap_mask[cfg_idx]); | |
1020 | return LFA_SPEED_CAP_MISMATCH; | |
1021 | } | |
1022 | } | |
1023 | ||
1024 | cur_req_fc_auto_adv = | |
1025 | REG_RD(sc, params->lfa_base + | |
1026 | offsetof(struct shmem_lfa, additional_config)) & | |
1027 | REQ_FC_AUTO_ADV_MASK; | |
1028 | ||
1029 | if ((uint16_t) cur_req_fc_auto_adv != params->req_fc_auto_adv) { | |
1030 | PMD_DRV_LOG(DEBUG, "Flow Ctrl AN mismatch %x vs. %x", | |
1031 | cur_req_fc_auto_adv, params->req_fc_auto_adv); | |
1032 | return LFA_FLOW_CTRL_MISMATCH; | |
1033 | } | |
1034 | ||
1035 | eee_status = REG_RD(sc, params->shmem2_base + | |
1036 | offsetof(struct shmem2_region, | |
1037 | eee_status[params->port])); | |
1038 | ||
1039 | if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^ | |
1040 | (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) || | |
1041 | ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^ | |
1042 | (params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) { | |
1043 | PMD_DRV_LOG(DEBUG, "EEE mismatch %x vs. %x", params->eee_mode, | |
1044 | eee_status); | |
1045 | return LFA_EEE_MISMATCH; | |
1046 | } | |
1047 | ||
1048 | /* LFA conditions are met */ | |
1049 | return 0; | |
1050 | } | |
1051 | ||
1052 | /******************************************************************/ | |
1053 | /* EPIO/GPIO section */ | |
1054 | /******************************************************************/ | |
1055 | static void elink_get_epio(struct bnx2x_softc *sc, uint32_t epio_pin, | |
1056 | uint32_t * en) | |
1057 | { | |
1058 | uint32_t epio_mask, gp_oenable; | |
1059 | *en = 0; | |
1060 | /* Sanity check */ | |
1061 | if (epio_pin > 31) { | |
1062 | PMD_DRV_LOG(DEBUG, "Invalid EPIO pin %d to get", epio_pin); | |
1063 | return; | |
1064 | } | |
1065 | ||
1066 | epio_mask = 1 << epio_pin; | |
1067 | /* Set this EPIO to output */ | |
1068 | gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE); | |
1069 | REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); | |
1070 | ||
1071 | *en = (REG_RD(sc, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; | |
1072 | } | |
1073 | ||
1074 | static void elink_set_epio(struct bnx2x_softc *sc, uint32_t epio_pin, uint32_t en) | |
1075 | { | |
1076 | uint32_t epio_mask, gp_output, gp_oenable; | |
1077 | ||
1078 | /* Sanity check */ | |
1079 | if (epio_pin > 31) { | |
1080 | PMD_DRV_LOG(DEBUG, "Invalid EPIO pin %d to set", epio_pin); | |
1081 | return; | |
1082 | } | |
1083 | PMD_DRV_LOG(DEBUG, "Setting EPIO pin %d to %d", epio_pin, en); | |
1084 | epio_mask = 1 << epio_pin; | |
1085 | /* Set this EPIO to output */ | |
1086 | gp_output = REG_RD(sc, MCP_REG_MCPR_GP_OUTPUTS); | |
1087 | if (en) | |
1088 | gp_output |= epio_mask; | |
1089 | else | |
1090 | gp_output &= ~epio_mask; | |
1091 | ||
1092 | REG_WR(sc, MCP_REG_MCPR_GP_OUTPUTS, gp_output); | |
1093 | ||
1094 | /* Set the value for this EPIO */ | |
1095 | gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE); | |
1096 | REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); | |
1097 | } | |
1098 | ||
1099 | static void elink_set_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg, | |
1100 | uint32_t val) | |
1101 | { | |
1102 | if (pin_cfg == PIN_CFG_NA) | |
1103 | return; | |
1104 | if (pin_cfg >= PIN_CFG_EPIO0) { | |
1105 | elink_set_epio(sc, pin_cfg - PIN_CFG_EPIO0, val); | |
1106 | } else { | |
1107 | uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; | |
1108 | uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; | |
1109 | elink_cb_gpio_write(sc, gpio_num, (uint8_t) val, gpio_port); | |
1110 | } | |
1111 | } | |
1112 | ||
1113 | static uint32_t elink_get_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg, | |
1114 | uint32_t * val) | |
1115 | { | |
1116 | if (pin_cfg == PIN_CFG_NA) | |
1117 | return ELINK_STATUS_ERROR; | |
1118 | if (pin_cfg >= PIN_CFG_EPIO0) { | |
1119 | elink_get_epio(sc, pin_cfg - PIN_CFG_EPIO0, val); | |
1120 | } else { | |
1121 | uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; | |
1122 | uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; | |
1123 | *val = elink_cb_gpio_read(sc, gpio_num, gpio_port); | |
1124 | } | |
1125 | return ELINK_STATUS_OK; | |
1126 | ||
1127 | } | |
1128 | ||
1129 | /******************************************************************/ | |
1130 | /* PFC section */ | |
1131 | /******************************************************************/ | |
1132 | static void elink_update_pfc_xmac(struct elink_params *params, | |
1133 | struct elink_vars *vars) | |
1134 | { | |
1135 | struct bnx2x_softc *sc = params->sc; | |
1136 | uint32_t xmac_base; | |
1137 | uint32_t pause_val, pfc0_val, pfc1_val; | |
1138 | ||
1139 | /* XMAC base adrr */ | |
1140 | xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
1141 | ||
1142 | /* Initialize pause and pfc registers */ | |
1143 | pause_val = 0x18000; | |
1144 | pfc0_val = 0xFFFF8000; | |
1145 | pfc1_val = 0x2; | |
1146 | ||
1147 | /* No PFC support */ | |
1148 | if (!(params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)) { | |
1149 | ||
1150 | /* RX flow control - Process pause frame in receive direction | |
1151 | */ | |
1152 | if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) | |
1153 | pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN; | |
1154 | ||
1155 | /* TX flow control - Send pause packet when buffer is full */ | |
1156 | if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) | |
1157 | pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN; | |
1158 | } else { /* PFC support */ | |
1159 | pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN | | |
1160 | XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN | | |
1161 | XMAC_PFC_CTRL_HI_REG_RX_PFC_EN | | |
1162 | XMAC_PFC_CTRL_HI_REG_TX_PFC_EN | | |
1163 | XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; | |
1164 | /* Write pause and PFC registers */ | |
1165 | REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); | |
1166 | REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); | |
1167 | REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); | |
1168 | pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; | |
1169 | ||
1170 | } | |
1171 | ||
1172 | /* Write pause and PFC registers */ | |
1173 | REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); | |
1174 | REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); | |
1175 | REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); | |
1176 | ||
1177 | /* Set MAC address for source TX Pause/PFC frames */ | |
1178 | REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_LO, | |
1179 | ((params->mac_addr[2] << 24) | | |
1180 | (params->mac_addr[3] << 16) | | |
1181 | (params->mac_addr[4] << 8) | (params->mac_addr[5]))); | |
1182 | REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_HI, | |
1183 | ((params->mac_addr[0] << 8) | (params->mac_addr[1]))); | |
1184 | ||
1185 | DELAY(30); | |
1186 | } | |
1187 | ||
1188 | /******************************************************************/ | |
1189 | /* MAC/PBF section */ | |
1190 | /******************************************************************/ | |
1191 | static void elink_set_mdio_clk(struct bnx2x_softc *sc, uint32_t emac_base) | |
1192 | { | |
1193 | uint32_t new_mode, cur_mode; | |
1194 | uint32_t clc_cnt; | |
1195 | /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz | |
1196 | * (a value of 49==0x31) and make sure that the AUTO poll is off | |
1197 | */ | |
1198 | cur_mode = REG_RD(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE); | |
1199 | ||
1200 | if (USES_WARPCORE(sc)) | |
1201 | clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; | |
1202 | else | |
1203 | clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; | |
1204 | ||
1205 | if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) && | |
1206 | (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45))) | |
1207 | return; | |
1208 | ||
1209 | new_mode = cur_mode & | |
1210 | ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT); | |
1211 | new_mode |= clc_cnt; | |
1212 | new_mode |= (EMAC_MDIO_MODE_CLAUSE_45); | |
1213 | ||
1214 | PMD_DRV_LOG(DEBUG, "Changing emac_mode from 0x%x to 0x%x", | |
1215 | cur_mode, new_mode); | |
1216 | REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); | |
1217 | DELAY(40); | |
1218 | } | |
1219 | ||
1220 | static void elink_set_mdio_emac_per_phy(struct bnx2x_softc *sc, | |
1221 | struct elink_params *params) | |
1222 | { | |
1223 | uint8_t phy_index; | |
1224 | /* Set mdio clock per phy */ | |
1225 | for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; | |
1226 | phy_index++) | |
1227 | elink_set_mdio_clk(sc, params->phy[phy_index].mdio_ctrl); | |
1228 | } | |
1229 | ||
1230 | static uint8_t elink_is_4_port_mode(struct bnx2x_softc *sc) | |
1231 | { | |
1232 | uint32_t port4mode_ovwr_val; | |
1233 | /* Check 4-port override enabled */ | |
1234 | port4mode_ovwr_val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR); | |
1235 | if (port4mode_ovwr_val & (1 << 0)) { | |
1236 | /* Return 4-port mode override value */ | |
1237 | return (port4mode_ovwr_val & (1 << 1)) == (1 << 1); | |
1238 | } | |
1239 | /* Return 4-port mode from input pin */ | |
1240 | return (uint8_t) REG_RD(sc, MISC_REG_PORT4MODE_EN); | |
1241 | } | |
1242 | ||
1243 | static void elink_emac_init(struct elink_params *params) | |
1244 | { | |
1245 | /* reset and unreset the emac core */ | |
1246 | struct bnx2x_softc *sc = params->sc; | |
1247 | uint8_t port = params->port; | |
1248 | uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
1249 | uint32_t val; | |
1250 | uint16_t timeout; | |
1251 | ||
1252 | REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1253 | (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); | |
1254 | DELAY(5); | |
1255 | REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
1256 | (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); | |
1257 | ||
1258 | /* init emac - use read-modify-write */ | |
1259 | /* self clear reset */ | |
1260 | val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE); | |
1261 | elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, | |
1262 | (val | EMAC_MODE_RESET)); | |
1263 | ||
1264 | timeout = 200; | |
1265 | do { | |
1266 | val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE); | |
1267 | PMD_DRV_LOG(DEBUG, "EMAC reset reg is %u", val); | |
1268 | if (!timeout) { | |
1269 | PMD_DRV_LOG(DEBUG, "EMAC timeout!"); | |
1270 | return; | |
1271 | } | |
1272 | timeout--; | |
1273 | } while (val & EMAC_MODE_RESET); | |
1274 | ||
1275 | elink_set_mdio_emac_per_phy(sc, params); | |
1276 | /* Set mac address */ | |
1277 | val = ((params->mac_addr[0] << 8) | params->mac_addr[1]); | |
1278 | elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH, val); | |
1279 | ||
1280 | val = ((params->mac_addr[2] << 24) | | |
1281 | (params->mac_addr[3] << 16) | | |
1282 | (params->mac_addr[4] << 8) | params->mac_addr[5]); | |
1283 | elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH + 4, val); | |
1284 | } | |
1285 | ||
1286 | static void elink_set_xumac_nig(struct elink_params *params, | |
1287 | uint16_t tx_pause_en, uint8_t enable) | |
1288 | { | |
1289 | struct bnx2x_softc *sc = params->sc; | |
1290 | ||
1291 | REG_WR(sc, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, | |
1292 | enable); | |
1293 | REG_WR(sc, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, | |
1294 | enable); | |
1295 | REG_WR(sc, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : | |
1296 | NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en); | |
1297 | } | |
1298 | ||
1299 | static void elink_set_umac_rxtx(struct elink_params *params, uint8_t en) | |
1300 | { | |
1301 | uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
1302 | uint32_t val; | |
1303 | struct bnx2x_softc *sc = params->sc; | |
1304 | if (!(REG_RD(sc, MISC_REG_RESET_REG_2) & | |
1305 | (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) | |
1306 | return; | |
1307 | val = REG_RD(sc, umac_base + UMAC_REG_COMMAND_CONFIG); | |
1308 | if (en) | |
1309 | val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA | | |
1310 | UMAC_COMMAND_CONFIG_REG_RX_ENA); | |
1311 | else | |
1312 | val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA | | |
1313 | UMAC_COMMAND_CONFIG_REG_RX_ENA); | |
1314 | /* Disable RX and TX */ | |
1315 | REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val); | |
1316 | } | |
1317 | ||
1318 | static void elink_umac_enable(struct elink_params *params, | |
1319 | struct elink_vars *vars, uint8_t lb) | |
1320 | { | |
1321 | uint32_t val; | |
1322 | uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
1323 | struct bnx2x_softc *sc = params->sc; | |
1324 | /* Reset UMAC */ | |
1325 | REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1326 | (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); | |
1327 | DELAY(1000 * 1); | |
1328 | ||
1329 | REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
1330 | (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); | |
1331 | ||
1332 | PMD_DRV_LOG(DEBUG, "enabling UMAC"); | |
1333 | ||
1334 | /* This register opens the gate for the UMAC despite its name */ | |
1335 | REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 1); | |
1336 | ||
1337 | val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN | | |
1338 | UMAC_COMMAND_CONFIG_REG_PAD_EN | | |
1339 | UMAC_COMMAND_CONFIG_REG_SW_RESET | | |
1340 | UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK; | |
1341 | switch (vars->line_speed) { | |
1342 | case ELINK_SPEED_10: | |
1343 | val |= (0 << 2); | |
1344 | break; | |
1345 | case ELINK_SPEED_100: | |
1346 | val |= (1 << 2); | |
1347 | break; | |
1348 | case ELINK_SPEED_1000: | |
1349 | val |= (2 << 2); | |
1350 | break; | |
1351 | case ELINK_SPEED_2500: | |
1352 | val |= (3 << 2); | |
1353 | break; | |
1354 | default: | |
1355 | PMD_DRV_LOG(DEBUG, "Invalid speed for UMAC %d", | |
1356 | vars->line_speed); | |
1357 | break; | |
1358 | } | |
1359 | if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) | |
1360 | val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE; | |
1361 | ||
1362 | if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) | |
1363 | val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE; | |
1364 | ||
1365 | if (vars->duplex == DUPLEX_HALF) | |
1366 | val |= UMAC_COMMAND_CONFIG_REG_HD_ENA; | |
1367 | ||
1368 | REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val); | |
1369 | DELAY(50); | |
1370 | ||
1371 | /* Configure UMAC for EEE */ | |
1372 | if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { | |
1373 | PMD_DRV_LOG(DEBUG, "configured UMAC for EEE"); | |
1374 | REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL, | |
1375 | UMAC_UMAC_EEE_CTRL_REG_EEE_EN); | |
1376 | REG_WR(sc, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); | |
1377 | } else { | |
1378 | REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); | |
1379 | } | |
1380 | ||
1381 | /* Set MAC address for source TX Pause/PFC frames (under SW reset) */ | |
1382 | REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR0, | |
1383 | ((params->mac_addr[2] << 24) | | |
1384 | (params->mac_addr[3] << 16) | | |
1385 | (params->mac_addr[4] << 8) | (params->mac_addr[5]))); | |
1386 | REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR1, | |
1387 | ((params->mac_addr[0] << 8) | (params->mac_addr[1]))); | |
1388 | ||
1389 | /* Enable RX and TX */ | |
1390 | val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN; | |
1391 | val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | UMAC_COMMAND_CONFIG_REG_RX_ENA; | |
1392 | REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val); | |
1393 | DELAY(50); | |
1394 | ||
1395 | /* Remove SW Reset */ | |
1396 | val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET; | |
1397 | ||
1398 | /* Check loopback mode */ | |
1399 | if (lb) | |
1400 | val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA; | |
1401 | REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val); | |
1402 | ||
1403 | /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame | |
1404 | * length used by the MAC receive logic to check frames. | |
1405 | */ | |
1406 | REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710); | |
1407 | elink_set_xumac_nig(params, | |
1408 | ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1); | |
1409 | vars->mac_type = ELINK_MAC_TYPE_UMAC; | |
1410 | ||
1411 | } | |
1412 | ||
1413 | /* Define the XMAC mode */ | |
1414 | static void elink_xmac_init(struct elink_params *params, uint32_t max_speed) | |
1415 | { | |
1416 | struct bnx2x_softc *sc = params->sc; | |
1417 | uint32_t is_port4mode = elink_is_4_port_mode(sc); | |
1418 | ||
1419 | /* In 4-port mode, need to set the mode only once, so if XMAC is | |
1420 | * already out of reset, it means the mode has already been set, | |
1421 | * and it must not* reset the XMAC again, since it controls both | |
1422 | * ports of the path | |
1423 | */ | |
1424 | ||
1425 | if (((CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || | |
1426 | (CHIP_NUM(sc) == CHIP_NUM_57840_2_20) || | |
1427 | (CHIP_NUM(sc) == CHIP_NUM_57840_OBS)) && | |
1428 | is_port4mode && | |
1429 | (REG_RD(sc, MISC_REG_RESET_REG_2) & | |
1430 | MISC_REGISTERS_RESET_REG_2_XMAC)) { | |
1431 | PMD_DRV_LOG(DEBUG, "XMAC already out of reset in 4-port mode"); | |
1432 | return; | |
1433 | } | |
1434 | ||
1435 | /* Hard reset */ | |
1436 | REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1437 | MISC_REGISTERS_RESET_REG_2_XMAC); | |
1438 | DELAY(1000 * 1); | |
1439 | ||
1440 | REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
1441 | MISC_REGISTERS_RESET_REG_2_XMAC); | |
1442 | if (is_port4mode) { | |
1443 | PMD_DRV_LOG(DEBUG, "Init XMAC to 2 ports x 10G per path"); | |
1444 | ||
1445 | /* Set the number of ports on the system side to up to 2 */ | |
1446 | REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 1); | |
1447 | ||
1448 | /* Set the number of ports on the Warp Core to 10G */ | |
1449 | REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3); | |
1450 | } else { | |
1451 | /* Set the number of ports on the system side to 1 */ | |
1452 | REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 0); | |
1453 | if (max_speed == ELINK_SPEED_10000) { | |
1454 | PMD_DRV_LOG(DEBUG, | |
1455 | "Init XMAC to 10G x 1 port per path"); | |
1456 | /* Set the number of ports on the Warp Core to 10G */ | |
1457 | REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3); | |
1458 | } else { | |
1459 | PMD_DRV_LOG(DEBUG, | |
1460 | "Init XMAC to 20G x 2 ports per path"); | |
1461 | /* Set the number of ports on the Warp Core to 20G */ | |
1462 | REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 1); | |
1463 | } | |
1464 | } | |
1465 | /* Soft reset */ | |
1466 | REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1467 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); | |
1468 | DELAY(1000 * 1); | |
1469 | ||
1470 | REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
1471 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); | |
1472 | ||
1473 | } | |
1474 | ||
1475 | static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en) | |
1476 | { | |
1477 | uint8_t port = params->port; | |
1478 | struct bnx2x_softc *sc = params->sc; | |
1479 | uint32_t pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
1480 | uint32_t val; | |
1481 | ||
1482 | if (REG_RD(sc, MISC_REG_RESET_REG_2) & MISC_REGISTERS_RESET_REG_2_XMAC) { | |
1483 | /* Send an indication to change the state in the NIG back to XON | |
1484 | * Clearing this bit enables the next set of this bit to get | |
1485 | * rising edge | |
1486 | */ | |
1487 | pfc_ctrl = REG_RD(sc, xmac_base + XMAC_REG_PFC_CTRL_HI); | |
1488 | REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, | |
1489 | (pfc_ctrl & ~(1 << 1))); | |
1490 | REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, | |
1491 | (pfc_ctrl | (1 << 1))); | |
1492 | PMD_DRV_LOG(DEBUG, "Disable XMAC on port %x", port); | |
1493 | val = REG_RD(sc, xmac_base + XMAC_REG_CTRL); | |
1494 | if (en) | |
1495 | val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); | |
1496 | else | |
1497 | val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); | |
1498 | REG_WR(sc, xmac_base + XMAC_REG_CTRL, val); | |
1499 | } | |
1500 | } | |
1501 | ||
1502 | static elink_status_t elink_xmac_enable(struct elink_params *params, | |
1503 | struct elink_vars *vars, uint8_t lb) | |
1504 | { | |
1505 | uint32_t val, xmac_base; | |
1506 | struct bnx2x_softc *sc = params->sc; | |
1507 | PMD_DRV_LOG(DEBUG, "enabling XMAC"); | |
1508 | ||
1509 | xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
1510 | ||
1511 | elink_xmac_init(params, vars->line_speed); | |
1512 | ||
1513 | /* This register determines on which events the MAC will assert | |
1514 | * error on the i/f to the NIG along w/ EOP. | |
1515 | */ | |
1516 | ||
1517 | /* This register tells the NIG whether to send traffic to UMAC | |
1518 | * or XMAC | |
1519 | */ | |
1520 | REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 0); | |
1521 | ||
1522 | /* When XMAC is in XLGMII mode, disable sending idles for fault | |
1523 | * detection. | |
1524 | */ | |
1525 | if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) { | |
1526 | REG_WR(sc, xmac_base + XMAC_REG_RX_LSS_CTRL, | |
1527 | (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE | | |
1528 | XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE)); | |
1529 | REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); | |
1530 | REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, | |
1531 | XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | | |
1532 | XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); | |
1533 | } | |
1534 | /* Set Max packet size */ | |
1535 | REG_WR(sc, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); | |
1536 | ||
1537 | /* CRC append for Tx packets */ | |
1538 | REG_WR(sc, xmac_base + XMAC_REG_TX_CTRL, 0xC800); | |
1539 | ||
1540 | /* update PFC */ | |
1541 | elink_update_pfc_xmac(params, vars); | |
1542 | ||
1543 | if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { | |
1544 | PMD_DRV_LOG(DEBUG, "Setting XMAC for EEE"); | |
1545 | REG_WR(sc, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); | |
1546 | REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x1); | |
1547 | } else { | |
1548 | REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x0); | |
1549 | } | |
1550 | ||
1551 | /* Enable TX and RX */ | |
1552 | val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN; | |
1553 | ||
1554 | /* Set MAC in XLGMII mode for dual-mode */ | |
1555 | if ((vars->line_speed == ELINK_SPEED_20000) && | |
1556 | (params->phy[ELINK_INT_PHY].supported & | |
1557 | ELINK_SUPPORTED_20000baseKR2_Full)) | |
1558 | val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB; | |
1559 | ||
1560 | /* Check loopback mode */ | |
1561 | if (lb) | |
1562 | val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK; | |
1563 | REG_WR(sc, xmac_base + XMAC_REG_CTRL, val); | |
1564 | elink_set_xumac_nig(params, | |
1565 | ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1); | |
1566 | ||
1567 | vars->mac_type = ELINK_MAC_TYPE_XMAC; | |
1568 | ||
1569 | return ELINK_STATUS_OK; | |
1570 | } | |
1571 | ||
1572 | static elink_status_t elink_emac_enable(struct elink_params *params, | |
1573 | struct elink_vars *vars, uint8_t lb) | |
1574 | { | |
1575 | struct bnx2x_softc *sc = params->sc; | |
1576 | uint8_t port = params->port; | |
1577 | uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
1578 | uint32_t val; | |
1579 | ||
1580 | PMD_DRV_LOG(DEBUG, "enabling EMAC"); | |
1581 | ||
1582 | /* Disable BMAC */ | |
1583 | REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1584 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
1585 | ||
1586 | /* enable emac and not bmac */ | |
1587 | REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 1); | |
1588 | ||
1589 | if (vars->phy_flags & PHY_XGXS_FLAG) { | |
1590 | uint32_t ser_lane = ((params->lane_config & | |
1591 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> | |
1592 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
1593 | ||
1594 | PMD_DRV_LOG(DEBUG, "XGXS"); | |
1595 | /* select the master lanes (out of 0-3) */ | |
1596 | REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, ser_lane); | |
1597 | /* select XGXS */ | |
1598 | REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1); | |
1599 | ||
1600 | } else { /* SerDes */ | |
1601 | PMD_DRV_LOG(DEBUG, "SerDes"); | |
1602 | /* select SerDes */ | |
1603 | REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0); | |
1604 | } | |
1605 | ||
1606 | elink_bits_en(sc, emac_base + EMAC_REG_EMAC_RX_MODE, | |
1607 | EMAC_RX_MODE_RESET); | |
1608 | elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE, | |
1609 | EMAC_TX_MODE_RESET); | |
1610 | ||
1611 | /* pause enable/disable */ | |
1612 | elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE, | |
1613 | EMAC_RX_MODE_FLOW_EN); | |
1614 | ||
1615 | elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE, | |
1616 | (EMAC_TX_MODE_EXT_PAUSE_EN | | |
1617 | EMAC_TX_MODE_FLOW_EN)); | |
1618 | if (!(params->feature_config_flags & | |
1619 | ELINK_FEATURE_CONFIG_PFC_ENABLED)) { | |
1620 | if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) | |
1621 | elink_bits_en(sc, emac_base + | |
1622 | EMAC_REG_EMAC_RX_MODE, | |
1623 | EMAC_RX_MODE_FLOW_EN); | |
1624 | ||
1625 | if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) | |
1626 | elink_bits_en(sc, emac_base + | |
1627 | EMAC_REG_EMAC_TX_MODE, | |
1628 | (EMAC_TX_MODE_EXT_PAUSE_EN | | |
1629 | EMAC_TX_MODE_FLOW_EN)); | |
1630 | } else | |
1631 | elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE, | |
1632 | EMAC_TX_MODE_FLOW_EN); | |
1633 | ||
1634 | /* KEEP_VLAN_TAG, promiscuous */ | |
1635 | val = REG_RD(sc, emac_base + EMAC_REG_EMAC_RX_MODE); | |
1636 | val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; | |
1637 | ||
1638 | /* Setting this bit causes MAC control frames (except for pause | |
1639 | * frames) to be passed on for processing. This setting has no | |
1640 | * affect on the operation of the pause frames. This bit effects | |
1641 | * all packets regardless of RX Parser packet sorting logic. | |
1642 | * Turn the PFC off to make sure we are in Xon state before | |
1643 | * enabling it. | |
1644 | */ | |
1645 | elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, 0); | |
1646 | if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) { | |
1647 | PMD_DRV_LOG(DEBUG, "PFC is enabled"); | |
1648 | /* Enable PFC again */ | |
1649 | elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, | |
1650 | EMAC_REG_RX_PFC_MODE_RX_EN | | |
1651 | EMAC_REG_RX_PFC_MODE_TX_EN | | |
1652 | EMAC_REG_RX_PFC_MODE_PRIORITIES); | |
1653 | ||
1654 | elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_PARAM, | |
1655 | ((0x0101 << | |
1656 | EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) | | |
1657 | (0x00ff << | |
1658 | EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT))); | |
1659 | val |= EMAC_RX_MODE_KEEP_MAC_CONTROL; | |
1660 | } | |
1661 | elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MODE, val); | |
1662 | ||
1663 | /* Set Loopback */ | |
1664 | val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE); | |
1665 | if (lb) | |
1666 | val |= 0x810; | |
1667 | else | |
1668 | val &= ~0x810; | |
1669 | elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, val); | |
1670 | ||
1671 | /* Enable emac */ | |
1672 | REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 1); | |
1673 | ||
1674 | /* Enable emac for jumbo packets */ | |
1675 | elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MTU_SIZE, | |
1676 | (EMAC_RX_MTU_SIZE_JUMBO_ENA | | |
1677 | (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + | |
1678 | ELINK_ETH_OVREHEAD))); | |
1679 | ||
1680 | /* Strip CRC */ | |
1681 | REG_WR(sc, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port * 4, 0x1); | |
1682 | ||
1683 | /* Disable the NIG in/out to the bmac */ | |
1684 | REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0x0); | |
1685 | REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port * 4, 0x0); | |
1686 | REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0x0); | |
1687 | ||
1688 | /* Enable the NIG in/out to the emac */ | |
1689 | REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0x1); | |
1690 | val = 0; | |
1691 | if ((params->feature_config_flags & | |
1692 | ELINK_FEATURE_CONFIG_PFC_ENABLED) || | |
1693 | (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) | |
1694 | val = 1; | |
1695 | ||
1696 | REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port * 4, val); | |
1697 | REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0x1); | |
1698 | ||
1699 | REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x0); | |
1700 | ||
1701 | vars->mac_type = ELINK_MAC_TYPE_EMAC; | |
1702 | return ELINK_STATUS_OK; | |
1703 | } | |
1704 | ||
1705 | static void elink_update_pfc_bmac1(struct elink_params *params, | |
1706 | struct elink_vars *vars) | |
1707 | { | |
1708 | uint32_t wb_data[2]; | |
1709 | struct bnx2x_softc *sc = params->sc; | |
1710 | uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : | |
1711 | NIG_REG_INGRESS_BMAC0_MEM; | |
1712 | ||
1713 | uint32_t val = 0x14; | |
1714 | if ((!(params->feature_config_flags & | |
1715 | ELINK_FEATURE_CONFIG_PFC_ENABLED)) && | |
1716 | (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) | |
1717 | /* Enable BigMAC to react on received Pause packets */ | |
1718 | val |= (1 << 5); | |
1719 | wb_data[0] = val; | |
1720 | wb_data[1] = 0; | |
1721 | REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); | |
1722 | ||
1723 | /* TX control */ | |
1724 | val = 0xc0; | |
1725 | if (!(params->feature_config_flags & | |
1726 | ELINK_FEATURE_CONFIG_PFC_ENABLED) && | |
1727 | (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) | |
1728 | val |= 0x800000; | |
1729 | wb_data[0] = val; | |
1730 | wb_data[1] = 0; | |
1731 | REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); | |
1732 | } | |
1733 | ||
1734 | static void elink_update_pfc_bmac2(struct elink_params *params, | |
1735 | struct elink_vars *vars, uint8_t is_lb) | |
1736 | { | |
1737 | /* Set rx control: Strip CRC and enable BigMAC to relay | |
1738 | * control packets to the system as well | |
1739 | */ | |
1740 | uint32_t wb_data[2]; | |
1741 | struct bnx2x_softc *sc = params->sc; | |
1742 | uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : | |
1743 | NIG_REG_INGRESS_BMAC0_MEM; | |
1744 | uint32_t val = 0x14; | |
1745 | ||
1746 | if ((!(params->feature_config_flags & | |
1747 | ELINK_FEATURE_CONFIG_PFC_ENABLED)) && | |
1748 | (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) | |
1749 | /* Enable BigMAC to react on received Pause packets */ | |
1750 | val |= (1 << 5); | |
1751 | wb_data[0] = val; | |
1752 | wb_data[1] = 0; | |
1753 | REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); | |
1754 | DELAY(30); | |
1755 | ||
1756 | /* Tx control */ | |
1757 | val = 0xc0; | |
1758 | if (!(params->feature_config_flags & | |
1759 | ELINK_FEATURE_CONFIG_PFC_ENABLED) && | |
1760 | (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) | |
1761 | val |= 0x800000; | |
1762 | wb_data[0] = val; | |
1763 | wb_data[1] = 0; | |
1764 | REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); | |
1765 | ||
1766 | if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) { | |
1767 | PMD_DRV_LOG(DEBUG, "PFC is enabled"); | |
1768 | /* Enable PFC RX & TX & STATS and set 8 COS */ | |
1769 | wb_data[0] = 0x0; | |
1770 | wb_data[0] |= (1 << 0); /* RX */ | |
1771 | wb_data[0] |= (1 << 1); /* TX */ | |
1772 | wb_data[0] |= (1 << 2); /* Force initial Xon */ | |
1773 | wb_data[0] |= (1 << 3); /* 8 cos */ | |
1774 | wb_data[0] |= (1 << 5); /* STATS */ | |
1775 | wb_data[1] = 0; | |
1776 | REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, | |
1777 | wb_data, 2); | |
1778 | /* Clear the force Xon */ | |
1779 | wb_data[0] &= ~(1 << 2); | |
1780 | } else { | |
1781 | PMD_DRV_LOG(DEBUG, "PFC is disabled"); | |
1782 | /* Disable PFC RX & TX & STATS and set 8 COS */ | |
1783 | wb_data[0] = 0x8; | |
1784 | wb_data[1] = 0; | |
1785 | } | |
1786 | ||
1787 | REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); | |
1788 | ||
1789 | /* Set Time (based unit is 512 bit time) between automatic | |
1790 | * re-sending of PP packets amd enable automatic re-send of | |
1791 | * Per-Priroity Packet as long as pp_gen is asserted and | |
1792 | * pp_disable is low. | |
1793 | */ | |
1794 | val = 0x8000; | |
1795 | if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) | |
1796 | val |= (1 << 16); /* enable automatic re-send */ | |
1797 | ||
1798 | wb_data[0] = val; | |
1799 | wb_data[1] = 0; | |
1800 | REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, | |
1801 | wb_data, 2); | |
1802 | ||
1803 | /* mac control */ | |
1804 | val = 0x3; /* Enable RX and TX */ | |
1805 | if (is_lb) { | |
1806 | val |= 0x4; /* Local loopback */ | |
1807 | PMD_DRV_LOG(DEBUG, "enable bmac loopback"); | |
1808 | } | |
1809 | /* When PFC enabled, Pass pause frames towards the NIG. */ | |
1810 | if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) | |
1811 | val |= ((1 << 6) | (1 << 5)); | |
1812 | ||
1813 | wb_data[0] = val; | |
1814 | wb_data[1] = 0; | |
1815 | REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); | |
1816 | } | |
1817 | ||
1818 | /****************************************************************************** | |
1819 | * Description: | |
1820 | * This function is needed because NIG ARB_CREDIT_WEIGHT_X are | |
1821 | * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. | |
1822 | ******************************************************************************/ | |
1823 | static elink_status_t elink_pfc_nig_rx_priority_mask(struct bnx2x_softc *sc, | |
1824 | uint8_t cos_entry, | |
1825 | uint32_t priority_mask, | |
1826 | uint8_t port) | |
1827 | { | |
1828 | uint32_t nig_reg_rx_priority_mask_add = 0; | |
1829 | ||
1830 | switch (cos_entry) { | |
1831 | case 0: | |
1832 | nig_reg_rx_priority_mask_add = (port) ? | |
1833 | NIG_REG_P1_RX_COS0_PRIORITY_MASK : | |
1834 | NIG_REG_P0_RX_COS0_PRIORITY_MASK; | |
1835 | break; | |
1836 | case 1: | |
1837 | nig_reg_rx_priority_mask_add = (port) ? | |
1838 | NIG_REG_P1_RX_COS1_PRIORITY_MASK : | |
1839 | NIG_REG_P0_RX_COS1_PRIORITY_MASK; | |
1840 | break; | |
1841 | case 2: | |
1842 | nig_reg_rx_priority_mask_add = (port) ? | |
1843 | NIG_REG_P1_RX_COS2_PRIORITY_MASK : | |
1844 | NIG_REG_P0_RX_COS2_PRIORITY_MASK; | |
1845 | break; | |
1846 | case 3: | |
1847 | if (port) | |
1848 | return ELINK_STATUS_ERROR; | |
1849 | nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK; | |
1850 | break; | |
1851 | case 4: | |
1852 | if (port) | |
1853 | return ELINK_STATUS_ERROR; | |
1854 | nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK; | |
1855 | break; | |
1856 | case 5: | |
1857 | if (port) | |
1858 | return ELINK_STATUS_ERROR; | |
1859 | nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK; | |
1860 | break; | |
1861 | } | |
1862 | ||
1863 | REG_WR(sc, nig_reg_rx_priority_mask_add, priority_mask); | |
1864 | ||
1865 | return ELINK_STATUS_OK; | |
1866 | } | |
1867 | ||
1868 | static void elink_update_mng(struct elink_params *params, uint32_t link_status) | |
1869 | { | |
1870 | struct bnx2x_softc *sc = params->sc; | |
1871 | ||
1872 | REG_WR(sc, params->shmem_base + | |
1873 | offsetof(struct shmem_region, | |
1874 | port_mb[params->port].link_status), link_status); | |
1875 | } | |
1876 | ||
1877 | static void elink_update_link_attr(struct elink_params *params, | |
1878 | uint32_t link_attr) | |
1879 | { | |
1880 | struct bnx2x_softc *sc = params->sc; | |
1881 | ||
1882 | if (SHMEM2_HAS(sc, link_attr_sync)) | |
1883 | REG_WR(sc, params->shmem2_base + | |
1884 | offsetof(struct shmem2_region, | |
1885 | link_attr_sync[params->port]), link_attr); | |
1886 | } | |
1887 | ||
1888 | static void elink_update_pfc_nig(struct elink_params *params, | |
1889 | struct elink_nig_brb_pfc_port_params | |
1890 | *nig_params) | |
1891 | { | |
1892 | uint32_t xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = | |
1893 | 0; | |
1894 | uint32_t llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0; | |
1895 | uint32_t pkt_priority_to_cos = 0; | |
1896 | struct bnx2x_softc *sc = params->sc; | |
1897 | uint8_t port = params->port; | |
1898 | ||
1899 | int set_pfc = params->feature_config_flags & | |
1900 | ELINK_FEATURE_CONFIG_PFC_ENABLED; | |
1901 | PMD_DRV_LOG(DEBUG, "updating pfc nig parameters"); | |
1902 | ||
1903 | /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set | |
1904 | * MAC control frames (that are not pause packets) | |
1905 | * will be forwarded to the XCM. | |
1906 | */ | |
1907 | xcm_mask = REG_RD(sc, port ? NIG_REG_LLH1_XCM_MASK : | |
1908 | NIG_REG_LLH0_XCM_MASK); | |
1909 | /* NIG params will override non PFC params, since it's possible to | |
1910 | * do transition from PFC to SAFC | |
1911 | */ | |
1912 | if (set_pfc) { | |
1913 | pause_enable = 0; | |
1914 | llfc_out_en = 0; | |
1915 | llfc_enable = 0; | |
1916 | if (CHIP_IS_E3(sc)) | |
1917 | ppp_enable = 0; | |
1918 | else | |
1919 | ppp_enable = 1; | |
1920 | xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : | |
1921 | NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); | |
1922 | xcm_out_en = 0; | |
1923 | hwpfc_enable = 1; | |
1924 | } else { | |
1925 | if (nig_params) { | |
1926 | llfc_out_en = nig_params->llfc_out_en; | |
1927 | llfc_enable = nig_params->llfc_enable; | |
1928 | pause_enable = nig_params->pause_enable; | |
1929 | } else /* Default non PFC mode - PAUSE */ | |
1930 | pause_enable = 1; | |
1931 | ||
1932 | xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : | |
1933 | NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); | |
1934 | xcm_out_en = 1; | |
1935 | } | |
1936 | ||
1937 | if (CHIP_IS_E3(sc)) | |
1938 | REG_WR(sc, port ? NIG_REG_BRB1_PAUSE_IN_EN : | |
1939 | NIG_REG_BRB0_PAUSE_IN_EN, pause_enable); | |
1940 | REG_WR(sc, port ? NIG_REG_LLFC_OUT_EN_1 : | |
1941 | NIG_REG_LLFC_OUT_EN_0, llfc_out_en); | |
1942 | REG_WR(sc, port ? NIG_REG_LLFC_ENABLE_1 : | |
1943 | NIG_REG_LLFC_ENABLE_0, llfc_enable); | |
1944 | REG_WR(sc, port ? NIG_REG_PAUSE_ENABLE_1 : | |
1945 | NIG_REG_PAUSE_ENABLE_0, pause_enable); | |
1946 | ||
1947 | REG_WR(sc, port ? NIG_REG_PPP_ENABLE_1 : | |
1948 | NIG_REG_PPP_ENABLE_0, ppp_enable); | |
1949 | ||
1950 | REG_WR(sc, port ? NIG_REG_LLH1_XCM_MASK : | |
1951 | NIG_REG_LLH0_XCM_MASK, xcm_mask); | |
1952 | ||
1953 | REG_WR(sc, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : | |
1954 | NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7); | |
1955 | ||
1956 | /* Output enable for RX_XCM # IF */ | |
1957 | REG_WR(sc, port ? NIG_REG_XCM1_OUT_EN : | |
1958 | NIG_REG_XCM0_OUT_EN, xcm_out_en); | |
1959 | ||
1960 | /* HW PFC TX enable */ | |
1961 | REG_WR(sc, port ? NIG_REG_P1_HWPFC_ENABLE : | |
1962 | NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable); | |
1963 | ||
1964 | if (nig_params) { | |
1965 | uint8_t i = 0; | |
1966 | pkt_priority_to_cos = nig_params->pkt_priority_to_cos; | |
1967 | ||
1968 | for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) | |
1969 | elink_pfc_nig_rx_priority_mask(sc, i, | |
1970 | nig_params-> | |
1971 | rx_cos_priority_mask[i], | |
1972 | port); | |
1973 | ||
1974 | REG_WR(sc, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : | |
1975 | NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0, | |
1976 | nig_params->llfc_high_priority_classes); | |
1977 | ||
1978 | REG_WR(sc, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : | |
1979 | NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0, | |
1980 | nig_params->llfc_low_priority_classes); | |
1981 | } | |
1982 | REG_WR(sc, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : | |
1983 | NIG_REG_P0_PKT_PRIORITY_TO_COS, pkt_priority_to_cos); | |
1984 | } | |
1985 | ||
1986 | elink_status_t elink_update_pfc(struct elink_params *params, | |
1987 | struct elink_vars *vars, | |
1988 | struct elink_nig_brb_pfc_port_params | |
1989 | *pfc_params) | |
1990 | { | |
1991 | /* The PFC and pause are orthogonal to one another, meaning when | |
1992 | * PFC is enabled, the pause are disabled, and when PFC is | |
1993 | * disabled, pause are set according to the pause result. | |
1994 | */ | |
1995 | uint32_t val; | |
1996 | struct bnx2x_softc *sc = params->sc; | |
1997 | elink_status_t elink_status = ELINK_STATUS_OK; | |
1998 | uint8_t bmac_loopback = (params->loopback_mode == ELINK_LOOPBACK_BMAC); | |
1999 | ||
2000 | if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) | |
2001 | vars->link_status |= LINK_STATUS_PFC_ENABLED; | |
2002 | else | |
2003 | vars->link_status &= ~LINK_STATUS_PFC_ENABLED; | |
2004 | ||
2005 | elink_update_mng(params, vars->link_status); | |
2006 | ||
2007 | /* Update NIG params */ | |
2008 | elink_update_pfc_nig(params, pfc_params); | |
2009 | ||
2010 | if (!vars->link_up) | |
2011 | return elink_status; | |
2012 | ||
2013 | PMD_DRV_LOG(DEBUG, "About to update PFC in BMAC"); | |
2014 | ||
2015 | if (CHIP_IS_E3(sc)) { | |
2016 | if (vars->mac_type == ELINK_MAC_TYPE_XMAC) | |
2017 | elink_update_pfc_xmac(params, vars); | |
2018 | } else { | |
2019 | val = REG_RD(sc, MISC_REG_RESET_REG_2); | |
2020 | if ((val & | |
2021 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) | |
2022 | == 0) { | |
2023 | PMD_DRV_LOG(DEBUG, "About to update PFC in EMAC"); | |
2024 | elink_emac_enable(params, vars, 0); | |
2025 | return elink_status; | |
2026 | } | |
2027 | if (CHIP_IS_E2(sc)) | |
2028 | elink_update_pfc_bmac2(params, vars, bmac_loopback); | |
2029 | else | |
2030 | elink_update_pfc_bmac1(params, vars); | |
2031 | ||
2032 | val = 0; | |
2033 | if ((params->feature_config_flags & | |
2034 | ELINK_FEATURE_CONFIG_PFC_ENABLED) || | |
2035 | (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) | |
2036 | val = 1; | |
2037 | REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port * 4, val); | |
2038 | } | |
2039 | return elink_status; | |
2040 | } | |
2041 | ||
2042 | static elink_status_t elink_bmac1_enable(struct elink_params *params, | |
2043 | struct elink_vars *vars, uint8_t is_lb) | |
2044 | { | |
2045 | struct bnx2x_softc *sc = params->sc; | |
2046 | uint8_t port = params->port; | |
2047 | uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
2048 | NIG_REG_INGRESS_BMAC0_MEM; | |
2049 | uint32_t wb_data[2]; | |
2050 | uint32_t val; | |
2051 | ||
2052 | PMD_DRV_LOG(DEBUG, "Enabling BigMAC1"); | |
2053 | ||
2054 | /* XGXS control */ | |
2055 | wb_data[0] = 0x3c; | |
2056 | wb_data[1] = 0; | |
2057 | REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, | |
2058 | wb_data, 2); | |
2059 | ||
2060 | /* TX MAC SA */ | |
2061 | wb_data[0] = ((params->mac_addr[2] << 24) | | |
2062 | (params->mac_addr[3] << 16) | | |
2063 | (params->mac_addr[4] << 8) | params->mac_addr[5]); | |
2064 | wb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]); | |
2065 | REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); | |
2066 | ||
2067 | /* MAC control */ | |
2068 | val = 0x3; | |
2069 | if (is_lb) { | |
2070 | val |= 0x4; | |
2071 | PMD_DRV_LOG(DEBUG, "enable bmac loopback"); | |
2072 | } | |
2073 | wb_data[0] = val; | |
2074 | wb_data[1] = 0; | |
2075 | REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); | |
2076 | ||
2077 | /* Set rx mtu */ | |
2078 | wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; | |
2079 | wb_data[1] = 0; | |
2080 | REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); | |
2081 | ||
2082 | elink_update_pfc_bmac1(params, vars); | |
2083 | ||
2084 | /* Set tx mtu */ | |
2085 | wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; | |
2086 | wb_data[1] = 0; | |
2087 | REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); | |
2088 | ||
2089 | /* Set cnt max size */ | |
2090 | wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; | |
2091 | wb_data[1] = 0; | |
2092 | REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); | |
2093 | ||
2094 | /* Configure SAFC */ | |
2095 | wb_data[0] = 0x1000200; | |
2096 | wb_data[1] = 0; | |
2097 | REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, | |
2098 | wb_data, 2); | |
2099 | ||
2100 | return ELINK_STATUS_OK; | |
2101 | } | |
2102 | ||
2103 | static elink_status_t elink_bmac2_enable(struct elink_params *params, | |
2104 | struct elink_vars *vars, uint8_t is_lb) | |
2105 | { | |
2106 | struct bnx2x_softc *sc = params->sc; | |
2107 | uint8_t port = params->port; | |
2108 | uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
2109 | NIG_REG_INGRESS_BMAC0_MEM; | |
2110 | uint32_t wb_data[2]; | |
2111 | ||
2112 | PMD_DRV_LOG(DEBUG, "Enabling BigMAC2"); | |
2113 | ||
2114 | wb_data[0] = 0; | |
2115 | wb_data[1] = 0; | |
2116 | REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); | |
2117 | DELAY(30); | |
2118 | ||
2119 | /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ | |
2120 | wb_data[0] = 0x3c; | |
2121 | wb_data[1] = 0; | |
2122 | REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, | |
2123 | wb_data, 2); | |
2124 | ||
2125 | DELAY(30); | |
2126 | ||
2127 | /* TX MAC SA */ | |
2128 | wb_data[0] = ((params->mac_addr[2] << 24) | | |
2129 | (params->mac_addr[3] << 16) | | |
2130 | (params->mac_addr[4] << 8) | params->mac_addr[5]); | |
2131 | wb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]); | |
2132 | REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, | |
2133 | wb_data, 2); | |
2134 | ||
2135 | DELAY(30); | |
2136 | ||
2137 | /* Configure SAFC */ | |
2138 | wb_data[0] = 0x1000200; | |
2139 | wb_data[1] = 0; | |
2140 | REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, | |
2141 | wb_data, 2); | |
2142 | DELAY(30); | |
2143 | ||
2144 | /* Set RX MTU */ | |
2145 | wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; | |
2146 | wb_data[1] = 0; | |
2147 | REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); | |
2148 | DELAY(30); | |
2149 | ||
2150 | /* Set TX MTU */ | |
2151 | wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; | |
2152 | wb_data[1] = 0; | |
2153 | REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); | |
2154 | DELAY(30); | |
2155 | /* Set cnt max size */ | |
2156 | wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD - 2; | |
2157 | wb_data[1] = 0; | |
2158 | REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); | |
2159 | DELAY(30); | |
2160 | elink_update_pfc_bmac2(params, vars, is_lb); | |
2161 | ||
2162 | return ELINK_STATUS_OK; | |
2163 | } | |
2164 | ||
2165 | static elink_status_t elink_bmac_enable(struct elink_params *params, | |
2166 | struct elink_vars *vars, | |
2167 | uint8_t is_lb, uint8_t reset_bmac) | |
2168 | { | |
2169 | elink_status_t rc = ELINK_STATUS_OK; | |
2170 | uint8_t port = params->port; | |
2171 | struct bnx2x_softc *sc = params->sc; | |
2172 | uint32_t val; | |
2173 | /* Reset and unreset the BigMac */ | |
2174 | if (reset_bmac) { | |
2175 | REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
2176 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
2177 | DELAY(1000 * 1); | |
2178 | } | |
2179 | ||
2180 | REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
2181 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
2182 | ||
2183 | /* Enable access for bmac registers */ | |
2184 | REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x1); | |
2185 | ||
2186 | /* Enable BMAC according to BMAC type */ | |
2187 | if (CHIP_IS_E2(sc)) | |
2188 | rc = elink_bmac2_enable(params, vars, is_lb); | |
2189 | else | |
2190 | rc = elink_bmac1_enable(params, vars, is_lb); | |
2191 | REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0x1); | |
2192 | REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 0x0); | |
2193 | REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 0x0); | |
2194 | val = 0; | |
2195 | if ((params->feature_config_flags & | |
2196 | ELINK_FEATURE_CONFIG_PFC_ENABLED) || | |
2197 | (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) | |
2198 | val = 1; | |
2199 | REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port * 4, val); | |
2200 | REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0x0); | |
2201 | REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0x0); | |
2202 | REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port * 4, 0x0); | |
2203 | REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0x1); | |
2204 | REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0x1); | |
2205 | ||
2206 | vars->mac_type = ELINK_MAC_TYPE_BMAC; | |
2207 | return rc; | |
2208 | } | |
2209 | ||
2210 | static void elink_set_bmac_rx(struct bnx2x_softc *sc, uint8_t port, uint8_t en) | |
2211 | { | |
2212 | uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
2213 | NIG_REG_INGRESS_BMAC0_MEM; | |
2214 | uint32_t wb_data[2]; | |
2215 | uint32_t nig_bmac_enable = | |
2216 | REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); | |
2217 | ||
2218 | if (CHIP_IS_E2(sc)) | |
2219 | bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL; | |
2220 | else | |
2221 | bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL; | |
2222 | /* Only if the bmac is out of reset */ | |
2223 | if (REG_RD(sc, MISC_REG_RESET_REG_2) & | |
2224 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && nig_bmac_enable) { | |
2225 | /* Clear Rx Enable bit in BMAC_CONTROL register */ | |
2226 | REG_RD_DMAE(sc, bmac_addr, wb_data, 2); | |
2227 | if (en) | |
2228 | wb_data[0] |= ELINK_BMAC_CONTROL_RX_ENABLE; | |
2229 | else | |
2230 | wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE; | |
2231 | REG_WR_DMAE(sc, bmac_addr, wb_data, 2); | |
2232 | DELAY(1000 * 1); | |
2233 | } | |
2234 | } | |
2235 | ||
2236 | static elink_status_t elink_pbf_update(struct elink_params *params, | |
2237 | uint32_t flow_ctrl, uint32_t line_speed) | |
2238 | { | |
2239 | struct bnx2x_softc *sc = params->sc; | |
2240 | uint8_t port = params->port; | |
2241 | uint32_t init_crd, crd; | |
2242 | uint32_t count = 1000; | |
2243 | ||
2244 | /* Disable port */ | |
2245 | REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port * 4, 0x1); | |
2246 | ||
2247 | /* Wait for init credit */ | |
2248 | init_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port * 4); | |
2249 | crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8); | |
2250 | PMD_DRV_LOG(DEBUG, "init_crd 0x%x crd 0x%x", init_crd, crd); | |
2251 | ||
2252 | while ((init_crd != crd) && count) { | |
2253 | DELAY(1000 * 5); | |
2254 | crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8); | |
2255 | count--; | |
2256 | } | |
2257 | crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8); | |
2258 | if (init_crd != crd) { | |
2259 | PMD_DRV_LOG(DEBUG, "BUG! init_crd 0x%x != crd 0x%x", | |
2260 | init_crd, crd); | |
2261 | return ELINK_STATUS_ERROR; | |
2262 | } | |
2263 | ||
2264 | if (flow_ctrl & ELINK_FLOW_CTRL_RX || | |
2265 | line_speed == ELINK_SPEED_10 || | |
2266 | line_speed == ELINK_SPEED_100 || | |
2267 | line_speed == ELINK_SPEED_1000 || line_speed == ELINK_SPEED_2500) { | |
2268 | REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 1); | |
2269 | /* Update threshold */ | |
2270 | REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, 0); | |
2271 | /* Update init credit */ | |
2272 | init_crd = 778; /* (800-18-4) */ | |
2273 | ||
2274 | } else { | |
2275 | uint32_t thresh = (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + | |
2276 | ELINK_ETH_OVREHEAD) / 16; | |
2277 | REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0); | |
2278 | /* Update threshold */ | |
2279 | REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, thresh); | |
2280 | /* Update init credit */ | |
2281 | switch (line_speed) { | |
2282 | case ELINK_SPEED_10000: | |
2283 | init_crd = thresh + 553 - 22; | |
2284 | break; | |
2285 | default: | |
2286 | PMD_DRV_LOG(DEBUG, "Invalid line_speed 0x%x", | |
2287 | line_speed); | |
2288 | return ELINK_STATUS_ERROR; | |
2289 | } | |
2290 | } | |
2291 | REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4, init_crd); | |
2292 | PMD_DRV_LOG(DEBUG, "PBF updated to speed %d credit %d", | |
2293 | line_speed, init_crd); | |
2294 | ||
2295 | /* Probe the credit changes */ | |
2296 | REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0x1); | |
2297 | DELAY(1000 * 5); | |
2298 | REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0x0); | |
2299 | ||
2300 | /* Enable port */ | |
2301 | REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port * 4, 0x0); | |
2302 | return ELINK_STATUS_OK; | |
2303 | } | |
2304 | ||
2305 | /** | |
2306 | * elink_get_emac_base - retrive emac base address | |
2307 | * | |
2308 | * @bp: driver handle | |
2309 | * @mdc_mdio_access: access type | |
2310 | * @port: port id | |
2311 | * | |
2312 | * This function selects the MDC/MDIO access (through emac0 or | |
2313 | * emac1) depend on the mdc_mdio_access, port, port swapped. Each | |
2314 | * phy has a default access mode, which could also be overridden | |
2315 | * by nvram configuration. This parameter, whether this is the | |
2316 | * default phy configuration, or the nvram overrun | |
2317 | * configuration, is passed here as mdc_mdio_access and selects | |
2318 | * the emac_base for the CL45 read/writes operations | |
2319 | */ | |
2320 | static uint32_t elink_get_emac_base(struct bnx2x_softc *sc, | |
2321 | uint32_t mdc_mdio_access, uint8_t port) | |
2322 | { | |
2323 | uint32_t emac_base = 0; | |
2324 | switch (mdc_mdio_access) { | |
2325 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE: | |
2326 | break; | |
2327 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0: | |
2328 | if (REG_RD(sc, NIG_REG_PORT_SWAP)) | |
2329 | emac_base = GRCBASE_EMAC1; | |
2330 | else | |
2331 | emac_base = GRCBASE_EMAC0; | |
2332 | break; | |
2333 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1: | |
2334 | if (REG_RD(sc, NIG_REG_PORT_SWAP)) | |
2335 | emac_base = GRCBASE_EMAC0; | |
2336 | else | |
2337 | emac_base = GRCBASE_EMAC1; | |
2338 | break; | |
2339 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH: | |
2340 | emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
2341 | break; | |
2342 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED: | |
2343 | emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; | |
2344 | break; | |
2345 | default: | |
2346 | break; | |
2347 | } | |
2348 | return emac_base; | |
2349 | ||
2350 | } | |
2351 | ||
2352 | /******************************************************************/ | |
2353 | /* CL22 access functions */ | |
2354 | /******************************************************************/ | |
2355 | static elink_status_t elink_cl22_write(struct bnx2x_softc *sc, | |
2356 | struct elink_phy *phy, | |
2357 | uint16_t reg, uint16_t val) | |
2358 | { | |
2359 | uint32_t tmp, mode; | |
2360 | uint8_t i; | |
2361 | elink_status_t rc = ELINK_STATUS_OK; | |
2362 | /* Switch to CL22 */ | |
2363 | mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); | |
2364 | REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, | |
2365 | mode & ~EMAC_MDIO_MODE_CLAUSE_45); | |
2366 | ||
2367 | /* Address */ | |
2368 | tmp = ((phy->addr << 21) | (reg << 16) | val | | |
2369 | EMAC_MDIO_COMM_COMMAND_WRITE_22 | EMAC_MDIO_COMM_START_BUSY); | |
2370 | REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); | |
2371 | ||
2372 | for (i = 0; i < 50; i++) { | |
2373 | DELAY(10); | |
2374 | ||
2375 | tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); | |
2376 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { | |
2377 | DELAY(5); | |
2378 | break; | |
2379 | } | |
2380 | } | |
2381 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { | |
2382 | PMD_DRV_LOG(DEBUG, "write phy register failed"); | |
2383 | rc = ELINK_STATUS_TIMEOUT; | |
2384 | } | |
2385 | REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); | |
2386 | return rc; | |
2387 | } | |
2388 | ||
2389 | static elink_status_t elink_cl22_read(struct bnx2x_softc *sc, | |
2390 | struct elink_phy *phy, | |
2391 | uint16_t reg, uint16_t * ret_val) | |
2392 | { | |
2393 | uint32_t val, mode; | |
2394 | uint16_t i; | |
2395 | elink_status_t rc = ELINK_STATUS_OK; | |
2396 | ||
2397 | /* Switch to CL22 */ | |
2398 | mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); | |
2399 | REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, | |
2400 | mode & ~EMAC_MDIO_MODE_CLAUSE_45); | |
2401 | ||
2402 | /* Address */ | |
2403 | val = ((phy->addr << 21) | (reg << 16) | | |
2404 | EMAC_MDIO_COMM_COMMAND_READ_22 | EMAC_MDIO_COMM_START_BUSY); | |
2405 | REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); | |
2406 | ||
2407 | for (i = 0; i < 50; i++) { | |
2408 | DELAY(10); | |
2409 | ||
2410 | val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); | |
2411 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { | |
2412 | *ret_val = (uint16_t) (val & EMAC_MDIO_COMM_DATA); | |
2413 | DELAY(5); | |
2414 | break; | |
2415 | } | |
2416 | } | |
2417 | if (val & EMAC_MDIO_COMM_START_BUSY) { | |
2418 | PMD_DRV_LOG(DEBUG, "read phy register failed"); | |
2419 | ||
2420 | *ret_val = 0; | |
2421 | rc = ELINK_STATUS_TIMEOUT; | |
2422 | } | |
2423 | REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); | |
2424 | return rc; | |
2425 | } | |
2426 | ||
2427 | /******************************************************************/ | |
2428 | /* CL45 access functions */ | |
2429 | /******************************************************************/ | |
2430 | static elink_status_t elink_cl45_read(struct bnx2x_softc *sc, | |
2431 | struct elink_phy *phy, uint8_t devad, | |
2432 | uint16_t reg, uint16_t * ret_val) | |
2433 | { | |
2434 | uint32_t val; | |
2435 | uint16_t i; | |
2436 | elink_status_t rc = ELINK_STATUS_OK; | |
2437 | if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) { | |
2438 | elink_set_mdio_clk(sc, phy->mdio_ctrl); | |
2439 | } | |
2440 | ||
2441 | if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) | |
2442 | elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
2443 | EMAC_MDIO_STATUS_10MB); | |
2444 | /* Address */ | |
2445 | val = ((phy->addr << 21) | (devad << 16) | reg | | |
2446 | EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY); | |
2447 | REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); | |
2448 | ||
2449 | for (i = 0; i < 50; i++) { | |
2450 | DELAY(10); | |
2451 | ||
2452 | val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); | |
2453 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { | |
2454 | DELAY(5); | |
2455 | break; | |
2456 | } | |
2457 | } | |
2458 | if (val & EMAC_MDIO_COMM_START_BUSY) { | |
2459 | PMD_DRV_LOG(DEBUG, "read phy register failed"); | |
2460 | elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout" | |
2461 | ||
2462 | *ret_val = 0; | |
2463 | rc = ELINK_STATUS_TIMEOUT; | |
2464 | } else { | |
2465 | /* Data */ | |
2466 | val = ((phy->addr << 21) | (devad << 16) | | |
2467 | EMAC_MDIO_COMM_COMMAND_READ_45 | | |
2468 | EMAC_MDIO_COMM_START_BUSY); | |
2469 | REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); | |
2470 | ||
2471 | for (i = 0; i < 50; i++) { | |
2472 | DELAY(10); | |
2473 | ||
2474 | val = REG_RD(sc, phy->mdio_ctrl + | |
2475 | EMAC_REG_EMAC_MDIO_COMM); | |
2476 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { | |
2477 | *ret_val = | |
2478 | (uint16_t) (val & EMAC_MDIO_COMM_DATA); | |
2479 | break; | |
2480 | } | |
2481 | } | |
2482 | if (val & EMAC_MDIO_COMM_START_BUSY) { | |
2483 | PMD_DRV_LOG(DEBUG, "read phy register failed"); | |
2484 | elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout" | |
2485 | ||
2486 | *ret_val = 0; | |
2487 | rc = ELINK_STATUS_TIMEOUT; | |
2488 | } | |
2489 | } | |
2490 | /* Work around for E3 A0 */ | |
2491 | if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) { | |
2492 | phy->flags ^= ELINK_FLAGS_DUMMY_READ; | |
2493 | if (phy->flags & ELINK_FLAGS_DUMMY_READ) { | |
2494 | uint16_t temp_val; | |
2495 | elink_cl45_read(sc, phy, devad, 0xf, &temp_val); | |
2496 | } | |
2497 | } | |
2498 | ||
2499 | if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) | |
2500 | elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
2501 | EMAC_MDIO_STATUS_10MB); | |
2502 | return rc; | |
2503 | } | |
2504 | ||
2505 | static elink_status_t elink_cl45_write(struct bnx2x_softc *sc, | |
2506 | struct elink_phy *phy, uint8_t devad, | |
2507 | uint16_t reg, uint16_t val) | |
2508 | { | |
2509 | uint32_t tmp; | |
2510 | uint8_t i; | |
2511 | elink_status_t rc = ELINK_STATUS_OK; | |
2512 | if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) { | |
2513 | elink_set_mdio_clk(sc, phy->mdio_ctrl); | |
2514 | } | |
2515 | ||
2516 | if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) | |
2517 | elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
2518 | EMAC_MDIO_STATUS_10MB); | |
2519 | ||
2520 | /* Address */ | |
2521 | tmp = ((phy->addr << 21) | (devad << 16) | reg | | |
2522 | EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY); | |
2523 | REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); | |
2524 | ||
2525 | for (i = 0; i < 50; i++) { | |
2526 | DELAY(10); | |
2527 | ||
2528 | tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); | |
2529 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { | |
2530 | DELAY(5); | |
2531 | break; | |
2532 | } | |
2533 | } | |
2534 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { | |
2535 | PMD_DRV_LOG(DEBUG, "write phy register failed"); | |
2536 | elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout" | |
2537 | ||
2538 | rc = ELINK_STATUS_TIMEOUT; | |
2539 | } else { | |
2540 | /* Data */ | |
2541 | tmp = ((phy->addr << 21) | (devad << 16) | val | | |
2542 | EMAC_MDIO_COMM_COMMAND_WRITE_45 | | |
2543 | EMAC_MDIO_COMM_START_BUSY); | |
2544 | REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); | |
2545 | ||
2546 | for (i = 0; i < 50; i++) { | |
2547 | DELAY(10); | |
2548 | ||
2549 | tmp = REG_RD(sc, phy->mdio_ctrl + | |
2550 | EMAC_REG_EMAC_MDIO_COMM); | |
2551 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { | |
2552 | DELAY(5); | |
2553 | break; | |
2554 | } | |
2555 | } | |
2556 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { | |
2557 | PMD_DRV_LOG(DEBUG, "write phy register failed"); | |
2558 | elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout" | |
2559 | ||
2560 | rc = ELINK_STATUS_TIMEOUT; | |
2561 | } | |
2562 | } | |
2563 | /* Work around for E3 A0 */ | |
2564 | if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) { | |
2565 | phy->flags ^= ELINK_FLAGS_DUMMY_READ; | |
2566 | if (phy->flags & ELINK_FLAGS_DUMMY_READ) { | |
2567 | uint16_t temp_val; | |
2568 | elink_cl45_read(sc, phy, devad, 0xf, &temp_val); | |
2569 | } | |
2570 | } | |
2571 | if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) | |
2572 | elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
2573 | EMAC_MDIO_STATUS_10MB); | |
2574 | return rc; | |
2575 | } | |
2576 | ||
2577 | /******************************************************************/ | |
2578 | /* EEE section */ | |
2579 | /******************************************************************/ | |
2580 | static uint8_t elink_eee_has_cap(struct elink_params *params) | |
2581 | { | |
2582 | struct bnx2x_softc *sc = params->sc; | |
2583 | ||
2584 | if (REG_RD(sc, params->shmem2_base) <= | |
2585 | offsetof(struct shmem2_region, eee_status[params->port])) | |
2586 | return 0; | |
2587 | ||
2588 | return 1; | |
2589 | } | |
2590 | ||
2591 | static elink_status_t elink_eee_nvram_to_time(uint32_t nvram_mode, | |
2592 | uint32_t * idle_timer) | |
2593 | { | |
2594 | switch (nvram_mode) { | |
2595 | case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED: | |
2596 | *idle_timer = ELINK_EEE_MODE_NVRAM_BALANCED_TIME; | |
2597 | break; | |
2598 | case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE: | |
2599 | *idle_timer = ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME; | |
2600 | break; | |
2601 | case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY: | |
2602 | *idle_timer = ELINK_EEE_MODE_NVRAM_LATENCY_TIME; | |
2603 | break; | |
2604 | default: | |
2605 | *idle_timer = 0; | |
2606 | break; | |
2607 | } | |
2608 | ||
2609 | return ELINK_STATUS_OK; | |
2610 | } | |
2611 | ||
2612 | static elink_status_t elink_eee_time_to_nvram(uint32_t idle_timer, | |
2613 | uint32_t * nvram_mode) | |
2614 | { | |
2615 | switch (idle_timer) { | |
2616 | case ELINK_EEE_MODE_NVRAM_BALANCED_TIME: | |
2617 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED; | |
2618 | break; | |
2619 | case ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME: | |
2620 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE; | |
2621 | break; | |
2622 | case ELINK_EEE_MODE_NVRAM_LATENCY_TIME: | |
2623 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY; | |
2624 | break; | |
2625 | default: | |
2626 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED; | |
2627 | break; | |
2628 | } | |
2629 | ||
2630 | return ELINK_STATUS_OK; | |
2631 | } | |
2632 | ||
2633 | static uint32_t elink_eee_calc_timer(struct elink_params *params) | |
2634 | { | |
2635 | uint32_t eee_mode, eee_idle; | |
2636 | struct bnx2x_softc *sc = params->sc; | |
2637 | ||
2638 | if (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) { | |
2639 | if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) { | |
2640 | /* time value in eee_mode --> used directly */ | |
2641 | eee_idle = params->eee_mode & ELINK_EEE_MODE_TIMER_MASK; | |
2642 | } else { | |
2643 | /* hsi value in eee_mode --> time */ | |
2644 | if (elink_eee_nvram_to_time(params->eee_mode & | |
2645 | ELINK_EEE_MODE_NVRAM_MASK, | |
2646 | &eee_idle)) | |
2647 | return 0; | |
2648 | } | |
2649 | } else { | |
2650 | /* hsi values in nvram --> time */ | |
2651 | eee_mode = ((REG_RD(sc, params->shmem_base + | |
2652 | offsetof(struct shmem_region, | |
2653 | dev_info.port_feature_config | |
2654 | [params-> | |
2655 | port].eee_power_mode)) & | |
2656 | PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> | |
2657 | PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); | |
2658 | ||
2659 | if (elink_eee_nvram_to_time(eee_mode, &eee_idle)) | |
2660 | return 0; | |
2661 | } | |
2662 | ||
2663 | return eee_idle; | |
2664 | } | |
2665 | ||
2666 | static elink_status_t elink_eee_set_timers(struct elink_params *params, | |
2667 | struct elink_vars *vars) | |
2668 | { | |
2669 | uint32_t eee_idle = 0, eee_mode; | |
2670 | struct bnx2x_softc *sc = params->sc; | |
2671 | ||
2672 | eee_idle = elink_eee_calc_timer(params); | |
2673 | ||
2674 | if (eee_idle) { | |
2675 | REG_WR(sc, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), | |
2676 | eee_idle); | |
2677 | } else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) && | |
2678 | (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) && | |
2679 | (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) { | |
2680 | PMD_DRV_LOG(DEBUG, "Error: Tx LPI is enabled with timer 0"); | |
2681 | return ELINK_STATUS_ERROR; | |
2682 | } | |
2683 | ||
2684 | vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT); | |
2685 | if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) { | |
2686 | /* eee_idle in 1u --> eee_status in 16u */ | |
2687 | eee_idle >>= 4; | |
2688 | vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) | | |
2689 | SHMEM_EEE_TIME_OUTPUT_BIT; | |
2690 | } else { | |
2691 | if (elink_eee_time_to_nvram(eee_idle, &eee_mode)) | |
2692 | return ELINK_STATUS_ERROR; | |
2693 | vars->eee_status |= eee_mode; | |
2694 | } | |
2695 | ||
2696 | return ELINK_STATUS_OK; | |
2697 | } | |
2698 | ||
2699 | static elink_status_t elink_eee_initial_config(struct elink_params *params, | |
2700 | struct elink_vars *vars, | |
2701 | uint8_t mode) | |
2702 | { | |
2703 | vars->eee_status |= ((uint32_t) mode) << SHMEM_EEE_SUPPORTED_SHIFT; | |
2704 | ||
2705 | /* Propogate params' bits --> vars (for migration exposure) */ | |
2706 | if (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) | |
2707 | vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT; | |
2708 | else | |
2709 | vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT; | |
2710 | ||
2711 | if (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) | |
2712 | vars->eee_status |= SHMEM_EEE_REQUESTED_BIT; | |
2713 | else | |
2714 | vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT; | |
2715 | ||
2716 | return elink_eee_set_timers(params, vars); | |
2717 | } | |
2718 | ||
2719 | static elink_status_t elink_eee_disable(struct elink_phy *phy, | |
2720 | struct elink_params *params, | |
2721 | struct elink_vars *vars) | |
2722 | { | |
2723 | struct bnx2x_softc *sc = params->sc; | |
2724 | ||
2725 | /* Make Certain LPI is disabled */ | |
2726 | REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); | |
2727 | ||
2728 | elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); | |
2729 | ||
2730 | vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; | |
2731 | ||
2732 | return ELINK_STATUS_OK; | |
2733 | } | |
2734 | ||
2735 | static elink_status_t elink_eee_advertise(struct elink_phy *phy, | |
2736 | struct elink_params *params, | |
2737 | struct elink_vars *vars, | |
2738 | uint8_t modes) | |
2739 | { | |
2740 | struct bnx2x_softc *sc = params->sc; | |
2741 | uint16_t val = 0; | |
2742 | ||
2743 | /* Mask events preventing LPI generation */ | |
2744 | REG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); | |
2745 | ||
2746 | if (modes & SHMEM_EEE_10G_ADV) { | |
2747 | PMD_DRV_LOG(DEBUG, "Advertise 10GBase-T EEE"); | |
2748 | val |= 0x8; | |
2749 | } | |
2750 | if (modes & SHMEM_EEE_1G_ADV) { | |
2751 | PMD_DRV_LOG(DEBUG, "Advertise 1GBase-T EEE"); | |
2752 | val |= 0x4; | |
2753 | } | |
2754 | ||
2755 | elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); | |
2756 | ||
2757 | vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; | |
2758 | vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT); | |
2759 | ||
2760 | return ELINK_STATUS_OK; | |
2761 | } | |
2762 | ||
2763 | static void elink_update_mng_eee(struct elink_params *params, | |
2764 | uint32_t eee_status) | |
2765 | { | |
2766 | struct bnx2x_softc *sc = params->sc; | |
2767 | ||
2768 | if (elink_eee_has_cap(params)) | |
2769 | REG_WR(sc, params->shmem2_base + | |
2770 | offsetof(struct shmem2_region, | |
2771 | eee_status[params->port]), eee_status); | |
2772 | } | |
2773 | ||
2774 | static void elink_eee_an_resolve(struct elink_phy *phy, | |
2775 | struct elink_params *params, | |
2776 | struct elink_vars *vars) | |
2777 | { | |
2778 | struct bnx2x_softc *sc = params->sc; | |
2779 | uint16_t adv = 0, lp = 0; | |
2780 | uint32_t lp_adv = 0; | |
2781 | uint8_t neg = 0; | |
2782 | ||
2783 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); | |
2784 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); | |
2785 | ||
2786 | if (lp & 0x2) { | |
2787 | lp_adv |= SHMEM_EEE_100M_ADV; | |
2788 | if (adv & 0x2) { | |
2789 | if (vars->line_speed == ELINK_SPEED_100) | |
2790 | neg = 1; | |
2791 | PMD_DRV_LOG(DEBUG, "EEE negotiated - 100M"); | |
2792 | } | |
2793 | } | |
2794 | if (lp & 0x14) { | |
2795 | lp_adv |= SHMEM_EEE_1G_ADV; | |
2796 | if (adv & 0x14) { | |
2797 | if (vars->line_speed == ELINK_SPEED_1000) | |
2798 | neg = 1; | |
2799 | PMD_DRV_LOG(DEBUG, "EEE negotiated - 1G"); | |
2800 | } | |
2801 | } | |
2802 | if (lp & 0x68) { | |
2803 | lp_adv |= SHMEM_EEE_10G_ADV; | |
2804 | if (adv & 0x68) { | |
2805 | if (vars->line_speed == ELINK_SPEED_10000) | |
2806 | neg = 1; | |
2807 | PMD_DRV_LOG(DEBUG, "EEE negotiated - 10G"); | |
2808 | } | |
2809 | } | |
2810 | ||
2811 | vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK; | |
2812 | vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT); | |
2813 | ||
2814 | if (neg) { | |
2815 | PMD_DRV_LOG(DEBUG, "EEE is active"); | |
2816 | vars->eee_status |= SHMEM_EEE_ACTIVE_BIT; | |
2817 | } | |
2818 | } | |
2819 | ||
2820 | /******************************************************************/ | |
2821 | /* BSC access functions from E3 */ | |
2822 | /******************************************************************/ | |
2823 | static void elink_bsc_module_sel(struct elink_params *params) | |
2824 | { | |
2825 | int idx; | |
2826 | uint32_t board_cfg, sfp_ctrl; | |
2827 | uint32_t i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH]; | |
2828 | struct bnx2x_softc *sc = params->sc; | |
2829 | uint8_t port = params->port; | |
2830 | /* Read I2C output PINs */ | |
2831 | board_cfg = REG_RD(sc, params->shmem_base + | |
2832 | offsetof(struct shmem_region, | |
2833 | dev_info.shared_hw_config.board)); | |
2834 | i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK; | |
2835 | i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >> | |
2836 | SHARED_HW_CFG_E3_I2C_MUX1_SHIFT; | |
2837 | ||
2838 | /* Read I2C output value */ | |
2839 | sfp_ctrl = REG_RD(sc, params->shmem_base + | |
2840 | offsetof(struct shmem_region, | |
2841 | dev_info.port_hw_config[port]. | |
2842 | e3_cmn_pin_cfg)); | |
2843 | i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0; | |
2844 | i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0; | |
2845 | PMD_DRV_LOG(DEBUG, "Setting BSC switch"); | |
2846 | for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++) | |
2847 | elink_set_cfg_pin(sc, i2c_pins[idx], i2c_val[idx]); | |
2848 | } | |
2849 | ||
2850 | static elink_status_t elink_bsc_read(struct elink_params *params, | |
2851 | struct bnx2x_softc *sc, | |
2852 | uint8_t sl_devid, | |
2853 | uint16_t sl_addr, | |
2854 | uint8_t lc_addr, | |
2855 | uint8_t xfer_cnt, uint32_t * data_array) | |
2856 | { | |
2857 | uint32_t val, i; | |
2858 | elink_status_t rc = ELINK_STATUS_OK; | |
2859 | ||
2860 | if (xfer_cnt > 16) { | |
2861 | PMD_DRV_LOG(DEBUG, "invalid xfer_cnt %d. Max is 16 bytes", | |
2862 | xfer_cnt); | |
2863 | return ELINK_STATUS_ERROR; | |
2864 | } | |
2865 | if (params) | |
2866 | elink_bsc_module_sel(params); | |
2867 | ||
2868 | xfer_cnt = 16 - lc_addr; | |
2869 | ||
2870 | /* Enable the engine */ | |
2871 | val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND); | |
2872 | val |= MCPR_IMC_COMMAND_ENABLE; | |
2873 | REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val); | |
2874 | ||
2875 | /* Program slave device ID */ | |
2876 | val = (sl_devid << 16) | sl_addr; | |
2877 | REG_WR(sc, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); | |
2878 | ||
2879 | /* Start xfer with 0 byte to update the address pointer ??? */ | |
2880 | val = (MCPR_IMC_COMMAND_ENABLE) | | |
2881 | (MCPR_IMC_COMMAND_WRITE_OP << | |
2882 | MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | | |
2883 | (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); | |
2884 | REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val); | |
2885 | ||
2886 | /* Poll for completion */ | |
2887 | i = 0; | |
2888 | val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND); | |
2889 | while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { | |
2890 | DELAY(10); | |
2891 | val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND); | |
2892 | if (i++ > 1000) { | |
2893 | PMD_DRV_LOG(DEBUG, "wr 0 byte timed out after %d try", | |
2894 | i); | |
2895 | rc = ELINK_STATUS_TIMEOUT; | |
2896 | break; | |
2897 | } | |
2898 | } | |
2899 | if (rc == ELINK_STATUS_TIMEOUT) | |
2900 | return rc; | |
2901 | ||
2902 | /* Start xfer with read op */ | |
2903 | val = (MCPR_IMC_COMMAND_ENABLE) | | |
2904 | (MCPR_IMC_COMMAND_READ_OP << | |
2905 | MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | | |
2906 | (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | | |
2907 | (xfer_cnt); | |
2908 | REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val); | |
2909 | ||
2910 | /* Poll for completion */ | |
2911 | i = 0; | |
2912 | val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND); | |
2913 | while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { | |
2914 | DELAY(10); | |
2915 | val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND); | |
2916 | if (i++ > 1000) { | |
2917 | PMD_DRV_LOG(DEBUG, "rd op timed out after %d try", i); | |
2918 | rc = ELINK_STATUS_TIMEOUT; | |
2919 | break; | |
2920 | } | |
2921 | } | |
2922 | if (rc == ELINK_STATUS_TIMEOUT) | |
2923 | return rc; | |
2924 | ||
2925 | for (i = (lc_addr >> 2); i < 4; i++) { | |
2926 | data_array[i] = REG_RD(sc, (MCP_REG_MCPR_IMC_DATAREG0 + i * 4)); | |
2927 | #ifdef __BIG_ENDIAN | |
2928 | data_array[i] = ((data_array[i] & 0x000000ff) << 24) | | |
2929 | ((data_array[i] & 0x0000ff00) << 8) | | |
2930 | ((data_array[i] & 0x00ff0000) >> 8) | | |
2931 | ((data_array[i] & 0xff000000) >> 24); | |
2932 | #endif | |
2933 | } | |
2934 | return rc; | |
2935 | } | |
2936 | ||
2937 | static void elink_cl45_read_or_write(struct bnx2x_softc *sc, | |
2938 | struct elink_phy *phy, uint8_t devad, | |
2939 | uint16_t reg, uint16_t or_val) | |
2940 | { | |
2941 | uint16_t val; | |
2942 | elink_cl45_read(sc, phy, devad, reg, &val); | |
2943 | elink_cl45_write(sc, phy, devad, reg, val | or_val); | |
2944 | } | |
2945 | ||
2946 | static void elink_cl45_read_and_write(struct bnx2x_softc *sc, | |
2947 | struct elink_phy *phy, | |
2948 | uint8_t devad, uint16_t reg, | |
2949 | uint16_t and_val) | |
2950 | { | |
2951 | uint16_t val; | |
2952 | elink_cl45_read(sc, phy, devad, reg, &val); | |
2953 | elink_cl45_write(sc, phy, devad, reg, val & and_val); | |
2954 | } | |
2955 | ||
2956 | static uint8_t elink_get_warpcore_lane(struct elink_params *params) | |
2957 | { | |
2958 | uint8_t lane = 0; | |
2959 | struct bnx2x_softc *sc = params->sc; | |
2960 | uint32_t path_swap, path_swap_ovr; | |
2961 | uint8_t path, port; | |
2962 | ||
2963 | path = SC_PATH(sc); | |
2964 | port = params->port; | |
2965 | ||
2966 | if (elink_is_4_port_mode(sc)) { | |
2967 | uint32_t port_swap, port_swap_ovr; | |
2968 | ||
2969 | /* Figure out path swap value */ | |
2970 | path_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); | |
2971 | if (path_swap_ovr & 0x1) | |
2972 | path_swap = (path_swap_ovr & 0x2); | |
2973 | else | |
2974 | path_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP); | |
2975 | ||
2976 | if (path_swap) | |
2977 | path = path ^ 1; | |
2978 | ||
2979 | /* Figure out port swap value */ | |
2980 | port_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); | |
2981 | if (port_swap_ovr & 0x1) | |
2982 | port_swap = (port_swap_ovr & 0x2); | |
2983 | else | |
2984 | port_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP); | |
2985 | ||
2986 | if (port_swap) | |
2987 | port = port ^ 1; | |
2988 | ||
2989 | lane = (port << 1) + path; | |
2990 | } else { /* Two port mode - no port swap */ | |
2991 | ||
2992 | /* Figure out path swap value */ | |
2993 | path_swap_ovr = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); | |
2994 | if (path_swap_ovr & 0x1) { | |
2995 | path_swap = (path_swap_ovr & 0x2); | |
2996 | } else { | |
2997 | path_swap = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP); | |
2998 | } | |
2999 | if (path_swap) | |
3000 | path = path ^ 1; | |
3001 | ||
3002 | lane = path << 1; | |
3003 | } | |
3004 | return lane; | |
3005 | } | |
3006 | ||
3007 | static void elink_set_aer_mmd(struct elink_params *params, | |
3008 | struct elink_phy *phy) | |
3009 | { | |
3010 | uint32_t ser_lane; | |
3011 | uint16_t offset, aer_val; | |
3012 | struct bnx2x_softc *sc = params->sc; | |
3013 | ser_lane = ((params->lane_config & | |
3014 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> | |
3015 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
3016 | ||
3017 | offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? | |
3018 | (phy->addr + ser_lane) : 0; | |
3019 | ||
3020 | if (USES_WARPCORE(sc)) { | |
3021 | aer_val = elink_get_warpcore_lane(params); | |
3022 | /* In Dual-lane mode, two lanes are joined together, | |
3023 | * so in order to configure them, the AER broadcast method is | |
3024 | * used here. | |
3025 | * 0x200 is the broadcast address for lanes 0,1 | |
3026 | * 0x201 is the broadcast address for lanes 2,3 | |
3027 | */ | |
3028 | if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) | |
3029 | aer_val = (aer_val >> 1) | 0x200; | |
3030 | } else if (CHIP_IS_E2(sc)) | |
3031 | aer_val = 0x3800 + offset - 1; | |
3032 | else | |
3033 | aer_val = 0x3800 + offset; | |
3034 | ||
3035 | CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, | |
3036 | MDIO_AER_BLOCK_AER_REG, aer_val); | |
3037 | ||
3038 | } | |
3039 | ||
3040 | /******************************************************************/ | |
3041 | /* Internal phy section */ | |
3042 | /******************************************************************/ | |
3043 | ||
3044 | static void elink_set_serdes_access(struct bnx2x_softc *sc, uint8_t port) | |
3045 | { | |
3046 | uint32_t emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
3047 | ||
3048 | /* Set Clause 22 */ | |
3049 | REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port * 0x10, 1); | |
3050 | REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); | |
3051 | DELAY(500); | |
3052 | REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); | |
3053 | DELAY(500); | |
3054 | /* Set Clause 45 */ | |
3055 | REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port * 0x10, 0); | |
3056 | } | |
3057 | ||
3058 | static void elink_serdes_deassert(struct bnx2x_softc *sc, uint8_t port) | |
3059 | { | |
3060 | uint32_t val; | |
3061 | ||
3062 | PMD_DRV_LOG(DEBUG, "elink_serdes_deassert"); | |
3063 | ||
3064 | val = ELINK_SERDES_RESET_BITS << (port * 16); | |
3065 | ||
3066 | /* Reset and unreset the SerDes/XGXS */ | |
3067 | REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); | |
3068 | DELAY(500); | |
3069 | REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); | |
3070 | ||
3071 | elink_set_serdes_access(sc, port); | |
3072 | ||
3073 | REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_DEVAD + port * 0x10, | |
3074 | ELINK_DEFAULT_PHY_DEV_ADDR); | |
3075 | } | |
3076 | ||
3077 | static void elink_xgxs_specific_func(struct elink_phy *phy, | |
3078 | struct elink_params *params, | |
3079 | uint32_t action) | |
3080 | { | |
3081 | struct bnx2x_softc *sc = params->sc; | |
3082 | switch (action) { | |
3083 | case ELINK_PHY_INIT: | |
3084 | /* Set correct devad */ | |
3085 | REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_ST + params->port * 0x18, 0); | |
3086 | REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port * 0x18, | |
3087 | phy->def_md_devad); | |
3088 | break; | |
3089 | } | |
3090 | } | |
3091 | ||
3092 | static void elink_xgxs_deassert(struct elink_params *params) | |
3093 | { | |
3094 | struct bnx2x_softc *sc = params->sc; | |
3095 | uint8_t port; | |
3096 | uint32_t val; | |
3097 | PMD_DRV_LOG(DEBUG, "elink_xgxs_deassert"); | |
3098 | port = params->port; | |
3099 | ||
3100 | val = ELINK_XGXS_RESET_BITS << (port * 16); | |
3101 | ||
3102 | /* Reset and unreset the SerDes/XGXS */ | |
3103 | REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); | |
3104 | DELAY(500); | |
3105 | REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); | |
3106 | elink_xgxs_specific_func(¶ms->phy[ELINK_INT_PHY], params, | |
3107 | ELINK_PHY_INIT); | |
3108 | } | |
3109 | ||
3110 | static void elink_calc_ieee_aneg_adv(struct elink_phy *phy, | |
3111 | struct elink_params *params, | |
3112 | uint16_t * ieee_fc) | |
3113 | { | |
3114 | *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; | |
3115 | /* Resolve pause mode and advertisement Please refer to Table | |
3116 | * 28B-3 of the 802.3ab-1999 spec | |
3117 | */ | |
3118 | ||
3119 | switch (phy->req_flow_ctrl) { | |
3120 | case ELINK_FLOW_CTRL_AUTO: | |
3121 | switch (params->req_fc_auto_adv) { | |
3122 | case ELINK_FLOW_CTRL_BOTH: | |
3123 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
3124 | break; | |
3125 | case ELINK_FLOW_CTRL_RX: | |
3126 | case ELINK_FLOW_CTRL_TX: | |
3127 | *ieee_fc |= | |
3128 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | |
3129 | break; | |
3130 | default: | |
3131 | break; | |
3132 | } | |
3133 | break; | |
3134 | case ELINK_FLOW_CTRL_TX: | |
3135 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | |
3136 | break; | |
3137 | ||
3138 | case ELINK_FLOW_CTRL_RX: | |
3139 | case ELINK_FLOW_CTRL_BOTH: | |
3140 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
3141 | break; | |
3142 | ||
3143 | case ELINK_FLOW_CTRL_NONE: | |
3144 | default: | |
3145 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; | |
3146 | break; | |
3147 | } | |
3148 | PMD_DRV_LOG(DEBUG, "ieee_fc = 0x%x", *ieee_fc); | |
3149 | } | |
3150 | ||
3151 | static void set_phy_vars(struct elink_params *params, struct elink_vars *vars) | |
3152 | { | |
3153 | uint8_t actual_phy_idx, phy_index, link_cfg_idx; | |
3154 | uint8_t phy_config_swapped = params->multi_phy_config & | |
3155 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
3156 | for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; | |
3157 | phy_index++) { | |
3158 | link_cfg_idx = ELINK_LINK_CONFIG_IDX(phy_index); | |
3159 | actual_phy_idx = phy_index; | |
3160 | if (phy_config_swapped) { | |
3161 | if (phy_index == ELINK_EXT_PHY1) | |
3162 | actual_phy_idx = ELINK_EXT_PHY2; | |
3163 | else if (phy_index == ELINK_EXT_PHY2) | |
3164 | actual_phy_idx = ELINK_EXT_PHY1; | |
3165 | } | |
3166 | params->phy[actual_phy_idx].req_flow_ctrl = | |
3167 | params->req_flow_ctrl[link_cfg_idx]; | |
3168 | ||
3169 | params->phy[actual_phy_idx].req_line_speed = | |
3170 | params->req_line_speed[link_cfg_idx]; | |
3171 | ||
3172 | params->phy[actual_phy_idx].speed_cap_mask = | |
3173 | params->speed_cap_mask[link_cfg_idx]; | |
3174 | ||
3175 | params->phy[actual_phy_idx].req_duplex = | |
3176 | params->req_duplex[link_cfg_idx]; | |
3177 | ||
3178 | if (params->req_line_speed[link_cfg_idx] == | |
3179 | ELINK_SPEED_AUTO_NEG) | |
3180 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; | |
3181 | ||
3182 | PMD_DRV_LOG(DEBUG, "req_flow_ctrl %x, req_line_speed %x," | |
3183 | " speed_cap_mask %x", | |
3184 | params->phy[actual_phy_idx].req_flow_ctrl, | |
3185 | params->phy[actual_phy_idx].req_line_speed, | |
3186 | params->phy[actual_phy_idx].speed_cap_mask); | |
3187 | } | |
3188 | } | |
3189 | ||
3190 | static void elink_ext_phy_set_pause(struct elink_params *params, | |
3191 | struct elink_phy *phy, | |
3192 | struct elink_vars *vars) | |
3193 | { | |
3194 | uint16_t val; | |
3195 | struct bnx2x_softc *sc = params->sc; | |
3196 | /* Read modify write pause advertizing */ | |
3197 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); | |
3198 | ||
3199 | val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; | |
3200 | ||
3201 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ | |
3202 | elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); | |
3203 | if ((vars->ieee_fc & | |
3204 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == | |
3205 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { | |
3206 | val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; | |
3207 | } | |
3208 | if ((vars->ieee_fc & | |
3209 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == | |
3210 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { | |
3211 | val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; | |
3212 | } | |
3213 | PMD_DRV_LOG(DEBUG, "Ext phy AN advertize 0x%x", val); | |
3214 | elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); | |
3215 | } | |
3216 | ||
3217 | static void elink_pause_resolve(struct elink_vars *vars, uint32_t pause_result) | |
3218 | { /* LD LP */ | |
3219 | switch (pause_result) { /* ASYM P ASYM P */ | |
3220 | case 0xb: /* 1 0 1 1 */ | |
3221 | vars->flow_ctrl = ELINK_FLOW_CTRL_TX; | |
3222 | break; | |
3223 | ||
3224 | case 0xe: /* 1 1 1 0 */ | |
3225 | vars->flow_ctrl = ELINK_FLOW_CTRL_RX; | |
3226 | break; | |
3227 | ||
3228 | case 0x5: /* 0 1 0 1 */ | |
3229 | case 0x7: /* 0 1 1 1 */ | |
3230 | case 0xd: /* 1 1 0 1 */ | |
3231 | case 0xf: /* 1 1 1 1 */ | |
3232 | vars->flow_ctrl = ELINK_FLOW_CTRL_BOTH; | |
3233 | break; | |
3234 | ||
3235 | default: | |
3236 | break; | |
3237 | } | |
3238 | if (pause_result & (1 << 0)) | |
3239 | vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; | |
3240 | if (pause_result & (1 << 1)) | |
3241 | vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; | |
3242 | ||
3243 | } | |
3244 | ||
3245 | static void elink_ext_phy_update_adv_fc(struct elink_phy *phy, | |
3246 | struct elink_params *params, | |
3247 | struct elink_vars *vars) | |
3248 | { | |
3249 | uint16_t ld_pause; /* local */ | |
3250 | uint16_t lp_pause; /* link partner */ | |
3251 | uint16_t pause_result; | |
3252 | struct bnx2x_softc *sc = params->sc; | |
3253 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) { | |
3254 | elink_cl22_read(sc, phy, 0x4, &ld_pause); | |
3255 | elink_cl22_read(sc, phy, 0x5, &lp_pause); | |
3256 | } else if (CHIP_IS_E3(sc) && ELINK_SINGLE_MEDIA_DIRECT(params)) { | |
3257 | uint8_t lane = elink_get_warpcore_lane(params); | |
3258 | uint16_t gp_status, gp_mask; | |
3259 | elink_cl45_read(sc, phy, | |
3260 | MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4, | |
3261 | &gp_status); | |
3262 | gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL | | |
3263 | MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) << | |
3264 | lane; | |
3265 | if ((gp_status & gp_mask) == gp_mask) { | |
3266 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, | |
3267 | MDIO_AN_REG_ADV_PAUSE, &ld_pause); | |
3268 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, | |
3269 | MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); | |
3270 | } else { | |
3271 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, | |
3272 | MDIO_AN_REG_CL37_FC_LD, &ld_pause); | |
3273 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, | |
3274 | MDIO_AN_REG_CL37_FC_LP, &lp_pause); | |
3275 | ld_pause = ((ld_pause & | |
3276 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) | |
3277 | << 3); | |
3278 | lp_pause = ((lp_pause & | |
3279 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) | |
3280 | << 3); | |
3281 | } | |
3282 | } else { | |
3283 | elink_cl45_read(sc, phy, | |
3284 | MDIO_AN_DEVAD, | |
3285 | MDIO_AN_REG_ADV_PAUSE, &ld_pause); | |
3286 | elink_cl45_read(sc, phy, | |
3287 | MDIO_AN_DEVAD, | |
3288 | MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); | |
3289 | } | |
3290 | pause_result = (ld_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; | |
3291 | pause_result |= (lp_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; | |
3292 | PMD_DRV_LOG(DEBUG, "Ext PHY pause result 0x%x", pause_result); | |
3293 | elink_pause_resolve(vars, pause_result); | |
3294 | ||
3295 | } | |
3296 | ||
3297 | static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy, | |
3298 | struct elink_params *params, | |
3299 | struct elink_vars *vars) | |
3300 | { | |
3301 | uint8_t ret = 0; | |
3302 | vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; | |
3303 | if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) { | |
3304 | /* Update the advertised flow-controled of LD/LP in AN */ | |
3305 | if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) | |
3306 | elink_ext_phy_update_adv_fc(phy, params, vars); | |
3307 | /* But set the flow-control result as the requested one */ | |
3308 | vars->flow_ctrl = phy->req_flow_ctrl; | |
3309 | } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) | |
3310 | vars->flow_ctrl = params->req_fc_auto_adv; | |
3311 | else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { | |
3312 | ret = 1; | |
3313 | elink_ext_phy_update_adv_fc(phy, params, vars); | |
3314 | } | |
3315 | return ret; | |
3316 | } | |
3317 | ||
3318 | /******************************************************************/ | |
3319 | /* Warpcore section */ | |
3320 | /******************************************************************/ | |
3321 | /* The init_internal_warpcore should mirror the xgxs, | |
3322 | * i.e. reset the lane (if needed), set aer for the | |
3323 | * init configuration, and set/clear SGMII flag. Internal | |
3324 | * phy init is done purely in phy_init stage. | |
3325 | */ | |
3326 | #define WC_TX_DRIVER(post2, idriver, ipre) \ | |
3327 | ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \ | |
3328 | (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \ | |
3329 | (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)) | |
3330 | ||
3331 | #define WC_TX_FIR(post, main, pre) \ | |
3332 | ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \ | |
3333 | (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \ | |
3334 | (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)) | |
3335 | ||
3336 | static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy, | |
3337 | struct elink_params *params, | |
3338 | struct elink_vars *vars) | |
3339 | { | |
3340 | struct bnx2x_softc *sc = params->sc; | |
3341 | uint16_t i; | |
3342 | static struct elink_reg_set reg_set[] = { | |
3343 | /* Step 1 - Program the TX/RX alignment markers */ | |
3344 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157}, | |
3345 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2}, | |
3346 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537}, | |
3347 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157}, | |
3348 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2}, | |
3349 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537}, | |
3350 | /* Step 2 - Configure the NP registers */ | |
3351 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a}, | |
3352 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400}, | |
3353 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620}, | |
3354 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157}, | |
3355 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464}, | |
3356 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150}, | |
3357 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150}, | |
3358 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157}, | |
3359 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620} | |
3360 | }; | |
3361 | PMD_DRV_LOG(DEBUG, "Enabling 20G-KR2"); | |
3362 | ||
3363 | elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, | |
3364 | MDIO_WC_REG_CL49_USERB0_CTRL, (3 << 6)); | |
3365 | ||
3366 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) | |
3367 | elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg, | |
3368 | reg_set[i].val); | |
3369 | ||
3370 | /* Start KR2 work-around timer which handles BNX2X8073 link-parner */ | |
3371 | vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE; | |
3372 | elink_update_link_attr(params, vars->link_attr_sync); | |
3373 | } | |
3374 | ||
3375 | static void elink_disable_kr2(struct elink_params *params, | |
3376 | struct elink_vars *vars, struct elink_phy *phy) | |
3377 | { | |
3378 | struct bnx2x_softc *sc = params->sc; | |
3379 | uint32_t i; | |
3380 | static struct elink_reg_set reg_set[] = { | |
3381 | /* Step 1 - Program the TX/RX alignment markers */ | |
3382 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690}, | |
3383 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647}, | |
3384 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0}, | |
3385 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690}, | |
3386 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647}, | |
3387 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0}, | |
3388 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c}, | |
3389 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000}, | |
3390 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000}, | |
3391 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002}, | |
3392 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000}, | |
3393 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7}, | |
3394 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7}, | |
3395 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002}, | |
3396 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000} | |
3397 | }; | |
3398 | PMD_DRV_LOG(DEBUG, "Disabling 20G-KR2"); | |
3399 | ||
3400 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) | |
3401 | elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg, | |
3402 | reg_set[i].val); | |
3403 | vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE; | |
3404 | elink_update_link_attr(params, vars->link_attr_sync); | |
3405 | ||
3406 | vars->check_kr2_recovery_cnt = ELINK_CHECK_KR2_RECOVERY_CNT; | |
3407 | } | |
3408 | ||
3409 | static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy, | |
3410 | struct elink_params *params) | |
3411 | { | |
3412 | struct bnx2x_softc *sc = params->sc; | |
3413 | ||
3414 | PMD_DRV_LOG(DEBUG, "Configure WC for LPI pass through"); | |
3415 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3416 | MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c); | |
3417 | elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, | |
3418 | MDIO_WC_REG_DIGITAL4_MISC5, 0xc000); | |
3419 | } | |
3420 | ||
3421 | static void elink_warpcore_restart_AN_KR(struct elink_phy *phy, | |
3422 | struct elink_params *params) | |
3423 | { | |
3424 | /* Restart autoneg on the leading lane only */ | |
3425 | struct bnx2x_softc *sc = params->sc; | |
3426 | uint16_t lane = elink_get_warpcore_lane(params); | |
3427 | CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, | |
3428 | MDIO_AER_BLOCK_AER_REG, lane); | |
3429 | elink_cl45_write(sc, phy, MDIO_AN_DEVAD, | |
3430 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); | |
3431 | ||
3432 | /* Restore AER */ | |
3433 | elink_set_aer_mmd(params, phy); | |
3434 | } | |
3435 | ||
3436 | static void elink_warpcore_enable_AN_KR(struct elink_phy *phy, | |
3437 | struct elink_params *params, | |
3438 | struct elink_vars *vars) | |
3439 | { | |
3440 | uint16_t lane, i, cl72_ctrl, an_adv = 0; | |
3441 | struct bnx2x_softc *sc = params->sc; | |
3442 | static struct elink_reg_set reg_set[] = { | |
3443 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, | |
3444 | {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0}, | |
3445 | {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, | |
3446 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, | |
3447 | /* Disable Autoneg: re-enable it after adv is done. */ | |
3448 | {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0}, | |
3449 | {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}, | |
3450 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0}, | |
3451 | }; | |
3452 | PMD_DRV_LOG(DEBUG, "Enable Auto Negotiation for KR"); | |
3453 | /* Set to default registers that may be overriden by 10G force */ | |
3454 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) | |
3455 | elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg, | |
3456 | reg_set[i].val); | |
3457 | ||
3458 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
3459 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl); | |
3460 | cl72_ctrl &= 0x08ff; | |
3461 | cl72_ctrl |= 0x3800; | |
3462 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3463 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl); | |
3464 | ||
3465 | /* Check adding advertisement for 1G KX */ | |
3466 | if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) && | |
3467 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || | |
3468 | (vars->line_speed == ELINK_SPEED_1000)) { | |
3469 | uint16_t addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2; | |
3470 | an_adv |= (1 << 5); | |
3471 | ||
3472 | /* Enable CL37 1G Parallel Detect */ | |
3473 | elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1); | |
3474 | PMD_DRV_LOG(DEBUG, "Advertize 1G"); | |
3475 | } | |
3476 | if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) && | |
3477 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || | |
3478 | (vars->line_speed == ELINK_SPEED_10000)) { | |
3479 | /* Check adding advertisement for 10G KR */ | |
3480 | an_adv |= (1 << 7); | |
3481 | /* Enable 10G Parallel Detect */ | |
3482 | CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, | |
3483 | MDIO_AER_BLOCK_AER_REG, 0); | |
3484 | ||
3485 | elink_cl45_write(sc, phy, MDIO_AN_DEVAD, | |
3486 | MDIO_WC_REG_PAR_DET_10G_CTRL, 1); | |
3487 | elink_set_aer_mmd(params, phy); | |
3488 | PMD_DRV_LOG(DEBUG, "Advertize 10G"); | |
3489 | } | |
3490 | ||
3491 | /* Set Transmit PMD settings */ | |
3492 | lane = elink_get_warpcore_lane(params); | |
3493 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3494 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane, | |
3495 | WC_TX_DRIVER(0x02, 0x06, 0x09)); | |
3496 | /* Configure the next lane if dual mode */ | |
3497 | if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) | |
3498 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3499 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * (lane + 1), | |
3500 | WC_TX_DRIVER(0x02, 0x06, 0x09)); | |
3501 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3502 | MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 0x03f0); | |
3503 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3504 | MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 0x03f0); | |
3505 | ||
3506 | /* Advertised speeds */ | |
3507 | elink_cl45_write(sc, phy, MDIO_AN_DEVAD, | |
3508 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv); | |
3509 | ||
3510 | /* Advertised and set FEC (Forward Error Correction) */ | |
3511 | elink_cl45_write(sc, phy, MDIO_AN_DEVAD, | |
3512 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2, | |
3513 | (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY | | |
3514 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ)); | |
3515 | ||
3516 | /* Enable CL37 BAM */ | |
3517 | if (REG_RD(sc, params->shmem_base + | |
3518 | offsetof(struct shmem_region, | |
3519 | dev_info.port_hw_config[params->port]. | |
3520 | default_cfg)) & | |
3521 | PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { | |
3522 | elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, | |
3523 | MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, | |
3524 | 1); | |
3525 | PMD_DRV_LOG(DEBUG, "Enable CL37 BAM on KR"); | |
3526 | } | |
3527 | ||
3528 | /* Advertise pause */ | |
3529 | elink_ext_phy_set_pause(params, phy, vars); | |
3530 | vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; | |
3531 | elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, | |
3532 | MDIO_WC_REG_DIGITAL5_MISC7, 0x100); | |
3533 | ||
3534 | /* Over 1G - AN local device user page 1 */ | |
3535 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3536 | MDIO_WC_REG_DIGITAL3_UP1, 0x1f); | |
3537 | ||
3538 | if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && | |
3539 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || | |
3540 | (phy->req_line_speed == ELINK_SPEED_20000)) { | |
3541 | ||
3542 | CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, | |
3543 | MDIO_AER_BLOCK_AER_REG, lane); | |
3544 | ||
3545 | elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, | |
3546 | MDIO_WC_REG_RX1_PCI_CTRL + | |
3547 | (0x10 * lane), (1 << 11)); | |
3548 | ||
3549 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3550 | MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7); | |
3551 | elink_set_aer_mmd(params, phy); | |
3552 | ||
3553 | elink_warpcore_enable_AN_KR2(phy, params, vars); | |
3554 | } else { | |
3555 | elink_disable_kr2(params, vars, phy); | |
3556 | } | |
3557 | ||
3558 | /* Enable Autoneg: only on the main lane */ | |
3559 | elink_warpcore_restart_AN_KR(phy, params); | |
3560 | } | |
3561 | ||
3562 | static void elink_warpcore_set_10G_KR(struct elink_phy *phy, | |
3563 | struct elink_params *params) | |
3564 | { | |
3565 | struct bnx2x_softc *sc = params->sc; | |
3566 | uint16_t val16, i, lane; | |
3567 | static struct elink_reg_set reg_set[] = { | |
3568 | /* Disable Autoneg */ | |
3569 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, | |
3570 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, | |
3571 | 0x3f00}, | |
3572 | {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, | |
3573 | {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, | |
3574 | {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, | |
3575 | {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, | |
3576 | /* Leave cl72 training enable, needed for KR */ | |
3577 | {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2} | |
3578 | }; | |
3579 | ||
3580 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) | |
3581 | elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg, | |
3582 | reg_set[i].val); | |
3583 | ||
3584 | lane = elink_get_warpcore_lane(params); | |
3585 | /* Global registers */ | |
3586 | CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, | |
3587 | MDIO_AER_BLOCK_AER_REG, 0); | |
3588 | /* Disable CL36 PCS Tx */ | |
3589 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
3590 | MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); | |
3591 | val16 &= ~(0x0011 << lane); | |
3592 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3593 | MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); | |
3594 | ||
3595 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
3596 | MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); | |
3597 | val16 |= (0x0303 << (lane << 1)); | |
3598 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3599 | MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); | |
3600 | /* Restore AER */ | |
3601 | elink_set_aer_mmd(params, phy); | |
3602 | /* Set speed via PMA/PMD register */ | |
3603 | elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, | |
3604 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); | |
3605 | ||
3606 | elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, | |
3607 | MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB); | |
3608 | ||
3609 | /* Enable encoded forced speed */ | |
3610 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3611 | MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30); | |
3612 | ||
3613 | /* Turn TX scramble payload only the 64/66 scrambler */ | |
3614 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_TX66_CONTROL, 0x9); | |
3615 | ||
3616 | /* Turn RX scramble payload only the 64/66 scrambler */ | |
3617 | elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, | |
3618 | MDIO_WC_REG_RX66_CONTROL, 0xF9); | |
3619 | ||
3620 | /* Set and clear loopback to cause a reset to 64/66 decoder */ | |
3621 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3622 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000); | |
3623 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3624 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0); | |
3625 | ||
3626 | } | |
3627 | ||
3628 | static void elink_warpcore_set_10G_XFI(struct elink_phy *phy, | |
3629 | struct elink_params *params, | |
3630 | uint8_t is_xfi) | |
3631 | { | |
3632 | struct bnx2x_softc *sc = params->sc; | |
3633 | uint16_t misc1_val, tap_val, tx_driver_val, lane, val; | |
3634 | uint32_t cfg_tap_val, tx_drv_brdct, tx_equal; | |
3635 | ||
3636 | /* Hold rxSeqStart */ | |
3637 | elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, | |
3638 | MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000); | |
3639 | ||
3640 | /* Hold tx_fifo_reset */ | |
3641 | elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, | |
3642 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1); | |
3643 | ||
3644 | /* Disable CL73 AN */ | |
3645 | elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); | |
3646 | ||
3647 | /* Disable 100FX Enable and Auto-Detect */ | |
3648 | elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, | |
3649 | MDIO_WC_REG_FX100_CTRL1, 0xFFFA); | |
3650 | ||
3651 | /* Disable 100FX Idle detect */ | |
3652 | elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, | |
3653 | MDIO_WC_REG_FX100_CTRL3, 0x0080); | |
3654 | ||
3655 | /* Set Block address to Remote PHY & Clear forced_speed[5] */ | |
3656 | elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, | |
3657 | MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F); | |
3658 | ||
3659 | /* Turn off auto-detect & fiber mode */ | |
3660 | elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, | |
3661 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, | |
3662 | 0xFFEE); | |
3663 | ||
3664 | /* Set filter_force_link, disable_false_link and parallel_detect */ | |
3665 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
3666 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val); | |
3667 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3668 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
3669 | ((val | 0x0006) & 0xFFFE)); | |
3670 | ||
3671 | /* Set XFI / SFI */ | |
3672 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
3673 | MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val); | |
3674 | ||
3675 | misc1_val &= ~(0x1f); | |
3676 | ||
3677 | if (is_xfi) { | |
3678 | misc1_val |= 0x5; | |
3679 | tap_val = WC_TX_FIR(0x08, 0x37, 0x00); | |
3680 | tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03); | |
3681 | } else { | |
3682 | cfg_tap_val = REG_RD(sc, params->shmem_base + | |
3683 | offsetof(struct shmem_region, | |
3684 | dev_info.port_hw_config[params-> | |
3685 | port].sfi_tap_values)); | |
3686 | ||
3687 | tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK; | |
3688 | ||
3689 | tx_drv_brdct = (cfg_tap_val & | |
3690 | PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >> | |
3691 | PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT; | |
3692 | ||
3693 | misc1_val |= 0x9; | |
3694 | ||
3695 | /* TAP values are controlled by nvram, if value there isn't 0 */ | |
3696 | if (tx_equal) | |
3697 | tap_val = (uint16_t) tx_equal; | |
3698 | else | |
3699 | tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02); | |
3700 | ||
3701 | if (tx_drv_brdct) | |
3702 | tx_driver_val = | |
3703 | WC_TX_DRIVER(0x03, (uint16_t) tx_drv_brdct, 0x06); | |
3704 | else | |
3705 | tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06); | |
3706 | } | |
3707 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3708 | MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); | |
3709 | ||
3710 | /* Set Transmit PMD settings */ | |
3711 | lane = elink_get_warpcore_lane(params); | |
3712 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3713 | MDIO_WC_REG_TX_FIR_TAP, | |
3714 | tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE); | |
3715 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3716 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane, | |
3717 | tx_driver_val); | |
3718 | ||
3719 | /* Enable fiber mode, enable and invert sig_det */ | |
3720 | elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, | |
3721 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd); | |
3722 | ||
3723 | /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */ | |
3724 | elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, | |
3725 | MDIO_WC_REG_DIGITAL4_MISC3, 0x8080); | |
3726 | ||
3727 | elink_warpcore_set_lpi_passthrough(phy, params); | |
3728 | ||
3729 | /* 10G XFI Full Duplex */ | |
3730 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3731 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100); | |
3732 | ||
3733 | /* Release tx_fifo_reset */ | |
3734 | elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, | |
3735 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, | |
3736 | 0xFFFE); | |
3737 | /* Release rxSeqStart */ | |
3738 | elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, | |
3739 | MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF); | |
3740 | } | |
3741 | ||
3742 | static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy, | |
3743 | struct elink_params *params) | |
3744 | { | |
3745 | uint16_t val; | |
3746 | struct bnx2x_softc *sc = params->sc; | |
3747 | /* Set global registers, so set AER lane to 0 */ | |
3748 | CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, | |
3749 | MDIO_AER_BLOCK_AER_REG, 0); | |
3750 | ||
3751 | /* Disable sequencer */ | |
3752 | elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, | |
3753 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1 << 13)); | |
3754 | ||
3755 | elink_set_aer_mmd(params, phy); | |
3756 | ||
3757 | elink_cl45_read_and_write(sc, phy, MDIO_PMA_DEVAD, | |
3758 | MDIO_WC_REG_PMD_KR_CONTROL, ~(1 << 1)); | |
3759 | elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); | |
3760 | /* Turn off CL73 */ | |
3761 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
3762 | MDIO_WC_REG_CL73_USERB0_CTRL, &val); | |
3763 | val &= ~(1 << 5); | |
3764 | val |= (1 << 6); | |
3765 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3766 | MDIO_WC_REG_CL73_USERB0_CTRL, val); | |
3767 | ||
3768 | /* Set 20G KR2 force speed */ | |
3769 | elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, | |
3770 | MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f); | |
3771 | ||
3772 | elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, | |
3773 | MDIO_WC_REG_DIGITAL4_MISC3, (1 << 7)); | |
3774 | ||
3775 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
3776 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val); | |
3777 | val &= ~(3 << 14); | |
3778 | val |= (1 << 15); | |
3779 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3780 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val); | |
3781 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3782 | MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A); | |
3783 | ||
3784 | /* Enable sequencer (over lane 0) */ | |
3785 | CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, | |
3786 | MDIO_AER_BLOCK_AER_REG, 0); | |
3787 | ||
3788 | elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, | |
3789 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1 << 13)); | |
3790 | ||
3791 | elink_set_aer_mmd(params, phy); | |
3792 | } | |
3793 | ||
3794 | static void elink_warpcore_set_20G_DXGXS(struct bnx2x_softc *sc, | |
3795 | struct elink_phy *phy, uint16_t lane) | |
3796 | { | |
3797 | /* Rx0 anaRxControl1G */ | |
3798 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3799 | MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90); | |
3800 | ||
3801 | /* Rx2 anaRxControl1G */ | |
3802 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3803 | MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90); | |
3804 | ||
3805 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW0, 0xE070); | |
3806 | ||
3807 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW1, 0xC0D0); | |
3808 | ||
3809 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW2, 0xA0B0); | |
3810 | ||
3811 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW3, 0x8090); | |
3812 | ||
3813 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3814 | MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0); | |
3815 | ||
3816 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3817 | MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0); | |
3818 | ||
3819 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3820 | MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0); | |
3821 | ||
3822 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3823 | MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0); | |
3824 | ||
3825 | /* Serdes Digital Misc1 */ | |
3826 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3827 | MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008); | |
3828 | ||
3829 | /* Serdes Digital4 Misc3 */ | |
3830 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3831 | MDIO_WC_REG_DIGITAL4_MISC3, 0x8088); | |
3832 | ||
3833 | /* Set Transmit PMD settings */ | |
3834 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3835 | MDIO_WC_REG_TX_FIR_TAP, | |
3836 | (WC_TX_FIR(0x12, 0x2d, 0x00) | | |
3837 | MDIO_WC_REG_TX_FIR_TAP_ENABLE)); | |
3838 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3839 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane, | |
3840 | WC_TX_DRIVER(0x02, 0x02, 0x02)); | |
3841 | } | |
3842 | ||
3843 | static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy, | |
3844 | struct elink_params *params, | |
3845 | uint8_t fiber_mode, | |
3846 | uint8_t always_autoneg) | |
3847 | { | |
3848 | struct bnx2x_softc *sc = params->sc; | |
3849 | uint16_t val16, digctrl_kx1, digctrl_kx2; | |
3850 | ||
3851 | /* Clear XFI clock comp in non-10G single lane mode. */ | |
3852 | elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, | |
3853 | MDIO_WC_REG_RX66_CONTROL, ~(3 << 13)); | |
3854 | ||
3855 | elink_warpcore_set_lpi_passthrough(phy, params); | |
3856 | ||
3857 | if (always_autoneg || phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { | |
3858 | /* SGMII Autoneg */ | |
3859 | elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, | |
3860 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, | |
3861 | 0x1000); | |
3862 | PMD_DRV_LOG(DEBUG, "set SGMII AUTONEG"); | |
3863 | } else { | |
3864 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
3865 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); | |
3866 | val16 &= 0xcebf; | |
3867 | switch (phy->req_line_speed) { | |
3868 | case ELINK_SPEED_10: | |
3869 | break; | |
3870 | case ELINK_SPEED_100: | |
3871 | val16 |= 0x2000; | |
3872 | break; | |
3873 | case ELINK_SPEED_1000: | |
3874 | val16 |= 0x0040; | |
3875 | break; | |
3876 | default: | |
3877 | PMD_DRV_LOG(DEBUG, | |
3878 | "Speed not supported: 0x%x", | |
3879 | phy->req_line_speed); | |
3880 | return; | |
3881 | } | |
3882 | ||
3883 | if (phy->req_duplex == DUPLEX_FULL) | |
3884 | val16 |= 0x0100; | |
3885 | ||
3886 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3887 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16); | |
3888 | ||
3889 | PMD_DRV_LOG(DEBUG, "set SGMII force speed %d", | |
3890 | phy->req_line_speed); | |
3891 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
3892 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); | |
3893 | PMD_DRV_LOG(DEBUG, " (readback) %x", val16); | |
3894 | } | |
3895 | ||
3896 | /* SGMII Slave mode and disable signal detect */ | |
3897 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
3898 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1); | |
3899 | if (fiber_mode) | |
3900 | digctrl_kx1 = 1; | |
3901 | else | |
3902 | digctrl_kx1 &= 0xff4a; | |
3903 | ||
3904 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3905 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, digctrl_kx1); | |
3906 | ||
3907 | /* Turn off parallel detect */ | |
3908 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
3909 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2); | |
3910 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3911 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
3912 | (digctrl_kx2 & ~(1 << 2))); | |
3913 | ||
3914 | /* Re-enable parallel detect */ | |
3915 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3916 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
3917 | (digctrl_kx2 | (1 << 2))); | |
3918 | ||
3919 | /* Enable autodet */ | |
3920 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3921 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, | |
3922 | (digctrl_kx1 | 0x10)); | |
3923 | } | |
3924 | ||
3925 | static void elink_warpcore_reset_lane(struct bnx2x_softc *sc, | |
3926 | struct elink_phy *phy, uint8_t reset) | |
3927 | { | |
3928 | uint16_t val; | |
3929 | /* Take lane out of reset after configuration is finished */ | |
3930 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
3931 | MDIO_WC_REG_DIGITAL5_MISC6, &val); | |
3932 | if (reset) | |
3933 | val |= 0xC000; | |
3934 | else | |
3935 | val &= 0x3FFF; | |
3936 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3937 | MDIO_WC_REG_DIGITAL5_MISC6, val); | |
3938 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
3939 | MDIO_WC_REG_DIGITAL5_MISC6, &val); | |
3940 | } | |
3941 | ||
3942 | /* Clear SFI/XFI link settings registers */ | |
3943 | static void elink_warpcore_clear_regs(struct elink_phy *phy, | |
3944 | struct elink_params *params, | |
3945 | uint16_t lane) | |
3946 | { | |
3947 | struct bnx2x_softc *sc = params->sc; | |
3948 | uint16_t i; | |
3949 | static struct elink_reg_set wc_regs[] = { | |
3950 | {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0}, | |
3951 | {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a}, | |
3952 | {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800}, | |
3953 | {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008}, | |
3954 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, | |
3955 | 0x0195}, | |
3956 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
3957 | 0x0007}, | |
3958 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, | |
3959 | 0x0002}, | |
3960 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000}, | |
3961 | {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000}, | |
3962 | {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040}, | |
3963 | {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140} | |
3964 | }; | |
3965 | /* Set XFI clock comp as default. */ | |
3966 | elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, | |
3967 | MDIO_WC_REG_RX66_CONTROL, (3 << 13)); | |
3968 | ||
3969 | for (i = 0; i < ARRAY_SIZE(wc_regs); i++) | |
3970 | elink_cl45_write(sc, phy, wc_regs[i].devad, wc_regs[i].reg, | |
3971 | wc_regs[i].val); | |
3972 | ||
3973 | lane = elink_get_warpcore_lane(params); | |
3974 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
3975 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane, 0x0990); | |
3976 | ||
3977 | } | |
3978 | ||
3979 | static elink_status_t elink_get_mod_abs_int_cfg(struct bnx2x_softc *sc, | |
3980 | uint32_t shmem_base, | |
3981 | uint8_t port, | |
3982 | uint8_t * gpio_num, | |
3983 | uint8_t * gpio_port) | |
3984 | { | |
3985 | uint32_t cfg_pin; | |
3986 | *gpio_num = 0; | |
3987 | *gpio_port = 0; | |
3988 | if (CHIP_IS_E3(sc)) { | |
3989 | cfg_pin = (REG_RD(sc, shmem_base + | |
3990 | offsetof(struct shmem_region, | |
3991 | dev_info.port_hw_config[port]. | |
3992 | e3_sfp_ctrl)) & | |
3993 | PORT_HW_CFG_E3_MOD_ABS_MASK) >> | |
3994 | PORT_HW_CFG_E3_MOD_ABS_SHIFT; | |
3995 | ||
3996 | /* Should not happen. This function called upon interrupt | |
3997 | * triggered by GPIO ( since EPIO can only generate interrupts | |
3998 | * to MCP). | |
3999 | * So if this function was called and none of the GPIOs was set, | |
4000 | * it means the shit hit the fan. | |
4001 | */ | |
4002 | if ((cfg_pin < PIN_CFG_GPIO0_P0) || | |
4003 | (cfg_pin > PIN_CFG_GPIO3_P1)) { | |
4004 | PMD_DRV_LOG(DEBUG, | |
4005 | "No cfg pin %x for module detect indication", | |
4006 | cfg_pin); | |
4007 | return ELINK_STATUS_ERROR; | |
4008 | } | |
4009 | ||
4010 | *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3; | |
4011 | *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2; | |
4012 | } else { | |
4013 | *gpio_num = MISC_REGISTERS_GPIO_3; | |
4014 | *gpio_port = port; | |
4015 | } | |
4016 | ||
4017 | return ELINK_STATUS_OK; | |
4018 | } | |
4019 | ||
4020 | static int elink_is_sfp_module_plugged(struct elink_params *params) | |
4021 | { | |
4022 | struct bnx2x_softc *sc = params->sc; | |
4023 | uint8_t gpio_num, gpio_port; | |
4024 | uint32_t gpio_val; | |
4025 | if (elink_get_mod_abs_int_cfg(sc, | |
4026 | params->shmem_base, params->port, | |
4027 | &gpio_num, &gpio_port) != ELINK_STATUS_OK) | |
4028 | return 0; | |
4029 | gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port); | |
4030 | ||
4031 | /* Call the handling function in case module is detected */ | |
4032 | if (gpio_val == 0) | |
4033 | return 1; | |
4034 | else | |
4035 | return 0; | |
4036 | } | |
4037 | ||
4038 | static int elink_warpcore_get_sigdet(struct elink_phy *phy, | |
4039 | struct elink_params *params) | |
4040 | { | |
4041 | uint16_t gp2_status_reg0, lane; | |
4042 | struct bnx2x_softc *sc = params->sc; | |
4043 | ||
4044 | lane = elink_get_warpcore_lane(params); | |
4045 | ||
4046 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, | |
4047 | &gp2_status_reg0); | |
4048 | ||
4049 | return (gp2_status_reg0 >> (8 + lane)) & 0x1; | |
4050 | } | |
4051 | ||
4052 | static void elink_warpcore_config_runtime(struct elink_phy *phy, | |
4053 | struct elink_params *params, | |
4054 | struct elink_vars *vars) | |
4055 | { | |
4056 | struct bnx2x_softc *sc = params->sc; | |
4057 | uint32_t serdes_net_if; | |
4058 | uint16_t gp_status1 = 0, lnkup = 0, lnkup_kr = 0; | |
4059 | ||
4060 | vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1; | |
4061 | ||
4062 | if (!vars->turn_to_run_wc_rt) | |
4063 | return; | |
4064 | ||
4065 | if (vars->rx_tx_asic_rst) { | |
4066 | uint16_t lane = elink_get_warpcore_lane(params); | |
4067 | serdes_net_if = (REG_RD(sc, params->shmem_base + | |
4068 | offsetof(struct shmem_region, | |
4069 | dev_info.port_hw_config | |
4070 | [params->port]. | |
4071 | default_cfg)) & | |
4072 | PORT_HW_CFG_NET_SERDES_IF_MASK); | |
4073 | ||
4074 | switch (serdes_net_if) { | |
4075 | case PORT_HW_CFG_NET_SERDES_IF_KR: | |
4076 | /* Do we get link yet? */ | |
4077 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1, | |
4078 | &gp_status1); | |
4079 | lnkup = (gp_status1 >> (8 + lane)) & 0x1; /* 1G */ | |
4080 | /*10G KR */ | |
4081 | lnkup_kr = (gp_status1 >> (12 + lane)) & 0x1; | |
4082 | ||
4083 | if (lnkup_kr || lnkup) { | |
4084 | vars->rx_tx_asic_rst = 0; | |
4085 | } else { | |
4086 | /* Reset the lane to see if link comes up. */ | |
4087 | elink_warpcore_reset_lane(sc, phy, 1); | |
4088 | elink_warpcore_reset_lane(sc, phy, 0); | |
4089 | ||
4090 | /* Restart Autoneg */ | |
4091 | elink_cl45_write(sc, phy, MDIO_AN_DEVAD, | |
4092 | MDIO_WC_REG_IEEE0BLK_MIICNTL, | |
4093 | 0x1200); | |
4094 | ||
4095 | vars->rx_tx_asic_rst--; | |
4096 | PMD_DRV_LOG(DEBUG, "0x%x retry left", | |
4097 | vars->rx_tx_asic_rst); | |
4098 | } | |
4099 | break; | |
4100 | ||
4101 | default: | |
4102 | break; | |
4103 | } | |
4104 | ||
4105 | } | |
4106 | /*params->rx_tx_asic_rst */ | |
4107 | } | |
4108 | ||
4109 | static void elink_warpcore_config_sfi(struct elink_phy *phy, | |
4110 | struct elink_params *params) | |
4111 | { | |
4112 | uint16_t lane = elink_get_warpcore_lane(params); | |
4113 | ||
4114 | elink_warpcore_clear_regs(phy, params, lane); | |
4115 | if ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] == | |
4116 | ELINK_SPEED_10000) && | |
4117 | (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) { | |
4118 | PMD_DRV_LOG(DEBUG, "Setting 10G SFI"); | |
4119 | elink_warpcore_set_10G_XFI(phy, params, 0); | |
4120 | } else { | |
4121 | PMD_DRV_LOG(DEBUG, "Setting 1G Fiber"); | |
4122 | elink_warpcore_set_sgmii_speed(phy, params, 1, 0); | |
4123 | } | |
4124 | } | |
4125 | ||
4126 | static void elink_sfp_e3_set_transmitter(struct elink_params *params, | |
4127 | struct elink_phy *phy, uint8_t tx_en) | |
4128 | { | |
4129 | struct bnx2x_softc *sc = params->sc; | |
4130 | uint32_t cfg_pin; | |
4131 | uint8_t port = params->port; | |
4132 | ||
4133 | cfg_pin = REG_RD(sc, params->shmem_base + | |
4134 | offsetof(struct shmem_region, | |
4135 | dev_info.port_hw_config[port].e3_sfp_ctrl)) & | |
4136 | PORT_HW_CFG_E3_TX_LASER_MASK; | |
4137 | /* Set the !tx_en since this pin is DISABLE_TX_LASER */ | |
4138 | PMD_DRV_LOG(DEBUG, "Setting WC TX to %d", tx_en); | |
4139 | ||
4140 | /* For 20G, the expected pin to be used is 3 pins after the current */ | |
4141 | elink_set_cfg_pin(sc, cfg_pin, tx_en ^ 1); | |
4142 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) | |
4143 | elink_set_cfg_pin(sc, cfg_pin + 3, tx_en ^ 1); | |
4144 | } | |
4145 | ||
4146 | static void elink_warpcore_config_init(struct elink_phy *phy, | |
4147 | struct elink_params *params, | |
4148 | struct elink_vars *vars) | |
4149 | { | |
4150 | struct bnx2x_softc *sc = params->sc; | |
4151 | uint32_t serdes_net_if; | |
4152 | uint8_t fiber_mode; | |
4153 | uint16_t lane = elink_get_warpcore_lane(params); | |
4154 | serdes_net_if = (REG_RD(sc, params->shmem_base + | |
4155 | offsetof(struct shmem_region, | |
4156 | dev_info.port_hw_config[params->port]. | |
4157 | default_cfg)) & | |
4158 | PORT_HW_CFG_NET_SERDES_IF_MASK); | |
4159 | PMD_DRV_LOG(DEBUG, | |
4160 | "Begin Warpcore init, link_speed %d, " | |
4161 | "serdes_net_if = 0x%x", vars->line_speed, serdes_net_if); | |
4162 | elink_set_aer_mmd(params, phy); | |
4163 | elink_warpcore_reset_lane(sc, phy, 1); | |
4164 | vars->phy_flags |= PHY_XGXS_FLAG; | |
4165 | if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) || | |
4166 | (phy->req_line_speed && | |
4167 | ((phy->req_line_speed == ELINK_SPEED_100) || | |
4168 | (phy->req_line_speed == ELINK_SPEED_10)))) { | |
4169 | vars->phy_flags |= PHY_SGMII_FLAG; | |
4170 | PMD_DRV_LOG(DEBUG, "Setting SGMII mode"); | |
4171 | elink_warpcore_clear_regs(phy, params, lane); | |
4172 | elink_warpcore_set_sgmii_speed(phy, params, 0, 1); | |
4173 | } else { | |
4174 | switch (serdes_net_if) { | |
4175 | case PORT_HW_CFG_NET_SERDES_IF_KR: | |
4176 | /* Enable KR Auto Neg */ | |
4177 | if (params->loopback_mode != ELINK_LOOPBACK_EXT) | |
4178 | elink_warpcore_enable_AN_KR(phy, params, vars); | |
4179 | else { | |
4180 | PMD_DRV_LOG(DEBUG, "Setting KR 10G-Force"); | |
4181 | elink_warpcore_set_10G_KR(phy, params); | |
4182 | } | |
4183 | break; | |
4184 | ||
4185 | case PORT_HW_CFG_NET_SERDES_IF_XFI: | |
4186 | elink_warpcore_clear_regs(phy, params, lane); | |
4187 | if (vars->line_speed == ELINK_SPEED_10000) { | |
4188 | PMD_DRV_LOG(DEBUG, "Setting 10G XFI"); | |
4189 | elink_warpcore_set_10G_XFI(phy, params, 1); | |
4190 | } else { | |
4191 | if (ELINK_SINGLE_MEDIA_DIRECT(params)) { | |
4192 | PMD_DRV_LOG(DEBUG, "1G Fiber"); | |
4193 | fiber_mode = 1; | |
4194 | } else { | |
4195 | PMD_DRV_LOG(DEBUG, "10/100/1G SGMII"); | |
4196 | fiber_mode = 0; | |
4197 | } | |
4198 | elink_warpcore_set_sgmii_speed(phy, | |
4199 | params, | |
4200 | fiber_mode, 0); | |
4201 | } | |
4202 | ||
4203 | break; | |
4204 | ||
4205 | case PORT_HW_CFG_NET_SERDES_IF_SFI: | |
4206 | /* Issue Module detection if module is plugged, or | |
4207 | * enabled transmitter to avoid current leakage in case | |
4208 | * no module is connected | |
4209 | */ | |
4210 | if ((params->loopback_mode == ELINK_LOOPBACK_NONE) || | |
4211 | (params->loopback_mode == ELINK_LOOPBACK_EXT)) { | |
4212 | if (elink_is_sfp_module_plugged(params)) | |
4213 | elink_sfp_module_detection(phy, params); | |
4214 | else | |
4215 | elink_sfp_e3_set_transmitter(params, | |
4216 | phy, 1); | |
4217 | } | |
4218 | ||
4219 | elink_warpcore_config_sfi(phy, params); | |
4220 | break; | |
4221 | ||
4222 | case PORT_HW_CFG_NET_SERDES_IF_DXGXS: | |
4223 | if (vars->line_speed != ELINK_SPEED_20000) { | |
4224 | PMD_DRV_LOG(DEBUG, "Speed not supported yet"); | |
4225 | return; | |
4226 | } | |
4227 | PMD_DRV_LOG(DEBUG, "Setting 20G DXGXS"); | |
4228 | elink_warpcore_set_20G_DXGXS(sc, phy, lane); | |
4229 | /* Issue Module detection */ | |
4230 | ||
4231 | elink_sfp_module_detection(phy, params); | |
4232 | break; | |
4233 | case PORT_HW_CFG_NET_SERDES_IF_KR2: | |
4234 | if (!params->loopback_mode) { | |
4235 | elink_warpcore_enable_AN_KR(phy, params, vars); | |
4236 | } else { | |
4237 | PMD_DRV_LOG(DEBUG, "Setting KR 20G-Force"); | |
4238 | elink_warpcore_set_20G_force_KR2(phy, params); | |
4239 | } | |
4240 | break; | |
4241 | default: | |
4242 | PMD_DRV_LOG(DEBUG, | |
4243 | "Unsupported Serdes Net Interface 0x%x", | |
4244 | serdes_net_if); | |
4245 | return; | |
4246 | } | |
4247 | } | |
4248 | ||
4249 | /* Take lane out of reset after configuration is finished */ | |
4250 | elink_warpcore_reset_lane(sc, phy, 0); | |
4251 | PMD_DRV_LOG(DEBUG, "Exit config init"); | |
4252 | } | |
4253 | ||
4254 | static void elink_warpcore_link_reset(struct elink_phy *phy, | |
4255 | struct elink_params *params) | |
4256 | { | |
4257 | struct bnx2x_softc *sc = params->sc; | |
4258 | uint16_t val16, lane; | |
4259 | elink_sfp_e3_set_transmitter(params, phy, 0); | |
4260 | elink_set_mdio_emac_per_phy(sc, params); | |
4261 | elink_set_aer_mmd(params, phy); | |
4262 | /* Global register */ | |
4263 | elink_warpcore_reset_lane(sc, phy, 1); | |
4264 | ||
4265 | /* Clear loopback settings (if any) */ | |
4266 | /* 10G & 20G */ | |
4267 | elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, | |
4268 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF); | |
4269 | ||
4270 | elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, | |
4271 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe); | |
4272 | ||
4273 | /* Update those 1-copy registers */ | |
4274 | CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, | |
4275 | MDIO_AER_BLOCK_AER_REG, 0); | |
4276 | /* Enable 1G MDIO (1-copy) */ | |
4277 | elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, | |
4278 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~0x10); | |
4279 | ||
4280 | elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, | |
4281 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00); | |
4282 | lane = elink_get_warpcore_lane(params); | |
4283 | /* Disable CL36 PCS Tx */ | |
4284 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
4285 | MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); | |
4286 | val16 |= (0x11 << lane); | |
4287 | if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) | |
4288 | val16 |= (0x22 << lane); | |
4289 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
4290 | MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); | |
4291 | ||
4292 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
4293 | MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); | |
4294 | val16 &= ~(0x0303 << (lane << 1)); | |
4295 | val16 |= (0x0101 << (lane << 1)); | |
4296 | if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) { | |
4297 | val16 &= ~(0x0c0c << (lane << 1)); | |
4298 | val16 |= (0x0404 << (lane << 1)); | |
4299 | } | |
4300 | ||
4301 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
4302 | MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); | |
4303 | /* Restore AER */ | |
4304 | elink_set_aer_mmd(params, phy); | |
4305 | ||
4306 | } | |
4307 | ||
4308 | static void elink_set_warpcore_loopback(struct elink_phy *phy, | |
4309 | struct elink_params *params) | |
4310 | { | |
4311 | struct bnx2x_softc *sc = params->sc; | |
4312 | uint16_t val16; | |
4313 | uint32_t lane; | |
4314 | PMD_DRV_LOG(DEBUG, "Setting Warpcore loopback type %x, speed %d", | |
4315 | params->loopback_mode, phy->req_line_speed); | |
4316 | ||
4317 | if (phy->req_line_speed < ELINK_SPEED_10000 || | |
4318 | phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) { | |
4319 | /* 10/100/1000/20G-KR2 */ | |
4320 | ||
4321 | /* Update those 1-copy registers */ | |
4322 | CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, | |
4323 | MDIO_AER_BLOCK_AER_REG, 0); | |
4324 | /* Enable 1G MDIO (1-copy) */ | |
4325 | elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, | |
4326 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, | |
4327 | 0x10); | |
4328 | /* Set 1G loopback based on lane (1-copy) */ | |
4329 | lane = elink_get_warpcore_lane(params); | |
4330 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
4331 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); | |
4332 | val16 |= (1 << lane); | |
4333 | if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) | |
4334 | val16 |= (2 << lane); | |
4335 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
4336 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, val16); | |
4337 | ||
4338 | /* Switch back to 4-copy registers */ | |
4339 | elink_set_aer_mmd(params, phy); | |
4340 | } else { | |
4341 | /* 10G / 20G-DXGXS */ | |
4342 | elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, | |
4343 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, | |
4344 | 0x4000); | |
4345 | elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, | |
4346 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1); | |
4347 | } | |
4348 | } | |
4349 | ||
4350 | static void elink_sync_link(struct elink_params *params, | |
4351 | struct elink_vars *vars) | |
4352 | { | |
4353 | struct bnx2x_softc *sc = params->sc; | |
4354 | uint8_t link_10g_plus; | |
4355 | if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) | |
4356 | vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; | |
4357 | vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); | |
4358 | if (vars->link_up) { | |
4359 | PMD_DRV_LOG(DEBUG, "phy link up"); | |
4360 | ||
4361 | vars->phy_link_up = 1; | |
4362 | vars->duplex = DUPLEX_FULL; | |
4363 | switch (vars->link_status & LINK_STATUS_SPEED_AND_DUPLEX_MASK) { | |
4364 | case ELINK_LINK_10THD: | |
4365 | vars->duplex = DUPLEX_HALF; | |
4366 | /* Fall thru */ | |
4367 | case ELINK_LINK_10TFD: | |
4368 | vars->line_speed = ELINK_SPEED_10; | |
4369 | break; | |
4370 | ||
4371 | case ELINK_LINK_100TXHD: | |
4372 | vars->duplex = DUPLEX_HALF; | |
4373 | /* Fall thru */ | |
4374 | case ELINK_LINK_100T4: | |
4375 | case ELINK_LINK_100TXFD: | |
4376 | vars->line_speed = ELINK_SPEED_100; | |
4377 | break; | |
4378 | ||
4379 | case ELINK_LINK_1000THD: | |
4380 | vars->duplex = DUPLEX_HALF; | |
4381 | /* Fall thru */ | |
4382 | case ELINK_LINK_1000TFD: | |
4383 | vars->line_speed = ELINK_SPEED_1000; | |
4384 | break; | |
4385 | ||
4386 | case ELINK_LINK_2500THD: | |
4387 | vars->duplex = DUPLEX_HALF; | |
4388 | /* Fall thru */ | |
4389 | case ELINK_LINK_2500TFD: | |
4390 | vars->line_speed = ELINK_SPEED_2500; | |
4391 | break; | |
4392 | ||
4393 | case ELINK_LINK_10GTFD: | |
4394 | vars->line_speed = ELINK_SPEED_10000; | |
4395 | break; | |
4396 | case ELINK_LINK_20GTFD: | |
4397 | vars->line_speed = ELINK_SPEED_20000; | |
4398 | break; | |
4399 | default: | |
4400 | break; | |
4401 | } | |
4402 | vars->flow_ctrl = 0; | |
4403 | if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) | |
4404 | vars->flow_ctrl |= ELINK_FLOW_CTRL_TX; | |
4405 | ||
4406 | if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) | |
4407 | vars->flow_ctrl |= ELINK_FLOW_CTRL_RX; | |
4408 | ||
4409 | if (!vars->flow_ctrl) | |
4410 | vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; | |
4411 | ||
4412 | if (vars->line_speed && | |
4413 | ((vars->line_speed == ELINK_SPEED_10) || | |
4414 | (vars->line_speed == ELINK_SPEED_100))) { | |
4415 | vars->phy_flags |= PHY_SGMII_FLAG; | |
4416 | } else { | |
4417 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
4418 | } | |
4419 | if (vars->line_speed && | |
4420 | USES_WARPCORE(sc) && (vars->line_speed == ELINK_SPEED_1000)) | |
4421 | vars->phy_flags |= PHY_SGMII_FLAG; | |
4422 | /* Anything 10 and over uses the bmac */ | |
4423 | link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000); | |
4424 | ||
4425 | if (link_10g_plus) { | |
4426 | if (USES_WARPCORE(sc)) | |
4427 | vars->mac_type = ELINK_MAC_TYPE_XMAC; | |
4428 | else | |
4429 | vars->mac_type = ELINK_MAC_TYPE_BMAC; | |
4430 | } else { | |
4431 | if (USES_WARPCORE(sc)) | |
4432 | vars->mac_type = ELINK_MAC_TYPE_UMAC; | |
4433 | else | |
4434 | vars->mac_type = ELINK_MAC_TYPE_EMAC; | |
4435 | } | |
4436 | } else { /* Link down */ | |
4437 | PMD_DRV_LOG(DEBUG, "phy link down"); | |
4438 | ||
4439 | vars->phy_link_up = 0; | |
4440 | ||
4441 | vars->line_speed = 0; | |
4442 | vars->duplex = DUPLEX_FULL; | |
4443 | vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; | |
4444 | ||
4445 | /* Indicate no mac active */ | |
4446 | vars->mac_type = ELINK_MAC_TYPE_NONE; | |
4447 | if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) | |
4448 | vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; | |
4449 | if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) | |
4450 | vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG; | |
4451 | } | |
4452 | } | |
4453 | ||
4454 | void elink_link_status_update(struct elink_params *params, | |
4455 | struct elink_vars *vars) | |
4456 | { | |
4457 | struct bnx2x_softc *sc = params->sc; | |
4458 | uint8_t port = params->port; | |
4459 | uint32_t sync_offset, media_types; | |
4460 | /* Update PHY configuration */ | |
4461 | set_phy_vars(params, vars); | |
4462 | ||
4463 | vars->link_status = REG_RD(sc, params->shmem_base + | |
4464 | offsetof(struct shmem_region, | |
4465 | port_mb[port].link_status)); | |
4466 | ||
4467 | /* Force link UP in non LOOPBACK_EXT loopback mode(s) */ | |
4468 | if (params->loopback_mode != ELINK_LOOPBACK_NONE && | |
4469 | params->loopback_mode != ELINK_LOOPBACK_EXT) | |
4470 | vars->link_status |= LINK_STATUS_LINK_UP; | |
4471 | ||
4472 | if (elink_eee_has_cap(params)) | |
4473 | vars->eee_status = REG_RD(sc, params->shmem2_base + | |
4474 | offsetof(struct shmem2_region, | |
4475 | eee_status[params->port])); | |
4476 | ||
4477 | vars->phy_flags = PHY_XGXS_FLAG; | |
4478 | elink_sync_link(params, vars); | |
4479 | /* Sync media type */ | |
4480 | sync_offset = params->shmem_base + | |
4481 | offsetof(struct shmem_region, | |
4482 | dev_info.port_hw_config[port].media_type); | |
4483 | media_types = REG_RD(sc, sync_offset); | |
4484 | ||
4485 | params->phy[ELINK_INT_PHY].media_type = | |
4486 | (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >> | |
4487 | PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT; | |
4488 | params->phy[ELINK_EXT_PHY1].media_type = | |
4489 | (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >> | |
4490 | PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT; | |
4491 | params->phy[ELINK_EXT_PHY2].media_type = | |
4492 | (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >> | |
4493 | PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT; | |
4494 | PMD_DRV_LOG(DEBUG, "media_types = 0x%x", media_types); | |
4495 | ||
4496 | /* Sync AEU offset */ | |
4497 | sync_offset = params->shmem_base + | |
4498 | offsetof(struct shmem_region, | |
4499 | dev_info.port_hw_config[port].aeu_int_mask); | |
4500 | ||
4501 | vars->aeu_int_mask = REG_RD(sc, sync_offset); | |
4502 | ||
4503 | /* Sync PFC status */ | |
4504 | if (vars->link_status & LINK_STATUS_PFC_ENABLED) | |
4505 | params->feature_config_flags |= | |
4506 | ELINK_FEATURE_CONFIG_PFC_ENABLED; | |
4507 | else | |
4508 | params->feature_config_flags &= | |
4509 | ~ELINK_FEATURE_CONFIG_PFC_ENABLED; | |
4510 | ||
4511 | if (SHMEM2_HAS(sc, link_attr_sync)) | |
4512 | vars->link_attr_sync = SHMEM2_RD(sc, | |
4513 | link_attr_sync[params->port]); | |
4514 | ||
4515 | PMD_DRV_LOG(DEBUG, "link_status 0x%x phy_link_up %x int_mask 0x%x", | |
4516 | vars->link_status, vars->phy_link_up, vars->aeu_int_mask); | |
4517 | PMD_DRV_LOG(DEBUG, "line_speed %x duplex %x flow_ctrl 0x%x", | |
4518 | vars->line_speed, vars->duplex, vars->flow_ctrl); | |
4519 | } | |
4520 | ||
4521 | static void elink_set_master_ln(struct elink_params *params, | |
4522 | struct elink_phy *phy) | |
4523 | { | |
4524 | struct bnx2x_softc *sc = params->sc; | |
4525 | uint16_t new_master_ln, ser_lane; | |
4526 | ser_lane = ((params->lane_config & | |
4527 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> | |
4528 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
4529 | ||
4530 | /* Set the master_ln for AN */ | |
4531 | CL22_RD_OVER_CL45(sc, phy, | |
4532 | MDIO_REG_BANK_XGXS_BLOCK2, | |
4533 | MDIO_XGXS_BLOCK2_TEST_MODE_LANE, &new_master_ln); | |
4534 | ||
4535 | CL22_WR_OVER_CL45(sc, phy, | |
4536 | MDIO_REG_BANK_XGXS_BLOCK2, | |
4537 | MDIO_XGXS_BLOCK2_TEST_MODE_LANE, | |
4538 | (new_master_ln | ser_lane)); | |
4539 | } | |
4540 | ||
4541 | static elink_status_t elink_reset_unicore(struct elink_params *params, | |
4542 | struct elink_phy *phy, | |
4543 | uint8_t set_serdes) | |
4544 | { | |
4545 | struct bnx2x_softc *sc = params->sc; | |
4546 | uint16_t mii_control; | |
4547 | uint16_t i; | |
4548 | CL22_RD_OVER_CL45(sc, phy, | |
4549 | MDIO_REG_BANK_COMBO_IEEE0, | |
4550 | MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); | |
4551 | ||
4552 | /* Reset the unicore */ | |
4553 | CL22_WR_OVER_CL45(sc, phy, | |
4554 | MDIO_REG_BANK_COMBO_IEEE0, | |
4555 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
4556 | (mii_control | MDIO_COMBO_IEEO_MII_CONTROL_RESET)); | |
4557 | if (set_serdes) | |
4558 | elink_set_serdes_access(sc, params->port); | |
4559 | ||
4560 | /* Wait for the reset to self clear */ | |
4561 | for (i = 0; i < ELINK_MDIO_ACCESS_TIMEOUT; i++) { | |
4562 | DELAY(5); | |
4563 | ||
4564 | /* The reset erased the previous bank value */ | |
4565 | CL22_RD_OVER_CL45(sc, phy, | |
4566 | MDIO_REG_BANK_COMBO_IEEE0, | |
4567 | MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); | |
4568 | ||
4569 | if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { | |
4570 | DELAY(5); | |
4571 | return ELINK_STATUS_OK; | |
4572 | } | |
4573 | } | |
4574 | ||
4575 | elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized," | |
4576 | // " Port %d", | |
4577 | ||
4578 | PMD_DRV_LOG(DEBUG, "BUG! XGXS is still in reset!"); | |
4579 | return ELINK_STATUS_ERROR; | |
4580 | ||
4581 | } | |
4582 | ||
4583 | static void elink_set_swap_lanes(struct elink_params *params, | |
4584 | struct elink_phy *phy) | |
4585 | { | |
4586 | struct bnx2x_softc *sc = params->sc; | |
4587 | /* Each two bits represents a lane number: | |
4588 | * No swap is 0123 => 0x1b no need to enable the swap | |
4589 | */ | |
4590 | uint16_t rx_lane_swap, tx_lane_swap; | |
4591 | ||
4592 | rx_lane_swap = ((params->lane_config & | |
4593 | PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> | |
4594 | PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); | |
4595 | tx_lane_swap = ((params->lane_config & | |
4596 | PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> | |
4597 | PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); | |
4598 | ||
4599 | if (rx_lane_swap != 0x1b) { | |
4600 | CL22_WR_OVER_CL45(sc, phy, | |
4601 | MDIO_REG_BANK_XGXS_BLOCK2, | |
4602 | MDIO_XGXS_BLOCK2_RX_LN_SWAP, | |
4603 | (rx_lane_swap | | |
4604 | MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | | |
4605 | MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); | |
4606 | } else { | |
4607 | CL22_WR_OVER_CL45(sc, phy, | |
4608 | MDIO_REG_BANK_XGXS_BLOCK2, | |
4609 | MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); | |
4610 | } | |
4611 | ||
4612 | if (tx_lane_swap != 0x1b) { | |
4613 | CL22_WR_OVER_CL45(sc, phy, | |
4614 | MDIO_REG_BANK_XGXS_BLOCK2, | |
4615 | MDIO_XGXS_BLOCK2_TX_LN_SWAP, | |
4616 | (tx_lane_swap | | |
4617 | MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); | |
4618 | } else { | |
4619 | CL22_WR_OVER_CL45(sc, phy, | |
4620 | MDIO_REG_BANK_XGXS_BLOCK2, | |
4621 | MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); | |
4622 | } | |
4623 | } | |
4624 | ||
4625 | static void elink_set_parallel_detection(struct elink_phy *phy, | |
4626 | struct elink_params *params) | |
4627 | { | |
4628 | struct bnx2x_softc *sc = params->sc; | |
4629 | uint16_t control2; | |
4630 | CL22_RD_OVER_CL45(sc, phy, | |
4631 | MDIO_REG_BANK_SERDES_DIGITAL, | |
4632 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, &control2); | |
4633 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) | |
4634 | control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; | |
4635 | else | |
4636 | control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; | |
4637 | PMD_DRV_LOG(DEBUG, "phy->speed_cap_mask = 0x%x, control2 = 0x%x", | |
4638 | phy->speed_cap_mask, control2); | |
4639 | CL22_WR_OVER_CL45(sc, phy, | |
4640 | MDIO_REG_BANK_SERDES_DIGITAL, | |
4641 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, control2); | |
4642 | ||
4643 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && | |
4644 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { | |
4645 | PMD_DRV_LOG(DEBUG, "XGXS"); | |
4646 | ||
4647 | CL22_WR_OVER_CL45(sc, phy, | |
4648 | MDIO_REG_BANK_10G_PARALLEL_DETECT, | |
4649 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, | |
4650 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); | |
4651 | ||
4652 | CL22_RD_OVER_CL45(sc, phy, | |
4653 | MDIO_REG_BANK_10G_PARALLEL_DETECT, | |
4654 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, | |
4655 | &control2); | |
4656 | ||
4657 | control2 |= | |
4658 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; | |
4659 | ||
4660 | CL22_WR_OVER_CL45(sc, phy, | |
4661 | MDIO_REG_BANK_10G_PARALLEL_DETECT, | |
4662 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, | |
4663 | control2); | |
4664 | ||
4665 | /* Disable parallel detection of HiG */ | |
4666 | CL22_WR_OVER_CL45(sc, phy, | |
4667 | MDIO_REG_BANK_XGXS_BLOCK2, | |
4668 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, | |
4669 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | | |
4670 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); | |
4671 | } | |
4672 | } | |
4673 | ||
4674 | static void elink_set_autoneg(struct elink_phy *phy, | |
4675 | struct elink_params *params, | |
4676 | struct elink_vars *vars, uint8_t enable_cl73) | |
4677 | { | |
4678 | struct bnx2x_softc *sc = params->sc; | |
4679 | uint16_t reg_val; | |
4680 | ||
4681 | /* CL37 Autoneg */ | |
4682 | CL22_RD_OVER_CL45(sc, phy, | |
4683 | MDIO_REG_BANK_COMBO_IEEE0, | |
4684 | MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); | |
4685 | ||
4686 | /* CL37 Autoneg Enabled */ | |
4687 | if (vars->line_speed == ELINK_SPEED_AUTO_NEG) | |
4688 | reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; | |
4689 | else /* CL37 Autoneg Disabled */ | |
4690 | reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | | |
4691 | MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); | |
4692 | ||
4693 | CL22_WR_OVER_CL45(sc, phy, | |
4694 | MDIO_REG_BANK_COMBO_IEEE0, | |
4695 | MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); | |
4696 | ||
4697 | /* Enable/Disable Autodetection */ | |
4698 | ||
4699 | CL22_RD_OVER_CL45(sc, phy, | |
4700 | MDIO_REG_BANK_SERDES_DIGITAL, | |
4701 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); | |
4702 | reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | | |
4703 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); | |
4704 | reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; | |
4705 | if (vars->line_speed == ELINK_SPEED_AUTO_NEG) | |
4706 | reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; | |
4707 | else | |
4708 | reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; | |
4709 | ||
4710 | CL22_WR_OVER_CL45(sc, phy, | |
4711 | MDIO_REG_BANK_SERDES_DIGITAL, | |
4712 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); | |
4713 | ||
4714 | /* Enable TetonII and BAM autoneg */ | |
4715 | CL22_RD_OVER_CL45(sc, phy, | |
4716 | MDIO_REG_BANK_BAM_NEXT_PAGE, | |
4717 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, ®_val); | |
4718 | if (vars->line_speed == ELINK_SPEED_AUTO_NEG) { | |
4719 | /* Enable BAM aneg Mode and TetonII aneg Mode */ | |
4720 | reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | | |
4721 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); | |
4722 | } else { | |
4723 | /* TetonII and BAM Autoneg Disabled */ | |
4724 | reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | | |
4725 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); | |
4726 | } | |
4727 | CL22_WR_OVER_CL45(sc, phy, | |
4728 | MDIO_REG_BANK_BAM_NEXT_PAGE, | |
4729 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, reg_val); | |
4730 | ||
4731 | if (enable_cl73) { | |
4732 | /* Enable Cl73 FSM status bits */ | |
4733 | CL22_WR_OVER_CL45(sc, phy, | |
4734 | MDIO_REG_BANK_CL73_USERB0, | |
4735 | MDIO_CL73_USERB0_CL73_UCTRL, 0xe); | |
4736 | ||
4737 | /* Enable BAM Station Manager */ | |
4738 | CL22_WR_OVER_CL45(sc, phy, | |
4739 | MDIO_REG_BANK_CL73_USERB0, | |
4740 | MDIO_CL73_USERB0_CL73_BAM_CTRL1, | |
4741 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | | |
4742 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | |
4743 | | | |
4744 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); | |
4745 | ||
4746 | /* Advertise CL73 link speeds */ | |
4747 | CL22_RD_OVER_CL45(sc, phy, | |
4748 | MDIO_REG_BANK_CL73_IEEEB1, | |
4749 | MDIO_CL73_IEEEB1_AN_ADV2, ®_val); | |
4750 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
4751 | reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; | |
4752 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) | |
4753 | reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; | |
4754 | ||
4755 | CL22_WR_OVER_CL45(sc, phy, | |
4756 | MDIO_REG_BANK_CL73_IEEEB1, | |
4757 | MDIO_CL73_IEEEB1_AN_ADV2, reg_val); | |
4758 | ||
4759 | /* CL73 Autoneg Enabled */ | |
4760 | reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; | |
4761 | ||
4762 | } else /* CL73 Autoneg Disabled */ | |
4763 | reg_val = 0; | |
4764 | ||
4765 | CL22_WR_OVER_CL45(sc, phy, | |
4766 | MDIO_REG_BANK_CL73_IEEEB0, | |
4767 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); | |
4768 | } | |
4769 | ||
4770 | /* Program SerDes, forced speed */ | |
4771 | static void elink_program_serdes(struct elink_phy *phy, | |
4772 | struct elink_params *params, | |
4773 | struct elink_vars *vars) | |
4774 | { | |
4775 | struct bnx2x_softc *sc = params->sc; | |
4776 | uint16_t reg_val; | |
4777 | ||
4778 | /* Program duplex, disable autoneg and sgmii */ | |
4779 | CL22_RD_OVER_CL45(sc, phy, | |
4780 | MDIO_REG_BANK_COMBO_IEEE0, | |
4781 | MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); | |
4782 | reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | | |
4783 | MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | | |
4784 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); | |
4785 | if (phy->req_duplex == DUPLEX_FULL) | |
4786 | reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; | |
4787 | CL22_WR_OVER_CL45(sc, phy, | |
4788 | MDIO_REG_BANK_COMBO_IEEE0, | |
4789 | MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); | |
4790 | ||
4791 | /* Program speed | |
4792 | * - needed only if the speed is greater than 1G (2.5G or 10G) | |
4793 | */ | |
4794 | CL22_RD_OVER_CL45(sc, phy, | |
4795 | MDIO_REG_BANK_SERDES_DIGITAL, | |
4796 | MDIO_SERDES_DIGITAL_MISC1, ®_val); | |
4797 | /* Clearing the speed value before setting the right speed */ | |
4798 | PMD_DRV_LOG(DEBUG, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x", reg_val); | |
4799 | ||
4800 | reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | | |
4801 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); | |
4802 | ||
4803 | if (!((vars->line_speed == ELINK_SPEED_1000) || | |
4804 | (vars->line_speed == ELINK_SPEED_100) || | |
4805 | (vars->line_speed == ELINK_SPEED_10))) { | |
4806 | ||
4807 | reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | | |
4808 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); | |
4809 | if (vars->line_speed == ELINK_SPEED_10000) | |
4810 | reg_val |= | |
4811 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; | |
4812 | } | |
4813 | ||
4814 | CL22_WR_OVER_CL45(sc, phy, | |
4815 | MDIO_REG_BANK_SERDES_DIGITAL, | |
4816 | MDIO_SERDES_DIGITAL_MISC1, reg_val); | |
4817 | ||
4818 | } | |
4819 | ||
4820 | static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy, | |
4821 | struct elink_params *params) | |
4822 | { | |
4823 | struct bnx2x_softc *sc = params->sc; | |
4824 | uint16_t val = 0; | |
4825 | ||
4826 | /* Set extended capabilities */ | |
4827 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) | |
4828 | val |= MDIO_OVER_1G_UP1_2_5G; | |
4829 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
4830 | val |= MDIO_OVER_1G_UP1_10G; | |
4831 | CL22_WR_OVER_CL45(sc, phy, | |
4832 | MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP1, val); | |
4833 | ||
4834 | CL22_WR_OVER_CL45(sc, phy, | |
4835 | MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP3, 0x400); | |
4836 | } | |
4837 | ||
4838 | static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy, | |
4839 | struct elink_params *params, | |
4840 | uint16_t ieee_fc) | |
4841 | { | |
4842 | struct bnx2x_softc *sc = params->sc; | |
4843 | uint16_t val; | |
4844 | /* For AN, we are always publishing full duplex */ | |
4845 | ||
4846 | CL22_WR_OVER_CL45(sc, phy, | |
4847 | MDIO_REG_BANK_COMBO_IEEE0, | |
4848 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); | |
4849 | CL22_RD_OVER_CL45(sc, phy, | |
4850 | MDIO_REG_BANK_CL73_IEEEB1, | |
4851 | MDIO_CL73_IEEEB1_AN_ADV1, &val); | |
4852 | val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; | |
4853 | val |= ((ieee_fc << 3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); | |
4854 | CL22_WR_OVER_CL45(sc, phy, | |
4855 | MDIO_REG_BANK_CL73_IEEEB1, | |
4856 | MDIO_CL73_IEEEB1_AN_ADV1, val); | |
4857 | } | |
4858 | ||
4859 | static void elink_restart_autoneg(struct elink_phy *phy, | |
4860 | struct elink_params *params, | |
4861 | uint8_t enable_cl73) | |
4862 | { | |
4863 | struct bnx2x_softc *sc = params->sc; | |
4864 | uint16_t mii_control; | |
4865 | ||
4866 | PMD_DRV_LOG(DEBUG, "elink_restart_autoneg"); | |
4867 | /* Enable and restart BAM/CL37 aneg */ | |
4868 | ||
4869 | if (enable_cl73) { | |
4870 | CL22_RD_OVER_CL45(sc, phy, | |
4871 | MDIO_REG_BANK_CL73_IEEEB0, | |
4872 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
4873 | &mii_control); | |
4874 | ||
4875 | CL22_WR_OVER_CL45(sc, phy, | |
4876 | MDIO_REG_BANK_CL73_IEEEB0, | |
4877 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
4878 | (mii_control | | |
4879 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | | |
4880 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); | |
4881 | } else { | |
4882 | ||
4883 | CL22_RD_OVER_CL45(sc, phy, | |
4884 | MDIO_REG_BANK_COMBO_IEEE0, | |
4885 | MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); | |
4886 | PMD_DRV_LOG(DEBUG, | |
4887 | "elink_restart_autoneg mii_control before = 0x%x", | |
4888 | mii_control); | |
4889 | CL22_WR_OVER_CL45(sc, phy, | |
4890 | MDIO_REG_BANK_COMBO_IEEE0, | |
4891 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
4892 | (mii_control | | |
4893 | MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | | |
4894 | MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); | |
4895 | } | |
4896 | } | |
4897 | ||
4898 | static void elink_initialize_sgmii_process(struct elink_phy *phy, | |
4899 | struct elink_params *params, | |
4900 | struct elink_vars *vars) | |
4901 | { | |
4902 | struct bnx2x_softc *sc = params->sc; | |
4903 | uint16_t control1; | |
4904 | ||
4905 | /* In SGMII mode, the unicore is always slave */ | |
4906 | ||
4907 | CL22_RD_OVER_CL45(sc, phy, | |
4908 | MDIO_REG_BANK_SERDES_DIGITAL, | |
4909 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &control1); | |
4910 | control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; | |
4911 | /* Set sgmii mode (and not fiber) */ | |
4912 | control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | | |
4913 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | | |
4914 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); | |
4915 | CL22_WR_OVER_CL45(sc, phy, | |
4916 | MDIO_REG_BANK_SERDES_DIGITAL, | |
4917 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, control1); | |
4918 | ||
4919 | /* If forced speed */ | |
4920 | if (!(vars->line_speed == ELINK_SPEED_AUTO_NEG)) { | |
4921 | /* Set speed, disable autoneg */ | |
4922 | uint16_t mii_control; | |
4923 | ||
4924 | CL22_RD_OVER_CL45(sc, phy, | |
4925 | MDIO_REG_BANK_COMBO_IEEE0, | |
4926 | MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); | |
4927 | mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | | |
4928 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK | | |
4929 | MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); | |
4930 | ||
4931 | switch (vars->line_speed) { | |
4932 | case ELINK_SPEED_100: | |
4933 | mii_control |= | |
4934 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; | |
4935 | break; | |
4936 | case ELINK_SPEED_1000: | |
4937 | mii_control |= | |
4938 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; | |
4939 | break; | |
4940 | case ELINK_SPEED_10: | |
4941 | /* There is nothing to set for 10M */ | |
4942 | break; | |
4943 | default: | |
4944 | /* Invalid speed for SGMII */ | |
4945 | PMD_DRV_LOG(DEBUG, "Invalid line_speed 0x%x", | |
4946 | vars->line_speed); | |
4947 | break; | |
4948 | } | |
4949 | ||
4950 | /* Setting the full duplex */ | |
4951 | if (phy->req_duplex == DUPLEX_FULL) | |
4952 | mii_control |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; | |
4953 | CL22_WR_OVER_CL45(sc, phy, | |
4954 | MDIO_REG_BANK_COMBO_IEEE0, | |
4955 | MDIO_COMBO_IEEE0_MII_CONTROL, mii_control); | |
4956 | ||
4957 | } else { /* AN mode */ | |
4958 | /* Enable and restart AN */ | |
4959 | elink_restart_autoneg(phy, params, 0); | |
4960 | } | |
4961 | } | |
4962 | ||
4963 | /* Link management | |
4964 | */ | |
4965 | static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy, | |
4966 | struct elink_params | |
4967 | *params) | |
4968 | { | |
4969 | struct bnx2x_softc *sc = params->sc; | |
4970 | uint16_t pd_10g, status2_1000x; | |
4971 | if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) | |
4972 | return ELINK_STATUS_OK; | |
4973 | CL22_RD_OVER_CL45(sc, phy, | |
4974 | MDIO_REG_BANK_SERDES_DIGITAL, | |
4975 | MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x); | |
4976 | CL22_RD_OVER_CL45(sc, phy, | |
4977 | MDIO_REG_BANK_SERDES_DIGITAL, | |
4978 | MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x); | |
4979 | if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { | |
4980 | PMD_DRV_LOG(DEBUG, "1G parallel detect link on port %d", | |
4981 | params->port); | |
4982 | return ELINK_STATUS_ERROR; | |
4983 | } | |
4984 | ||
4985 | CL22_RD_OVER_CL45(sc, phy, | |
4986 | MDIO_REG_BANK_10G_PARALLEL_DETECT, | |
4987 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, &pd_10g); | |
4988 | ||
4989 | if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { | |
4990 | PMD_DRV_LOG(DEBUG, "10G parallel detect link on port %d", | |
4991 | params->port); | |
4992 | return ELINK_STATUS_ERROR; | |
4993 | } | |
4994 | return ELINK_STATUS_OK; | |
4995 | } | |
4996 | ||
4997 | static void elink_update_adv_fc(struct elink_phy *phy, | |
4998 | struct elink_params *params, | |
4999 | struct elink_vars *vars, uint32_t gp_status) | |
5000 | { | |
5001 | uint16_t ld_pause; /* local driver */ | |
5002 | uint16_t lp_pause; /* link partner */ | |
5003 | uint16_t pause_result; | |
5004 | struct bnx2x_softc *sc = params->sc; | |
5005 | if ((gp_status & | |
5006 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | | |
5007 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == | |
5008 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | | |
5009 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { | |
5010 | ||
5011 | CL22_RD_OVER_CL45(sc, phy, | |
5012 | MDIO_REG_BANK_CL73_IEEEB1, | |
5013 | MDIO_CL73_IEEEB1_AN_ADV1, &ld_pause); | |
5014 | CL22_RD_OVER_CL45(sc, phy, | |
5015 | MDIO_REG_BANK_CL73_IEEEB1, | |
5016 | MDIO_CL73_IEEEB1_AN_LP_ADV1, &lp_pause); | |
5017 | pause_result = (ld_pause & | |
5018 | MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8; | |
5019 | pause_result |= (lp_pause & | |
5020 | MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10; | |
5021 | PMD_DRV_LOG(DEBUG, "pause_result CL73 0x%x", pause_result); | |
5022 | } else { | |
5023 | CL22_RD_OVER_CL45(sc, phy, | |
5024 | MDIO_REG_BANK_COMBO_IEEE0, | |
5025 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV, &ld_pause); | |
5026 | CL22_RD_OVER_CL45(sc, phy, | |
5027 | MDIO_REG_BANK_COMBO_IEEE0, | |
5028 | MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, | |
5029 | &lp_pause); | |
5030 | pause_result = (ld_pause & | |
5031 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 5; | |
5032 | pause_result |= (lp_pause & | |
5033 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 7; | |
5034 | PMD_DRV_LOG(DEBUG, "pause_result CL37 0x%x", pause_result); | |
5035 | } | |
5036 | elink_pause_resolve(vars, pause_result); | |
5037 | ||
5038 | } | |
5039 | ||
5040 | static void elink_flow_ctrl_resolve(struct elink_phy *phy, | |
5041 | struct elink_params *params, | |
5042 | struct elink_vars *vars, uint32_t gp_status) | |
5043 | { | |
5044 | vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; | |
5045 | ||
5046 | /* Resolve from gp_status in case of AN complete and not sgmii */ | |
5047 | if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) { | |
5048 | /* Update the advertised flow-controled of LD/LP in AN */ | |
5049 | if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) | |
5050 | elink_update_adv_fc(phy, params, vars, gp_status); | |
5051 | /* But set the flow-control result as the requested one */ | |
5052 | vars->flow_ctrl = phy->req_flow_ctrl; | |
5053 | } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) | |
5054 | vars->flow_ctrl = params->req_fc_auto_adv; | |
5055 | else if ((gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) && | |
5056 | (!(vars->phy_flags & PHY_SGMII_FLAG))) { | |
5057 | if (elink_direct_parallel_detect_used(phy, params)) { | |
5058 | vars->flow_ctrl = params->req_fc_auto_adv; | |
5059 | return; | |
5060 | } | |
5061 | elink_update_adv_fc(phy, params, vars, gp_status); | |
5062 | } | |
5063 | PMD_DRV_LOG(DEBUG, "flow_ctrl 0x%x", vars->flow_ctrl); | |
5064 | } | |
5065 | ||
5066 | static void elink_check_fallback_to_cl37(struct elink_phy *phy, | |
5067 | struct elink_params *params) | |
5068 | { | |
5069 | struct bnx2x_softc *sc = params->sc; | |
5070 | uint16_t rx_status, ustat_val, cl37_fsm_received; | |
5071 | PMD_DRV_LOG(DEBUG, "elink_check_fallback_to_cl37"); | |
5072 | /* Step 1: Make sure signal is detected */ | |
5073 | CL22_RD_OVER_CL45(sc, phy, | |
5074 | MDIO_REG_BANK_RX0, MDIO_RX0_RX_STATUS, &rx_status); | |
5075 | if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != | |
5076 | (MDIO_RX0_RX_STATUS_SIGDET)) { | |
5077 | PMD_DRV_LOG(DEBUG, "Signal is not detected. Restoring CL73." | |
5078 | "rx_status(0x80b0) = 0x%x", rx_status); | |
5079 | CL22_WR_OVER_CL45(sc, phy, | |
5080 | MDIO_REG_BANK_CL73_IEEEB0, | |
5081 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
5082 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); | |
5083 | return; | |
5084 | } | |
5085 | /* Step 2: Check CL73 state machine */ | |
5086 | CL22_RD_OVER_CL45(sc, phy, | |
5087 | MDIO_REG_BANK_CL73_USERB0, | |
5088 | MDIO_CL73_USERB0_CL73_USTAT1, &ustat_val); | |
5089 | if ((ustat_val & | |
5090 | (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | | |
5091 | MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != | |
5092 | (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | | |
5093 | MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { | |
5094 | PMD_DRV_LOG(DEBUG, "CL73 state-machine is not stable. " | |
5095 | "ustat_val(0x8371) = 0x%x", ustat_val); | |
5096 | return; | |
5097 | } | |
5098 | /* Step 3: Check CL37 Message Pages received to indicate LP | |
5099 | * supports only CL37 | |
5100 | */ | |
5101 | CL22_RD_OVER_CL45(sc, phy, | |
5102 | MDIO_REG_BANK_REMOTE_PHY, | |
5103 | MDIO_REMOTE_PHY_MISC_RX_STATUS, &cl37_fsm_received); | |
5104 | if ((cl37_fsm_received & | |
5105 | (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | | |
5106 | MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != | |
5107 | (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | | |
5108 | MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { | |
5109 | PMD_DRV_LOG(DEBUG, "No CL37 FSM were received. " | |
5110 | "misc_rx_status(0x8330) = 0x%x", cl37_fsm_received); | |
5111 | return; | |
5112 | } | |
5113 | /* The combined cl37/cl73 fsm state information indicating that | |
5114 | * we are connected to a device which does not support cl73, but | |
5115 | * does support cl37 BAM. In this case we disable cl73 and | |
5116 | * restart cl37 auto-neg | |
5117 | */ | |
5118 | ||
5119 | /* Disable CL73 */ | |
5120 | CL22_WR_OVER_CL45(sc, phy, | |
5121 | MDIO_REG_BANK_CL73_IEEEB0, | |
5122 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 0); | |
5123 | /* Restart CL37 autoneg */ | |
5124 | elink_restart_autoneg(phy, params, 0); | |
5125 | PMD_DRV_LOG(DEBUG, "Disabling CL73, and restarting CL37 autoneg"); | |
5126 | } | |
5127 | ||
5128 | static void elink_xgxs_an_resolve(struct elink_phy *phy, | |
5129 | struct elink_params *params, | |
5130 | struct elink_vars *vars, uint32_t gp_status) | |
5131 | { | |
5132 | if (gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) | |
5133 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
5134 | ||
5135 | if (elink_direct_parallel_detect_used(phy, params)) | |
5136 | vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; | |
5137 | } | |
5138 | ||
5139 | static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy, | |
5140 | struct elink_params *params __rte_unused, | |
5141 | struct elink_vars *vars, | |
5142 | uint16_t is_link_up, | |
5143 | uint16_t speed_mask, | |
5144 | uint16_t is_duplex) | |
5145 | { | |
5146 | if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) | |
5147 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; | |
5148 | if (is_link_up) { | |
5149 | PMD_DRV_LOG(DEBUG, "phy link up"); | |
5150 | ||
5151 | vars->phy_link_up = 1; | |
5152 | vars->link_status |= LINK_STATUS_LINK_UP; | |
5153 | ||
5154 | switch (speed_mask) { | |
5155 | case ELINK_GP_STATUS_10M: | |
5156 | vars->line_speed = ELINK_SPEED_10; | |
5157 | if (is_duplex == DUPLEX_FULL) | |
5158 | vars->link_status |= ELINK_LINK_10TFD; | |
5159 | else | |
5160 | vars->link_status |= ELINK_LINK_10THD; | |
5161 | break; | |
5162 | ||
5163 | case ELINK_GP_STATUS_100M: | |
5164 | vars->line_speed = ELINK_SPEED_100; | |
5165 | if (is_duplex == DUPLEX_FULL) | |
5166 | vars->link_status |= ELINK_LINK_100TXFD; | |
5167 | else | |
5168 | vars->link_status |= ELINK_LINK_100TXHD; | |
5169 | break; | |
5170 | ||
5171 | case ELINK_GP_STATUS_1G: | |
5172 | case ELINK_GP_STATUS_1G_KX: | |
5173 | vars->line_speed = ELINK_SPEED_1000; | |
5174 | if (is_duplex == DUPLEX_FULL) | |
5175 | vars->link_status |= ELINK_LINK_1000TFD; | |
5176 | else | |
5177 | vars->link_status |= ELINK_LINK_1000THD; | |
5178 | break; | |
5179 | ||
5180 | case ELINK_GP_STATUS_2_5G: | |
5181 | vars->line_speed = ELINK_SPEED_2500; | |
5182 | if (is_duplex == DUPLEX_FULL) | |
5183 | vars->link_status |= ELINK_LINK_2500TFD; | |
5184 | else | |
5185 | vars->link_status |= ELINK_LINK_2500THD; | |
5186 | break; | |
5187 | ||
5188 | case ELINK_GP_STATUS_5G: | |
5189 | case ELINK_GP_STATUS_6G: | |
5190 | PMD_DRV_LOG(DEBUG, | |
5191 | "link speed unsupported gp_status 0x%x", | |
5192 | speed_mask); | |
5193 | return ELINK_STATUS_ERROR; | |
5194 | ||
5195 | case ELINK_GP_STATUS_10G_KX4: | |
5196 | case ELINK_GP_STATUS_10G_HIG: | |
5197 | case ELINK_GP_STATUS_10G_CX4: | |
5198 | case ELINK_GP_STATUS_10G_KR: | |
5199 | case ELINK_GP_STATUS_10G_SFI: | |
5200 | case ELINK_GP_STATUS_10G_XFI: | |
5201 | vars->line_speed = ELINK_SPEED_10000; | |
5202 | vars->link_status |= ELINK_LINK_10GTFD; | |
5203 | break; | |
5204 | case ELINK_GP_STATUS_20G_DXGXS: | |
5205 | case ELINK_GP_STATUS_20G_KR2: | |
5206 | vars->line_speed = ELINK_SPEED_20000; | |
5207 | vars->link_status |= ELINK_LINK_20GTFD; | |
5208 | break; | |
5209 | default: | |
5210 | PMD_DRV_LOG(DEBUG, | |
5211 | "link speed unsupported gp_status 0x%x", | |
5212 | speed_mask); | |
5213 | return ELINK_STATUS_ERROR; | |
5214 | } | |
5215 | } else { /* link_down */ | |
5216 | PMD_DRV_LOG(DEBUG, "phy link down"); | |
5217 | ||
5218 | vars->phy_link_up = 0; | |
5219 | ||
5220 | vars->duplex = DUPLEX_FULL; | |
5221 | vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; | |
5222 | vars->mac_type = ELINK_MAC_TYPE_NONE; | |
5223 | } | |
5224 | PMD_DRV_LOG(DEBUG, " phy_link_up %x line_speed %d", | |
5225 | vars->phy_link_up, vars->line_speed); | |
5226 | return ELINK_STATUS_OK; | |
5227 | } | |
5228 | ||
5229 | static elink_status_t elink_link_settings_status(struct elink_phy *phy, | |
5230 | struct elink_params *params, | |
5231 | struct elink_vars *vars) | |
5232 | { | |
5233 | struct bnx2x_softc *sc = params->sc; | |
5234 | ||
5235 | uint16_t gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask; | |
5236 | elink_status_t rc = ELINK_STATUS_OK; | |
5237 | ||
5238 | /* Read gp_status */ | |
5239 | CL22_RD_OVER_CL45(sc, phy, | |
5240 | MDIO_REG_BANK_GP_STATUS, | |
5241 | MDIO_GP_STATUS_TOP_AN_STATUS1, &gp_status); | |
5242 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) | |
5243 | duplex = DUPLEX_FULL; | |
5244 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) | |
5245 | link_up = 1; | |
5246 | speed_mask = gp_status & ELINK_GP_STATUS_SPEED_MASK; | |
5247 | PMD_DRV_LOG(DEBUG, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x", | |
5248 | gp_status, link_up, speed_mask); | |
5249 | rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, | |
5250 | duplex); | |
5251 | if (rc == ELINK_STATUS_ERROR) | |
5252 | return rc; | |
5253 | ||
5254 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { | |
5255 | if (ELINK_SINGLE_MEDIA_DIRECT(params)) { | |
5256 | vars->duplex = duplex; | |
5257 | elink_flow_ctrl_resolve(phy, params, vars, gp_status); | |
5258 | if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) | |
5259 | elink_xgxs_an_resolve(phy, params, vars, | |
5260 | gp_status); | |
5261 | } | |
5262 | } else { /* Link_down */ | |
5263 | if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && | |
5264 | ELINK_SINGLE_MEDIA_DIRECT(params)) { | |
5265 | /* Check signal is detected */ | |
5266 | elink_check_fallback_to_cl37(phy, params); | |
5267 | } | |
5268 | } | |
5269 | ||
5270 | /* Read LP advertised speeds */ | |
5271 | if (ELINK_SINGLE_MEDIA_DIRECT(params) && | |
5272 | (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) { | |
5273 | uint16_t val; | |
5274 | ||
5275 | CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB1, | |
5276 | MDIO_CL73_IEEEB1_AN_LP_ADV2, &val); | |
5277 | ||
5278 | if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) | |
5279 | vars->link_status |= | |
5280 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
5281 | if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | | |
5282 | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) | |
5283 | vars->link_status |= | |
5284 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5285 | ||
5286 | CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_OVER_1G, | |
5287 | MDIO_OVER_1G_LP_UP1, &val); | |
5288 | ||
5289 | if (val & MDIO_OVER_1G_UP1_2_5G) | |
5290 | vars->link_status |= | |
5291 | LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; | |
5292 | if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) | |
5293 | vars->link_status |= | |
5294 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5295 | } | |
5296 | ||
5297 | PMD_DRV_LOG(DEBUG, "duplex %x flow_ctrl 0x%x link_status 0x%x", | |
5298 | vars->duplex, vars->flow_ctrl, vars->link_status); | |
5299 | return rc; | |
5300 | } | |
5301 | ||
5302 | static elink_status_t elink_warpcore_read_status(struct elink_phy *phy, | |
5303 | struct elink_params *params, | |
5304 | struct elink_vars *vars) | |
5305 | { | |
5306 | struct bnx2x_softc *sc = params->sc; | |
5307 | uint8_t lane; | |
5308 | uint16_t gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL; | |
5309 | elink_status_t rc = ELINK_STATUS_OK; | |
5310 | lane = elink_get_warpcore_lane(params); | |
5311 | /* Read gp_status */ | |
5312 | if ((params->loopback_mode) && (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) { | |
5313 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
5314 | MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); | |
5315 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
5316 | MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); | |
5317 | link_up &= 0x1; | |
5318 | } else if ((phy->req_line_speed > ELINK_SPEED_10000) && | |
5319 | (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) { | |
5320 | uint16_t temp_link_up; | |
5321 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &temp_link_up); | |
5322 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &link_up); | |
5323 | PMD_DRV_LOG(DEBUG, "PCS RX link status = 0x%x-->0x%x", | |
5324 | temp_link_up, link_up); | |
5325 | link_up &= (1 << 2); | |
5326 | if (link_up) | |
5327 | elink_ext_phy_resolve_fc(phy, params, vars); | |
5328 | } else { | |
5329 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
5330 | MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1); | |
5331 | PMD_DRV_LOG(DEBUG, "0x81d1 = 0x%x", gp_status1); | |
5332 | /* Check for either KR, 1G, or AN up. */ | |
5333 | link_up = ((gp_status1 >> 8) | | |
5334 | (gp_status1 >> 12) | (gp_status1)) & (1 << lane); | |
5335 | if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) { | |
5336 | uint16_t an_link; | |
5337 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, | |
5338 | MDIO_AN_REG_STATUS, &an_link); | |
5339 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, | |
5340 | MDIO_AN_REG_STATUS, &an_link); | |
5341 | link_up |= (an_link & (1 << 2)); | |
5342 | } | |
5343 | if (link_up && ELINK_SINGLE_MEDIA_DIRECT(params)) { | |
5344 | uint16_t pd, gp_status4; | |
5345 | if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { | |
5346 | /* Check Autoneg complete */ | |
5347 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
5348 | MDIO_WC_REG_GP2_STATUS_GP_2_4, | |
5349 | &gp_status4); | |
5350 | if (gp_status4 & ((1 << 12) << lane)) | |
5351 | vars->link_status |= | |
5352 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
5353 | ||
5354 | /* Check parallel detect used */ | |
5355 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
5356 | MDIO_WC_REG_PAR_DET_10G_STATUS, | |
5357 | &pd); | |
5358 | if (pd & (1 << 15)) | |
5359 | vars->link_status |= | |
5360 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
5361 | } | |
5362 | elink_ext_phy_resolve_fc(phy, params, vars); | |
5363 | vars->duplex = duplex; | |
5364 | } | |
5365 | } | |
5366 | ||
5367 | if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) && | |
5368 | ELINK_SINGLE_MEDIA_DIRECT(params)) { | |
5369 | uint16_t val; | |
5370 | ||
5371 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, | |
5372 | MDIO_AN_REG_LP_AUTO_NEG2, &val); | |
5373 | ||
5374 | if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) | |
5375 | vars->link_status |= | |
5376 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
5377 | if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | | |
5378 | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) | |
5379 | vars->link_status |= | |
5380 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5381 | ||
5382 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
5383 | MDIO_WC_REG_DIGITAL3_LP_UP1, &val); | |
5384 | ||
5385 | if (val & MDIO_OVER_1G_UP1_2_5G) | |
5386 | vars->link_status |= | |
5387 | LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; | |
5388 | if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) | |
5389 | vars->link_status |= | |
5390 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5391 | ||
5392 | } | |
5393 | ||
5394 | if (lane < 2) { | |
5395 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
5396 | MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed); | |
5397 | } else { | |
5398 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
5399 | MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed); | |
5400 | } | |
5401 | PMD_DRV_LOG(DEBUG, "lane %d gp_speed 0x%x", lane, gp_speed); | |
5402 | ||
5403 | if ((lane & 1) == 0) | |
5404 | gp_speed <<= 8; | |
5405 | gp_speed &= 0x3f00; | |
5406 | link_up = ! !link_up; | |
5407 | ||
5408 | /* Reset the TX FIFO to fix SGMII issue */ | |
5409 | rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, | |
5410 | duplex); | |
5411 | ||
5412 | /* In case of KR link down, start up the recovering procedure */ | |
5413 | if ((!link_up) && (phy->media_type == ELINK_ETH_PHY_KR) && | |
5414 | (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE))) | |
5415 | vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; | |
5416 | ||
5417 | PMD_DRV_LOG(DEBUG, "duplex %x flow_ctrl 0x%x link_status 0x%x", | |
5418 | vars->duplex, vars->flow_ctrl, vars->link_status); | |
5419 | return rc; | |
5420 | } | |
5421 | ||
5422 | static void elink_set_gmii_tx_driver(struct elink_params *params) | |
5423 | { | |
5424 | struct bnx2x_softc *sc = params->sc; | |
5425 | struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; | |
5426 | uint16_t lp_up2; | |
5427 | uint16_t tx_driver; | |
5428 | uint16_t bank; | |
5429 | ||
5430 | /* Read precomp */ | |
5431 | CL22_RD_OVER_CL45(sc, phy, | |
5432 | MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_LP_UP2, &lp_up2); | |
5433 | ||
5434 | /* Bits [10:7] at lp_up2, positioned at [15:12] */ | |
5435 | lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> | |
5436 | MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << | |
5437 | MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); | |
5438 | ||
5439 | if (lp_up2 == 0) | |
5440 | return; | |
5441 | ||
5442 | for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; | |
5443 | bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { | |
5444 | CL22_RD_OVER_CL45(sc, phy, | |
5445 | bank, MDIO_TX0_TX_DRIVER, &tx_driver); | |
5446 | ||
5447 | /* Replace tx_driver bits [15:12] */ | |
5448 | if (lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { | |
5449 | tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; | |
5450 | tx_driver |= lp_up2; | |
5451 | CL22_WR_OVER_CL45(sc, phy, | |
5452 | bank, MDIO_TX0_TX_DRIVER, tx_driver); | |
5453 | } | |
5454 | } | |
5455 | } | |
5456 | ||
5457 | static elink_status_t elink_emac_program(struct elink_params *params, | |
5458 | struct elink_vars *vars) | |
5459 | { | |
5460 | struct bnx2x_softc *sc = params->sc; | |
5461 | uint8_t port = params->port; | |
5462 | uint16_t mode = 0; | |
5463 | ||
5464 | PMD_DRV_LOG(DEBUG, "setting link speed & duplex"); | |
5465 | elink_bits_dis(sc, GRCBASE_EMAC0 + port * 0x400 + | |
5466 | EMAC_REG_EMAC_MODE, | |
5467 | (EMAC_MODE_25G_MODE | | |
5468 | EMAC_MODE_PORT_MII_10M | EMAC_MODE_HALF_DUPLEX)); | |
5469 | switch (vars->line_speed) { | |
5470 | case ELINK_SPEED_10: | |
5471 | mode |= EMAC_MODE_PORT_MII_10M; | |
5472 | break; | |
5473 | ||
5474 | case ELINK_SPEED_100: | |
5475 | mode |= EMAC_MODE_PORT_MII; | |
5476 | break; | |
5477 | ||
5478 | case ELINK_SPEED_1000: | |
5479 | mode |= EMAC_MODE_PORT_GMII; | |
5480 | break; | |
5481 | ||
5482 | case ELINK_SPEED_2500: | |
5483 | mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII); | |
5484 | break; | |
5485 | ||
5486 | default: | |
5487 | /* 10G not valid for EMAC */ | |
5488 | PMD_DRV_LOG(DEBUG, "Invalid line_speed 0x%x", vars->line_speed); | |
5489 | return ELINK_STATUS_ERROR; | |
5490 | } | |
5491 | ||
5492 | if (vars->duplex == DUPLEX_HALF) | |
5493 | mode |= EMAC_MODE_HALF_DUPLEX; | |
5494 | elink_bits_en(sc, | |
5495 | GRCBASE_EMAC0 + port * 0x400 + EMAC_REG_EMAC_MODE, mode); | |
5496 | ||
5497 | elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed); | |
5498 | return ELINK_STATUS_OK; | |
5499 | } | |
5500 | ||
5501 | static void elink_set_preemphasis(struct elink_phy *phy, | |
5502 | struct elink_params *params) | |
5503 | { | |
5504 | ||
5505 | uint16_t bank, i = 0; | |
5506 | struct bnx2x_softc *sc = params->sc; | |
5507 | ||
5508 | for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; | |
5509 | bank += (MDIO_REG_BANK_RX1 - MDIO_REG_BANK_RX0), i++) { | |
5510 | CL22_WR_OVER_CL45(sc, phy, | |
5511 | bank, | |
5512 | MDIO_RX0_RX_EQ_BOOST, phy->rx_preemphasis[i]); | |
5513 | } | |
5514 | ||
5515 | for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; | |
5516 | bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { | |
5517 | CL22_WR_OVER_CL45(sc, phy, | |
5518 | bank, | |
5519 | MDIO_TX0_TX_DRIVER, phy->tx_preemphasis[i]); | |
5520 | } | |
5521 | } | |
5522 | ||
5523 | static void elink_xgxs_config_init(struct elink_phy *phy, | |
5524 | struct elink_params *params, | |
5525 | struct elink_vars *vars) | |
5526 | { | |
5527 | uint8_t enable_cl73 = (ELINK_SINGLE_MEDIA_DIRECT(params) || | |
5528 | (params->loopback_mode == ELINK_LOOPBACK_XGXS)); | |
5529 | ||
5530 | if (!(vars->phy_flags & PHY_SGMII_FLAG)) { | |
5531 | if (ELINK_SINGLE_MEDIA_DIRECT(params) && | |
5532 | (params->feature_config_flags & | |
5533 | ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) | |
5534 | elink_set_preemphasis(phy, params); | |
5535 | ||
5536 | /* Forced speed requested? */ | |
5537 | if (vars->line_speed != ELINK_SPEED_AUTO_NEG || | |
5538 | (ELINK_SINGLE_MEDIA_DIRECT(params) && | |
5539 | params->loopback_mode == ELINK_LOOPBACK_EXT)) { | |
5540 | PMD_DRV_LOG(DEBUG, "not SGMII, no AN"); | |
5541 | ||
5542 | /* Disable autoneg */ | |
5543 | elink_set_autoneg(phy, params, vars, 0); | |
5544 | ||
5545 | /* Program speed and duplex */ | |
5546 | elink_program_serdes(phy, params, vars); | |
5547 | ||
5548 | } else { /* AN_mode */ | |
5549 | PMD_DRV_LOG(DEBUG, "not SGMII, AN"); | |
5550 | ||
5551 | /* AN enabled */ | |
5552 | elink_set_brcm_cl37_advertisement(phy, params); | |
5553 | ||
5554 | /* Program duplex & pause advertisement (for aneg) */ | |
5555 | elink_set_ieee_aneg_advertisement(phy, params, | |
5556 | vars->ieee_fc); | |
5557 | ||
5558 | /* Enable autoneg */ | |
5559 | elink_set_autoneg(phy, params, vars, enable_cl73); | |
5560 | ||
5561 | /* Enable and restart AN */ | |
5562 | elink_restart_autoneg(phy, params, enable_cl73); | |
5563 | } | |
5564 | ||
5565 | } else { /* SGMII mode */ | |
5566 | PMD_DRV_LOG(DEBUG, "SGMII"); | |
5567 | ||
5568 | elink_initialize_sgmii_process(phy, params, vars); | |
5569 | } | |
5570 | } | |
5571 | ||
5572 | static elink_status_t elink_prepare_xgxs(struct elink_phy *phy, | |
5573 | struct elink_params *params, | |
5574 | struct elink_vars *vars) | |
5575 | { | |
5576 | elink_status_t rc; | |
5577 | vars->phy_flags |= PHY_XGXS_FLAG; | |
5578 | if ((phy->req_line_speed && | |
5579 | ((phy->req_line_speed == ELINK_SPEED_100) || | |
5580 | (phy->req_line_speed == ELINK_SPEED_10))) || | |
5581 | (!phy->req_line_speed && | |
5582 | (phy->speed_cap_mask >= | |
5583 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && | |
5584 | (phy->speed_cap_mask < | |
5585 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || | |
5586 | (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) | |
5587 | vars->phy_flags |= PHY_SGMII_FLAG; | |
5588 | else | |
5589 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
5590 | ||
5591 | elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); | |
5592 | elink_set_aer_mmd(params, phy); | |
5593 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) | |
5594 | elink_set_master_ln(params, phy); | |
5595 | ||
5596 | rc = elink_reset_unicore(params, phy, 0); | |
5597 | /* Reset the SerDes and wait for reset bit return low */ | |
5598 | if (rc != ELINK_STATUS_OK) | |
5599 | return rc; | |
5600 | ||
5601 | elink_set_aer_mmd(params, phy); | |
5602 | /* Setting the masterLn_def again after the reset */ | |
5603 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { | |
5604 | elink_set_master_ln(params, phy); | |
5605 | elink_set_swap_lanes(params, phy); | |
5606 | } | |
5607 | ||
5608 | return rc; | |
5609 | } | |
5610 | ||
5611 | static uint16_t elink_wait_reset_complete(struct bnx2x_softc *sc, | |
5612 | struct elink_phy *phy, | |
5613 | struct elink_params *params) | |
5614 | { | |
5615 | uint16_t cnt, ctrl; | |
5616 | /* Wait for soft reset to get cleared up to 1 sec */ | |
5617 | for (cnt = 0; cnt < 1000; cnt++) { | |
5618 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) | |
5619 | elink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &ctrl); | |
5620 | else | |
5621 | elink_cl45_read(sc, phy, | |
5622 | MDIO_PMA_DEVAD, | |
5623 | MDIO_PMA_REG_CTRL, &ctrl); | |
5624 | if (!(ctrl & (1 << 15))) | |
5625 | break; | |
5626 | DELAY(1000 * 1); | |
5627 | } | |
5628 | ||
5629 | if (cnt == 1000) | |
5630 | elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized," | |
5631 | // " Port %d", | |
5632 | ||
5633 | PMD_DRV_LOG(DEBUG, "control reg 0x%x (after %d ms)", ctrl, cnt); | |
5634 | return cnt; | |
5635 | } | |
5636 | ||
5637 | static void elink_link_int_enable(struct elink_params *params) | |
5638 | { | |
5639 | uint8_t port = params->port; | |
5640 | uint32_t mask; | |
5641 | struct bnx2x_softc *sc = params->sc; | |
5642 | ||
5643 | /* Setting the status to report on link up for either XGXS or SerDes */ | |
5644 | if (CHIP_IS_E3(sc)) { | |
5645 | mask = ELINK_NIG_MASK_XGXS0_LINK_STATUS; | |
5646 | if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) | |
5647 | mask |= ELINK_NIG_MASK_MI_INT; | |
5648 | } else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) { | |
5649 | mask = (ELINK_NIG_MASK_XGXS0_LINK10G | | |
5650 | ELINK_NIG_MASK_XGXS0_LINK_STATUS); | |
5651 | PMD_DRV_LOG(DEBUG, "enabled XGXS interrupt"); | |
5652 | if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && | |
5653 | params->phy[ELINK_INT_PHY].type != | |
5654 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { | |
5655 | mask |= ELINK_NIG_MASK_MI_INT; | |
5656 | PMD_DRV_LOG(DEBUG, "enabled external phy int"); | |
5657 | } | |
5658 | ||
5659 | } else { /* SerDes */ | |
5660 | mask = ELINK_NIG_MASK_SERDES0_LINK_STATUS; | |
5661 | PMD_DRV_LOG(DEBUG, "enabled SerDes interrupt"); | |
5662 | if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && | |
5663 | params->phy[ELINK_INT_PHY].type != | |
5664 | PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { | |
5665 | mask |= ELINK_NIG_MASK_MI_INT; | |
5666 | PMD_DRV_LOG(DEBUG, "enabled external phy int"); | |
5667 | } | |
5668 | } | |
5669 | elink_bits_en(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, mask); | |
5670 | ||
5671 | PMD_DRV_LOG(DEBUG, "port %x, is_xgxs %x, int_status 0x%x", port, | |
5672 | (params->switch_cfg == ELINK_SWITCH_CFG_10G), | |
5673 | REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4)); | |
5674 | PMD_DRV_LOG(DEBUG, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x", | |
5675 | REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4), | |
5676 | REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port * 0x18), | |
5677 | REG_RD(sc, | |
5678 | NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c)); | |
5679 | PMD_DRV_LOG(DEBUG, " 10G %x, XGXS_LINK %x", | |
5680 | REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68), | |
5681 | REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68)); | |
5682 | } | |
5683 | ||
5684 | static void elink_rearm_latch_signal(struct bnx2x_softc *sc, uint8_t port, | |
5685 | uint8_t exp_mi_int) | |
5686 | { | |
5687 | uint32_t latch_status = 0; | |
5688 | ||
5689 | /* Disable the MI INT ( external phy int ) by writing 1 to the | |
5690 | * status register. Link down indication is high-active-signal, | |
5691 | * so in this case we need to write the status to clear the XOR | |
5692 | */ | |
5693 | /* Read Latched signals */ | |
5694 | latch_status = REG_RD(sc, NIG_REG_LATCH_STATUS_0 + port * 8); | |
5695 | PMD_DRV_LOG(DEBUG, "latch_status = 0x%x", latch_status); | |
5696 | /* Handle only those with latched-signal=up. */ | |
5697 | if (exp_mi_int) | |
5698 | elink_bits_en(sc, | |
5699 | NIG_REG_STATUS_INTERRUPT_PORT0 | |
5700 | + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT); | |
5701 | else | |
5702 | elink_bits_dis(sc, | |
5703 | NIG_REG_STATUS_INTERRUPT_PORT0 | |
5704 | + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT); | |
5705 | ||
5706 | if (latch_status & 1) { | |
5707 | ||
5708 | /* For all latched-signal=up : Re-Arm Latch signals */ | |
5709 | REG_WR(sc, NIG_REG_LATCH_STATUS_0 + port * 8, | |
5710 | (latch_status & 0xfffe) | (latch_status & 1)); | |
5711 | } | |
5712 | /* For all latched-signal=up,Write original_signal to status */ | |
5713 | } | |
5714 | ||
5715 | static void elink_link_int_ack(struct elink_params *params, | |
5716 | struct elink_vars *vars, uint8_t is_10g_plus) | |
5717 | { | |
5718 | struct bnx2x_softc *sc = params->sc; | |
5719 | uint8_t port = params->port; | |
5720 | uint32_t mask; | |
5721 | /* First reset all status we assume only one line will be | |
5722 | * change at a time | |
5723 | */ | |
5724 | elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4, | |
5725 | (ELINK_NIG_STATUS_XGXS0_LINK10G | | |
5726 | ELINK_NIG_STATUS_XGXS0_LINK_STATUS | | |
5727 | ELINK_NIG_STATUS_SERDES0_LINK_STATUS)); | |
5728 | if (vars->phy_link_up) { | |
5729 | if (USES_WARPCORE(sc)) | |
5730 | mask = ELINK_NIG_STATUS_XGXS0_LINK_STATUS; | |
5731 | else { | |
5732 | if (is_10g_plus) | |
5733 | mask = ELINK_NIG_STATUS_XGXS0_LINK10G; | |
5734 | else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) { | |
5735 | /* Disable the link interrupt by writing 1 to | |
5736 | * the relevant lane in the status register | |
5737 | */ | |
5738 | uint32_t ser_lane = | |
5739 | ((params->lane_config & | |
5740 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> | |
5741 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
5742 | mask = ((1 << ser_lane) << | |
5743 | ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE); | |
5744 | } else | |
5745 | mask = ELINK_NIG_STATUS_SERDES0_LINK_STATUS; | |
5746 | } | |
5747 | PMD_DRV_LOG(DEBUG, "Ack link up interrupt with mask 0x%x", | |
5748 | mask); | |
5749 | elink_bits_en(sc, | |
5750 | NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4, mask); | |
5751 | } | |
5752 | } | |
5753 | ||
5754 | static elink_status_t elink_format_ver(uint32_t num, uint8_t * str, | |
5755 | uint16_t * len) | |
5756 | { | |
5757 | uint8_t *str_ptr = str; | |
5758 | uint32_t mask = 0xf0000000; | |
5759 | uint8_t shift = 8 * 4; | |
5760 | uint8_t digit; | |
5761 | uint8_t remove_leading_zeros = 1; | |
5762 | if (*len < 10) { | |
5763 | /* Need more than 10chars for this format */ | |
5764 | *str_ptr = '\0'; | |
5765 | (*len)--; | |
5766 | return ELINK_STATUS_ERROR; | |
5767 | } | |
5768 | while (shift > 0) { | |
5769 | ||
5770 | shift -= 4; | |
5771 | digit = ((num & mask) >> shift); | |
5772 | if (digit == 0 && remove_leading_zeros) { | |
5773 | mask = mask >> 4; | |
5774 | continue; | |
5775 | } else if (digit < 0xa) | |
5776 | *str_ptr = digit + '0'; | |
5777 | else | |
5778 | *str_ptr = digit - 0xa + 'a'; | |
5779 | remove_leading_zeros = 0; | |
5780 | str_ptr++; | |
5781 | (*len)--; | |
5782 | mask = mask >> 4; | |
5783 | if (shift == 4 * 4) { | |
5784 | *str_ptr = '.'; | |
5785 | str_ptr++; | |
5786 | (*len)--; | |
5787 | remove_leading_zeros = 1; | |
5788 | } | |
5789 | } | |
5790 | return ELINK_STATUS_OK; | |
5791 | } | |
5792 | ||
5793 | static elink_status_t elink_null_format_ver(__rte_unused uint32_t spirom_ver, | |
5794 | uint8_t * str, uint16_t * len) | |
5795 | { | |
5796 | str[0] = '\0'; | |
5797 | (*len)--; | |
5798 | return ELINK_STATUS_OK; | |
5799 | } | |
5800 | ||
5801 | static void elink_set_xgxs_loopback(struct elink_phy *phy, | |
5802 | struct elink_params *params) | |
5803 | { | |
5804 | uint8_t port = params->port; | |
5805 | struct bnx2x_softc *sc = params->sc; | |
5806 | ||
5807 | if (phy->req_line_speed != ELINK_SPEED_1000) { | |
5808 | uint32_t md_devad = 0; | |
5809 | ||
5810 | PMD_DRV_LOG(DEBUG, "XGXS 10G loopback enable"); | |
5811 | ||
5812 | if (!CHIP_IS_E3(sc)) { | |
5813 | /* Change the uni_phy_addr in the nig */ | |
5814 | md_devad = REG_RD(sc, (NIG_REG_XGXS0_CTRL_MD_DEVAD + | |
5815 | port * 0x18)); | |
5816 | ||
5817 | REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port * 0x18, | |
5818 | 0x5); | |
5819 | } | |
5820 | ||
5821 | elink_cl45_write(sc, phy, | |
5822 | 5, | |
5823 | (MDIO_REG_BANK_AER_BLOCK + | |
5824 | (MDIO_AER_BLOCK_AER_REG & 0xf)), 0x2800); | |
5825 | ||
5826 | elink_cl45_write(sc, phy, | |
5827 | 5, | |
5828 | (MDIO_REG_BANK_CL73_IEEEB0 + | |
5829 | (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), | |
5830 | 0x6041); | |
5831 | DELAY(1000 * 200); | |
5832 | /* Set aer mmd back */ | |
5833 | elink_set_aer_mmd(params, phy); | |
5834 | ||
5835 | if (!CHIP_IS_E3(sc)) { | |
5836 | /* And md_devad */ | |
5837 | REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port * 0x18, | |
5838 | md_devad); | |
5839 | } | |
5840 | } else { | |
5841 | uint16_t mii_ctrl; | |
5842 | PMD_DRV_LOG(DEBUG, "XGXS 1G loopback enable"); | |
5843 | elink_cl45_read(sc, phy, 5, | |
5844 | (MDIO_REG_BANK_COMBO_IEEE0 + | |
5845 | (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), | |
5846 | &mii_ctrl); | |
5847 | elink_cl45_write(sc, phy, 5, | |
5848 | (MDIO_REG_BANK_COMBO_IEEE0 + | |
5849 | (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), | |
5850 | mii_ctrl | | |
5851 | MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK); | |
5852 | } | |
5853 | } | |
5854 | ||
5855 | elink_status_t elink_set_led(struct elink_params *params, | |
5856 | struct elink_vars *vars, uint8_t mode, | |
5857 | uint32_t speed) | |
5858 | { | |
5859 | uint8_t port = params->port; | |
5860 | uint16_t hw_led_mode = params->hw_led_mode; | |
5861 | elink_status_t rc = ELINK_STATUS_OK; | |
5862 | uint8_t phy_idx; | |
5863 | uint32_t tmp; | |
5864 | uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
5865 | struct bnx2x_softc *sc = params->sc; | |
5866 | PMD_DRV_LOG(DEBUG, "elink_set_led: port %x, mode %d", port, mode); | |
5867 | PMD_DRV_LOG(DEBUG, "speed 0x%x, hw_led_mode 0x%x", speed, hw_led_mode); | |
5868 | /* In case */ | |
5869 | for (phy_idx = ELINK_EXT_PHY1; phy_idx < ELINK_MAX_PHYS; phy_idx++) { | |
5870 | if (params->phy[phy_idx].set_link_led) { | |
5871 | params->phy[phy_idx].set_link_led(¶ms->phy[phy_idx], | |
5872 | params, mode); | |
5873 | } | |
5874 | } | |
5875 | ||
5876 | switch (mode) { | |
5877 | case ELINK_LED_MODE_FRONT_PANEL_OFF: | |
5878 | case ELINK_LED_MODE_OFF: | |
5879 | REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 0); | |
5880 | REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, | |
5881 | SHARED_HW_CFG_LED_MAC1); | |
5882 | ||
5883 | tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED); | |
5884 | if (params->phy[ELINK_EXT_PHY1].type == | |
5885 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) | |
5886 | tmp &= ~(EMAC_LED_1000MB_OVERRIDE | | |
5887 | EMAC_LED_100MB_OVERRIDE | | |
5888 | EMAC_LED_10MB_OVERRIDE); | |
5889 | else | |
5890 | tmp |= EMAC_LED_OVERRIDE; | |
5891 | ||
5892 | elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, tmp); | |
5893 | break; | |
5894 | ||
5895 | case ELINK_LED_MODE_OPER: | |
5896 | /* For all other phys, OPER mode is same as ON, so in case | |
5897 | * link is down, do nothing | |
5898 | */ | |
5899 | if (!vars->link_up) | |
5900 | break; | |
5901 | case ELINK_LED_MODE_ON: | |
5902 | if (((params->phy[ELINK_EXT_PHY1].type == | |
5903 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727) || | |
5904 | (params->phy[ELINK_EXT_PHY1].type == | |
5905 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722)) && | |
5906 | CHIP_IS_E2(sc) && params->num_phys == 2) { | |
5907 | /* This is a work-around for E2+8727 Configurations */ | |
5908 | if (mode == ELINK_LED_MODE_ON || | |
5909 | speed == ELINK_SPEED_10000) { | |
5910 | REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0); | |
5911 | REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1); | |
5912 | ||
5913 | tmp = | |
5914 | elink_cb_reg_read(sc, | |
5915 | emac_base + | |
5916 | EMAC_REG_EMAC_LED); | |
5917 | elink_cb_reg_write(sc, | |
5918 | emac_base + | |
5919 | EMAC_REG_EMAC_LED, | |
5920 | (tmp | EMAC_LED_OVERRIDE)); | |
5921 | /* Return here without enabling traffic | |
5922 | * LED blink and setting rate in ON mode. | |
5923 | * In oper mode, enabling LED blink | |
5924 | * and setting rate is needed. | |
5925 | */ | |
5926 | if (mode == ELINK_LED_MODE_ON) | |
5927 | return rc; | |
5928 | } | |
5929 | } else if (ELINK_SINGLE_MEDIA_DIRECT(params)) { | |
5930 | /* This is a work-around for HW issue found when link | |
5931 | * is up in CL73 | |
5932 | */ | |
5933 | if ((!CHIP_IS_E3(sc)) || | |
5934 | (CHIP_IS_E3(sc) && mode == ELINK_LED_MODE_ON)) | |
5935 | REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1); | |
5936 | ||
5937 | if (CHIP_IS_E1x(sc) || | |
5938 | CHIP_IS_E2(sc) || (mode == ELINK_LED_MODE_ON)) | |
5939 | REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0); | |
5940 | else | |
5941 | REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, | |
5942 | hw_led_mode); | |
5943 | } else if ((params->phy[ELINK_EXT_PHY1].type == | |
5944 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) && | |
5945 | (mode == ELINK_LED_MODE_ON)) { | |
5946 | REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0); | |
5947 | tmp = | |
5948 | elink_cb_reg_read(sc, | |
5949 | emac_base + EMAC_REG_EMAC_LED); | |
5950 | elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, | |
5951 | tmp | EMAC_LED_OVERRIDE | | |
5952 | EMAC_LED_1000MB_OVERRIDE); | |
5953 | /* Break here; otherwise, it'll disable the | |
5954 | * intended override. | |
5955 | */ | |
5956 | break; | |
5957 | } else { | |
5958 | uint32_t nig_led_mode = ((params->hw_led_mode << | |
5959 | SHARED_HW_CFG_LED_MODE_SHIFT) | |
5960 | == | |
5961 | SHARED_HW_CFG_LED_EXTPHY2) | |
5962 | ? (SHARED_HW_CFG_LED_PHY1 >> | |
5963 | SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode; | |
5964 | REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, | |
5965 | nig_led_mode); | |
5966 | } | |
5967 | ||
5968 | REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port * 4, | |
5969 | 0); | |
5970 | /* Set blinking rate to ~15.9Hz */ | |
5971 | if (CHIP_IS_E3(sc)) | |
5972 | REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port * 4, | |
5973 | LED_BLINK_RATE_VAL_E3); | |
5974 | else | |
5975 | REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port * 4, | |
5976 | LED_BLINK_RATE_VAL_E1X_E2); | |
5977 | REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + port * 4, 1); | |
5978 | tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED); | |
5979 | elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, | |
5980 | (tmp & (~EMAC_LED_OVERRIDE))); | |
5981 | ||
5982 | break; | |
5983 | ||
5984 | default: | |
5985 | rc = ELINK_STATUS_ERROR; | |
5986 | PMD_DRV_LOG(DEBUG, "elink_set_led: Invalid led mode %d", mode); | |
5987 | break; | |
5988 | } | |
5989 | return rc; | |
5990 | ||
5991 | } | |
5992 | ||
5993 | static elink_status_t elink_link_initialize(struct elink_params *params, | |
5994 | struct elink_vars *vars) | |
5995 | { | |
5996 | elink_status_t rc = ELINK_STATUS_OK; | |
5997 | uint8_t phy_index, non_ext_phy; | |
5998 | struct bnx2x_softc *sc = params->sc; | |
5999 | /* In case of external phy existence, the line speed would be the | |
6000 | * line speed linked up by the external phy. In case it is direct | |
6001 | * only, then the line_speed during initialization will be | |
6002 | * equal to the req_line_speed | |
6003 | */ | |
6004 | vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed; | |
6005 | ||
6006 | /* Initialize the internal phy in case this is a direct board | |
6007 | * (no external phys), or this board has external phy which requires | |
6008 | * to first. | |
6009 | */ | |
6010 | if (!USES_WARPCORE(sc)) | |
6011 | elink_prepare_xgxs(¶ms->phy[ELINK_INT_PHY], params, vars); | |
6012 | /* init ext phy and enable link state int */ | |
6013 | non_ext_phy = (ELINK_SINGLE_MEDIA_DIRECT(params) || | |
6014 | (params->loopback_mode == ELINK_LOOPBACK_XGXS)); | |
6015 | ||
6016 | if (non_ext_phy || | |
6017 | (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) || | |
6018 | (params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) { | |
6019 | struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; | |
6020 | if (vars->line_speed == ELINK_SPEED_AUTO_NEG && | |
6021 | (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))) | |
6022 | elink_set_parallel_detection(phy, params); | |
6023 | if (params->phy[ELINK_INT_PHY].config_init) | |
6024 | params->phy[ELINK_INT_PHY].config_init(phy, | |
6025 | params, vars); | |
6026 | } | |
6027 | ||
6028 | /* Re-read this value in case it was changed inside config_init due to | |
6029 | * limitations of optic module | |
6030 | */ | |
6031 | vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed; | |
6032 | ||
6033 | /* Init external phy */ | |
6034 | if (non_ext_phy) { | |
6035 | if (params->phy[ELINK_INT_PHY].supported & | |
6036 | ELINK_SUPPORTED_FIBRE) | |
6037 | vars->link_status |= LINK_STATUS_SERDES_LINK; | |
6038 | } else { | |
6039 | for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; | |
6040 | phy_index++) { | |
6041 | /* No need to initialize second phy in case of first | |
6042 | * phy only selection. In case of second phy, we do | |
6043 | * need to initialize the first phy, since they are | |
6044 | * connected. | |
6045 | */ | |
6046 | if (params->phy[phy_index].supported & | |
6047 | ELINK_SUPPORTED_FIBRE) | |
6048 | vars->link_status |= LINK_STATUS_SERDES_LINK; | |
6049 | ||
6050 | if (phy_index == ELINK_EXT_PHY2 && | |
6051 | (elink_phy_selection(params) == | |
6052 | PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) { | |
6053 | PMD_DRV_LOG(DEBUG, | |
6054 | "Not initializing second phy"); | |
6055 | continue; | |
6056 | } | |
6057 | params->phy[phy_index].config_init(¶ms-> | |
6058 | phy[phy_index], | |
6059 | params, vars); | |
6060 | } | |
6061 | } | |
6062 | /* Reset the interrupt indication after phy was initialized */ | |
6063 | elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + | |
6064 | params->port * 4, | |
6065 | (ELINK_NIG_STATUS_XGXS0_LINK10G | | |
6066 | ELINK_NIG_STATUS_XGXS0_LINK_STATUS | | |
6067 | ELINK_NIG_STATUS_SERDES0_LINK_STATUS | | |
6068 | ELINK_NIG_MASK_MI_INT)); | |
6069 | return rc; | |
6070 | } | |
6071 | ||
6072 | static void elink_int_link_reset(__rte_unused struct elink_phy *phy, | |
6073 | struct elink_params *params) | |
6074 | { | |
6075 | /* Reset the SerDes/XGXS */ | |
6076 | REG_WR(params->sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, | |
6077 | (0x1ff << (params->port * 16))); | |
6078 | } | |
6079 | ||
6080 | static void elink_common_ext_link_reset(__rte_unused struct elink_phy *phy, | |
6081 | struct elink_params *params) | |
6082 | { | |
6083 | struct bnx2x_softc *sc = params->sc; | |
6084 | uint8_t gpio_port; | |
6085 | /* HW reset */ | |
6086 | if (CHIP_IS_E2(sc)) | |
6087 | gpio_port = SC_PATH(sc); | |
6088 | else | |
6089 | gpio_port = params->port; | |
6090 | elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1, | |
6091 | MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port); | |
6092 | elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, | |
6093 | MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port); | |
6094 | PMD_DRV_LOG(DEBUG, "reset external PHY"); | |
6095 | } | |
6096 | ||
6097 | static elink_status_t elink_update_link_down(struct elink_params *params, | |
6098 | struct elink_vars *vars) | |
6099 | { | |
6100 | struct bnx2x_softc *sc = params->sc; | |
6101 | uint8_t port = params->port; | |
6102 | ||
6103 | PMD_DRV_LOG(DEBUG, "Port %x: Link is down", port); | |
6104 | elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0); | |
6105 | vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; | |
6106 | /* Indicate no mac active */ | |
6107 | vars->mac_type = ELINK_MAC_TYPE_NONE; | |
6108 | ||
6109 | /* Update shared memory */ | |
6110 | vars->link_status &= ~ELINK_LINK_UPDATE_MASK; | |
6111 | vars->line_speed = 0; | |
6112 | elink_update_mng(params, vars->link_status); | |
6113 | ||
6114 | /* Activate nig drain */ | |
6115 | REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 1); | |
6116 | ||
6117 | /* Disable emac */ | |
6118 | if (!CHIP_IS_E3(sc)) | |
6119 | REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0); | |
6120 | ||
6121 | DELAY(1000 * 10); | |
6122 | /* Reset BigMac/Xmac */ | |
6123 | if (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc)) | |
6124 | elink_set_bmac_rx(sc, params->port, 0); | |
6125 | ||
6126 | if (CHIP_IS_E3(sc)) { | |
6127 | /* Prevent LPI Generation by chip */ | |
6128 | REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), | |
6129 | 0); | |
6130 | REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), | |
6131 | 0); | |
6132 | vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | | |
6133 | SHMEM_EEE_ACTIVE_BIT); | |
6134 | ||
6135 | elink_update_mng_eee(params, vars->eee_status); | |
6136 | elink_set_xmac_rxtx(params, 0); | |
6137 | elink_set_umac_rxtx(params, 0); | |
6138 | } | |
6139 | ||
6140 | return ELINK_STATUS_OK; | |
6141 | } | |
6142 | ||
6143 | static elink_status_t elink_update_link_up(struct elink_params *params, | |
6144 | struct elink_vars *vars, | |
6145 | uint8_t link_10g) | |
6146 | { | |
6147 | struct bnx2x_softc *sc = params->sc; | |
6148 | uint8_t phy_idx, port = params->port; | |
6149 | elink_status_t rc = ELINK_STATUS_OK; | |
6150 | ||
6151 | vars->link_status |= (LINK_STATUS_LINK_UP | | |
6152 | LINK_STATUS_PHYSICAL_LINK_FLAG); | |
6153 | vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; | |
6154 | ||
6155 | if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) | |
6156 | vars->link_status |= LINK_STATUS_TX_FLOW_CONTROL_ENABLED; | |
6157 | ||
6158 | if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) | |
6159 | vars->link_status |= LINK_STATUS_RX_FLOW_CONTROL_ENABLED; | |
6160 | if (USES_WARPCORE(sc)) { | |
6161 | if (link_10g) { | |
6162 | if (elink_xmac_enable(params, vars, 0) == | |
6163 | ELINK_STATUS_NO_LINK) { | |
6164 | PMD_DRV_LOG(DEBUG, "Found errors on XMAC"); | |
6165 | vars->link_up = 0; | |
6166 | vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; | |
6167 | vars->link_status &= ~LINK_STATUS_LINK_UP; | |
6168 | } | |
6169 | } else | |
6170 | elink_umac_enable(params, vars, 0); | |
6171 | elink_set_led(params, vars, | |
6172 | ELINK_LED_MODE_OPER, vars->line_speed); | |
6173 | ||
6174 | if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) && | |
6175 | (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) { | |
6176 | PMD_DRV_LOG(DEBUG, "Enabling LPI assertion"); | |
6177 | REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + | |
6178 | (params->port << 2), 1); | |
6179 | REG_WR(sc, MISC_REG_CPMU_LP_DR_ENABLE, 1); | |
6180 | REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 + | |
6181 | (params->port << 2), 0xfc20); | |
6182 | } | |
6183 | } | |
6184 | if ((CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))) { | |
6185 | if (link_10g) { | |
6186 | if (elink_bmac_enable(params, vars, 0, 1) == | |
6187 | ELINK_STATUS_NO_LINK) { | |
6188 | PMD_DRV_LOG(DEBUG, "Found errors on BMAC"); | |
6189 | vars->link_up = 0; | |
6190 | vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; | |
6191 | vars->link_status &= ~LINK_STATUS_LINK_UP; | |
6192 | } | |
6193 | ||
6194 | elink_set_led(params, vars, | |
6195 | ELINK_LED_MODE_OPER, ELINK_SPEED_10000); | |
6196 | } else { | |
6197 | rc = elink_emac_program(params, vars); | |
6198 | elink_emac_enable(params, vars, 0); | |
6199 | ||
6200 | /* AN complete? */ | |
6201 | if ((vars->link_status & | |
6202 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) | |
6203 | && (!(vars->phy_flags & PHY_SGMII_FLAG)) && | |
6204 | ELINK_SINGLE_MEDIA_DIRECT(params)) | |
6205 | elink_set_gmii_tx_driver(params); | |
6206 | } | |
6207 | } | |
6208 | ||
6209 | /* PBF - link up */ | |
6210 | if (CHIP_IS_E1x(sc)) | |
6211 | rc |= elink_pbf_update(params, vars->flow_ctrl, | |
6212 | vars->line_speed); | |
6213 | ||
6214 | /* Disable drain */ | |
6215 | REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 0); | |
6216 | ||
6217 | /* Update shared memory */ | |
6218 | elink_update_mng(params, vars->link_status); | |
6219 | elink_update_mng_eee(params, vars->eee_status); | |
6220 | /* Check remote fault */ | |
6221 | for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) { | |
6222 | if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) { | |
6223 | elink_check_half_open_conn(params, vars, 0); | |
6224 | break; | |
6225 | } | |
6226 | } | |
6227 | DELAY(1000 * 20); | |
6228 | return rc; | |
6229 | } | |
6230 | ||
6231 | /* The elink_link_update function should be called upon link | |
6232 | * interrupt. | |
6233 | * Link is considered up as follows: | |
6234 | * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs | |
6235 | * to be up | |
6236 | * - SINGLE_MEDIA - The link between the 577xx and the external | |
6237 | * phy (XGXS) need to up as well as the external link of the | |
6238 | * phy (PHY_EXT1) | |
6239 | * - DUAL_MEDIA - The link between the 577xx and the first | |
6240 | * external phy needs to be up, and at least one of the 2 | |
6241 | * external phy link must be up. | |
6242 | */ | |
6243 | elink_status_t elink_link_update(struct elink_params * params, | |
6244 | struct elink_vars * vars) | |
6245 | { | |
6246 | struct bnx2x_softc *sc = params->sc; | |
6247 | struct elink_vars phy_vars[ELINK_MAX_PHYS]; | |
6248 | uint8_t port = params->port; | |
6249 | uint8_t link_10g_plus, phy_index; | |
6250 | uint8_t ext_phy_link_up = 0, cur_link_up; | |
6251 | elink_status_t rc = ELINK_STATUS_OK; | |
6252 | __rte_unused uint8_t is_mi_int = 0; | |
6253 | uint16_t ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; | |
6254 | uint8_t active_external_phy = ELINK_INT_PHY; | |
6255 | vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; | |
6256 | vars->link_status &= ~ELINK_LINK_UPDATE_MASK; | |
6257 | for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; | |
6258 | phy_index++) { | |
6259 | phy_vars[phy_index].flow_ctrl = 0; | |
6260 | phy_vars[phy_index].link_status = ETH_LINK_DOWN; | |
6261 | phy_vars[phy_index].line_speed = 0; | |
6262 | phy_vars[phy_index].duplex = DUPLEX_FULL; | |
6263 | phy_vars[phy_index].phy_link_up = 0; | |
6264 | phy_vars[phy_index].link_up = 0; | |
6265 | phy_vars[phy_index].fault_detected = 0; | |
6266 | /* different consideration, since vars holds inner state */ | |
6267 | phy_vars[phy_index].eee_status = vars->eee_status; | |
6268 | } | |
6269 | ||
6270 | if (USES_WARPCORE(sc)) | |
6271 | elink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]); | |
6272 | ||
6273 | PMD_DRV_LOG(DEBUG, "port %x, XGXS?%x, int_status 0x%x", | |
6274 | port, (vars->phy_flags & PHY_XGXS_FLAG), | |
6275 | REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4)); | |
6276 | ||
6277 | is_mi_int = (uint8_t) (REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + | |
6278 | port * 0x18) > 0); | |
6279 | PMD_DRV_LOG(DEBUG, "int_mask 0x%x MI_INT %x, SERDES_LINK %x", | |
6280 | REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4), | |
6281 | is_mi_int, | |
6282 | REG_RD(sc, | |
6283 | NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c)); | |
6284 | ||
6285 | PMD_DRV_LOG(DEBUG, " 10G %x, XGXS_LINK %x", | |
6286 | REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68), | |
6287 | REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68)); | |
6288 | ||
6289 | /* Disable emac */ | |
6290 | if (!CHIP_IS_E3(sc)) | |
6291 | REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0); | |
6292 | ||
6293 | /* Step 1: | |
6294 | * Check external link change only for external phys, and apply | |
6295 | * priority selection between them in case the link on both phys | |
6296 | * is up. Note that instead of the common vars, a temporary | |
6297 | * vars argument is used since each phy may have different link/ | |
6298 | * speed/duplex result | |
6299 | */ | |
6300 | for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; | |
6301 | phy_index++) { | |
6302 | struct elink_phy *phy = ¶ms->phy[phy_index]; | |
6303 | if (!phy->read_status) | |
6304 | continue; | |
6305 | /* Read link status and params of this ext phy */ | |
6306 | cur_link_up = phy->read_status(phy, params, | |
6307 | &phy_vars[phy_index]); | |
6308 | if (cur_link_up) { | |
6309 | PMD_DRV_LOG(DEBUG, "phy in index %d link is up", | |
6310 | phy_index); | |
6311 | } else { | |
6312 | PMD_DRV_LOG(DEBUG, "phy in index %d link is down", | |
6313 | phy_index); | |
6314 | continue; | |
6315 | } | |
6316 | ||
6317 | if (!ext_phy_link_up) { | |
6318 | ext_phy_link_up = 1; | |
6319 | active_external_phy = phy_index; | |
6320 | } else { | |
6321 | switch (elink_phy_selection(params)) { | |
6322 | case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: | |
6323 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
6324 | /* In this option, the first PHY makes sure to pass the | |
6325 | * traffic through itself only. | |
6326 | * Its not clear how to reset the link on the second phy | |
6327 | */ | |
6328 | active_external_phy = ELINK_EXT_PHY1; | |
6329 | break; | |
6330 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
6331 | /* In this option, the first PHY makes sure to pass the | |
6332 | * traffic through the second PHY. | |
6333 | */ | |
6334 | active_external_phy = ELINK_EXT_PHY2; | |
6335 | break; | |
6336 | default: | |
6337 | /* Link indication on both PHYs with the following cases | |
6338 | * is invalid: | |
6339 | * - FIRST_PHY means that second phy wasn't initialized, | |
6340 | * hence its link is expected to be down | |
6341 | * - SECOND_PHY means that first phy should not be able | |
6342 | * to link up by itself (using configuration) | |
6343 | * - DEFAULT should be overriden during initialiazation | |
6344 | */ | |
6345 | PMD_DRV_LOG(DEBUG, "Invalid link indication" | |
6346 | "mpc=0x%x. DISABLING LINK !!!", | |
6347 | params->multi_phy_config); | |
6348 | ext_phy_link_up = 0; | |
6349 | break; | |
6350 | } | |
6351 | } | |
6352 | } | |
6353 | prev_line_speed = vars->line_speed; | |
6354 | /* Step 2: | |
6355 | * Read the status of the internal phy. In case of | |
6356 | * DIRECT_SINGLE_MEDIA board, this link is the external link, | |
6357 | * otherwise this is the link between the 577xx and the first | |
6358 | * external phy | |
6359 | */ | |
6360 | if (params->phy[ELINK_INT_PHY].read_status) | |
6361 | params->phy[ELINK_INT_PHY].read_status(¶ms-> | |
6362 | phy[ELINK_INT_PHY], | |
6363 | params, vars); | |
6364 | /* The INT_PHY flow control reside in the vars. This include the | |
6365 | * case where the speed or flow control are not set to AUTO. | |
6366 | * Otherwise, the active external phy flow control result is set | |
6367 | * to the vars. The ext_phy_line_speed is needed to check if the | |
6368 | * speed is different between the internal phy and external phy. | |
6369 | * This case may be result of intermediate link speed change. | |
6370 | */ | |
6371 | if (active_external_phy > ELINK_INT_PHY) { | |
6372 | vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; | |
6373 | /* Link speed is taken from the XGXS. AN and FC result from | |
6374 | * the external phy. | |
6375 | */ | |
6376 | vars->link_status |= phy_vars[active_external_phy].link_status; | |
6377 | ||
6378 | /* if active_external_phy is first PHY and link is up - disable | |
6379 | * disable TX on second external PHY | |
6380 | */ | |
6381 | if (active_external_phy == ELINK_EXT_PHY1) { | |
6382 | if (params->phy[ELINK_EXT_PHY2].phy_specific_func) { | |
6383 | PMD_DRV_LOG(DEBUG, "Disabling TX on EXT_PHY2"); | |
6384 | params->phy[ELINK_EXT_PHY2]. | |
6385 | phy_specific_func(¶ms-> | |
6386 | phy[ELINK_EXT_PHY2], | |
6387 | params, ELINK_DISABLE_TX); | |
6388 | } | |
6389 | } | |
6390 | ||
6391 | ext_phy_line_speed = phy_vars[active_external_phy].line_speed; | |
6392 | vars->duplex = phy_vars[active_external_phy].duplex; | |
6393 | if (params->phy[active_external_phy].supported & | |
6394 | ELINK_SUPPORTED_FIBRE) | |
6395 | vars->link_status |= LINK_STATUS_SERDES_LINK; | |
6396 | else | |
6397 | vars->link_status &= ~LINK_STATUS_SERDES_LINK; | |
6398 | ||
6399 | vars->eee_status = phy_vars[active_external_phy].eee_status; | |
6400 | ||
6401 | PMD_DRV_LOG(DEBUG, "Active external phy selected: %x", | |
6402 | active_external_phy); | |
6403 | } | |
6404 | ||
6405 | for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; | |
6406 | phy_index++) { | |
6407 | if (params->phy[phy_index].flags & | |
6408 | ELINK_FLAGS_REARM_LATCH_SIGNAL) { | |
6409 | elink_rearm_latch_signal(sc, port, | |
6410 | phy_index == | |
6411 | active_external_phy); | |
6412 | break; | |
6413 | } | |
6414 | } | |
6415 | PMD_DRV_LOG(DEBUG, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," | |
6416 | " ext_phy_line_speed = %d", vars->flow_ctrl, | |
6417 | vars->link_status, ext_phy_line_speed); | |
6418 | /* Upon link speed change set the NIG into drain mode. Comes to | |
6419 | * deals with possible FIFO glitch due to clk change when speed | |
6420 | * is decreased without link down indicator | |
6421 | */ | |
6422 | ||
6423 | if (vars->phy_link_up) { | |
6424 | if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up && | |
6425 | (ext_phy_line_speed != vars->line_speed)) { | |
6426 | PMD_DRV_LOG(DEBUG, "Internal link speed %d is" | |
6427 | " different than the external" | |
6428 | " link speed %d", vars->line_speed, | |
6429 | ext_phy_line_speed); | |
6430 | vars->phy_link_up = 0; | |
6431 | } else if (prev_line_speed != vars->line_speed) { | |
6432 | REG_WR(sc, | |
6433 | NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, | |
6434 | 0); | |
6435 | DELAY(1000 * 1); | |
6436 | } | |
6437 | } | |
6438 | ||
6439 | /* Anything 10 and over uses the bmac */ | |
6440 | link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000); | |
6441 | ||
6442 | elink_link_int_ack(params, vars, link_10g_plus); | |
6443 | ||
6444 | /* In case external phy link is up, and internal link is down | |
6445 | * (not initialized yet probably after link initialization, it | |
6446 | * needs to be initialized. | |
6447 | * Note that after link down-up as result of cable plug, the xgxs | |
6448 | * link would probably become up again without the need | |
6449 | * initialize it | |
6450 | */ | |
6451 | if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) { | |
6452 | PMD_DRV_LOG(DEBUG, "ext_phy_link_up = %d, int_link_up = %d," | |
6453 | " init_preceding = %d", ext_phy_link_up, | |
6454 | vars->phy_link_up, | |
6455 | params->phy[ELINK_EXT_PHY1].flags & | |
6456 | ELINK_FLAGS_INIT_XGXS_FIRST); | |
6457 | if (!(params->phy[ELINK_EXT_PHY1].flags & | |
6458 | ELINK_FLAGS_INIT_XGXS_FIRST) | |
6459 | && ext_phy_link_up && !vars->phy_link_up) { | |
6460 | vars->line_speed = ext_phy_line_speed; | |
6461 | if (vars->line_speed < ELINK_SPEED_1000) | |
6462 | vars->phy_flags |= PHY_SGMII_FLAG; | |
6463 | else | |
6464 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
6465 | ||
6466 | if (params->phy[ELINK_INT_PHY].config_init) | |
6467 | params->phy[ELINK_INT_PHY].config_init(¶ms-> | |
6468 | phy | |
6469 | [ELINK_INT_PHY], | |
6470 | params, | |
6471 | vars); | |
6472 | } | |
6473 | } | |
6474 | /* Link is up only if both local phy and external phy (in case of | |
6475 | * non-direct board) are up and no fault detected on active PHY. | |
6476 | */ | |
6477 | vars->link_up = (vars->phy_link_up && | |
6478 | (ext_phy_link_up || | |
6479 | ELINK_SINGLE_MEDIA_DIRECT(params)) && | |
6480 | (phy_vars[active_external_phy].fault_detected == 0)); | |
6481 | ||
6482 | /* Update the PFC configuration in case it was changed */ | |
6483 | if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) | |
6484 | vars->link_status |= LINK_STATUS_PFC_ENABLED; | |
6485 | else | |
6486 | vars->link_status &= ~LINK_STATUS_PFC_ENABLED; | |
6487 | ||
6488 | if (vars->link_up) | |
6489 | rc = elink_update_link_up(params, vars, link_10g_plus); | |
6490 | else | |
6491 | rc = elink_update_link_down(params, vars); | |
6492 | ||
6493 | /* Update MCP link status was changed */ | |
6494 | if (params-> | |
6495 | feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX) | |
6496 | elink_cb_fw_command(sc, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); | |
6497 | ||
6498 | return rc; | |
6499 | } | |
6500 | ||
6501 | /*****************************************************************************/ | |
6502 | /* External Phy section */ | |
6503 | /*****************************************************************************/ | |
6504 | static void elink_ext_phy_hw_reset(struct bnx2x_softc *sc, uint8_t port) | |
6505 | { | |
6506 | elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1, | |
6507 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); | |
6508 | DELAY(1000 * 1); | |
6509 | elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1, | |
6510 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); | |
6511 | } | |
6512 | ||
6513 | static void elink_save_spirom_version(struct bnx2x_softc *sc, | |
6514 | __rte_unused uint8_t port, | |
6515 | uint32_t spirom_ver, uint32_t ver_addr) | |
6516 | { | |
6517 | PMD_DRV_LOG(DEBUG, "FW version 0x%x:0x%x for port %d", | |
6518 | (uint16_t) (spirom_ver >> 16), (uint16_t) spirom_ver, port); | |
6519 | ||
6520 | if (ver_addr) | |
6521 | REG_WR(sc, ver_addr, spirom_ver); | |
6522 | } | |
6523 | ||
6524 | static void elink_save_bnx2x_spirom_ver(struct bnx2x_softc *sc, | |
6525 | struct elink_phy *phy, uint8_t port) | |
6526 | { | |
6527 | uint16_t fw_ver1, fw_ver2; | |
6528 | ||
6529 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, | |
6530 | MDIO_PMA_REG_ROM_VER1, &fw_ver1); | |
6531 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, | |
6532 | MDIO_PMA_REG_ROM_VER2, &fw_ver2); | |
6533 | elink_save_spirom_version(sc, port, | |
6534 | (uint32_t) (fw_ver1 << 16 | fw_ver2), | |
6535 | phy->ver_addr); | |
6536 | } | |
6537 | ||
6538 | static void elink_ext_phy_10G_an_resolve(struct bnx2x_softc *sc, | |
6539 | struct elink_phy *phy, | |
6540 | struct elink_vars *vars) | |
6541 | { | |
6542 | uint16_t val; | |
6543 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val); | |
6544 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val); | |
6545 | if (val & (1 << 5)) | |
6546 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
6547 | if ((val & (1 << 0)) == 0) | |
6548 | vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; | |
6549 | } | |
6550 | ||
6551 | /******************************************************************/ | |
6552 | /* common BNX2X8073/BNX2X8727 PHY SECTION */ | |
6553 | /******************************************************************/ | |
6554 | static void elink_8073_resolve_fc(struct elink_phy *phy, | |
6555 | struct elink_params *params, | |
6556 | struct elink_vars *vars) | |
6557 | { | |
6558 | struct bnx2x_softc *sc = params->sc; | |
6559 | if (phy->req_line_speed == ELINK_SPEED_10 || | |
6560 | phy->req_line_speed == ELINK_SPEED_100) { | |
6561 | vars->flow_ctrl = phy->req_flow_ctrl; | |
6562 | return; | |
6563 | } | |
6564 | ||
6565 | if (elink_ext_phy_resolve_fc(phy, params, vars) && | |
6566 | (vars->flow_ctrl == ELINK_FLOW_CTRL_NONE)) { | |
6567 | uint16_t pause_result; | |
6568 | uint16_t ld_pause; /* local */ | |
6569 | uint16_t lp_pause; /* link partner */ | |
6570 | elink_cl45_read(sc, phy, | |
6571 | MDIO_AN_DEVAD, | |
6572 | MDIO_AN_REG_CL37_FC_LD, &ld_pause); | |
6573 | ||
6574 | elink_cl45_read(sc, phy, | |
6575 | MDIO_AN_DEVAD, | |
6576 | MDIO_AN_REG_CL37_FC_LP, &lp_pause); | |
6577 | pause_result = (ld_pause & | |
6578 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5; | |
6579 | pause_result |= (lp_pause & | |
6580 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; | |
6581 | ||
6582 | elink_pause_resolve(vars, pause_result); | |
6583 | PMD_DRV_LOG(DEBUG, "Ext PHY CL37 pause result 0x%x", | |
6584 | pause_result); | |
6585 | } | |
6586 | } | |
6587 | ||
6588 | static elink_status_t elink_8073_8727_external_rom_boot(struct bnx2x_softc *sc, | |
6589 | struct elink_phy *phy, | |
6590 | uint8_t port) | |
6591 | { | |
6592 | uint32_t count = 0; | |
6593 | uint16_t fw_ver1 = 0, fw_msgout; | |
6594 | elink_status_t rc = ELINK_STATUS_OK; | |
6595 | ||
6596 | /* Boot port from external ROM */ | |
6597 | /* EDC grst */ | |
6598 | elink_cl45_write(sc, phy, | |
6599 | MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); | |
6600 | ||
6601 | /* Ucode reboot and rst */ | |
6602 | elink_cl45_write(sc, phy, | |
6603 | MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x008c); | |
6604 | ||
6605 | elink_cl45_write(sc, phy, | |
6606 | MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001); | |
6607 | ||
6608 | /* Reset internal microprocessor */ | |
6609 | elink_cl45_write(sc, phy, | |
6610 | MDIO_PMA_DEVAD, | |
6611 | MDIO_PMA_REG_GEN_CTRL, | |
6612 | MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); | |
6613 | ||
6614 | /* Release srst bit */ | |
6615 | elink_cl45_write(sc, phy, | |
6616 | MDIO_PMA_DEVAD, | |
6617 | MDIO_PMA_REG_GEN_CTRL, | |
6618 | MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); | |
6619 | ||
6620 | /* Delay 100ms per the PHY specifications */ | |
6621 | DELAY(1000 * 100); | |
6622 | ||
6623 | /* 8073 sometimes taking longer to download */ | |
6624 | do { | |
6625 | count++; | |
6626 | if (count > 300) { | |
6627 | PMD_DRV_LOG(DEBUG, | |
6628 | "elink_8073_8727_external_rom_boot port %x:" | |
6629 | "Download failed. fw version = 0x%x", | |
6630 | port, fw_ver1); | |
6631 | rc = ELINK_STATUS_ERROR; | |
6632 | break; | |
6633 | } | |
6634 | ||
6635 | elink_cl45_read(sc, phy, | |
6636 | MDIO_PMA_DEVAD, | |
6637 | MDIO_PMA_REG_ROM_VER1, &fw_ver1); | |
6638 | elink_cl45_read(sc, phy, | |
6639 | MDIO_PMA_DEVAD, | |
6640 | MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); | |
6641 | ||
6642 | DELAY(1000 * 1); | |
6643 | } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || | |
6644 | ((fw_msgout & 0xff) != 0x03 && (phy->type == | |
6645 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073))); | |
6646 | ||
6647 | /* Clear ser_boot_ctl bit */ | |
6648 | elink_cl45_write(sc, phy, | |
6649 | MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000); | |
6650 | elink_save_bnx2x_spirom_ver(sc, phy, port); | |
6651 | ||
6652 | PMD_DRV_LOG(DEBUG, | |
6653 | "elink_8073_8727_external_rom_boot port %x:" | |
6654 | "Download complete. fw version = 0x%x", port, fw_ver1); | |
6655 | ||
6656 | return rc; | |
6657 | } | |
6658 | ||
6659 | /******************************************************************/ | |
6660 | /* BNX2X8073 PHY SECTION */ | |
6661 | /******************************************************************/ | |
6662 | static elink_status_t elink_8073_is_snr_needed(struct bnx2x_softc *sc, | |
6663 | struct elink_phy *phy) | |
6664 | { | |
6665 | /* This is only required for 8073A1, version 102 only */ | |
6666 | uint16_t val; | |
6667 | ||
6668 | /* Read 8073 HW revision */ | |
6669 | elink_cl45_read(sc, phy, | |
6670 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val); | |
6671 | ||
6672 | if (val != 1) { | |
6673 | /* No need to workaround in 8073 A1 */ | |
6674 | return ELINK_STATUS_OK; | |
6675 | } | |
6676 | ||
6677 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &val); | |
6678 | ||
6679 | /* SNR should be applied only for version 0x102 */ | |
6680 | if (val != 0x102) | |
6681 | return ELINK_STATUS_OK; | |
6682 | ||
6683 | return ELINK_STATUS_ERROR; | |
6684 | } | |
6685 | ||
6686 | static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc, | |
6687 | struct elink_phy *phy) | |
6688 | { | |
6689 | uint16_t val, cnt, cnt1; | |
6690 | ||
6691 | elink_cl45_read(sc, phy, | |
6692 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val); | |
6693 | ||
6694 | if (val > 0) { | |
6695 | /* No need to workaround in 8073 A1 */ | |
6696 | return ELINK_STATUS_OK; | |
6697 | } | |
6698 | /* XAUI workaround in 8073 A0: */ | |
6699 | ||
6700 | /* After loading the boot ROM and restarting Autoneg, poll | |
6701 | * Dev1, Reg $C820: | |
6702 | */ | |
6703 | ||
6704 | for (cnt = 0; cnt < 1000; cnt++) { | |
6705 | elink_cl45_read(sc, phy, | |
6706 | MDIO_PMA_DEVAD, | |
6707 | MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &val); | |
6708 | /* If bit [14] = 0 or bit [13] = 0, continue on with | |
6709 | * system initialization (XAUI work-around not required, as | |
6710 | * these bits indicate 2.5G or 1G link up). | |
6711 | */ | |
6712 | if (!(val & (1 << 14)) || !(val & (1 << 13))) { | |
6713 | PMD_DRV_LOG(DEBUG, "XAUI work-around not required"); | |
6714 | return ELINK_STATUS_OK; | |
6715 | } else if (!(val & (1 << 15))) { | |
6716 | PMD_DRV_LOG(DEBUG, "bit 15 went off"); | |
6717 | /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's | |
6718 | * MSB (bit15) goes to 1 (indicating that the XAUI | |
6719 | * workaround has completed), then continue on with | |
6720 | * system initialization. | |
6721 | */ | |
6722 | for (cnt1 = 0; cnt1 < 1000; cnt1++) { | |
6723 | elink_cl45_read(sc, phy, | |
6724 | MDIO_PMA_DEVAD, | |
6725 | MDIO_PMA_REG_8073_XAUI_WA, | |
6726 | &val); | |
6727 | if (val & (1 << 15)) { | |
6728 | PMD_DRV_LOG(DEBUG, | |
6729 | "XAUI workaround has completed"); | |
6730 | return ELINK_STATUS_OK; | |
6731 | } | |
6732 | DELAY(1000 * 3); | |
6733 | } | |
6734 | break; | |
6735 | } | |
6736 | DELAY(1000 * 3); | |
6737 | } | |
6738 | PMD_DRV_LOG(DEBUG, "Warning: XAUI work-around timeout !!!"); | |
6739 | return ELINK_STATUS_ERROR; | |
6740 | } | |
6741 | ||
6742 | static void elink_807x_force_10G(struct bnx2x_softc *sc, struct elink_phy *phy) | |
6743 | { | |
6744 | /* Force KR or KX */ | |
6745 | elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); | |
6746 | elink_cl45_write(sc, phy, | |
6747 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); | |
6748 | elink_cl45_write(sc, phy, | |
6749 | MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0000); | |
6750 | elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); | |
6751 | } | |
6752 | ||
6753 | static void elink_8073_set_pause_cl37(struct elink_params *params, | |
6754 | struct elink_phy *phy, | |
6755 | struct elink_vars *vars) | |
6756 | { | |
6757 | uint16_t cl37_val; | |
6758 | struct bnx2x_softc *sc = params->sc; | |
6759 | elink_cl45_read(sc, phy, | |
6760 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val); | |
6761 | ||
6762 | cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
6763 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ | |
6764 | elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); | |
6765 | if ((vars->ieee_fc & | |
6766 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == | |
6767 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { | |
6768 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; | |
6769 | } | |
6770 | if ((vars->ieee_fc & | |
6771 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == | |
6772 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { | |
6773 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | |
6774 | } | |
6775 | if ((vars->ieee_fc & | |
6776 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == | |
6777 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { | |
6778 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
6779 | } | |
6780 | PMD_DRV_LOG(DEBUG, "Ext phy AN advertize cl37 0x%x", cl37_val); | |
6781 | ||
6782 | elink_cl45_write(sc, phy, | |
6783 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); | |
6784 | DELAY(1000 * 500); | |
6785 | } | |
6786 | ||
6787 | static void elink_8073_specific_func(struct elink_phy *phy, | |
6788 | struct elink_params *params, | |
6789 | uint32_t action) | |
6790 | { | |
6791 | struct bnx2x_softc *sc = params->sc; | |
6792 | switch (action) { | |
6793 | case ELINK_PHY_INIT: | |
6794 | /* Enable LASI */ | |
6795 | elink_cl45_write(sc, phy, | |
6796 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, | |
6797 | (1 << 2)); | |
6798 | elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, | |
6799 | 0x0004); | |
6800 | break; | |
6801 | } | |
6802 | } | |
6803 | ||
6804 | static elink_status_t elink_8073_config_init(struct elink_phy *phy, | |
6805 | struct elink_params *params, | |
6806 | struct elink_vars *vars) | |
6807 | { | |
6808 | struct bnx2x_softc *sc = params->sc; | |
6809 | uint16_t val = 0, tmp1; | |
6810 | uint8_t gpio_port; | |
6811 | PMD_DRV_LOG(DEBUG, "Init 8073"); | |
6812 | ||
6813 | if (CHIP_IS_E2(sc)) | |
6814 | gpio_port = SC_PATH(sc); | |
6815 | else | |
6816 | gpio_port = params->port; | |
6817 | /* Restore normal power mode */ | |
6818 | elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, | |
6819 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); | |
6820 | ||
6821 | elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1, | |
6822 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); | |
6823 | ||
6824 | elink_8073_specific_func(phy, params, ELINK_PHY_INIT); | |
6825 | elink_8073_set_pause_cl37(params, phy, vars); | |
6826 | ||
6827 | elink_cl45_read(sc, phy, | |
6828 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); | |
6829 | ||
6830 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); | |
6831 | ||
6832 | PMD_DRV_LOG(DEBUG, "Before rom RX_ALARM(port1): 0x%x", tmp1); | |
6833 | ||
6834 | /* Swap polarity if required - Must be done only in non-1G mode */ | |
6835 | if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { | |
6836 | /* Configure the 8073 to swap _P and _N of the KR lines */ | |
6837 | PMD_DRV_LOG(DEBUG, "Swapping polarity for the 8073"); | |
6838 | /* 10G Rx/Tx and 1G Tx signal polarity swap */ | |
6839 | elink_cl45_read(sc, phy, | |
6840 | MDIO_PMA_DEVAD, | |
6841 | MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val); | |
6842 | elink_cl45_write(sc, phy, | |
6843 | MDIO_PMA_DEVAD, | |
6844 | MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, | |
6845 | (val | (3 << 9))); | |
6846 | } | |
6847 | ||
6848 | /* Enable CL37 BAM */ | |
6849 | if (REG_RD(sc, params->shmem_base + | |
6850 | offsetof(struct shmem_region, | |
6851 | dev_info.port_hw_config[params->port]. | |
6852 | default_cfg)) & | |
6853 | PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { | |
6854 | ||
6855 | elink_cl45_read(sc, phy, | |
6856 | MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, &val); | |
6857 | elink_cl45_write(sc, phy, | |
6858 | MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, val | 1); | |
6859 | PMD_DRV_LOG(DEBUG, "Enable CL37 BAM on KR"); | |
6860 | } | |
6861 | if (params->loopback_mode == ELINK_LOOPBACK_EXT) { | |
6862 | elink_807x_force_10G(sc, phy); | |
6863 | PMD_DRV_LOG(DEBUG, "Forced speed 10G on 807X"); | |
6864 | return ELINK_STATUS_OK; | |
6865 | } else { | |
6866 | elink_cl45_write(sc, phy, | |
6867 | MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0002); | |
6868 | } | |
6869 | if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) { | |
6870 | if (phy->req_line_speed == ELINK_SPEED_10000) { | |
6871 | val = (1 << 7); | |
6872 | } else if (phy->req_line_speed == ELINK_SPEED_2500) { | |
6873 | val = (1 << 5); | |
6874 | /* Note that 2.5G works only when used with 1G | |
6875 | * advertisement | |
6876 | */ | |
6877 | } else | |
6878 | val = (1 << 5); | |
6879 | } else { | |
6880 | val = 0; | |
6881 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
6882 | val |= (1 << 7); | |
6883 | ||
6884 | /* Note that 2.5G works only when used with 1G advertisement */ | |
6885 | if (phy->speed_cap_mask & | |
6886 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | | |
6887 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) | |
6888 | val |= (1 << 5); | |
6889 | PMD_DRV_LOG(DEBUG, "807x autoneg val = 0x%x", val); | |
6890 | } | |
6891 | ||
6892 | elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); | |
6893 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); | |
6894 | ||
6895 | if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && | |
6896 | (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)) || | |
6897 | (phy->req_line_speed == ELINK_SPEED_2500)) { | |
6898 | uint16_t phy_ver; | |
6899 | /* Allow 2.5G for A1 and above */ | |
6900 | elink_cl45_read(sc, phy, | |
6901 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, | |
6902 | &phy_ver); | |
6903 | PMD_DRV_LOG(DEBUG, "Add 2.5G"); | |
6904 | if (phy_ver > 0) | |
6905 | tmp1 |= 1; | |
6906 | else | |
6907 | tmp1 &= 0xfffe; | |
6908 | } else { | |
6909 | PMD_DRV_LOG(DEBUG, "Disable 2.5G"); | |
6910 | tmp1 &= 0xfffe; | |
6911 | } | |
6912 | ||
6913 | elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); | |
6914 | /* Add support for CL37 (passive mode) II */ | |
6915 | ||
6916 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); | |
6917 | elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, | |
6918 | (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? | |
6919 | 0x20 : 0x40))); | |
6920 | ||
6921 | /* Add support for CL37 (passive mode) III */ | |
6922 | elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
6923 | ||
6924 | /* The SNR will improve about 2db by changing BW and FEE main | |
6925 | * tap. Rest commands are executed after link is up | |
6926 | * Change FFE main cursor to 5 in EDC register | |
6927 | */ | |
6928 | if (elink_8073_is_snr_needed(sc, phy)) | |
6929 | elink_cl45_write(sc, phy, | |
6930 | MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN, | |
6931 | 0xFB0C); | |
6932 | ||
6933 | /* Enable FEC (Forware Error Correction) Request in the AN */ | |
6934 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); | |
6935 | tmp1 |= (1 << 15); | |
6936 | elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); | |
6937 | ||
6938 | elink_ext_phy_set_pause(params, phy, vars); | |
6939 | ||
6940 | /* Restart autoneg */ | |
6941 | DELAY(1000 * 500); | |
6942 | elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
6943 | PMD_DRV_LOG(DEBUG, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x", | |
6944 | ((val & (1 << 5)) > 0), ((val & (1 << 7)) > 0)); | |
6945 | return ELINK_STATUS_OK; | |
6946 | } | |
6947 | ||
6948 | static uint8_t elink_8073_read_status(struct elink_phy *phy, | |
6949 | struct elink_params *params, | |
6950 | struct elink_vars *vars) | |
6951 | { | |
6952 | struct bnx2x_softc *sc = params->sc; | |
6953 | uint8_t link_up = 0; | |
6954 | uint16_t val1, val2; | |
6955 | uint16_t link_status = 0; | |
6956 | uint16_t an1000_status = 0; | |
6957 | ||
6958 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); | |
6959 | ||
6960 | PMD_DRV_LOG(DEBUG, "8703 LASI status 0x%x", val1); | |
6961 | ||
6962 | /* Clear the interrupt LASI status register */ | |
6963 | elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); | |
6964 | elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); | |
6965 | PMD_DRV_LOG(DEBUG, "807x PCS status 0x%x->0x%x", val2, val1); | |
6966 | /* Clear MSG-OUT */ | |
6967 | elink_cl45_read(sc, phy, | |
6968 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); | |
6969 | ||
6970 | /* Check the LASI */ | |
6971 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); | |
6972 | ||
6973 | PMD_DRV_LOG(DEBUG, "KR 0x9003 0x%x", val2); | |
6974 | ||
6975 | /* Check the link status */ | |
6976 | elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); | |
6977 | PMD_DRV_LOG(DEBUG, "KR PCS status 0x%x", val2); | |
6978 | ||
6979 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
6980 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
6981 | link_up = ((val1 & 4) == 4); | |
6982 | PMD_DRV_LOG(DEBUG, "PMA_REG_STATUS=0x%x", val1); | |
6983 | ||
6984 | if (link_up && ((phy->req_line_speed != ELINK_SPEED_10000))) { | |
6985 | if (elink_8073_xaui_wa(sc, phy) != 0) | |
6986 | return 0; | |
6987 | } | |
6988 | elink_cl45_read(sc, phy, | |
6989 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); | |
6990 | elink_cl45_read(sc, phy, | |
6991 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); | |
6992 | ||
6993 | /* Check the link status on 1.1.2 */ | |
6994 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
6995 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
6996 | PMD_DRV_LOG(DEBUG, "KR PMA status 0x%x->0x%x," | |
6997 | "an_link_status=0x%x", val2, val1, an1000_status); | |
6998 | ||
6999 | link_up = (((val1 & 4) == 4) || (an1000_status & (1 << 1))); | |
7000 | if (link_up && elink_8073_is_snr_needed(sc, phy)) { | |
7001 | /* The SNR will improve about 2dbby changing the BW and FEE main | |
7002 | * tap. The 1st write to change FFE main tap is set before | |
7003 | * restart AN. Change PLL Bandwidth in EDC register | |
7004 | */ | |
7005 | elink_cl45_write(sc, phy, | |
7006 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH, | |
7007 | 0x26BC); | |
7008 | ||
7009 | /* Change CDR Bandwidth in EDC register */ | |
7010 | elink_cl45_write(sc, phy, | |
7011 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH, | |
7012 | 0x0333); | |
7013 | } | |
7014 | elink_cl45_read(sc, phy, | |
7015 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS, | |
7016 | &link_status); | |
7017 | ||
7018 | /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ | |
7019 | if ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) { | |
7020 | link_up = 1; | |
7021 | vars->line_speed = ELINK_SPEED_10000; | |
7022 | PMD_DRV_LOG(DEBUG, "port %x: External link up in 10G", | |
7023 | params->port); | |
7024 | } else if ((link_status & (1 << 1)) && (!(link_status & (1 << 14)))) { | |
7025 | link_up = 1; | |
7026 | vars->line_speed = ELINK_SPEED_2500; | |
7027 | PMD_DRV_LOG(DEBUG, "port %x: External link up in 2.5G", | |
7028 | params->port); | |
7029 | } else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) { | |
7030 | link_up = 1; | |
7031 | vars->line_speed = ELINK_SPEED_1000; | |
7032 | PMD_DRV_LOG(DEBUG, "port %x: External link up in 1G", | |
7033 | params->port); | |
7034 | } else { | |
7035 | link_up = 0; | |
7036 | PMD_DRV_LOG(DEBUG, "port %x: External link is down", | |
7037 | params->port); | |
7038 | } | |
7039 | ||
7040 | if (link_up) { | |
7041 | /* Swap polarity if required */ | |
7042 | if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { | |
7043 | /* Configure the 8073 to swap P and N of the KR lines */ | |
7044 | elink_cl45_read(sc, phy, | |
7045 | MDIO_XS_DEVAD, | |
7046 | MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1); | |
7047 | /* Set bit 3 to invert Rx in 1G mode and clear this bit | |
7048 | * when it`s in 10G mode. | |
7049 | */ | |
7050 | if (vars->line_speed == ELINK_SPEED_1000) { | |
7051 | PMD_DRV_LOG(DEBUG, "Swapping 1G polarity for" | |
7052 | "the 8073"); | |
7053 | val1 |= (1 << 3); | |
7054 | } else | |
7055 | val1 &= ~(1 << 3); | |
7056 | ||
7057 | elink_cl45_write(sc, phy, | |
7058 | MDIO_XS_DEVAD, | |
7059 | MDIO_XS_REG_8073_RX_CTRL_PCIE, val1); | |
7060 | } | |
7061 | elink_ext_phy_10G_an_resolve(sc, phy, vars); | |
7062 | elink_8073_resolve_fc(phy, params, vars); | |
7063 | vars->duplex = DUPLEX_FULL; | |
7064 | } | |
7065 | ||
7066 | if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { | |
7067 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, | |
7068 | MDIO_AN_REG_LP_AUTO_NEG2, &val1); | |
7069 | ||
7070 | if (val1 & (1 << 5)) | |
7071 | vars->link_status |= | |
7072 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
7073 | if (val1 & (1 << 7)) | |
7074 | vars->link_status |= | |
7075 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
7076 | } | |
7077 | ||
7078 | return link_up; | |
7079 | } | |
7080 | ||
7081 | static void elink_8073_link_reset(__rte_unused struct elink_phy *phy, | |
7082 | struct elink_params *params) | |
7083 | { | |
7084 | struct bnx2x_softc *sc = params->sc; | |
7085 | uint8_t gpio_port; | |
7086 | if (CHIP_IS_E2(sc)) | |
7087 | gpio_port = SC_PATH(sc); | |
7088 | else | |
7089 | gpio_port = params->port; | |
7090 | PMD_DRV_LOG(DEBUG, "Setting 8073 port %d into low power mode", | |
7091 | gpio_port); | |
7092 | elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, | |
7093 | MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port); | |
7094 | } | |
7095 | ||
7096 | /******************************************************************/ | |
7097 | /* BNX2X8705 PHY SECTION */ | |
7098 | /******************************************************************/ | |
7099 | static elink_status_t elink_8705_config_init(struct elink_phy *phy, | |
7100 | struct elink_params *params, | |
7101 | __rte_unused struct elink_vars | |
7102 | *vars) | |
7103 | { | |
7104 | struct bnx2x_softc *sc = params->sc; | |
7105 | PMD_DRV_LOG(DEBUG, "init 8705"); | |
7106 | /* Restore normal power mode */ | |
7107 | elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, | |
7108 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); | |
7109 | /* HW reset */ | |
7110 | elink_ext_phy_hw_reset(sc, params->port); | |
7111 | elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); | |
7112 | elink_wait_reset_complete(sc, phy, params); | |
7113 | ||
7114 | elink_cl45_write(sc, phy, | |
7115 | MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288); | |
7116 | elink_cl45_write(sc, phy, | |
7117 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); | |
7118 | elink_cl45_write(sc, phy, | |
7119 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); | |
7120 | elink_cl45_write(sc, phy, MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); | |
7121 | /* BNX2X8705 doesn't have microcode, hence the 0 */ | |
7122 | elink_save_spirom_version(sc, params->port, params->shmem_base, 0); | |
7123 | return ELINK_STATUS_OK; | |
7124 | } | |
7125 | ||
7126 | static uint8_t elink_8705_read_status(struct elink_phy *phy, | |
7127 | struct elink_params *params, | |
7128 | struct elink_vars *vars) | |
7129 | { | |
7130 | uint8_t link_up = 0; | |
7131 | uint16_t val1, rx_sd; | |
7132 | struct bnx2x_softc *sc = params->sc; | |
7133 | PMD_DRV_LOG(DEBUG, "read status 8705"); | |
7134 | elink_cl45_read(sc, phy, | |
7135 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); | |
7136 | PMD_DRV_LOG(DEBUG, "8705 LASI status 0x%x", val1); | |
7137 | ||
7138 | elink_cl45_read(sc, phy, | |
7139 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); | |
7140 | PMD_DRV_LOG(DEBUG, "8705 LASI status 0x%x", val1); | |
7141 | ||
7142 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); | |
7143 | ||
7144 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1); | |
7145 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1); | |
7146 | ||
7147 | PMD_DRV_LOG(DEBUG, "8705 1.c809 val=0x%x", val1); | |
7148 | link_up = ((rx_sd & 0x1) && (val1 & (1 << 9)) | |
7149 | && ((val1 & (1 << 8)) == 0)); | |
7150 | if (link_up) { | |
7151 | vars->line_speed = ELINK_SPEED_10000; | |
7152 | elink_ext_phy_resolve_fc(phy, params, vars); | |
7153 | } | |
7154 | return link_up; | |
7155 | } | |
7156 | ||
7157 | /******************************************************************/ | |
7158 | /* SFP+ module Section */ | |
7159 | /******************************************************************/ | |
7160 | static void elink_set_disable_pmd_transmit(struct elink_params *params, | |
7161 | struct elink_phy *phy, | |
7162 | uint8_t pmd_dis) | |
7163 | { | |
7164 | struct bnx2x_softc *sc = params->sc; | |
7165 | /* Disable transmitter only for bootcodes which can enable it afterwards | |
7166 | * (for D3 link) | |
7167 | */ | |
7168 | if (pmd_dis) { | |
7169 | if (params->feature_config_flags & | |
7170 | ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) { | |
7171 | PMD_DRV_LOG(DEBUG, "Disabling PMD transmitter"); | |
7172 | } else { | |
7173 | PMD_DRV_LOG(DEBUG, "NOT disabling PMD transmitter"); | |
7174 | return; | |
7175 | } | |
7176 | } else { | |
7177 | PMD_DRV_LOG(DEBUG, "Enabling PMD transmitter"); | |
7178 | } | |
7179 | elink_cl45_write(sc, phy, | |
7180 | MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, pmd_dis); | |
7181 | } | |
7182 | ||
7183 | static uint8_t elink_get_gpio_port(struct elink_params *params) | |
7184 | { | |
7185 | uint8_t gpio_port; | |
7186 | uint32_t swap_val, swap_override; | |
7187 | struct bnx2x_softc *sc = params->sc; | |
7188 | if (CHIP_IS_E2(sc)) { | |
7189 | gpio_port = SC_PATH(sc); | |
7190 | } else { | |
7191 | gpio_port = params->port; | |
7192 | } | |
7193 | swap_val = REG_RD(sc, NIG_REG_PORT_SWAP); | |
7194 | swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE); | |
7195 | return gpio_port ^ (swap_val && swap_override); | |
7196 | } | |
7197 | ||
7198 | static void elink_sfp_e1e2_set_transmitter(struct elink_params *params, | |
7199 | struct elink_phy *phy, uint8_t tx_en) | |
7200 | { | |
7201 | uint16_t val; | |
7202 | uint8_t port = params->port; | |
7203 | struct bnx2x_softc *sc = params->sc; | |
7204 | uint32_t tx_en_mode; | |
7205 | ||
7206 | /* Disable/Enable transmitter ( TX laser of the SFP+ module.) */ | |
7207 | tx_en_mode = REG_RD(sc, params->shmem_base + | |
7208 | offsetof(struct shmem_region, | |
7209 | dev_info.port_hw_config[port].sfp_ctrl)) & | |
7210 | PORT_HW_CFG_TX_LASER_MASK; | |
7211 | PMD_DRV_LOG(DEBUG, "Setting transmitter tx_en=%x for port %x " | |
7212 | "mode = %x", tx_en, port, tx_en_mode); | |
7213 | switch (tx_en_mode) { | |
7214 | case PORT_HW_CFG_TX_LASER_MDIO: | |
7215 | ||
7216 | elink_cl45_read(sc, phy, | |
7217 | MDIO_PMA_DEVAD, | |
7218 | MDIO_PMA_REG_PHY_IDENTIFIER, &val); | |
7219 | ||
7220 | if (tx_en) | |
7221 | val &= ~(1 << 15); | |
7222 | else | |
7223 | val |= (1 << 15); | |
7224 | ||
7225 | elink_cl45_write(sc, phy, | |
7226 | MDIO_PMA_DEVAD, | |
7227 | MDIO_PMA_REG_PHY_IDENTIFIER, val); | |
7228 | break; | |
7229 | case PORT_HW_CFG_TX_LASER_GPIO0: | |
7230 | case PORT_HW_CFG_TX_LASER_GPIO1: | |
7231 | case PORT_HW_CFG_TX_LASER_GPIO2: | |
7232 | case PORT_HW_CFG_TX_LASER_GPIO3: | |
7233 | { | |
7234 | uint16_t gpio_pin; | |
7235 | uint8_t gpio_port, gpio_mode; | |
7236 | if (tx_en) | |
7237 | gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH; | |
7238 | else | |
7239 | gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW; | |
7240 | ||
7241 | gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; | |
7242 | gpio_port = elink_get_gpio_port(params); | |
7243 | elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port); | |
7244 | break; | |
7245 | } | |
7246 | default: | |
7247 | PMD_DRV_LOG(DEBUG, "Invalid TX_LASER_MDIO 0x%x", tx_en_mode); | |
7248 | break; | |
7249 | } | |
7250 | } | |
7251 | ||
7252 | static void elink_sfp_set_transmitter(struct elink_params *params, | |
7253 | struct elink_phy *phy, uint8_t tx_en) | |
7254 | { | |
7255 | struct bnx2x_softc *sc = params->sc; | |
7256 | PMD_DRV_LOG(DEBUG, "Setting SFP+ transmitter to %d", tx_en); | |
7257 | if (CHIP_IS_E3(sc)) | |
7258 | elink_sfp_e3_set_transmitter(params, phy, tx_en); | |
7259 | else | |
7260 | elink_sfp_e1e2_set_transmitter(params, phy, tx_en); | |
7261 | } | |
7262 | ||
7263 | static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy, | |
7264 | struct elink_params | |
7265 | *params, | |
7266 | uint8_t dev_addr, | |
7267 | uint16_t addr, | |
7268 | uint8_t byte_cnt, | |
7269 | uint8_t * o_buf, | |
7270 | __rte_unused uint8_t | |
7271 | is_init) | |
7272 | { | |
7273 | struct bnx2x_softc *sc = params->sc; | |
7274 | uint16_t val = 0; | |
7275 | uint16_t i; | |
7276 | if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) { | |
7277 | PMD_DRV_LOG(DEBUG, "Reading from eeprom is limited to 0xf"); | |
7278 | return ELINK_STATUS_ERROR; | |
7279 | } | |
7280 | /* Set the read command byte count */ | |
7281 | elink_cl45_write(sc, phy, | |
7282 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, | |
7283 | (byte_cnt | (dev_addr << 8))); | |
7284 | ||
7285 | /* Set the read command address */ | |
7286 | elink_cl45_write(sc, phy, | |
7287 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, | |
7288 | addr); | |
7289 | ||
7290 | /* Activate read command */ | |
7291 | elink_cl45_write(sc, phy, | |
7292 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, | |
7293 | 0x2c0f); | |
7294 | ||
7295 | /* Wait up to 500us for command complete status */ | |
7296 | for (i = 0; i < 100; i++) { | |
7297 | elink_cl45_read(sc, phy, | |
7298 | MDIO_PMA_DEVAD, | |
7299 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
7300 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == | |
7301 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) | |
7302 | break; | |
7303 | DELAY(5); | |
7304 | } | |
7305 | ||
7306 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != | |
7307 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { | |
7308 | PMD_DRV_LOG(DEBUG, | |
7309 | "Got bad status 0x%x when reading from SFP+ EEPROM", | |
7310 | (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); | |
7311 | return ELINK_STATUS_ERROR; | |
7312 | } | |
7313 | ||
7314 | /* Read the buffer */ | |
7315 | for (i = 0; i < byte_cnt; i++) { | |
7316 | elink_cl45_read(sc, phy, | |
7317 | MDIO_PMA_DEVAD, | |
7318 | MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); | |
7319 | o_buf[i] = | |
7320 | (uint8_t) (val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); | |
7321 | } | |
7322 | ||
7323 | for (i = 0; i < 100; i++) { | |
7324 | elink_cl45_read(sc, phy, | |
7325 | MDIO_PMA_DEVAD, | |
7326 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
7327 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == | |
7328 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) | |
7329 | return ELINK_STATUS_OK; | |
7330 | DELAY(1000 * 1); | |
7331 | } | |
7332 | return ELINK_STATUS_ERROR; | |
7333 | } | |
7334 | ||
7335 | static void elink_warpcore_power_module(struct elink_params *params, | |
7336 | uint8_t power) | |
7337 | { | |
7338 | uint32_t pin_cfg; | |
7339 | struct bnx2x_softc *sc = params->sc; | |
7340 | ||
7341 | pin_cfg = (REG_RD(sc, params->shmem_base + | |
7342 | offsetof(struct shmem_region, | |
7343 | dev_info.port_hw_config[params->port]. | |
7344 | e3_sfp_ctrl)) & PORT_HW_CFG_E3_PWR_DIS_MASK) | |
7345 | >> PORT_HW_CFG_E3_PWR_DIS_SHIFT; | |
7346 | ||
7347 | if (pin_cfg == PIN_CFG_NA) | |
7348 | return; | |
7349 | PMD_DRV_LOG(DEBUG, "Setting SFP+ module power to %d using pin cfg %d", | |
7350 | power, pin_cfg); | |
7351 | /* Low ==> corresponding SFP+ module is powered | |
7352 | * high ==> the SFP+ module is powered down | |
7353 | */ | |
7354 | elink_set_cfg_pin(sc, pin_cfg, power ^ 1); | |
7355 | } | |
7356 | ||
7357 | static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct | |
7358 | elink_phy *phy, | |
7359 | struct elink_params | |
7360 | *params, | |
7361 | uint8_t dev_addr, | |
7362 | uint16_t addr, | |
7363 | uint8_t byte_cnt, | |
7364 | uint8_t * o_buf, | |
7365 | uint8_t is_init) | |
7366 | { | |
7367 | elink_status_t rc = ELINK_STATUS_OK; | |
7368 | uint8_t i, j = 0, cnt = 0; | |
7369 | uint32_t data_array[4]; | |
7370 | uint16_t addr32; | |
7371 | struct bnx2x_softc *sc = params->sc; | |
7372 | ||
7373 | if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) { | |
7374 | PMD_DRV_LOG(DEBUG, | |
7375 | "Reading from eeprom is limited to 16 bytes"); | |
7376 | return ELINK_STATUS_ERROR; | |
7377 | } | |
7378 | ||
7379 | /* 4 byte aligned address */ | |
7380 | addr32 = addr & (~0x3); | |
7381 | do { | |
7382 | if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) { | |
7383 | elink_warpcore_power_module(params, 0); | |
7384 | /* Note that 100us are not enough here */ | |
7385 | DELAY(1000 * 1); | |
7386 | elink_warpcore_power_module(params, 1); | |
7387 | } | |
7388 | rc = elink_bsc_read(params, sc, dev_addr, addr32, 0, byte_cnt, | |
7389 | data_array); | |
7390 | } while ((rc != ELINK_STATUS_OK) && (++cnt < I2C_WA_RETRY_CNT)); | |
7391 | ||
7392 | if (rc == ELINK_STATUS_OK) { | |
7393 | for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) { | |
7394 | o_buf[j] = *((uint8_t *) data_array + i); | |
7395 | j++; | |
7396 | } | |
7397 | } | |
7398 | ||
7399 | return rc; | |
7400 | } | |
7401 | ||
7402 | static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy, | |
7403 | struct elink_params | |
7404 | *params, | |
7405 | uint8_t dev_addr, | |
7406 | uint16_t addr, | |
7407 | uint8_t byte_cnt, | |
7408 | uint8_t * o_buf, | |
7409 | __rte_unused uint8_t | |
7410 | is_init) | |
7411 | { | |
7412 | struct bnx2x_softc *sc = params->sc; | |
7413 | uint16_t val, i; | |
7414 | ||
7415 | if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) { | |
7416 | PMD_DRV_LOG(DEBUG, "Reading from eeprom is limited to 0xf"); | |
7417 | return ELINK_STATUS_ERROR; | |
7418 | } | |
7419 | ||
7420 | /* Set 2-wire transfer rate of SFP+ module EEPROM | |
7421 | * to 100Khz since some DACs(direct attached cables) do | |
7422 | * not work at 400Khz. | |
7423 | */ | |
7424 | elink_cl45_write(sc, phy, | |
7425 | MDIO_PMA_DEVAD, | |
7426 | MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, | |
7427 | ((dev_addr << 8) | 1)); | |
7428 | ||
7429 | /* Need to read from 1.8000 to clear it */ | |
7430 | elink_cl45_read(sc, phy, | |
7431 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
7432 | ||
7433 | /* Set the read command byte count */ | |
7434 | elink_cl45_write(sc, phy, | |
7435 | MDIO_PMA_DEVAD, | |
7436 | MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, | |
7437 | ((byte_cnt < 2) ? 2 : byte_cnt)); | |
7438 | ||
7439 | /* Set the read command address */ | |
7440 | elink_cl45_write(sc, phy, | |
7441 | MDIO_PMA_DEVAD, | |
7442 | MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, addr); | |
7443 | /* Set the destination address */ | |
7444 | elink_cl45_write(sc, phy, | |
7445 | MDIO_PMA_DEVAD, | |
7446 | 0x8004, MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); | |
7447 | ||
7448 | /* Activate read command */ | |
7449 | elink_cl45_write(sc, phy, | |
7450 | MDIO_PMA_DEVAD, | |
7451 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 0x8002); | |
7452 | /* Wait appropriate time for two-wire command to finish before | |
7453 | * polling the status register | |
7454 | */ | |
7455 | DELAY(1000 * 1); | |
7456 | ||
7457 | /* Wait up to 500us for command complete status */ | |
7458 | for (i = 0; i < 100; i++) { | |
7459 | elink_cl45_read(sc, phy, | |
7460 | MDIO_PMA_DEVAD, | |
7461 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
7462 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == | |
7463 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) | |
7464 | break; | |
7465 | DELAY(5); | |
7466 | } | |
7467 | ||
7468 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != | |
7469 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { | |
7470 | PMD_DRV_LOG(DEBUG, | |
7471 | "Got bad status 0x%x when reading from SFP+ EEPROM", | |
7472 | (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); | |
7473 | return ELINK_STATUS_TIMEOUT; | |
7474 | } | |
7475 | ||
7476 | /* Read the buffer */ | |
7477 | for (i = 0; i < byte_cnt; i++) { | |
7478 | elink_cl45_read(sc, phy, | |
7479 | MDIO_PMA_DEVAD, | |
7480 | MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); | |
7481 | o_buf[i] = | |
7482 | (uint8_t) (val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); | |
7483 | } | |
7484 | ||
7485 | for (i = 0; i < 100; i++) { | |
7486 | elink_cl45_read(sc, phy, | |
7487 | MDIO_PMA_DEVAD, | |
7488 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
7489 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == | |
7490 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) | |
7491 | return ELINK_STATUS_OK; | |
7492 | DELAY(1000 * 1); | |
7493 | } | |
7494 | ||
7495 | return ELINK_STATUS_ERROR; | |
7496 | } | |
7497 | ||
7498 | static elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy, | |
7499 | struct elink_params *params, | |
7500 | uint8_t dev_addr, | |
7501 | uint16_t addr, | |
7502 | uint16_t byte_cnt, | |
7503 | uint8_t * o_buf) | |
7504 | { | |
7505 | elink_status_t rc = ELINK_STATUS_OK; | |
7506 | uint8_t xfer_size; | |
7507 | uint8_t *user_data = o_buf; | |
7508 | read_sfp_module_eeprom_func_p read_func; | |
7509 | ||
7510 | if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) { | |
7511 | PMD_DRV_LOG(DEBUG, "invalid dev_addr 0x%x", dev_addr); | |
7512 | return ELINK_STATUS_ERROR; | |
7513 | } | |
7514 | ||
7515 | switch (phy->type) { | |
7516 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726: | |
7517 | read_func = elink_8726_read_sfp_module_eeprom; | |
7518 | break; | |
7519 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727: | |
7520 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722: | |
7521 | read_func = elink_8727_read_sfp_module_eeprom; | |
7522 | break; | |
7523 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: | |
7524 | read_func = elink_warpcore_read_sfp_module_eeprom; | |
7525 | break; | |
7526 | default: | |
7527 | return ELINK_OP_NOT_SUPPORTED; | |
7528 | } | |
7529 | ||
7530 | while (!rc && (byte_cnt > 0)) { | |
7531 | xfer_size = (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) ? | |
7532 | ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt; | |
7533 | rc = read_func(phy, params, dev_addr, addr, xfer_size, | |
7534 | user_data, 0); | |
7535 | byte_cnt -= xfer_size; | |
7536 | user_data += xfer_size; | |
7537 | addr += xfer_size; | |
7538 | } | |
7539 | return rc; | |
7540 | } | |
7541 | ||
7542 | static elink_status_t elink_get_edc_mode(struct elink_phy *phy, | |
7543 | struct elink_params *params, | |
7544 | uint16_t * edc_mode) | |
7545 | { | |
7546 | struct bnx2x_softc *sc = params->sc; | |
7547 | uint32_t sync_offset = 0, phy_idx, media_types; | |
7548 | uint8_t gport, val[2], check_limiting_mode = 0; | |
7549 | *edc_mode = ELINK_EDC_MODE_LIMITING; | |
7550 | phy->media_type = ELINK_ETH_PHY_UNSPECIFIED; | |
7551 | /* First check for copper cable */ | |
7552 | if (elink_read_sfp_module_eeprom(phy, | |
7553 | params, | |
7554 | ELINK_I2C_DEV_ADDR_A0, | |
7555 | ELINK_SFP_EEPROM_CON_TYPE_ADDR, | |
7556 | 2, (uint8_t *) val) != 0) { | |
7557 | PMD_DRV_LOG(DEBUG, "Failed to read from SFP+ module EEPROM"); | |
7558 | return ELINK_STATUS_ERROR; | |
7559 | } | |
7560 | ||
7561 | switch (val[0]) { | |
7562 | case ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER: | |
7563 | { | |
7564 | uint8_t copper_module_type; | |
7565 | phy->media_type = ELINK_ETH_PHY_DA_TWINAX; | |
7566 | /* Check if its active cable (includes SFP+ module) | |
7567 | * of passive cable | |
7568 | */ | |
7569 | if (elink_read_sfp_module_eeprom(phy, | |
7570 | params, | |
7571 | ELINK_I2C_DEV_ADDR_A0, | |
7572 | ELINK_SFP_EEPROM_FC_TX_TECH_ADDR, | |
7573 | 1, | |
7574 | &copper_module_type) != | |
7575 | 0) { | |
7576 | PMD_DRV_LOG(DEBUG, | |
7577 | "Failed to read copper-cable-type" | |
7578 | " from SFP+ EEPROM"); | |
7579 | return ELINK_STATUS_ERROR; | |
7580 | } | |
7581 | ||
7582 | if (copper_module_type & | |
7583 | ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { | |
7584 | PMD_DRV_LOG(DEBUG, | |
7585 | "Active Copper cable detected"); | |
7586 | if (phy->type == | |
7587 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) | |
7588 | *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC; | |
7589 | else | |
7590 | check_limiting_mode = 1; | |
7591 | } else if (copper_module_type & | |
7592 | ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) | |
7593 | { | |
7594 | PMD_DRV_LOG(DEBUG, | |
7595 | "Passive Copper cable detected"); | |
7596 | *edc_mode = ELINK_EDC_MODE_PASSIVE_DAC; | |
7597 | } else { | |
7598 | PMD_DRV_LOG(DEBUG, | |
7599 | "Unknown copper-cable-type 0x%x !!!", | |
7600 | copper_module_type); | |
7601 | return ELINK_STATUS_ERROR; | |
7602 | } | |
7603 | break; | |
7604 | } | |
7605 | case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC: | |
7606 | case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45: | |
7607 | check_limiting_mode = 1; | |
7608 | if ((val[1] & (ELINK_SFP_EEPROM_COMP_CODE_SR_MASK | | |
7609 | ELINK_SFP_EEPROM_COMP_CODE_LR_MASK | | |
7610 | ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) { | |
7611 | PMD_DRV_LOG(DEBUG, "1G SFP module detected"); | |
7612 | gport = params->port; | |
7613 | phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER; | |
7614 | if (phy->req_line_speed != ELINK_SPEED_1000) { | |
7615 | phy->req_line_speed = ELINK_SPEED_1000; | |
7616 | if (!CHIP_IS_E1x(sc)) { | |
7617 | gport = SC_PATH(sc) + | |
7618 | (params->port << 1); | |
7619 | } | |
7620 | elink_cb_event_log(sc, ELINK_LOG_ID_NON_10G_MODULE, gport); //"Warning: Link speed was forced to 1000Mbps." | |
7621 | // " Current SFP module in port %d is not" | |
7622 | // " compliant with 10G Ethernet", | |
7623 | ||
7624 | } | |
7625 | } else { | |
7626 | int idx, cfg_idx = 0; | |
7627 | PMD_DRV_LOG(DEBUG, "10G Optic module detected"); | |
7628 | for (idx = ELINK_INT_PHY; idx < ELINK_MAX_PHYS; idx++) { | |
7629 | if (params->phy[idx].type == phy->type) { | |
7630 | cfg_idx = ELINK_LINK_CONFIG_IDX(idx); | |
7631 | break; | |
7632 | } | |
7633 | } | |
7634 | phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER; | |
7635 | phy->req_line_speed = params->req_line_speed[cfg_idx]; | |
7636 | } | |
7637 | break; | |
7638 | default: | |
7639 | PMD_DRV_LOG(DEBUG, "Unable to determine module type 0x%x !!!", | |
7640 | val[0]); | |
7641 | return ELINK_STATUS_ERROR; | |
7642 | } | |
7643 | sync_offset = params->shmem_base + | |
7644 | offsetof(struct shmem_region, | |
7645 | dev_info.port_hw_config[params->port].media_type); | |
7646 | media_types = REG_RD(sc, sync_offset); | |
7647 | /* Update media type for non-PMF sync */ | |
7648 | for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) { | |
7649 | if (&(params->phy[phy_idx]) == phy) { | |
7650 | media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << | |
7651 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * | |
7652 | phy_idx)); | |
7653 | media_types |= | |
7654 | ((phy-> | |
7655 | media_type & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << | |
7656 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); | |
7657 | break; | |
7658 | } | |
7659 | } | |
7660 | REG_WR(sc, sync_offset, media_types); | |
7661 | if (check_limiting_mode) { | |
7662 | uint8_t options[ELINK_SFP_EEPROM_OPTIONS_SIZE]; | |
7663 | if (elink_read_sfp_module_eeprom(phy, | |
7664 | params, | |
7665 | ELINK_I2C_DEV_ADDR_A0, | |
7666 | ELINK_SFP_EEPROM_OPTIONS_ADDR, | |
7667 | ELINK_SFP_EEPROM_OPTIONS_SIZE, | |
7668 | options) != 0) { | |
7669 | PMD_DRV_LOG(DEBUG, | |
7670 | "Failed to read Option field from module EEPROM"); | |
7671 | return ELINK_STATUS_ERROR; | |
7672 | } | |
7673 | if ((options[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) | |
7674 | *edc_mode = ELINK_EDC_MODE_LINEAR; | |
7675 | else | |
7676 | *edc_mode = ELINK_EDC_MODE_LIMITING; | |
7677 | } | |
7678 | PMD_DRV_LOG(DEBUG, "EDC mode is set to 0x%x", *edc_mode); | |
7679 | return ELINK_STATUS_OK; | |
7680 | } | |
7681 | ||
7682 | /* This function read the relevant field from the module (SFP+), and verify it | |
7683 | * is compliant with this board | |
7684 | */ | |
7685 | static elink_status_t elink_verify_sfp_module(struct elink_phy *phy, | |
7686 | struct elink_params *params) | |
7687 | { | |
7688 | struct bnx2x_softc *sc = params->sc; | |
7689 | uint32_t val, cmd; | |
7690 | uint32_t fw_resp, fw_cmd_param; | |
7691 | char vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE + 1]; | |
7692 | char vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE + 1]; | |
7693 | phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED; | |
7694 | val = REG_RD(sc, params->shmem_base + | |
7695 | offsetof(struct shmem_region, | |
7696 | dev_info.port_feature_config[params->port]. | |
7697 | config)); | |
7698 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == | |
7699 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { | |
7700 | PMD_DRV_LOG(DEBUG, "NOT enforcing module verification"); | |
7701 | return ELINK_STATUS_OK; | |
7702 | } | |
7703 | ||
7704 | if (params->feature_config_flags & | |
7705 | ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) { | |
7706 | /* Use specific phy request */ | |
7707 | cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL; | |
7708 | } else if (params->feature_config_flags & | |
7709 | ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) { | |
7710 | /* Use first phy request only in case of non-dual media */ | |
7711 | if (ELINK_DUAL_MEDIA(params)) { | |
7712 | PMD_DRV_LOG(DEBUG, | |
7713 | "FW does not support OPT MDL verification"); | |
7714 | return ELINK_STATUS_ERROR; | |
7715 | } | |
7716 | cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL; | |
7717 | } else { | |
7718 | /* No support in OPT MDL detection */ | |
7719 | PMD_DRV_LOG(DEBUG, "FW does not support OPT MDL verification"); | |
7720 | return ELINK_STATUS_ERROR; | |
7721 | } | |
7722 | ||
7723 | fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); | |
7724 | fw_resp = elink_cb_fw_command(sc, cmd, fw_cmd_param); | |
7725 | if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { | |
7726 | PMD_DRV_LOG(DEBUG, "Approved module"); | |
7727 | return ELINK_STATUS_OK; | |
7728 | } | |
7729 | ||
7730 | /* Format the warning message */ | |
7731 | if (elink_read_sfp_module_eeprom(phy, | |
7732 | params, | |
7733 | ELINK_I2C_DEV_ADDR_A0, | |
7734 | ELINK_SFP_EEPROM_VENDOR_NAME_ADDR, | |
7735 | ELINK_SFP_EEPROM_VENDOR_NAME_SIZE, | |
7736 | (uint8_t *) vendor_name)) | |
7737 | vendor_name[0] = '\0'; | |
7738 | else | |
7739 | vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; | |
7740 | if (elink_read_sfp_module_eeprom(phy, | |
7741 | params, | |
7742 | ELINK_I2C_DEV_ADDR_A0, | |
7743 | ELINK_SFP_EEPROM_PART_NO_ADDR, | |
7744 | ELINK_SFP_EEPROM_PART_NO_SIZE, | |
7745 | (uint8_t *) vendor_pn)) | |
7746 | vendor_pn[0] = '\0'; | |
7747 | else | |
7748 | vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE] = '\0'; | |
7749 | ||
7750 | elink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn); // "Warning: Unqualified SFP+ module detected," | |
7751 | // " Port %d from %s part number %s", | |
7752 | ||
7753 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != | |
7754 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG) | |
7755 | phy->flags |= ELINK_FLAGS_SFP_NOT_APPROVED; | |
7756 | return ELINK_STATUS_ERROR; | |
7757 | } | |
7758 | ||
7759 | static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy | |
7760 | *phy, | |
7761 | struct elink_params | |
7762 | *params) | |
7763 | { | |
7764 | uint8_t val; | |
7765 | elink_status_t rc; | |
7766 | uint16_t timeout; | |
7767 | /* Initialization time after hot-plug may take up to 300ms for | |
7768 | * some phys type ( e.g. JDSU ) | |
7769 | */ | |
7770 | ||
7771 | for (timeout = 0; timeout < 60; timeout++) { | |
7772 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) | |
7773 | rc = elink_warpcore_read_sfp_module_eeprom(phy, params, | |
7774 | ELINK_I2C_DEV_ADDR_A0, | |
7775 | 1, 1, &val, | |
7776 | 1); | |
7777 | else | |
7778 | rc = elink_read_sfp_module_eeprom(phy, params, | |
7779 | ELINK_I2C_DEV_ADDR_A0, | |
7780 | 1, 1, &val); | |
7781 | if (rc == 0) { | |
7782 | PMD_DRV_LOG(DEBUG, | |
7783 | "SFP+ module initialization took %d ms", | |
7784 | timeout * 5); | |
7785 | return ELINK_STATUS_OK; | |
7786 | } | |
7787 | DELAY(1000 * 5); | |
7788 | } | |
7789 | rc = elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0, | |
7790 | 1, 1, &val); | |
7791 | return rc; | |
7792 | } | |
7793 | ||
7794 | static void elink_8727_power_module(struct bnx2x_softc *sc, | |
7795 | struct elink_phy *phy, uint8_t is_power_up) | |
7796 | { | |
7797 | /* Make sure GPIOs are not using for LED mode */ | |
7798 | uint16_t val; | |
7799 | /* In the GPIO register, bit 4 is use to determine if the GPIOs are | |
7800 | * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for | |
7801 | * output | |
7802 | * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 | |
7803 | * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1 | |
7804 | * where the 1st bit is the over-current(only input), and 2nd bit is | |
7805 | * for power( only output ) | |
7806 | * | |
7807 | * In case of NOC feature is disabled and power is up, set GPIO control | |
7808 | * as input to enable listening of over-current indication | |
7809 | */ | |
7810 | if (phy->flags & ELINK_FLAGS_NOC) | |
7811 | return; | |
7812 | if (is_power_up) | |
7813 | val = (1 << 4); | |
7814 | else | |
7815 | /* Set GPIO control to OUTPUT, and set the power bit | |
7816 | * to according to the is_power_up | |
7817 | */ | |
7818 | val = (1 << 1); | |
7819 | ||
7820 | elink_cl45_write(sc, phy, | |
7821 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val); | |
7822 | } | |
7823 | ||
7824 | static elink_status_t elink_8726_set_limiting_mode(struct bnx2x_softc *sc, | |
7825 | struct elink_phy *phy, | |
7826 | uint16_t edc_mode) | |
7827 | { | |
7828 | uint16_t cur_limiting_mode; | |
7829 | ||
7830 | elink_cl45_read(sc, phy, | |
7831 | MDIO_PMA_DEVAD, | |
7832 | MDIO_PMA_REG_ROM_VER2, &cur_limiting_mode); | |
7833 | PMD_DRV_LOG(DEBUG, "Current Limiting mode is 0x%x", cur_limiting_mode); | |
7834 | ||
7835 | if (edc_mode == ELINK_EDC_MODE_LIMITING) { | |
7836 | PMD_DRV_LOG(DEBUG, "Setting LIMITING MODE"); | |
7837 | elink_cl45_write(sc, phy, | |
7838 | MDIO_PMA_DEVAD, | |
7839 | MDIO_PMA_REG_ROM_VER2, | |
7840 | ELINK_EDC_MODE_LIMITING); | |
7841 | } else { /* LRM mode ( default ) */ | |
7842 | ||
7843 | PMD_DRV_LOG(DEBUG, "Setting LRM MODE"); | |
7844 | ||
7845 | /* Changing to LRM mode takes quite few seconds. So do it only | |
7846 | * if current mode is limiting (default is LRM) | |
7847 | */ | |
7848 | if (cur_limiting_mode != ELINK_EDC_MODE_LIMITING) | |
7849 | return ELINK_STATUS_OK; | |
7850 | ||
7851 | elink_cl45_write(sc, phy, | |
7852 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0); | |
7853 | elink_cl45_write(sc, phy, | |
7854 | MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, 0x128); | |
7855 | elink_cl45_write(sc, phy, | |
7856 | MDIO_PMA_DEVAD, | |
7857 | MDIO_PMA_REG_MISC_CTRL0, 0x4008); | |
7858 | elink_cl45_write(sc, phy, | |
7859 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0xaaaa); | |
7860 | } | |
7861 | return ELINK_STATUS_OK; | |
7862 | } | |
7863 | ||
7864 | static elink_status_t elink_8727_set_limiting_mode(struct bnx2x_softc *sc, | |
7865 | struct elink_phy *phy, | |
7866 | uint16_t edc_mode) | |
7867 | { | |
7868 | uint16_t phy_identifier; | |
7869 | uint16_t rom_ver2_val; | |
7870 | elink_cl45_read(sc, phy, | |
7871 | MDIO_PMA_DEVAD, | |
7872 | MDIO_PMA_REG_PHY_IDENTIFIER, &phy_identifier); | |
7873 | ||
7874 | elink_cl45_write(sc, phy, | |
7875 | MDIO_PMA_DEVAD, | |
7876 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
7877 | (phy_identifier & ~(1 << 9))); | |
7878 | ||
7879 | elink_cl45_read(sc, phy, | |
7880 | MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &rom_ver2_val); | |
7881 | /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ | |
7882 | elink_cl45_write(sc, phy, | |
7883 | MDIO_PMA_DEVAD, | |
7884 | MDIO_PMA_REG_ROM_VER2, | |
7885 | (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); | |
7886 | ||
7887 | elink_cl45_write(sc, phy, | |
7888 | MDIO_PMA_DEVAD, | |
7889 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
7890 | (phy_identifier | (1 << 9))); | |
7891 | ||
7892 | return ELINK_STATUS_OK; | |
7893 | } | |
7894 | ||
7895 | static void elink_8727_specific_func(struct elink_phy *phy, | |
7896 | struct elink_params *params, | |
7897 | uint32_t action) | |
7898 | { | |
7899 | struct bnx2x_softc *sc = params->sc; | |
7900 | uint16_t val; | |
7901 | switch (action) { | |
7902 | case ELINK_DISABLE_TX: | |
7903 | elink_sfp_set_transmitter(params, phy, 0); | |
7904 | break; | |
7905 | case ELINK_ENABLE_TX: | |
7906 | if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) | |
7907 | elink_sfp_set_transmitter(params, phy, 1); | |
7908 | break; | |
7909 | case ELINK_PHY_INIT: | |
7910 | elink_cl45_write(sc, phy, | |
7911 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, | |
7912 | (1 << 2) | (1 << 5)); | |
7913 | elink_cl45_write(sc, phy, | |
7914 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0); | |
7915 | elink_cl45_write(sc, phy, | |
7916 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006); | |
7917 | /* Make MOD_ABS give interrupt on change */ | |
7918 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, | |
7919 | MDIO_PMA_REG_8727_PCS_OPT_CTRL, &val); | |
7920 | val |= (1 << 12); | |
7921 | if (phy->flags & ELINK_FLAGS_NOC) | |
7922 | val |= (3 << 5); | |
7923 | /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0 | |
7924 | * status which reflect SFP+ module over-current | |
7925 | */ | |
7926 | if (!(phy->flags & ELINK_FLAGS_NOC)) | |
7927 | val &= 0xff8f; /* Reset bits 4-6 */ | |
7928 | elink_cl45_write(sc, phy, | |
7929 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
7930 | val); | |
7931 | break; | |
7932 | default: | |
7933 | PMD_DRV_LOG(DEBUG, "Function 0x%x not supported by 8727", | |
7934 | action); | |
7935 | return; | |
7936 | } | |
7937 | } | |
7938 | ||
7939 | static void elink_set_e1e2_module_fault_led(struct elink_params *params, | |
7940 | uint8_t gpio_mode) | |
7941 | { | |
7942 | struct bnx2x_softc *sc = params->sc; | |
7943 | ||
7944 | uint32_t fault_led_gpio = REG_RD(sc, params->shmem_base + | |
7945 | offsetof(struct shmem_region, | |
7946 | dev_info. | |
7947 | port_hw_config[params->port]. | |
7948 | sfp_ctrl)) & | |
7949 | PORT_HW_CFG_FAULT_MODULE_LED_MASK; | |
7950 | switch (fault_led_gpio) { | |
7951 | case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED: | |
7952 | return; | |
7953 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0: | |
7954 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1: | |
7955 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2: | |
7956 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3: | |
7957 | { | |
7958 | uint8_t gpio_port = elink_get_gpio_port(params); | |
7959 | uint16_t gpio_pin = fault_led_gpio - | |
7960 | PORT_HW_CFG_FAULT_MODULE_LED_GPIO0; | |
7961 | PMD_DRV_LOG(DEBUG, "Set fault module-detected led " | |
7962 | "pin %x port %x mode %x", | |
7963 | gpio_pin, gpio_port, gpio_mode); | |
7964 | elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port); | |
7965 | } | |
7966 | break; | |
7967 | default: | |
7968 | PMD_DRV_LOG(DEBUG, "Error: Invalid fault led mode 0x%x", | |
7969 | fault_led_gpio); | |
7970 | } | |
7971 | } | |
7972 | ||
7973 | static void elink_set_e3_module_fault_led(struct elink_params *params, | |
7974 | uint8_t gpio_mode) | |
7975 | { | |
7976 | uint32_t pin_cfg; | |
7977 | uint8_t port = params->port; | |
7978 | struct bnx2x_softc *sc = params->sc; | |
7979 | pin_cfg = (REG_RD(sc, params->shmem_base + | |
7980 | offsetof(struct shmem_region, | |
7981 | dev_info.port_hw_config[port].e3_sfp_ctrl)) & | |
7982 | PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >> | |
7983 | PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT; | |
7984 | PMD_DRV_LOG(DEBUG, "Setting Fault LED to %d using pin cfg %d", | |
7985 | gpio_mode, pin_cfg); | |
7986 | elink_set_cfg_pin(sc, pin_cfg, gpio_mode); | |
7987 | } | |
7988 | ||
7989 | static void elink_set_sfp_module_fault_led(struct elink_params *params, | |
7990 | uint8_t gpio_mode) | |
7991 | { | |
7992 | struct bnx2x_softc *sc = params->sc; | |
7993 | PMD_DRV_LOG(DEBUG, "Setting SFP+ module fault LED to %d", gpio_mode); | |
7994 | if (CHIP_IS_E3(sc)) { | |
7995 | /* Low ==> if SFP+ module is supported otherwise | |
7996 | * High ==> if SFP+ module is not on the approved vendor list | |
7997 | */ | |
7998 | elink_set_e3_module_fault_led(params, gpio_mode); | |
7999 | } else | |
8000 | elink_set_e1e2_module_fault_led(params, gpio_mode); | |
8001 | } | |
8002 | ||
8003 | static void elink_warpcore_hw_reset(__rte_unused struct elink_phy *phy, | |
8004 | struct elink_params *params) | |
8005 | { | |
8006 | struct bnx2x_softc *sc = params->sc; | |
8007 | elink_warpcore_power_module(params, 0); | |
8008 | /* Put Warpcore in low power mode */ | |
8009 | REG_WR(sc, MISC_REG_WC0_RESET, 0x0c0e); | |
8010 | ||
8011 | /* Put LCPLL in low power mode */ | |
8012 | REG_WR(sc, MISC_REG_LCPLL_E40_PWRDWN, 1); | |
8013 | REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_ANA, 0); | |
8014 | REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_DIG, 0); | |
8015 | } | |
8016 | ||
8017 | static void elink_power_sfp_module(struct elink_params *params, | |
8018 | struct elink_phy *phy, uint8_t power) | |
8019 | { | |
8020 | PMD_DRV_LOG(DEBUG, "Setting SFP+ power to %x", power); | |
8021 | ||
8022 | switch (phy->type) { | |
8023 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727: | |
8024 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722: | |
8025 | elink_8727_power_module(params->sc, phy, power); | |
8026 | break; | |
8027 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: | |
8028 | elink_warpcore_power_module(params, power); | |
8029 | break; | |
8030 | default: | |
8031 | break; | |
8032 | } | |
8033 | } | |
8034 | ||
8035 | static void elink_warpcore_set_limiting_mode(struct elink_params *params, | |
8036 | struct elink_phy *phy, | |
8037 | uint16_t edc_mode) | |
8038 | { | |
8039 | uint16_t val = 0; | |
8040 | uint16_t mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; | |
8041 | struct bnx2x_softc *sc = params->sc; | |
8042 | ||
8043 | uint8_t lane = elink_get_warpcore_lane(params); | |
8044 | /* This is a global register which controls all lanes */ | |
8045 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
8046 | MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); | |
8047 | val &= ~(0xf << (lane << 2)); | |
8048 | ||
8049 | switch (edc_mode) { | |
8050 | case ELINK_EDC_MODE_LINEAR: | |
8051 | case ELINK_EDC_MODE_LIMITING: | |
8052 | mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; | |
8053 | break; | |
8054 | case ELINK_EDC_MODE_PASSIVE_DAC: | |
8055 | case ELINK_EDC_MODE_ACTIVE_DAC: | |
8056 | mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC; | |
8057 | break; | |
8058 | default: | |
8059 | break; | |
8060 | } | |
8061 | ||
8062 | val |= (mode << (lane << 2)); | |
8063 | elink_cl45_write(sc, phy, MDIO_WC_DEVAD, | |
8064 | MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val); | |
8065 | /* A must read */ | |
8066 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
8067 | MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); | |
8068 | ||
8069 | /* Restart microcode to re-read the new mode */ | |
8070 | elink_warpcore_reset_lane(sc, phy, 1); | |
8071 | elink_warpcore_reset_lane(sc, phy, 0); | |
8072 | ||
8073 | } | |
8074 | ||
8075 | static void elink_set_limiting_mode(struct elink_params *params, | |
8076 | struct elink_phy *phy, uint16_t edc_mode) | |
8077 | { | |
8078 | switch (phy->type) { | |
8079 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726: | |
8080 | elink_8726_set_limiting_mode(params->sc, phy, edc_mode); | |
8081 | break; | |
8082 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727: | |
8083 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722: | |
8084 | elink_8727_set_limiting_mode(params->sc, phy, edc_mode); | |
8085 | break; | |
8086 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: | |
8087 | elink_warpcore_set_limiting_mode(params, phy, edc_mode); | |
8088 | break; | |
8089 | } | |
8090 | } | |
8091 | ||
8092 | static elink_status_t elink_sfp_module_detection(struct elink_phy *phy, | |
8093 | struct elink_params *params) | |
8094 | { | |
8095 | struct bnx2x_softc *sc = params->sc; | |
8096 | uint16_t edc_mode; | |
8097 | elink_status_t rc = ELINK_STATUS_OK; | |
8098 | ||
8099 | uint32_t val = REG_RD(sc, params->shmem_base + | |
8100 | offsetof(struct shmem_region, | |
8101 | dev_info.port_feature_config[params-> | |
8102 | port]. | |
8103 | config)); | |
8104 | /* Enabled transmitter by default */ | |
8105 | elink_sfp_set_transmitter(params, phy, 1); | |
8106 | PMD_DRV_LOG(DEBUG, "SFP+ module plugged in/out detected on port %d", | |
8107 | params->port); | |
8108 | /* Power up module */ | |
8109 | elink_power_sfp_module(params, phy, 1); | |
8110 | if (elink_get_edc_mode(phy, params, &edc_mode) != 0) { | |
8111 | PMD_DRV_LOG(DEBUG, "Failed to get valid module type"); | |
8112 | return ELINK_STATUS_ERROR; | |
8113 | } else if (elink_verify_sfp_module(phy, params) != 0) { | |
8114 | /* Check SFP+ module compatibility */ | |
8115 | PMD_DRV_LOG(DEBUG, "Module verification failed!!"); | |
8116 | rc = ELINK_STATUS_ERROR; | |
8117 | /* Turn on fault module-detected led */ | |
8118 | elink_set_sfp_module_fault_led(params, | |
8119 | MISC_REGISTERS_GPIO_HIGH); | |
8120 | ||
8121 | /* Check if need to power down the SFP+ module */ | |
8122 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == | |
8123 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) { | |
8124 | PMD_DRV_LOG(DEBUG, "Shutdown SFP+ module!!"); | |
8125 | elink_power_sfp_module(params, phy, 0); | |
8126 | return rc; | |
8127 | } | |
8128 | } else { | |
8129 | /* Turn off fault module-detected led */ | |
8130 | elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW); | |
8131 | } | |
8132 | ||
8133 | /* Check and set limiting mode / LRM mode on 8726. On 8727 it | |
8134 | * is done automatically | |
8135 | */ | |
8136 | elink_set_limiting_mode(params, phy, edc_mode); | |
8137 | ||
8138 | /* Disable transmit for this module if the module is not approved, and | |
8139 | * laser needs to be disabled. | |
8140 | */ | |
8141 | if ((rc != 0) && | |
8142 | ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == | |
8143 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)) | |
8144 | elink_sfp_set_transmitter(params, phy, 0); | |
8145 | ||
8146 | return rc; | |
8147 | } | |
8148 | ||
8149 | void elink_handle_module_detect_int(struct elink_params *params) | |
8150 | { | |
8151 | struct bnx2x_softc *sc = params->sc; | |
8152 | struct elink_phy *phy; | |
8153 | uint32_t gpio_val; | |
8154 | uint8_t gpio_num, gpio_port; | |
8155 | if (CHIP_IS_E3(sc)) { | |
8156 | phy = ¶ms->phy[ELINK_INT_PHY]; | |
8157 | /* Always enable TX laser,will be disabled in case of fault */ | |
8158 | elink_sfp_set_transmitter(params, phy, 1); | |
8159 | } else { | |
8160 | phy = ¶ms->phy[ELINK_EXT_PHY1]; | |
8161 | } | |
8162 | if (elink_get_mod_abs_int_cfg(sc, params->shmem_base, | |
8163 | params->port, &gpio_num, &gpio_port) == | |
8164 | ELINK_STATUS_ERROR) { | |
8165 | PMD_DRV_LOG(DEBUG, "Failed to get MOD_ABS interrupt config"); | |
8166 | return; | |
8167 | } | |
8168 | ||
8169 | /* Set valid module led off */ | |
8170 | elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH); | |
8171 | ||
8172 | /* Get current gpio val reflecting module plugged in / out */ | |
8173 | gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port); | |
8174 | ||
8175 | /* Call the handling function in case module is detected */ | |
8176 | if (gpio_val == 0) { | |
8177 | elink_set_mdio_emac_per_phy(sc, params); | |
8178 | elink_set_aer_mmd(params, phy); | |
8179 | ||
8180 | elink_power_sfp_module(params, phy, 1); | |
8181 | elink_cb_gpio_int_write(sc, gpio_num, | |
8182 | MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, | |
8183 | gpio_port); | |
8184 | if (elink_wait_for_sfp_module_initialized(phy, params) == 0) { | |
8185 | elink_sfp_module_detection(phy, params); | |
8186 | if (CHIP_IS_E3(sc)) { | |
8187 | uint16_t rx_tx_in_reset; | |
8188 | /* In case WC is out of reset, reconfigure the | |
8189 | * link speed while taking into account 1G | |
8190 | * module limitation. | |
8191 | */ | |
8192 | elink_cl45_read(sc, phy, | |
8193 | MDIO_WC_DEVAD, | |
8194 | MDIO_WC_REG_DIGITAL5_MISC6, | |
8195 | &rx_tx_in_reset); | |
8196 | if ((!rx_tx_in_reset) && | |
8197 | (params->link_flags & | |
8198 | ELINK_PHY_INITIALIZED)) { | |
8199 | elink_warpcore_reset_lane(sc, phy, 1); | |
8200 | elink_warpcore_config_sfi(phy, params); | |
8201 | elink_warpcore_reset_lane(sc, phy, 0); | |
8202 | } | |
8203 | } | |
8204 | } else { | |
8205 | PMD_DRV_LOG(DEBUG, "SFP+ module is not initialized"); | |
8206 | } | |
8207 | } else { | |
8208 | elink_cb_gpio_int_write(sc, gpio_num, | |
8209 | MISC_REGISTERS_GPIO_INT_OUTPUT_SET, | |
8210 | gpio_port); | |
8211 | /* Module was plugged out. | |
8212 | * Disable transmit for this module | |
8213 | */ | |
8214 | phy->media_type = ELINK_ETH_PHY_NOT_PRESENT; | |
8215 | } | |
8216 | } | |
8217 | ||
8218 | /******************************************************************/ | |
8219 | /* Used by 8706 and 8727 */ | |
8220 | /******************************************************************/ | |
8221 | static void elink_sfp_mask_fault(struct bnx2x_softc *sc, | |
8222 | struct elink_phy *phy, | |
8223 | uint16_t alarm_status_offset, | |
8224 | uint16_t alarm_ctrl_offset) | |
8225 | { | |
8226 | uint16_t alarm_status, val; | |
8227 | elink_cl45_read(sc, phy, | |
8228 | MDIO_PMA_DEVAD, alarm_status_offset, &alarm_status); | |
8229 | elink_cl45_read(sc, phy, | |
8230 | MDIO_PMA_DEVAD, alarm_status_offset, &alarm_status); | |
8231 | /* Mask or enable the fault event. */ | |
8232 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); | |
8233 | if (alarm_status & (1 << 0)) | |
8234 | val &= ~(1 << 0); | |
8235 | else | |
8236 | val |= (1 << 0); | |
8237 | elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); | |
8238 | } | |
8239 | ||
8240 | /******************************************************************/ | |
8241 | /* common BNX2X8706/BNX2X8726 PHY SECTION */ | |
8242 | /******************************************************************/ | |
8243 | static uint8_t elink_8706_8726_read_status(struct elink_phy *phy, | |
8244 | struct elink_params *params, | |
8245 | struct elink_vars *vars) | |
8246 | { | |
8247 | uint8_t link_up = 0; | |
8248 | uint16_t val1, val2, rx_sd, pcs_status; | |
8249 | struct bnx2x_softc *sc = params->sc; | |
8250 | PMD_DRV_LOG(DEBUG, "XGXS 8706/8726"); | |
8251 | /* Clear RX Alarm */ | |
8252 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); | |
8253 | ||
8254 | elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT, | |
8255 | MDIO_PMA_LASI_TXCTRL); | |
8256 | ||
8257 | /* Clear LASI indication */ | |
8258 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); | |
8259 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); | |
8260 | PMD_DRV_LOG(DEBUG, "8706/8726 LASI status 0x%x--> 0x%x", val1, val2); | |
8261 | ||
8262 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); | |
8263 | elink_cl45_read(sc, phy, | |
8264 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status); | |
8265 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); | |
8266 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); | |
8267 | ||
8268 | PMD_DRV_LOG(DEBUG, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" | |
8269 | " link_status 0x%x", rx_sd, pcs_status, val2); | |
8270 | /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status | |
8271 | * are set, or if the autoneg bit 1 is set | |
8272 | */ | |
8273 | link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1 << 1))); | |
8274 | if (link_up) { | |
8275 | if (val2 & (1 << 1)) | |
8276 | vars->line_speed = ELINK_SPEED_1000; | |
8277 | else | |
8278 | vars->line_speed = ELINK_SPEED_10000; | |
8279 | elink_ext_phy_resolve_fc(phy, params, vars); | |
8280 | vars->duplex = DUPLEX_FULL; | |
8281 | } | |
8282 | ||
8283 | /* Capture 10G link fault. Read twice to clear stale value. */ | |
8284 | if (vars->line_speed == ELINK_SPEED_10000) { | |
8285 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, | |
8286 | MDIO_PMA_LASI_TXSTAT, &val1); | |
8287 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, | |
8288 | MDIO_PMA_LASI_TXSTAT, &val1); | |
8289 | if (val1 & (1 << 0)) | |
8290 | vars->fault_detected = 1; | |
8291 | } | |
8292 | ||
8293 | return link_up; | |
8294 | } | |
8295 | ||
8296 | /******************************************************************/ | |
8297 | /* BNX2X8706 PHY SECTION */ | |
8298 | /******************************************************************/ | |
8299 | static uint8_t elink_8706_config_init(struct elink_phy *phy, | |
8300 | struct elink_params *params, | |
8301 | __rte_unused struct elink_vars *vars) | |
8302 | { | |
8303 | uint32_t tx_en_mode; | |
8304 | uint16_t cnt, val, tmp1; | |
8305 | struct bnx2x_softc *sc = params->sc; | |
8306 | ||
8307 | elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, | |
8308 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); | |
8309 | /* HW reset */ | |
8310 | elink_ext_phy_hw_reset(sc, params->port); | |
8311 | elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); | |
8312 | elink_wait_reset_complete(sc, phy, params); | |
8313 | ||
8314 | /* Wait until fw is loaded */ | |
8315 | for (cnt = 0; cnt < 100; cnt++) { | |
8316 | elink_cl45_read(sc, phy, | |
8317 | MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); | |
8318 | if (val) | |
8319 | break; | |
8320 | DELAY(1000 * 10); | |
8321 | } | |
8322 | PMD_DRV_LOG(DEBUG, "XGXS 8706 is initialized after %d ms", cnt); | |
8323 | if ((params->feature_config_flags & | |
8324 | ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
8325 | uint8_t i; | |
8326 | uint16_t reg; | |
8327 | for (i = 0; i < 4; i++) { | |
8328 | reg = MDIO_XS_8706_REG_BANK_RX0 + | |
8329 | i * (MDIO_XS_8706_REG_BANK_RX1 - | |
8330 | MDIO_XS_8706_REG_BANK_RX0); | |
8331 | elink_cl45_read(sc, phy, MDIO_XS_DEVAD, reg, &val); | |
8332 | /* Clear first 3 bits of the control */ | |
8333 | val &= ~0x7; | |
8334 | /* Set control bits according to configuration */ | |
8335 | val |= (phy->rx_preemphasis[i] & 0x7); | |
8336 | PMD_DRV_LOG(DEBUG, "Setting RX Equalizer to BNX2X8706" | |
8337 | " reg 0x%x <-- val 0x%x", reg, val); | |
8338 | elink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val); | |
8339 | } | |
8340 | } | |
8341 | /* Force speed */ | |
8342 | if (phy->req_line_speed == ELINK_SPEED_10000) { | |
8343 | PMD_DRV_LOG(DEBUG, "XGXS 8706 force 10Gbps"); | |
8344 | ||
8345 | elink_cl45_write(sc, phy, | |
8346 | MDIO_PMA_DEVAD, | |
8347 | MDIO_PMA_REG_DIGITAL_CTRL, 0x400); | |
8348 | elink_cl45_write(sc, phy, | |
8349 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0); | |
8350 | /* Arm LASI for link and Tx fault. */ | |
8351 | elink_cl45_write(sc, phy, | |
8352 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3); | |
8353 | } else { | |
8354 | /* Force 1Gbps using autoneg with 1G advertisement */ | |
8355 | ||
8356 | /* Allow CL37 through CL73 */ | |
8357 | PMD_DRV_LOG(DEBUG, "XGXS 8706 AutoNeg"); | |
8358 | elink_cl45_write(sc, phy, | |
8359 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); | |
8360 | ||
8361 | /* Enable Full-Duplex advertisement on CL37 */ | |
8362 | elink_cl45_write(sc, phy, | |
8363 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); | |
8364 | /* Enable CL37 AN */ | |
8365 | elink_cl45_write(sc, phy, | |
8366 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
8367 | /* 1G support */ | |
8368 | elink_cl45_write(sc, phy, | |
8369 | MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1 << 5)); | |
8370 | ||
8371 | /* Enable clause 73 AN */ | |
8372 | elink_cl45_write(sc, phy, | |
8373 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
8374 | elink_cl45_write(sc, phy, | |
8375 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x0400); | |
8376 | elink_cl45_write(sc, phy, | |
8377 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004); | |
8378 | } | |
8379 | elink_save_bnx2x_spirom_ver(sc, phy, params->port); | |
8380 | ||
8381 | /* If TX Laser is controlled by GPIO_0, do not let PHY go into low | |
8382 | * power mode, if TX Laser is disabled | |
8383 | */ | |
8384 | ||
8385 | tx_en_mode = REG_RD(sc, params->shmem_base + | |
8386 | offsetof(struct shmem_region, | |
8387 | dev_info.port_hw_config[params->port]. | |
8388 | sfp_ctrl)) | |
8389 | & PORT_HW_CFG_TX_LASER_MASK; | |
8390 | ||
8391 | if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { | |
8392 | PMD_DRV_LOG(DEBUG, "Enabling TXONOFF_PWRDN_DIS"); | |
8393 | elink_cl45_read(sc, phy, | |
8394 | MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, | |
8395 | &tmp1); | |
8396 | tmp1 |= 0x1; | |
8397 | elink_cl45_write(sc, phy, | |
8398 | MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, | |
8399 | tmp1); | |
8400 | } | |
8401 | ||
8402 | return ELINK_STATUS_OK; | |
8403 | } | |
8404 | ||
8405 | static elink_status_t elink_8706_read_status(struct elink_phy *phy, | |
8406 | struct elink_params *params, | |
8407 | struct elink_vars *vars) | |
8408 | { | |
8409 | return elink_8706_8726_read_status(phy, params, vars); | |
8410 | } | |
8411 | ||
8412 | /******************************************************************/ | |
8413 | /* BNX2X8726 PHY SECTION */ | |
8414 | /******************************************************************/ | |
8415 | static void elink_8726_config_loopback(struct elink_phy *phy, | |
8416 | struct elink_params *params) | |
8417 | { | |
8418 | struct bnx2x_softc *sc = params->sc; | |
8419 | PMD_DRV_LOG(DEBUG, "PMA/PMD ext_phy_loopback: 8726"); | |
8420 | elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); | |
8421 | } | |
8422 | ||
8423 | static void elink_8726_external_rom_boot(struct elink_phy *phy, | |
8424 | struct elink_params *params) | |
8425 | { | |
8426 | struct bnx2x_softc *sc = params->sc; | |
8427 | /* Need to wait 100ms after reset */ | |
8428 | DELAY(1000 * 100); | |
8429 | ||
8430 | /* Micro controller re-boot */ | |
8431 | elink_cl45_write(sc, phy, | |
8432 | MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B); | |
8433 | ||
8434 | /* Set soft reset */ | |
8435 | elink_cl45_write(sc, phy, | |
8436 | MDIO_PMA_DEVAD, | |
8437 | MDIO_PMA_REG_GEN_CTRL, | |
8438 | MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); | |
8439 | ||
8440 | elink_cl45_write(sc, phy, | |
8441 | MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001); | |
8442 | ||
8443 | elink_cl45_write(sc, phy, | |
8444 | MDIO_PMA_DEVAD, | |
8445 | MDIO_PMA_REG_GEN_CTRL, | |
8446 | MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); | |
8447 | ||
8448 | /* Wait for 150ms for microcode load */ | |
8449 | DELAY(1000 * 150); | |
8450 | ||
8451 | /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ | |
8452 | elink_cl45_write(sc, phy, | |
8453 | MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000); | |
8454 | ||
8455 | DELAY(1000 * 200); | |
8456 | elink_save_bnx2x_spirom_ver(sc, phy, params->port); | |
8457 | } | |
8458 | ||
8459 | static uint8_t elink_8726_read_status(struct elink_phy *phy, | |
8460 | struct elink_params *params, | |
8461 | struct elink_vars *vars) | |
8462 | { | |
8463 | struct bnx2x_softc *sc = params->sc; | |
8464 | uint16_t val1; | |
8465 | uint8_t link_up = elink_8706_8726_read_status(phy, params, vars); | |
8466 | if (link_up) { | |
8467 | elink_cl45_read(sc, phy, | |
8468 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, | |
8469 | &val1); | |
8470 | if (val1 & (1 << 15)) { | |
8471 | PMD_DRV_LOG(DEBUG, "Tx is disabled"); | |
8472 | link_up = 0; | |
8473 | vars->line_speed = 0; | |
8474 | } | |
8475 | } | |
8476 | return link_up; | |
8477 | } | |
8478 | ||
8479 | static elink_status_t elink_8726_config_init(struct elink_phy *phy, | |
8480 | struct elink_params *params, | |
8481 | struct elink_vars *vars) | |
8482 | { | |
8483 | struct bnx2x_softc *sc = params->sc; | |
8484 | PMD_DRV_LOG(DEBUG, "Initializing BNX2X8726"); | |
8485 | ||
8486 | elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15); | |
8487 | elink_wait_reset_complete(sc, phy, params); | |
8488 | ||
8489 | elink_8726_external_rom_boot(phy, params); | |
8490 | ||
8491 | /* Need to call module detected on initialization since the module | |
8492 | * detection triggered by actual module insertion might occur before | |
8493 | * driver is loaded, and when driver is loaded, it reset all | |
8494 | * registers, including the transmitter | |
8495 | */ | |
8496 | elink_sfp_module_detection(phy, params); | |
8497 | ||
8498 | if (phy->req_line_speed == ELINK_SPEED_1000) { | |
8499 | PMD_DRV_LOG(DEBUG, "Setting 1G force"); | |
8500 | elink_cl45_write(sc, phy, | |
8501 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); | |
8502 | elink_cl45_write(sc, phy, | |
8503 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); | |
8504 | elink_cl45_write(sc, phy, | |
8505 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5); | |
8506 | elink_cl45_write(sc, phy, | |
8507 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400); | |
8508 | } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && | |
8509 | (phy->speed_cap_mask & | |
8510 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && | |
8511 | ((phy->speed_cap_mask & | |
8512 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != | |
8513 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { | |
8514 | PMD_DRV_LOG(DEBUG, "Setting 1G clause37"); | |
8515 | /* Set Flow control */ | |
8516 | elink_ext_phy_set_pause(params, phy, vars); | |
8517 | elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); | |
8518 | elink_cl45_write(sc, phy, | |
8519 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); | |
8520 | elink_cl45_write(sc, phy, | |
8521 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); | |
8522 | elink_cl45_write(sc, phy, | |
8523 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
8524 | elink_cl45_write(sc, phy, | |
8525 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
8526 | /* Enable RX-ALARM control to receive interrupt for 1G speed | |
8527 | * change | |
8528 | */ | |
8529 | elink_cl45_write(sc, phy, | |
8530 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4); | |
8531 | elink_cl45_write(sc, phy, | |
8532 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400); | |
8533 | ||
8534 | } else { /* Default 10G. Set only LASI control */ | |
8535 | elink_cl45_write(sc, phy, | |
8536 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1); | |
8537 | } | |
8538 | ||
8539 | /* Set TX PreEmphasis if needed */ | |
8540 | if ((params->feature_config_flags & | |
8541 | ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
8542 | PMD_DRV_LOG(DEBUG, | |
8543 | "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x", | |
8544 | phy->tx_preemphasis[0], phy->tx_preemphasis[1]); | |
8545 | elink_cl45_write(sc, phy, | |
8546 | MDIO_PMA_DEVAD, | |
8547 | MDIO_PMA_REG_8726_TX_CTRL1, | |
8548 | phy->tx_preemphasis[0]); | |
8549 | ||
8550 | elink_cl45_write(sc, phy, | |
8551 | MDIO_PMA_DEVAD, | |
8552 | MDIO_PMA_REG_8726_TX_CTRL2, | |
8553 | phy->tx_preemphasis[1]); | |
8554 | } | |
8555 | ||
8556 | return ELINK_STATUS_OK; | |
8557 | ||
8558 | } | |
8559 | ||
8560 | static void elink_8726_link_reset(struct elink_phy *phy, | |
8561 | struct elink_params *params) | |
8562 | { | |
8563 | struct bnx2x_softc *sc = params->sc; | |
8564 | PMD_DRV_LOG(DEBUG, "elink_8726_link_reset port %d", params->port); | |
8565 | /* Set serial boot control for external load */ | |
8566 | elink_cl45_write(sc, phy, | |
8567 | MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); | |
8568 | } | |
8569 | ||
8570 | /******************************************************************/ | |
8571 | /* BNX2X8727 PHY SECTION */ | |
8572 | /******************************************************************/ | |
8573 | ||
8574 | static void elink_8727_set_link_led(struct elink_phy *phy, | |
8575 | struct elink_params *params, uint8_t mode) | |
8576 | { | |
8577 | struct bnx2x_softc *sc = params->sc; | |
8578 | uint16_t led_mode_bitmask = 0; | |
8579 | uint16_t gpio_pins_bitmask = 0; | |
8580 | uint16_t val; | |
8581 | /* Only NOC flavor requires to set the LED specifically */ | |
8582 | if (!(phy->flags & ELINK_FLAGS_NOC)) | |
8583 | return; | |
8584 | switch (mode) { | |
8585 | case ELINK_LED_MODE_FRONT_PANEL_OFF: | |
8586 | case ELINK_LED_MODE_OFF: | |
8587 | led_mode_bitmask = 0; | |
8588 | gpio_pins_bitmask = 0x03; | |
8589 | break; | |
8590 | case ELINK_LED_MODE_ON: | |
8591 | led_mode_bitmask = 0; | |
8592 | gpio_pins_bitmask = 0x02; | |
8593 | break; | |
8594 | case ELINK_LED_MODE_OPER: | |
8595 | led_mode_bitmask = 0x60; | |
8596 | gpio_pins_bitmask = 0x11; | |
8597 | break; | |
8598 | } | |
8599 | elink_cl45_read(sc, phy, | |
8600 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, &val); | |
8601 | val &= 0xff8f; | |
8602 | val |= led_mode_bitmask; | |
8603 | elink_cl45_write(sc, phy, | |
8604 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val); | |
8605 | elink_cl45_read(sc, phy, | |
8606 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, &val); | |
8607 | val &= 0xffe0; | |
8608 | val |= gpio_pins_bitmask; | |
8609 | elink_cl45_write(sc, phy, | |
8610 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val); | |
8611 | } | |
8612 | ||
8613 | static void elink_8727_hw_reset(__rte_unused struct elink_phy *phy, | |
8614 | struct elink_params *params) | |
8615 | { | |
8616 | uint32_t swap_val, swap_override; | |
8617 | uint8_t port; | |
8618 | /* The PHY reset is controlled by GPIO 1. Fake the port number | |
8619 | * to cancel the swap done in set_gpio() | |
8620 | */ | |
8621 | struct bnx2x_softc *sc = params->sc; | |
8622 | swap_val = REG_RD(sc, NIG_REG_PORT_SWAP); | |
8623 | swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE); | |
8624 | port = (swap_val && swap_override) ^ 1; | |
8625 | elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1, | |
8626 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); | |
8627 | } | |
8628 | ||
8629 | static void elink_8727_config_speed(struct elink_phy *phy, | |
8630 | struct elink_params *params) | |
8631 | { | |
8632 | struct bnx2x_softc *sc = params->sc; | |
8633 | uint16_t tmp1, val; | |
8634 | /* Set option 1G speed */ | |
8635 | if ((phy->req_line_speed == ELINK_SPEED_1000) || | |
8636 | (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) { | |
8637 | PMD_DRV_LOG(DEBUG, "Setting 1G force"); | |
8638 | elink_cl45_write(sc, phy, | |
8639 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); | |
8640 | elink_cl45_write(sc, phy, | |
8641 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); | |
8642 | elink_cl45_read(sc, phy, | |
8643 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); | |
8644 | PMD_DRV_LOG(DEBUG, "1.7 = 0x%x", tmp1); | |
8645 | /* Power down the XAUI until link is up in case of dual-media | |
8646 | * and 1G | |
8647 | */ | |
8648 | if (ELINK_DUAL_MEDIA(params)) { | |
8649 | elink_cl45_read(sc, phy, | |
8650 | MDIO_PMA_DEVAD, | |
8651 | MDIO_PMA_REG_8727_PCS_GP, &val); | |
8652 | val |= (3 << 10); | |
8653 | elink_cl45_write(sc, phy, | |
8654 | MDIO_PMA_DEVAD, | |
8655 | MDIO_PMA_REG_8727_PCS_GP, val); | |
8656 | } | |
8657 | } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && | |
8658 | ((phy->speed_cap_mask & | |
8659 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && | |
8660 | ((phy->speed_cap_mask & | |
8661 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != | |
8662 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { | |
8663 | ||
8664 | PMD_DRV_LOG(DEBUG, "Setting 1G clause37"); | |
8665 | elink_cl45_write(sc, phy, | |
8666 | MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); | |
8667 | elink_cl45_write(sc, phy, | |
8668 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); | |
8669 | } else { | |
8670 | /* Since the 8727 has only single reset pin, need to set the 10G | |
8671 | * registers although it is default | |
8672 | */ | |
8673 | elink_cl45_write(sc, phy, | |
8674 | MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, | |
8675 | 0x0020); | |
8676 | elink_cl45_write(sc, phy, | |
8677 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); | |
8678 | elink_cl45_write(sc, phy, | |
8679 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); | |
8680 | elink_cl45_write(sc, phy, | |
8681 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, | |
8682 | 0x0008); | |
8683 | } | |
8684 | } | |
8685 | ||
8686 | static elink_status_t elink_8727_config_init(struct elink_phy *phy, | |
8687 | struct elink_params *params, | |
8688 | __rte_unused struct elink_vars | |
8689 | *vars) | |
8690 | { | |
8691 | uint32_t tx_en_mode; | |
8692 | uint16_t tmp1, mod_abs, tmp2; | |
8693 | struct bnx2x_softc *sc = params->sc; | |
8694 | /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ | |
8695 | ||
8696 | elink_wait_reset_complete(sc, phy, params); | |
8697 | ||
8698 | PMD_DRV_LOG(DEBUG, "Initializing BNX2X8727"); | |
8699 | ||
8700 | elink_8727_specific_func(phy, params, ELINK_PHY_INIT); | |
8701 | /* Initially configure MOD_ABS to interrupt when module is | |
8702 | * presence( bit 8) | |
8703 | */ | |
8704 | elink_cl45_read(sc, phy, | |
8705 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); | |
8706 | /* Set EDC off by setting OPTXLOS signal input to low (bit 9). | |
8707 | * When the EDC is off it locks onto a reference clock and avoids | |
8708 | * becoming 'lost' | |
8709 | */ | |
8710 | mod_abs &= ~(1 << 8); | |
8711 | if (!(phy->flags & ELINK_FLAGS_NOC)) | |
8712 | mod_abs &= ~(1 << 9); | |
8713 | elink_cl45_write(sc, phy, | |
8714 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
8715 | ||
8716 | /* Enable/Disable PHY transmitter output */ | |
8717 | elink_set_disable_pmd_transmit(params, phy, 0); | |
8718 | ||
8719 | elink_8727_power_module(sc, phy, 1); | |
8720 | ||
8721 | elink_cl45_read(sc, phy, | |
8722 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); | |
8723 | ||
8724 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); | |
8725 | ||
8726 | elink_8727_config_speed(phy, params); | |
8727 | ||
8728 | /* Set TX PreEmphasis if needed */ | |
8729 | if ((params->feature_config_flags & | |
8730 | ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
8731 | PMD_DRV_LOG(DEBUG, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x", | |
8732 | phy->tx_preemphasis[0], phy->tx_preemphasis[1]); | |
8733 | elink_cl45_write(sc, phy, | |
8734 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1, | |
8735 | phy->tx_preemphasis[0]); | |
8736 | ||
8737 | elink_cl45_write(sc, phy, | |
8738 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2, | |
8739 | phy->tx_preemphasis[1]); | |
8740 | } | |
8741 | ||
8742 | /* If TX Laser is controlled by GPIO_0, do not let PHY go into low | |
8743 | * power mode, if TX Laser is disabled | |
8744 | */ | |
8745 | tx_en_mode = REG_RD(sc, params->shmem_base + | |
8746 | offsetof(struct shmem_region, | |
8747 | dev_info.port_hw_config[params->port]. | |
8748 | sfp_ctrl)) | |
8749 | & PORT_HW_CFG_TX_LASER_MASK; | |
8750 | ||
8751 | if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { | |
8752 | ||
8753 | PMD_DRV_LOG(DEBUG, "Enabling TXONOFF_PWRDN_DIS"); | |
8754 | elink_cl45_read(sc, phy, | |
8755 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, | |
8756 | &tmp2); | |
8757 | tmp2 |= 0x1000; | |
8758 | tmp2 &= 0xFFEF; | |
8759 | elink_cl45_write(sc, phy, | |
8760 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, | |
8761 | tmp2); | |
8762 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, | |
8763 | MDIO_PMA_REG_PHY_IDENTIFIER, &tmp2); | |
8764 | elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, | |
8765 | MDIO_PMA_REG_PHY_IDENTIFIER, (tmp2 & 0x7fff)); | |
8766 | } | |
8767 | ||
8768 | return ELINK_STATUS_OK; | |
8769 | } | |
8770 | ||
8771 | static void elink_8727_handle_mod_abs(struct elink_phy *phy, | |
8772 | struct elink_params *params) | |
8773 | { | |
8774 | struct bnx2x_softc *sc = params->sc; | |
8775 | uint16_t mod_abs, rx_alarm_status; | |
8776 | uint32_t val = REG_RD(sc, params->shmem_base + | |
8777 | offsetof(struct shmem_region, | |
8778 | dev_info.port_feature_config[params-> | |
8779 | port].config)); | |
8780 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, | |
8781 | &mod_abs); | |
8782 | if (mod_abs & (1 << 8)) { | |
8783 | ||
8784 | /* Module is absent */ | |
8785 | PMD_DRV_LOG(DEBUG, "MOD_ABS indication show module is absent"); | |
8786 | phy->media_type = ELINK_ETH_PHY_NOT_PRESENT; | |
8787 | /* 1. Set mod_abs to detect next module | |
8788 | * presence event | |
8789 | * 2. Set EDC off by setting OPTXLOS signal input to low | |
8790 | * (bit 9). | |
8791 | * When the EDC is off it locks onto a reference clock and | |
8792 | * avoids becoming 'lost'. | |
8793 | */ | |
8794 | mod_abs &= ~(1 << 8); | |
8795 | if (!(phy->flags & ELINK_FLAGS_NOC)) | |
8796 | mod_abs &= ~(1 << 9); | |
8797 | elink_cl45_write(sc, phy, | |
8798 | MDIO_PMA_DEVAD, | |
8799 | MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
8800 | ||
8801 | /* Clear RX alarm since it stays up as long as | |
8802 | * the mod_abs wasn't changed | |
8803 | */ | |
8804 | elink_cl45_read(sc, phy, | |
8805 | MDIO_PMA_DEVAD, | |
8806 | MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); | |
8807 | ||
8808 | } else { | |
8809 | /* Module is present */ | |
8810 | PMD_DRV_LOG(DEBUG, "MOD_ABS indication show module is present"); | |
8811 | /* First disable transmitter, and if the module is ok, the | |
8812 | * module_detection will enable it | |
8813 | * 1. Set mod_abs to detect next module absent event ( bit 8) | |
8814 | * 2. Restore the default polarity of the OPRXLOS signal and | |
8815 | * this signal will then correctly indicate the presence or | |
8816 | * absence of the Rx signal. (bit 9) | |
8817 | */ | |
8818 | mod_abs |= (1 << 8); | |
8819 | if (!(phy->flags & ELINK_FLAGS_NOC)) | |
8820 | mod_abs |= (1 << 9); | |
8821 | elink_cl45_write(sc, phy, | |
8822 | MDIO_PMA_DEVAD, | |
8823 | MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
8824 | ||
8825 | /* Clear RX alarm since it stays up as long as the mod_abs | |
8826 | * wasn't changed. This is need to be done before calling the | |
8827 | * module detection, otherwise it will clear* the link update | |
8828 | * alarm | |
8829 | */ | |
8830 | elink_cl45_read(sc, phy, | |
8831 | MDIO_PMA_DEVAD, | |
8832 | MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); | |
8833 | ||
8834 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == | |
8835 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) | |
8836 | elink_sfp_set_transmitter(params, phy, 0); | |
8837 | ||
8838 | if (elink_wait_for_sfp_module_initialized(phy, params) == 0) { | |
8839 | elink_sfp_module_detection(phy, params); | |
8840 | } else { | |
8841 | PMD_DRV_LOG(DEBUG, "SFP+ module is not initialized"); | |
8842 | } | |
8843 | ||
8844 | /* Reconfigure link speed based on module type limitations */ | |
8845 | elink_8727_config_speed(phy, params); | |
8846 | } | |
8847 | ||
8848 | PMD_DRV_LOG(DEBUG, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status); | |
8849 | /* No need to check link status in case of module plugged in/out */ | |
8850 | } | |
8851 | ||
8852 | static uint8_t elink_8727_read_status(struct elink_phy *phy, | |
8853 | struct elink_params *params, | |
8854 | struct elink_vars *vars) | |
8855 | { | |
8856 | struct bnx2x_softc *sc = params->sc; | |
8857 | uint8_t link_up = 0, oc_port = params->port; | |
8858 | uint16_t link_status = 0; | |
8859 | uint16_t rx_alarm_status, lasi_ctrl, val1; | |
8860 | ||
8861 | /* If PHY is not initialized, do not check link status */ | |
8862 | elink_cl45_read(sc, phy, | |
8863 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, &lasi_ctrl); | |
8864 | if (!lasi_ctrl) | |
8865 | return 0; | |
8866 | ||
8867 | /* Check the LASI on Rx */ | |
8868 | elink_cl45_read(sc, phy, | |
8869 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); | |
8870 | vars->line_speed = 0; | |
8871 | PMD_DRV_LOG(DEBUG, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status); | |
8872 | ||
8873 | elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT, | |
8874 | MDIO_PMA_LASI_TXCTRL); | |
8875 | ||
8876 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); | |
8877 | ||
8878 | PMD_DRV_LOG(DEBUG, "8727 LASI status 0x%x", val1); | |
8879 | ||
8880 | /* Clear MSG-OUT */ | |
8881 | elink_cl45_read(sc, phy, | |
8882 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); | |
8883 | ||
8884 | /* If a module is present and there is need to check | |
8885 | * for over current | |
8886 | */ | |
8887 | if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1 << 5))) { | |
8888 | /* Check over-current using 8727 GPIO0 input */ | |
8889 | elink_cl45_read(sc, phy, | |
8890 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, | |
8891 | &val1); | |
8892 | ||
8893 | if ((val1 & (1 << 8)) == 0) { | |
8894 | if (!CHIP_IS_E1x(sc)) | |
8895 | oc_port = SC_PATH(sc) + (params->port << 1); | |
8896 | PMD_DRV_LOG(DEBUG, | |
8897 | "8727 Power fault has been detected on port %d", | |
8898 | oc_port); | |
8899 | elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, oc_port); //"Error: Power fault on Port %d has " | |
8900 | // "been detected and the power to " | |
8901 | // "that SFP+ module has been removed " | |
8902 | // "to prevent failure of the card. " | |
8903 | // "Please remove the SFP+ module and " | |
8904 | // "restart the system to clear this " | |
8905 | // "error.", | |
8906 | /* Disable all RX_ALARMs except for mod_abs */ | |
8907 | elink_cl45_write(sc, phy, | |
8908 | MDIO_PMA_DEVAD, | |
8909 | MDIO_PMA_LASI_RXCTRL, (1 << 5)); | |
8910 | ||
8911 | elink_cl45_read(sc, phy, | |
8912 | MDIO_PMA_DEVAD, | |
8913 | MDIO_PMA_REG_PHY_IDENTIFIER, &val1); | |
8914 | /* Wait for module_absent_event */ | |
8915 | val1 |= (1 << 8); | |
8916 | elink_cl45_write(sc, phy, | |
8917 | MDIO_PMA_DEVAD, | |
8918 | MDIO_PMA_REG_PHY_IDENTIFIER, val1); | |
8919 | /* Clear RX alarm */ | |
8920 | elink_cl45_read(sc, phy, | |
8921 | MDIO_PMA_DEVAD, | |
8922 | MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); | |
8923 | elink_8727_power_module(params->sc, phy, 0); | |
8924 | return 0; | |
8925 | } | |
8926 | } | |
8927 | ||
8928 | /* Over current check */ | |
8929 | /* When module absent bit is set, check module */ | |
8930 | if (rx_alarm_status & (1 << 5)) { | |
8931 | elink_8727_handle_mod_abs(phy, params); | |
8932 | /* Enable all mod_abs and link detection bits */ | |
8933 | elink_cl45_write(sc, phy, | |
8934 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, | |
8935 | ((1 << 5) | (1 << 2))); | |
8936 | } | |
8937 | ||
8938 | if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) { | |
8939 | PMD_DRV_LOG(DEBUG, "Enabling 8727 TX laser"); | |
8940 | elink_sfp_set_transmitter(params, phy, 1); | |
8941 | } else { | |
8942 | PMD_DRV_LOG(DEBUG, "Tx is disabled"); | |
8943 | return 0; | |
8944 | } | |
8945 | ||
8946 | elink_cl45_read(sc, phy, | |
8947 | MDIO_PMA_DEVAD, | |
8948 | MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status); | |
8949 | ||
8950 | /* Bits 0..2 --> speed detected, | |
8951 | * Bits 13..15--> link is down | |
8952 | */ | |
8953 | if ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) { | |
8954 | link_up = 1; | |
8955 | vars->line_speed = ELINK_SPEED_10000; | |
8956 | PMD_DRV_LOG(DEBUG, "port %x: External link up in 10G", | |
8957 | params->port); | |
8958 | } else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) { | |
8959 | link_up = 1; | |
8960 | vars->line_speed = ELINK_SPEED_1000; | |
8961 | PMD_DRV_LOG(DEBUG, "port %x: External link up in 1G", | |
8962 | params->port); | |
8963 | } else { | |
8964 | link_up = 0; | |
8965 | PMD_DRV_LOG(DEBUG, "port %x: External link is down", | |
8966 | params->port); | |
8967 | } | |
8968 | ||
8969 | /* Capture 10G link fault. */ | |
8970 | if (vars->line_speed == ELINK_SPEED_10000) { | |
8971 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, | |
8972 | MDIO_PMA_LASI_TXSTAT, &val1); | |
8973 | ||
8974 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, | |
8975 | MDIO_PMA_LASI_TXSTAT, &val1); | |
8976 | ||
8977 | if (val1 & (1 << 0)) { | |
8978 | vars->fault_detected = 1; | |
8979 | } | |
8980 | } | |
8981 | ||
8982 | if (link_up) { | |
8983 | elink_ext_phy_resolve_fc(phy, params, vars); | |
8984 | vars->duplex = DUPLEX_FULL; | |
8985 | PMD_DRV_LOG(DEBUG, "duplex = 0x%x", vars->duplex); | |
8986 | } | |
8987 | ||
8988 | if ((ELINK_DUAL_MEDIA(params)) && | |
8989 | (phy->req_line_speed == ELINK_SPEED_1000)) { | |
8990 | elink_cl45_read(sc, phy, | |
8991 | MDIO_PMA_DEVAD, | |
8992 | MDIO_PMA_REG_8727_PCS_GP, &val1); | |
8993 | /* In case of dual-media board and 1G, power up the XAUI side, | |
8994 | * otherwise power it down. For 10G it is done automatically | |
8995 | */ | |
8996 | if (link_up) | |
8997 | val1 &= ~(3 << 10); | |
8998 | else | |
8999 | val1 |= (3 << 10); | |
9000 | elink_cl45_write(sc, phy, | |
9001 | MDIO_PMA_DEVAD, | |
9002 | MDIO_PMA_REG_8727_PCS_GP, val1); | |
9003 | } | |
9004 | return link_up; | |
9005 | } | |
9006 | ||
9007 | static void elink_8727_link_reset(struct elink_phy *phy, | |
9008 | struct elink_params *params) | |
9009 | { | |
9010 | struct bnx2x_softc *sc = params->sc; | |
9011 | ||
9012 | /* Enable/Disable PHY transmitter output */ | |
9013 | elink_set_disable_pmd_transmit(params, phy, 1); | |
9014 | ||
9015 | /* Disable Transmitter */ | |
9016 | elink_sfp_set_transmitter(params, phy, 0); | |
9017 | /* Clear LASI */ | |
9018 | elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); | |
9019 | ||
9020 | } | |
9021 | ||
9022 | /******************************************************************/ | |
9023 | /* BNX2X8481/BNX2X84823/BNX2X84833 PHY SECTION */ | |
9024 | /******************************************************************/ | |
9025 | static void elink_save_848xx_spirom_version(struct elink_phy *phy, | |
9026 | struct bnx2x_softc *sc, uint8_t port) | |
9027 | { | |
9028 | uint16_t val, fw_ver2, cnt, i; | |
9029 | static struct elink_reg_set reg_set[] = { | |
9030 | {MDIO_PMA_DEVAD, 0xA819, 0x0014}, | |
9031 | {MDIO_PMA_DEVAD, 0xA81A, 0xc200}, | |
9032 | {MDIO_PMA_DEVAD, 0xA81B, 0x0000}, | |
9033 | {MDIO_PMA_DEVAD, 0xA81C, 0x0300}, | |
9034 | {MDIO_PMA_DEVAD, 0xA817, 0x0009} | |
9035 | }; | |
9036 | uint16_t fw_ver1; | |
9037 | ||
9038 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) || | |
9039 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) { | |
9040 | elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); | |
9041 | elink_save_spirom_version(sc, port, fw_ver1 & 0xfff, | |
9042 | phy->ver_addr); | |
9043 | } else { | |
9044 | /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ | |
9045 | /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ | |
9046 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) | |
9047 | elink_cl45_write(sc, phy, reg_set[i].devad, | |
9048 | reg_set[i].reg, reg_set[i].val); | |
9049 | ||
9050 | for (cnt = 0; cnt < 100; cnt++) { | |
9051 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val); | |
9052 | if (val & 1) | |
9053 | break; | |
9054 | DELAY(5); | |
9055 | } | |
9056 | if (cnt == 100) { | |
9057 | PMD_DRV_LOG(DEBUG, "Unable to read 848xx " | |
9058 | "phy fw version(1)"); | |
9059 | elink_save_spirom_version(sc, port, 0, phy->ver_addr); | |
9060 | return; | |
9061 | } | |
9062 | ||
9063 | /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ | |
9064 | elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); | |
9065 | elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); | |
9066 | elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); | |
9067 | for (cnt = 0; cnt < 100; cnt++) { | |
9068 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val); | |
9069 | if (val & 1) | |
9070 | break; | |
9071 | DELAY(5); | |
9072 | } | |
9073 | if (cnt == 100) { | |
9074 | PMD_DRV_LOG(DEBUG, "Unable to read 848xx phy fw " | |
9075 | "version(2)"); | |
9076 | elink_save_spirom_version(sc, port, 0, phy->ver_addr); | |
9077 | return; | |
9078 | } | |
9079 | ||
9080 | /* lower 16 bits of the register SPI_FW_STATUS */ | |
9081 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); | |
9082 | /* upper 16 bits of register SPI_FW_STATUS */ | |
9083 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); | |
9084 | ||
9085 | elink_save_spirom_version(sc, port, (fw_ver2 << 16) | fw_ver1, | |
9086 | phy->ver_addr); | |
9087 | } | |
9088 | ||
9089 | } | |
9090 | ||
9091 | static void elink_848xx_set_led(struct bnx2x_softc *sc, struct elink_phy *phy) | |
9092 | { | |
9093 | uint16_t val, offset, i; | |
9094 | static struct elink_reg_set reg_set[] = { | |
9095 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080}, | |
9096 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018}, | |
9097 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006}, | |
9098 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000}, | |
9099 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH, | |
9100 | MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ}, | |
9101 | {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD} | |
9102 | }; | |
9103 | /* PHYC_CTL_LED_CTL */ | |
9104 | elink_cl45_read(sc, phy, | |
9105 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, &val); | |
9106 | val &= 0xFE00; | |
9107 | val |= 0x0092; | |
9108 | ||
9109 | elink_cl45_write(sc, phy, | |
9110 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, val); | |
9111 | ||
9112 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) | |
9113 | elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg, | |
9114 | reg_set[i].val); | |
9115 | ||
9116 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) || | |
9117 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) | |
9118 | offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1; | |
9119 | else | |
9120 | offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1; | |
9121 | ||
9122 | /* stretch_en for LED3 */ | |
9123 | elink_cl45_read_or_write(sc, phy, | |
9124 | MDIO_PMA_DEVAD, offset, | |
9125 | MDIO_PMA_REG_84823_LED3_STRETCH_EN); | |
9126 | } | |
9127 | ||
9128 | static void elink_848xx_specific_func(struct elink_phy *phy, | |
9129 | struct elink_params *params, | |
9130 | uint32_t action) | |
9131 | { | |
9132 | struct bnx2x_softc *sc = params->sc; | |
9133 | switch (action) { | |
9134 | case ELINK_PHY_INIT: | |
9135 | if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) && | |
9136 | (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) { | |
9137 | /* Save spirom version */ | |
9138 | elink_save_848xx_spirom_version(phy, sc, params->port); | |
9139 | } | |
9140 | /* This phy uses the NIG latch mechanism since link indication | |
9141 | * arrives through its LED4 and not via its LASI signal, so we | |
9142 | * get steady signal instead of clear on read | |
9143 | */ | |
9144 | elink_bits_en(sc, NIG_REG_LATCH_BC_0 + params->port * 4, | |
9145 | 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT); | |
9146 | ||
9147 | elink_848xx_set_led(sc, phy); | |
9148 | break; | |
9149 | } | |
9150 | } | |
9151 | ||
9152 | static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy, | |
9153 | struct elink_params *params, | |
9154 | struct elink_vars *vars) | |
9155 | { | |
9156 | struct bnx2x_softc *sc = params->sc; | |
9157 | uint16_t autoneg_val, an_1000_val, an_10_100_val; | |
9158 | ||
9159 | elink_848xx_specific_func(phy, params, ELINK_PHY_INIT); | |
9160 | elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); | |
9161 | ||
9162 | /* set 1000 speed advertisement */ | |
9163 | elink_cl45_read(sc, phy, | |
9164 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, | |
9165 | &an_1000_val); | |
9166 | ||
9167 | elink_ext_phy_set_pause(params, phy, vars); | |
9168 | elink_cl45_read(sc, phy, | |
9169 | MDIO_AN_DEVAD, | |
9170 | MDIO_AN_REG_8481_LEGACY_AN_ADV, &an_10_100_val); | |
9171 | elink_cl45_read(sc, phy, | |
9172 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, | |
9173 | &autoneg_val); | |
9174 | /* Disable forced speed */ | |
9175 | autoneg_val &= | |
9176 | ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13)); | |
9177 | an_10_100_val &= ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8)); | |
9178 | ||
9179 | if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && | |
9180 | (phy->speed_cap_mask & | |
9181 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || | |
9182 | (phy->req_line_speed == ELINK_SPEED_1000)) { | |
9183 | an_1000_val |= (1 << 8); | |
9184 | autoneg_val |= (1 << 9 | 1 << 12); | |
9185 | if (phy->req_duplex == DUPLEX_FULL) | |
9186 | an_1000_val |= (1 << 9); | |
9187 | PMD_DRV_LOG(DEBUG, "Advertising 1G"); | |
9188 | } else | |
9189 | an_1000_val &= ~((1 << 8) | (1 << 9)); | |
9190 | ||
9191 | elink_cl45_write(sc, phy, | |
9192 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, | |
9193 | an_1000_val); | |
9194 | ||
9195 | /* Set 10/100 speed advertisement */ | |
9196 | if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { | |
9197 | if (phy->speed_cap_mask & | |
9198 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { | |
9199 | /* Enable autoneg and restart autoneg for legacy speeds | |
9200 | */ | |
9201 | autoneg_val |= (1 << 9 | 1 << 12); | |
9202 | an_10_100_val |= (1 << 8); | |
9203 | PMD_DRV_LOG(DEBUG, "Advertising 100M-FD"); | |
9204 | } | |
9205 | ||
9206 | if (phy->speed_cap_mask & | |
9207 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { | |
9208 | /* Enable autoneg and restart autoneg for legacy speeds | |
9209 | */ | |
9210 | autoneg_val |= (1 << 9 | 1 << 12); | |
9211 | an_10_100_val |= (1 << 7); | |
9212 | PMD_DRV_LOG(DEBUG, "Advertising 100M-HD"); | |
9213 | } | |
9214 | ||
9215 | if ((phy->speed_cap_mask & | |
9216 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && | |
9217 | (phy->supported & ELINK_SUPPORTED_10baseT_Full)) { | |
9218 | an_10_100_val |= (1 << 6); | |
9219 | autoneg_val |= (1 << 9 | 1 << 12); | |
9220 | PMD_DRV_LOG(DEBUG, "Advertising 10M-FD"); | |
9221 | } | |
9222 | ||
9223 | if ((phy->speed_cap_mask & | |
9224 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) && | |
9225 | (phy->supported & ELINK_SUPPORTED_10baseT_Half)) { | |
9226 | an_10_100_val |= (1 << 5); | |
9227 | autoneg_val |= (1 << 9 | 1 << 12); | |
9228 | PMD_DRV_LOG(DEBUG, "Advertising 10M-HD"); | |
9229 | } | |
9230 | } | |
9231 | ||
9232 | /* Only 10/100 are allowed to work in FORCE mode */ | |
9233 | if ((phy->req_line_speed == ELINK_SPEED_100) && | |
9234 | (phy->supported & | |
9235 | (ELINK_SUPPORTED_100baseT_Half | ELINK_SUPPORTED_100baseT_Full))) { | |
9236 | autoneg_val |= (1 << 13); | |
9237 | /* Enabled AUTO-MDIX when autoneg is disabled */ | |
9238 | elink_cl45_write(sc, phy, | |
9239 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, | |
9240 | (1 << 15 | 1 << 9 | 7 << 0)); | |
9241 | /* The PHY needs this set even for forced link. */ | |
9242 | an_10_100_val |= (1 << 8) | (1 << 7); | |
9243 | PMD_DRV_LOG(DEBUG, "Setting 100M force"); | |
9244 | } | |
9245 | if ((phy->req_line_speed == ELINK_SPEED_10) && | |
9246 | (phy->supported & | |
9247 | (ELINK_SUPPORTED_10baseT_Half | ELINK_SUPPORTED_10baseT_Full))) { | |
9248 | /* Enabled AUTO-MDIX when autoneg is disabled */ | |
9249 | elink_cl45_write(sc, phy, | |
9250 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, | |
9251 | (1 << 15 | 1 << 9 | 7 << 0)); | |
9252 | PMD_DRV_LOG(DEBUG, "Setting 10M force"); | |
9253 | } | |
9254 | ||
9255 | elink_cl45_write(sc, phy, | |
9256 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV, | |
9257 | an_10_100_val); | |
9258 | ||
9259 | if (phy->req_duplex == DUPLEX_FULL) | |
9260 | autoneg_val |= (1 << 8); | |
9261 | ||
9262 | /* Always write this if this is not 84833/4. | |
9263 | * For 84833/4, write it only when it's a forced speed. | |
9264 | */ | |
9265 | if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) && | |
9266 | (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) || | |
9267 | ((autoneg_val & (1 << 12)) == 0)) | |
9268 | elink_cl45_write(sc, phy, | |
9269 | MDIO_AN_DEVAD, | |
9270 | MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); | |
9271 | ||
9272 | if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && | |
9273 | (phy->speed_cap_mask & | |
9274 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || | |
9275 | (phy->req_line_speed == ELINK_SPEED_10000)) { | |
9276 | PMD_DRV_LOG(DEBUG, "Advertising 10G"); | |
9277 | /* Restart autoneg for 10G */ | |
9278 | ||
9279 | elink_cl45_read_or_write(sc, phy, | |
9280 | MDIO_AN_DEVAD, | |
9281 | MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, | |
9282 | 0x1000); | |
9283 | elink_cl45_write(sc, phy, | |
9284 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x3200); | |
9285 | } else | |
9286 | elink_cl45_write(sc, phy, | |
9287 | MDIO_AN_DEVAD, | |
9288 | MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 1); | |
9289 | ||
9290 | return ELINK_STATUS_OK; | |
9291 | } | |
9292 | ||
9293 | static elink_status_t elink_8481_config_init(struct elink_phy *phy, | |
9294 | struct elink_params *params, | |
9295 | struct elink_vars *vars) | |
9296 | { | |
9297 | struct bnx2x_softc *sc = params->sc; | |
9298 | /* Restore normal power mode */ | |
9299 | elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, | |
9300 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); | |
9301 | ||
9302 | /* HW reset */ | |
9303 | elink_ext_phy_hw_reset(sc, params->port); | |
9304 | elink_wait_reset_complete(sc, phy, params); | |
9305 | ||
9306 | elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15); | |
9307 | return elink_848xx_cmn_config_init(phy, params, vars); | |
9308 | } | |
9309 | ||
9310 | #define PHY84833_CMDHDLR_WAIT 300 | |
9311 | #define PHY84833_CMDHDLR_MAX_ARGS 5 | |
9312 | static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy, | |
9313 | struct elink_params *params, | |
9314 | uint16_t fw_cmd, uint16_t cmd_args[], | |
9315 | int argc) | |
9316 | { | |
9317 | int idx; | |
9318 | uint16_t val; | |
9319 | struct bnx2x_softc *sc = params->sc; | |
9320 | /* Write CMD_OPEN_OVERRIDE to STATUS reg */ | |
9321 | elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, | |
9322 | MDIO_84833_CMD_HDLR_STATUS, | |
9323 | PHY84833_STATUS_CMD_OPEN_OVERRIDE); | |
9324 | for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { | |
9325 | elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, | |
9326 | MDIO_84833_CMD_HDLR_STATUS, &val); | |
9327 | if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) | |
9328 | break; | |
9329 | DELAY(1000 * 1); | |
9330 | } | |
9331 | if (idx >= PHY84833_CMDHDLR_WAIT) { | |
9332 | PMD_DRV_LOG(DEBUG, "FW cmd: FW not ready."); | |
9333 | return ELINK_STATUS_ERROR; | |
9334 | } | |
9335 | ||
9336 | /* Prepare argument(s) and issue command */ | |
9337 | for (idx = 0; idx < argc; idx++) { | |
9338 | elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, | |
9339 | MDIO_84833_CMD_HDLR_DATA1 + idx, | |
9340 | cmd_args[idx]); | |
9341 | } | |
9342 | elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, | |
9343 | MDIO_84833_CMD_HDLR_COMMAND, fw_cmd); | |
9344 | for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { | |
9345 | elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, | |
9346 | MDIO_84833_CMD_HDLR_STATUS, &val); | |
9347 | if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || | |
9348 | (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) | |
9349 | break; | |
9350 | DELAY(1000 * 1); | |
9351 | } | |
9352 | if ((idx >= PHY84833_CMDHDLR_WAIT) || | |
9353 | (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { | |
9354 | PMD_DRV_LOG(DEBUG, "FW cmd failed."); | |
9355 | return ELINK_STATUS_ERROR; | |
9356 | } | |
9357 | /* Gather returning data */ | |
9358 | for (idx = 0; idx < argc; idx++) { | |
9359 | elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, | |
9360 | MDIO_84833_CMD_HDLR_DATA1 + idx, | |
9361 | &cmd_args[idx]); | |
9362 | } | |
9363 | elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, | |
9364 | MDIO_84833_CMD_HDLR_STATUS, | |
9365 | PHY84833_STATUS_CMD_CLEAR_COMPLETE); | |
9366 | return ELINK_STATUS_OK; | |
9367 | } | |
9368 | ||
9369 | static elink_status_t elink_84833_pair_swap_cfg(struct elink_phy *phy, | |
9370 | struct elink_params *params, | |
9371 | __rte_unused struct elink_vars | |
9372 | *vars) | |
9373 | { | |
9374 | uint32_t pair_swap; | |
9375 | uint16_t data[PHY84833_CMDHDLR_MAX_ARGS]; | |
9376 | elink_status_t status; | |
9377 | struct bnx2x_softc *sc = params->sc; | |
9378 | ||
9379 | /* Check for configuration. */ | |
9380 | pair_swap = REG_RD(sc, params->shmem_base + | |
9381 | offsetof(struct shmem_region, | |
9382 | dev_info.port_hw_config[params->port]. | |
9383 | xgbt_phy_cfg)) & | |
9384 | PORT_HW_CFG_RJ45_PAIR_SWAP_MASK; | |
9385 | ||
9386 | if (pair_swap == 0) | |
9387 | return ELINK_STATUS_OK; | |
9388 | ||
9389 | /* Only the second argument is used for this command */ | |
9390 | data[1] = (uint16_t) pair_swap; | |
9391 | ||
9392 | status = elink_84833_cmd_hdlr(phy, params, | |
9393 | PHY84833_CMD_SET_PAIR_SWAP, data, | |
9394 | PHY84833_CMDHDLR_MAX_ARGS); | |
9395 | if (status == ELINK_STATUS_OK) { | |
9396 | PMD_DRV_LOG(DEBUG, "Pairswap OK, val=0x%x", data[1]); | |
9397 | } | |
9398 | ||
9399 | return status; | |
9400 | } | |
9401 | ||
9402 | static uint8_t elink_84833_get_reset_gpios(struct bnx2x_softc *sc, | |
9403 | uint32_t shmem_base_path[], | |
9404 | __rte_unused uint32_t chip_id) | |
9405 | { | |
9406 | uint32_t reset_pin[2]; | |
9407 | uint32_t idx; | |
9408 | uint8_t reset_gpios; | |
9409 | if (CHIP_IS_E3(sc)) { | |
9410 | /* Assume that these will be GPIOs, not EPIOs. */ | |
9411 | for (idx = 0; idx < 2; idx++) { | |
9412 | /* Map config param to register bit. */ | |
9413 | reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] + | |
9414 | offsetof(struct shmem_region, | |
9415 | dev_info. | |
9416 | port_hw_config[0]. | |
9417 | e3_cmn_pin_cfg)); | |
9418 | reset_pin[idx] = | |
9419 | (reset_pin[idx] & PORT_HW_CFG_E3_PHY_RESET_MASK) >> | |
9420 | PORT_HW_CFG_E3_PHY_RESET_SHIFT; | |
9421 | reset_pin[idx] -= PIN_CFG_GPIO0_P0; | |
9422 | reset_pin[idx] = (1 << reset_pin[idx]); | |
9423 | } | |
9424 | reset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]); | |
9425 | } else { | |
9426 | /* E2, look from diff place of shmem. */ | |
9427 | for (idx = 0; idx < 2; idx++) { | |
9428 | reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] + | |
9429 | offsetof(struct shmem_region, | |
9430 | dev_info. | |
9431 | port_hw_config[0]. | |
9432 | default_cfg)); | |
9433 | reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK; | |
9434 | reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0; | |
9435 | reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT; | |
9436 | reset_pin[idx] = (1 << reset_pin[idx]); | |
9437 | } | |
9438 | reset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]); | |
9439 | } | |
9440 | ||
9441 | return reset_gpios; | |
9442 | } | |
9443 | ||
9444 | static elink_status_t elink_84833_hw_reset_phy(struct elink_phy *phy, | |
9445 | struct elink_params *params) | |
9446 | { | |
9447 | struct bnx2x_softc *sc = params->sc; | |
9448 | uint8_t reset_gpios; | |
9449 | uint32_t other_shmem_base_addr = REG_RD(sc, params->shmem2_base + | |
9450 | offsetof(struct shmem2_region, | |
9451 | other_shmem_base_addr)); | |
9452 | ||
9453 | uint32_t shmem_base_path[2]; | |
9454 | ||
9455 | /* Work around for 84833 LED failure inside RESET status */ | |
9456 | elink_cl45_write(sc, phy, MDIO_AN_DEVAD, | |
9457 | MDIO_AN_REG_8481_LEGACY_MII_CTRL, | |
9458 | MDIO_AN_REG_8481_MII_CTRL_FORCE_1G); | |
9459 | elink_cl45_write(sc, phy, MDIO_AN_DEVAD, | |
9460 | MDIO_AN_REG_8481_1G_100T_EXT_CTRL, | |
9461 | MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF); | |
9462 | ||
9463 | shmem_base_path[0] = params->shmem_base; | |
9464 | shmem_base_path[1] = other_shmem_base_addr; | |
9465 | ||
9466 | reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path, | |
9467 | params->chip_id); | |
9468 | ||
9469 | elink_cb_gpio_mult_write(sc, reset_gpios, | |
9470 | MISC_REGISTERS_GPIO_OUTPUT_LOW); | |
9471 | DELAY(10); | |
9472 | PMD_DRV_LOG(DEBUG, "84833 hw reset on pin values 0x%x", reset_gpios); | |
9473 | ||
9474 | return ELINK_STATUS_OK; | |
9475 | } | |
9476 | ||
9477 | static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy, | |
9478 | struct elink_params *params, | |
9479 | struct elink_vars *vars) | |
9480 | { | |
9481 | elink_status_t rc; | |
9482 | uint16_t cmd_args = 0; | |
9483 | ||
9484 | PMD_DRV_LOG(DEBUG, "Don't Advertise 10GBase-T EEE"); | |
9485 | ||
9486 | /* Prevent Phy from working in EEE and advertising it */ | |
9487 | rc = elink_84833_cmd_hdlr(phy, params, | |
9488 | PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); | |
9489 | if (rc != ELINK_STATUS_OK) { | |
9490 | PMD_DRV_LOG(DEBUG, "EEE disable failed."); | |
9491 | return rc; | |
9492 | } | |
9493 | ||
9494 | return elink_eee_disable(phy, params, vars); | |
9495 | } | |
9496 | ||
9497 | static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy, | |
9498 | struct elink_params *params, | |
9499 | struct elink_vars *vars) | |
9500 | { | |
9501 | elink_status_t rc; | |
9502 | uint16_t cmd_args = 1; | |
9503 | ||
9504 | rc = elink_84833_cmd_hdlr(phy, params, | |
9505 | PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); | |
9506 | if (rc != ELINK_STATUS_OK) { | |
9507 | PMD_DRV_LOG(DEBUG, "EEE enable failed."); | |
9508 | return rc; | |
9509 | } | |
9510 | ||
9511 | return elink_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV); | |
9512 | } | |
9513 | ||
9514 | #define PHY84833_CONSTANT_LATENCY 1193 | |
9515 | static elink_status_t elink_848x3_config_init(struct elink_phy *phy, | |
9516 | struct elink_params *params, | |
9517 | struct elink_vars *vars) | |
9518 | { | |
9519 | struct bnx2x_softc *sc = params->sc; | |
9520 | uint8_t port, initialize = 1; | |
9521 | uint16_t val; | |
9522 | uint32_t actual_phy_selection; | |
9523 | uint16_t cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; | |
9524 | elink_status_t rc = ELINK_STATUS_OK; | |
9525 | ||
9526 | DELAY(1000 * 1); | |
9527 | ||
9528 | if (!(CHIP_IS_E1x(sc))) | |
9529 | port = SC_PATH(sc); | |
9530 | else | |
9531 | port = params->port; | |
9532 | ||
9533 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) { | |
9534 | elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3, | |
9535 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); | |
9536 | } else { | |
9537 | /* MDIO reset */ | |
9538 | elink_cl45_write(sc, phy, | |
9539 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x8000); | |
9540 | } | |
9541 | ||
9542 | elink_wait_reset_complete(sc, phy, params); | |
9543 | ||
9544 | /* Wait for GPHY to come out of reset */ | |
9545 | DELAY(1000 * 50); | |
9546 | if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) && | |
9547 | (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) { | |
9548 | /* BNX2X84823 requires that XGXS links up first @ 10G for normal | |
9549 | * behavior. | |
9550 | */ | |
9551 | uint16_t temp; | |
9552 | temp = vars->line_speed; | |
9553 | vars->line_speed = ELINK_SPEED_10000; | |
9554 | elink_set_autoneg(¶ms->phy[ELINK_INT_PHY], params, vars, 0); | |
9555 | elink_program_serdes(¶ms->phy[ELINK_INT_PHY], params, vars); | |
9556 | vars->line_speed = temp; | |
9557 | } | |
9558 | ||
9559 | elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, | |
9560 | MDIO_CTL_REG_84823_MEDIA, &val); | |
9561 | val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | | |
9562 | MDIO_CTL_REG_84823_MEDIA_LINE_MASK | | |
9563 | MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | | |
9564 | MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK | | |
9565 | MDIO_CTL_REG_84823_MEDIA_FIBER_1G); | |
9566 | ||
9567 | if (CHIP_IS_E3(sc)) { | |
9568 | val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | | |
9569 | MDIO_CTL_REG_84823_MEDIA_LINE_MASK); | |
9570 | } else { | |
9571 | val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI | | |
9572 | MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L); | |
9573 | } | |
9574 | ||
9575 | actual_phy_selection = elink_phy_selection(params); | |
9576 | ||
9577 | switch (actual_phy_selection) { | |
9578 | case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: | |
9579 | /* Do nothing. Essentially this is like the priority copper */ | |
9580 | break; | |
9581 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
9582 | val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; | |
9583 | break; | |
9584 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
9585 | val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER; | |
9586 | break; | |
9587 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: | |
9588 | /* Do nothing here. The first PHY won't be initialized at all */ | |
9589 | break; | |
9590 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: | |
9591 | val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN; | |
9592 | initialize = 0; | |
9593 | break; | |
9594 | } | |
9595 | if (params->phy[ELINK_EXT_PHY2].req_line_speed == ELINK_SPEED_1000) | |
9596 | val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; | |
9597 | ||
9598 | elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, | |
9599 | MDIO_CTL_REG_84823_MEDIA, val); | |
9600 | PMD_DRV_LOG(DEBUG, "Multi_phy config = 0x%x, Media control = 0x%x", | |
9601 | params->multi_phy_config, val); | |
9602 | ||
9603 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) || | |
9604 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) { | |
9605 | elink_84833_pair_swap_cfg(phy, params, vars); | |
9606 | ||
9607 | /* Keep AutogrEEEn disabled. */ | |
9608 | cmd_args[0] = 0x0; | |
9609 | cmd_args[1] = 0x0; | |
9610 | cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1; | |
9611 | cmd_args[3] = PHY84833_CONSTANT_LATENCY; | |
9612 | rc = elink_84833_cmd_hdlr(phy, params, | |
9613 | PHY84833_CMD_SET_EEE_MODE, cmd_args, | |
9614 | PHY84833_CMDHDLR_MAX_ARGS); | |
9615 | if (rc != ELINK_STATUS_OK) { | |
9616 | PMD_DRV_LOG(DEBUG, "Cfg AutogrEEEn failed."); | |
9617 | } | |
9618 | } | |
9619 | if (initialize) { | |
9620 | rc = elink_848xx_cmn_config_init(phy, params, vars); | |
9621 | } else { | |
9622 | elink_save_848xx_spirom_version(phy, sc, params->port); | |
9623 | } | |
9624 | /* 84833 PHY has a better feature and doesn't need to support this. */ | |
9625 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) { | |
9626 | uint32_t cms_enable = REG_RD(sc, params->shmem_base + | |
9627 | offsetof(struct shmem_region, | |
9628 | dev_info. | |
9629 | port_hw_config[params-> | |
9630 | port]. | |
9631 | default_cfg)) & | |
9632 | PORT_HW_CFG_ENABLE_CMS_MASK; | |
9633 | ||
9634 | elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, | |
9635 | MDIO_CTL_REG_84823_USER_CTRL_REG, &val); | |
9636 | if (cms_enable) | |
9637 | val |= MDIO_CTL_REG_84823_USER_CTRL_CMS; | |
9638 | else | |
9639 | val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS; | |
9640 | elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, | |
9641 | MDIO_CTL_REG_84823_USER_CTRL_REG, val); | |
9642 | } | |
9643 | ||
9644 | elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, | |
9645 | MDIO_84833_TOP_CFG_FW_REV, &val); | |
9646 | ||
9647 | /* Configure EEE support */ | |
9648 | if ((val >= MDIO_84833_TOP_CFG_FW_EEE) && | |
9649 | (val != MDIO_84833_TOP_CFG_FW_NO_EEE) && | |
9650 | elink_eee_has_cap(params)) { | |
9651 | rc = elink_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV); | |
9652 | if (rc != ELINK_STATUS_OK) { | |
9653 | PMD_DRV_LOG(DEBUG, "Failed to configure EEE timers"); | |
9654 | elink_8483x_disable_eee(phy, params, vars); | |
9655 | return rc; | |
9656 | } | |
9657 | ||
9658 | if ((phy->req_duplex == DUPLEX_FULL) && | |
9659 | (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) && | |
9660 | (elink_eee_calc_timer(params) || | |
9661 | !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) | |
9662 | rc = elink_8483x_enable_eee(phy, params, vars); | |
9663 | else | |
9664 | rc = elink_8483x_disable_eee(phy, params, vars); | |
9665 | if (rc != ELINK_STATUS_OK) { | |
9666 | PMD_DRV_LOG(DEBUG, "Failed to set EEE advertisement"); | |
9667 | return rc; | |
9668 | } | |
9669 | } else { | |
9670 | vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK; | |
9671 | } | |
9672 | ||
9673 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) || | |
9674 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) { | |
9675 | /* Bring PHY out of super isolate mode as the final step. */ | |
9676 | elink_cl45_read_and_write(sc, phy, | |
9677 | MDIO_CTL_DEVAD, | |
9678 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, | |
9679 | (uint16_t) ~ | |
9680 | MDIO_84833_SUPER_ISOLATE); | |
9681 | } | |
9682 | return rc; | |
9683 | } | |
9684 | ||
9685 | static uint8_t elink_848xx_read_status(struct elink_phy *phy, | |
9686 | struct elink_params *params, | |
9687 | struct elink_vars *vars) | |
9688 | { | |
9689 | struct bnx2x_softc *sc = params->sc; | |
9690 | uint16_t val, val1, val2; | |
9691 | uint8_t link_up = 0; | |
9692 | ||
9693 | /* Check 10G-BaseT link status */ | |
9694 | /* Check PMD signal ok */ | |
9695 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 0xFFFA, &val1); | |
9696 | elink_cl45_read(sc, phy, | |
9697 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, &val2); | |
9698 | PMD_DRV_LOG(DEBUG, "BNX2X848xx: PMD_SIGNAL 1.a811 = 0x%x", val2); | |
9699 | ||
9700 | /* Check link 10G */ | |
9701 | if (val2 & (1 << 11)) { | |
9702 | vars->line_speed = ELINK_SPEED_10000; | |
9703 | vars->duplex = DUPLEX_FULL; | |
9704 | link_up = 1; | |
9705 | elink_ext_phy_10G_an_resolve(sc, phy, vars); | |
9706 | } else { /* Check Legacy speed link */ | |
9707 | uint16_t legacy_status, legacy_speed, mii_ctrl; | |
9708 | ||
9709 | /* Enable expansion register 0x42 (Operation mode status) */ | |
9710 | elink_cl45_write(sc, phy, | |
9711 | MDIO_AN_DEVAD, | |
9712 | MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42); | |
9713 | ||
9714 | /* Get legacy speed operation status */ | |
9715 | elink_cl45_read(sc, phy, | |
9716 | MDIO_AN_DEVAD, | |
9717 | MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, | |
9718 | &legacy_status); | |
9719 | ||
9720 | PMD_DRV_LOG(DEBUG, "Legacy speed status = 0x%x", legacy_status); | |
9721 | link_up = ((legacy_status & (1 << 11)) == (1 << 11)); | |
9722 | legacy_speed = (legacy_status & (3 << 9)); | |
9723 | if (legacy_speed == (0 << 9)) | |
9724 | vars->line_speed = ELINK_SPEED_10; | |
9725 | else if (legacy_speed == (1 << 9)) | |
9726 | vars->line_speed = ELINK_SPEED_100; | |
9727 | else if (legacy_speed == (2 << 9)) | |
9728 | vars->line_speed = ELINK_SPEED_1000; | |
9729 | else { /* Should not happen: Treat as link down */ | |
9730 | vars->line_speed = 0; | |
9731 | link_up = 0; | |
9732 | } | |
9733 | ||
9734 | if (params->feature_config_flags & | |
9735 | ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) { | |
9736 | elink_cl45_read(sc, phy, | |
9737 | MDIO_AN_DEVAD, | |
9738 | MDIO_AN_REG_8481_LEGACY_MII_CTRL, | |
9739 | &mii_ctrl); | |
9740 | /* For IEEE testing, check for a fake link. */ | |
9741 | link_up |= ((mii_ctrl & 0x3040) == 0x40); | |
9742 | } | |
9743 | ||
9744 | if (link_up) { | |
9745 | if (legacy_status & (1 << 8)) | |
9746 | vars->duplex = DUPLEX_FULL; | |
9747 | else | |
9748 | vars->duplex = DUPLEX_HALF; | |
9749 | ||
9750 | PMD_DRV_LOG(DEBUG, | |
9751 | "Link is up in %dMbps, is_duplex_full= %d", | |
9752 | vars->line_speed, | |
9753 | (vars->duplex == DUPLEX_FULL)); | |
9754 | /* Check legacy speed AN resolution */ | |
9755 | elink_cl45_read(sc, phy, | |
9756 | MDIO_AN_DEVAD, | |
9757 | MDIO_AN_REG_8481_LEGACY_MII_STATUS, | |
9758 | &val); | |
9759 | if (val & (1 << 5)) | |
9760 | vars->link_status |= | |
9761 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
9762 | elink_cl45_read(sc, phy, | |
9763 | MDIO_AN_DEVAD, | |
9764 | MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, | |
9765 | &val); | |
9766 | if ((val & (1 << 0)) == 0) | |
9767 | vars->link_status |= | |
9768 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
9769 | } | |
9770 | } | |
9771 | if (link_up) { | |
9772 | PMD_DRV_LOG(DEBUG, "BNX2X848x3: link speed is %d", | |
9773 | vars->line_speed); | |
9774 | elink_ext_phy_resolve_fc(phy, params, vars); | |
9775 | ||
9776 | /* Read LP advertised speeds */ | |
9777 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, | |
9778 | MDIO_AN_REG_CL37_FC_LP, &val); | |
9779 | if (val & (1 << 5)) | |
9780 | vars->link_status |= | |
9781 | LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; | |
9782 | if (val & (1 << 6)) | |
9783 | vars->link_status |= | |
9784 | LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; | |
9785 | if (val & (1 << 7)) | |
9786 | vars->link_status |= | |
9787 | LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; | |
9788 | if (val & (1 << 8)) | |
9789 | vars->link_status |= | |
9790 | LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; | |
9791 | if (val & (1 << 9)) | |
9792 | vars->link_status |= | |
9793 | LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; | |
9794 | ||
9795 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, | |
9796 | MDIO_AN_REG_1000T_STATUS, &val); | |
9797 | ||
9798 | if (val & (1 << 10)) | |
9799 | vars->link_status |= | |
9800 | LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; | |
9801 | if (val & (1 << 11)) | |
9802 | vars->link_status |= | |
9803 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
9804 | ||
9805 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, | |
9806 | MDIO_AN_REG_MASTER_STATUS, &val); | |
9807 | ||
9808 | if (val & (1 << 11)) | |
9809 | vars->link_status |= | |
9810 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
9811 | ||
9812 | /* Determine if EEE was negotiated */ | |
9813 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) || | |
9814 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) | |
9815 | elink_eee_an_resolve(phy, params, vars); | |
9816 | } | |
9817 | ||
9818 | return link_up; | |
9819 | } | |
9820 | ||
9821 | static elink_status_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t * str, | |
9822 | uint16_t * len) | |
9823 | { | |
9824 | elink_status_t status = ELINK_STATUS_OK; | |
9825 | uint32_t spirom_ver; | |
9826 | spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F); | |
9827 | status = elink_format_ver(spirom_ver, str, len); | |
9828 | return status; | |
9829 | } | |
9830 | ||
9831 | static void elink_8481_hw_reset(__rte_unused struct elink_phy *phy, | |
9832 | struct elink_params *params) | |
9833 | { | |
9834 | elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1, | |
9835 | MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); | |
9836 | elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1, | |
9837 | MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); | |
9838 | } | |
9839 | ||
9840 | static void elink_8481_link_reset(struct elink_phy *phy, | |
9841 | struct elink_params *params) | |
9842 | { | |
9843 | elink_cl45_write(params->sc, phy, | |
9844 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); | |
9845 | elink_cl45_write(params->sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); | |
9846 | } | |
9847 | ||
9848 | static void elink_848x3_link_reset(struct elink_phy *phy, | |
9849 | struct elink_params *params) | |
9850 | { | |
9851 | struct bnx2x_softc *sc = params->sc; | |
9852 | uint8_t port; | |
9853 | uint16_t val16; | |
9854 | ||
9855 | if (!(CHIP_IS_E1x(sc))) | |
9856 | port = SC_PATH(sc); | |
9857 | else | |
9858 | port = params->port; | |
9859 | ||
9860 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) { | |
9861 | elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3, | |
9862 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); | |
9863 | } else { | |
9864 | elink_cl45_read(sc, phy, | |
9865 | MDIO_CTL_DEVAD, | |
9866 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16); | |
9867 | val16 |= MDIO_84833_SUPER_ISOLATE; | |
9868 | elink_cl45_write(sc, phy, | |
9869 | MDIO_CTL_DEVAD, | |
9870 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16); | |
9871 | } | |
9872 | } | |
9873 | ||
9874 | static void elink_848xx_set_link_led(struct elink_phy *phy, | |
9875 | struct elink_params *params, uint8_t mode) | |
9876 | { | |
9877 | struct bnx2x_softc *sc = params->sc; | |
9878 | uint16_t val; | |
9879 | __rte_unused uint8_t port; | |
9880 | ||
9881 | if (!(CHIP_IS_E1x(sc))) | |
9882 | port = SC_PATH(sc); | |
9883 | else | |
9884 | port = params->port; | |
9885 | ||
9886 | switch (mode) { | |
9887 | case ELINK_LED_MODE_OFF: | |
9888 | ||
9889 | PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE OFF", port); | |
9890 | ||
9891 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
9892 | SHARED_HW_CFG_LED_EXTPHY1) { | |
9893 | ||
9894 | /* Set LED masks */ | |
9895 | elink_cl45_write(sc, phy, | |
9896 | MDIO_PMA_DEVAD, | |
9897 | MDIO_PMA_REG_8481_LED1_MASK, 0x0); | |
9898 | ||
9899 | elink_cl45_write(sc, phy, | |
9900 | MDIO_PMA_DEVAD, | |
9901 | MDIO_PMA_REG_8481_LED2_MASK, 0x0); | |
9902 | ||
9903 | elink_cl45_write(sc, phy, | |
9904 | MDIO_PMA_DEVAD, | |
9905 | MDIO_PMA_REG_8481_LED3_MASK, 0x0); | |
9906 | ||
9907 | elink_cl45_write(sc, phy, | |
9908 | MDIO_PMA_DEVAD, | |
9909 | MDIO_PMA_REG_8481_LED5_MASK, 0x0); | |
9910 | ||
9911 | } else { | |
9912 | elink_cl45_write(sc, phy, | |
9913 | MDIO_PMA_DEVAD, | |
9914 | MDIO_PMA_REG_8481_LED1_MASK, 0x0); | |
9915 | } | |
9916 | break; | |
9917 | case ELINK_LED_MODE_FRONT_PANEL_OFF: | |
9918 | ||
9919 | PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE FRONT PANEL OFF", port); | |
9920 | ||
9921 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
9922 | SHARED_HW_CFG_LED_EXTPHY1) { | |
9923 | ||
9924 | /* Set LED masks */ | |
9925 | elink_cl45_write(sc, phy, | |
9926 | MDIO_PMA_DEVAD, | |
9927 | MDIO_PMA_REG_8481_LED1_MASK, 0x0); | |
9928 | ||
9929 | elink_cl45_write(sc, phy, | |
9930 | MDIO_PMA_DEVAD, | |
9931 | MDIO_PMA_REG_8481_LED2_MASK, 0x0); | |
9932 | ||
9933 | elink_cl45_write(sc, phy, | |
9934 | MDIO_PMA_DEVAD, | |
9935 | MDIO_PMA_REG_8481_LED3_MASK, 0x0); | |
9936 | ||
9937 | elink_cl45_write(sc, phy, | |
9938 | MDIO_PMA_DEVAD, | |
9939 | MDIO_PMA_REG_8481_LED5_MASK, 0x20); | |
9940 | ||
9941 | } else { | |
9942 | elink_cl45_write(sc, phy, | |
9943 | MDIO_PMA_DEVAD, | |
9944 | MDIO_PMA_REG_8481_LED1_MASK, 0x0); | |
9945 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) { | |
9946 | /* Disable MI_INT interrupt before setting LED4 | |
9947 | * source to constant off. | |
9948 | */ | |
9949 | if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + | |
9950 | params->port * 4) & | |
9951 | ELINK_NIG_MASK_MI_INT) { | |
9952 | params->link_flags |= | |
9953 | ELINK_LINK_FLAGS_INT_DISABLED; | |
9954 | ||
9955 | elink_bits_dis(sc, | |
9956 | NIG_REG_MASK_INTERRUPT_PORT0 | |
9957 | + params->port * 4, | |
9958 | ELINK_NIG_MASK_MI_INT); | |
9959 | } | |
9960 | elink_cl45_write(sc, phy, | |
9961 | MDIO_PMA_DEVAD, | |
9962 | MDIO_PMA_REG_8481_SIGNAL_MASK, | |
9963 | 0x0); | |
9964 | } | |
9965 | } | |
9966 | break; | |
9967 | case ELINK_LED_MODE_ON: | |
9968 | ||
9969 | PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE ON", port); | |
9970 | ||
9971 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
9972 | SHARED_HW_CFG_LED_EXTPHY1) { | |
9973 | /* Set control reg */ | |
9974 | elink_cl45_read(sc, phy, | |
9975 | MDIO_PMA_DEVAD, | |
9976 | MDIO_PMA_REG_8481_LINK_SIGNAL, &val); | |
9977 | val &= 0x8000; | |
9978 | val |= 0x2492; | |
9979 | ||
9980 | elink_cl45_write(sc, phy, | |
9981 | MDIO_PMA_DEVAD, | |
9982 | MDIO_PMA_REG_8481_LINK_SIGNAL, val); | |
9983 | ||
9984 | /* Set LED masks */ | |
9985 | elink_cl45_write(sc, phy, | |
9986 | MDIO_PMA_DEVAD, | |
9987 | MDIO_PMA_REG_8481_LED1_MASK, 0x0); | |
9988 | ||
9989 | elink_cl45_write(sc, phy, | |
9990 | MDIO_PMA_DEVAD, | |
9991 | MDIO_PMA_REG_8481_LED2_MASK, 0x20); | |
9992 | ||
9993 | elink_cl45_write(sc, phy, | |
9994 | MDIO_PMA_DEVAD, | |
9995 | MDIO_PMA_REG_8481_LED3_MASK, 0x20); | |
9996 | ||
9997 | elink_cl45_write(sc, phy, | |
9998 | MDIO_PMA_DEVAD, | |
9999 | MDIO_PMA_REG_8481_LED5_MASK, 0x0); | |
10000 | } else { | |
10001 | elink_cl45_write(sc, phy, | |
10002 | MDIO_PMA_DEVAD, | |
10003 | MDIO_PMA_REG_8481_LED1_MASK, 0x20); | |
10004 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) { | |
10005 | /* Disable MI_INT interrupt before setting LED4 | |
10006 | * source to constant on. | |
10007 | */ | |
10008 | if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + | |
10009 | params->port * 4) & | |
10010 | ELINK_NIG_MASK_MI_INT) { | |
10011 | params->link_flags |= | |
10012 | ELINK_LINK_FLAGS_INT_DISABLED; | |
10013 | ||
10014 | elink_bits_dis(sc, | |
10015 | NIG_REG_MASK_INTERRUPT_PORT0 | |
10016 | + params->port * 4, | |
10017 | ELINK_NIG_MASK_MI_INT); | |
10018 | } | |
10019 | elink_cl45_write(sc, phy, | |
10020 | MDIO_PMA_DEVAD, | |
10021 | MDIO_PMA_REG_8481_SIGNAL_MASK, | |
10022 | 0x20); | |
10023 | } | |
10024 | } | |
10025 | break; | |
10026 | ||
10027 | case ELINK_LED_MODE_OPER: | |
10028 | ||
10029 | PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE OPER", port); | |
10030 | ||
10031 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10032 | SHARED_HW_CFG_LED_EXTPHY1) { | |
10033 | ||
10034 | /* Set control reg */ | |
10035 | elink_cl45_read(sc, phy, | |
10036 | MDIO_PMA_DEVAD, | |
10037 | MDIO_PMA_REG_8481_LINK_SIGNAL, &val); | |
10038 | ||
10039 | if (!((val & | |
10040 | MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) | |
10041 | >> | |
10042 | MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) | |
10043 | { | |
10044 | PMD_DRV_LOG(DEBUG, "Setting LINK_SIGNAL"); | |
10045 | elink_cl45_write(sc, phy, | |
10046 | MDIO_PMA_DEVAD, | |
10047 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10048 | 0xa492); | |
10049 | } | |
10050 | ||
10051 | /* Set LED masks */ | |
10052 | elink_cl45_write(sc, phy, | |
10053 | MDIO_PMA_DEVAD, | |
10054 | MDIO_PMA_REG_8481_LED1_MASK, 0x10); | |
10055 | ||
10056 | elink_cl45_write(sc, phy, | |
10057 | MDIO_PMA_DEVAD, | |
10058 | MDIO_PMA_REG_8481_LED2_MASK, 0x80); | |
10059 | ||
10060 | elink_cl45_write(sc, phy, | |
10061 | MDIO_PMA_DEVAD, | |
10062 | MDIO_PMA_REG_8481_LED3_MASK, 0x98); | |
10063 | ||
10064 | elink_cl45_write(sc, phy, | |
10065 | MDIO_PMA_DEVAD, | |
10066 | MDIO_PMA_REG_8481_LED5_MASK, 0x40); | |
10067 | ||
10068 | } else { | |
10069 | /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED | |
10070 | * sources are all wired through LED1, rather than only | |
10071 | * 10G in other modes. | |
10072 | */ | |
10073 | val = ((params->hw_led_mode << | |
10074 | SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10075 | SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80; | |
10076 | ||
10077 | elink_cl45_write(sc, phy, | |
10078 | MDIO_PMA_DEVAD, | |
10079 | MDIO_PMA_REG_8481_LED1_MASK, val); | |
10080 | ||
10081 | /* Tell LED3 to blink on source */ | |
10082 | elink_cl45_read(sc, phy, | |
10083 | MDIO_PMA_DEVAD, | |
10084 | MDIO_PMA_REG_8481_LINK_SIGNAL, &val); | |
10085 | val &= ~(7 << 6); | |
10086 | val |= (1 << 6); /* A83B[8:6]= 1 */ | |
10087 | elink_cl45_write(sc, phy, | |
10088 | MDIO_PMA_DEVAD, | |
10089 | MDIO_PMA_REG_8481_LINK_SIGNAL, val); | |
10090 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) { | |
10091 | /* Restore LED4 source to external link, | |
10092 | * and re-enable interrupts. | |
10093 | */ | |
10094 | elink_cl45_write(sc, phy, | |
10095 | MDIO_PMA_DEVAD, | |
10096 | MDIO_PMA_REG_8481_SIGNAL_MASK, | |
10097 | 0x40); | |
10098 | if (params->link_flags & | |
10099 | ELINK_LINK_FLAGS_INT_DISABLED) { | |
10100 | elink_link_int_enable(params); | |
10101 | params->link_flags &= | |
10102 | ~ELINK_LINK_FLAGS_INT_DISABLED; | |
10103 | } | |
10104 | } | |
10105 | } | |
10106 | break; | |
10107 | } | |
10108 | ||
10109 | /* This is a workaround for E3+84833 until autoneg | |
10110 | * restart is fixed in f/w | |
10111 | */ | |
10112 | if (CHIP_IS_E3(sc)) { | |
10113 | elink_cl45_read(sc, phy, MDIO_WC_DEVAD, | |
10114 | MDIO_WC_REG_GP2_STATUS_GP_2_1, &val); | |
10115 | } | |
10116 | } | |
10117 | ||
10118 | /******************************************************************/ | |
10119 | /* 54618SE PHY SECTION */ | |
10120 | /******************************************************************/ | |
10121 | static void elink_54618se_specific_func(struct elink_phy *phy, | |
10122 | struct elink_params *params, | |
10123 | uint32_t action) | |
10124 | { | |
10125 | struct bnx2x_softc *sc = params->sc; | |
10126 | uint16_t temp; | |
10127 | switch (action) { | |
10128 | case ELINK_PHY_INIT: | |
10129 | /* Configure LED4: set to INTR (0x6). */ | |
10130 | /* Accessing shadow register 0xe. */ | |
10131 | elink_cl22_write(sc, phy, | |
10132 | MDIO_REG_GPHY_SHADOW, | |
10133 | MDIO_REG_GPHY_SHADOW_LED_SEL2); | |
10134 | elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp); | |
10135 | temp &= ~(0xf << 4); | |
10136 | temp |= (0x6 << 4); | |
10137 | elink_cl22_write(sc, phy, | |
10138 | MDIO_REG_GPHY_SHADOW, | |
10139 | MDIO_REG_GPHY_SHADOW_WR_ENA | temp); | |
10140 | /* Configure INTR based on link status change. */ | |
10141 | elink_cl22_write(sc, phy, | |
10142 | MDIO_REG_INTR_MASK, | |
10143 | ~MDIO_REG_INTR_MASK_LINK_STATUS); | |
10144 | break; | |
10145 | } | |
10146 | } | |
10147 | ||
10148 | static elink_status_t elink_54618se_config_init(struct elink_phy *phy, | |
10149 | struct elink_params *params, | |
10150 | struct elink_vars *vars) | |
10151 | { | |
10152 | struct bnx2x_softc *sc = params->sc; | |
10153 | uint8_t port; | |
10154 | uint16_t autoneg_val, an_1000_val, an_10_100_val, fc_val, temp; | |
10155 | uint32_t cfg_pin; | |
10156 | ||
10157 | PMD_DRV_LOG(DEBUG, "54618SE cfg init"); | |
10158 | DELAY(1000 * 1); | |
10159 | ||
10160 | /* This works with E3 only, no need to check the chip | |
10161 | * before determining the port. | |
10162 | */ | |
10163 | port = params->port; | |
10164 | ||
10165 | cfg_pin = (REG_RD(sc, params->shmem_base + | |
10166 | offsetof(struct shmem_region, | |
10167 | dev_info.port_hw_config[port]. | |
10168 | e3_cmn_pin_cfg)) & | |
10169 | PORT_HW_CFG_E3_PHY_RESET_MASK) >> | |
10170 | PORT_HW_CFG_E3_PHY_RESET_SHIFT; | |
10171 | ||
10172 | /* Drive pin high to bring the GPHY out of reset. */ | |
10173 | elink_set_cfg_pin(sc, cfg_pin, 1); | |
10174 | ||
10175 | /* wait for GPHY to reset */ | |
10176 | DELAY(1000 * 50); | |
10177 | ||
10178 | /* reset phy */ | |
10179 | elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x8000); | |
10180 | elink_wait_reset_complete(sc, phy, params); | |
10181 | ||
10182 | /* Wait for GPHY to reset */ | |
10183 | DELAY(1000 * 50); | |
10184 | ||
10185 | elink_54618se_specific_func(phy, params, ELINK_PHY_INIT); | |
10186 | /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */ | |
10187 | elink_cl22_write(sc, phy, | |
10188 | MDIO_REG_GPHY_SHADOW, | |
10189 | MDIO_REG_GPHY_SHADOW_AUTO_DET_MED); | |
10190 | elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp); | |
10191 | temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD; | |
10192 | elink_cl22_write(sc, phy, | |
10193 | MDIO_REG_GPHY_SHADOW, | |
10194 | MDIO_REG_GPHY_SHADOW_WR_ENA | temp); | |
10195 | ||
10196 | /* Set up fc */ | |
10197 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ | |
10198 | elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); | |
10199 | fc_val = 0; | |
10200 | if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == | |
10201 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) | |
10202 | fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; | |
10203 | ||
10204 | if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == | |
10205 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) | |
10206 | fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; | |
10207 | ||
10208 | /* Read all advertisement */ | |
10209 | elink_cl22_read(sc, phy, 0x09, &an_1000_val); | |
10210 | ||
10211 | elink_cl22_read(sc, phy, 0x04, &an_10_100_val); | |
10212 | ||
10213 | elink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &autoneg_val); | |
10214 | ||
10215 | /* Disable forced speed */ | |
10216 | autoneg_val &= | |
10217 | ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13)); | |
10218 | an_10_100_val &= | |
10219 | ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 10) | | |
10220 | (1 << 11)); | |
10221 | ||
10222 | if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && | |
10223 | (phy->speed_cap_mask & | |
10224 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || | |
10225 | (phy->req_line_speed == ELINK_SPEED_1000)) { | |
10226 | an_1000_val |= (1 << 8); | |
10227 | autoneg_val |= (1 << 9 | 1 << 12); | |
10228 | if (phy->req_duplex == DUPLEX_FULL) | |
10229 | an_1000_val |= (1 << 9); | |
10230 | PMD_DRV_LOG(DEBUG, "Advertising 1G"); | |
10231 | } else | |
10232 | an_1000_val &= ~((1 << 8) | (1 << 9)); | |
10233 | ||
10234 | elink_cl22_write(sc, phy, 0x09, an_1000_val); | |
10235 | elink_cl22_read(sc, phy, 0x09, &an_1000_val); | |
10236 | ||
10237 | /* Advertise 10/100 link speed */ | |
10238 | if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { | |
10239 | if (phy->speed_cap_mask & | |
10240 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) { | |
10241 | an_10_100_val |= (1 << 5); | |
10242 | autoneg_val |= (1 << 9 | 1 << 12); | |
10243 | PMD_DRV_LOG(DEBUG, "Advertising 10M-HD"); | |
10244 | } | |
10245 | if (phy->speed_cap_mask & | |
10246 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) { | |
10247 | an_10_100_val |= (1 << 6); | |
10248 | autoneg_val |= (1 << 9 | 1 << 12); | |
10249 | PMD_DRV_LOG(DEBUG, "Advertising 10M-FD"); | |
10250 | } | |
10251 | if (phy->speed_cap_mask & | |
10252 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { | |
10253 | an_10_100_val |= (1 << 7); | |
10254 | autoneg_val |= (1 << 9 | 1 << 12); | |
10255 | PMD_DRV_LOG(DEBUG, "Advertising 100M-HD"); | |
10256 | } | |
10257 | if (phy->speed_cap_mask & | |
10258 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { | |
10259 | an_10_100_val |= (1 << 8); | |
10260 | autoneg_val |= (1 << 9 | 1 << 12); | |
10261 | PMD_DRV_LOG(DEBUG, "Advertising 100M-FD"); | |
10262 | } | |
10263 | } | |
10264 | ||
10265 | /* Only 10/100 are allowed to work in FORCE mode */ | |
10266 | if (phy->req_line_speed == ELINK_SPEED_100) { | |
10267 | autoneg_val |= (1 << 13); | |
10268 | /* Enabled AUTO-MDIX when autoneg is disabled */ | |
10269 | elink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0)); | |
10270 | PMD_DRV_LOG(DEBUG, "Setting 100M force"); | |
10271 | } | |
10272 | if (phy->req_line_speed == ELINK_SPEED_10) { | |
10273 | /* Enabled AUTO-MDIX when autoneg is disabled */ | |
10274 | elink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0)); | |
10275 | PMD_DRV_LOG(DEBUG, "Setting 10M force"); | |
10276 | } | |
10277 | ||
10278 | if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) { | |
10279 | elink_status_t rc; | |
10280 | ||
10281 | elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS, | |
10282 | MDIO_REG_GPHY_EXP_ACCESS_TOP | | |
10283 | MDIO_REG_GPHY_EXP_TOP_2K_BUF); | |
10284 | elink_cl22_read(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); | |
10285 | temp &= 0xfffe; | |
10286 | elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); | |
10287 | ||
10288 | rc = elink_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV); | |
10289 | if (rc != ELINK_STATUS_OK) { | |
10290 | PMD_DRV_LOG(DEBUG, "Failed to configure EEE timers"); | |
10291 | elink_eee_disable(phy, params, vars); | |
10292 | } else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) && | |
10293 | (phy->req_duplex == DUPLEX_FULL) && | |
10294 | (elink_eee_calc_timer(params) || | |
10295 | !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) { | |
10296 | /* Need to advertise EEE only when requested, | |
10297 | * and either no LPI assertion was requested, | |
10298 | * or it was requested and a valid timer was set. | |
10299 | * Also notice full duplex is required for EEE. | |
10300 | */ | |
10301 | elink_eee_advertise(phy, params, vars, | |
10302 | SHMEM_EEE_1G_ADV); | |
10303 | } else { | |
10304 | PMD_DRV_LOG(DEBUG, "Don't Advertise 1GBase-T EEE"); | |
10305 | elink_eee_disable(phy, params, vars); | |
10306 | } | |
10307 | } else { | |
10308 | vars->eee_status &= ~SHMEM_EEE_1G_ADV << | |
10309 | SHMEM_EEE_SUPPORTED_SHIFT; | |
10310 | ||
10311 | if (phy->flags & ELINK_FLAGS_EEE) { | |
10312 | /* Handle legacy auto-grEEEn */ | |
10313 | if (params->feature_config_flags & | |
10314 | ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED) { | |
10315 | temp = 6; | |
10316 | PMD_DRV_LOG(DEBUG, "Enabling Auto-GrEEEn"); | |
10317 | } else { | |
10318 | temp = 0; | |
10319 | PMD_DRV_LOG(DEBUG, "Don't Adv. EEE"); | |
10320 | } | |
10321 | elink_cl45_write(sc, phy, MDIO_AN_DEVAD, | |
10322 | MDIO_AN_REG_EEE_ADV, temp); | |
10323 | } | |
10324 | } | |
10325 | ||
10326 | elink_cl22_write(sc, phy, 0x04, an_10_100_val | fc_val); | |
10327 | ||
10328 | if (phy->req_duplex == DUPLEX_FULL) | |
10329 | autoneg_val |= (1 << 8); | |
10330 | ||
10331 | elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, autoneg_val); | |
10332 | ||
10333 | return ELINK_STATUS_OK; | |
10334 | } | |
10335 | ||
10336 | static void elink_5461x_set_link_led(struct elink_phy *phy, | |
10337 | struct elink_params *params, uint8_t mode) | |
10338 | { | |
10339 | struct bnx2x_softc *sc = params->sc; | |
10340 | uint16_t temp; | |
10341 | ||
10342 | elink_cl22_write(sc, phy, | |
10343 | MDIO_REG_GPHY_SHADOW, MDIO_REG_GPHY_SHADOW_LED_SEL1); | |
10344 | elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp); | |
10345 | temp &= 0xff00; | |
10346 | ||
10347 | PMD_DRV_LOG(DEBUG, "54618x set link led (mode=%x)", mode); | |
10348 | switch (mode) { | |
10349 | case ELINK_LED_MODE_FRONT_PANEL_OFF: | |
10350 | case ELINK_LED_MODE_OFF: | |
10351 | temp |= 0x00ee; | |
10352 | break; | |
10353 | case ELINK_LED_MODE_OPER: | |
10354 | temp |= 0x0001; | |
10355 | break; | |
10356 | case ELINK_LED_MODE_ON: | |
10357 | temp |= 0x00ff; | |
10358 | break; | |
10359 | default: | |
10360 | break; | |
10361 | } | |
10362 | elink_cl22_write(sc, phy, | |
10363 | MDIO_REG_GPHY_SHADOW, | |
10364 | MDIO_REG_GPHY_SHADOW_WR_ENA | temp); | |
10365 | return; | |
10366 | } | |
10367 | ||
10368 | static void elink_54618se_link_reset(struct elink_phy *phy, | |
10369 | struct elink_params *params) | |
10370 | { | |
10371 | struct bnx2x_softc *sc = params->sc; | |
10372 | uint32_t cfg_pin; | |
10373 | uint8_t port; | |
10374 | ||
10375 | /* In case of no EPIO routed to reset the GPHY, put it | |
10376 | * in low power mode. | |
10377 | */ | |
10378 | elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x800); | |
10379 | /* This works with E3 only, no need to check the chip | |
10380 | * before determining the port. | |
10381 | */ | |
10382 | port = params->port; | |
10383 | cfg_pin = (REG_RD(sc, params->shmem_base + | |
10384 | offsetof(struct shmem_region, | |
10385 | dev_info.port_hw_config[port]. | |
10386 | e3_cmn_pin_cfg)) & | |
10387 | PORT_HW_CFG_E3_PHY_RESET_MASK) >> | |
10388 | PORT_HW_CFG_E3_PHY_RESET_SHIFT; | |
10389 | ||
10390 | /* Drive pin low to put GPHY in reset. */ | |
10391 | elink_set_cfg_pin(sc, cfg_pin, 0); | |
10392 | } | |
10393 | ||
10394 | static uint8_t elink_54618se_read_status(struct elink_phy *phy, | |
10395 | struct elink_params *params, | |
10396 | struct elink_vars *vars) | |
10397 | { | |
10398 | struct bnx2x_softc *sc = params->sc; | |
10399 | uint16_t val; | |
10400 | uint8_t link_up = 0; | |
10401 | uint16_t legacy_status, legacy_speed; | |
10402 | ||
10403 | /* Get speed operation status */ | |
10404 | elink_cl22_read(sc, phy, MDIO_REG_GPHY_AUX_STATUS, &legacy_status); | |
10405 | PMD_DRV_LOG(DEBUG, "54618SE read_status: 0x%x", legacy_status); | |
10406 | ||
10407 | /* Read status to clear the PHY interrupt. */ | |
10408 | elink_cl22_read(sc, phy, MDIO_REG_INTR_STATUS, &val); | |
10409 | ||
10410 | link_up = ((legacy_status & (1 << 2)) == (1 << 2)); | |
10411 | ||
10412 | if (link_up) { | |
10413 | legacy_speed = (legacy_status & (7 << 8)); | |
10414 | if (legacy_speed == (7 << 8)) { | |
10415 | vars->line_speed = ELINK_SPEED_1000; | |
10416 | vars->duplex = DUPLEX_FULL; | |
10417 | } else if (legacy_speed == (6 << 8)) { | |
10418 | vars->line_speed = ELINK_SPEED_1000; | |
10419 | vars->duplex = DUPLEX_HALF; | |
10420 | } else if (legacy_speed == (5 << 8)) { | |
10421 | vars->line_speed = ELINK_SPEED_100; | |
10422 | vars->duplex = DUPLEX_FULL; | |
10423 | } | |
10424 | /* Omitting 100Base-T4 for now */ | |
10425 | else if (legacy_speed == (3 << 8)) { | |
10426 | vars->line_speed = ELINK_SPEED_100; | |
10427 | vars->duplex = DUPLEX_HALF; | |
10428 | } else if (legacy_speed == (2 << 8)) { | |
10429 | vars->line_speed = ELINK_SPEED_10; | |
10430 | vars->duplex = DUPLEX_FULL; | |
10431 | } else if (legacy_speed == (1 << 8)) { | |
10432 | vars->line_speed = ELINK_SPEED_10; | |
10433 | vars->duplex = DUPLEX_HALF; | |
10434 | } else /* Should not happen */ | |
10435 | vars->line_speed = 0; | |
10436 | ||
10437 | PMD_DRV_LOG(DEBUG, | |
10438 | "Link is up in %dMbps, is_duplex_full= %d", | |
10439 | vars->line_speed, (vars->duplex == DUPLEX_FULL)); | |
10440 | ||
10441 | /* Check legacy speed AN resolution */ | |
10442 | elink_cl22_read(sc, phy, 0x01, &val); | |
10443 | if (val & (1 << 5)) | |
10444 | vars->link_status |= | |
10445 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
10446 | elink_cl22_read(sc, phy, 0x06, &val); | |
10447 | if ((val & (1 << 0)) == 0) | |
10448 | vars->link_status |= | |
10449 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
10450 | ||
10451 | PMD_DRV_LOG(DEBUG, "BNX2X54618SE: link speed is %d", | |
10452 | vars->line_speed); | |
10453 | ||
10454 | elink_ext_phy_resolve_fc(phy, params, vars); | |
10455 | ||
10456 | if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { | |
10457 | /* Report LP advertised speeds */ | |
10458 | elink_cl22_read(sc, phy, 0x5, &val); | |
10459 | ||
10460 | if (val & (1 << 5)) | |
10461 | vars->link_status |= | |
10462 | LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; | |
10463 | if (val & (1 << 6)) | |
10464 | vars->link_status |= | |
10465 | LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; | |
10466 | if (val & (1 << 7)) | |
10467 | vars->link_status |= | |
10468 | LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; | |
10469 | if (val & (1 << 8)) | |
10470 | vars->link_status |= | |
10471 | LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; | |
10472 | if (val & (1 << 9)) | |
10473 | vars->link_status |= | |
10474 | LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; | |
10475 | ||
10476 | elink_cl22_read(sc, phy, 0xa, &val); | |
10477 | if (val & (1 << 10)) | |
10478 | vars->link_status |= | |
10479 | LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; | |
10480 | if (val & (1 << 11)) | |
10481 | vars->link_status |= | |
10482 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
10483 | ||
10484 | if ((phy->flags & ELINK_FLAGS_EEE) && | |
10485 | elink_eee_has_cap(params)) | |
10486 | elink_eee_an_resolve(phy, params, vars); | |
10487 | } | |
10488 | } | |
10489 | return link_up; | |
10490 | } | |
10491 | ||
10492 | static void elink_54618se_config_loopback(struct elink_phy *phy, | |
10493 | struct elink_params *params) | |
10494 | { | |
10495 | struct bnx2x_softc *sc = params->sc; | |
10496 | uint16_t val; | |
10497 | uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
10498 | ||
10499 | PMD_DRV_LOG(DEBUG, "2PMA/PMD ext_phy_loopback: 54618se"); | |
10500 | ||
10501 | /* Enable master/slave manual mmode and set to master */ | |
10502 | /* mii write 9 [bits set 11 12] */ | |
10503 | elink_cl22_write(sc, phy, 0x09, 3 << 11); | |
10504 | ||
10505 | /* forced 1G and disable autoneg */ | |
10506 | /* set val [mii read 0] */ | |
10507 | /* set val [expr $val & [bits clear 6 12 13]] */ | |
10508 | /* set val [expr $val | [bits set 6 8]] */ | |
10509 | /* mii write 0 $val */ | |
10510 | elink_cl22_read(sc, phy, 0x00, &val); | |
10511 | val &= ~((1 << 6) | (1 << 12) | (1 << 13)); | |
10512 | val |= (1 << 6) | (1 << 8); | |
10513 | elink_cl22_write(sc, phy, 0x00, val); | |
10514 | ||
10515 | /* Set external loopback and Tx using 6dB coding */ | |
10516 | /* mii write 0x18 7 */ | |
10517 | /* set val [mii read 0x18] */ | |
10518 | /* mii write 0x18 [expr $val | [bits set 10 15]] */ | |
10519 | elink_cl22_write(sc, phy, 0x18, 7); | |
10520 | elink_cl22_read(sc, phy, 0x18, &val); | |
10521 | elink_cl22_write(sc, phy, 0x18, val | (1 << 10) | (1 << 15)); | |
10522 | ||
10523 | /* This register opens the gate for the UMAC despite its name */ | |
10524 | REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 1); | |
10525 | ||
10526 | /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame | |
10527 | * length used by the MAC receive logic to check frames. | |
10528 | */ | |
10529 | REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710); | |
10530 | } | |
10531 | ||
10532 | /******************************************************************/ | |
10533 | /* SFX7101 PHY SECTION */ | |
10534 | /******************************************************************/ | |
10535 | static void elink_7101_config_loopback(struct elink_phy *phy, | |
10536 | struct elink_params *params) | |
10537 | { | |
10538 | struct bnx2x_softc *sc = params->sc; | |
10539 | /* SFX7101_XGXS_TEST1 */ | |
10540 | elink_cl45_write(sc, phy, | |
10541 | MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100); | |
10542 | } | |
10543 | ||
10544 | static elink_status_t elink_7101_config_init(struct elink_phy *phy, | |
10545 | struct elink_params *params, | |
10546 | struct elink_vars *vars) | |
10547 | { | |
10548 | uint16_t fw_ver1, fw_ver2, val; | |
10549 | struct bnx2x_softc *sc = params->sc; | |
10550 | PMD_DRV_LOG(DEBUG, "Setting the SFX7101 LASI indication"); | |
10551 | ||
10552 | /* Restore normal power mode */ | |
10553 | elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, | |
10554 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); | |
10555 | /* HW reset */ | |
10556 | elink_ext_phy_hw_reset(sc, params->port); | |
10557 | elink_wait_reset_complete(sc, phy, params); | |
10558 | ||
10559 | elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1); | |
10560 | PMD_DRV_LOG(DEBUG, "Setting the SFX7101 LED to blink on traffic"); | |
10561 | elink_cl45_write(sc, phy, | |
10562 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1 << 3)); | |
10563 | ||
10564 | elink_ext_phy_set_pause(params, phy, vars); | |
10565 | /* Restart autoneg */ | |
10566 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); | |
10567 | val |= 0x200; | |
10568 | elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); | |
10569 | ||
10570 | /* Save spirom version */ | |
10571 | elink_cl45_read(sc, phy, | |
10572 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1); | |
10573 | ||
10574 | elink_cl45_read(sc, phy, | |
10575 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2); | |
10576 | elink_save_spirom_version(sc, params->port, | |
10577 | (uint32_t) (fw_ver1 << 16 | fw_ver2), | |
10578 | phy->ver_addr); | |
10579 | return ELINK_STATUS_OK; | |
10580 | } | |
10581 | ||
10582 | static uint8_t elink_7101_read_status(struct elink_phy *phy, | |
10583 | struct elink_params *params, | |
10584 | struct elink_vars *vars) | |
10585 | { | |
10586 | struct bnx2x_softc *sc = params->sc; | |
10587 | uint8_t link_up; | |
10588 | uint16_t val1, val2; | |
10589 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); | |
10590 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); | |
10591 | PMD_DRV_LOG(DEBUG, "10G-base-T LASI status 0x%x->0x%x", val2, val1); | |
10592 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
10593 | elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
10594 | PMD_DRV_LOG(DEBUG, "10G-base-T PMA status 0x%x->0x%x", val2, val1); | |
10595 | link_up = ((val1 & 4) == 4); | |
10596 | /* If link is up print the AN outcome of the SFX7101 PHY */ | |
10597 | if (link_up) { | |
10598 | elink_cl45_read(sc, phy, | |
10599 | MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, | |
10600 | &val2); | |
10601 | vars->line_speed = ELINK_SPEED_10000; | |
10602 | vars->duplex = DUPLEX_FULL; | |
10603 | PMD_DRV_LOG(DEBUG, "SFX7101 AN status 0x%x->Master=%x", | |
10604 | val2, (val2 & (1 << 14))); | |
10605 | elink_ext_phy_10G_an_resolve(sc, phy, vars); | |
10606 | elink_ext_phy_resolve_fc(phy, params, vars); | |
10607 | ||
10608 | /* Read LP advertised speeds */ | |
10609 | if (val2 & (1 << 11)) | |
10610 | vars->link_status |= | |
10611 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
10612 | } | |
10613 | return link_up; | |
10614 | } | |
10615 | ||
10616 | static elink_status_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t * str, | |
10617 | uint16_t * len) | |
10618 | { | |
10619 | if (*len < 5) | |
10620 | return ELINK_STATUS_ERROR; | |
10621 | str[0] = (spirom_ver & 0xFF); | |
10622 | str[1] = (spirom_ver & 0xFF00) >> 8; | |
10623 | str[2] = (spirom_ver & 0xFF0000) >> 16; | |
10624 | str[3] = (spirom_ver & 0xFF000000) >> 24; | |
10625 | str[4] = '\0'; | |
10626 | *len -= 5; | |
10627 | return ELINK_STATUS_OK; | |
10628 | } | |
10629 | ||
10630 | static void elink_7101_hw_reset(__rte_unused struct elink_phy *phy, | |
10631 | struct elink_params *params) | |
10632 | { | |
10633 | /* Low power mode is controlled by GPIO 2 */ | |
10634 | elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_2, | |
10635 | MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); | |
10636 | /* The PHY reset is controlled by GPIO 1 */ | |
10637 | elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1, | |
10638 | MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); | |
10639 | } | |
10640 | ||
10641 | static void elink_7101_set_link_led(struct elink_phy *phy, | |
10642 | struct elink_params *params, uint8_t mode) | |
10643 | { | |
10644 | uint16_t val = 0; | |
10645 | struct bnx2x_softc *sc = params->sc; | |
10646 | switch (mode) { | |
10647 | case ELINK_LED_MODE_FRONT_PANEL_OFF: | |
10648 | case ELINK_LED_MODE_OFF: | |
10649 | val = 2; | |
10650 | break; | |
10651 | case ELINK_LED_MODE_ON: | |
10652 | val = 1; | |
10653 | break; | |
10654 | case ELINK_LED_MODE_OPER: | |
10655 | val = 0; | |
10656 | break; | |
10657 | } | |
10658 | elink_cl45_write(sc, phy, | |
10659 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LINK_LED_CNTL, val); | |
10660 | } | |
10661 | ||
10662 | /******************************************************************/ | |
10663 | /* STATIC PHY DECLARATION */ | |
10664 | /******************************************************************/ | |
10665 | ||
10666 | static const struct elink_phy phy_null = { | |
10667 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, | |
10668 | .addr = 0, | |
10669 | .def_md_devad = 0, | |
10670 | .flags = ELINK_FLAGS_INIT_XGXS_FIRST, | |
10671 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10672 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10673 | .mdio_ctrl = 0, | |
10674 | .supported = 0, | |
10675 | .media_type = ELINK_ETH_PHY_NOT_PRESENT, | |
10676 | .ver_addr = 0, | |
10677 | .req_flow_ctrl = 0, | |
10678 | .req_line_speed = 0, | |
10679 | .speed_cap_mask = 0, | |
10680 | .req_duplex = 0, | |
10681 | .rsrv = 0, | |
10682 | .config_init = (config_init_t) NULL, | |
10683 | .read_status = (read_status_t) NULL, | |
10684 | .link_reset = (link_reset_t) NULL, | |
10685 | .config_loopback = (config_loopback_t) NULL, | |
10686 | .format_fw_ver = (format_fw_ver_t) NULL, | |
10687 | .hw_reset = (hw_reset_t) NULL, | |
10688 | .set_link_led = (set_link_led_t) NULL, | |
10689 | .phy_specific_func = (phy_specific_func_t) NULL | |
10690 | }; | |
10691 | ||
10692 | static const struct elink_phy phy_serdes = { | |
10693 | .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, | |
10694 | .addr = 0xff, | |
10695 | .def_md_devad = 0, | |
10696 | .flags = 0, | |
10697 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10698 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10699 | .mdio_ctrl = 0, | |
10700 | .supported = (ELINK_SUPPORTED_10baseT_Half | | |
10701 | ELINK_SUPPORTED_10baseT_Full | | |
10702 | ELINK_SUPPORTED_100baseT_Half | | |
10703 | ELINK_SUPPORTED_100baseT_Full | | |
10704 | ELINK_SUPPORTED_1000baseT_Full | | |
10705 | ELINK_SUPPORTED_2500baseX_Full | | |
10706 | ELINK_SUPPORTED_TP | | |
10707 | ELINK_SUPPORTED_Autoneg | | |
10708 | ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), | |
10709 | .media_type = ELINK_ETH_PHY_BASE_T, | |
10710 | .ver_addr = 0, | |
10711 | .req_flow_ctrl = 0, | |
10712 | .req_line_speed = 0, | |
10713 | .speed_cap_mask = 0, | |
10714 | .req_duplex = 0, | |
10715 | .rsrv = 0, | |
10716 | .config_init = (config_init_t) elink_xgxs_config_init, | |
10717 | .read_status = (read_status_t) elink_link_settings_status, | |
10718 | .link_reset = (link_reset_t) elink_int_link_reset, | |
10719 | .config_loopback = (config_loopback_t) NULL, | |
10720 | .format_fw_ver = (format_fw_ver_t) NULL, | |
10721 | .hw_reset = (hw_reset_t) NULL, | |
10722 | .set_link_led = (set_link_led_t) NULL, | |
10723 | .phy_specific_func = (phy_specific_func_t) NULL | |
10724 | }; | |
10725 | ||
10726 | static const struct elink_phy phy_xgxs = { | |
10727 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, | |
10728 | .addr = 0xff, | |
10729 | .def_md_devad = 0, | |
10730 | .flags = 0, | |
10731 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10732 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10733 | .mdio_ctrl = 0, | |
10734 | .supported = (ELINK_SUPPORTED_10baseT_Half | | |
10735 | ELINK_SUPPORTED_10baseT_Full | | |
10736 | ELINK_SUPPORTED_100baseT_Half | | |
10737 | ELINK_SUPPORTED_100baseT_Full | | |
10738 | ELINK_SUPPORTED_1000baseT_Full | | |
10739 | ELINK_SUPPORTED_2500baseX_Full | | |
10740 | ELINK_SUPPORTED_10000baseT_Full | | |
10741 | ELINK_SUPPORTED_FIBRE | | |
10742 | ELINK_SUPPORTED_Autoneg | | |
10743 | ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), | |
10744 | .media_type = ELINK_ETH_PHY_CX4, | |
10745 | .ver_addr = 0, | |
10746 | .req_flow_ctrl = 0, | |
10747 | .req_line_speed = 0, | |
10748 | .speed_cap_mask = 0, | |
10749 | .req_duplex = 0, | |
10750 | .rsrv = 0, | |
10751 | .config_init = (config_init_t) elink_xgxs_config_init, | |
10752 | .read_status = (read_status_t) elink_link_settings_status, | |
10753 | .link_reset = (link_reset_t) elink_int_link_reset, | |
10754 | .config_loopback = (config_loopback_t) elink_set_xgxs_loopback, | |
10755 | .format_fw_ver = (format_fw_ver_t) NULL, | |
10756 | .hw_reset = (hw_reset_t) NULL, | |
10757 | .set_link_led = (set_link_led_t) NULL, | |
10758 | .phy_specific_func = (phy_specific_func_t) elink_xgxs_specific_func | |
10759 | }; | |
10760 | ||
10761 | static const struct elink_phy phy_warpcore = { | |
10762 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, | |
10763 | .addr = 0xff, | |
10764 | .def_md_devad = 0, | |
10765 | .flags = ELINK_FLAGS_TX_ERROR_CHECK, | |
10766 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10767 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10768 | .mdio_ctrl = 0, | |
10769 | .supported = (ELINK_SUPPORTED_10baseT_Half | | |
10770 | ELINK_SUPPORTED_10baseT_Full | | |
10771 | ELINK_SUPPORTED_100baseT_Half | | |
10772 | ELINK_SUPPORTED_100baseT_Full | | |
10773 | ELINK_SUPPORTED_1000baseT_Full | | |
10774 | ELINK_SUPPORTED_10000baseT_Full | | |
10775 | ELINK_SUPPORTED_20000baseKR2_Full | | |
10776 | ELINK_SUPPORTED_20000baseMLD2_Full | | |
10777 | ELINK_SUPPORTED_FIBRE | | |
10778 | ELINK_SUPPORTED_Autoneg | | |
10779 | ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), | |
10780 | .media_type = ELINK_ETH_PHY_UNSPECIFIED, | |
10781 | .ver_addr = 0, | |
10782 | .req_flow_ctrl = 0, | |
10783 | .req_line_speed = 0, | |
10784 | .speed_cap_mask = 0, | |
10785 | /* req_duplex = */ 0, | |
10786 | /* rsrv = */ 0, | |
10787 | .config_init = (config_init_t) elink_warpcore_config_init, | |
10788 | .read_status = (read_status_t) elink_warpcore_read_status, | |
10789 | .link_reset = (link_reset_t) elink_warpcore_link_reset, | |
10790 | .config_loopback = (config_loopback_t) elink_set_warpcore_loopback, | |
10791 | .format_fw_ver = (format_fw_ver_t) NULL, | |
10792 | .hw_reset = (hw_reset_t) elink_warpcore_hw_reset, | |
10793 | .set_link_led = (set_link_led_t) NULL, | |
10794 | .phy_specific_func = (phy_specific_func_t) NULL | |
10795 | }; | |
10796 | ||
10797 | static const struct elink_phy phy_7101 = { | |
10798 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, | |
10799 | .addr = 0xff, | |
10800 | .def_md_devad = 0, | |
10801 | .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ, | |
10802 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10803 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10804 | .mdio_ctrl = 0, | |
10805 | .supported = (ELINK_SUPPORTED_10000baseT_Full | | |
10806 | ELINK_SUPPORTED_TP | | |
10807 | ELINK_SUPPORTED_Autoneg | | |
10808 | ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), | |
10809 | .media_type = ELINK_ETH_PHY_BASE_T, | |
10810 | .ver_addr = 0, | |
10811 | .req_flow_ctrl = 0, | |
10812 | .req_line_speed = 0, | |
10813 | .speed_cap_mask = 0, | |
10814 | .req_duplex = 0, | |
10815 | .rsrv = 0, | |
10816 | .config_init = (config_init_t) elink_7101_config_init, | |
10817 | .read_status = (read_status_t) elink_7101_read_status, | |
10818 | .link_reset = (link_reset_t) elink_common_ext_link_reset, | |
10819 | .config_loopback = (config_loopback_t) elink_7101_config_loopback, | |
10820 | .format_fw_ver = (format_fw_ver_t) elink_7101_format_ver, | |
10821 | .hw_reset = (hw_reset_t) elink_7101_hw_reset, | |
10822 | .set_link_led = (set_link_led_t) elink_7101_set_link_led, | |
10823 | .phy_specific_func = (phy_specific_func_t) NULL | |
10824 | }; | |
10825 | ||
10826 | static const struct elink_phy phy_8073 = { | |
10827 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073, | |
10828 | .addr = 0xff, | |
10829 | .def_md_devad = 0, | |
10830 | .flags = 0, | |
10831 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10832 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10833 | .mdio_ctrl = 0, | |
10834 | .supported = (ELINK_SUPPORTED_10000baseT_Full | | |
10835 | ELINK_SUPPORTED_2500baseX_Full | | |
10836 | ELINK_SUPPORTED_1000baseT_Full | | |
10837 | ELINK_SUPPORTED_FIBRE | | |
10838 | ELINK_SUPPORTED_Autoneg | | |
10839 | ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), | |
10840 | .media_type = ELINK_ETH_PHY_KR, | |
10841 | .ver_addr = 0, | |
10842 | .req_flow_ctrl = 0, | |
10843 | .req_line_speed = 0, | |
10844 | .speed_cap_mask = 0, | |
10845 | .req_duplex = 0, | |
10846 | .rsrv = 0, | |
10847 | .config_init = (config_init_t) elink_8073_config_init, | |
10848 | .read_status = (read_status_t) elink_8073_read_status, | |
10849 | .link_reset = (link_reset_t) elink_8073_link_reset, | |
10850 | .config_loopback = (config_loopback_t) NULL, | |
10851 | .format_fw_ver = (format_fw_ver_t) elink_format_ver, | |
10852 | .hw_reset = (hw_reset_t) NULL, | |
10853 | .set_link_led = (set_link_led_t) NULL, | |
10854 | .phy_specific_func = (phy_specific_func_t) elink_8073_specific_func | |
10855 | }; | |
10856 | ||
10857 | static const struct elink_phy phy_8705 = { | |
10858 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705, | |
10859 | .addr = 0xff, | |
10860 | .def_md_devad = 0, | |
10861 | .flags = ELINK_FLAGS_INIT_XGXS_FIRST, | |
10862 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10863 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10864 | .mdio_ctrl = 0, | |
10865 | .supported = (ELINK_SUPPORTED_10000baseT_Full | | |
10866 | ELINK_SUPPORTED_FIBRE | | |
10867 | ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), | |
10868 | .media_type = ELINK_ETH_PHY_XFP_FIBER, | |
10869 | .ver_addr = 0, | |
10870 | .req_flow_ctrl = 0, | |
10871 | .req_line_speed = 0, | |
10872 | .speed_cap_mask = 0, | |
10873 | .req_duplex = 0, | |
10874 | .rsrv = 0, | |
10875 | .config_init = (config_init_t) elink_8705_config_init, | |
10876 | .read_status = (read_status_t) elink_8705_read_status, | |
10877 | .link_reset = (link_reset_t) elink_common_ext_link_reset, | |
10878 | .config_loopback = (config_loopback_t) NULL, | |
10879 | .format_fw_ver = (format_fw_ver_t) elink_null_format_ver, | |
10880 | .hw_reset = (hw_reset_t) NULL, | |
10881 | .set_link_led = (set_link_led_t) NULL, | |
10882 | .phy_specific_func = (phy_specific_func_t) NULL | |
10883 | }; | |
10884 | ||
10885 | static const struct elink_phy phy_8706 = { | |
10886 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706, | |
10887 | .addr = 0xff, | |
10888 | .def_md_devad = 0, | |
10889 | .flags = ELINK_FLAGS_INIT_XGXS_FIRST, | |
10890 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10891 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10892 | .mdio_ctrl = 0, | |
10893 | .supported = (ELINK_SUPPORTED_10000baseT_Full | | |
10894 | ELINK_SUPPORTED_1000baseT_Full | | |
10895 | ELINK_SUPPORTED_FIBRE | | |
10896 | ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), | |
10897 | .media_type = ELINK_ETH_PHY_SFPP_10G_FIBER, | |
10898 | .ver_addr = 0, | |
10899 | .req_flow_ctrl = 0, | |
10900 | .req_line_speed = 0, | |
10901 | .speed_cap_mask = 0, | |
10902 | .req_duplex = 0, | |
10903 | .rsrv = 0, | |
10904 | .config_init = (config_init_t) elink_8706_config_init, | |
10905 | .read_status = (read_status_t) elink_8706_read_status, | |
10906 | .link_reset = (link_reset_t) elink_common_ext_link_reset, | |
10907 | .config_loopback = (config_loopback_t) NULL, | |
10908 | .format_fw_ver = (format_fw_ver_t) elink_format_ver, | |
10909 | .hw_reset = (hw_reset_t) NULL, | |
10910 | .set_link_led = (set_link_led_t) NULL, | |
10911 | .phy_specific_func = (phy_specific_func_t) NULL | |
10912 | }; | |
10913 | ||
10914 | static const struct elink_phy phy_8726 = { | |
10915 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726, | |
10916 | .addr = 0xff, | |
10917 | .def_md_devad = 0, | |
10918 | .flags = (ELINK_FLAGS_INIT_XGXS_FIRST | ELINK_FLAGS_TX_ERROR_CHECK), | |
10919 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10920 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10921 | .mdio_ctrl = 0, | |
10922 | .supported = (ELINK_SUPPORTED_10000baseT_Full | | |
10923 | ELINK_SUPPORTED_1000baseT_Full | | |
10924 | ELINK_SUPPORTED_Autoneg | | |
10925 | ELINK_SUPPORTED_FIBRE | | |
10926 | ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), | |
10927 | .media_type = ELINK_ETH_PHY_NOT_PRESENT, | |
10928 | .ver_addr = 0, | |
10929 | .req_flow_ctrl = 0, | |
10930 | .req_line_speed = 0, | |
10931 | .speed_cap_mask = 0, | |
10932 | .req_duplex = 0, | |
10933 | .rsrv = 0, | |
10934 | .config_init = (config_init_t) elink_8726_config_init, | |
10935 | .read_status = (read_status_t) elink_8726_read_status, | |
10936 | .link_reset = (link_reset_t) elink_8726_link_reset, | |
10937 | .config_loopback = (config_loopback_t) elink_8726_config_loopback, | |
10938 | .format_fw_ver = (format_fw_ver_t) elink_format_ver, | |
10939 | .hw_reset = (hw_reset_t) NULL, | |
10940 | .set_link_led = (set_link_led_t) NULL, | |
10941 | .phy_specific_func = (phy_specific_func_t) NULL | |
10942 | }; | |
10943 | ||
10944 | static const struct elink_phy phy_8727 = { | |
10945 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727, | |
10946 | .addr = 0xff, | |
10947 | .def_md_devad = 0, | |
10948 | .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | ELINK_FLAGS_TX_ERROR_CHECK), | |
10949 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10950 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10951 | .mdio_ctrl = 0, | |
10952 | .supported = (ELINK_SUPPORTED_10000baseT_Full | | |
10953 | ELINK_SUPPORTED_1000baseT_Full | | |
10954 | ELINK_SUPPORTED_FIBRE | | |
10955 | ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), | |
10956 | .media_type = ELINK_ETH_PHY_NOT_PRESENT, | |
10957 | .ver_addr = 0, | |
10958 | .req_flow_ctrl = 0, | |
10959 | .req_line_speed = 0, | |
10960 | .speed_cap_mask = 0, | |
10961 | .req_duplex = 0, | |
10962 | .rsrv = 0, | |
10963 | .config_init = (config_init_t) elink_8727_config_init, | |
10964 | .read_status = (read_status_t) elink_8727_read_status, | |
10965 | .link_reset = (link_reset_t) elink_8727_link_reset, | |
10966 | .config_loopback = (config_loopback_t) NULL, | |
10967 | .format_fw_ver = (format_fw_ver_t) elink_format_ver, | |
10968 | .hw_reset = (hw_reset_t) elink_8727_hw_reset, | |
10969 | .set_link_led = (set_link_led_t) elink_8727_set_link_led, | |
10970 | .phy_specific_func = (phy_specific_func_t) elink_8727_specific_func | |
10971 | }; | |
10972 | ||
10973 | static const struct elink_phy phy_8481 = { | |
10974 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481, | |
10975 | .addr = 0xff, | |
10976 | .def_md_devad = 0, | |
10977 | .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ | | |
10978 | ELINK_FLAGS_REARM_LATCH_SIGNAL, | |
10979 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10980 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
10981 | .mdio_ctrl = 0, | |
10982 | .supported = (ELINK_SUPPORTED_10baseT_Half | | |
10983 | ELINK_SUPPORTED_10baseT_Full | | |
10984 | ELINK_SUPPORTED_100baseT_Half | | |
10985 | ELINK_SUPPORTED_100baseT_Full | | |
10986 | ELINK_SUPPORTED_1000baseT_Full | | |
10987 | ELINK_SUPPORTED_10000baseT_Full | | |
10988 | ELINK_SUPPORTED_TP | | |
10989 | ELINK_SUPPORTED_Autoneg | | |
10990 | ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), | |
10991 | .media_type = ELINK_ETH_PHY_BASE_T, | |
10992 | .ver_addr = 0, | |
10993 | .req_flow_ctrl = 0, | |
10994 | .req_line_speed = 0, | |
10995 | .speed_cap_mask = 0, | |
10996 | .req_duplex = 0, | |
10997 | .rsrv = 0, | |
10998 | .config_init = (config_init_t) elink_8481_config_init, | |
10999 | .read_status = (read_status_t) elink_848xx_read_status, | |
11000 | .link_reset = (link_reset_t) elink_8481_link_reset, | |
11001 | .config_loopback = (config_loopback_t) NULL, | |
11002 | .format_fw_ver = (format_fw_ver_t) elink_848xx_format_ver, | |
11003 | .hw_reset = (hw_reset_t) elink_8481_hw_reset, | |
11004 | .set_link_led = (set_link_led_t) elink_848xx_set_link_led, | |
11005 | .phy_specific_func = (phy_specific_func_t) NULL | |
11006 | }; | |
11007 | ||
11008 | static const struct elink_phy phy_84823 = { | |
11009 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823, | |
11010 | .addr = 0xff, | |
11011 | .def_md_devad = 0, | |
11012 | .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | | |
11013 | ELINK_FLAGS_REARM_LATCH_SIGNAL | ELINK_FLAGS_TX_ERROR_CHECK), | |
11014 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11015 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11016 | .mdio_ctrl = 0, | |
11017 | .supported = (ELINK_SUPPORTED_10baseT_Half | | |
11018 | ELINK_SUPPORTED_10baseT_Full | | |
11019 | ELINK_SUPPORTED_100baseT_Half | | |
11020 | ELINK_SUPPORTED_100baseT_Full | | |
11021 | ELINK_SUPPORTED_1000baseT_Full | | |
11022 | ELINK_SUPPORTED_10000baseT_Full | | |
11023 | ELINK_SUPPORTED_TP | | |
11024 | ELINK_SUPPORTED_Autoneg | | |
11025 | ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), | |
11026 | .media_type = ELINK_ETH_PHY_BASE_T, | |
11027 | .ver_addr = 0, | |
11028 | .req_flow_ctrl = 0, | |
11029 | .req_line_speed = 0, | |
11030 | .speed_cap_mask = 0, | |
11031 | .req_duplex = 0, | |
11032 | .rsrv = 0, | |
11033 | .config_init = (config_init_t) elink_848x3_config_init, | |
11034 | .read_status = (read_status_t) elink_848xx_read_status, | |
11035 | .link_reset = (link_reset_t) elink_848x3_link_reset, | |
11036 | .config_loopback = (config_loopback_t) NULL, | |
11037 | .format_fw_ver = (format_fw_ver_t) elink_848xx_format_ver, | |
11038 | .hw_reset = (hw_reset_t) NULL, | |
11039 | .set_link_led = (set_link_led_t) elink_848xx_set_link_led, | |
11040 | .phy_specific_func = (phy_specific_func_t) elink_848xx_specific_func | |
11041 | }; | |
11042 | ||
11043 | static const struct elink_phy phy_84833 = { | |
11044 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833, | |
11045 | .addr = 0xff, | |
11046 | .def_md_devad = 0, | |
11047 | .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | | |
11048 | ELINK_FLAGS_REARM_LATCH_SIGNAL | | |
11049 | ELINK_FLAGS_TX_ERROR_CHECK | ELINK_FLAGS_TEMPERATURE), | |
11050 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11051 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11052 | .mdio_ctrl = 0, | |
11053 | .supported = (ELINK_SUPPORTED_100baseT_Half | | |
11054 | ELINK_SUPPORTED_100baseT_Full | | |
11055 | ELINK_SUPPORTED_1000baseT_Full | | |
11056 | ELINK_SUPPORTED_10000baseT_Full | | |
11057 | ELINK_SUPPORTED_TP | | |
11058 | ELINK_SUPPORTED_Autoneg | | |
11059 | ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), | |
11060 | .media_type = ELINK_ETH_PHY_BASE_T, | |
11061 | .ver_addr = 0, | |
11062 | .req_flow_ctrl = 0, | |
11063 | .req_line_speed = 0, | |
11064 | .speed_cap_mask = 0, | |
11065 | .req_duplex = 0, | |
11066 | .rsrv = 0, | |
11067 | .config_init = (config_init_t) elink_848x3_config_init, | |
11068 | .read_status = (read_status_t) elink_848xx_read_status, | |
11069 | .link_reset = (link_reset_t) elink_848x3_link_reset, | |
11070 | .config_loopback = (config_loopback_t) NULL, | |
11071 | .format_fw_ver = (format_fw_ver_t) elink_848xx_format_ver, | |
11072 | .hw_reset = (hw_reset_t) elink_84833_hw_reset_phy, | |
11073 | .set_link_led = (set_link_led_t) elink_848xx_set_link_led, | |
11074 | .phy_specific_func = (phy_specific_func_t) elink_848xx_specific_func | |
11075 | }; | |
11076 | ||
11077 | static const struct elink_phy phy_84834 = { | |
11078 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834, | |
11079 | .addr = 0xff, | |
11080 | .def_md_devad = 0, | |
11081 | .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ | | |
11082 | ELINK_FLAGS_REARM_LATCH_SIGNAL, | |
11083 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11084 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11085 | .mdio_ctrl = 0, | |
11086 | .supported = (ELINK_SUPPORTED_100baseT_Half | | |
11087 | ELINK_SUPPORTED_100baseT_Full | | |
11088 | ELINK_SUPPORTED_1000baseT_Full | | |
11089 | ELINK_SUPPORTED_10000baseT_Full | | |
11090 | ELINK_SUPPORTED_TP | | |
11091 | ELINK_SUPPORTED_Autoneg | | |
11092 | ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), | |
11093 | .media_type = ELINK_ETH_PHY_BASE_T, | |
11094 | .ver_addr = 0, | |
11095 | .req_flow_ctrl = 0, | |
11096 | .req_line_speed = 0, | |
11097 | .speed_cap_mask = 0, | |
11098 | .req_duplex = 0, | |
11099 | .rsrv = 0, | |
11100 | .config_init = (config_init_t) elink_848x3_config_init, | |
11101 | .read_status = (read_status_t) elink_848xx_read_status, | |
11102 | .link_reset = (link_reset_t) elink_848x3_link_reset, | |
11103 | .config_loopback = (config_loopback_t) NULL, | |
11104 | .format_fw_ver = (format_fw_ver_t) elink_848xx_format_ver, | |
11105 | .hw_reset = (hw_reset_t) elink_84833_hw_reset_phy, | |
11106 | .set_link_led = (set_link_led_t) elink_848xx_set_link_led, | |
11107 | .phy_specific_func = (phy_specific_func_t) elink_848xx_specific_func | |
11108 | }; | |
11109 | ||
11110 | static const struct elink_phy phy_54618se = { | |
11111 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE, | |
11112 | .addr = 0xff, | |
11113 | .def_md_devad = 0, | |
11114 | .flags = ELINK_FLAGS_INIT_XGXS_FIRST, | |
11115 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11116 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11117 | .mdio_ctrl = 0, | |
11118 | .supported = (ELINK_SUPPORTED_10baseT_Half | | |
11119 | ELINK_SUPPORTED_10baseT_Full | | |
11120 | ELINK_SUPPORTED_100baseT_Half | | |
11121 | ELINK_SUPPORTED_100baseT_Full | | |
11122 | ELINK_SUPPORTED_1000baseT_Full | | |
11123 | ELINK_SUPPORTED_TP | | |
11124 | ELINK_SUPPORTED_Autoneg | | |
11125 | ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause), | |
11126 | .media_type = ELINK_ETH_PHY_BASE_T, | |
11127 | .ver_addr = 0, | |
11128 | .req_flow_ctrl = 0, | |
11129 | .req_line_speed = 0, | |
11130 | .speed_cap_mask = 0, | |
11131 | /* req_duplex = */ 0, | |
11132 | /* rsrv = */ 0, | |
11133 | .config_init = (config_init_t) elink_54618se_config_init, | |
11134 | .read_status = (read_status_t) elink_54618se_read_status, | |
11135 | .link_reset = (link_reset_t) elink_54618se_link_reset, | |
11136 | .config_loopback = (config_loopback_t) elink_54618se_config_loopback, | |
11137 | .format_fw_ver = (format_fw_ver_t) NULL, | |
11138 | .hw_reset = (hw_reset_t) NULL, | |
11139 | .set_link_led = (set_link_led_t) elink_5461x_set_link_led, | |
11140 | .phy_specific_func = (phy_specific_func_t) elink_54618se_specific_func | |
11141 | }; | |
11142 | ||
11143 | /*****************************************************************/ | |
11144 | /* */ | |
11145 | /* Populate the phy according. Main function: elink_populate_phy */ | |
11146 | /* */ | |
11147 | /*****************************************************************/ | |
11148 | ||
11149 | static void elink_populate_preemphasis(struct bnx2x_softc *sc, | |
11150 | uint32_t shmem_base, | |
11151 | struct elink_phy *phy, uint8_t port, | |
11152 | uint8_t phy_index) | |
11153 | { | |
11154 | /* Get the 4 lanes xgxs config rx and tx */ | |
11155 | uint32_t rx = 0, tx = 0, i; | |
11156 | for (i = 0; i < 2; i++) { | |
11157 | /* INT_PHY and ELINK_EXT_PHY1 share the same value location in | |
11158 | * the shmem. When num_phys is greater than 1, than this value | |
11159 | * applies only to ELINK_EXT_PHY1 | |
11160 | */ | |
11161 | if (phy_index == ELINK_INT_PHY || phy_index == ELINK_EXT_PHY1) { | |
11162 | rx = REG_RD(sc, shmem_base + | |
11163 | offsetof(struct shmem_region, | |
11164 | dev_info.port_hw_config[port]. | |
11165 | xgxs_config_rx[i << 1])); | |
11166 | ||
11167 | tx = REG_RD(sc, shmem_base + | |
11168 | offsetof(struct shmem_region, | |
11169 | dev_info.port_hw_config[port]. | |
11170 | xgxs_config_tx[i << 1])); | |
11171 | } else { | |
11172 | rx = REG_RD(sc, shmem_base + | |
11173 | offsetof(struct shmem_region, | |
11174 | dev_info.port_hw_config[port]. | |
11175 | xgxs_config2_rx[i << 1])); | |
11176 | ||
11177 | tx = REG_RD(sc, shmem_base + | |
11178 | offsetof(struct shmem_region, | |
11179 | dev_info.port_hw_config[port]. | |
11180 | xgxs_config2_rx[i << 1])); | |
11181 | } | |
11182 | ||
11183 | phy->rx_preemphasis[i << 1] = ((rx >> 16) & 0xffff); | |
11184 | phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); | |
11185 | ||
11186 | phy->tx_preemphasis[i << 1] = ((tx >> 16) & 0xffff); | |
11187 | phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); | |
11188 | } | |
11189 | } | |
11190 | ||
11191 | static uint32_t elink_get_ext_phy_config(struct bnx2x_softc *sc, | |
11192 | uint32_t shmem_base, uint8_t phy_index, | |
11193 | uint8_t port) | |
11194 | { | |
11195 | uint32_t ext_phy_config = 0; | |
11196 | switch (phy_index) { | |
11197 | case ELINK_EXT_PHY1: | |
11198 | ext_phy_config = REG_RD(sc, shmem_base + | |
11199 | offsetof(struct shmem_region, | |
11200 | dev_info.port_hw_config[port]. | |
11201 | external_phy_config)); | |
11202 | break; | |
11203 | case ELINK_EXT_PHY2: | |
11204 | ext_phy_config = REG_RD(sc, shmem_base + | |
11205 | offsetof(struct shmem_region, | |
11206 | dev_info.port_hw_config[port]. | |
11207 | external_phy_config2)); | |
11208 | break; | |
11209 | default: | |
11210 | PMD_DRV_LOG(DEBUG, "Invalid phy_index %d", phy_index); | |
11211 | return ELINK_STATUS_ERROR; | |
11212 | } | |
11213 | ||
11214 | return ext_phy_config; | |
11215 | } | |
11216 | ||
11217 | static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc, | |
11218 | uint32_t shmem_base, uint8_t port, | |
11219 | struct elink_phy *phy) | |
11220 | { | |
11221 | uint32_t phy_addr; | |
11222 | __rte_unused uint32_t chip_id; | |
11223 | uint32_t switch_cfg = (REG_RD(sc, shmem_base + | |
11224 | offsetof(struct shmem_region, | |
11225 | dev_info. | |
11226 | port_feature_config[port]. | |
11227 | link_config)) & | |
11228 | PORT_FEATURE_CONNECTED_SWITCH_MASK); | |
11229 | chip_id = | |
11230 | (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) | | |
11231 | ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12); | |
11232 | ||
11233 | PMD_DRV_LOG(DEBUG, ":chip_id = 0x%x", chip_id); | |
11234 | if (USES_WARPCORE(sc)) { | |
11235 | uint32_t serdes_net_if; | |
11236 | phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR); | |
11237 | *phy = phy_warpcore; | |
11238 | if (REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) | |
11239 | phy->flags |= ELINK_FLAGS_4_PORT_MODE; | |
11240 | else | |
11241 | phy->flags &= ~ELINK_FLAGS_4_PORT_MODE; | |
11242 | /* Check Dual mode */ | |
11243 | serdes_net_if = (REG_RD(sc, shmem_base + | |
11244 | offsetof(struct shmem_region, | |
11245 | dev_info.port_hw_config[port]. | |
11246 | default_cfg)) & | |
11247 | PORT_HW_CFG_NET_SERDES_IF_MASK); | |
11248 | /* Set the appropriate supported and flags indications per | |
11249 | * interface type of the chip | |
11250 | */ | |
11251 | switch (serdes_net_if) { | |
11252 | case PORT_HW_CFG_NET_SERDES_IF_SGMII: | |
11253 | phy->supported &= (ELINK_SUPPORTED_10baseT_Half | | |
11254 | ELINK_SUPPORTED_10baseT_Full | | |
11255 | ELINK_SUPPORTED_100baseT_Half | | |
11256 | ELINK_SUPPORTED_100baseT_Full | | |
11257 | ELINK_SUPPORTED_1000baseT_Full | | |
11258 | ELINK_SUPPORTED_FIBRE | | |
11259 | ELINK_SUPPORTED_Autoneg | | |
11260 | ELINK_SUPPORTED_Pause | | |
11261 | ELINK_SUPPORTED_Asym_Pause); | |
11262 | phy->media_type = ELINK_ETH_PHY_BASE_T; | |
11263 | break; | |
11264 | case PORT_HW_CFG_NET_SERDES_IF_XFI: | |
11265 | phy->supported &= (ELINK_SUPPORTED_1000baseT_Full | | |
11266 | ELINK_SUPPORTED_10000baseT_Full | | |
11267 | ELINK_SUPPORTED_FIBRE | | |
11268 | ELINK_SUPPORTED_Pause | | |
11269 | ELINK_SUPPORTED_Asym_Pause); | |
11270 | phy->media_type = ELINK_ETH_PHY_XFP_FIBER; | |
11271 | break; | |
11272 | case PORT_HW_CFG_NET_SERDES_IF_SFI: | |
11273 | phy->supported &= (ELINK_SUPPORTED_1000baseT_Full | | |
11274 | ELINK_SUPPORTED_10000baseT_Full | | |
11275 | ELINK_SUPPORTED_FIBRE | | |
11276 | ELINK_SUPPORTED_Pause | | |
11277 | ELINK_SUPPORTED_Asym_Pause); | |
11278 | phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER; | |
11279 | break; | |
11280 | case PORT_HW_CFG_NET_SERDES_IF_KR: | |
11281 | phy->media_type = ELINK_ETH_PHY_KR; | |
11282 | phy->supported &= (ELINK_SUPPORTED_1000baseT_Full | | |
11283 | ELINK_SUPPORTED_10000baseT_Full | | |
11284 | ELINK_SUPPORTED_FIBRE | | |
11285 | ELINK_SUPPORTED_Autoneg | | |
11286 | ELINK_SUPPORTED_Pause | | |
11287 | ELINK_SUPPORTED_Asym_Pause); | |
11288 | break; | |
11289 | case PORT_HW_CFG_NET_SERDES_IF_DXGXS: | |
11290 | phy->media_type = ELINK_ETH_PHY_KR; | |
11291 | phy->flags |= ELINK_FLAGS_WC_DUAL_MODE; | |
11292 | phy->supported &= (ELINK_SUPPORTED_20000baseMLD2_Full | | |
11293 | ELINK_SUPPORTED_FIBRE | | |
11294 | ELINK_SUPPORTED_Pause | | |
11295 | ELINK_SUPPORTED_Asym_Pause); | |
11296 | break; | |
11297 | case PORT_HW_CFG_NET_SERDES_IF_KR2: | |
11298 | phy->media_type = ELINK_ETH_PHY_KR; | |
11299 | phy->flags |= ELINK_FLAGS_WC_DUAL_MODE; | |
11300 | phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full | | |
11301 | ELINK_SUPPORTED_10000baseT_Full | | |
11302 | ELINK_SUPPORTED_1000baseT_Full | | |
11303 | ELINK_SUPPORTED_Autoneg | | |
11304 | ELINK_SUPPORTED_FIBRE | | |
11305 | ELINK_SUPPORTED_Pause | | |
11306 | ELINK_SUPPORTED_Asym_Pause); | |
11307 | phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK; | |
11308 | break; | |
11309 | default: | |
11310 | PMD_DRV_LOG(DEBUG, "Unknown WC interface type 0x%x", | |
11311 | serdes_net_if); | |
11312 | break; | |
11313 | } | |
11314 | ||
11315 | /* Enable MDC/MDIO work-around for E3 A0 since free running MDC | |
11316 | * was not set as expected. For B0, ECO will be enabled so there | |
11317 | * won't be an issue there | |
11318 | */ | |
11319 | if (CHIP_REV(sc) == CHIP_REV_Ax) | |
11320 | phy->flags |= ELINK_FLAGS_MDC_MDIO_WA; | |
11321 | else | |
11322 | phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0; | |
11323 | } else { | |
11324 | switch (switch_cfg) { | |
11325 | case ELINK_SWITCH_CFG_1G: | |
11326 | phy_addr = REG_RD(sc, | |
11327 | NIG_REG_SERDES0_CTRL_PHY_ADDR + | |
11328 | port * 0x10); | |
11329 | *phy = phy_serdes; | |
11330 | break; | |
11331 | case ELINK_SWITCH_CFG_10G: | |
11332 | phy_addr = REG_RD(sc, | |
11333 | NIG_REG_XGXS0_CTRL_PHY_ADDR + | |
11334 | port * 0x18); | |
11335 | *phy = phy_xgxs; | |
11336 | break; | |
11337 | default: | |
11338 | PMD_DRV_LOG(DEBUG, "Invalid switch_cfg"); | |
11339 | return ELINK_STATUS_ERROR; | |
11340 | } | |
11341 | } | |
11342 | phy->addr = (uint8_t) phy_addr; | |
11343 | phy->mdio_ctrl = elink_get_emac_base(sc, | |
11344 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, | |
11345 | port); | |
11346 | if (CHIP_IS_E2(sc)) | |
11347 | phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR; | |
11348 | else | |
11349 | phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR; | |
11350 | ||
11351 | PMD_DRV_LOG(DEBUG, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x", | |
11352 | port, phy->addr, phy->mdio_ctrl); | |
11353 | ||
11354 | elink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY); | |
11355 | return ELINK_STATUS_OK; | |
11356 | } | |
11357 | ||
11358 | static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc, | |
11359 | uint8_t phy_index, | |
11360 | uint32_t shmem_base, | |
11361 | uint32_t shmem2_base, | |
11362 | uint8_t port, | |
11363 | struct elink_phy *phy) | |
11364 | { | |
11365 | uint32_t ext_phy_config, phy_type, config2; | |
11366 | uint32_t mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH; | |
11367 | ext_phy_config = elink_get_ext_phy_config(sc, shmem_base, | |
11368 | phy_index, port); | |
11369 | phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config); | |
11370 | /* Select the phy type */ | |
11371 | switch (phy_type) { | |
11372 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073: | |
11373 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED; | |
11374 | *phy = phy_8073; | |
11375 | break; | |
11376 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705: | |
11377 | *phy = phy_8705; | |
11378 | break; | |
11379 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706: | |
11380 | *phy = phy_8706; | |
11381 | break; | |
11382 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726: | |
11383 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
11384 | *phy = phy_8726; | |
11385 | break; | |
11386 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC: | |
11387 | /* BNX2X8727_NOC => BNX2X8727 no over current */ | |
11388 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
11389 | *phy = phy_8727; | |
11390 | phy->flags |= ELINK_FLAGS_NOC; | |
11391 | break; | |
11392 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722: | |
11393 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727: | |
11394 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
11395 | *phy = phy_8727; | |
11396 | break; | |
11397 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481: | |
11398 | *phy = phy_8481; | |
11399 | break; | |
11400 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823: | |
11401 | *phy = phy_84823; | |
11402 | break; | |
11403 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833: | |
11404 | *phy = phy_84833; | |
11405 | break; | |
11406 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834: | |
11407 | *phy = phy_84834; | |
11408 | break; | |
11409 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54616: | |
11410 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE: | |
11411 | *phy = phy_54618se; | |
11412 | if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) | |
11413 | phy->flags |= ELINK_FLAGS_EEE; | |
11414 | break; | |
11415 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: | |
11416 | *phy = phy_7101; | |
11417 | break; | |
11418 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: | |
11419 | *phy = phy_null; | |
11420 | return ELINK_STATUS_ERROR; | |
11421 | default: | |
11422 | *phy = phy_null; | |
11423 | /* In case external PHY wasn't found */ | |
11424 | if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && | |
11425 | (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) | |
11426 | return ELINK_STATUS_ERROR; | |
11427 | return ELINK_STATUS_OK; | |
11428 | } | |
11429 | ||
11430 | phy->addr = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config); | |
11431 | elink_populate_preemphasis(sc, shmem_base, phy, port, phy_index); | |
11432 | ||
11433 | /* The shmem address of the phy version is located on different | |
11434 | * structures. In case this structure is too old, do not set | |
11435 | * the address | |
11436 | */ | |
11437 | config2 = REG_RD(sc, shmem_base + offsetof(struct shmem_region, | |
11438 | dev_info.shared_hw_config. | |
11439 | config2)); | |
11440 | if (phy_index == ELINK_EXT_PHY1) { | |
11441 | phy->ver_addr = shmem_base + offsetof(struct shmem_region, | |
11442 | port_mb[port]. | |
11443 | ext_phy_fw_version); | |
11444 | ||
11445 | /* Check specific mdc mdio settings */ | |
11446 | if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) | |
11447 | mdc_mdio_access = config2 & | |
11448 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; | |
11449 | } else { | |
11450 | uint32_t size = REG_RD(sc, shmem2_base); | |
11451 | ||
11452 | if (size > offsetof(struct shmem2_region, ext_phy_fw_version2)) { | |
11453 | phy->ver_addr = shmem2_base + | |
11454 | offsetof(struct shmem2_region, | |
11455 | ext_phy_fw_version2[port]); | |
11456 | } | |
11457 | /* Check specific mdc mdio settings */ | |
11458 | if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) | |
11459 | mdc_mdio_access = (config2 & | |
11460 | SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) | |
11461 | >> (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - | |
11462 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); | |
11463 | } | |
11464 | phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port); | |
11465 | ||
11466 | if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) || | |
11467 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) && | |
11468 | (phy->ver_addr)) { | |
11469 | /* Remove 100Mb link supported for BNX2X84833/4 when phy fw | |
11470 | * version lower than or equal to 1.39 | |
11471 | */ | |
11472 | uint32_t raw_ver = REG_RD(sc, phy->ver_addr); | |
11473 | if (((raw_ver & 0x7F) <= 39) && (((raw_ver & 0xF80) >> 7) <= 1)) | |
11474 | phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half | | |
11475 | ELINK_SUPPORTED_100baseT_Full); | |
11476 | } | |
11477 | ||
11478 | PMD_DRV_LOG(DEBUG, "phy_type 0x%x port %d found in index %d", | |
11479 | phy_type, port, phy_index); | |
11480 | PMD_DRV_LOG(DEBUG, " addr=0x%x, mdio_ctl=0x%x", | |
11481 | phy->addr, phy->mdio_ctrl); | |
11482 | return ELINK_STATUS_OK; | |
11483 | } | |
11484 | ||
11485 | static elink_status_t elink_populate_phy(struct bnx2x_softc *sc, | |
11486 | uint8_t phy_index, uint32_t shmem_base, | |
11487 | uint32_t shmem2_base, uint8_t port, | |
11488 | struct elink_phy *phy) | |
11489 | { | |
11490 | elink_status_t status = ELINK_STATUS_OK; | |
11491 | phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; | |
11492 | if (phy_index == ELINK_INT_PHY) | |
11493 | return elink_populate_int_phy(sc, shmem_base, port, phy); | |
11494 | status = elink_populate_ext_phy(sc, phy_index, shmem_base, shmem2_base, | |
11495 | port, phy); | |
11496 | return status; | |
11497 | } | |
11498 | ||
11499 | static void elink_phy_def_cfg(struct elink_params *params, | |
11500 | struct elink_phy *phy, uint8_t phy_index) | |
11501 | { | |
11502 | struct bnx2x_softc *sc = params->sc; | |
11503 | uint32_t link_config; | |
11504 | /* Populate the default phy configuration for MF mode */ | |
11505 | if (phy_index == ELINK_EXT_PHY2) { | |
11506 | link_config = REG_RD(sc, params->shmem_base + | |
11507 | offsetof(struct shmem_region, | |
11508 | dev_info.port_feature_config | |
11509 | [params->port].link_config2)); | |
11510 | phy->speed_cap_mask = | |
11511 | REG_RD(sc, | |
11512 | params->shmem_base + offsetof(struct shmem_region, | |
11513 | dev_info.port_hw_config | |
11514 | [params->port]. | |
11515 | speed_capability_mask2)); | |
11516 | } else { | |
11517 | link_config = REG_RD(sc, params->shmem_base + | |
11518 | offsetof(struct shmem_region, | |
11519 | dev_info.port_feature_config | |
11520 | [params->port].link_config)); | |
11521 | phy->speed_cap_mask = | |
11522 | REG_RD(sc, | |
11523 | params->shmem_base + offsetof(struct shmem_region, | |
11524 | dev_info.port_hw_config | |
11525 | [params->port]. | |
11526 | speed_capability_mask)); | |
11527 | } | |
11528 | ||
11529 | PMD_DRV_LOG(DEBUG, | |
11530 | "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x", | |
11531 | phy_index, link_config, phy->speed_cap_mask); | |
11532 | ||
11533 | phy->req_duplex = DUPLEX_FULL; | |
11534 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { | |
11535 | case PORT_FEATURE_LINK_SPEED_10M_HALF: | |
11536 | phy->req_duplex = DUPLEX_HALF; | |
11537 | case PORT_FEATURE_LINK_SPEED_10M_FULL: | |
11538 | phy->req_line_speed = ELINK_SPEED_10; | |
11539 | break; | |
11540 | case PORT_FEATURE_LINK_SPEED_100M_HALF: | |
11541 | phy->req_duplex = DUPLEX_HALF; | |
11542 | case PORT_FEATURE_LINK_SPEED_100M_FULL: | |
11543 | phy->req_line_speed = ELINK_SPEED_100; | |
11544 | break; | |
11545 | case PORT_FEATURE_LINK_SPEED_1G: | |
11546 | phy->req_line_speed = ELINK_SPEED_1000; | |
11547 | break; | |
11548 | case PORT_FEATURE_LINK_SPEED_2_5G: | |
11549 | phy->req_line_speed = ELINK_SPEED_2500; | |
11550 | break; | |
11551 | case PORT_FEATURE_LINK_SPEED_10G_CX4: | |
11552 | phy->req_line_speed = ELINK_SPEED_10000; | |
11553 | break; | |
11554 | default: | |
11555 | phy->req_line_speed = ELINK_SPEED_AUTO_NEG; | |
11556 | break; | |
11557 | } | |
11558 | ||
11559 | switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { | |
11560 | case PORT_FEATURE_FLOW_CONTROL_AUTO: | |
11561 | phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO; | |
11562 | break; | |
11563 | case PORT_FEATURE_FLOW_CONTROL_TX: | |
11564 | phy->req_flow_ctrl = ELINK_FLOW_CTRL_TX; | |
11565 | break; | |
11566 | case PORT_FEATURE_FLOW_CONTROL_RX: | |
11567 | phy->req_flow_ctrl = ELINK_FLOW_CTRL_RX; | |
11568 | break; | |
11569 | case PORT_FEATURE_FLOW_CONTROL_BOTH: | |
11570 | phy->req_flow_ctrl = ELINK_FLOW_CTRL_BOTH; | |
11571 | break; | |
11572 | default: | |
11573 | phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE; | |
11574 | break; | |
11575 | } | |
11576 | } | |
11577 | ||
11578 | uint32_t elink_phy_selection(struct elink_params *params) | |
11579 | { | |
11580 | uint32_t phy_config_swapped, prio_cfg; | |
11581 | uint32_t return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT; | |
11582 | ||
11583 | phy_config_swapped = params->multi_phy_config & | |
11584 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
11585 | ||
11586 | prio_cfg = params->multi_phy_config & PORT_HW_CFG_PHY_SELECTION_MASK; | |
11587 | ||
11588 | if (phy_config_swapped) { | |
11589 | switch (prio_cfg) { | |
11590 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
11591 | return_cfg = | |
11592 | PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; | |
11593 | break; | |
11594 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
11595 | return_cfg = | |
11596 | PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; | |
11597 | break; | |
11598 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: | |
11599 | return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; | |
11600 | break; | |
11601 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: | |
11602 | return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; | |
11603 | break; | |
11604 | } | |
11605 | } else | |
11606 | return_cfg = prio_cfg; | |
11607 | ||
11608 | return return_cfg; | |
11609 | } | |
11610 | ||
11611 | elink_status_t elink_phy_probe(struct elink_params * params) | |
11612 | { | |
11613 | uint8_t phy_index, actual_phy_idx; | |
11614 | uint32_t phy_config_swapped, sync_offset, media_types; | |
11615 | struct bnx2x_softc *sc = params->sc; | |
11616 | struct elink_phy *phy; | |
11617 | params->num_phys = 0; | |
11618 | PMD_DRV_LOG(DEBUG, "Begin phy probe"); | |
11619 | ||
11620 | phy_config_swapped = params->multi_phy_config & | |
11621 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
11622 | ||
11623 | for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) { | |
11624 | actual_phy_idx = phy_index; | |
11625 | if (phy_config_swapped) { | |
11626 | if (phy_index == ELINK_EXT_PHY1) | |
11627 | actual_phy_idx = ELINK_EXT_PHY2; | |
11628 | else if (phy_index == ELINK_EXT_PHY2) | |
11629 | actual_phy_idx = ELINK_EXT_PHY1; | |
11630 | } | |
11631 | PMD_DRV_LOG(DEBUG, "phy_config_swapped %x, phy_index %x," | |
11632 | " actual_phy_idx %x", phy_config_swapped, | |
11633 | phy_index, actual_phy_idx); | |
11634 | phy = ¶ms->phy[actual_phy_idx]; | |
11635 | if (elink_populate_phy(sc, phy_index, params->shmem_base, | |
11636 | params->shmem2_base, params->port, | |
11637 | phy) != ELINK_STATUS_OK) { | |
11638 | params->num_phys = 0; | |
11639 | PMD_DRV_LOG(DEBUG, "phy probe failed in phy index %d", | |
11640 | phy_index); | |
11641 | for (phy_index = ELINK_INT_PHY; | |
11642 | phy_index < ELINK_MAX_PHYS; phy_index++) | |
11643 | *phy = phy_null; | |
11644 | return ELINK_STATUS_ERROR; | |
11645 | } | |
11646 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) | |
11647 | break; | |
11648 | ||
11649 | if (params->feature_config_flags & | |
11650 | ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET) | |
11651 | phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK; | |
11652 | ||
11653 | if (!(params->feature_config_flags & | |
11654 | ELINK_FEATURE_CONFIG_MT_SUPPORT)) | |
11655 | phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G; | |
11656 | ||
11657 | sync_offset = params->shmem_base + | |
11658 | offsetof(struct shmem_region, | |
11659 | dev_info.port_hw_config[params->port].media_type); | |
11660 | media_types = REG_RD(sc, sync_offset); | |
11661 | ||
11662 | /* Update media type for non-PMF sync only for the first time | |
11663 | * In case the media type changes afterwards, it will be updated | |
11664 | * using the update_status function | |
11665 | */ | |
11666 | if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << | |
11667 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * | |
11668 | actual_phy_idx))) == 0) { | |
11669 | media_types |= ((phy->media_type & | |
11670 | PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << | |
11671 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * | |
11672 | actual_phy_idx)); | |
11673 | } | |
11674 | REG_WR(sc, sync_offset, media_types); | |
11675 | ||
11676 | elink_phy_def_cfg(params, phy, phy_index); | |
11677 | params->num_phys++; | |
11678 | } | |
11679 | ||
11680 | PMD_DRV_LOG(DEBUG, "End phy probe. #phys found %x", params->num_phys); | |
11681 | return ELINK_STATUS_OK; | |
11682 | } | |
11683 | ||
11684 | static void elink_init_bmac_loopback(struct elink_params *params, | |
11685 | struct elink_vars *vars) | |
11686 | { | |
11687 | struct bnx2x_softc *sc = params->sc; | |
11688 | vars->link_up = 1; | |
11689 | vars->line_speed = ELINK_SPEED_10000; | |
11690 | vars->duplex = DUPLEX_FULL; | |
11691 | vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; | |
11692 | vars->mac_type = ELINK_MAC_TYPE_BMAC; | |
11693 | ||
11694 | vars->phy_flags = PHY_XGXS_FLAG; | |
11695 | ||
11696 | elink_xgxs_deassert(params); | |
11697 | ||
11698 | /* Set bmac loopback */ | |
11699 | elink_bmac_enable(params, vars, 1, 1); | |
11700 | ||
11701 | REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); | |
11702 | } | |
11703 | ||
11704 | static void elink_init_emac_loopback(struct elink_params *params, | |
11705 | struct elink_vars *vars) | |
11706 | { | |
11707 | struct bnx2x_softc *sc = params->sc; | |
11708 | vars->link_up = 1; | |
11709 | vars->line_speed = ELINK_SPEED_1000; | |
11710 | vars->duplex = DUPLEX_FULL; | |
11711 | vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; | |
11712 | vars->mac_type = ELINK_MAC_TYPE_EMAC; | |
11713 | ||
11714 | vars->phy_flags = PHY_XGXS_FLAG; | |
11715 | ||
11716 | elink_xgxs_deassert(params); | |
11717 | /* Set bmac loopback */ | |
11718 | elink_emac_enable(params, vars, 1); | |
11719 | elink_emac_program(params, vars); | |
11720 | REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); | |
11721 | } | |
11722 | ||
11723 | static void elink_init_xmac_loopback(struct elink_params *params, | |
11724 | struct elink_vars *vars) | |
11725 | { | |
11726 | struct bnx2x_softc *sc = params->sc; | |
11727 | vars->link_up = 1; | |
11728 | if (!params->req_line_speed[0]) | |
11729 | vars->line_speed = ELINK_SPEED_10000; | |
11730 | else | |
11731 | vars->line_speed = params->req_line_speed[0]; | |
11732 | vars->duplex = DUPLEX_FULL; | |
11733 | vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; | |
11734 | vars->mac_type = ELINK_MAC_TYPE_XMAC; | |
11735 | vars->phy_flags = PHY_XGXS_FLAG; | |
11736 | /* Set WC to loopback mode since link is required to provide clock | |
11737 | * to the XMAC in 20G mode | |
11738 | */ | |
11739 | elink_set_aer_mmd(params, ¶ms->phy[0]); | |
11740 | elink_warpcore_reset_lane(sc, ¶ms->phy[0], 0); | |
11741 | params->phy[ELINK_INT_PHY].config_loopback(¶ms->phy[ELINK_INT_PHY], | |
11742 | params); | |
11743 | ||
11744 | elink_xmac_enable(params, vars, 1); | |
11745 | REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); | |
11746 | } | |
11747 | ||
11748 | static void elink_init_umac_loopback(struct elink_params *params, | |
11749 | struct elink_vars *vars) | |
11750 | { | |
11751 | struct bnx2x_softc *sc = params->sc; | |
11752 | vars->link_up = 1; | |
11753 | vars->line_speed = ELINK_SPEED_1000; | |
11754 | vars->duplex = DUPLEX_FULL; | |
11755 | vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; | |
11756 | vars->mac_type = ELINK_MAC_TYPE_UMAC; | |
11757 | vars->phy_flags = PHY_XGXS_FLAG; | |
11758 | elink_umac_enable(params, vars, 1); | |
11759 | ||
11760 | REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); | |
11761 | } | |
11762 | ||
11763 | static void elink_init_xgxs_loopback(struct elink_params *params, | |
11764 | struct elink_vars *vars) | |
11765 | { | |
11766 | struct bnx2x_softc *sc = params->sc; | |
11767 | struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY]; | |
11768 | vars->link_up = 1; | |
11769 | vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; | |
11770 | vars->duplex = DUPLEX_FULL; | |
11771 | if (params->req_line_speed[0] == ELINK_SPEED_1000) | |
11772 | vars->line_speed = ELINK_SPEED_1000; | |
11773 | else if ((params->req_line_speed[0] == ELINK_SPEED_20000) || | |
11774 | (int_phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) | |
11775 | vars->line_speed = ELINK_SPEED_20000; | |
11776 | else | |
11777 | vars->line_speed = ELINK_SPEED_10000; | |
11778 | ||
11779 | if (!USES_WARPCORE(sc)) | |
11780 | elink_xgxs_deassert(params); | |
11781 | elink_link_initialize(params, vars); | |
11782 | ||
11783 | if (params->req_line_speed[0] == ELINK_SPEED_1000) { | |
11784 | if (USES_WARPCORE(sc)) | |
11785 | elink_umac_enable(params, vars, 0); | |
11786 | else { | |
11787 | elink_emac_program(params, vars); | |
11788 | elink_emac_enable(params, vars, 0); | |
11789 | } | |
11790 | } else { | |
11791 | if (USES_WARPCORE(sc)) | |
11792 | elink_xmac_enable(params, vars, 0); | |
11793 | else | |
11794 | elink_bmac_enable(params, vars, 0, 1); | |
11795 | } | |
11796 | ||
11797 | if (params->loopback_mode == ELINK_LOOPBACK_XGXS) { | |
11798 | /* Set 10G XGXS loopback */ | |
11799 | int_phy->config_loopback(int_phy, params); | |
11800 | } else { | |
11801 | /* Set external phy loopback */ | |
11802 | uint8_t phy_index; | |
11803 | for (phy_index = ELINK_EXT_PHY1; | |
11804 | phy_index < params->num_phys; phy_index++) | |
11805 | if (params->phy[phy_index].config_loopback) | |
11806 | params->phy[phy_index].config_loopback(¶ms-> | |
11807 | phy | |
11808 | [phy_index], | |
11809 | params); | |
11810 | } | |
11811 | REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); | |
11812 | ||
11813 | elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed); | |
11814 | } | |
11815 | ||
11816 | void elink_set_rx_filter(struct elink_params *params, uint8_t en) | |
11817 | { | |
11818 | struct bnx2x_softc *sc = params->sc; | |
11819 | uint8_t val = en * 0x1F; | |
11820 | ||
11821 | /* Open / close the gate between the NIG and the BRB */ | |
11822 | if (!CHIP_IS_E1x(sc)) | |
11823 | val |= en * 0x20; | |
11824 | REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + params->port * 4, val); | |
11825 | ||
11826 | REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port * 4, en * 0x3); | |
11827 | ||
11828 | REG_WR(sc, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : | |
11829 | NIG_REG_LLH0_BRB1_NOT_MCP), en); | |
11830 | } | |
11831 | ||
11832 | static elink_status_t elink_avoid_link_flap(struct elink_params *params, | |
11833 | struct elink_vars *vars) | |
11834 | { | |
11835 | uint32_t phy_idx; | |
11836 | uint32_t dont_clear_stat, lfa_sts; | |
11837 | struct bnx2x_softc *sc = params->sc; | |
11838 | ||
11839 | /* Sync the link parameters */ | |
11840 | elink_link_status_update(params, vars); | |
11841 | ||
11842 | /* | |
11843 | * The module verification was already done by previous link owner, | |
11844 | * so this call is meant only to get warning message | |
11845 | */ | |
11846 | ||
11847 | for (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) { | |
11848 | struct elink_phy *phy = ¶ms->phy[phy_idx]; | |
11849 | if (phy->phy_specific_func) { | |
11850 | PMD_DRV_LOG(DEBUG, "Calling PHY specific func"); | |
11851 | phy->phy_specific_func(phy, params, ELINK_PHY_INIT); | |
11852 | } | |
11853 | if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) || | |
11854 | (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER) || | |
11855 | (phy->media_type == ELINK_ETH_PHY_DA_TWINAX)) | |
11856 | elink_verify_sfp_module(phy, params); | |
11857 | } | |
11858 | lfa_sts = REG_RD(sc, params->lfa_base + | |
11859 | offsetof(struct shmem_lfa, lfa_sts)); | |
11860 | ||
11861 | dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT; | |
11862 | ||
11863 | /* Re-enable the NIG/MAC */ | |
11864 | if (CHIP_IS_E3(sc)) { | |
11865 | if (!dont_clear_stat) { | |
11866 | REG_WR(sc, GRCBASE_MISC + | |
11867 | MISC_REGISTERS_RESET_REG_2_CLEAR, | |
11868 | (MISC_REGISTERS_RESET_REG_2_MSTAT0 << | |
11869 | params->port)); | |
11870 | REG_WR(sc, GRCBASE_MISC + | |
11871 | MISC_REGISTERS_RESET_REG_2_SET, | |
11872 | (MISC_REGISTERS_RESET_REG_2_MSTAT0 << | |
11873 | params->port)); | |
11874 | } | |
11875 | if (vars->line_speed < ELINK_SPEED_10000) | |
11876 | elink_umac_enable(params, vars, 0); | |
11877 | else | |
11878 | elink_xmac_enable(params, vars, 0); | |
11879 | } else { | |
11880 | if (vars->line_speed < ELINK_SPEED_10000) | |
11881 | elink_emac_enable(params, vars, 0); | |
11882 | else | |
11883 | elink_bmac_enable(params, vars, 0, !dont_clear_stat); | |
11884 | } | |
11885 | ||
11886 | /* Increment LFA count */ | |
11887 | lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) | | |
11888 | (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >> | |
11889 | LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff) | |
11890 | << LINK_FLAP_AVOIDANCE_COUNT_OFFSET)); | |
11891 | /* Clear link flap reason */ | |
11892 | lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; | |
11893 | ||
11894 | REG_WR(sc, params->lfa_base + | |
11895 | offsetof(struct shmem_lfa, lfa_sts), lfa_sts); | |
11896 | ||
11897 | /* Disable NIG DRAIN */ | |
11898 | REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); | |
11899 | ||
11900 | /* Enable interrupts */ | |
11901 | elink_link_int_enable(params); | |
11902 | return ELINK_STATUS_OK; | |
11903 | } | |
11904 | ||
11905 | static void elink_cannot_avoid_link_flap(struct elink_params *params, | |
11906 | struct elink_vars *vars, | |
11907 | int lfa_status) | |
11908 | { | |
11909 | uint32_t lfa_sts, cfg_idx, tmp_val; | |
11910 | struct bnx2x_softc *sc = params->sc; | |
11911 | ||
11912 | elink_link_reset(params, vars, 1); | |
11913 | ||
11914 | if (!params->lfa_base) | |
11915 | return; | |
11916 | /* Store the new link parameters */ | |
11917 | REG_WR(sc, params->lfa_base + | |
11918 | offsetof(struct shmem_lfa, req_duplex), | |
11919 | params->req_duplex[0] | (params->req_duplex[1] << 16)); | |
11920 | ||
11921 | REG_WR(sc, params->lfa_base + | |
11922 | offsetof(struct shmem_lfa, req_flow_ctrl), | |
11923 | params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16)); | |
11924 | ||
11925 | REG_WR(sc, params->lfa_base + | |
11926 | offsetof(struct shmem_lfa, req_line_speed), | |
11927 | params->req_line_speed[0] | (params->req_line_speed[1] << 16)); | |
11928 | ||
11929 | for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) { | |
11930 | REG_WR(sc, params->lfa_base + | |
11931 | offsetof(struct shmem_lfa, | |
11932 | speed_cap_mask[cfg_idx]), | |
11933 | params->speed_cap_mask[cfg_idx]); | |
11934 | } | |
11935 | ||
11936 | tmp_val = REG_RD(sc, params->lfa_base + | |
11937 | offsetof(struct shmem_lfa, additional_config)); | |
11938 | tmp_val &= ~REQ_FC_AUTO_ADV_MASK; | |
11939 | tmp_val |= params->req_fc_auto_adv; | |
11940 | ||
11941 | REG_WR(sc, params->lfa_base + | |
11942 | offsetof(struct shmem_lfa, additional_config), tmp_val); | |
11943 | ||
11944 | lfa_sts = REG_RD(sc, params->lfa_base + | |
11945 | offsetof(struct shmem_lfa, lfa_sts)); | |
11946 | ||
11947 | /* Clear the "Don't Clear Statistics" bit, and set reason */ | |
11948 | lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT; | |
11949 | ||
11950 | /* Set link flap reason */ | |
11951 | lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; | |
11952 | lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) << | |
11953 | LFA_LINK_FLAP_REASON_OFFSET); | |
11954 | ||
11955 | /* Increment link flap counter */ | |
11956 | lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) | | |
11957 | (((((lfa_sts & LINK_FLAP_COUNT_MASK) >> | |
11958 | LINK_FLAP_COUNT_OFFSET) + 1) & 0xff) | |
11959 | << LINK_FLAP_COUNT_OFFSET)); | |
11960 | REG_WR(sc, params->lfa_base + | |
11961 | offsetof(struct shmem_lfa, lfa_sts), lfa_sts); | |
11962 | /* Proceed with regular link initialization */ | |
11963 | } | |
11964 | ||
11965 | elink_status_t elink_phy_init(struct elink_params *params, | |
11966 | struct elink_vars *vars) | |
11967 | { | |
11968 | int lfa_status; | |
11969 | struct bnx2x_softc *sc = params->sc; | |
11970 | PMD_DRV_LOG(DEBUG, "Phy Initialization started"); | |
11971 | PMD_DRV_LOG(DEBUG, "(1) req_speed %d, req_flowctrl %d", | |
11972 | params->req_line_speed[0], params->req_flow_ctrl[0]); | |
11973 | PMD_DRV_LOG(DEBUG, "(2) req_speed %d, req_flowctrl %d", | |
11974 | params->req_line_speed[1], params->req_flow_ctrl[1]); | |
11975 | PMD_DRV_LOG(DEBUG, "req_adv_flow_ctrl 0x%x", params->req_fc_auto_adv); | |
11976 | vars->link_status = 0; | |
11977 | vars->phy_link_up = 0; | |
11978 | vars->link_up = 0; | |
11979 | vars->line_speed = 0; | |
11980 | vars->duplex = DUPLEX_FULL; | |
11981 | vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; | |
11982 | vars->mac_type = ELINK_MAC_TYPE_NONE; | |
11983 | vars->phy_flags = 0; | |
11984 | vars->check_kr2_recovery_cnt = 0; | |
11985 | params->link_flags = ELINK_PHY_INITIALIZED; | |
11986 | /* Driver opens NIG-BRB filters */ | |
11987 | elink_set_rx_filter(params, 1); | |
11988 | /* Check if link flap can be avoided */ | |
11989 | lfa_status = elink_check_lfa(params); | |
11990 | ||
11991 | if (lfa_status == 0) { | |
11992 | PMD_DRV_LOG(DEBUG, "Link Flap Avoidance in progress"); | |
11993 | return elink_avoid_link_flap(params, vars); | |
11994 | } | |
11995 | ||
11996 | PMD_DRV_LOG(DEBUG, "Cannot avoid link flap lfa_sta=0x%x", lfa_status); | |
11997 | elink_cannot_avoid_link_flap(params, vars, lfa_status); | |
11998 | ||
11999 | /* Disable attentions */ | |
12000 | elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port * 4, | |
12001 | (ELINK_NIG_MASK_XGXS0_LINK_STATUS | | |
12002 | ELINK_NIG_MASK_XGXS0_LINK10G | | |
12003 | ELINK_NIG_MASK_SERDES0_LINK_STATUS | | |
12004 | ELINK_NIG_MASK_MI_INT)); | |
12005 | ||
12006 | elink_emac_init(params); | |
12007 | ||
12008 | if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) | |
12009 | vars->link_status |= LINK_STATUS_PFC_ENABLED; | |
12010 | ||
12011 | if ((params->num_phys == 0) && !CHIP_REV_IS_SLOW(sc)) { | |
12012 | PMD_DRV_LOG(DEBUG, "No phy found for initialization !!"); | |
12013 | return ELINK_STATUS_ERROR; | |
12014 | } | |
12015 | set_phy_vars(params, vars); | |
12016 | ||
12017 | PMD_DRV_LOG(DEBUG, "Num of phys on board: %d", params->num_phys); | |
12018 | ||
12019 | switch (params->loopback_mode) { | |
12020 | case ELINK_LOOPBACK_BMAC: | |
12021 | elink_init_bmac_loopback(params, vars); | |
12022 | break; | |
12023 | case ELINK_LOOPBACK_EMAC: | |
12024 | elink_init_emac_loopback(params, vars); | |
12025 | break; | |
12026 | case ELINK_LOOPBACK_XMAC: | |
12027 | elink_init_xmac_loopback(params, vars); | |
12028 | break; | |
12029 | case ELINK_LOOPBACK_UMAC: | |
12030 | elink_init_umac_loopback(params, vars); | |
12031 | break; | |
12032 | case ELINK_LOOPBACK_XGXS: | |
12033 | case ELINK_LOOPBACK_EXT_PHY: | |
12034 | elink_init_xgxs_loopback(params, vars); | |
12035 | break; | |
12036 | default: | |
12037 | if (!CHIP_IS_E3(sc)) { | |
12038 | if (params->switch_cfg == ELINK_SWITCH_CFG_10G) | |
12039 | elink_xgxs_deassert(params); | |
12040 | else | |
12041 | elink_serdes_deassert(sc, params->port); | |
12042 | } | |
12043 | elink_link_initialize(params, vars); | |
12044 | DELAY(1000 * 30); | |
12045 | elink_link_int_enable(params); | |
12046 | break; | |
12047 | } | |
12048 | elink_update_mng(params, vars->link_status); | |
12049 | ||
12050 | elink_update_mng_eee(params, vars->eee_status); | |
12051 | return ELINK_STATUS_OK; | |
12052 | } | |
12053 | ||
12054 | static elink_status_t elink_link_reset(struct elink_params *params, | |
12055 | struct elink_vars *vars, | |
12056 | uint8_t reset_ext_phy) | |
12057 | { | |
12058 | struct bnx2x_softc *sc = params->sc; | |
12059 | uint8_t phy_index, port = params->port, clear_latch_ind = 0; | |
12060 | PMD_DRV_LOG(DEBUG, "Resetting the link of port %d", port); | |
12061 | /* Disable attentions */ | |
12062 | vars->link_status = 0; | |
12063 | elink_update_mng(params, vars->link_status); | |
12064 | vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | | |
12065 | SHMEM_EEE_ACTIVE_BIT); | |
12066 | elink_update_mng_eee(params, vars->eee_status); | |
12067 | elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, | |
12068 | (ELINK_NIG_MASK_XGXS0_LINK_STATUS | | |
12069 | ELINK_NIG_MASK_XGXS0_LINK10G | | |
12070 | ELINK_NIG_MASK_SERDES0_LINK_STATUS | | |
12071 | ELINK_NIG_MASK_MI_INT)); | |
12072 | ||
12073 | /* Activate nig drain */ | |
12074 | REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 1); | |
12075 | ||
12076 | /* Disable nig egress interface */ | |
12077 | if (!CHIP_IS_E3(sc)) { | |
12078 | REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0); | |
12079 | REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0); | |
12080 | } | |
12081 | if (!CHIP_IS_E3(sc)) | |
12082 | elink_set_bmac_rx(sc, port, 0); | |
12083 | if (CHIP_IS_E3(sc) && !CHIP_REV_IS_FPGA(sc)) { | |
12084 | elink_set_xmac_rxtx(params, 0); | |
12085 | elink_set_umac_rxtx(params, 0); | |
12086 | } | |
12087 | /* Disable emac */ | |
12088 | if (!CHIP_IS_E3(sc)) | |
12089 | REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0); | |
12090 | ||
12091 | DELAY(1000 * 10); | |
12092 | /* The PHY reset is controlled by GPIO 1 | |
12093 | * Hold it as vars low | |
12094 | */ | |
12095 | /* Clear link led */ | |
12096 | elink_set_mdio_emac_per_phy(sc, params); | |
12097 | elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0); | |
12098 | ||
12099 | if (reset_ext_phy && (!CHIP_REV_IS_SLOW(sc))) { | |
12100 | for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; | |
12101 | phy_index++) { | |
12102 | if (params->phy[phy_index].link_reset) { | |
12103 | elink_set_aer_mmd(params, | |
12104 | ¶ms->phy[phy_index]); | |
12105 | params->phy[phy_index].link_reset(¶ms-> | |
12106 | phy | |
12107 | [phy_index], | |
12108 | params); | |
12109 | } | |
12110 | if (params->phy[phy_index].flags & | |
12111 | ELINK_FLAGS_REARM_LATCH_SIGNAL) | |
12112 | clear_latch_ind = 1; | |
12113 | } | |
12114 | } | |
12115 | ||
12116 | if (clear_latch_ind) { | |
12117 | /* Clear latching indication */ | |
12118 | elink_rearm_latch_signal(sc, port, 0); | |
12119 | elink_bits_dis(sc, NIG_REG_LATCH_BC_0 + port * 4, | |
12120 | 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT); | |
12121 | } | |
12122 | if (params->phy[ELINK_INT_PHY].link_reset) | |
12123 | params->phy[ELINK_INT_PHY].link_reset(¶ms-> | |
12124 | phy | |
12125 | [ELINK_INT_PHY], | |
12126 | params); | |
12127 | ||
12128 | /* Disable nig ingress interface */ | |
12129 | if (!CHIP_IS_E3(sc)) { | |
12130 | /* Reset BigMac */ | |
12131 | REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
12132 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
12133 | REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0); | |
12134 | REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0); | |
12135 | } else { | |
12136 | uint32_t xmac_base = | |
12137 | (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
12138 | elink_set_xumac_nig(params, 0, 0); | |
12139 | if (REG_RD(sc, MISC_REG_RESET_REG_2) & | |
12140 | MISC_REGISTERS_RESET_REG_2_XMAC) | |
12141 | REG_WR(sc, xmac_base + XMAC_REG_CTRL, | |
12142 | XMAC_CTRL_REG_SOFT_RESET); | |
12143 | } | |
12144 | vars->link_up = 0; | |
12145 | vars->phy_flags = 0; | |
12146 | return ELINK_STATUS_OK; | |
12147 | } | |
12148 | ||
12149 | elink_status_t elink_lfa_reset(struct elink_params * params, | |
12150 | struct elink_vars * vars) | |
12151 | { | |
12152 | struct bnx2x_softc *sc = params->sc; | |
12153 | vars->link_up = 0; | |
12154 | vars->phy_flags = 0; | |
12155 | params->link_flags &= ~ELINK_PHY_INITIALIZED; | |
12156 | if (!params->lfa_base) | |
12157 | return elink_link_reset(params, vars, 1); | |
12158 | /* | |
12159 | * Activate NIG drain so that during this time the device won't send | |
12160 | * anything while it is unable to response. | |
12161 | */ | |
12162 | REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 1); | |
12163 | ||
12164 | /* | |
12165 | * Close gracefully the gate from BMAC to NIG such that no half packets | |
12166 | * are passed. | |
12167 | */ | |
12168 | if (!CHIP_IS_E3(sc)) | |
12169 | elink_set_bmac_rx(sc, params->port, 0); | |
12170 | ||
12171 | if (CHIP_IS_E3(sc)) { | |
12172 | elink_set_xmac_rxtx(params, 0); | |
12173 | elink_set_umac_rxtx(params, 0); | |
12174 | } | |
12175 | /* Wait 10ms for the pipe to clean up */ | |
12176 | DELAY(1000 * 10); | |
12177 | ||
12178 | /* Clean the NIG-BRB using the network filters in a way that will | |
12179 | * not cut a packet in the middle. | |
12180 | */ | |
12181 | elink_set_rx_filter(params, 0); | |
12182 | ||
12183 | /* | |
12184 | * Re-open the gate between the BMAC and the NIG, after verifying the | |
12185 | * gate to the BRB is closed, otherwise packets may arrive to the | |
12186 | * firmware before driver had initialized it. The target is to achieve | |
12187 | * minimum management protocol down time. | |
12188 | */ | |
12189 | if (!CHIP_IS_E3(sc)) | |
12190 | elink_set_bmac_rx(sc, params->port, 1); | |
12191 | ||
12192 | if (CHIP_IS_E3(sc)) { | |
12193 | elink_set_xmac_rxtx(params, 1); | |
12194 | elink_set_umac_rxtx(params, 1); | |
12195 | } | |
12196 | /* Disable NIG drain */ | |
12197 | REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); | |
12198 | return ELINK_STATUS_OK; | |
12199 | } | |
12200 | ||
12201 | /****************************************************************************/ | |
12202 | /* Common function */ | |
12203 | /****************************************************************************/ | |
12204 | static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc, | |
12205 | uint32_t shmem_base_path[], | |
12206 | uint32_t shmem2_base_path[], | |
12207 | uint8_t phy_index, | |
12208 | __rte_unused uint32_t chip_id) | |
12209 | { | |
12210 | struct elink_phy phy[PORT_MAX]; | |
12211 | struct elink_phy *phy_blk[PORT_MAX]; | |
12212 | uint16_t val; | |
12213 | int8_t port = 0; | |
12214 | int8_t port_of_path = 0; | |
12215 | uint32_t swap_val, swap_override; | |
12216 | swap_val = REG_RD(sc, NIG_REG_PORT_SWAP); | |
12217 | swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE); | |
12218 | port ^= (swap_val && swap_override); | |
12219 | elink_ext_phy_hw_reset(sc, port); | |
12220 | /* PART1 - Reset both phys */ | |
12221 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
12222 | uint32_t shmem_base, shmem2_base; | |
12223 | /* In E2, same phy is using for port0 of the two paths */ | |
12224 | if (CHIP_IS_E1x(sc)) { | |
12225 | shmem_base = shmem_base_path[0]; | |
12226 | shmem2_base = shmem2_base_path[0]; | |
12227 | port_of_path = port; | |
12228 | } else { | |
12229 | shmem_base = shmem_base_path[port]; | |
12230 | shmem2_base = shmem2_base_path[port]; | |
12231 | port_of_path = 0; | |
12232 | } | |
12233 | ||
12234 | /* Extract the ext phy address for the port */ | |
12235 | if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base, | |
12236 | port_of_path, &phy[port]) != | |
12237 | ELINK_STATUS_OK) { | |
12238 | PMD_DRV_LOG(DEBUG, "populate_phy failed"); | |
12239 | return ELINK_STATUS_ERROR; | |
12240 | } | |
12241 | /* Disable attentions */ | |
12242 | elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + | |
12243 | port_of_path * 4, | |
12244 | (ELINK_NIG_MASK_XGXS0_LINK_STATUS | | |
12245 | ELINK_NIG_MASK_XGXS0_LINK10G | | |
12246 | ELINK_NIG_MASK_SERDES0_LINK_STATUS | | |
12247 | ELINK_NIG_MASK_MI_INT)); | |
12248 | ||
12249 | /* Need to take the phy out of low power mode in order | |
12250 | * to write to access its registers | |
12251 | */ | |
12252 | elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, | |
12253 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); | |
12254 | ||
12255 | /* Reset the phy */ | |
12256 | elink_cl45_write(sc, &phy[port], | |
12257 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15); | |
12258 | } | |
12259 | ||
12260 | /* Add delay of 150ms after reset */ | |
12261 | DELAY(1000 * 150); | |
12262 | ||
12263 | if (phy[PORT_0].addr & 0x1) { | |
12264 | phy_blk[PORT_0] = &(phy[PORT_1]); | |
12265 | phy_blk[PORT_1] = &(phy[PORT_0]); | |
12266 | } else { | |
12267 | phy_blk[PORT_0] = &(phy[PORT_0]); | |
12268 | phy_blk[PORT_1] = &(phy[PORT_1]); | |
12269 | } | |
12270 | ||
12271 | /* PART2 - Download firmware to both phys */ | |
12272 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
12273 | if (CHIP_IS_E1x(sc)) | |
12274 | port_of_path = port; | |
12275 | else | |
12276 | port_of_path = 0; | |
12277 | ||
12278 | PMD_DRV_LOG(DEBUG, "Loading spirom for phy address 0x%x", | |
12279 | phy_blk[port]->addr); | |
12280 | if (elink_8073_8727_external_rom_boot(sc, phy_blk[port], | |
12281 | port_of_path)) | |
12282 | return ELINK_STATUS_ERROR; | |
12283 | ||
12284 | /* Only set bit 10 = 1 (Tx power down) */ | |
12285 | elink_cl45_read(sc, phy_blk[port], | |
12286 | MDIO_PMA_DEVAD, | |
12287 | MDIO_PMA_REG_TX_POWER_DOWN, &val); | |
12288 | ||
12289 | /* Phase1 of TX_POWER_DOWN reset */ | |
12290 | elink_cl45_write(sc, phy_blk[port], | |
12291 | MDIO_PMA_DEVAD, | |
12292 | MDIO_PMA_REG_TX_POWER_DOWN, (val | 1 << 10)); | |
12293 | } | |
12294 | ||
12295 | /* Toggle Transmitter: Power down and then up with 600ms delay | |
12296 | * between | |
12297 | */ | |
12298 | DELAY(1000 * 600); | |
12299 | ||
12300 | /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ | |
12301 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
12302 | /* Phase2 of POWER_DOWN_RESET */ | |
12303 | /* Release bit 10 (Release Tx power down) */ | |
12304 | elink_cl45_read(sc, phy_blk[port], | |
12305 | MDIO_PMA_DEVAD, | |
12306 | MDIO_PMA_REG_TX_POWER_DOWN, &val); | |
12307 | ||
12308 | elink_cl45_write(sc, phy_blk[port], | |
12309 | MDIO_PMA_DEVAD, | |
12310 | MDIO_PMA_REG_TX_POWER_DOWN, | |
12311 | (val & (~(1 << 10)))); | |
12312 | DELAY(1000 * 15); | |
12313 | ||
12314 | /* Read modify write the SPI-ROM version select register */ | |
12315 | elink_cl45_read(sc, phy_blk[port], | |
12316 | MDIO_PMA_DEVAD, | |
12317 | MDIO_PMA_REG_EDC_FFE_MAIN, &val); | |
12318 | elink_cl45_write(sc, phy_blk[port], | |
12319 | MDIO_PMA_DEVAD, | |
12320 | MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1 << 12))); | |
12321 | ||
12322 | /* set GPIO2 back to LOW */ | |
12323 | elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, | |
12324 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); | |
12325 | } | |
12326 | return ELINK_STATUS_OK; | |
12327 | } | |
12328 | ||
12329 | static elink_status_t elink_8726_common_init_phy(struct bnx2x_softc *sc, | |
12330 | uint32_t shmem_base_path[], | |
12331 | uint32_t shmem2_base_path[], | |
12332 | uint8_t phy_index, | |
12333 | __rte_unused uint32_t chip_id) | |
12334 | { | |
12335 | uint32_t val; | |
12336 | int8_t port; | |
12337 | struct elink_phy phy; | |
12338 | /* Use port1 because of the static port-swap */ | |
12339 | /* Enable the module detection interrupt */ | |
12340 | val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN); | |
12341 | val |= ((1 << MISC_REGISTERS_GPIO_3) | | |
12342 | (1 << | |
12343 | (MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT))); | |
12344 | REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val); | |
12345 | ||
12346 | elink_ext_phy_hw_reset(sc, 0); | |
12347 | DELAY(1000 * 5); | |
12348 | for (port = 0; port < PORT_MAX; port++) { | |
12349 | uint32_t shmem_base, shmem2_base; | |
12350 | ||
12351 | /* In E2, same phy is using for port0 of the two paths */ | |
12352 | if (CHIP_IS_E1x(sc)) { | |
12353 | shmem_base = shmem_base_path[0]; | |
12354 | shmem2_base = shmem2_base_path[0]; | |
12355 | } else { | |
12356 | shmem_base = shmem_base_path[port]; | |
12357 | shmem2_base = shmem2_base_path[port]; | |
12358 | } | |
12359 | /* Extract the ext phy address for the port */ | |
12360 | if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base, | |
12361 | port, &phy) != ELINK_STATUS_OK) { | |
12362 | PMD_DRV_LOG(DEBUG, "populate phy failed"); | |
12363 | return ELINK_STATUS_ERROR; | |
12364 | } | |
12365 | ||
12366 | /* Reset phy */ | |
12367 | elink_cl45_write(sc, &phy, | |
12368 | MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); | |
12369 | ||
12370 | /* Set fault module detected LED on */ | |
12371 | elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_0, | |
12372 | MISC_REGISTERS_GPIO_HIGH, port); | |
12373 | } | |
12374 | ||
12375 | return ELINK_STATUS_OK; | |
12376 | } | |
12377 | ||
12378 | static void elink_get_ext_phy_reset_gpio(struct bnx2x_softc *sc, | |
12379 | uint32_t shmem_base, uint8_t * io_gpio, | |
12380 | uint8_t * io_port) | |
12381 | { | |
12382 | ||
12383 | uint32_t phy_gpio_reset = REG_RD(sc, shmem_base + | |
12384 | offsetof(struct shmem_region, | |
12385 | dev_info. | |
12386 | port_hw_config[PORT_0]. | |
12387 | default_cfg)); | |
12388 | switch (phy_gpio_reset) { | |
12389 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0: | |
12390 | *io_gpio = 0; | |
12391 | *io_port = 0; | |
12392 | break; | |
12393 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0: | |
12394 | *io_gpio = 1; | |
12395 | *io_port = 0; | |
12396 | break; | |
12397 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0: | |
12398 | *io_gpio = 2; | |
12399 | *io_port = 0; | |
12400 | break; | |
12401 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0: | |
12402 | *io_gpio = 3; | |
12403 | *io_port = 0; | |
12404 | break; | |
12405 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1: | |
12406 | *io_gpio = 0; | |
12407 | *io_port = 1; | |
12408 | break; | |
12409 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1: | |
12410 | *io_gpio = 1; | |
12411 | *io_port = 1; | |
12412 | break; | |
12413 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1: | |
12414 | *io_gpio = 2; | |
12415 | *io_port = 1; | |
12416 | break; | |
12417 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1: | |
12418 | *io_gpio = 3; | |
12419 | *io_port = 1; | |
12420 | break; | |
12421 | default: | |
12422 | /* Don't override the io_gpio and io_port */ | |
12423 | break; | |
12424 | } | |
12425 | } | |
12426 | ||
12427 | static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc, | |
12428 | uint32_t shmem_base_path[], | |
12429 | uint32_t shmem2_base_path[], | |
12430 | uint8_t phy_index, | |
12431 | __rte_unused uint32_t chip_id) | |
12432 | { | |
12433 | int8_t port, reset_gpio; | |
12434 | uint32_t swap_val, swap_override; | |
12435 | struct elink_phy phy[PORT_MAX]; | |
12436 | struct elink_phy *phy_blk[PORT_MAX]; | |
12437 | int8_t port_of_path; | |
12438 | swap_val = REG_RD(sc, NIG_REG_PORT_SWAP); | |
12439 | swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE); | |
12440 | ||
12441 | reset_gpio = MISC_REGISTERS_GPIO_1; | |
12442 | port = 1; | |
12443 | ||
12444 | /* Retrieve the reset gpio/port which control the reset. | |
12445 | * Default is GPIO1, PORT1 | |
12446 | */ | |
12447 | elink_get_ext_phy_reset_gpio(sc, shmem_base_path[0], | |
12448 | (uint8_t *) & reset_gpio, | |
12449 | (uint8_t *) & port); | |
12450 | ||
12451 | /* Calculate the port based on port swap */ | |
12452 | port ^= (swap_val && swap_override); | |
12453 | ||
12454 | /* Initiate PHY reset */ | |
12455 | elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, | |
12456 | port); | |
12457 | DELAY(1000 * 1); | |
12458 | elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, | |
12459 | port); | |
12460 | ||
12461 | DELAY(1000 * 5); | |
12462 | ||
12463 | /* PART1 - Reset both phys */ | |
12464 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
12465 | uint32_t shmem_base, shmem2_base; | |
12466 | ||
12467 | /* In E2, same phy is using for port0 of the two paths */ | |
12468 | if (CHIP_IS_E1x(sc)) { | |
12469 | shmem_base = shmem_base_path[0]; | |
12470 | shmem2_base = shmem2_base_path[0]; | |
12471 | port_of_path = port; | |
12472 | } else { | |
12473 | shmem_base = shmem_base_path[port]; | |
12474 | shmem2_base = shmem2_base_path[port]; | |
12475 | port_of_path = 0; | |
12476 | } | |
12477 | ||
12478 | /* Extract the ext phy address for the port */ | |
12479 | if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base, | |
12480 | port_of_path, &phy[port]) != | |
12481 | ELINK_STATUS_OK) { | |
12482 | PMD_DRV_LOG(DEBUG, "populate phy failed"); | |
12483 | return ELINK_STATUS_ERROR; | |
12484 | } | |
12485 | /* disable attentions */ | |
12486 | elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + | |
12487 | port_of_path * 4, | |
12488 | (ELINK_NIG_MASK_XGXS0_LINK_STATUS | | |
12489 | ELINK_NIG_MASK_XGXS0_LINK10G | | |
12490 | ELINK_NIG_MASK_SERDES0_LINK_STATUS | | |
12491 | ELINK_NIG_MASK_MI_INT)); | |
12492 | ||
12493 | /* Reset the phy */ | |
12494 | elink_cl45_write(sc, &phy[port], | |
12495 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15); | |
12496 | } | |
12497 | ||
12498 | /* Add delay of 150ms after reset */ | |
12499 | DELAY(1000 * 150); | |
12500 | if (phy[PORT_0].addr & 0x1) { | |
12501 | phy_blk[PORT_0] = &(phy[PORT_1]); | |
12502 | phy_blk[PORT_1] = &(phy[PORT_0]); | |
12503 | } else { | |
12504 | phy_blk[PORT_0] = &(phy[PORT_0]); | |
12505 | phy_blk[PORT_1] = &(phy[PORT_1]); | |
12506 | } | |
12507 | /* PART2 - Download firmware to both phys */ | |
12508 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
12509 | if (CHIP_IS_E1x(sc)) | |
12510 | port_of_path = port; | |
12511 | else | |
12512 | port_of_path = 0; | |
12513 | PMD_DRV_LOG(DEBUG, "Loading spirom for phy address 0x%x", | |
12514 | phy_blk[port]->addr); | |
12515 | if (elink_8073_8727_external_rom_boot(sc, phy_blk[port], | |
12516 | port_of_path)) | |
12517 | return ELINK_STATUS_ERROR; | |
12518 | /* Disable PHY transmitter output */ | |
12519 | elink_cl45_write(sc, phy_blk[port], | |
12520 | MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, 1); | |
12521 | ||
12522 | } | |
12523 | return ELINK_STATUS_OK; | |
12524 | } | |
12525 | ||
12526 | static elink_status_t elink_84833_common_init_phy(struct bnx2x_softc *sc, | |
12527 | uint32_t shmem_base_path[], | |
12528 | __rte_unused uint32_t | |
12529 | shmem2_base_path[], | |
12530 | __rte_unused uint8_t | |
12531 | phy_index, uint32_t chip_id) | |
12532 | { | |
12533 | uint8_t reset_gpios; | |
12534 | reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path, chip_id); | |
12535 | elink_cb_gpio_mult_write(sc, reset_gpios, | |
12536 | MISC_REGISTERS_GPIO_OUTPUT_LOW); | |
12537 | DELAY(10); | |
12538 | elink_cb_gpio_mult_write(sc, reset_gpios, | |
12539 | MISC_REGISTERS_GPIO_OUTPUT_HIGH); | |
12540 | PMD_DRV_LOG(DEBUG, "84833 reset pulse on pin values 0x%x", reset_gpios); | |
12541 | return ELINK_STATUS_OK; | |
12542 | } | |
12543 | ||
12544 | static elink_status_t elink_ext_phy_common_init(struct bnx2x_softc *sc, | |
12545 | uint32_t shmem_base_path[], | |
12546 | uint32_t shmem2_base_path[], | |
12547 | uint8_t phy_index, | |
12548 | uint32_t ext_phy_type, | |
12549 | uint32_t chip_id) | |
12550 | { | |
12551 | elink_status_t rc = ELINK_STATUS_OK; | |
12552 | ||
12553 | switch (ext_phy_type) { | |
12554 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073: | |
12555 | rc = elink_8073_common_init_phy(sc, shmem_base_path, | |
12556 | shmem2_base_path, | |
12557 | phy_index, chip_id); | |
12558 | break; | |
12559 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722: | |
12560 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727: | |
12561 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC: | |
12562 | rc = elink_8727_common_init_phy(sc, shmem_base_path, | |
12563 | shmem2_base_path, | |
12564 | phy_index, chip_id); | |
12565 | break; | |
12566 | ||
12567 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726: | |
12568 | /* GPIO1 affects both ports, so there's need to pull | |
12569 | * it for single port alone | |
12570 | */ | |
12571 | rc = elink_8726_common_init_phy(sc, shmem_base_path, | |
12572 | shmem2_base_path, | |
12573 | phy_index, chip_id); | |
12574 | break; | |
12575 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833: | |
12576 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834: | |
12577 | /* GPIO3's are linked, and so both need to be toggled | |
12578 | * to obtain required 2us pulse. | |
12579 | */ | |
12580 | rc = elink_84833_common_init_phy(sc, shmem_base_path, | |
12581 | shmem2_base_path, | |
12582 | phy_index, chip_id); | |
12583 | break; | |
12584 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: | |
12585 | rc = ELINK_STATUS_ERROR; | |
12586 | break; | |
12587 | default: | |
12588 | PMD_DRV_LOG(DEBUG, | |
12589 | "ext_phy 0x%x common init not required", | |
12590 | ext_phy_type); | |
12591 | break; | |
12592 | } | |
12593 | ||
12594 | if (rc != ELINK_STATUS_OK) | |
12595 | elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, 0); // "Warning: PHY was not initialized," | |
12596 | // " Port %d", | |
12597 | ||
12598 | return rc; | |
12599 | } | |
12600 | ||
12601 | elink_status_t elink_common_init_phy(struct bnx2x_softc * sc, | |
12602 | uint32_t shmem_base_path[], | |
12603 | uint32_t shmem2_base_path[], | |
12604 | uint32_t chip_id, | |
12605 | __rte_unused uint8_t one_port_enabled) | |
12606 | { | |
12607 | elink_status_t rc = ELINK_STATUS_OK; | |
12608 | uint32_t phy_ver, val; | |
12609 | uint8_t phy_index = 0; | |
12610 | uint32_t ext_phy_type, ext_phy_config; | |
12611 | ||
12612 | elink_set_mdio_clk(sc, GRCBASE_EMAC0); | |
12613 | elink_set_mdio_clk(sc, GRCBASE_EMAC1); | |
12614 | PMD_DRV_LOG(DEBUG, "Begin common phy init"); | |
12615 | if (CHIP_IS_E3(sc)) { | |
12616 | /* Enable EPIO */ | |
12617 | val = REG_RD(sc, MISC_REG_GEN_PURP_HWG); | |
12618 | REG_WR(sc, MISC_REG_GEN_PURP_HWG, val | 1); | |
12619 | } | |
12620 | /* Check if common init was already done */ | |
12621 | phy_ver = REG_RD(sc, shmem_base_path[0] + | |
12622 | offsetof(struct shmem_region, | |
12623 | port_mb[PORT_0].ext_phy_fw_version)); | |
12624 | if (phy_ver) { | |
12625 | PMD_DRV_LOG(DEBUG, "Not doing common init; phy ver is 0x%x", | |
12626 | phy_ver); | |
12627 | return ELINK_STATUS_OK; | |
12628 | } | |
12629 | ||
12630 | /* Read the ext_phy_type for arbitrary port(0) */ | |
12631 | for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; | |
12632 | phy_index++) { | |
12633 | ext_phy_config = elink_get_ext_phy_config(sc, | |
12634 | shmem_base_path[0], | |
12635 | phy_index, 0); | |
12636 | ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config); | |
12637 | rc |= elink_ext_phy_common_init(sc, shmem_base_path, | |
12638 | shmem2_base_path, | |
12639 | phy_index, ext_phy_type, | |
12640 | chip_id); | |
12641 | } | |
12642 | return rc; | |
12643 | } | |
12644 | ||
12645 | static void elink_check_over_curr(struct elink_params *params, | |
12646 | struct elink_vars *vars) | |
12647 | { | |
12648 | struct bnx2x_softc *sc = params->sc; | |
12649 | uint32_t cfg_pin; | |
12650 | uint8_t port = params->port; | |
12651 | uint32_t pin_val; | |
12652 | ||
12653 | cfg_pin = (REG_RD(sc, params->shmem_base + | |
12654 | offsetof(struct shmem_region, | |
12655 | dev_info.port_hw_config[port]. | |
12656 | e3_cmn_pin_cfg1)) & | |
12657 | PORT_HW_CFG_E3_OVER_CURRENT_MASK) >> | |
12658 | PORT_HW_CFG_E3_OVER_CURRENT_SHIFT; | |
12659 | ||
12660 | /* Ignore check if no external input PIN available */ | |
12661 | if (elink_get_cfg_pin(sc, cfg_pin, &pin_val) != ELINK_STATUS_OK) | |
12662 | return; | |
12663 | ||
12664 | if (!pin_val) { | |
12665 | if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { | |
12666 | elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, params->port); //"Error: Power fault on Port %d has" | |
12667 | // " been detected and the power to " | |
12668 | // "that SFP+ module has been removed" | |
12669 | // " to prevent failure of the card." | |
12670 | // " Please remove the SFP+ module and" | |
12671 | // " restart the system to clear this" | |
12672 | // " error.", | |
12673 | vars->phy_flags |= PHY_OVER_CURRENT_FLAG; | |
12674 | elink_warpcore_power_module(params, 0); | |
12675 | } | |
12676 | } else | |
12677 | vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG; | |
12678 | } | |
12679 | ||
12680 | /* Returns 0 if no change occured since last check; 1 otherwise. */ | |
12681 | static uint8_t elink_analyze_link_error(struct elink_params *params, | |
12682 | struct elink_vars *vars, | |
12683 | uint32_t status, uint32_t phy_flag, | |
12684 | uint32_t link_flag, uint8_t notify) | |
12685 | { | |
12686 | struct bnx2x_softc *sc = params->sc; | |
12687 | /* Compare new value with previous value */ | |
12688 | uint8_t led_mode; | |
12689 | uint32_t old_status = (vars->phy_flags & phy_flag) ? 1 : 0; | |
12690 | ||
12691 | if ((status ^ old_status) == 0) | |
12692 | return 0; | |
12693 | ||
12694 | /* If values differ */ | |
12695 | switch (phy_flag) { | |
12696 | case PHY_HALF_OPEN_CONN_FLAG: | |
12697 | PMD_DRV_LOG(DEBUG, "Analyze Remote Fault"); | |
12698 | break; | |
12699 | case PHY_SFP_TX_FAULT_FLAG: | |
12700 | PMD_DRV_LOG(DEBUG, "Analyze TX Fault"); | |
12701 | break; | |
12702 | default: | |
12703 | PMD_DRV_LOG(DEBUG, "Analyze UNKNOWN"); | |
12704 | } | |
12705 | PMD_DRV_LOG(DEBUG, "Link changed:[%x %x]->%x", vars->link_up, | |
12706 | old_status, status); | |
12707 | ||
12708 | /* a. Update shmem->link_status accordingly | |
12709 | * b. Update elink_vars->link_up | |
12710 | */ | |
12711 | if (status) { | |
12712 | vars->link_status &= ~LINK_STATUS_LINK_UP; | |
12713 | vars->link_status |= link_flag; | |
12714 | vars->link_up = 0; | |
12715 | vars->phy_flags |= phy_flag; | |
12716 | ||
12717 | /* activate nig drain */ | |
12718 | REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 1); | |
12719 | /* Set LED mode to off since the PHY doesn't know about these | |
12720 | * errors | |
12721 | */ | |
12722 | led_mode = ELINK_LED_MODE_OFF; | |
12723 | } else { | |
12724 | vars->link_status |= LINK_STATUS_LINK_UP; | |
12725 | vars->link_status &= ~link_flag; | |
12726 | vars->link_up = 1; | |
12727 | vars->phy_flags &= ~phy_flag; | |
12728 | led_mode = ELINK_LED_MODE_OPER; | |
12729 | ||
12730 | /* Clear nig drain */ | |
12731 | REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); | |
12732 | } | |
12733 | elink_sync_link(params, vars); | |
12734 | /* Update the LED according to the link state */ | |
12735 | elink_set_led(params, vars, led_mode, ELINK_SPEED_10000); | |
12736 | ||
12737 | /* Update link status in the shared memory */ | |
12738 | elink_update_mng(params, vars->link_status); | |
12739 | ||
12740 | /* C. Trigger General Attention */ | |
12741 | vars->periodic_flags |= ELINK_PERIODIC_FLAGS_LINK_EVENT; | |
12742 | if (notify) | |
12743 | elink_cb_notify_link_changed(sc); | |
12744 | ||
12745 | return 1; | |
12746 | } | |
12747 | ||
12748 | /****************************************************************************** | |
12749 | * Description: | |
12750 | * This function checks for half opened connection change indication. | |
12751 | * When such change occurs, it calls the elink_analyze_link_error | |
12752 | * to check if Remote Fault is set or cleared. Reception of remote fault | |
12753 | * status message in the MAC indicates that the peer's MAC has detected | |
12754 | * a fault, for example, due to break in the TX side of fiber. | |
12755 | * | |
12756 | ******************************************************************************/ | |
12757 | static elink_status_t elink_check_half_open_conn(struct elink_params *params, | |
12758 | struct elink_vars *vars, | |
12759 | uint8_t notify) | |
12760 | { | |
12761 | struct bnx2x_softc *sc = params->sc; | |
12762 | uint32_t lss_status = 0; | |
12763 | uint32_t mac_base; | |
12764 | /* In case link status is physically up @ 10G do */ | |
12765 | if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) || | |
12766 | (REG_RD(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4))) | |
12767 | return ELINK_STATUS_OK; | |
12768 | ||
12769 | if (CHIP_IS_E3(sc) && | |
12770 | (REG_RD(sc, MISC_REG_RESET_REG_2) & | |
12771 | (MISC_REGISTERS_RESET_REG_2_XMAC))) { | |
12772 | /* Check E3 XMAC */ | |
12773 | /* Note that link speed cannot be queried here, since it may be | |
12774 | * zero while link is down. In case UMAC is active, LSS will | |
12775 | * simply not be set | |
12776 | */ | |
12777 | mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
12778 | ||
12779 | /* Clear stick bits (Requires rising edge) */ | |
12780 | REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); | |
12781 | REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, | |
12782 | XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | | |
12783 | XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); | |
12784 | if (REG_RD(sc, mac_base + XMAC_REG_RX_LSS_STATUS)) | |
12785 | lss_status = 1; | |
12786 | ||
12787 | elink_analyze_link_error(params, vars, lss_status, | |
12788 | PHY_HALF_OPEN_CONN_FLAG, | |
12789 | LINK_STATUS_NONE, notify); | |
12790 | } else if (REG_RD(sc, MISC_REG_RESET_REG_2) & | |
12791 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) { | |
12792 | /* Check E1X / E2 BMAC */ | |
12793 | uint32_t lss_status_reg; | |
12794 | uint32_t wb_data[2]; | |
12795 | mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : | |
12796 | NIG_REG_INGRESS_BMAC0_MEM; | |
12797 | /* Read BIGMAC_REGISTER_RX_LSS_STATUS */ | |
12798 | if (CHIP_IS_E2(sc)) | |
12799 | lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT; | |
12800 | else | |
12801 | lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS; | |
12802 | ||
12803 | REG_RD_DMAE(sc, mac_base + lss_status_reg, wb_data, 2); | |
12804 | lss_status = (wb_data[0] > 0); | |
12805 | ||
12806 | elink_analyze_link_error(params, vars, lss_status, | |
12807 | PHY_HALF_OPEN_CONN_FLAG, | |
12808 | LINK_STATUS_NONE, notify); | |
12809 | } | |
12810 | return ELINK_STATUS_OK; | |
12811 | } | |
12812 | ||
12813 | static void elink_sfp_tx_fault_detection(struct elink_phy *phy, | |
12814 | struct elink_params *params, | |
12815 | struct elink_vars *vars) | |
12816 | { | |
12817 | struct bnx2x_softc *sc = params->sc; | |
12818 | uint32_t cfg_pin, value = 0; | |
12819 | uint8_t led_change, port = params->port; | |
12820 | ||
12821 | /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */ | |
12822 | cfg_pin = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region, | |
12823 | dev_info. | |
12824 | port_hw_config | |
12825 | [port]. | |
12826 | e3_cmn_pin_cfg)) & | |
12827 | PORT_HW_CFG_E3_TX_FAULT_MASK) >> | |
12828 | PORT_HW_CFG_E3_TX_FAULT_SHIFT; | |
12829 | ||
12830 | if (elink_get_cfg_pin(sc, cfg_pin, &value)) { | |
12831 | PMD_DRV_LOG(DEBUG, "Failed to read pin 0x%02x", cfg_pin); | |
12832 | return; | |
12833 | } | |
12834 | ||
12835 | led_change = elink_analyze_link_error(params, vars, value, | |
12836 | PHY_SFP_TX_FAULT_FLAG, | |
12837 | LINK_STATUS_SFP_TX_FAULT, 1); | |
12838 | ||
12839 | if (led_change) { | |
12840 | /* Change TX_Fault led, set link status for further syncs */ | |
12841 | uint8_t led_mode; | |
12842 | ||
12843 | if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) { | |
12844 | led_mode = MISC_REGISTERS_GPIO_HIGH; | |
12845 | vars->link_status |= LINK_STATUS_SFP_TX_FAULT; | |
12846 | } else { | |
12847 | led_mode = MISC_REGISTERS_GPIO_LOW; | |
12848 | vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; | |
12849 | } | |
12850 | ||
12851 | /* If module is unapproved, led should be on regardless */ | |
12852 | if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) { | |
12853 | PMD_DRV_LOG(DEBUG, "Change TX_Fault LED: ->%x", | |
12854 | led_mode); | |
12855 | elink_set_e3_module_fault_led(params, led_mode); | |
12856 | } | |
12857 | } | |
12858 | } | |
12859 | ||
12860 | static void elink_kr2_recovery(struct elink_params *params, | |
12861 | struct elink_vars *vars, struct elink_phy *phy) | |
12862 | { | |
12863 | PMD_DRV_LOG(DEBUG, "KR2 recovery"); | |
12864 | ||
12865 | elink_warpcore_enable_AN_KR2(phy, params, vars); | |
12866 | elink_warpcore_restart_AN_KR(phy, params); | |
12867 | } | |
12868 | ||
12869 | static void elink_check_kr2_wa(struct elink_params *params, | |
12870 | struct elink_vars *vars, struct elink_phy *phy) | |
12871 | { | |
12872 | struct bnx2x_softc *sc = params->sc; | |
12873 | uint16_t base_page, next_page, not_kr2_device, lane; | |
12874 | int sigdet; | |
12875 | ||
12876 | /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery | |
12877 | * Since some switches tend to reinit the AN process and clear the | |
12878 | * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled | |
12879 | * and recovered many times | |
12880 | */ | |
12881 | if (vars->check_kr2_recovery_cnt > 0) { | |
12882 | vars->check_kr2_recovery_cnt--; | |
12883 | return; | |
12884 | } | |
12885 | ||
12886 | sigdet = elink_warpcore_get_sigdet(phy, params); | |
12887 | if (!sigdet) { | |
12888 | if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { | |
12889 | elink_kr2_recovery(params, vars, phy); | |
12890 | PMD_DRV_LOG(DEBUG, "No sigdet"); | |
12891 | } | |
12892 | return; | |
12893 | } | |
12894 | ||
12895 | lane = elink_get_warpcore_lane(params); | |
12896 | CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, | |
12897 | MDIO_AER_BLOCK_AER_REG, lane); | |
12898 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, | |
12899 | MDIO_AN_REG_LP_AUTO_NEG, &base_page); | |
12900 | elink_cl45_read(sc, phy, MDIO_AN_DEVAD, | |
12901 | MDIO_AN_REG_LP_AUTO_NEG2, &next_page); | |
12902 | elink_set_aer_mmd(params, phy); | |
12903 | ||
12904 | /* CL73 has not begun yet */ | |
12905 | if (base_page == 0) { | |
12906 | if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { | |
12907 | elink_kr2_recovery(params, vars, phy); | |
12908 | PMD_DRV_LOG(DEBUG, "No BP"); | |
12909 | } | |
12910 | return; | |
12911 | } | |
12912 | ||
12913 | /* In case NP bit is not set in the BasePage, or it is set, | |
12914 | * but only KX is advertised, declare this link partner as non-KR2 | |
12915 | * device. | |
12916 | */ | |
12917 | not_kr2_device = (((base_page & 0x8000) == 0) || | |
12918 | (((base_page & 0x8000) && | |
12919 | ((next_page & 0xe0) == 0x2)))); | |
12920 | ||
12921 | /* In case KR2 is already disabled, check if we need to re-enable it */ | |
12922 | if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { | |
12923 | if (!not_kr2_device) { | |
12924 | PMD_DRV_LOG(DEBUG, "BP=0x%x, NP=0x%x", base_page, | |
12925 | next_page); | |
12926 | elink_kr2_recovery(params, vars, phy); | |
12927 | } | |
12928 | return; | |
12929 | } | |
12930 | /* KR2 is enabled, but not KR2 device */ | |
12931 | if (not_kr2_device) { | |
12932 | /* Disable KR2 on both lanes */ | |
12933 | PMD_DRV_LOG(DEBUG, "BP=0x%x, NP=0x%x", base_page, next_page); | |
12934 | elink_disable_kr2(params, vars, phy); | |
12935 | /* Restart AN on leading lane */ | |
12936 | elink_warpcore_restart_AN_KR(phy, params); | |
12937 | return; | |
12938 | } | |
12939 | } | |
12940 | ||
12941 | void elink_period_func(struct elink_params *params, struct elink_vars *vars) | |
12942 | { | |
12943 | uint16_t phy_idx; | |
12944 | struct bnx2x_softc *sc = params->sc; | |
12945 | for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) { | |
12946 | if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) { | |
12947 | elink_set_aer_mmd(params, ¶ms->phy[phy_idx]); | |
12948 | if (elink_check_half_open_conn(params, vars, 1) != | |
12949 | ELINK_STATUS_OK) { | |
12950 | PMD_DRV_LOG(DEBUG, "Fault detection failed"); | |
12951 | } | |
12952 | break; | |
12953 | } | |
12954 | } | |
12955 | ||
12956 | if (CHIP_IS_E3(sc)) { | |
12957 | struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; | |
12958 | elink_set_aer_mmd(params, phy); | |
12959 | if ((phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) && | |
12960 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) | |
12961 | elink_check_kr2_wa(params, vars, phy); | |
12962 | elink_check_over_curr(params, vars); | |
12963 | if (vars->rx_tx_asic_rst) | |
12964 | elink_warpcore_config_runtime(phy, params, vars); | |
12965 | ||
12966 | if ((REG_RD(sc, params->shmem_base + | |
12967 | offsetof(struct shmem_region, | |
12968 | dev_info.port_hw_config[params->port]. | |
12969 | default_cfg)) | |
12970 | & PORT_HW_CFG_NET_SERDES_IF_MASK) == | |
12971 | PORT_HW_CFG_NET_SERDES_IF_SFI) { | |
12972 | if (elink_is_sfp_module_plugged(params)) { | |
12973 | elink_sfp_tx_fault_detection(phy, params, vars); | |
12974 | } else if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) { | |
12975 | /* Clean trail, interrupt corrects the leds */ | |
12976 | vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; | |
12977 | vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG; | |
12978 | /* Update link status in the shared memory */ | |
12979 | elink_update_mng(params, vars->link_status); | |
12980 | } | |
12981 | } | |
12982 | } | |
12983 | } | |
12984 | ||
12985 | uint8_t elink_fan_failure_det_req(struct bnx2x_softc *sc, | |
12986 | uint32_t shmem_base, | |
12987 | uint32_t shmem2_base, uint8_t port) | |
12988 | { | |
12989 | uint8_t phy_index, fan_failure_det_req = 0; | |
12990 | struct elink_phy phy; | |
12991 | for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; | |
12992 | phy_index++) { | |
12993 | if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base, | |
12994 | port, &phy) | |
12995 | != ELINK_STATUS_OK) { | |
12996 | PMD_DRV_LOG(DEBUG, "populate phy failed"); | |
12997 | return 0; | |
12998 | } | |
12999 | fan_failure_det_req |= (phy.flags & | |
13000 | ELINK_FLAGS_FAN_FAILURE_DET_REQ); | |
13001 | } | |
13002 | return fan_failure_det_req; | |
13003 | } | |
13004 | ||
13005 | void elink_hw_reset_phy(struct elink_params *params) | |
13006 | { | |
13007 | uint8_t phy_index; | |
13008 | struct bnx2x_softc *sc = params->sc; | |
13009 | elink_update_mng(params, 0); | |
13010 | elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port * 4, | |
13011 | (ELINK_NIG_MASK_XGXS0_LINK_STATUS | | |
13012 | ELINK_NIG_MASK_XGXS0_LINK10G | | |
13013 | ELINK_NIG_MASK_SERDES0_LINK_STATUS | | |
13014 | ELINK_NIG_MASK_MI_INT)); | |
13015 | ||
13016 | for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) { | |
13017 | if (params->phy[phy_index].hw_reset) { | |
13018 | params->phy[phy_index].hw_reset(¶ms->phy[phy_index], | |
13019 | params); | |
13020 | params->phy[phy_index] = phy_null; | |
13021 | } | |
13022 | } | |
13023 | } | |
13024 | ||
13025 | void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars, | |
13026 | __rte_unused uint32_t chip_id, uint32_t shmem_base, | |
13027 | uint32_t shmem2_base, uint8_t port) | |
13028 | { | |
13029 | uint8_t gpio_num = 0xff, gpio_port = 0xff, phy_index; | |
13030 | uint32_t val; | |
13031 | uint32_t offset, aeu_mask, swap_val, swap_override, sync_offset; | |
13032 | if (CHIP_IS_E3(sc)) { | |
13033 | if (elink_get_mod_abs_int_cfg(sc, | |
13034 | shmem_base, | |
13035 | port, | |
13036 | &gpio_num, | |
13037 | &gpio_port) != ELINK_STATUS_OK) | |
13038 | return; | |
13039 | } else { | |
13040 | struct elink_phy phy; | |
13041 | for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; | |
13042 | phy_index++) { | |
13043 | if (elink_populate_phy(sc, phy_index, shmem_base, | |
13044 | shmem2_base, port, &phy) | |
13045 | != ELINK_STATUS_OK) { | |
13046 | PMD_DRV_LOG(DEBUG, "populate phy failed"); | |
13047 | return; | |
13048 | } | |
13049 | if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726) { | |
13050 | gpio_num = MISC_REGISTERS_GPIO_3; | |
13051 | gpio_port = port; | |
13052 | break; | |
13053 | } | |
13054 | } | |
13055 | } | |
13056 | ||
13057 | if (gpio_num == 0xff) | |
13058 | return; | |
13059 | ||
13060 | /* Set GPIO3 to trigger SFP+ module insertion/removal */ | |
13061 | elink_cb_gpio_write(sc, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, | |
13062 | gpio_port); | |
13063 | ||
13064 | swap_val = REG_RD(sc, NIG_REG_PORT_SWAP); | |
13065 | swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE); | |
13066 | gpio_port ^= (swap_val && swap_override); | |
13067 | ||
13068 | vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 << | |
13069 | (gpio_num + (gpio_port << 2)); | |
13070 | ||
13071 | sync_offset = shmem_base + | |
13072 | offsetof(struct shmem_region, | |
13073 | dev_info.port_hw_config[port].aeu_int_mask); | |
13074 | REG_WR(sc, sync_offset, vars->aeu_int_mask); | |
13075 | ||
13076 | PMD_DRV_LOG(DEBUG, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x", | |
13077 | gpio_num, gpio_port, vars->aeu_int_mask); | |
13078 | ||
13079 | if (port == 0) | |
13080 | offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; | |
13081 | else | |
13082 | offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0; | |
13083 | ||
13084 | /* Open appropriate AEU for interrupts */ | |
13085 | aeu_mask = REG_RD(sc, offset); | |
13086 | aeu_mask |= vars->aeu_int_mask; | |
13087 | REG_WR(sc, offset, aeu_mask); | |
13088 | ||
13089 | /* Enable the GPIO to trigger interrupt */ | |
13090 | val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN); | |
13091 | val |= 1 << (gpio_num + (gpio_port << 2)); | |
13092 | REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val); | |
13093 | } |