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1 | /******************************************************************************* |
2 | ||
3 | Copyright (c) 2001-2015, Intel Corporation | |
4 | All rights reserved. | |
5 | ||
6 | Redistribution and use in source and binary forms, with or without | |
7 | modification, are permitted provided that the following conditions are met: | |
8 | ||
9 | 1. Redistributions of source code must retain the above copyright notice, | |
10 | this list of conditions and the following disclaimer. | |
11 | ||
12 | 2. Redistributions in binary form must reproduce the above copyright | |
13 | notice, this list of conditions and the following disclaimer in the | |
14 | documentation and/or other materials provided with the distribution. | |
15 | ||
16 | 3. Neither the name of the Intel Corporation nor the names of its | |
17 | contributors may be used to endorse or promote products derived from | |
18 | this software without specific prior written permission. | |
19 | ||
20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
23 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | |
24 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
25 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
26 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
27 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
28 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
29 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
30 | POSSIBILITY OF SUCH DAMAGE. | |
31 | ||
32 | ***************************************************************************/ | |
33 | ||
34 | #ifndef _E1000_82541_H_ | |
35 | #define _E1000_82541_H_ | |
36 | ||
37 | #define NVM_WORD_SIZE_BASE_SHIFT_82541 (NVM_WORD_SIZE_BASE_SHIFT + 1) | |
38 | ||
39 | #define IGP01E1000_PHY_CHANNEL_NUM 4 | |
40 | ||
41 | #define IGP01E1000_PHY_AGC_A 0x1172 | |
42 | #define IGP01E1000_PHY_AGC_B 0x1272 | |
43 | #define IGP01E1000_PHY_AGC_C 0x1472 | |
44 | #define IGP01E1000_PHY_AGC_D 0x1872 | |
45 | ||
46 | #define IGP01E1000_PHY_AGC_PARAM_A 0x1171 | |
47 | #define IGP01E1000_PHY_AGC_PARAM_B 0x1271 | |
48 | #define IGP01E1000_PHY_AGC_PARAM_C 0x1471 | |
49 | #define IGP01E1000_PHY_AGC_PARAM_D 0x1871 | |
50 | ||
51 | #define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000 | |
52 | #define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000 | |
53 | ||
54 | #define IGP01E1000_PHY_DSP_RESET 0x1F33 | |
55 | ||
56 | #define IGP01E1000_PHY_DSP_FFE 0x1F35 | |
57 | #define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069 | |
58 | #define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A | |
59 | ||
60 | #define IGP01E1000_IEEE_FORCE_GIG 0x0140 | |
61 | #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 | |
62 | ||
63 | #define IGP01E1000_AGC_LENGTH_SHIFT 7 | |
64 | #define IGP01E1000_AGC_RANGE 10 | |
65 | ||
66 | #define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20 | |
67 | #define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100 | |
68 | ||
69 | #define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0 | |
70 | #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1 | |
71 | #define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC | |
72 | #define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE | |
73 | ||
74 | #define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100 | |
75 | #define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80 | |
76 | #define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070 | |
77 | #define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040 | |
78 | #define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010 | |
79 | #define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080 | |
80 | #define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500 | |
81 | #define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000 | |
82 | #define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002 | |
83 | ||
84 | #define IGP01E1000_MSE_CHANNEL_D 0x000F | |
85 | #define IGP01E1000_MSE_CHANNEL_C 0x00F0 | |
86 | #define IGP01E1000_MSE_CHANNEL_B 0x0F00 | |
87 | #define IGP01E1000_MSE_CHANNEL_A 0xF000 | |
88 | ||
89 | ||
90 | void e1000_init_script_state_82541(struct e1000_hw *hw, bool state); | |
91 | #endif |