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1 | /******************************************************************************* |
2 | ||
3 | Copyright (c) 2001-2015, Intel Corporation | |
4 | All rights reserved. | |
5 | ||
6 | Redistribution and use in source and binary forms, with or without | |
7 | modification, are permitted provided that the following conditions are met: | |
8 | ||
9 | 1. Redistributions of source code must retain the above copyright notice, | |
10 | this list of conditions and the following disclaimer. | |
11 | ||
12 | 2. Redistributions in binary form must reproduce the above copyright | |
13 | notice, this list of conditions and the following disclaimer in the | |
14 | documentation and/or other materials provided with the distribution. | |
15 | ||
16 | 3. Neither the name of the Intel Corporation nor the names of its | |
17 | contributors may be used to endorse or promote products derived from | |
18 | this software without specific prior written permission. | |
19 | ||
20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
23 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | |
24 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
25 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
26 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
27 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
28 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
29 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
30 | POSSIBILITY OF SUCH DAMAGE. | |
31 | ||
32 | ***************************************************************************/ | |
33 | ||
34 | #ifndef _E1000_DEFINES_H_ | |
35 | #define _E1000_DEFINES_H_ | |
36 | ||
37 | /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ | |
38 | #define REQ_TX_DESCRIPTOR_MULTIPLE 8 | |
39 | #define REQ_RX_DESCRIPTOR_MULTIPLE 8 | |
40 | ||
41 | /* Definitions for power management and wakeup registers */ | |
42 | /* Wake Up Control */ | |
43 | #define E1000_WUC_APME 0x00000001 /* APM Enable */ | |
44 | #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ | |
45 | #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ | |
46 | #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ | |
47 | #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ | |
48 | ||
49 | /* Wake Up Filter Control */ | |
50 | #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ | |
51 | #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ | |
52 | #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ | |
53 | #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ | |
54 | #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ | |
55 | #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ | |
56 | #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ | |
57 | #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ | |
58 | ||
59 | /* Wake Up Status */ | |
60 | #define E1000_WUS_LNKC E1000_WUFC_LNKC | |
61 | #define E1000_WUS_MAG E1000_WUFC_MAG | |
62 | #define E1000_WUS_EX E1000_WUFC_EX | |
63 | #define E1000_WUS_MC E1000_WUFC_MC | |
64 | #define E1000_WUS_BC E1000_WUFC_BC | |
65 | ||
66 | /* Extended Device Control */ | |
67 | #define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */ | |
68 | #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */ | |
69 | #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */ | |
70 | #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */ | |
71 | /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */ | |
72 | #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ | |
73 | #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ | |
74 | #define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */ | |
75 | #define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */ | |
76 | #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ | |
77 | /* Physical Func Reset Done Indication */ | |
78 | #define E1000_CTRL_EXT_PFRSTD 0x00004000 | |
79 | #define E1000_CTRL_EXT_SDLPE 0X00040000 /* SerDes Low Power Enable */ | |
80 | #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ | |
81 | #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ | |
82 | #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clk Gating */ | |
83 | #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 | |
84 | /* Offset of the link mode field in Ctrl Ext register */ | |
85 | #define E1000_CTRL_EXT_LINK_MODE_OFFSET 22 | |
86 | #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000 | |
87 | #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 | |
88 | #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 | |
89 | #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 | |
90 | #define E1000_CTRL_EXT_EIAME 0x01000000 | |
91 | #define E1000_CTRL_EXT_IRCA 0x00000001 | |
92 | #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */ | |
93 | #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */ | |
94 | #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ | |
95 | #define E1000_CTRL_EXT_LSECCK 0x00001000 | |
96 | #define E1000_CTRL_EXT_PHYPDEN 0x00100000 | |
97 | #define E1000_I2CCMD_REG_ADDR_SHIFT 16 | |
98 | #define E1000_I2CCMD_PHY_ADDR_SHIFT 24 | |
99 | #define E1000_I2CCMD_OPCODE_READ 0x08000000 | |
100 | #define E1000_I2CCMD_OPCODE_WRITE 0x00000000 | |
101 | #define E1000_I2CCMD_READY 0x20000000 | |
102 | #define E1000_I2CCMD_ERROR 0x80000000 | |
103 | #define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a)) | |
104 | #define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a)) | |
105 | #define E1000_MAX_SGMII_PHY_REG_ADDR 255 | |
106 | #define E1000_I2CCMD_PHY_TIMEOUT 200 | |
107 | #define E1000_IVAR_VALID 0x80 | |
108 | #define E1000_GPIE_NSICR 0x00000001 | |
109 | #define E1000_GPIE_MSIX_MODE 0x00000010 | |
110 | #define E1000_GPIE_EIAME 0x40000000 | |
111 | #define E1000_GPIE_PBA 0x80000000 | |
112 | ||
113 | /* Receive Descriptor bit definitions */ | |
114 | #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ | |
115 | #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ | |
116 | #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ | |
117 | #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ | |
118 | #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ | |
119 | #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ | |
120 | #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ | |
121 | #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ | |
122 | #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ | |
123 | #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ | |
124 | #define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ | |
125 | #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ | |
126 | #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ | |
127 | #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ | |
128 | #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ | |
129 | #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ | |
130 | #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ | |
131 | #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ | |
132 | #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ | |
133 | ||
134 | #define E1000_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */ | |
135 | #define E1000_RXDEXT_STATERR_LB 0x00040000 | |
136 | #define E1000_RXDEXT_STATERR_CE 0x01000000 | |
137 | #define E1000_RXDEXT_STATERR_SE 0x02000000 | |
138 | #define E1000_RXDEXT_STATERR_SEQ 0x04000000 | |
139 | #define E1000_RXDEXT_STATERR_CXE 0x10000000 | |
140 | #define E1000_RXDEXT_STATERR_TCPE 0x20000000 | |
141 | #define E1000_RXDEXT_STATERR_IPE 0x40000000 | |
142 | #define E1000_RXDEXT_STATERR_RXE 0x80000000 | |
143 | ||
144 | /* mask to determine if packets should be dropped due to frame errors */ | |
145 | #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ | |
146 | E1000_RXD_ERR_CE | \ | |
147 | E1000_RXD_ERR_SE | \ | |
148 | E1000_RXD_ERR_SEQ | \ | |
149 | E1000_RXD_ERR_CXE | \ | |
150 | E1000_RXD_ERR_RXE) | |
151 | ||
152 | /* Same mask, but for extended and packet split descriptors */ | |
153 | #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ | |
154 | E1000_RXDEXT_STATERR_CE | \ | |
155 | E1000_RXDEXT_STATERR_SE | \ | |
156 | E1000_RXDEXT_STATERR_SEQ | \ | |
157 | E1000_RXDEXT_STATERR_CXE | \ | |
158 | E1000_RXDEXT_STATERR_RXE) | |
159 | ||
160 | #if !defined(EXTERNAL_RELEASE) || defined(E1000E_MQ) | |
161 | #define E1000_MRQC_ENABLE_RSS_2Q 0x00000001 | |
162 | #endif /* !EXTERNAL_RELEASE || E1000E_MQ */ | |
163 | #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 | |
164 | #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 | |
165 | #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 | |
166 | #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 | |
167 | #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 | |
168 | #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 | |
169 | ||
170 | #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 | |
171 | ||
172 | /* Management Control */ | |
173 | #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ | |
174 | #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ | |
175 | #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ | |
176 | #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ | |
177 | #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ | |
178 | /* Enable MAC address filtering */ | |
179 | #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 | |
180 | /* Enable MNG packets to host memory */ | |
181 | #define E1000_MANC_EN_MNG2HOST 0x00200000 | |
182 | ||
183 | #define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */ | |
184 | #define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */ | |
185 | #define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */ | |
186 | #define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */ | |
187 | ||
188 | /* Receive Control */ | |
189 | #define E1000_RCTL_RST 0x00000001 /* Software reset */ | |
190 | #define E1000_RCTL_EN 0x00000002 /* enable */ | |
191 | #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ | |
192 | #define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */ | |
193 | #define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */ | |
194 | #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ | |
195 | #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ | |
196 | #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ | |
197 | #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ | |
198 | #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ | |
199 | #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */ | |
200 | #define E1000_RCTL_RDMTS_HEX 0x00010000 | |
201 | #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ | |
202 | #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ | |
203 | #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ | |
204 | /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ | |
205 | #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ | |
206 | #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ | |
207 | #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ | |
208 | #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ | |
209 | /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ | |
210 | #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */ | |
211 | #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */ | |
212 | #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */ | |
213 | #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ | |
214 | #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ | |
215 | #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ | |
216 | #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ | |
217 | #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ | |
218 | #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ | |
219 | #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ | |
220 | ||
221 | /* Use byte values for the following shift parameters | |
222 | * Usage: | |
223 | * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & | |
224 | * E1000_PSRCTL_BSIZE0_MASK) | | |
225 | * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & | |
226 | * E1000_PSRCTL_BSIZE1_MASK) | | |
227 | * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & | |
228 | * E1000_PSRCTL_BSIZE2_MASK) | | |
229 | * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; | |
230 | * E1000_PSRCTL_BSIZE3_MASK)) | |
231 | * where value0 = [128..16256], default=256 | |
232 | * value1 = [1024..64512], default=4096 | |
233 | * value2 = [0..64512], default=4096 | |
234 | * value3 = [0..64512], default=0 | |
235 | */ | |
236 | ||
237 | #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F | |
238 | #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 | |
239 | #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 | |
240 | #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 | |
241 | ||
242 | #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ | |
243 | #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ | |
244 | #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ | |
245 | #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ | |
246 | ||
247 | /* SWFW_SYNC Definitions */ | |
248 | #define E1000_SWFW_EEP_SM 0x01 | |
249 | #define E1000_SWFW_PHY0_SM 0x02 | |
250 | #define E1000_SWFW_PHY1_SM 0x04 | |
251 | #define E1000_SWFW_CSR_SM 0x08 | |
252 | #define E1000_SWFW_PHY2_SM 0x20 | |
253 | #define E1000_SWFW_PHY3_SM 0x40 | |
254 | #define E1000_SWFW_SW_MNG_SM 0x400 | |
255 | ||
256 | /* Device Control */ | |
257 | #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ | |
258 | #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ | |
259 | #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */ | |
260 | #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ | |
261 | #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ | |
262 | #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ | |
263 | #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ | |
264 | #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ | |
265 | #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ | |
266 | #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ | |
267 | #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ | |
268 | #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ | |
269 | #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ | |
270 | #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ | |
271 | #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ | |
272 | #define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */ | |
273 | #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ | |
274 | #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ | |
275 | #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ | |
276 | #define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ | |
277 | #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */ | |
278 | #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ | |
279 | #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ | |
280 | #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ | |
281 | #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ | |
282 | #define E1000_CTRL_RST 0x04000000 /* Global reset */ | |
283 | #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ | |
284 | #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ | |
285 | #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ | |
286 | #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ | |
287 | #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ | |
288 | ||
289 | #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 | |
290 | #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 | |
291 | #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 | |
292 | #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 | |
293 | ||
294 | #define E1000_CONNSW_ENRGSRC 0x4 | |
295 | #define E1000_CONNSW_PHYSD 0x400 | |
296 | #define E1000_CONNSW_PHY_PDN 0x800 | |
297 | #define E1000_CONNSW_SERDESD 0x200 | |
298 | #define E1000_CONNSW_AUTOSENSE_CONF 0x2 | |
299 | #define E1000_CONNSW_AUTOSENSE_EN 0x1 | |
300 | #define E1000_PCS_CFG_PCS_EN 8 | |
301 | #define E1000_PCS_LCTL_FLV_LINK_UP 1 | |
302 | #define E1000_PCS_LCTL_FSV_10 0 | |
303 | #define E1000_PCS_LCTL_FSV_100 2 | |
304 | #define E1000_PCS_LCTL_FSV_1000 4 | |
305 | #define E1000_PCS_LCTL_FDV_FULL 8 | |
306 | #define E1000_PCS_LCTL_FSD 0x10 | |
307 | #define E1000_PCS_LCTL_FORCE_LINK 0x20 | |
308 | #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 | |
309 | #define E1000_PCS_LCTL_AN_ENABLE 0x10000 | |
310 | #define E1000_PCS_LCTL_AN_RESTART 0x20000 | |
311 | #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 | |
312 | #define E1000_ENABLE_SERDES_LOOPBACK 0x0410 | |
313 | ||
314 | #define E1000_PCS_LSTS_LINK_OK 1 | |
315 | #define E1000_PCS_LSTS_SPEED_100 2 | |
316 | #define E1000_PCS_LSTS_SPEED_1000 4 | |
317 | #define E1000_PCS_LSTS_DUPLEX_FULL 8 | |
318 | #define E1000_PCS_LSTS_SYNK_OK 0x10 | |
319 | #define E1000_PCS_LSTS_AN_COMPLETE 0x10000 | |
320 | ||
321 | /* Device Status */ | |
322 | #define E1000_STATUS_FD 0x00000001 /* Duplex 0=half 1=full */ | |
323 | #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ | |
324 | #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ | |
325 | #define E1000_STATUS_FUNC_SHIFT 2 | |
326 | #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ | |
327 | #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ | |
328 | #define E1000_STATUS_SPEED_MASK 0x000000C0 | |
329 | #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ | |
330 | #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ | |
331 | #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ | |
332 | #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Compltn by NVM */ | |
333 | #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ | |
334 | #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */ | |
335 | #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ | |
336 | #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ | |
337 | #define E1000_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */ | |
338 | #define E1000_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */ | |
339 | #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ | |
340 | #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ | |
341 | ||
342 | /* Constants used to interpret the masked PCI-X bus speed. */ | |
343 | #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */ | |
344 | #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */ | |
345 | #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/ | |
346 | ||
347 | #define SPEED_10 10 | |
348 | #define SPEED_100 100 | |
349 | #define SPEED_1000 1000 | |
350 | #define SPEED_2500 2500 | |
351 | #define HALF_DUPLEX 1 | |
352 | #define FULL_DUPLEX 2 | |
353 | ||
354 | #define PHY_FORCE_TIME 20 | |
355 | ||
356 | #define ADVERTISE_10_HALF 0x0001 | |
357 | #define ADVERTISE_10_FULL 0x0002 | |
358 | #define ADVERTISE_100_HALF 0x0004 | |
359 | #define ADVERTISE_100_FULL 0x0008 | |
360 | #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ | |
361 | #define ADVERTISE_1000_FULL 0x0020 | |
362 | ||
363 | /* 1000/H is not supported, nor spec-compliant. */ | |
364 | #define E1000_ALL_SPEED_DUPLEX ( \ | |
365 | ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ | |
366 | ADVERTISE_100_FULL | ADVERTISE_1000_FULL) | |
367 | #define E1000_ALL_NOT_GIG ( \ | |
368 | ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ | |
369 | ADVERTISE_100_FULL) | |
370 | #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) | |
371 | #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) | |
372 | #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) | |
373 | ||
374 | #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX | |
375 | ||
376 | /* LED Control */ | |
377 | #define E1000_PHY_LED0_MODE_MASK 0x00000007 | |
378 | #define E1000_PHY_LED0_IVRT 0x00000008 | |
379 | #define E1000_PHY_LED0_MASK 0x0000001F | |
380 | ||
381 | #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F | |
382 | #define E1000_LEDCTL_LED0_MODE_SHIFT 0 | |
383 | #define E1000_LEDCTL_LED0_IVRT 0x00000040 | |
384 | #define E1000_LEDCTL_LED0_BLINK 0x00000080 | |
385 | ||
386 | #define E1000_LEDCTL_MODE_LINK_UP 0x2 | |
387 | #define E1000_LEDCTL_MODE_LED_ON 0xE | |
388 | #define E1000_LEDCTL_MODE_LED_OFF 0xF | |
389 | ||
390 | /* Transmit Descriptor bit definitions */ | |
391 | #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ | |
392 | #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ | |
393 | #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ | |
394 | #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ | |
395 | #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ | |
396 | #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ | |
397 | #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ | |
398 | #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ | |
399 | #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ | |
400 | #define E1000_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */ | |
401 | #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ | |
402 | #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ | |
403 | #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ | |
404 | #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ | |
405 | #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ | |
406 | #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ | |
407 | #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ | |
408 | #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ | |
409 | #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ | |
410 | #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ | |
411 | #define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */ | |
412 | ||
413 | /* Transmit Control */ | |
414 | #define E1000_TCTL_EN 0x00000002 /* enable Tx */ | |
415 | #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ | |
416 | #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ | |
417 | #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ | |
418 | #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ | |
419 | #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ | |
420 | ||
421 | /* Transmit Arbitration Count */ | |
422 | #define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */ | |
423 | ||
424 | /* SerDes Control */ | |
425 | #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 | |
426 | #define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410 | |
427 | ||
428 | /* Receive Checksum Control */ | |
429 | #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ | |
430 | #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ | |
431 | #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ | |
432 | #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ | |
433 | #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ | |
434 | ||
435 | /* Header split receive */ | |
436 | #define E1000_RFCTL_NFSW_DIS 0x00000040 | |
437 | #define E1000_RFCTL_NFSR_DIS 0x00000080 | |
438 | #define E1000_RFCTL_ACK_DIS 0x00001000 | |
439 | #define E1000_RFCTL_EXTEN 0x00008000 | |
440 | #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 | |
441 | #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 | |
442 | #define E1000_RFCTL_LEF 0x00040000 | |
443 | ||
444 | /* Collision related configuration parameters */ | |
445 | #define E1000_COLLISION_THRESHOLD 15 | |
446 | #define E1000_CT_SHIFT 4 | |
447 | #define E1000_COLLISION_DISTANCE 63 | |
448 | #define E1000_COLD_SHIFT 12 | |
449 | ||
450 | /* Default values for the transmit IPG register */ | |
451 | #define DEFAULT_82542_TIPG_IPGT 10 | |
452 | #define DEFAULT_82543_TIPG_IPGT_FIBER 9 | |
453 | #define DEFAULT_82543_TIPG_IPGT_COPPER 8 | |
454 | ||
455 | #define E1000_TIPG_IPGT_MASK 0x000003FF | |
456 | ||
457 | #define DEFAULT_82542_TIPG_IPGR1 2 | |
458 | #define DEFAULT_82543_TIPG_IPGR1 8 | |
459 | #define E1000_TIPG_IPGR1_SHIFT 10 | |
460 | ||
461 | #define DEFAULT_82542_TIPG_IPGR2 10 | |
462 | #define DEFAULT_82543_TIPG_IPGR2 6 | |
463 | #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 | |
464 | #define E1000_TIPG_IPGR2_SHIFT 20 | |
465 | ||
466 | /* Ethertype field values */ | |
467 | #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ | |
468 | ||
469 | #define ETHERNET_FCS_SIZE 4 | |
470 | #define MAX_JUMBO_FRAME_SIZE 0x3F00 | |
471 | #define E1000_TX_PTR_GAP 0x1F | |
472 | ||
473 | /* Extended Configuration Control and Size */ | |
474 | #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 | |
475 | #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 | |
476 | #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 | |
477 | #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 | |
478 | #define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080 | |
479 | #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 | |
480 | #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 | |
481 | #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 | |
482 | #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 | |
483 | ||
484 | #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 | |
485 | #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 | |
486 | #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 | |
487 | #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 | |
488 | ||
489 | #define E1000_KABGTXD_BGSQLBIAS 0x00050000 | |
490 | ||
491 | /* Low Power IDLE Control */ | |
492 | #define E1000_LPIC_LPIET_SHIFT 24 /* Low Power Idle Entry Time */ | |
493 | ||
494 | /* PBA constants */ | |
495 | #define E1000_PBA_8K 0x0008 /* 8KB */ | |
496 | #define E1000_PBA_10K 0x000A /* 10KB */ | |
497 | #define E1000_PBA_12K 0x000C /* 12KB */ | |
498 | #define E1000_PBA_14K 0x000E /* 14KB */ | |
499 | #define E1000_PBA_16K 0x0010 /* 16KB */ | |
500 | #define E1000_PBA_18K 0x0012 | |
501 | #define E1000_PBA_20K 0x0014 | |
502 | #define E1000_PBA_22K 0x0016 | |
503 | #define E1000_PBA_24K 0x0018 | |
504 | #define E1000_PBA_26K 0x001A | |
505 | #define E1000_PBA_30K 0x001E | |
506 | #define E1000_PBA_32K 0x0020 | |
507 | #define E1000_PBA_34K 0x0022 | |
508 | #define E1000_PBA_35K 0x0023 | |
509 | #define E1000_PBA_38K 0x0026 | |
510 | #define E1000_PBA_40K 0x0028 | |
511 | #define E1000_PBA_48K 0x0030 /* 48KB */ | |
512 | #define E1000_PBA_64K 0x0040 /* 64KB */ | |
513 | ||
514 | #define E1000_PBA_RXA_MASK 0xFFFF | |
515 | ||
516 | #define E1000_PBS_16K E1000_PBA_16K | |
517 | ||
518 | /* Uncorrectable/correctable ECC Error counts and enable bits */ | |
519 | #define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF | |
520 | #define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00 | |
521 | #define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8 | |
522 | #define E1000_PBECCSTS_ECC_ENABLE 0x00010000 | |
523 | ||
524 | #define IFS_MAX 80 | |
525 | #define IFS_MIN 40 | |
526 | #define IFS_RATIO 4 | |
527 | #define IFS_STEP 10 | |
528 | #define MIN_NUM_XMITS 1000 | |
529 | ||
530 | /* SW Semaphore Register */ | |
531 | #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ | |
532 | #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ | |
533 | #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ | |
534 | ||
535 | #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ | |
536 | ||
537 | /* Interrupt Cause Read */ | |
538 | #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ | |
539 | #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ | |
540 | #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ | |
541 | #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */ | |
542 | #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ | |
543 | #define E1000_ICR_RXO 0x00000040 /* Rx overrun */ | |
544 | #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ | |
545 | #define E1000_ICR_VMMB 0x00000100 /* VM MB event */ | |
546 | #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */ | |
547 | #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ | |
548 | #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ | |
549 | #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ | |
550 | #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ | |
551 | #define E1000_ICR_TXD_LOW 0x00008000 | |
552 | #define E1000_ICR_MNG 0x00040000 /* Manageability event */ | |
553 | #define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */ | |
554 | #define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */ | |
555 | #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ | |
556 | /* If this bit asserted, the driver should claim the interrupt */ | |
557 | #define E1000_ICR_INT_ASSERTED 0x80000000 | |
558 | #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ | |
559 | #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ | |
560 | #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ | |
561 | #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ | |
562 | #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ | |
563 | #define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ | |
564 | #define E1000_ICR_FER 0x00400000 /* Fatal Error */ | |
565 | ||
566 | #define E1000_ICR_THS 0x00800000 /* ICR.THS: Thermal Sensor Event*/ | |
567 | #define E1000_ICR_MDDET 0x10000000 /* Malicious Driver Detect */ | |
568 | ||
569 | /* PBA ECC Register */ | |
570 | #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ | |
571 | #define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ | |
572 | #define E1000_PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */ | |
573 | #define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ | |
574 | #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */ | |
575 | ||
576 | /* Extended Interrupt Cause Read */ | |
577 | #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ | |
578 | #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ | |
579 | #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ | |
580 | #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ | |
581 | #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ | |
582 | #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ | |
583 | #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ | |
584 | #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ | |
585 | #define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ | |
586 | #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ | |
587 | /* TCP Timer */ | |
588 | #define E1000_TCPTIMER_KS 0x00000100 /* KickStart */ | |
589 | #define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */ | |
590 | #define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */ | |
591 | #define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */ | |
592 | ||
593 | /* This defines the bits that are set in the Interrupt Mask | |
594 | * Set/Read Register. Each bit is documented below: | |
595 | * o RXT0 = Receiver Timer Interrupt (ring 0) | |
596 | * o TXDW = Transmit Descriptor Written Back | |
597 | * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) | |
598 | * o RXSEQ = Receive Sequence Error | |
599 | * o LSC = Link Status Change | |
600 | */ | |
601 | #define IMS_ENABLE_MASK ( \ | |
602 | E1000_IMS_RXT0 | \ | |
603 | E1000_IMS_TXDW | \ | |
604 | E1000_IMS_RXDMT0 | \ | |
605 | E1000_IMS_RXSEQ | \ | |
606 | E1000_IMS_LSC) | |
607 | ||
608 | /* Interrupt Mask Set */ | |
609 | #define E1000_IMS_TXDW E1000_ICR_TXDW /* Tx desc written back */ | |
610 | #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ | |
611 | #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ | |
612 | #define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */ | |
613 | #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ | |
614 | #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ | |
615 | #define E1000_IMS_RXO E1000_ICR_RXO /* Rx overrun */ | |
616 | #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ | |
617 | #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW | |
618 | #define E1000_IMS_ECCER E1000_ICR_ECCER /* Uncorrectable ECC Error */ | |
619 | #define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */ | |
620 | #define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */ | |
621 | #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ | |
622 | #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ | |
623 | #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ | |
624 | #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ | |
625 | #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */ | |
626 | #define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */ | |
627 | #define E1000_IMS_FER E1000_ICR_FER /* Fatal Error */ | |
628 | ||
629 | #define E1000_IMS_THS E1000_ICR_THS /* ICR.TS: Thermal Sensor Event*/ | |
630 | #define E1000_IMS_MDDET E1000_ICR_MDDET /* Malicious Driver Detect */ | |
631 | /* Extended Interrupt Mask Set */ | |
632 | #define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ | |
633 | #define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ | |
634 | #define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ | |
635 | #define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ | |
636 | #define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ | |
637 | #define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ | |
638 | #define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ | |
639 | #define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ | |
640 | #define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ | |
641 | #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ | |
642 | ||
643 | /* Interrupt Cause Set */ | |
644 | #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ | |
645 | #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ | |
646 | #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ | |
647 | ||
648 | /* Extended Interrupt Cause Set */ | |
649 | #define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ | |
650 | #define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ | |
651 | #define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ | |
652 | #define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ | |
653 | #define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ | |
654 | #define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ | |
655 | #define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ | |
656 | #define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ | |
657 | #define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ | |
658 | #define E1000_EICS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ | |
659 | ||
660 | #define E1000_EITR_ITR_INT_MASK 0x0000FFFF | |
661 | /* E1000_EITR_CNT_IGNR is only for 82576 and newer */ | |
662 | #define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */ | |
663 | #define E1000_EITR_INTERVAL 0x00007FFC | |
664 | ||
665 | /* Transmit Descriptor Control */ | |
666 | #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ | |
667 | #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ | |
668 | #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ | |
669 | #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ | |
670 | #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ | |
671 | #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ | |
672 | /* Enable the counting of descriptors still to be processed. */ | |
673 | #define E1000_TXDCTL_COUNT_DESC 0x00400000 | |
674 | ||
675 | /* Flow Control Constants */ | |
676 | #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 | |
677 | #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 | |
678 | #define FLOW_CONTROL_TYPE 0x8808 | |
679 | ||
680 | /* 802.1q VLAN Packet Size */ | |
681 | #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ | |
682 | #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ | |
683 | ||
684 | /* Receive Address | |
685 | * Number of high/low register pairs in the RAR. The RAR (Receive Address | |
686 | * Registers) holds the directed and multicast addresses that we monitor. | |
687 | * Technically, we have 16 spots. However, we reserve one of these spots | |
688 | * (RAR[15]) for our directed address used by controllers with | |
689 | * manageability enabled, allowing us room for 15 multicast addresses. | |
690 | */ | |
691 | #define E1000_RAR_ENTRIES 15 | |
692 | #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ | |
693 | #define E1000_RAL_MAC_ADDR_LEN 4 | |
694 | #define E1000_RAH_MAC_ADDR_LEN 2 | |
695 | #define E1000_RAH_QUEUE_MASK_82575 0x000C0000 | |
696 | #define E1000_RAH_POOL_1 0x00040000 | |
697 | ||
698 | /* Error Codes */ | |
699 | #define E1000_SUCCESS 0 | |
700 | #define E1000_ERR_NVM 1 | |
701 | #define E1000_ERR_PHY 2 | |
702 | #define E1000_ERR_CONFIG 3 | |
703 | #define E1000_ERR_PARAM 4 | |
704 | #define E1000_ERR_MAC_INIT 5 | |
705 | #define E1000_ERR_PHY_TYPE 6 | |
706 | #define E1000_ERR_RESET 9 | |
707 | #define E1000_ERR_MASTER_REQUESTS_PENDING 10 | |
708 | #define E1000_ERR_HOST_INTERFACE_COMMAND 11 | |
709 | #define E1000_BLK_PHY_RESET 12 | |
710 | #define E1000_ERR_SWFW_SYNC 13 | |
711 | #define E1000_NOT_IMPLEMENTED 14 | |
712 | #define E1000_ERR_MBX 15 | |
713 | #define E1000_ERR_INVALID_ARGUMENT 16 | |
714 | #define E1000_ERR_NO_SPACE 17 | |
715 | #define E1000_ERR_NVM_PBA_SECTION 18 | |
716 | #define E1000_ERR_I2C 19 | |
717 | #define E1000_ERR_INVM_VALUE_NOT_FOUND 20 | |
718 | ||
719 | /* Loop limit on how long we wait for auto-negotiation to complete */ | |
720 | #define FIBER_LINK_UP_LIMIT 50 | |
721 | #define COPPER_LINK_UP_LIMIT 10 | |
722 | #define PHY_AUTO_NEG_LIMIT 45 | |
723 | #define PHY_FORCE_LIMIT 20 | |
724 | /* Number of 100 microseconds we wait for PCI Express master disable */ | |
725 | #define MASTER_DISABLE_TIMEOUT 800 | |
726 | /* Number of milliseconds we wait for PHY configuration done after MAC reset */ | |
727 | #define PHY_CFG_TIMEOUT 100 | |
728 | /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ | |
729 | #define MDIO_OWNERSHIP_TIMEOUT 10 | |
730 | /* Number of milliseconds for NVM auto read done after MAC reset. */ | |
731 | #define AUTO_READ_DONE_TIMEOUT 10 | |
732 | ||
733 | /* Flow Control */ | |
734 | #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ | |
735 | #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ | |
736 | #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ | |
737 | ||
738 | /* Transmit Configuration Word */ | |
739 | #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ | |
740 | #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ | |
741 | #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ | |
742 | #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ | |
743 | #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ | |
744 | ||
745 | /* Receive Configuration Word */ | |
746 | #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ | |
747 | #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ | |
748 | #define E1000_RXCW_C 0x20000000 /* Receive config */ | |
749 | #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ | |
750 | ||
751 | #define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ | |
752 | #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */ | |
753 | ||
754 | #define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ | |
755 | #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ | |
756 | #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 | |
757 | #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 | |
758 | #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 | |
759 | #define E1000_TSYNCRXCTL_TYPE_ALL 0x08 | |
760 | #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A | |
761 | #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ | |
762 | #define E1000_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */ | |
763 | ||
764 | #define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000 | |
765 | #define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000 | |
766 | ||
767 | #define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000 | |
768 | #define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000 | |
769 | ||
770 | #define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF | |
771 | #define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 | |
772 | #define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01 | |
773 | #define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02 | |
774 | #define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03 | |
775 | #define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04 | |
776 | ||
777 | #define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00 | |
778 | #define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000 | |
779 | #define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100 | |
780 | #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200 | |
781 | #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300 | |
782 | #define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800 | |
783 | #define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900 | |
784 | #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00 | |
785 | #define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00 | |
786 | #define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00 | |
787 | #define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00 | |
788 | ||
789 | #define E1000_TIMINCA_16NS_SHIFT 24 | |
790 | #define E1000_TIMINCA_INCPERIOD_SHIFT 24 | |
791 | #define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF | |
792 | ||
793 | #define E1000_TSICR_TXTS 0x00000002 | |
794 | #define E1000_TSIM_TXTS 0x00000002 | |
795 | /* TUPLE Filtering Configuration */ | |
796 | #define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */ | |
797 | #define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */ | |
798 | #define E1000_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */ | |
799 | /* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */ | |
800 | #define E1000_TTQF_PROTOCOL_TCP 0x0 | |
801 | /* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */ | |
802 | #define E1000_TTQF_PROTOCOL_UDP 0x1 | |
803 | /* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */ | |
804 | #define E1000_TTQF_PROTOCOL_SCTP 0x2 | |
805 | #define E1000_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */ | |
806 | #define E1000_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */ | |
807 | #define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */ | |
808 | #define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */ | |
809 | #define E1000_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */ | |
810 | #define E1000_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */ | |
811 | #define E1000_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */ | |
812 | #define E1000_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */ | |
813 | ||
814 | #define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */ | |
815 | #define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */ | |
816 | #define E1000_MDICNFG_PHY_MASK 0x03E00000 | |
817 | #define E1000_MDICNFG_PHY_SHIFT 21 | |
818 | ||
819 | #define E1000_MEDIA_PORT_COPPER 1 | |
820 | #define E1000_MEDIA_PORT_OTHER 2 | |
821 | #define E1000_M88E1112_AUTO_COPPER_SGMII 0x2 | |
822 | #define E1000_M88E1112_AUTO_COPPER_BASEX 0x3 | |
823 | #define E1000_M88E1112_STATUS_LINK 0x0004 /* Interface Link Bit */ | |
824 | #define E1000_M88E1112_MAC_CTRL_1 0x10 | |
825 | #define E1000_M88E1112_MAC_CTRL_1_MODE_MASK 0x0380 /* Mode Select */ | |
826 | #define E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT 7 | |
827 | #define E1000_M88E1112_PAGE_ADDR 0x16 | |
828 | #define E1000_M88E1112_STATUS 0x01 | |
829 | ||
830 | #define E1000_THSTAT_LOW_EVENT 0x20000000 /* Low thermal threshold */ | |
831 | #define E1000_THSTAT_MID_EVENT 0x00200000 /* Mid thermal threshold */ | |
832 | #define E1000_THSTAT_HIGH_EVENT 0x00002000 /* High thermal threshold */ | |
833 | #define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */ | |
834 | #define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Spd Throttle Event */ | |
835 | ||
836 | /* I350 EEE defines */ | |
837 | #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */ | |
838 | #define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */ | |
839 | #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */ | |
840 | #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */ | |
841 | #define E1000_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */ | |
842 | /* EEE status */ | |
843 | #define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */ | |
844 | #define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */ | |
845 | #define E1000_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */ | |
846 | #define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */ | |
847 | #define E1000_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */ | |
848 | #define E1000_M88E1543_EEE_CTRL_1 0x0 | |
849 | #define E1000_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */ | |
850 | #define E1000_M88E1543_FIBER_CTRL 0x0 /* Fiber Control Register */ | |
851 | #define E1000_EEE_ADV_DEV_I354 7 | |
852 | #define E1000_EEE_ADV_ADDR_I354 60 | |
853 | #define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */ | |
854 | #define E1000_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */ | |
855 | #define E1000_PCS_STATUS_DEV_I354 3 | |
856 | #define E1000_PCS_STATUS_ADDR_I354 1 | |
857 | #define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400 | |
858 | #define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800 | |
859 | #define E1000_M88E1512_CFG_REG_1 0x0010 | |
860 | #define E1000_M88E1512_CFG_REG_2 0x0011 | |
861 | #define E1000_M88E1512_CFG_REG_3 0x0007 | |
862 | #define E1000_M88E1512_MODE 0x0014 | |
863 | #define E1000_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */ | |
864 | #define E1000_EEE_LP_ADV_DEV_I210 7 /* EEE LP Adv Device */ | |
865 | #define E1000_EEE_LP_ADV_ADDR_I210 61 /* EEE LP Adv Register */ | |
866 | /* PCI Express Control */ | |
867 | #define E1000_GCR_RXD_NO_SNOOP 0x00000001 | |
868 | #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 | |
869 | #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 | |
870 | #define E1000_GCR_TXD_NO_SNOOP 0x00000008 | |
871 | #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 | |
872 | #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 | |
873 | #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 | |
874 | #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 | |
875 | #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 | |
876 | #define E1000_GCR_CAP_VER2 0x00040000 | |
877 | ||
878 | #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ | |
879 | E1000_GCR_RXDSCW_NO_SNOOP | \ | |
880 | E1000_GCR_RXDSCR_NO_SNOOP | \ | |
881 | E1000_GCR_TXD_NO_SNOOP | \ | |
882 | E1000_GCR_TXDSCW_NO_SNOOP | \ | |
883 | E1000_GCR_TXDSCR_NO_SNOOP) | |
884 | ||
885 | #define E1000_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */ | |
886 | ||
887 | /* mPHY address control and data registers */ | |
888 | #define E1000_MPHY_ADDR_CTL 0x0024 /* Address Control Reg */ | |
889 | #define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000 | |
890 | #define E1000_MPHY_DATA 0x0E10 /* Data Register */ | |
891 | ||
892 | /* AFE CSR Offset for PCS CLK */ | |
893 | #define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004 | |
894 | /* Override for near end digital loopback. */ | |
895 | #define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10 | |
896 | ||
897 | /* PHY Control Register */ | |
898 | #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ | |
899 | #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ | |
900 | #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ | |
901 | #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ | |
902 | #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ | |
903 | #define MII_CR_POWER_DOWN 0x0800 /* Power down */ | |
904 | #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ | |
905 | #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ | |
906 | #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ | |
907 | #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ | |
908 | #define MII_CR_SPEED_1000 0x0040 | |
909 | #define MII_CR_SPEED_100 0x2000 | |
910 | #define MII_CR_SPEED_10 0x0000 | |
911 | ||
912 | /* PHY Status Register */ | |
913 | #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ | |
914 | #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ | |
915 | #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ | |
916 | #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ | |
917 | #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ | |
918 | #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ | |
919 | #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ | |
920 | #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ | |
921 | #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ | |
922 | #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ | |
923 | #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ | |
924 | #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ | |
925 | #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ | |
926 | #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ | |
927 | #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ | |
928 | ||
929 | /* Autoneg Advertisement Register */ | |
930 | #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ | |
931 | #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ | |
932 | #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ | |
933 | #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ | |
934 | #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ | |
935 | #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ | |
936 | #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ | |
937 | #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ | |
938 | #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ | |
939 | #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ | |
940 | ||
941 | /* Link Partner Ability Register (Base Page) */ | |
942 | #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ | |
943 | #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP 10T Half Dplx Capable */ | |
944 | #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP 10T Full Dplx Capable */ | |
945 | #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */ | |
946 | #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */ | |
947 | #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ | |
948 | #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ | |
949 | #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asym Pause Direction bit */ | |
950 | #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP detected Remote Fault */ | |
951 | #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */ | |
952 | #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ | |
953 | ||
954 | /* Autoneg Expansion Register */ | |
955 | #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ | |
956 | #define NWAY_ER_PAGE_RXD 0x0002 /* LP 10T Half Dplx Capable */ | |
957 | #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP 10T Full Dplx Capable */ | |
958 | #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */ | |
959 | #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */ | |
960 | ||
961 | /* 1000BASE-T Control Register */ | |
962 | #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ | |
963 | #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ | |
964 | #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ | |
965 | /* 1=Repeater/switch device port 0=DTE device */ | |
966 | #define CR_1000T_REPEATER_DTE 0x0400 | |
967 | /* 1=Configure PHY as Master 0=Configure PHY as Slave */ | |
968 | #define CR_1000T_MS_VALUE 0x0800 | |
969 | /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ | |
970 | #define CR_1000T_MS_ENABLE 0x1000 | |
971 | #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ | |
972 | #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ | |
973 | #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ | |
974 | #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ | |
975 | #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ | |
976 | ||
977 | /* 1000BASE-T Status Register */ | |
978 | #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle err since last rd */ | |
979 | #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asym pause direction bit */ | |
980 | #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ | |
981 | #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ | |
982 | #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ | |
983 | #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ | |
984 | #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx Master, 0=Slave */ | |
985 | #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ | |
986 | ||
987 | #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 | |
988 | ||
989 | /* PHY 1000 MII Register/Bit Definitions */ | |
990 | /* PHY Registers defined by IEEE */ | |
991 | #define PHY_CONTROL 0x00 /* Control Register */ | |
992 | #define PHY_STATUS 0x01 /* Status Register */ | |
993 | #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ | |
994 | #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ | |
995 | #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ | |
996 | #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ | |
997 | #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ | |
998 | #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */ | |
999 | #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ | |
1000 | #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ | |
1001 | #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ | |
1002 | #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ | |
1003 | ||
1004 | #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */ | |
1005 | ||
1006 | /* NVM Control */ | |
1007 | #define E1000_EECD_SK 0x00000001 /* NVM Clock */ | |
1008 | #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ | |
1009 | #define E1000_EECD_DI 0x00000004 /* NVM Data In */ | |
1010 | #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ | |
1011 | #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ | |
1012 | #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ | |
1013 | #define E1000_EECD_PRES 0x00000100 /* NVM Present */ | |
1014 | #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ | |
1015 | #define E1000_EECD_BLOCKED 0x00008000 /* Bit banging access blocked flag */ | |
1016 | #define E1000_EECD_ABORT 0x00010000 /* NVM operation aborted flag */ | |
1017 | #define E1000_EECD_TIMEOUT 0x00020000 /* NVM read operation timeout flag */ | |
1018 | #define E1000_EECD_ERROR_CLR 0x00040000 /* NVM error status clear bit */ | |
1019 | /* NVM Addressing bits based on type 0=small, 1=large */ | |
1020 | #define E1000_EECD_ADDR_BITS 0x00000400 | |
1021 | #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */ | |
1022 | #ifndef E1000_NVM_GRANT_ATTEMPTS | |
1023 | #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ | |
1024 | #endif | |
1025 | #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ | |
1026 | #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ | |
1027 | #define E1000_EECD_SIZE_EX_SHIFT 11 | |
1028 | #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ | |
1029 | #define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */ | |
1030 | #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ | |
1031 | #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) | |
1032 | #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ | |
1033 | #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done */ | |
1034 | #define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */ | |
1035 | #define E1000_EECD_SEC1VAL_I210 0x02000000 /* Sector One Valid */ | |
1036 | #define E1000_FLUDONE_ATTEMPTS 20000 | |
1037 | #define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ | |
1038 | #define E1000_I210_FIFO_SEL_RX 0x00 | |
1039 | #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) | |
1040 | #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0) | |
1041 | #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06 | |
1042 | #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01 | |
1043 | ||
1044 | #define E1000_I210_FLASH_SECTOR_SIZE 0x1000 /* 4KB FLASH sector unit size */ | |
1045 | /* Secure FLASH mode requires removing MSb */ | |
1046 | #define E1000_I210_FW_PTR_MASK 0x7FFF | |
1047 | /* Firmware code revision field word offset*/ | |
1048 | #define E1000_I210_FW_VER_OFFSET 328 | |
1049 | ||
1050 | #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */ | |
1051 | #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ | |
1052 | #define E1000_NVM_RW_REG_START 1 /* Start operation */ | |
1053 | #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ | |
1054 | #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ | |
1055 | #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ | |
1056 | #define E1000_FLASH_UPDATES 2000 | |
1057 | ||
1058 | /* NVM Word Offsets */ | |
1059 | #define NVM_COMPAT 0x0003 | |
1060 | #define NVM_ID_LED_SETTINGS 0x0004 | |
1061 | #define NVM_VERSION 0x0005 | |
1062 | #define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */ | |
1063 | #define NVM_PHY_CLASS_WORD 0x0007 | |
1064 | #define E1000_I210_NVM_FW_MODULE_PTR 0x0010 | |
1065 | #define E1000_I350_NVM_FW_MODULE_PTR 0x0051 | |
1066 | #define NVM_FUTURE_INIT_WORD1 0x0019 | |
1067 | #define NVM_ETRACK_WORD 0x0042 | |
1068 | #define NVM_ETRACK_HIWORD 0x0043 | |
1069 | #define NVM_COMB_VER_OFF 0x0083 | |
1070 | #define NVM_COMB_VER_PTR 0x003d | |
1071 | ||
1072 | /* NVM version defines */ | |
1073 | #define NVM_MAJOR_MASK 0xF000 | |
1074 | #define NVM_MINOR_MASK 0x0FF0 | |
1075 | #define NVM_IMAGE_ID_MASK 0x000F | |
1076 | #define NVM_COMB_VER_MASK 0x00FF | |
1077 | #define NVM_MAJOR_SHIFT 12 | |
1078 | #define NVM_MINOR_SHIFT 4 | |
1079 | #define NVM_COMB_VER_SHFT 8 | |
1080 | #define NVM_VER_INVALID 0xFFFF | |
1081 | #define NVM_ETRACK_SHIFT 16 | |
1082 | #define NVM_ETRACK_VALID 0x8000 | |
1083 | #define NVM_NEW_DEC_MASK 0x0F00 | |
1084 | #define NVM_HEX_CONV 16 | |
1085 | #define NVM_HEX_TENS 10 | |
1086 | ||
1087 | /* FW version defines */ | |
1088 | /* Offset of "Loader patch ptr" in Firmware Header */ | |
1089 | #define E1000_I350_NVM_FW_LOADER_PATCH_PTR_OFFSET 0x01 | |
1090 | /* Patch generation hour & minutes */ | |
1091 | #define E1000_I350_NVM_FW_VER_WORD1_OFFSET 0x04 | |
1092 | /* Patch generation month & day */ | |
1093 | #define E1000_I350_NVM_FW_VER_WORD2_OFFSET 0x05 | |
1094 | /* Patch generation year */ | |
1095 | #define E1000_I350_NVM_FW_VER_WORD3_OFFSET 0x06 | |
1096 | /* Patch major & minor numbers */ | |
1097 | #define E1000_I350_NVM_FW_VER_WORD4_OFFSET 0x07 | |
1098 | ||
1099 | #define NVM_MAC_ADDR 0x0000 | |
1100 | #define NVM_SUB_DEV_ID 0x000B | |
1101 | #define NVM_SUB_VEN_ID 0x000C | |
1102 | #define NVM_DEV_ID 0x000D | |
1103 | #define NVM_VEN_ID 0x000E | |
1104 | #define NVM_INIT_CTRL_2 0x000F | |
1105 | #define NVM_INIT_CTRL_4 0x0013 | |
1106 | #define NVM_LED_1_CFG 0x001C | |
1107 | #define NVM_LED_0_2_CFG 0x001F | |
1108 | ||
1109 | #define NVM_COMPAT_VALID_CSUM 0x0001 | |
1110 | #define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040 | |
1111 | ||
1112 | #define NVM_INIT_CONTROL2_REG 0x000F | |
1113 | #define NVM_INIT_CONTROL3_PORT_B 0x0014 | |
1114 | #define NVM_INIT_3GIO_3 0x001A | |
1115 | #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 | |
1116 | #define NVM_INIT_CONTROL3_PORT_A 0x0024 | |
1117 | #define NVM_CFG 0x0012 | |
1118 | #define NVM_ALT_MAC_ADDR_PTR 0x0037 | |
1119 | #define NVM_CHECKSUM_REG 0x003F | |
1120 | #define NVM_COMPATIBILITY_REG_3 0x0003 | |
1121 | #define NVM_COMPATIBILITY_BIT_MASK 0x8000 | |
1122 | ||
1123 | #define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ | |
1124 | #define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ | |
1125 | #define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */ | |
1126 | #define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */ | |
1127 | ||
1128 | #define NVM_82580_LAN_FUNC_OFFSET(a) ((a) ? (0x40 + (0x40 * (a))) : 0) | |
1129 | ||
1130 | /* Mask bits for fields in Word 0x24 of the NVM */ | |
1131 | #define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */ | |
1132 | #define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed extrnl */ | |
1133 | /* Offset of Link Mode bits for 82575/82576 */ | |
1134 | #define NVM_WORD24_LNK_MODE_OFFSET 8 | |
1135 | /* Offset of Link Mode bits for 82580 up */ | |
1136 | #define NVM_WORD24_82580_LNK_MODE_OFFSET 4 | |
1137 | ||
1138 | ||
1139 | /* Mask bits for fields in Word 0x0f of the NVM */ | |
1140 | #define NVM_WORD0F_PAUSE_MASK 0x3000 | |
1141 | #define NVM_WORD0F_PAUSE 0x1000 | |
1142 | #define NVM_WORD0F_ASM_DIR 0x2000 | |
1143 | #define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 | |
1144 | ||
1145 | /* Mask bits for fields in Word 0x1a of the NVM */ | |
1146 | #define NVM_WORD1A_ASPM_MASK 0x000C | |
1147 | ||
1148 | /* Mask bits for fields in Word 0x03 of the EEPROM */ | |
1149 | #define NVM_COMPAT_LOM 0x0800 | |
1150 | ||
1151 | /* length of string needed to store PBA number */ | |
1152 | #define E1000_PBANUM_LENGTH 11 | |
1153 | ||
1154 | /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ | |
1155 | #define NVM_SUM 0xBABA | |
1156 | ||
1157 | /* PBA (printed board assembly) number words */ | |
1158 | #define NVM_PBA_OFFSET_0 8 | |
1159 | #define NVM_PBA_OFFSET_1 9 | |
1160 | #define NVM_PBA_PTR_GUARD 0xFAFA | |
1161 | #define NVM_RESERVED_WORD 0xFFFF | |
1162 | #define NVM_PHY_CLASS_A 0x8000 | |
1163 | #define NVM_SERDES_AMPLITUDE_MASK 0x000F | |
1164 | #define NVM_SIZE_MASK 0x1C00 | |
1165 | #define NVM_SIZE_SHIFT 10 | |
1166 | #define NVM_WORD_SIZE_BASE_SHIFT 6 | |
1167 | #define NVM_SWDPIO_EXT_SHIFT 4 | |
1168 | ||
1169 | /* NVM Commands - Microwire */ | |
1170 | #define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */ | |
1171 | #define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */ | |
1172 | #define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */ | |
1173 | #define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */ | |
1174 | #define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erase/write disable */ | |
1175 | ||
1176 | /* NVM Commands - SPI */ | |
1177 | #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ | |
1178 | #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ | |
1179 | #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ | |
1180 | #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ | |
1181 | #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ | |
1182 | #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ | |
1183 | ||
1184 | /* SPI NVM Status Register */ | |
1185 | #define NVM_STATUS_RDY_SPI 0x01 | |
1186 | ||
1187 | /* Word definitions for ID LED Settings */ | |
1188 | #define ID_LED_RESERVED_0000 0x0000 | |
1189 | #define ID_LED_RESERVED_FFFF 0xFFFF | |
1190 | #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ | |
1191 | (ID_LED_OFF1_OFF2 << 8) | \ | |
1192 | (ID_LED_DEF1_DEF2 << 4) | \ | |
1193 | (ID_LED_DEF1_DEF2)) | |
1194 | #define ID_LED_DEF1_DEF2 0x1 | |
1195 | #define ID_LED_DEF1_ON2 0x2 | |
1196 | #define ID_LED_DEF1_OFF2 0x3 | |
1197 | #define ID_LED_ON1_DEF2 0x4 | |
1198 | #define ID_LED_ON1_ON2 0x5 | |
1199 | #define ID_LED_ON1_OFF2 0x6 | |
1200 | #define ID_LED_OFF1_DEF2 0x7 | |
1201 | #define ID_LED_OFF1_ON2 0x8 | |
1202 | #define ID_LED_OFF1_OFF2 0x9 | |
1203 | ||
1204 | #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF | |
1205 | #define IGP_ACTIVITY_LED_ENABLE 0x0300 | |
1206 | #define IGP_LED3_MODE 0x07000000 | |
1207 | ||
1208 | /* PCI/PCI-X/PCI-EX Config space */ | |
1209 | #define PCIX_COMMAND_REGISTER 0xE6 | |
1210 | #define PCIX_STATUS_REGISTER_LO 0xE8 | |
1211 | #define PCIX_STATUS_REGISTER_HI 0xEA | |
1212 | #define PCI_HEADER_TYPE_REGISTER 0x0E | |
1213 | #define PCIE_LINK_STATUS 0x12 | |
1214 | #define PCIE_DEVICE_CONTROL2 0x28 | |
1215 | ||
1216 | #define PCIX_COMMAND_MMRBC_MASK 0x000C | |
1217 | #define PCIX_COMMAND_MMRBC_SHIFT 0x2 | |
1218 | #define PCIX_STATUS_HI_MMRBC_MASK 0x0060 | |
1219 | #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 | |
1220 | #define PCIX_STATUS_HI_MMRBC_4K 0x3 | |
1221 | #define PCIX_STATUS_HI_MMRBC_2K 0x2 | |
1222 | #define PCIX_STATUS_LO_FUNC_MASK 0x7 | |
1223 | #define PCI_HEADER_TYPE_MULTIFUNC 0x80 | |
1224 | #define PCIE_LINK_WIDTH_MASK 0x3F0 | |
1225 | #define PCIE_LINK_WIDTH_SHIFT 4 | |
1226 | #define PCIE_LINK_SPEED_MASK 0x0F | |
1227 | #define PCIE_LINK_SPEED_2500 0x01 | |
1228 | #define PCIE_LINK_SPEED_5000 0x02 | |
1229 | #define PCIE_DEVICE_CONTROL2_16ms 0x0005 | |
1230 | ||
1231 | #ifndef ETH_ADDR_LEN | |
1232 | #define ETH_ADDR_LEN 6 | |
1233 | #endif | |
1234 | ||
1235 | #define PHY_REVISION_MASK 0xFFFFFFF0 | |
1236 | #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ | |
1237 | #define MAX_PHY_MULTI_PAGE_REG 0xF | |
1238 | ||
1239 | /* Bit definitions for valid PHY IDs. | |
1240 | * I = Integrated | |
1241 | * E = External | |
1242 | */ | |
1243 | #define M88E1000_E_PHY_ID 0x01410C50 | |
1244 | #define M88E1000_I_PHY_ID 0x01410C30 | |
1245 | #define M88E1011_I_PHY_ID 0x01410C20 | |
1246 | #define IGP01E1000_I_PHY_ID 0x02A80380 | |
1247 | #define M88E1111_I_PHY_ID 0x01410CC0 | |
1248 | #define M88E1543_E_PHY_ID 0x01410EA0 | |
1249 | #define M88E1512_E_PHY_ID 0x01410DD0 | |
1250 | #define M88E1112_E_PHY_ID 0x01410C90 | |
1251 | #define I347AT4_E_PHY_ID 0x01410DC0 | |
1252 | #define M88E1340M_E_PHY_ID 0x01410DF0 | |
1253 | #define GG82563_E_PHY_ID 0x01410CA0 | |
1254 | #define IGP03E1000_E_PHY_ID 0x02A80390 | |
1255 | #define IFE_E_PHY_ID 0x02A80330 | |
1256 | #define IFE_PLUS_E_PHY_ID 0x02A80320 | |
1257 | #define IFE_C_E_PHY_ID 0x02A80310 | |
1258 | #define BME1000_E_PHY_ID 0x01410CB0 | |
1259 | #define BME1000_E_PHY_ID_R2 0x01410CB1 | |
1260 | #define I82577_E_PHY_ID 0x01540050 | |
1261 | #define I82578_E_PHY_ID 0x004DD040 | |
1262 | #define I82579_E_PHY_ID 0x01540090 | |
1263 | #define I217_E_PHY_ID 0x015400A0 | |
1264 | #define I82580_I_PHY_ID 0x015403A0 | |
1265 | #define I350_I_PHY_ID 0x015403B0 | |
1266 | #define I210_I_PHY_ID 0x01410C00 | |
1267 | #define IGP04E1000_E_PHY_ID 0x02A80391 | |
1268 | #define M88_VENDOR 0x0141 | |
1269 | ||
1270 | /* M88E1000 Specific Registers */ | |
1271 | #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */ | |
1272 | #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Reg */ | |
1273 | #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Cntrl */ | |
1274 | #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ | |
1275 | ||
1276 | #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ | |
1277 | #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for pg number setting */ | |
1278 | #define M88E1000_PHY_GEN_CONTROL 0x1E /* meaning depends on reg 29 */ | |
1279 | #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ | |
1280 | #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ | |
1281 | ||
1282 | /* M88E1000 PHY Specific Control Register */ | |
1283 | #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */ | |
1284 | /* MDI Crossover Mode bits 6:5 Manual MDI configuration */ | |
1285 | #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 | |
1286 | #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ | |
1287 | /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ | |
1288 | #define M88E1000_PSCR_AUTO_X_1000T 0x0040 | |
1289 | /* Auto crossover enabled all speeds */ | |
1290 | #define M88E1000_PSCR_AUTO_X_MODE 0x0060 | |
1291 | #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */ | |
1292 | ||
1293 | /* M88E1000 PHY Specific Status Register */ | |
1294 | #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ | |
1295 | #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ | |
1296 | #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ | |
1297 | /* 0 = <50M | |
1298 | * 1 = 50-80M | |
1299 | * 2 = 80-110M | |
1300 | * 3 = 110-140M | |
1301 | * 4 = >140M | |
1302 | */ | |
1303 | #define M88E1000_PSSR_CABLE_LENGTH 0x0380 | |
1304 | #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ | |
1305 | #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ | |
1306 | #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ | |
1307 | #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ | |
1308 | #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ | |
1309 | #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ | |
1310 | ||
1311 | #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 | |
1312 | ||
1313 | /* Number of times we will attempt to autonegotiate before downshifting if we | |
1314 | * are the master | |
1315 | */ | |
1316 | #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 | |
1317 | #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 | |
1318 | /* Number of times we will attempt to autonegotiate before downshifting if we | |
1319 | * are the slave | |
1320 | */ | |
1321 | #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 | |
1322 | #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 | |
1323 | #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ | |
1324 | ||
1325 | /* Intel I347AT4 Registers */ | |
1326 | #define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */ | |
1327 | #define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */ | |
1328 | #define I347AT4_PAGE_SELECT 0x16 | |
1329 | ||
1330 | /* I347AT4 Extended PHY Specific Control Register */ | |
1331 | ||
1332 | /* Number of times we will attempt to autonegotiate before downshifting if we | |
1333 | * are the master | |
1334 | */ | |
1335 | #define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800 | |
1336 | #define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000 | |
1337 | #define I347AT4_PSCR_DOWNSHIFT_1X 0x0000 | |
1338 | #define I347AT4_PSCR_DOWNSHIFT_2X 0x1000 | |
1339 | #define I347AT4_PSCR_DOWNSHIFT_3X 0x2000 | |
1340 | #define I347AT4_PSCR_DOWNSHIFT_4X 0x3000 | |
1341 | #define I347AT4_PSCR_DOWNSHIFT_5X 0x4000 | |
1342 | #define I347AT4_PSCR_DOWNSHIFT_6X 0x5000 | |
1343 | #define I347AT4_PSCR_DOWNSHIFT_7X 0x6000 | |
1344 | #define I347AT4_PSCR_DOWNSHIFT_8X 0x7000 | |
1345 | ||
1346 | /* I347AT4 PHY Cable Diagnostics Control */ | |
1347 | #define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */ | |
1348 | ||
1349 | /* M88E1112 only registers */ | |
1350 | #define M88E1112_VCT_DSP_DISTANCE 0x001A | |
1351 | ||
1352 | /* M88EC018 Rev 2 specific DownShift settings */ | |
1353 | #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 | |
1354 | #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 | |
1355 | ||
1356 | #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 | |
1357 | #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C | |
1358 | ||
1359 | /* BME1000 PHY Specific Control Register */ | |
1360 | #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ | |
1361 | ||
1362 | /* Bits... | |
1363 | * 15-5: page | |
1364 | * 4-0: register offset | |
1365 | */ | |
1366 | #define GG82563_PAGE_SHIFT 5 | |
1367 | #define GG82563_REG(page, reg) \ | |
1368 | (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) | |
1369 | #define GG82563_MIN_ALT_REG 30 | |
1370 | ||
1371 | /* GG82563 Specific Registers */ | |
1372 | #define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Spec Cntrl */ | |
1373 | #define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */ | |
1374 | #define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Spec Cntrl2 */ | |
1375 | #define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alt Page Select */ | |
1376 | ||
1377 | /* MAC Specific Control Register */ | |
1378 | #define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21) | |
1379 | ||
1380 | #define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) /* DSP Distance */ | |
1381 | ||
1382 | /* Page 193 - Port Control Registers */ | |
1383 | /* Kumeran Mode Control */ | |
1384 | #define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16) | |
1385 | #define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Pwr Mgt Ctrl */ | |
1386 | ||
1387 | /* Page 194 - KMRN Registers */ | |
1388 | #define GG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) /* Inband Ctrl */ | |
1389 | ||
1390 | /* MDI Control */ | |
1391 | #define E1000_MDIC_REG_MASK 0x001F0000 | |
1392 | #define E1000_MDIC_REG_SHIFT 16 | |
1393 | #define E1000_MDIC_PHY_MASK 0x03E00000 | |
1394 | #define E1000_MDIC_PHY_SHIFT 21 | |
1395 | #define E1000_MDIC_OP_WRITE 0x04000000 | |
1396 | #define E1000_MDIC_OP_READ 0x08000000 | |
1397 | #define E1000_MDIC_READY 0x10000000 | |
1398 | #define E1000_MDIC_ERROR 0x40000000 | |
1399 | #define E1000_MDIC_DEST 0x80000000 | |
1400 | ||
1401 | /* SerDes Control */ | |
1402 | #define E1000_GEN_CTL_READY 0x80000000 | |
1403 | #define E1000_GEN_CTL_ADDRESS_SHIFT 8 | |
1404 | #define E1000_GEN_POLL_TIMEOUT 640 | |
1405 | ||
1406 | /* LinkSec register fields */ | |
1407 | #define E1000_LSECTXCAP_SUM_MASK 0x00FF0000 | |
1408 | #define E1000_LSECTXCAP_SUM_SHIFT 16 | |
1409 | #define E1000_LSECRXCAP_SUM_MASK 0x00FF0000 | |
1410 | #define E1000_LSECRXCAP_SUM_SHIFT 16 | |
1411 | ||
1412 | #define E1000_LSECTXCTRL_EN_MASK 0x00000003 | |
1413 | #define E1000_LSECTXCTRL_DISABLE 0x0 | |
1414 | #define E1000_LSECTXCTRL_AUTH 0x1 | |
1415 | #define E1000_LSECTXCTRL_AUTH_ENCRYPT 0x2 | |
1416 | #define E1000_LSECTXCTRL_AISCI 0x00000020 | |
1417 | #define E1000_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 | |
1418 | #define E1000_LSECTXCTRL_RSV_MASK 0x000000D8 | |
1419 | ||
1420 | #define E1000_LSECRXCTRL_EN_MASK 0x0000000C | |
1421 | #define E1000_LSECRXCTRL_EN_SHIFT 2 | |
1422 | #define E1000_LSECRXCTRL_DISABLE 0x0 | |
1423 | #define E1000_LSECRXCTRL_CHECK 0x1 | |
1424 | #define E1000_LSECRXCTRL_STRICT 0x2 | |
1425 | #define E1000_LSECRXCTRL_DROP 0x3 | |
1426 | #define E1000_LSECRXCTRL_PLSH 0x00000040 | |
1427 | #define E1000_LSECRXCTRL_RP 0x00000080 | |
1428 | #define E1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33 | |
1429 | ||
1430 | /* Tx Rate-Scheduler Config fields */ | |
1431 | #define E1000_RTTBCNRC_RS_ENA 0x80000000 | |
1432 | #define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF | |
1433 | #define E1000_RTTBCNRC_RF_INT_SHIFT 14 | |
1434 | #define E1000_RTTBCNRC_RF_INT_MASK \ | |
1435 | (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT) | |
1436 | ||
1437 | /* DMA Coalescing register fields */ | |
1438 | /* DMA Coalescing Watchdog Timer */ | |
1439 | #define E1000_DMACR_DMACWT_MASK 0x00003FFF | |
1440 | /* DMA Coalescing Rx Threshold */ | |
1441 | #define E1000_DMACR_DMACTHR_MASK 0x00FF0000 | |
1442 | #define E1000_DMACR_DMACTHR_SHIFT 16 | |
1443 | /* Lx when no PCIe transactions */ | |
1444 | #define E1000_DMACR_DMAC_LX_MASK 0x30000000 | |
1445 | #define E1000_DMACR_DMAC_LX_SHIFT 28 | |
1446 | #define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */ | |
1447 | /* DMA Coalescing BMC-to-OS Watchdog Enable */ | |
1448 | #define E1000_DMACR_DC_BMC2OSW_EN 0x00008000 | |
1449 | ||
1450 | /* DMA Coalescing Transmit Threshold */ | |
1451 | #define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF | |
1452 | ||
1453 | #define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */ | |
1454 | ||
1455 | /* Rx Traffic Rate Threshold */ | |
1456 | #define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF | |
1457 | /* Rx packet rate in current window */ | |
1458 | #define E1000_DMCRTRH_LRPRCW 0x80000000 | |
1459 | ||
1460 | /* DMA Coal Rx Traffic Current Count */ | |
1461 | #define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF | |
1462 | ||
1463 | /* Flow ctrl Rx Threshold High val */ | |
1464 | #define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 | |
1465 | #define E1000_FCRTC_RTH_COAL_SHIFT 4 | |
1466 | /* Lx power decision based on DMA coal */ | |
1467 | #define E1000_PCIEMISC_LX_DECISION 0x00000080 | |
1468 | ||
1469 | #define E1000_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */ | |
1470 | #define E1000_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */ | |
1471 | #define E1000_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */ | |
1472 | #define I210_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */ | |
1473 | #define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */ | |
1474 | ||
1475 | ||
1476 | /* Proxy Filter Control */ | |
1477 | #define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */ | |
1478 | #define E1000_PROXYFC_EX 0x00000004 /* Directed exact proxy */ | |
1479 | #define E1000_PROXYFC_MC 0x00000008 /* Directed MC Proxy */ | |
1480 | #define E1000_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */ | |
1481 | #define E1000_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy Ena */ | |
1482 | #define E1000_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */ | |
1483 | #define E1000_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */ | |
1484 | #define E1000_PROXYFC_NS 0x00000200 /* IPv6 Neighbor Solicitation */ | |
1485 | #define E1000_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Ena */ | |
1486 | /* Proxy Status */ | |
1487 | #define E1000_PROXYS_CLEAR 0xFFFFFFFF /* Clear */ | |
1488 | ||
1489 | /* Firmware Status */ | |
1490 | #define E1000_FWSTS_FWRI 0x80000000 /* FW Reset Indication */ | |
1491 | /* VF Control */ | |
1492 | #define E1000_VTCTRL_RST 0x04000000 /* Reset VF */ | |
1493 | ||
1494 | #define E1000_STATUS_LAN_ID_MASK 0x00000000C /* Mask for Lan ID field */ | |
1495 | /* Lan ID bit field offset in status register */ | |
1496 | #define E1000_STATUS_LAN_ID_OFFSET 2 | |
1497 | #define E1000_VFTA_ENTRIES 128 | |
1498 | #ifndef E1000_UNUSEDARG | |
1499 | #define E1000_UNUSEDARG | |
1500 | #endif /* E1000_UNUSEDARG */ | |
1501 | #ifndef ERROR_REPORT | |
1502 | #define ERROR_REPORT(fmt) do { } while (0) | |
1503 | #endif /* ERROR_REPORT */ | |
1504 | #endif /* _E1000_DEFINES_H_ */ |