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1 | /****************************************************************************** |
2 | ||
3 | Copyright (c) 2001-2014, Intel Corporation | |
4 | All rights reserved. | |
5 | ||
6 | Redistribution and use in source and binary forms, with or without | |
7 | modification, are permitted provided that the following conditions are met: | |
8 | ||
9 | 1. Redistributions of source code must retain the above copyright notice, | |
10 | this list of conditions and the following disclaimer. | |
11 | ||
12 | 2. Redistributions in binary form must reproduce the above copyright | |
13 | notice, this list of conditions and the following disclaimer in the | |
14 | documentation and/or other materials provided with the distribution. | |
15 | ||
16 | 3. Neither the name of the Intel Corporation nor the names of its | |
17 | contributors may be used to endorse or promote products derived from | |
18 | this software without specific prior written permission. | |
19 | ||
20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
23 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | |
24 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
25 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
26 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
27 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
28 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
29 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
30 | POSSIBILITY OF SUCH DAMAGE. | |
31 | ||
32 | ******************************************************************************/ | |
33 | /*$FreeBSD$*/ | |
34 | ||
35 | #ifndef _E1000_OSDEP_H_ | |
36 | #define _E1000_OSDEP_H_ | |
37 | ||
38 | #include <stdint.h> | |
39 | #include <stdio.h> | |
40 | #include <stdarg.h> | |
41 | #include <string.h> | |
42 | #include <rte_common.h> | |
43 | #include <rte_cycles.h> | |
44 | #include <rte_log.h> | |
45 | #include <rte_debug.h> | |
46 | #include <rte_byteorder.h> | |
47 | ||
48 | #include "../e1000_logs.h" | |
49 | ||
50 | #define DELAY(x) rte_delay_us(x) | |
51 | #define usec_delay(x) DELAY(x) | |
52 | #define usec_delay_irq(x) DELAY(x) | |
53 | #define msec_delay(x) DELAY(1000*(x)) | |
54 | #define msec_delay_irq(x) DELAY(1000*(x)) | |
55 | ||
56 | #define DEBUGFUNC(F) DEBUGOUT(F "\n"); | |
57 | #define DEBUGOUT(S, args...) PMD_DRV_LOG_RAW(DEBUG, S, ##args) | |
58 | #define DEBUGOUT1(S, args...) DEBUGOUT(S, ##args) | |
59 | #define DEBUGOUT2(S, args...) DEBUGOUT(S, ##args) | |
60 | #define DEBUGOUT3(S, args...) DEBUGOUT(S, ##args) | |
61 | #define DEBUGOUT6(S, args...) DEBUGOUT(S, ##args) | |
62 | #define DEBUGOUT7(S, args...) DEBUGOUT(S, ##args) | |
63 | ||
64 | #define UNREFERENCED_PARAMETER(_p) | |
65 | #define UNREFERENCED_1PARAMETER(_p) | |
66 | #define UNREFERENCED_2PARAMETER(_p, _q) | |
67 | #define UNREFERENCED_3PARAMETER(_p, _q, _r) | |
68 | #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) | |
69 | ||
70 | #define FALSE 0 | |
71 | #define TRUE 1 | |
72 | ||
73 | #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */ | |
74 | ||
75 | /* Mutex used in the shared code */ | |
76 | #define E1000_MUTEX uintptr_t | |
77 | #define E1000_MUTEX_INIT(mutex) (*(mutex) = 0) | |
78 | #define E1000_MUTEX_LOCK(mutex) (*(mutex) = 1) | |
79 | #define E1000_MUTEX_UNLOCK(mutex) (*(mutex) = 0) | |
80 | ||
81 | typedef uint64_t u64; | |
82 | typedef uint32_t u32; | |
83 | typedef uint16_t u16; | |
84 | typedef uint8_t u8; | |
85 | typedef int64_t s64; | |
86 | typedef int32_t s32; | |
87 | typedef int16_t s16; | |
88 | typedef int8_t s8; | |
89 | typedef int bool; | |
90 | ||
91 | #define __le16 u16 | |
92 | #define __le32 u32 | |
93 | #define __le64 u64 | |
94 | ||
95 | #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS) | |
96 | ||
97 | #define E1000_PCI_REG(reg) (*((volatile uint32_t *)(reg))) | |
98 | ||
99 | #define E1000_PCI_REG16(reg) (*((volatile uint16_t *)(reg))) | |
100 | ||
101 | #define E1000_PCI_REG_WRITE(reg, value) do { \ | |
102 | E1000_PCI_REG((reg)) = (rte_cpu_to_le_32(value)); \ | |
103 | } while (0) | |
104 | ||
105 | #define E1000_PCI_REG_WRITE16(reg, value) do { \ | |
106 | E1000_PCI_REG16((reg)) = (rte_cpu_to_le_16(value)); \ | |
107 | } while (0) | |
108 | ||
109 | #define E1000_PCI_REG_ADDR(hw, reg) \ | |
110 | ((volatile uint32_t *)((char *)(hw)->hw_addr + (reg))) | |
111 | ||
112 | #define E1000_PCI_REG_ARRAY_ADDR(hw, reg, index) \ | |
113 | E1000_PCI_REG_ADDR((hw), (reg) + ((index) << 2)) | |
114 | ||
115 | #define E1000_PCI_REG_FLASH_ADDR(hw, reg) \ | |
116 | ((volatile uint32_t *)((char *)(hw)->flash_address + (reg))) | |
117 | ||
118 | static inline uint32_t e1000_read_addr(volatile void *addr) | |
119 | { | |
120 | return rte_le_to_cpu_32(E1000_PCI_REG(addr)); | |
121 | } | |
122 | ||
123 | static inline uint16_t e1000_read_addr16(volatile void *addr) | |
124 | { | |
125 | return rte_le_to_cpu_16(E1000_PCI_REG16(addr)); | |
126 | } | |
127 | ||
128 | /* Necessary defines */ | |
129 | #define E1000_MRQC_ENABLE_MASK 0x00000007 | |
130 | #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 | |
131 | #define E1000_ALL_FULL_DUPLEX ( \ | |
132 | ADVERTISE_10_FULL | ADVERTISE_100_FULL | ADVERTISE_1000_FULL) | |
133 | ||
134 | #define M88E1543_E_PHY_ID 0x01410EA0 | |
135 | #define ULP_SUPPORT | |
136 | ||
137 | #define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ | |
138 | #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 | |
139 | ||
140 | /* Register READ/WRITE macros */ | |
141 | ||
142 | #define E1000_READ_REG(hw, reg) \ | |
143 | e1000_read_addr(E1000_PCI_REG_ADDR((hw), (reg))) | |
144 | ||
145 | #define E1000_WRITE_REG(hw, reg, value) \ | |
146 | E1000_PCI_REG_WRITE(E1000_PCI_REG_ADDR((hw), (reg)), (value)) | |
147 | ||
148 | #define E1000_READ_REG_ARRAY(hw, reg, index) \ | |
149 | E1000_PCI_REG(E1000_PCI_REG_ARRAY_ADDR((hw), (reg), (index))) | |
150 | ||
151 | #define E1000_WRITE_REG_ARRAY(hw, reg, index, value) \ | |
152 | E1000_PCI_REG_WRITE(E1000_PCI_REG_ARRAY_ADDR((hw), (reg), (index)), (value)) | |
153 | ||
154 | #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY | |
155 | #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY | |
156 | ||
157 | #define E1000_ACCESS_PANIC(x, hw, reg, value) \ | |
158 | rte_panic("%s:%u\t" RTE_STR(x) "(%p, 0x%x, 0x%x)", \ | |
159 | __FILE__, __LINE__, (hw), (reg), (unsigned int)(value)) | |
160 | ||
161 | /* | |
162 | * To be able to do IO write, we need to map IO BAR | |
163 | * (bar 2/4 depending on device). | |
164 | * Right now mapping multiple BARs is not supported by DPDK. | |
165 | * Fortunatelly we need it only for legacy hw support. | |
166 | */ | |
167 | ||
168 | #define E1000_WRITE_REG_IO(hw, reg, value) \ | |
169 | E1000_WRITE_REG(hw, reg, value) | |
170 | ||
171 | /* | |
172 | * Tested on I217/I218 chipset. | |
173 | */ | |
174 | ||
175 | #define E1000_READ_FLASH_REG(hw, reg) \ | |
176 | e1000_read_addr(E1000_PCI_REG_FLASH_ADDR((hw), (reg))) | |
177 | ||
178 | #define E1000_READ_FLASH_REG16(hw, reg) \ | |
179 | e1000_read_addr16(E1000_PCI_REG_FLASH_ADDR((hw), (reg))) | |
180 | ||
181 | #define E1000_WRITE_FLASH_REG(hw, reg, value) \ | |
182 | E1000_PCI_REG_WRITE(E1000_PCI_REG_FLASH_ADDR((hw), (reg)), (value)) | |
183 | ||
184 | #define E1000_WRITE_FLASH_REG16(hw, reg, value) \ | |
185 | E1000_PCI_REG_WRITE16(E1000_PCI_REG_FLASH_ADDR((hw), (reg)), (value)) | |
186 | ||
187 | #define STATIC static | |
188 | ||
189 | #ifndef ETH_ADDR_LEN | |
190 | #define ETH_ADDR_LEN 6 | |
191 | #endif | |
192 | ||
193 | #define false FALSE | |
194 | #define true TRUE | |
195 | ||
196 | #endif /* _E1000_OSDEP_H_ */ |