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1 | /*- |
2 | * BSD LICENSE | |
3 | * | |
4 | * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. | |
5 | * All rights reserved. | |
6 | * | |
7 | * Redistribution and use in source and binary forms, with or without | |
8 | * modification, are permitted provided that the following conditions | |
9 | * are met: | |
10 | * | |
11 | * * Redistributions of source code must retain the above copyright | |
12 | * notice, this list of conditions and the following disclaimer. | |
13 | * * Redistributions in binary form must reproduce the above copyright | |
14 | * notice, this list of conditions and the following disclaimer in | |
15 | * the documentation and/or other materials provided with the | |
16 | * distribution. | |
17 | * * Neither the name of Intel Corporation nor the names of its | |
18 | * contributors may be used to endorse or promote products derived | |
19 | * from this software without specific prior written permission. | |
20 | * | |
21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
22 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
23 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
24 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
25 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
26 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
27 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
28 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
29 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | */ | |
33 | ||
34 | #ifndef _I40E_ETHDEV_H_ | |
35 | #define _I40E_ETHDEV_H_ | |
36 | ||
37 | #include <rte_eth_ctrl.h> | |
38 | #include <rte_time.h> | |
39 | #include <rte_kvargs.h> | |
40 | ||
41 | #define I40E_VLAN_TAG_SIZE 4 | |
42 | ||
43 | #define I40E_AQ_LEN 32 | |
44 | #define I40E_AQ_BUF_SZ 4096 | |
45 | /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */ | |
46 | #define I40E_MAX_Q_PER_TC 64 | |
47 | #define I40E_NUM_DESC_DEFAULT 512 | |
48 | #define I40E_NUM_DESC_ALIGN 32 | |
49 | #define I40E_BUF_SIZE_MIN 1024 | |
50 | #define I40E_FRAME_SIZE_MAX 9728 | |
51 | #define I40E_QUEUE_BASE_ADDR_UNIT 128 | |
52 | /* number of VSIs and queue default setting */ | |
53 | #define I40E_MAX_QP_NUM_PER_VF 16 | |
54 | #define I40E_DEFAULT_QP_NUM_FDIR 1 | |
55 | #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t)) | |
56 | #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE) | |
57 | /* Maximun number of MAC addresses */ | |
58 | #define I40E_NUM_MACADDR_MAX 64 | |
59 | /* Maximum number of VFs */ | |
60 | #define I40E_MAX_VF 128 | |
61 | ||
62 | /* | |
63 | * vlan_id is a 12 bit number. | |
64 | * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. | |
65 | * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element. | |
66 | * The higher 7 bit val specifies VFTA array index. | |
67 | */ | |
68 | #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F)) | |
69 | #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5) | |
70 | ||
71 | /* Default TC traffic in case DCB is not enabled */ | |
72 | #define I40E_DEFAULT_TCMAP 0x1 | |
73 | #define I40E_FDIR_QUEUE_ID 0 | |
74 | ||
75 | /* Always assign pool 0 to main VSI, VMDQ will start from 1 */ | |
76 | #define I40E_VMDQ_POOL_BASE 1 | |
77 | ||
78 | #define I40E_DEFAULT_RX_FREE_THRESH 32 | |
79 | #define I40E_DEFAULT_RX_PTHRESH 8 | |
80 | #define I40E_DEFAULT_RX_HTHRESH 8 | |
81 | #define I40E_DEFAULT_RX_WTHRESH 0 | |
82 | ||
83 | #define I40E_DEFAULT_TX_FREE_THRESH 32 | |
84 | #define I40E_DEFAULT_TX_PTHRESH 32 | |
85 | #define I40E_DEFAULT_TX_HTHRESH 0 | |
86 | #define I40E_DEFAULT_TX_WTHRESH 0 | |
87 | #define I40E_DEFAULT_TX_RSBIT_THRESH 32 | |
88 | ||
89 | /* Bit shift and mask */ | |
90 | #define I40E_4_BIT_WIDTH (CHAR_BIT / 2) | |
91 | #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t) | |
92 | #define I40E_8_BIT_WIDTH CHAR_BIT | |
93 | #define I40E_8_BIT_MASK UINT8_MAX | |
94 | #define I40E_16_BIT_WIDTH (CHAR_BIT * 2) | |
95 | #define I40E_16_BIT_MASK UINT16_MAX | |
96 | #define I40E_32_BIT_WIDTH (CHAR_BIT * 4) | |
97 | #define I40E_32_BIT_MASK UINT32_MAX | |
98 | #define I40E_48_BIT_WIDTH (CHAR_BIT * 6) | |
99 | #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t) | |
100 | ||
101 | /* Linux PF host with virtchnl version 1.1 */ | |
102 | #define PF_IS_V11(vf) \ | |
103 | (((vf)->version_major == I40E_VIRTCHNL_VERSION_MAJOR) && \ | |
104 | ((vf)->version_minor == 1)) | |
105 | ||
106 | /* index flex payload per layer */ | |
107 | enum i40e_flxpld_layer_idx { | |
108 | I40E_FLXPLD_L2_IDX = 0, | |
109 | I40E_FLXPLD_L3_IDX = 1, | |
110 | I40E_FLXPLD_L4_IDX = 2, | |
111 | I40E_MAX_FLXPLD_LAYER = 3, | |
112 | }; | |
113 | #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */ | |
114 | #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */ | |
115 | #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */ | |
116 | #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */ | |
117 | #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */ | |
118 | ||
119 | /* i40e flags */ | |
120 | #define I40E_FLAG_RSS (1ULL << 0) | |
121 | #define I40E_FLAG_DCB (1ULL << 1) | |
122 | #define I40E_FLAG_VMDQ (1ULL << 2) | |
123 | #define I40E_FLAG_SRIOV (1ULL << 3) | |
124 | #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4) | |
125 | #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5) | |
126 | #define I40E_FLAG_FDIR (1ULL << 6) | |
127 | #define I40E_FLAG_VXLAN (1ULL << 7) | |
128 | #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8) | |
129 | #define I40E_FLAG_ALL (I40E_FLAG_RSS | \ | |
130 | I40E_FLAG_DCB | \ | |
131 | I40E_FLAG_VMDQ | \ | |
132 | I40E_FLAG_SRIOV | \ | |
133 | I40E_FLAG_HEADER_SPLIT_DISABLED | \ | |
134 | I40E_FLAG_HEADER_SPLIT_ENABLED | \ | |
135 | I40E_FLAG_FDIR | \ | |
136 | I40E_FLAG_VXLAN | \ | |
137 | I40E_FLAG_RSS_AQ_CAPABLE) | |
138 | ||
139 | #define I40E_RSS_OFFLOAD_ALL ( \ | |
140 | ETH_RSS_FRAG_IPV4 | \ | |
141 | ETH_RSS_NONFRAG_IPV4_TCP | \ | |
142 | ETH_RSS_NONFRAG_IPV4_UDP | \ | |
143 | ETH_RSS_NONFRAG_IPV4_SCTP | \ | |
144 | ETH_RSS_NONFRAG_IPV4_OTHER | \ | |
145 | ETH_RSS_FRAG_IPV6 | \ | |
146 | ETH_RSS_NONFRAG_IPV6_TCP | \ | |
147 | ETH_RSS_NONFRAG_IPV6_UDP | \ | |
148 | ETH_RSS_NONFRAG_IPV6_SCTP | \ | |
149 | ETH_RSS_NONFRAG_IPV6_OTHER | \ | |
150 | ETH_RSS_L2_PAYLOAD) | |
151 | ||
152 | /* All bits of RSS hash enable for X722*/ | |
153 | #define I40E_RSS_HENA_ALL_X722 ( \ | |
154 | (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ | |
155 | (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ | |
156 | (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ | |
157 | (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ | |
158 | (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \ | |
159 | (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \ | |
160 | I40E_RSS_HENA_ALL) | |
161 | ||
162 | /* All bits of RSS hash enable */ | |
163 | #define I40E_RSS_HENA_ALL ( \ | |
164 | (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ | |
165 | (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ | |
166 | (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ | |
167 | (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ | |
168 | (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \ | |
169 | (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ | |
170 | (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ | |
171 | (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ | |
172 | (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ | |
173 | (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \ | |
174 | (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \ | |
175 | (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \ | |
176 | (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \ | |
177 | (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD)) | |
178 | ||
179 | #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET | |
180 | #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET | |
181 | ||
182 | /* Default queue interrupt throttling time in microseconds */ | |
183 | #define I40E_ITR_INDEX_DEFAULT 0 | |
184 | #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ | |
185 | #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */ | |
186 | ||
187 | /* Special FW support this floating VEB feature */ | |
188 | #define FLOATING_VEB_SUPPORTED_FW_MAJ 5 | |
189 | #define FLOATING_VEB_SUPPORTED_FW_MIN 0 | |
190 | ||
191 | struct i40e_adapter; | |
192 | ||
193 | /** | |
194 | * MAC filter structure | |
195 | */ | |
196 | struct i40e_mac_filter_info { | |
197 | enum rte_mac_filter_type filter_type; | |
198 | struct ether_addr mac_addr; | |
199 | }; | |
200 | ||
201 | TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter); | |
202 | ||
203 | /* MAC filter list structure */ | |
204 | struct i40e_mac_filter { | |
205 | TAILQ_ENTRY(i40e_mac_filter) next; | |
206 | struct i40e_mac_filter_info mac_info; | |
207 | }; | |
208 | ||
209 | TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list); | |
210 | ||
211 | struct i40e_vsi; | |
212 | ||
213 | /* VSI list structure */ | |
214 | struct i40e_vsi_list { | |
215 | TAILQ_ENTRY(i40e_vsi_list) list; | |
216 | struct i40e_vsi *vsi; | |
217 | }; | |
218 | ||
219 | struct i40e_rx_queue; | |
220 | struct i40e_tx_queue; | |
221 | ||
222 | /* Bandwidth limit information */ | |
223 | struct i40e_bw_info { | |
224 | uint16_t bw_limit; /* BW Limit (0 = disabled) */ | |
225 | uint8_t bw_max; /* Max BW limit if enabled */ | |
226 | ||
227 | /* Relative credits within same TC with respect to other VSIs or Comps */ | |
228 | uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; | |
229 | /* Bandwidth limit per TC */ | |
230 | uint8_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS]; | |
231 | /* Max bandwidth limit per TC */ | |
232 | uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS]; | |
233 | }; | |
234 | ||
235 | /* Structure that defines a VEB */ | |
236 | struct i40e_veb { | |
237 | struct i40e_vsi_list_head head; | |
238 | struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */ | |
239 | struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */ | |
240 | uint16_t seid; /* The seid of VEB itself */ | |
241 | uint16_t uplink_seid; /* The uplink seid of this VEB */ | |
242 | uint16_t stats_idx; | |
243 | struct i40e_eth_stats stats; | |
244 | uint8_t enabled_tc; /* The traffic class enabled */ | |
245 | struct i40e_bw_info bw_info; /* VEB bandwidth information */ | |
246 | }; | |
247 | ||
248 | /* i40e MACVLAN filter structure */ | |
249 | struct i40e_macvlan_filter { | |
250 | struct ether_addr macaddr; | |
251 | enum rte_mac_filter_type filter_type; | |
252 | uint16_t vlan_id; | |
253 | }; | |
254 | ||
255 | /* | |
256 | * Structure that defines a VSI, associated with a adapter. | |
257 | */ | |
258 | struct i40e_vsi { | |
259 | struct i40e_adapter *adapter; /* Backreference to associated adapter */ | |
260 | struct i40e_aqc_vsi_properties_data info; /* VSI properties */ | |
261 | ||
262 | struct i40e_eth_stats eth_stats_offset; | |
263 | struct i40e_eth_stats eth_stats; | |
264 | /* | |
265 | * When drivers loaded, only a default main VSI exists. In case new VSI | |
266 | * needs to add, HW needs to know the layout that VSIs are organized. | |
267 | * Besides that, VSI isan element and can't switch packets, which needs | |
268 | * to add new component VEB to perform switching. So, a new VSI needs | |
269 | * to specify the the uplink VSI (Parent VSI) before created. The | |
270 | * uplink VSI will check whether it had a VEB to switch packets. If no, | |
271 | * it will try to create one. Then, uplink VSI will move the new VSI | |
272 | * into its' sib_vsi_list to manage all the downlink VSI. | |
273 | * sib_vsi_list: the VSI list that shared the same uplink VSI. | |
274 | * parent_vsi : the uplink VSI. It's NULL for main VSI. | |
275 | * veb : the VEB associates with the VSI. | |
276 | */ | |
277 | struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */ | |
278 | struct i40e_vsi *parent_vsi; | |
279 | struct i40e_veb *veb; /* Associated veb, could be null */ | |
280 | struct i40e_veb *floating_veb; /* Associated floating veb */ | |
281 | bool offset_loaded; | |
282 | enum i40e_vsi_type type; /* VSI types */ | |
283 | uint16_t vlan_num; /* Total VLAN number */ | |
284 | uint16_t mac_num; /* Total mac number */ | |
285 | uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */ | |
286 | struct i40e_mac_filter_list mac_list; /* macvlan filter list */ | |
287 | /* specific VSI-defined parameters, SRIOV stored the vf_id */ | |
288 | uint32_t user_param; | |
289 | uint16_t seid; /* The seid of VSI itself */ | |
290 | uint16_t uplink_seid; /* The uplink seid of this VSI */ | |
291 | uint16_t nb_qps; /* Number of queue pairs VSI can occupy */ | |
292 | uint16_t nb_used_qps; /* Number of queue pairs VSI uses */ | |
293 | uint16_t max_macaddrs; /* Maximum number of MAC addresses */ | |
294 | uint16_t base_queue; /* The first queue index of this VSI */ | |
295 | /* | |
296 | * The offset to visit VSI related register, assigned by HW when | |
297 | * creating VSI | |
298 | */ | |
299 | uint16_t vsi_id; | |
300 | uint16_t msix_intr; /* The MSIX interrupt binds to VSI */ | |
301 | uint16_t nb_msix; /* The max number of msix vector */ | |
302 | uint8_t enabled_tc; /* The traffic class enabled */ | |
303 | struct i40e_bw_info bw_info; /* VSI bandwidth information */ | |
304 | }; | |
305 | ||
306 | struct pool_entry { | |
307 | LIST_ENTRY(pool_entry) next; | |
308 | uint16_t base; | |
309 | uint16_t len; | |
310 | }; | |
311 | ||
312 | LIST_HEAD(res_list, pool_entry); | |
313 | ||
314 | struct i40e_res_pool_info { | |
315 | uint32_t base; /* Resource start index */ | |
316 | uint32_t num_alloc; /* Allocated resource number */ | |
317 | uint32_t num_free; /* Total available resource number */ | |
318 | struct res_list alloc_list; /* Allocated resource list */ | |
319 | struct res_list free_list; /* Available resource list */ | |
320 | }; | |
321 | ||
322 | enum I40E_VF_STATE { | |
323 | I40E_VF_INACTIVE = 0, | |
324 | I40E_VF_INRESET, | |
325 | I40E_VF_ININIT, | |
326 | I40E_VF_ACTIVE, | |
327 | }; | |
328 | ||
329 | /* | |
330 | * Structure to store private data for PF host. | |
331 | */ | |
332 | struct i40e_pf_vf { | |
333 | struct i40e_pf *pf; | |
334 | struct i40e_vsi *vsi; | |
335 | enum I40E_VF_STATE state; /* The number of queue pairs availiable */ | |
336 | uint16_t vf_idx; /* VF index in pf->vfs */ | |
337 | uint16_t lan_nb_qps; /* Actual queues allocated */ | |
338 | uint16_t reset_cnt; /* Total vf reset times */ | |
339 | struct ether_addr mac_addr; /* Default MAC address */ | |
340 | }; | |
341 | ||
342 | /* | |
343 | * Structure to store private data for flow control. | |
344 | */ | |
345 | struct i40e_fc_conf { | |
346 | uint16_t pause_time; /* Flow control pause timer */ | |
347 | /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */ | |
348 | uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1]; | |
349 | /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */ | |
350 | uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1]; | |
351 | }; | |
352 | ||
353 | /* | |
354 | * Structure to store private data for VMDQ instance | |
355 | */ | |
356 | struct i40e_vmdq_info { | |
357 | struct i40e_pf *pf; | |
358 | struct i40e_vsi *vsi; | |
359 | }; | |
360 | ||
361 | /* | |
362 | * Structure to store flex pit for flow diretor. | |
363 | */ | |
364 | struct i40e_fdir_flex_pit { | |
365 | uint8_t src_offset; /* offset in words from the beginning of payload */ | |
366 | uint8_t size; /* size in words */ | |
367 | uint8_t dst_offset; /* offset in words of flexible payload */ | |
368 | }; | |
369 | ||
370 | struct i40e_fdir_flex_mask { | |
371 | uint8_t word_mask; /**< Bit i enables word i of flexible payload */ | |
372 | struct { | |
373 | uint8_t offset; | |
374 | uint16_t mask; | |
375 | } bitmask[I40E_FDIR_BITMASK_NUM_WORD]; | |
376 | }; | |
377 | ||
378 | #define I40E_FILTER_PCTYPE_MAX 64 | |
379 | /* | |
380 | * A structure used to define fields of a FDIR related info. | |
381 | */ | |
382 | struct i40e_fdir_info { | |
383 | struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */ | |
384 | uint16_t match_counter_index; /* Statistic counter index used for fdir*/ | |
385 | struct i40e_tx_queue *txq; | |
386 | struct i40e_rx_queue *rxq; | |
387 | void *prg_pkt; /* memory for fdir program packet */ | |
388 | uint64_t dma_addr; /* physic address of packet memory*/ | |
389 | /* input set bits for each pctype */ | |
390 | uint64_t input_set[I40E_FILTER_PCTYPE_MAX]; | |
391 | /* | |
392 | * the rule how bytes stream is extracted as flexible payload | |
393 | * for each payload layer, the setting can up to three elements | |
394 | */ | |
395 | struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED]; | |
396 | struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX]; | |
397 | }; | |
398 | ||
399 | #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64 | |
400 | #define I40E_MAX_MIRROR_RULES 64 | |
401 | /* | |
402 | * Mirror rule structure | |
403 | */ | |
404 | struct i40e_mirror_rule { | |
405 | TAILQ_ENTRY(i40e_mirror_rule) rules; | |
406 | uint8_t rule_type; | |
407 | uint16_t index; /* the sw index of mirror rule */ | |
408 | uint16_t id; /* the rule id assigned by firmware */ | |
409 | uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */ | |
410 | uint16_t num_entries; | |
411 | /* the info stores depend on the rule type. | |
412 | If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here. | |
413 | If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored. | |
414 | */ | |
415 | uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE]; | |
416 | }; | |
417 | ||
418 | TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule); | |
419 | ||
420 | /* | |
421 | * Structure to store private data specific for PF instance. | |
422 | */ | |
423 | struct i40e_pf { | |
424 | struct i40e_adapter *adapter; /* The adapter this PF associate to */ | |
425 | struct i40e_vsi *main_vsi; /* pointer to main VSI structure */ | |
426 | uint16_t mac_seid; /* The seid of the MAC of this PF */ | |
427 | uint16_t main_vsi_seid; /* The seid of the main VSI */ | |
428 | uint16_t max_num_vsi; | |
429 | struct i40e_res_pool_info qp_pool; /*Queue pair pool */ | |
430 | struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */ | |
431 | ||
432 | struct i40e_hw_port_stats stats_offset; | |
433 | struct i40e_hw_port_stats stats; | |
434 | bool offset_loaded; | |
435 | ||
436 | struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ | |
437 | struct ether_addr dev_addr; /* PF device mac address */ | |
438 | uint64_t flags; /* PF feature flags */ | |
439 | /* All kinds of queue pair setting for different VSIs */ | |
440 | struct i40e_pf_vf *vfs; | |
441 | uint16_t vf_num; | |
442 | /* Each of below queue pairs should be power of 2 since it's the | |
443 | precondition after TC configuration applied */ | |
444 | uint16_t lan_nb_qp_max; | |
445 | uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ | |
446 | uint16_t lan_qp_offset; | |
447 | uint16_t vmdq_nb_qp_max; | |
448 | uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */ | |
449 | uint16_t vmdq_qp_offset; | |
450 | uint16_t vf_nb_qp_max; | |
451 | uint16_t vf_nb_qps; /* The number of queue pairs of VF */ | |
452 | uint16_t vf_qp_offset; | |
453 | uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */ | |
454 | uint16_t fdir_qp_offset; | |
455 | ||
456 | uint16_t hash_lut_size; /* The size of hash lookup table */ | |
457 | /* input set bits for each pctype */ | |
458 | uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX]; | |
459 | /* store VXLAN UDP ports */ | |
460 | uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; | |
461 | uint16_t vxlan_bitmap; /* Vxlan bit mask */ | |
462 | ||
463 | /* VMDQ related info */ | |
464 | uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */ | |
465 | uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */ | |
466 | struct i40e_vmdq_info *vmdq; | |
467 | ||
468 | struct i40e_fdir_info fdir; /* flow director info */ | |
469 | struct i40e_fc_conf fc_conf; /* Flow control conf */ | |
470 | struct i40e_mirror_rule_list mirror_list; | |
471 | uint16_t nb_mirror_rule; /* The number of mirror rules */ | |
472 | bool floating_veb; /* The flag to use the floating VEB */ | |
473 | /* The floating enable flag for the specific VF */ | |
474 | bool floating_veb_list[I40E_MAX_VF]; | |
475 | }; | |
476 | ||
477 | enum pending_msg { | |
478 | PFMSG_LINK_CHANGE = 0x1, | |
479 | PFMSG_RESET_IMPENDING = 0x2, | |
480 | PFMSG_DRIVER_CLOSE = 0x4, | |
481 | }; | |
482 | ||
483 | struct i40e_vsi_vlan_pvid_info { | |
484 | uint16_t on; /* Enable or disable pvid */ | |
485 | union { | |
486 | uint16_t pvid; /* Valid in case 'on' is set to set pvid */ | |
487 | struct { | |
488 | /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets, | |
489 | * while 'untagged' will reject untagged packets. | |
490 | */ | |
491 | uint8_t tagged; | |
492 | uint8_t untagged; | |
493 | } reject; | |
494 | } config; | |
495 | }; | |
496 | ||
497 | struct i40e_vf_rx_queues { | |
498 | uint64_t rx_dma_addr; | |
499 | uint32_t rx_ring_len; | |
500 | uint32_t buff_size; | |
501 | }; | |
502 | ||
503 | struct i40e_vf_tx_queues { | |
504 | uint64_t tx_dma_addr; | |
505 | uint32_t tx_ring_len; | |
506 | }; | |
507 | ||
508 | /* | |
509 | * Structure to store private data specific for VF instance. | |
510 | */ | |
511 | struct i40e_vf { | |
512 | struct i40e_adapter *adapter; /* The adapter this VF associate to */ | |
513 | struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ | |
514 | uint16_t num_queue_pairs; | |
515 | uint16_t max_pkt_len; /* Maximum packet length */ | |
516 | bool promisc_unicast_enabled; | |
517 | bool promisc_multicast_enabled; | |
518 | ||
519 | uint32_t version_major; /* Major version number */ | |
520 | uint32_t version_minor; /* Minor version number */ | |
521 | uint16_t promisc_flags; /* Promiscuous setting */ | |
522 | uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */ | |
523 | ||
524 | /* Event from pf */ | |
525 | bool dev_closed; | |
526 | bool link_up; | |
527 | enum i40e_aq_link_speed link_speed; | |
528 | bool vf_reset; | |
529 | volatile uint32_t pend_cmd; /* pending command not finished yet */ | |
530 | uint32_t cmd_retval; /* return value of the cmd response from PF */ | |
531 | u16 pend_msg; /* flags indicates events from pf not handled yet */ | |
532 | uint8_t *aq_resp; /* buffer to store the adminq response from PF */ | |
533 | ||
534 | /* VSI info */ | |
535 | struct i40e_virtchnl_vf_resource *vf_res; /* All VSIs */ | |
536 | struct i40e_virtchnl_vsi_resource *vsi_res; /* LAN VSI */ | |
537 | struct i40e_vsi vsi; | |
538 | uint64_t flags; | |
539 | }; | |
540 | ||
541 | /* | |
542 | * Structure to store private data for each PF/VF instance. | |
543 | */ | |
544 | struct i40e_adapter { | |
545 | /* Common for both PF and VF */ | |
546 | struct i40e_hw hw; | |
547 | struct rte_eth_dev *eth_dev; | |
548 | ||
549 | /* Specific for PF or VF */ | |
550 | union { | |
551 | struct i40e_pf pf; | |
552 | struct i40e_vf vf; | |
553 | }; | |
554 | ||
555 | /* For vector PMD */ | |
556 | bool rx_bulk_alloc_allowed; | |
557 | bool rx_vec_allowed; | |
558 | bool tx_simple_allowed; | |
559 | bool tx_vec_allowed; | |
560 | ||
561 | /* For PTP */ | |
562 | struct rte_timecounter systime_tc; | |
563 | struct rte_timecounter rx_tstamp_tc; | |
564 | struct rte_timecounter tx_tstamp_tc; | |
565 | }; | |
566 | ||
567 | int i40e_dev_switch_queues(struct i40e_pf *pf, bool on); | |
568 | int i40e_vsi_release(struct i40e_vsi *vsi); | |
569 | struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, | |
570 | enum i40e_vsi_type type, | |
571 | struct i40e_vsi *uplink_vsi, | |
572 | uint16_t user_param); | |
573 | int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); | |
574 | int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on); | |
575 | int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan); | |
576 | int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan); | |
577 | int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter); | |
578 | int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr); | |
579 | void i40e_update_vsi_stats(struct i40e_vsi *vsi); | |
580 | void i40e_pf_disable_irq0(struct i40e_hw *hw); | |
581 | void i40e_pf_enable_irq0(struct i40e_hw *hw); | |
582 | int i40e_dev_link_update(struct rte_eth_dev *dev, | |
583 | __rte_unused int wait_to_complete); | |
584 | void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi); | |
585 | void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi); | |
586 | int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi, | |
587 | struct i40e_vsi_vlan_pvid_info *info); | |
588 | int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on); | |
589 | int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on); | |
590 | uint64_t i40e_config_hena(uint64_t flags, enum i40e_mac_type type); | |
591 | uint64_t i40e_parse_hena(uint64_t flags); | |
592 | enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf); | |
593 | enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf); | |
594 | int i40e_fdir_setup(struct i40e_pf *pf); | |
595 | const struct rte_memzone *i40e_memzone_reserve(const char *name, | |
596 | uint32_t len, | |
597 | int socket_id); | |
598 | int i40e_fdir_configure(struct rte_eth_dev *dev); | |
599 | void i40e_fdir_teardown(struct i40e_pf *pf); | |
600 | enum i40e_filter_pctype i40e_flowtype_to_pctype(uint16_t flow_type); | |
601 | uint16_t i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype); | |
602 | int i40e_fdir_ctrl_func(struct rte_eth_dev *dev, | |
603 | enum rte_filter_op filter_op, | |
604 | void *arg); | |
605 | int i40e_select_filter_input_set(struct i40e_hw *hw, | |
606 | struct rte_eth_input_set_conf *conf, | |
607 | enum rte_filter_type filter); | |
608 | int i40e_hash_filter_inset_select(struct i40e_hw *hw, | |
609 | struct rte_eth_input_set_conf *conf); | |
610 | int i40e_fdir_filter_inset_select(struct i40e_pf *pf, | |
611 | struct rte_eth_input_set_conf *conf); | |
612 | int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode, | |
613 | uint32_t retval, uint8_t *msg, | |
614 | uint16_t msglen); | |
615 | void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, | |
616 | struct rte_eth_rxq_info *qinfo); | |
617 | void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, | |
618 | struct rte_eth_txq_info *qinfo); | |
619 | ||
620 | /* I40E_DEV_PRIVATE_TO */ | |
621 | #define I40E_DEV_PRIVATE_TO_PF(adapter) \ | |
622 | (&((struct i40e_adapter *)adapter)->pf) | |
623 | #define I40E_DEV_PRIVATE_TO_HW(adapter) \ | |
624 | (&((struct i40e_adapter *)adapter)->hw) | |
625 | #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \ | |
626 | ((struct i40e_adapter *)adapter) | |
627 | ||
628 | /* I40EVF_DEV_PRIVATE_TO */ | |
629 | #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \ | |
630 | (&((struct i40e_adapter *)adapter)->vf) | |
631 | ||
632 | static inline struct i40e_vsi * | |
633 | i40e_get_vsi_from_adapter(struct i40e_adapter *adapter) | |
634 | { | |
635 | struct i40e_hw *hw; | |
636 | ||
637 | if (!adapter) | |
638 | return NULL; | |
639 | ||
640 | hw = I40E_DEV_PRIVATE_TO_HW(adapter); | |
641 | if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) { | |
642 | struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter); | |
643 | return &vf->vsi; | |
644 | } else { | |
645 | struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter); | |
646 | return pf->main_vsi; | |
647 | } | |
648 | } | |
649 | #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \ | |
650 | i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter) | |
651 | ||
652 | /* I40E_VSI_TO */ | |
653 | #define I40E_VSI_TO_HW(vsi) \ | |
654 | (&(((struct i40e_vsi *)vsi)->adapter->hw)) | |
655 | #define I40E_VSI_TO_PF(vsi) \ | |
656 | (&(((struct i40e_vsi *)vsi)->adapter->pf)) | |
657 | #define I40E_VSI_TO_VF(vsi) \ | |
658 | (&(((struct i40e_vsi *)vsi)->adapter->vf)) | |
659 | #define I40E_VSI_TO_DEV_DATA(vsi) \ | |
660 | (((struct i40e_vsi *)vsi)->adapter->pf.dev_data) | |
661 | #define I40E_VSI_TO_ETH_DEV(vsi) \ | |
662 | (((struct i40e_vsi *)vsi)->adapter->eth_dev) | |
663 | ||
664 | /* I40E_PF_TO */ | |
665 | #define I40E_PF_TO_HW(pf) \ | |
666 | (&(((struct i40e_pf *)pf)->adapter->hw)) | |
667 | #define I40E_PF_TO_ADAPTER(pf) \ | |
668 | ((struct i40e_adapter *)pf->adapter) | |
669 | ||
670 | /* I40E_VF_TO */ | |
671 | #define I40E_VF_TO_HW(vf) \ | |
672 | (&(((struct i40e_vf *)vf)->adapter->hw)) | |
673 | ||
674 | static inline void | |
675 | i40e_init_adminq_parameter(struct i40e_hw *hw) | |
676 | { | |
677 | hw->aq.num_arq_entries = I40E_AQ_LEN; | |
678 | hw->aq.num_asq_entries = I40E_AQ_LEN; | |
679 | hw->aq.arq_buf_size = I40E_AQ_BUF_SZ; | |
680 | hw->aq.asq_buf_size = I40E_AQ_BUF_SZ; | |
681 | } | |
682 | ||
683 | static inline int | |
684 | i40e_align_floor(int n) | |
685 | { | |
686 | if (n == 0) | |
687 | return 0; | |
688 | return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)); | |
689 | } | |
690 | ||
691 | static inline uint16_t | |
692 | i40e_calc_itr_interval(int16_t interval) | |
693 | { | |
694 | if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX) | |
695 | interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT; | |
696 | ||
697 | /* Convert to hardware count, as writing each 1 represents 2 us */ | |
698 | return interval / 2; | |
699 | } | |
700 | ||
701 | #define I40E_VALID_FLOW(flow_type) \ | |
702 | ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \ | |
703 | (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \ | |
704 | (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \ | |
705 | (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \ | |
706 | (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \ | |
707 | (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \ | |
708 | (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \ | |
709 | (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \ | |
710 | (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \ | |
711 | (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \ | |
712 | (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD) | |
713 | ||
714 | #define I40E_VALID_PCTYPE_X722(pctype) \ | |
715 | ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ | |
716 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ | |
717 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \ | |
718 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ | |
719 | (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \ | |
720 | (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \ | |
721 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ | |
722 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ | |
723 | (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ | |
724 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ | |
725 | (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \ | |
726 | (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \ | |
727 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ | |
728 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \ | |
729 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ | |
730 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ | |
731 | (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) | |
732 | ||
733 | #define I40E_VALID_PCTYPE(pctype) \ | |
734 | ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \ | |
735 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \ | |
736 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \ | |
737 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \ | |
738 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \ | |
739 | (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \ | |
740 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \ | |
741 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ | |
742 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ | |
743 | (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ | |
744 | (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) | |
745 | ||
746 | #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \ | |
747 | (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \ | |
748 | ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \ | |
749 | ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \ | |
750 | ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \ | |
751 | ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \ | |
752 | ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4)) | |
753 | ||
754 | #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \ | |
755 | (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \ | |
756 | ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \ | |
757 | ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \ | |
758 | ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR)) | |
759 | ||
760 | #endif /* _I40E_ETHDEV_H_ */ |