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[ceph.git] / ceph / src / dpdk / drivers / net / ixgbe / ixgbe_ethdev.c
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7c673cae
FG		 1/*-
2 * BSD LICENSE
3 *
4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <sys/queue.h>
35#include <stdio.h>
36#include <errno.h>
37#include <stdint.h>
38#include <string.h>
39#include <unistd.h>
40#include <stdarg.h>
41#include <inttypes.h>
42#include <netinet/in.h>
43#include <rte_byteorder.h>
44#include <rte_common.h>
45#include <rte_cycles.h>
46
47#include <rte_interrupts.h>
48#include <rte_log.h>
49#include <rte_debug.h>
50#include <rte_pci.h>
51#include <rte_atomic.h>
52#include <rte_branch_prediction.h>
53#include <rte_memory.h>
54#include <rte_memzone.h>
55#include <rte_eal.h>
56#include <rte_alarm.h>
57#include <rte_ether.h>
58#include <rte_ethdev.h>
59#include <rte_atomic.h>
60#include <rte_malloc.h>
61#include <rte_random.h>
62#include <rte_dev.h>
63
64#include "ixgbe_logs.h"
65#include "base/ixgbe_api.h"
66#include "base/ixgbe_vf.h"
67#include "base/ixgbe_common.h"
68#include "ixgbe_ethdev.h"
69#include "ixgbe_bypass.h"
70#include "ixgbe_rxtx.h"
71#include "base/ixgbe_type.h"
72#include "base/ixgbe_phy.h"
73#include "ixgbe_regs.h"
74
75#include "rte_pmd_ixgbe.h"
76
77/*
78 * High threshold controlling when to start sending XOFF frames. Must be at
79 * least 8 bytes less than receive packet buffer size. This value is in units
80 * of 1024 bytes.
81 */
82#define IXGBE_FC_HI 0x80
83
84/*
85 * Low threshold controlling when to start sending XON frames. This value is
86 * in units of 1024 bytes.
87 */
88#define IXGBE_FC_LO 0x40
89
90/* Default minimum inter-interrupt interval for EITR configuration */
91#define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
92
93/* Timer value included in XOFF frames. */
94#define IXGBE_FC_PAUSE 0x680
95
96#define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
97#define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
98#define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
99
100#define IXGBE_MMW_SIZE_DEFAULT 0x4
101#define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
102#define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
103
104/*
105 * Default values for RX/TX configuration
106 */
107#define IXGBE_DEFAULT_RX_FREE_THRESH 32
108#define IXGBE_DEFAULT_RX_PTHRESH 8
109#define IXGBE_DEFAULT_RX_HTHRESH 8
110#define IXGBE_DEFAULT_RX_WTHRESH 0
111
112#define IXGBE_DEFAULT_TX_FREE_THRESH 32
113#define IXGBE_DEFAULT_TX_PTHRESH 32
114#define IXGBE_DEFAULT_TX_HTHRESH 0
115#define IXGBE_DEFAULT_TX_WTHRESH 0
116#define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
117
118/* Bit shift and mask */
119#define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
120#define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
121#define IXGBE_8_BIT_WIDTH CHAR_BIT
122#define IXGBE_8_BIT_MASK UINT8_MAX
123
124#define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
125
126#define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
127
128#define IXGBE_HKEY_MAX_INDEX 10
129
130/* Additional timesync values. */
131#define NSEC_PER_SEC 1000000000L
132#define IXGBE_INCVAL_10GB 0x66666666
133#define IXGBE_INCVAL_1GB 0x40000000
134#define IXGBE_INCVAL_100 0x50000000
135#define IXGBE_INCVAL_SHIFT_10GB 28
136#define IXGBE_INCVAL_SHIFT_1GB 24
137#define IXGBE_INCVAL_SHIFT_100 21
138#define IXGBE_INCVAL_SHIFT_82599 7
139#define IXGBE_INCPER_SHIFT_82599 24
140
141#define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
142
143#define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
144#define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
145#define DEFAULT_ETAG_ETYPE 0x893f
146#define IXGBE_ETAG_ETYPE 0x00005084
147#define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
148#define IXGBE_ETAG_ETYPE_VALID 0x80000000
149#define IXGBE_RAH_ADTYPE 0x40000000
150#define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
151#define IXGBE_VMVIR_TAGA_MASK 0x18000000
152#define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
153#define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
154#define IXGBE_QDE_STRIP_TAG 0x00000004
155#define IXGBE_VTEICR_MASK 0x07
156
157enum ixgbevf_xcast_modes {
158 IXGBEVF_XCAST_MODE_NONE = 0,
159 IXGBEVF_XCAST_MODE_MULTI,
160 IXGBEVF_XCAST_MODE_ALLMULTI,
161};
162
163#define IXGBE_EXVET_VET_EXT_SHIFT 16
164#define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
165
166static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
167static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
168static int ixgbe_dev_configure(struct rte_eth_dev *dev);
169static int ixgbe_dev_start(struct rte_eth_dev *dev);
170static void ixgbe_dev_stop(struct rte_eth_dev *dev);
171static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
172static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
173static void ixgbe_dev_close(struct rte_eth_dev *dev);
174static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
175static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
176static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
177static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
178static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
179 int wait_to_complete);
180static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
181 struct rte_eth_stats *stats);
182static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
183 struct rte_eth_xstat *xstats, unsigned n);
184static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
185 struct rte_eth_xstat *xstats, unsigned n);
186static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
187static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
188static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
189 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
190static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
191 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
192static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
193 uint16_t queue_id,
194 uint8_t stat_idx,
195 uint8_t is_rx);
196static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
197 struct rte_eth_dev_info *dev_info);
198static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
199static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
200 struct rte_eth_dev_info *dev_info);
201static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
202
203static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
204 uint16_t vlan_id, int on);
205static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
206 enum rte_vlan_type vlan_type,
207 uint16_t tpid_id);
208static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
209 uint16_t queue, bool on);
210static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
211 int on);
212static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
213static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
214static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
215static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
216static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
217
218static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
219static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
220static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
221 struct rte_eth_fc_conf *fc_conf);
222static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
223 struct rte_eth_fc_conf *fc_conf);
224static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
225 struct rte_eth_pfc_conf *pfc_conf);
226static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
227 struct rte_eth_rss_reta_entry64 *reta_conf,
228 uint16_t reta_size);
229static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
230 struct rte_eth_rss_reta_entry64 *reta_conf,
231 uint16_t reta_size);
232static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
233static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
234static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
235static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
236static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
237static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
238 void *param);
239static void ixgbe_dev_interrupt_delayed_handler(void *param);
240static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
241 uint32_t index, uint32_t pool);
242static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
243static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
244 struct ether_addr *mac_addr);
245static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
246
247/* For Virtual Function support */
248static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
249static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
250static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
251static int ixgbevf_dev_start(struct rte_eth_dev *dev);
252static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
253static void ixgbevf_dev_close(struct rte_eth_dev *dev);
254static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
255static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
256static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
257 struct rte_eth_stats *stats);
258static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
259static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
260 uint16_t vlan_id, int on);
261static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
262 uint16_t queue, int on);
263static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
264static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
265static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
266 uint16_t queue_id);
267static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
268 uint16_t queue_id);
269static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
270 uint8_t queue, uint8_t msix_vector);
271static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
272static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
273static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
274
275/* For Eth VMDQ APIs support */
276static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
277 ether_addr * mac_addr, uint8_t on);
278static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
279static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
280 uint16_t rx_mask, uint8_t on);
281static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
282static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
283static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
284 uint64_t pool_mask, uint8_t vlan_on);
285static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
286 struct rte_eth_mirror_conf *mirror_conf,
287 uint8_t rule_id, uint8_t on);
288static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
289 uint8_t rule_id);
290static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
291 uint16_t queue_id);
292static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
293 uint16_t queue_id);
294static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
295 uint8_t queue, uint8_t msix_vector);
296static void ixgbe_configure_msix(struct rte_eth_dev *dev);
297
298static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
299 uint16_t queue_idx, uint16_t tx_rate);
300static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
301 uint16_t tx_rate, uint64_t q_msk);
302
303static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
304 struct ether_addr *mac_addr,
305 uint32_t index, uint32_t pool);
306static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
307static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
308 struct ether_addr *mac_addr);
309static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
310 struct rte_eth_syn_filter *filter,
311 bool add);
312static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
313 struct rte_eth_syn_filter *filter);
314static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
315 enum rte_filter_op filter_op,
316 void *arg);
317static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
318 struct ixgbe_5tuple_filter *filter);
319static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
320 struct ixgbe_5tuple_filter *filter);
321static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
322 struct rte_eth_ntuple_filter *filter,
323 bool add);
324static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
325 enum rte_filter_op filter_op,
326 void *arg);
327static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
328 struct rte_eth_ntuple_filter *filter);
329static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
330 struct rte_eth_ethertype_filter *filter,
331 bool add);
332static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
333 enum rte_filter_op filter_op,
334 void *arg);
335static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
336 struct rte_eth_ethertype_filter *filter);
337static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
338 enum rte_filter_type filter_type,
339 enum rte_filter_op filter_op,
340 void *arg);
341static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
342
343static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
344 struct ether_addr *mc_addr_set,
345 uint32_t nb_mc_addr);
346static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
347 struct rte_eth_dcb_info *dcb_info);
348
349static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
350static int ixgbe_get_regs(struct rte_eth_dev *dev,
351 struct rte_dev_reg_info *regs);
352static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
353static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
354 struct rte_dev_eeprom_info *eeprom);
355static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
356 struct rte_dev_eeprom_info *eeprom);
357
358static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
359static int ixgbevf_get_regs(struct rte_eth_dev *dev,
360 struct rte_dev_reg_info *regs);
361
362static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
363static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
364static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
365 struct timespec *timestamp,
366 uint32_t flags);
367static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
368 struct timespec *timestamp);
369static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
370static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
371 struct timespec *timestamp);
372static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
373 const struct timespec *timestamp);
374static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
375 void *param);
376
377static int ixgbe_dev_l2_tunnel_eth_type_conf
378 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
379static int ixgbe_dev_l2_tunnel_offload_set
380 (struct rte_eth_dev *dev,
381 struct rte_eth_l2_tunnel_conf *l2_tunnel,
382 uint32_t mask,
383 uint8_t en);
384static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
385 enum rte_filter_op filter_op,
386 void *arg);
387
388static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
389 struct rte_eth_udp_tunnel *udp_tunnel);
390static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
391 struct rte_eth_udp_tunnel *udp_tunnel);
392
393/*
394 * Define VF Stats MACRO for Non "cleared on read" register
395 */
396#define UPDATE_VF_STAT(reg, last, cur) \
397{ \
398 uint32_t latest = IXGBE_READ_REG(hw, reg); \
399 cur += (latest - last) & UINT_MAX; \
400 last = latest; \
401}
402
403#define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
404{ \
405 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
406 u64 new_msb = IXGBE_READ_REG(hw, msb); \
407 u64 latest = ((new_msb << 32) | new_lsb); \
408 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
409 last = latest; \
410}
411
412#define IXGBE_SET_HWSTRIP(h, q) do {\
413 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
414 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
415 (h)->bitmap[idx] |= 1 << bit;\
416 } while (0)
417
418#define IXGBE_CLEAR_HWSTRIP(h, q) do {\
419 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
420 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
421 (h)->bitmap[idx] &= ~(1 << bit);\
422 } while (0)
423
424#define IXGBE_GET_HWSTRIP(h, q, r) do {\
425 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
426 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
427 (r) = (h)->bitmap[idx] >> bit & 1;\
428 } while (0)
429
430/*
431 * The set of PCI devices this driver supports
432 */
433static const struct rte_pci_id pci_id_ixgbe_map[] = {
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
483 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
484 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
486 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
487#ifdef RTE_NIC_BYPASS
488 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
489#endif
490 { .vendor_id = 0, /* sentinel */ },
491};
492
493/*
494 * The set of PCI devices this driver supports (for 82599 VF)
495 */
496static const struct rte_pci_id pci_id_ixgbevf_map[] = {
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
500 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
501 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
502 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
503 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
504 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
505 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
506 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
507 { .vendor_id = 0, /* sentinel */ },
508};
509
510static const struct rte_eth_desc_lim rx_desc_lim = {
511 .nb_max = IXGBE_MAX_RING_DESC,
512 .nb_min = IXGBE_MIN_RING_DESC,
513 .nb_align = IXGBE_RXD_ALIGN,
514};
515
516static const struct rte_eth_desc_lim tx_desc_lim = {
517 .nb_max = IXGBE_MAX_RING_DESC,
518 .nb_min = IXGBE_MIN_RING_DESC,
519 .nb_align = IXGBE_TXD_ALIGN,
520};
521
522static const struct eth_dev_ops ixgbe_eth_dev_ops = {
523 .dev_configure = ixgbe_dev_configure,
524 .dev_start = ixgbe_dev_start,
525 .dev_stop = ixgbe_dev_stop,
526 .dev_set_link_up = ixgbe_dev_set_link_up,
527 .dev_set_link_down = ixgbe_dev_set_link_down,
528 .dev_close = ixgbe_dev_close,
529 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
530 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
531 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
532 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
533 .link_update = ixgbe_dev_link_update,
534 .stats_get = ixgbe_dev_stats_get,
535 .xstats_get = ixgbe_dev_xstats_get,
536 .stats_reset = ixgbe_dev_stats_reset,
537 .xstats_reset = ixgbe_dev_xstats_reset,
538 .xstats_get_names = ixgbe_dev_xstats_get_names,
539 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
540 .dev_infos_get = ixgbe_dev_info_get,
541 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
542 .mtu_set = ixgbe_dev_mtu_set,
543 .vlan_filter_set = ixgbe_vlan_filter_set,
544 .vlan_tpid_set = ixgbe_vlan_tpid_set,
545 .vlan_offload_set = ixgbe_vlan_offload_set,
546 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
547 .rx_queue_start = ixgbe_dev_rx_queue_start,
548 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
549 .tx_queue_start = ixgbe_dev_tx_queue_start,
550 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
551 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
552 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
553 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
554 .rx_queue_release = ixgbe_dev_rx_queue_release,
555 .rx_queue_count = ixgbe_dev_rx_queue_count,
556 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
557 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
558 .tx_queue_release = ixgbe_dev_tx_queue_release,
559 .dev_led_on = ixgbe_dev_led_on,
560 .dev_led_off = ixgbe_dev_led_off,
561 .flow_ctrl_get = ixgbe_flow_ctrl_get,
562 .flow_ctrl_set = ixgbe_flow_ctrl_set,
563 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
564 .mac_addr_add = ixgbe_add_rar,
565 .mac_addr_remove = ixgbe_remove_rar,
566 .mac_addr_set = ixgbe_set_default_mac_addr,
567 .uc_hash_table_set = ixgbe_uc_hash_table_set,
568 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
569 .mirror_rule_set = ixgbe_mirror_rule_set,
570 .mirror_rule_reset = ixgbe_mirror_rule_reset,
571 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
572 .set_vf_rx = ixgbe_set_pool_rx,
573 .set_vf_tx = ixgbe_set_pool_tx,
574 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
575 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
576 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
577 .reta_update = ixgbe_dev_rss_reta_update,
578 .reta_query = ixgbe_dev_rss_reta_query,
579#ifdef RTE_NIC_BYPASS
580 .bypass_init = ixgbe_bypass_init,
581 .bypass_state_set = ixgbe_bypass_state_store,
582 .bypass_state_show = ixgbe_bypass_state_show,
583 .bypass_event_set = ixgbe_bypass_event_store,
584 .bypass_event_show = ixgbe_bypass_event_show,
585 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
586 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
587 .bypass_ver_show = ixgbe_bypass_ver_show,
588 .bypass_wd_reset = ixgbe_bypass_wd_reset,
589#endif /* RTE_NIC_BYPASS */
590 .rss_hash_update = ixgbe_dev_rss_hash_update,
591 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
592 .filter_ctrl = ixgbe_dev_filter_ctrl,
593 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
594 .rxq_info_get = ixgbe_rxq_info_get,
595 .txq_info_get = ixgbe_txq_info_get,
596 .timesync_enable = ixgbe_timesync_enable,
597 .timesync_disable = ixgbe_timesync_disable,
598 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
599 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
600 .get_reg = ixgbe_get_regs,
601 .get_eeprom_length = ixgbe_get_eeprom_length,
602 .get_eeprom = ixgbe_get_eeprom,
603 .set_eeprom = ixgbe_set_eeprom,
604 .get_dcb_info = ixgbe_dev_get_dcb_info,
605 .timesync_adjust_time = ixgbe_timesync_adjust_time,
606 .timesync_read_time = ixgbe_timesync_read_time,
607 .timesync_write_time = ixgbe_timesync_write_time,
608 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
609 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
610 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
611 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
612};
613
614/*
615 * dev_ops for virtual function, bare necessities for basic vf
616 * operation have been implemented
617 */
618static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
619 .dev_configure = ixgbevf_dev_configure,
620 .dev_start = ixgbevf_dev_start,
621 .dev_stop = ixgbevf_dev_stop,
622 .link_update = ixgbe_dev_link_update,
623 .stats_get = ixgbevf_dev_stats_get,
624 .xstats_get = ixgbevf_dev_xstats_get,
625 .stats_reset = ixgbevf_dev_stats_reset,
626 .xstats_reset = ixgbevf_dev_stats_reset,
627 .xstats_get_names = ixgbevf_dev_xstats_get_names,
628 .dev_close = ixgbevf_dev_close,
629 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
630 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
631 .dev_infos_get = ixgbevf_dev_info_get,
632 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
633 .mtu_set = ixgbevf_dev_set_mtu,
634 .vlan_filter_set = ixgbevf_vlan_filter_set,
635 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
636 .vlan_offload_set = ixgbevf_vlan_offload_set,
637 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
638 .rx_queue_release = ixgbe_dev_rx_queue_release,
639 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
640 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
641 .tx_queue_release = ixgbe_dev_tx_queue_release,
642 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
643 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
644 .mac_addr_add = ixgbevf_add_mac_addr,
645 .mac_addr_remove = ixgbevf_remove_mac_addr,
646 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
647 .rxq_info_get = ixgbe_rxq_info_get,
648 .txq_info_get = ixgbe_txq_info_get,
649 .mac_addr_set = ixgbevf_set_default_mac_addr,
650 .get_reg = ixgbevf_get_regs,
651 .reta_update = ixgbe_dev_rss_reta_update,
652 .reta_query = ixgbe_dev_rss_reta_query,
653 .rss_hash_update = ixgbe_dev_rss_hash_update,
654 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
655};
656
657/* store statistics names and its offset in stats structure */
658struct rte_ixgbe_xstats_name_off {
659 char name[RTE_ETH_XSTATS_NAME_SIZE];
660 unsigned offset;
661};
662
663static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
664 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
665 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
666 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
667 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
668 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
669 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
670 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
671 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
672 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
673 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
674 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
675 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
676 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
677 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
678 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
679 prc1023)},
680 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
681 prc1522)},
682 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
683 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
684 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
685 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
686 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
687 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
688 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
689 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
690 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
691 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
692 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
693 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
694 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
695 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
696 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
697 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
698 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
699 ptc1023)},
700 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
701 ptc1522)},
702 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
703 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
704 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
705 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
706
707 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
708 fdirustat_add)},
709 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
710 fdirustat_remove)},
711 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
712 fdirfstat_fadd)},
713 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
714 fdirfstat_fremove)},
715 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
716 fdirmatch)},
717 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
718 fdirmiss)},
719
720 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
721 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
722 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
723 fclast)},
724 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
725 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
726 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
727 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
728 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
729 fcoe_noddp)},
730 {"rx_fcoe_no_direct_data_placement_ext_buff",
731 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
732
733 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
734 lxontxc)},
735 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
736 lxonrxc)},
737 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
738 lxofftxc)},
739 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
740 lxoffrxc)},
741 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
742};
743
744#define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
745 sizeof(rte_ixgbe_stats_strings[0]))
746
747/* Per-queue statistics */
748static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
749 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
750 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
751 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
752 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
753};
754
755#define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
756 sizeof(rte_ixgbe_rxq_strings[0]))
757#define IXGBE_NB_RXQ_PRIO_VALUES 8
758
759static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
760 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
761 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
762 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
763 pxon2offc)},
764};
765
766#define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
767 sizeof(rte_ixgbe_txq_strings[0]))
768#define IXGBE_NB_TXQ_PRIO_VALUES 8
769
770static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
771 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
772};
773
774#define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
775 sizeof(rte_ixgbevf_stats_strings[0]))
776
777/**
778 * Atomically reads the link status information from global
779 * structure rte_eth_dev.
780 *
781 * @param dev
782 * - Pointer to the structure rte_eth_dev to read from.
783 * - Pointer to the buffer to be saved with the link status.
784 *
785 * @return
786 * - On success, zero.
787 * - On failure, negative value.
788 */
789static inline int
790rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
791 struct rte_eth_link *link)
792{
793 struct rte_eth_link *dst = link;
794 struct rte_eth_link *src = &(dev->data->dev_link);
795
796 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
797 *(uint64_t *)src) == 0)
798 return -1;
799
800 return 0;
801}
802
803/**
804 * Atomically writes the link status information into global
805 * structure rte_eth_dev.
806 *
807 * @param dev
808 * - Pointer to the structure rte_eth_dev to read from.
809 * - Pointer to the buffer to be saved with the link status.
810 *
811 * @return
812 * - On success, zero.
813 * - On failure, negative value.
814 */
815static inline int
816rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
817 struct rte_eth_link *link)
818{
819 struct rte_eth_link *dst = &(dev->data->dev_link);
820 struct rte_eth_link *src = link;
821
822 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
823 *(uint64_t *)src) == 0)
824 return -1;
825
826 return 0;
827}
828
829/*
830 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
831 */
832static inline int
833ixgbe_is_sfp(struct ixgbe_hw *hw)
834{
835 switch (hw->phy.type) {
836 case ixgbe_phy_sfp_avago:
837 case ixgbe_phy_sfp_ftl:
838 case ixgbe_phy_sfp_intel:
839 case ixgbe_phy_sfp_unknown:
840 case ixgbe_phy_sfp_passive_tyco:
841 case ixgbe_phy_sfp_passive_unknown:
842 return 1;
843 default:
844 return 0;
845 }
846}
847
848static inline int32_t
849ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
850{
851 uint32_t ctrl_ext;
852 int32_t status;
853
854 status = ixgbe_reset_hw(hw);
855
856 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
857 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
858 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
859 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
860 IXGBE_WRITE_FLUSH(hw);
861
862 return status;
863}
864
865static inline void
866ixgbe_enable_intr(struct rte_eth_dev *dev)
867{
868 struct ixgbe_interrupt *intr =
869 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
870 struct ixgbe_hw *hw =
871 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
872
873 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
874 IXGBE_WRITE_FLUSH(hw);
875}
876
877/*
878 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
879 */
880static void
881ixgbe_disable_intr(struct ixgbe_hw *hw)
882{
883 PMD_INIT_FUNC_TRACE();
884
885 if (hw->mac.type == ixgbe_mac_82598EB) {
886 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
887 } else {
888 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
889 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
890 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
891 }
892 IXGBE_WRITE_FLUSH(hw);
893}
894
895/*
896 * This function resets queue statistics mapping registers.
897 * From Niantic datasheet, Initialization of Statistics section:
898 * "...if software requires the queue counters, the RQSMR and TQSM registers
899 * must be re-programmed following a device reset.
900 */
901static void
902ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
903{
904 uint32_t i;
905
906 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
907 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
908 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
909 }
910}
911
912
913static int
914ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
915 uint16_t queue_id,
916 uint8_t stat_idx,
917 uint8_t is_rx)
918{
919#define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
920#define NB_QMAP_FIELDS_PER_QSM_REG 4
921#define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
922
923 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
924 struct ixgbe_stat_mapping_registers *stat_mappings =
925 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
926 uint32_t qsmr_mask = 0;
927 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
928 uint32_t q_map;
929 uint8_t n, offset;
930
931 if ((hw->mac.type != ixgbe_mac_82599EB) &&
932 (hw->mac.type != ixgbe_mac_X540) &&
933 (hw->mac.type != ixgbe_mac_X550) &&
934 (hw->mac.type != ixgbe_mac_X550EM_x) &&
935 (hw->mac.type != ixgbe_mac_X550EM_a))
936 return -ENOSYS;
937
938 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
939 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
940 queue_id, stat_idx);
941
942 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
943 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
944 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
945 return -EIO;
946 }
947 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
948
949 /* Now clear any previous stat_idx set */
950 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
951 if (!is_rx)
952 stat_mappings->tqsm[n] &= ~clearing_mask;
953 else
954 stat_mappings->rqsmr[n] &= ~clearing_mask;
955
956 q_map = (uint32_t)stat_idx;
957 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
958 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
959 if (!is_rx)
960 stat_mappings->tqsm[n] |= qsmr_mask;
961 else
962 stat_mappings->rqsmr[n] |= qsmr_mask;
963
964 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
965 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
966 queue_id, stat_idx);
967 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
968 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
969
970 /* Now write the mapping in the appropriate register */
971 if (is_rx) {
972 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
973 stat_mappings->rqsmr[n], n);
974 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
975 } else {
976 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
977 stat_mappings->tqsm[n], n);
978 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
979 }
980 return 0;
981}
982
983static void
984ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
985{
986 struct ixgbe_stat_mapping_registers *stat_mappings =
987 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
988 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
989 int i;
990
991 /* write whatever was in stat mapping table to the NIC */
992 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
993 /* rx */
994 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
995
996 /* tx */
997 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
998 }
999}
1000
1001static void
1002ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1003{
1004 uint8_t i;
1005 struct ixgbe_dcb_tc_config *tc;
1006 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1007
1008 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1009 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1010 for (i = 0; i < dcb_max_tc; i++) {
1011 tc = &dcb_config->tc_config[i];
1012 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1013 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1014 (uint8_t)(100/dcb_max_tc + (i & 1));
1015 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1016 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1017 (uint8_t)(100/dcb_max_tc + (i & 1));
1018 tc->pfc = ixgbe_dcb_pfc_disabled;
1019 }
1020
1021 /* Initialize default user to priority mapping, UPx->TC0 */
1022 tc = &dcb_config->tc_config[0];
1023 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1024 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1025 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1026 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1027 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1028 }
1029 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1030 dcb_config->pfc_mode_enable = false;
1031 dcb_config->vt_mode = true;
1032 dcb_config->round_robin_enable = false;
1033 /* support all DCB capabilities in 82599 */
1034 dcb_config->support.capabilities = 0xFF;
1035
1036 /*we only support 4 Tcs for X540, X550 */
1037 if (hw->mac.type == ixgbe_mac_X540 ||
1038 hw->mac.type == ixgbe_mac_X550 ||
1039 hw->mac.type == ixgbe_mac_X550EM_x ||
1040 hw->mac.type == ixgbe_mac_X550EM_a) {
1041 dcb_config->num_tcs.pg_tcs = 4;
1042 dcb_config->num_tcs.pfc_tcs = 4;
1043 }
1044}
1045
1046/*
1047 * Ensure that all locks are released before first NVM or PHY access
1048 */
1049static void
1050ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1051{
1052 uint16_t mask;
1053
1054 /*
1055 * Phy lock should not fail in this early stage. If this is the case,
1056 * it is due to an improper exit of the application.
1057 * So force the release of the faulty lock. Release of common lock
1058 * is done automatically by swfw_sync function.
1059 */
1060 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1061 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1062 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1063 }
1064 ixgbe_release_swfw_semaphore(hw, mask);
1065
1066 /*
1067 * These ones are more tricky since they are common to all ports; but
1068 * swfw_sync retries last long enough (1s) to be almost sure that if
1069 * lock can not be taken it is due to an improper lock of the
1070 * semaphore.
1071 */
1072 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1073 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1074 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1075 }
1076 ixgbe_release_swfw_semaphore(hw, mask);
1077}
1078
1079/*
1080 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1081 * It returns 0 on success.
1082 */
1083static int
1084eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1085{
1086 struct rte_pci_device *pci_dev;
1087 struct ixgbe_hw *hw =
1088 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1089 struct ixgbe_vfta *shadow_vfta =
1090 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1091 struct ixgbe_hwstrip *hwstrip =
1092 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1093 struct ixgbe_dcb_config *dcb_config =
1094 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1095 struct ixgbe_filter_info *filter_info =
1096 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1097 uint32_t ctrl_ext;
1098 uint16_t csum;
1099 int diag, i;
1100
1101 PMD_INIT_FUNC_TRACE();
1102
1103 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1104 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1105 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1106
1107 /*
1108 * For secondary processes, we don't initialise any further as primary
1109 * has already done this work. Only check we don't need a different
1110 * RX and TX function.
1111 */
1112 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1113 struct ixgbe_tx_queue *txq;
1114 /* TX queue function in primary, set by last queue initialized
1115 * Tx queue may not initialized by primary process
1116 */
1117 if (eth_dev->data->tx_queues) {
1118 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1119 ixgbe_set_tx_function(eth_dev, txq);
1120 } else {
1121 /* Use default TX function if we get here */
1122 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1123 "Using default TX function.");
1124 }
1125
1126 ixgbe_set_rx_function(eth_dev);
1127
1128 return 0;
1129 }
1130 pci_dev = eth_dev->pci_dev;
1131
1132 rte_eth_copy_pci_info(eth_dev, pci_dev);
1133
1134 /* Vendor and Device ID need to be set before init of shared code */
1135 hw->device_id = pci_dev->id.device_id;
1136 hw->vendor_id = pci_dev->id.vendor_id;
1137 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1138 hw->allow_unsupported_sfp = 1;
1139
1140 /* Initialize the shared code (base driver) */
1141#ifdef RTE_NIC_BYPASS
1142 diag = ixgbe_bypass_init_shared_code(hw);
1143#else
1144 diag = ixgbe_init_shared_code(hw);
1145#endif /* RTE_NIC_BYPASS */
1146
1147 if (diag != IXGBE_SUCCESS) {
1148 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1149 return -EIO;
1150 }
1151
1152 /* pick up the PCI bus settings for reporting later */
1153 ixgbe_get_bus_info(hw);
1154
1155 /* Unlock any pending hardware semaphore */
1156 ixgbe_swfw_lock_reset(hw);
1157
1158 /* Initialize DCB configuration*/
1159 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1160 ixgbe_dcb_init(hw, dcb_config);
1161 /* Get Hardware Flow Control setting */
1162 hw->fc.requested_mode = ixgbe_fc_full;
1163 hw->fc.current_mode = ixgbe_fc_full;
1164 hw->fc.pause_time = IXGBE_FC_PAUSE;
1165 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1166 hw->fc.low_water[i] = IXGBE_FC_LO;
1167 hw->fc.high_water[i] = IXGBE_FC_HI;
1168 }
1169 hw->fc.send_xon = 1;
1170
1171 /* Make sure we have a good EEPROM before we read from it */
1172 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1173 if (diag != IXGBE_SUCCESS) {
1174 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1175 return -EIO;
1176 }
1177
1178#ifdef RTE_NIC_BYPASS
1179 diag = ixgbe_bypass_init_hw(hw);
1180#else
1181 diag = ixgbe_init_hw(hw);
1182#endif /* RTE_NIC_BYPASS */
1183
1184 /*
1185 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1186 * is called too soon after the kernel driver unbinding/binding occurs.
1187 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1188 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1189 * also called. See ixgbe_identify_phy_82599(). The reason for the
1190 * failure is not known, and only occuts when virtualisation features
1191 * are disabled in the bios. A delay of 100ms was found to be enough by
1192 * trial-and-error, and is doubled to be safe.
1193 */
1194 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1195 rte_delay_ms(200);
1196 diag = ixgbe_init_hw(hw);
1197 }
1198
1199 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1200 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1201 "LOM. Please be aware there may be issues associated "
1202 "with your hardware.");
1203 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1204 "please contact your Intel or hardware representative "
1205 "who provided you with this hardware.");
1206 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1207 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1208 if (diag) {
1209 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1210 return -EIO;
1211 }
1212
1213 /* Reset the hw statistics */
1214 ixgbe_dev_stats_reset(eth_dev);
1215
1216 /* disable interrupt */
1217 ixgbe_disable_intr(hw);
1218
1219 /* reset mappings for queue statistics hw counters*/
1220 ixgbe_reset_qstat_mappings(hw);
1221
1222 /* Allocate memory for storing MAC addresses */
1223 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1224 hw->mac.num_rar_entries, 0);
1225 if (eth_dev->data->mac_addrs == NULL) {
1226 PMD_INIT_LOG(ERR,
1227 "Failed to allocate %u bytes needed to store "
1228 "MAC addresses",
1229 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1230 return -ENOMEM;
1231 }
1232 /* Copy the permanent MAC address */
1233 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1234 &eth_dev->data->mac_addrs[0]);
1235
1236 /* Allocate memory for storing hash filter MAC addresses */
1237 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1238 IXGBE_VMDQ_NUM_UC_MAC, 0);
1239 if (eth_dev->data->hash_mac_addrs == NULL) {
1240 PMD_INIT_LOG(ERR,
1241 "Failed to allocate %d bytes needed to store MAC addresses",
1242 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1243 return -ENOMEM;
1244 }
1245
1246 /* initialize the vfta */
1247 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1248
1249 /* initialize the hw strip bitmap*/
1250 memset(hwstrip, 0, sizeof(*hwstrip));
1251
1252 /* initialize PF if max_vfs not zero */
1253 ixgbe_pf_host_init(eth_dev);
1254
1255 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1256 /* let hardware know driver is loaded */
1257 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1258 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1259 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1260 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1261 IXGBE_WRITE_FLUSH(hw);
1262
1263 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1264 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1265 (int) hw->mac.type, (int) hw->phy.type,
1266 (int) hw->phy.sfp_type);
1267 else
1268 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1269 (int) hw->mac.type, (int) hw->phy.type);
1270
1271 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1272 eth_dev->data->port_id, pci_dev->id.vendor_id,
1273 pci_dev->id.device_id);
1274
1275 rte_intr_callback_register(&pci_dev->intr_handle,
1276 ixgbe_dev_interrupt_handler,
1277 (void *)eth_dev);
1278
1279 /* enable uio/vfio intr/eventfd mapping */
1280 rte_intr_enable(&pci_dev->intr_handle);
1281
1282 /* enable support intr */
1283 ixgbe_enable_intr(eth_dev);
1284
1285 /* initialize 5tuple filter list */
1286 TAILQ_INIT(&filter_info->fivetuple_list);
1287 memset(filter_info->fivetuple_mask, 0,
1288 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1289
1290 return 0;
1291}
1292
1293static int
1294eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1295{
1296 struct rte_pci_device *pci_dev;
1297 struct ixgbe_hw *hw;
1298
1299 PMD_INIT_FUNC_TRACE();
1300
1301 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1302 return -EPERM;
1303
1304 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1305 pci_dev = eth_dev->pci_dev;
1306
1307 if (hw->adapter_stopped == 0)
1308 ixgbe_dev_close(eth_dev);
1309
1310 eth_dev->dev_ops = NULL;
1311 eth_dev->rx_pkt_burst = NULL;
1312 eth_dev->tx_pkt_burst = NULL;
1313
1314 /* Unlock any pending hardware semaphore */
1315 ixgbe_swfw_lock_reset(hw);
1316
1317 /* disable uio intr before callback unregister */
1318 rte_intr_disable(&(pci_dev->intr_handle));
1319 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1320 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1321
1322 /* uninitialize PF if max_vfs not zero */
1323 ixgbe_pf_host_uninit(eth_dev);
1324
1325 rte_free(eth_dev->data->mac_addrs);
1326 eth_dev->data->mac_addrs = NULL;
1327
1328 rte_free(eth_dev->data->hash_mac_addrs);
1329 eth_dev->data->hash_mac_addrs = NULL;
1330
1331 return 0;
1332}
1333
1334/*
1335 * Negotiate mailbox API version with the PF.
1336 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1337 * Then we try to negotiate starting with the most recent one.
1338 * If all negotiation attempts fail, then we will proceed with
1339 * the default one (ixgbe_mbox_api_10).
1340 */
1341static void
1342ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1343{
1344 int32_t i;
1345
1346 /* start with highest supported, proceed down */
1347 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1348 ixgbe_mbox_api_12,
1349 ixgbe_mbox_api_11,
1350 ixgbe_mbox_api_10,
1351 };
1352
1353 for (i = 0;
1354 i != RTE_DIM(sup_ver) &&
1355 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1356 i++)
1357 ;
1358}
1359
1360static void
1361generate_random_mac_addr(struct ether_addr *mac_addr)
1362{
1363 uint64_t random;
1364
1365 /* Set Organizationally Unique Identifier (OUI) prefix. */
1366 mac_addr->addr_bytes[0] = 0x00;
1367 mac_addr->addr_bytes[1] = 0x09;
1368 mac_addr->addr_bytes[2] = 0xC0;
1369 /* Force indication of locally assigned MAC address. */
1370 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1371 /* Generate the last 3 bytes of the MAC address with a random number. */
1372 random = rte_rand();
1373 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1374}
1375
1376/*
1377 * Virtual Function device init
1378 */
1379static int
1380eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1381{
1382 int diag;
1383 uint32_t tc, tcs;
1384 struct rte_pci_device *pci_dev;
1385 struct ixgbe_hw *hw =
1386 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1387 struct ixgbe_vfta *shadow_vfta =
1388 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1389 struct ixgbe_hwstrip *hwstrip =
1390 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1391 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1392
1393 PMD_INIT_FUNC_TRACE();
1394
1395 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1396 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1397 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1398
1399 /* for secondary processes, we don't initialise any further as primary
1400 * has already done this work. Only check we don't need a different
1401 * RX function
1402 */
1403 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1404 struct ixgbe_tx_queue *txq;
1405 /* TX queue function in primary, set by last queue initialized
1406 * Tx queue may not initialized by primary process
1407 */
1408 if (eth_dev->data->tx_queues) {
1409 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1410 ixgbe_set_tx_function(eth_dev, txq);
1411 } else {
1412 /* Use default TX function if we get here */
1413 PMD_INIT_LOG(NOTICE,
1414 "No TX queues configured yet. Using default TX function.");
1415 }
1416
1417 ixgbe_set_rx_function(eth_dev);
1418
1419 return 0;
1420 }
1421
1422 pci_dev = eth_dev->pci_dev;
1423
1424 rte_eth_copy_pci_info(eth_dev, pci_dev);
1425
1426 hw->device_id = pci_dev->id.device_id;
1427 hw->vendor_id = pci_dev->id.vendor_id;
1428 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1429
1430 /* initialize the vfta */
1431 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1432
1433 /* initialize the hw strip bitmap*/
1434 memset(hwstrip, 0, sizeof(*hwstrip));
1435
1436 /* Initialize the shared code (base driver) */
1437 diag = ixgbe_init_shared_code(hw);
1438 if (diag != IXGBE_SUCCESS) {
1439 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1440 return -EIO;
1441 }
1442
1443 /* init_mailbox_params */
1444 hw->mbx.ops.init_params(hw);
1445
1446 /* Reset the hw statistics */
1447 ixgbevf_dev_stats_reset(eth_dev);
1448
1449 /* Disable the interrupts for VF */
1450 ixgbevf_intr_disable(hw);
1451
1452 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1453 diag = hw->mac.ops.reset_hw(hw);
1454
1455 /*
1456 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1457 * the underlying PF driver has not assigned a MAC address to the VF.
1458 * In this case, assign a random MAC address.
1459 */
1460 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1461 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1462 return diag;
1463 }
1464
1465 /* negotiate mailbox API version to use with the PF. */
1466 ixgbevf_negotiate_api(hw);
1467
1468 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1469 ixgbevf_get_queues(hw, &tcs, &tc);
1470
1471 /* Allocate memory for storing MAC addresses */
1472 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1473 hw->mac.num_rar_entries, 0);
1474 if (eth_dev->data->mac_addrs == NULL) {
1475 PMD_INIT_LOG(ERR,
1476 "Failed to allocate %u bytes needed to store "
1477 "MAC addresses",
1478 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1479 return -ENOMEM;
1480 }
1481
1482 /* Generate a random MAC address, if none was assigned by PF. */
1483 if (is_zero_ether_addr(perm_addr)) {
1484 generate_random_mac_addr(perm_addr);
1485 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1486 if (diag) {
1487 rte_free(eth_dev->data->mac_addrs);
1488 eth_dev->data->mac_addrs = NULL;
1489 return diag;
1490 }
1491 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1492 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1493 "%02x:%02x:%02x:%02x:%02x:%02x",
1494 perm_addr->addr_bytes[0],
1495 perm_addr->addr_bytes[1],
1496 perm_addr->addr_bytes[2],
1497 perm_addr->addr_bytes[3],
1498 perm_addr->addr_bytes[4],
1499 perm_addr->addr_bytes[5]);
1500 }
1501
1502 /* Copy the permanent MAC address */
1503 ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1504
1505 /* reset the hardware with the new settings */
1506 diag = hw->mac.ops.start_hw(hw);
1507 switch (diag) {
1508 case 0:
1509 break;
1510
1511 default:
1512 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1513 return -EIO;
1514 }
1515
1516 rte_intr_callback_register(&pci_dev->intr_handle,
1517 ixgbevf_dev_interrupt_handler,
1518 (void *)eth_dev);
1519 rte_intr_enable(&pci_dev->intr_handle);
1520 ixgbevf_intr_enable(hw);
1521
1522 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1523 eth_dev->data->port_id, pci_dev->id.vendor_id,
1524 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1525
1526 return 0;
1527}
1528
1529/* Virtual Function device uninit */
1530
1531static int
1532eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1533{
1534 struct ixgbe_hw *hw;
1535 struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1536
1537 PMD_INIT_FUNC_TRACE();
1538
1539 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1540 return -EPERM;
1541
1542 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1543
1544 if (hw->adapter_stopped == 0)
1545 ixgbevf_dev_close(eth_dev);
1546
1547 eth_dev->dev_ops = NULL;
1548 eth_dev->rx_pkt_burst = NULL;
1549 eth_dev->tx_pkt_burst = NULL;
1550
1551 /* Disable the interrupts for VF */
1552 ixgbevf_intr_disable(hw);
1553
1554 rte_free(eth_dev->data->mac_addrs);
1555 eth_dev->data->mac_addrs = NULL;
1556
1557 rte_intr_disable(&pci_dev->intr_handle);
1558 rte_intr_callback_unregister(&pci_dev->intr_handle,
1559 ixgbevf_dev_interrupt_handler,
1560 (void *)eth_dev);
1561
1562 return 0;
1563}
1564
1565static struct eth_driver rte_ixgbe_pmd = {
1566 .pci_drv = {
1567 .id_table = pci_id_ixgbe_map,
1568 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1569 RTE_PCI_DRV_DETACHABLE,
1570 .probe = rte_eth_dev_pci_probe,
1571 .remove = rte_eth_dev_pci_remove,
1572 },
1573 .eth_dev_init = eth_ixgbe_dev_init,
1574 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1575 .dev_private_size = sizeof(struct ixgbe_adapter),
1576};
1577
1578/*
1579 * virtual function driver struct
1580 */
1581static struct eth_driver rte_ixgbevf_pmd = {
1582 .pci_drv = {
1583 .id_table = pci_id_ixgbevf_map,
1584 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1585 .probe = rte_eth_dev_pci_probe,
1586 .remove = rte_eth_dev_pci_remove,
1587 },
1588 .eth_dev_init = eth_ixgbevf_dev_init,
1589 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1590 .dev_private_size = sizeof(struct ixgbe_adapter),
1591};
1592
1593static int
1594ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1595{
1596 struct ixgbe_hw *hw =
1597 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1598 struct ixgbe_vfta *shadow_vfta =
1599 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1600 uint32_t vfta;
1601 uint32_t vid_idx;
1602 uint32_t vid_bit;
1603
1604 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1605 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1606 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1607 if (on)
1608 vfta |= vid_bit;
1609 else
1610 vfta &= ~vid_bit;
1611 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1612
1613 /* update local VFTA copy */
1614 shadow_vfta->vfta[vid_idx] = vfta;
1615
1616 return 0;
1617}
1618
1619static void
1620ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1621{
1622 if (on)
1623 ixgbe_vlan_hw_strip_enable(dev, queue);
1624 else
1625 ixgbe_vlan_hw_strip_disable(dev, queue);
1626}
1627
1628static int
1629ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1630 enum rte_vlan_type vlan_type,
1631 uint16_t tpid)
1632{
1633 struct ixgbe_hw *hw =
1634 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1635 int ret = 0;
1636 uint32_t reg;
1637 uint32_t qinq;
1638
1639 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1640 qinq &= IXGBE_DMATXCTL_GDV;
1641
1642 switch (vlan_type) {
1643 case ETH_VLAN_TYPE_INNER:
1644 if (qinq) {
1645 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1646 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1647 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1648 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1649 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1650 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1651 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1652 } else {
1653 ret = -ENOTSUP;
1654 PMD_DRV_LOG(ERR, "Inner type is not supported"
1655 " by single VLAN");
1656 }
1657 break;
1658 case ETH_VLAN_TYPE_OUTER:
1659 if (qinq) {
1660 /* Only the high 16-bits is valid */
1661 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1662 IXGBE_EXVET_VET_EXT_SHIFT);
1663 } else {
1664 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1665 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1666 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1667 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1668 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1669 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1670 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1671 }
1672
1673 break;
1674 default:
1675 ret = -EINVAL;
1676 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1677 break;
1678 }
1679
1680 return ret;
1681}
1682
1683void
1684ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1685{
1686 struct ixgbe_hw *hw =
1687 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1688 uint32_t vlnctrl;
1689
1690 PMD_INIT_FUNC_TRACE();
1691
1692 /* Filter Table Disable */
1693 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1694 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1695
1696 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1697}
1698
1699void
1700ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1701{
1702 struct ixgbe_hw *hw =
1703 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1704 struct ixgbe_vfta *shadow_vfta =
1705 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1706 uint32_t vlnctrl;
1707 uint16_t i;
1708
1709 PMD_INIT_FUNC_TRACE();
1710
1711 /* Filter Table Enable */
1712 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1713 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1714 vlnctrl |= IXGBE_VLNCTRL_VFE;
1715
1716 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1717
1718 /* write whatever is in local vfta copy */
1719 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1720 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1721}
1722
1723static void
1724ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1725{
1726 struct ixgbe_hwstrip *hwstrip =
1727 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1728 struct ixgbe_rx_queue *rxq;
1729
1730 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1731 return;
1732
1733 if (on)
1734 IXGBE_SET_HWSTRIP(hwstrip, queue);
1735 else
1736 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1737
1738 if (queue >= dev->data->nb_rx_queues)
1739 return;
1740
1741 rxq = dev->data->rx_queues[queue];
1742
1743 if (on)
1744 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1745 else
1746 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1747}
1748
1749static void
1750ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1751{
1752 struct ixgbe_hw *hw =
1753 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1754 uint32_t ctrl;
1755
1756 PMD_INIT_FUNC_TRACE();
1757
1758 if (hw->mac.type == ixgbe_mac_82598EB) {
1759 /* No queue level support */
1760 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1761 return;
1762 }
1763
1764 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1765 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1766 ctrl &= ~IXGBE_RXDCTL_VME;
1767 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1768
1769 /* record those setting for HW strip per queue */
1770 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1771}
1772
1773static void
1774ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1775{
1776 struct ixgbe_hw *hw =
1777 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1778 uint32_t ctrl;
1779
1780 PMD_INIT_FUNC_TRACE();
1781
1782 if (hw->mac.type == ixgbe_mac_82598EB) {
1783 /* No queue level supported */
1784 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1785 return;
1786 }
1787
1788 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1789 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1790 ctrl |= IXGBE_RXDCTL_VME;
1791 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1792
1793 /* record those setting for HW strip per queue */
1794 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1795}
1796
1797void
1798ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1799{
1800 struct ixgbe_hw *hw =
1801 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1802 uint32_t ctrl;
1803 uint16_t i;
1804 struct ixgbe_rx_queue *rxq;
1805
1806 PMD_INIT_FUNC_TRACE();
1807
1808 if (hw->mac.type == ixgbe_mac_82598EB) {
1809 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1810 ctrl &= ~IXGBE_VLNCTRL_VME;
1811 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1812 } else {
1813 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1814 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1815 rxq = dev->data->rx_queues[i];
1816 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1817 ctrl &= ~IXGBE_RXDCTL_VME;
1818 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1819
1820 /* record those setting for HW strip per queue */
1821 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1822 }
1823 }
1824}
1825
1826void
1827ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1828{
1829 struct ixgbe_hw *hw =
1830 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1831 uint32_t ctrl;
1832 uint16_t i;
1833 struct ixgbe_rx_queue *rxq;
1834
1835 PMD_INIT_FUNC_TRACE();
1836
1837 if (hw->mac.type == ixgbe_mac_82598EB) {
1838 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1839 ctrl |= IXGBE_VLNCTRL_VME;
1840 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1841 } else {
1842 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1843 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1844 rxq = dev->data->rx_queues[i];
1845 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1846 ctrl |= IXGBE_RXDCTL_VME;
1847 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1848
1849 /* record those setting for HW strip per queue */
1850 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1851 }
1852 }
1853}
1854
1855static void
1856ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1857{
1858 struct ixgbe_hw *hw =
1859 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1860 uint32_t ctrl;
1861
1862 PMD_INIT_FUNC_TRACE();
1863
1864 /* DMATXCTRL: Geric Double VLAN Disable */
1865 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1866 ctrl &= ~IXGBE_DMATXCTL_GDV;
1867 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1868
1869 /* CTRL_EXT: Global Double VLAN Disable */
1870 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1871 ctrl &= ~IXGBE_EXTENDED_VLAN;
1872 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1873
1874}
1875
1876static void
1877ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1878{
1879 struct ixgbe_hw *hw =
1880 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1881 uint32_t ctrl;
1882
1883 PMD_INIT_FUNC_TRACE();
1884
1885 /* DMATXCTRL: Geric Double VLAN Enable */
1886 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1887 ctrl |= IXGBE_DMATXCTL_GDV;
1888 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1889
1890 /* CTRL_EXT: Global Double VLAN Enable */
1891 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1892 ctrl |= IXGBE_EXTENDED_VLAN;
1893 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1894
1895 /* Clear pooling mode of PFVTCTL. It's required by X550. */
1896 if (hw->mac.type == ixgbe_mac_X550 ||
1897 hw->mac.type == ixgbe_mac_X550EM_x ||
1898 hw->mac.type == ixgbe_mac_X550EM_a) {
1899 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1900 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1901 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1902 }
1903
1904 /*
1905 * VET EXT field in the EXVET register = 0x8100 by default
1906 * So no need to change. Same to VT field of DMATXCTL register
1907 */
1908}
1909
1910static void
1911ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1912{
1913 if (mask & ETH_VLAN_STRIP_MASK) {
1914 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1915 ixgbe_vlan_hw_strip_enable_all(dev);
1916 else
1917 ixgbe_vlan_hw_strip_disable_all(dev);
1918 }
1919
1920 if (mask & ETH_VLAN_FILTER_MASK) {
1921 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1922 ixgbe_vlan_hw_filter_enable(dev);
1923 else
1924 ixgbe_vlan_hw_filter_disable(dev);
1925 }
1926
1927 if (mask & ETH_VLAN_EXTEND_MASK) {
1928 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1929 ixgbe_vlan_hw_extend_enable(dev);
1930 else
1931 ixgbe_vlan_hw_extend_disable(dev);
1932 }
1933}
1934
1935static void
1936ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1937{
1938 struct ixgbe_hw *hw =
1939 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1940 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1941 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1942
1943 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1944 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1945}
1946
1947static int
1948ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1949{
1950 switch (nb_rx_q) {
1951 case 1:
1952 case 2:
1953 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1954 break;
1955 case 4:
1956 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1957 break;
1958 default:
1959 return -EINVAL;
1960 }
1961
1962 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1963 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1964
1965 return 0;
1966}
1967
1968static int
1969ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1970{
1971 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1972 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1973 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1974 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1975
1976 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1977 /* check multi-queue mode */
1978 switch (dev_conf->rxmode.mq_mode) {
1979 case ETH_MQ_RX_VMDQ_DCB:
1980 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1981 break;
1982 case ETH_MQ_RX_VMDQ_DCB_RSS:
1983 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1984 PMD_INIT_LOG(ERR, "SRIOV active,"
1985 " unsupported mq_mode rx %d.",
1986 dev_conf->rxmode.mq_mode);
1987 return -EINVAL;
1988 case ETH_MQ_RX_RSS:
1989 case ETH_MQ_RX_VMDQ_RSS:
1990 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1991 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1992 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1993 PMD_INIT_LOG(ERR, "SRIOV is active,"
1994 " invalid queue number"
1995 " for VMDQ RSS, allowed"
1996 " value are 1, 2 or 4.");
1997 return -EINVAL;
1998 }
1999 break;
2000 case ETH_MQ_RX_VMDQ_ONLY:
2001 case ETH_MQ_RX_NONE:
2002 /* if nothing mq mode configure, use default scheme */
2003 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2004 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2005 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2006 break;
2007 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2008 /* SRIOV only works in VMDq enable mode */
2009 PMD_INIT_LOG(ERR, "SRIOV is active,"
2010 " wrong mq_mode rx %d.",
2011 dev_conf->rxmode.mq_mode);
2012 return -EINVAL;
2013 }
2014
2015 switch (dev_conf->txmode.mq_mode) {
2016 case ETH_MQ_TX_VMDQ_DCB:
2017 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2018 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2019 break;
2020 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2021 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2022 break;
2023 }
2024
2025 /* check valid queue number */
2026 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2027 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2028 PMD_INIT_LOG(ERR, "SRIOV is active,"
2029 " nb_rx_q=%d nb_tx_q=%d queue number"
2030 " must be less than or equal to %d.",
2031 nb_rx_q, nb_tx_q,
2032 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2033 return -EINVAL;
2034 }
2035 } else {
2036 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2037 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2038 " not supported.");
2039 return -EINVAL;
2040 }
2041 /* check configuration for vmdb+dcb mode */
2042 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2043 const struct rte_eth_vmdq_dcb_conf *conf;
2044
2045 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2046 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2047 IXGBE_VMDQ_DCB_NB_QUEUES);
2048 return -EINVAL;
2049 }
2050 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2051 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2052 conf->nb_queue_pools == ETH_32_POOLS)) {
2053 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2054 " nb_queue_pools must be %d or %d.",
2055 ETH_16_POOLS, ETH_32_POOLS);
2056 return -EINVAL;
2057 }
2058 }
2059 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2060 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2061
2062 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2063 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2064 IXGBE_VMDQ_DCB_NB_QUEUES);
2065 return -EINVAL;
2066 }
2067 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2068 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2069 conf->nb_queue_pools == ETH_32_POOLS)) {
2070 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2071 " nb_queue_pools != %d and"
2072 " nb_queue_pools != %d.",
2073 ETH_16_POOLS, ETH_32_POOLS);
2074 return -EINVAL;
2075 }
2076 }
2077
2078 /* For DCB mode check our configuration before we go further */
2079 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2080 const struct rte_eth_dcb_rx_conf *conf;
2081
2082 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2083 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2084 IXGBE_DCB_NB_QUEUES);
2085 return -EINVAL;
2086 }
2087 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2088 if (!(conf->nb_tcs == ETH_4_TCS ||
2089 conf->nb_tcs == ETH_8_TCS)) {
2090 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2091 " and nb_tcs != %d.",
2092 ETH_4_TCS, ETH_8_TCS);
2093 return -EINVAL;
2094 }
2095 }
2096
2097 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2098 const struct rte_eth_dcb_tx_conf *conf;
2099
2100 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2101 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2102 IXGBE_DCB_NB_QUEUES);
2103 return -EINVAL;
2104 }
2105 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2106 if (!(conf->nb_tcs == ETH_4_TCS ||
2107 conf->nb_tcs == ETH_8_TCS)) {
2108 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2109 " and nb_tcs != %d.",
2110 ETH_4_TCS, ETH_8_TCS);
2111 return -EINVAL;
2112 }
2113 }
2114
2115 /*
2116 * When DCB/VT is off, maximum number of queues changes,
2117 * except for 82598EB, which remains constant.
2118 */
2119 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2120 hw->mac.type != ixgbe_mac_82598EB) {
2121 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2122 PMD_INIT_LOG(ERR,
2123 "Neither VT nor DCB are enabled, "
2124 "nb_tx_q > %d.",
2125 IXGBE_NONE_MODE_TX_NB_QUEUES);
2126 return -EINVAL;
2127 }
2128 }
2129 }
2130 return 0;
2131}
2132
2133static int
2134ixgbe_dev_configure(struct rte_eth_dev *dev)
2135{
2136 struct ixgbe_interrupt *intr =
2137 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2138 struct ixgbe_adapter *adapter =
2139 (struct ixgbe_adapter *)dev->data->dev_private;
2140 int ret;
2141
2142 PMD_INIT_FUNC_TRACE();
2143 /* multipe queue mode checking */
2144 ret = ixgbe_check_mq_mode(dev);
2145 if (ret != 0) {
2146 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2147 ret);
2148 return ret;
2149 }
2150
2151 /* set flag to update link status after init */
2152 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2153
2154 /*
2155 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2156 * allocation or vector Rx preconditions we will reset it.
2157 */
2158 adapter->rx_bulk_alloc_allowed = true;
2159 adapter->rx_vec_allowed = true;
2160
2161 return 0;
2162}
2163
2164static void
2165ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2166{
2167 struct ixgbe_hw *hw =
2168 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2169 struct ixgbe_interrupt *intr =
2170 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2171 uint32_t gpie;
2172
2173 /* only set up it on X550EM_X */
2174 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2175 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2176 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2177 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2178 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2179 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2180 }
2181}
2182
2183/*
2184 * Configure device link speed and setup link.
2185 * It returns 0 on success.
2186 */
2187static int
2188ixgbe_dev_start(struct rte_eth_dev *dev)
2189{
2190 struct ixgbe_hw *hw =
2191 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2192 struct ixgbe_vf_info *vfinfo =
2193 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2194 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2195 uint32_t intr_vector = 0;
2196 int err, link_up = 0, negotiate = 0;
2197 uint32_t speed = 0;
2198 int mask = 0;
2199 int status;
2200 uint16_t vf, idx;
2201 uint32_t *link_speeds;
2202
2203 PMD_INIT_FUNC_TRACE();
2204
2205 /* IXGBE devices don't support:
2206 * - half duplex (checked afterwards for valid speeds)
2207 * - fixed speed: TODO implement
2208 */
2209 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2210 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2211 dev->data->port_id);
2212 return -EINVAL;
2213 }
2214
2215 /* disable uio/vfio intr/eventfd mapping */
2216 rte_intr_disable(intr_handle);
2217
2218 /* stop adapter */
2219 hw->adapter_stopped = 0;
2220 ixgbe_stop_adapter(hw);
2221
2222 /* reinitialize adapter
2223 * this calls reset and start
2224 */
2225 status = ixgbe_pf_reset_hw(hw);
2226 if (status != 0)
2227 return -1;
2228 hw->mac.ops.start_hw(hw);
2229 hw->mac.get_link_status = true;
2230
2231 /* configure PF module if SRIOV enabled */
2232 ixgbe_pf_host_configure(dev);
2233
2234 ixgbe_dev_phy_intr_setup(dev);
2235
2236 /* check and configure queue intr-vector mapping */
2237 if ((rte_intr_cap_multiple(intr_handle) ||
2238 !RTE_ETH_DEV_SRIOV(dev).active) &&
2239 dev->data->dev_conf.intr_conf.rxq != 0) {
2240 intr_vector = dev->data->nb_rx_queues;
2241 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2242 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2243 IXGBE_MAX_INTR_QUEUE_NUM);
2244 return -ENOTSUP;
2245 }
2246 if (rte_intr_efd_enable(intr_handle, intr_vector))
2247 return -1;
2248 }
2249
2250 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2251 intr_handle->intr_vec =
2252 rte_zmalloc("intr_vec",
2253 dev->data->nb_rx_queues * sizeof(int), 0);
2254 if (intr_handle->intr_vec == NULL) {
2255 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2256 " intr_vec\n", dev->data->nb_rx_queues);
2257 return -ENOMEM;
2258 }
2259 }
2260
2261 /* confiugre msix for sleep until rx interrupt */
2262 ixgbe_configure_msix(dev);
2263
2264 /* initialize transmission unit */
2265 ixgbe_dev_tx_init(dev);
2266
2267 /* This can fail when allocating mbufs for descriptor rings */
2268 err = ixgbe_dev_rx_init(dev);
2269 if (err) {
2270 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2271 goto error;
2272 }
2273
2274 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2275 ETH_VLAN_EXTEND_MASK;
2276 ixgbe_vlan_offload_set(dev, mask);
2277
2278 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2279 /* Enable vlan filtering for VMDq */
2280 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2281 }
2282
2283 /* Configure DCB hw */
2284 ixgbe_configure_dcb(dev);
2285
2286 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2287 err = ixgbe_fdir_configure(dev);
2288 if (err)
2289 goto error;
2290 }
2291
2292 /* Restore vf rate limit */
2293 if (vfinfo != NULL) {
2294 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2295 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2296 if (vfinfo[vf].tx_rate[idx] != 0)
2297 ixgbe_set_vf_rate_limit(dev, vf,
2298 vfinfo[vf].tx_rate[idx],
2299 1 << idx);
2300 }
2301
2302 ixgbe_restore_statistics_mapping(dev);
2303
2304 err = ixgbe_dev_rxtx_start(dev);
2305 if (err < 0) {
2306 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2307 goto error;
2308 }
2309
2310 /* Skip link setup if loopback mode is enabled for 82599. */
2311 if (hw->mac.type == ixgbe_mac_82599EB &&
2312 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2313 goto skip_link_setup;
2314
2315 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2316 err = hw->mac.ops.setup_sfp(hw);
2317 if (err)
2318 goto error;
2319 }
2320
2321 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2322 /* Turn on the copper */
2323 ixgbe_set_phy_power(hw, true);
2324 } else {
2325 /* Turn on the laser */
2326 ixgbe_enable_tx_laser(hw);
2327 }
2328
2329 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2330 if (err)
2331 goto error;
2332 dev->data->dev_link.link_status = link_up;
2333
2334 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2335 if (err)
2336 goto error;
2337
2338 link_speeds = &dev->data->dev_conf.link_speeds;
2339 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2340 ETH_LINK_SPEED_10G)) {
2341 PMD_INIT_LOG(ERR, "Invalid link setting");
2342 goto error;
2343 }
2344
2345 speed = 0x0;
2346 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2347 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2348 IXGBE_LINK_SPEED_82599_AUTONEG :
2349 IXGBE_LINK_SPEED_82598_AUTONEG;
2350 } else {
2351 if (*link_speeds & ETH_LINK_SPEED_10G)
2352 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2353 if (*link_speeds & ETH_LINK_SPEED_1G)
2354 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2355 if (*link_speeds & ETH_LINK_SPEED_100M)
2356 speed |= IXGBE_LINK_SPEED_100_FULL;
2357 }
2358
2359 err = ixgbe_setup_link(hw, speed, link_up);
2360 if (err)
2361 goto error;
2362
2363skip_link_setup:
2364
2365 if (rte_intr_allow_others(intr_handle)) {
2366 /* check if lsc interrupt is enabled */
2367 if (dev->data->dev_conf.intr_conf.lsc != 0)
2368 ixgbe_dev_lsc_interrupt_setup(dev);
2369 } else {
2370 rte_intr_callback_unregister(intr_handle,
2371 ixgbe_dev_interrupt_handler,
2372 (void *)dev);
2373 if (dev->data->dev_conf.intr_conf.lsc != 0)
2374 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2375 " no intr multiplex\n");
2376 }
2377
2378 /* check if rxq interrupt is enabled */
2379 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2380 rte_intr_dp_is_en(intr_handle))
2381 ixgbe_dev_rxq_interrupt_setup(dev);
2382
2383 /* enable uio/vfio intr/eventfd mapping */
2384 rte_intr_enable(intr_handle);
2385
2386 /* resume enabled intr since hw reset */
2387 ixgbe_enable_intr(dev);
2388
2389 return 0;
2390
2391error:
2392 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2393 ixgbe_dev_clear_queues(dev);
2394 return -EIO;
2395}
2396
2397/*
2398 * Stop device: disable rx and tx functions to allow for reconfiguring.
2399 */
2400static void
2401ixgbe_dev_stop(struct rte_eth_dev *dev)
2402{
2403 struct rte_eth_link link;
2404 struct ixgbe_hw *hw =
2405 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2406 struct ixgbe_vf_info *vfinfo =
2407 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2408 struct ixgbe_filter_info *filter_info =
2409 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2410 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2411 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2412 int vf;
2413
2414 PMD_INIT_FUNC_TRACE();
2415
2416 /* disable interrupts */
2417 ixgbe_disable_intr(hw);
2418
2419 /* reset the NIC */
2420 ixgbe_pf_reset_hw(hw);
2421 hw->adapter_stopped = 0;
2422
2423 /* stop adapter */
2424 ixgbe_stop_adapter(hw);
2425
2426 for (vf = 0; vfinfo != NULL &&
2427 vf < dev->pci_dev->max_vfs; vf++)
2428 vfinfo[vf].clear_to_send = false;
2429
2430 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2431 /* Turn off the copper */
2432 ixgbe_set_phy_power(hw, false);
2433 } else {
2434 /* Turn off the laser */
2435 ixgbe_disable_tx_laser(hw);
2436 }
2437
2438 ixgbe_dev_clear_queues(dev);
2439
2440 /* Clear stored conf */
2441 dev->data->scattered_rx = 0;
2442 dev->data->lro = 0;
2443
2444 /* Clear recorded link status */
2445 memset(&link, 0, sizeof(link));
2446 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2447
2448 /* Remove all ntuple filters of the device */
2449 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2450 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2451 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2452 TAILQ_REMOVE(&filter_info->fivetuple_list,
2453 p_5tuple, entries);
2454 rte_free(p_5tuple);
2455 }
2456 memset(filter_info->fivetuple_mask, 0,
2457 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2458
2459 if (!rte_intr_allow_others(intr_handle))
2460 /* resume to the default handler */
2461 rte_intr_callback_register(intr_handle,
2462 ixgbe_dev_interrupt_handler,
2463 (void *)dev);
2464
2465 /* Clean datapath event and queue/vec mapping */
2466 rte_intr_efd_disable(intr_handle);
2467 if (intr_handle->intr_vec != NULL) {
2468 rte_free(intr_handle->intr_vec);
2469 intr_handle->intr_vec = NULL;
2470 }
2471}
2472
2473/*
2474 * Set device link up: enable tx.
2475 */
2476static int
2477ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2478{
2479 struct ixgbe_hw *hw =
2480 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2481 if (hw->mac.type == ixgbe_mac_82599EB) {
2482#ifdef RTE_NIC_BYPASS
2483 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2484 /* Not suported in bypass mode */
2485 PMD_INIT_LOG(ERR, "Set link up is not supported "
2486 "by device id 0x%x", hw->device_id);
2487 return -ENOTSUP;
2488 }
2489#endif
2490 }
2491
2492 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2493 /* Turn on the copper */
2494 ixgbe_set_phy_power(hw, true);
2495 } else {
2496 /* Turn on the laser */
2497 ixgbe_enable_tx_laser(hw);
2498 }
2499
2500 return 0;
2501}
2502
2503/*
2504 * Set device link down: disable tx.
2505 */
2506static int
2507ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2508{
2509 struct ixgbe_hw *hw =
2510 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2511 if (hw->mac.type == ixgbe_mac_82599EB) {
2512#ifdef RTE_NIC_BYPASS
2513 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2514 /* Not suported in bypass mode */
2515 PMD_INIT_LOG(ERR, "Set link down is not supported "
2516 "by device id 0x%x", hw->device_id);
2517 return -ENOTSUP;
2518 }
2519#endif
2520 }
2521
2522 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2523 /* Turn off the copper */
2524 ixgbe_set_phy_power(hw, false);
2525 } else {
2526 /* Turn off the laser */
2527 ixgbe_disable_tx_laser(hw);
2528 }
2529
2530 return 0;
2531}
2532
2533/*
2534 * Reest and stop device.
2535 */
2536static void
2537ixgbe_dev_close(struct rte_eth_dev *dev)
2538{
2539 struct ixgbe_hw *hw =
2540 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541
2542 PMD_INIT_FUNC_TRACE();
2543
2544 ixgbe_pf_reset_hw(hw);
2545
2546 ixgbe_dev_stop(dev);
2547 hw->adapter_stopped = 1;
2548
2549 ixgbe_dev_free_queues(dev);
2550
2551 ixgbe_disable_pcie_master(hw);
2552
2553 /* reprogram the RAR[0] in case user changed it. */
2554 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2555}
2556
2557static void
2558ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2559 struct ixgbe_hw_stats *hw_stats,
2560 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2561 uint64_t *total_qprc, uint64_t *total_qprdc)
2562{
2563 uint32_t bprc, lxon, lxoff, total;
2564 uint32_t delta_gprc = 0;
2565 unsigned i;
2566 /* Workaround for RX byte count not including CRC bytes when CRC
2567+ * strip is enabled. CRC bytes are removed from counters when crc_strip
2568 * is disabled.
2569+ */
2570 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2571 IXGBE_HLREG0_RXCRCSTRP);
2572
2573 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2574 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2575 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2576 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2577
2578 for (i = 0; i < 8; i++) {
2579 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2580
2581 /* global total per queue */
2582 hw_stats->mpc[i] += mp;
2583 /* Running comprehensive total for stats display */
2584 *total_missed_rx += hw_stats->mpc[i];
2585 if (hw->mac.type == ixgbe_mac_82598EB) {
2586 hw_stats->rnbc[i] +=
2587 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2588 hw_stats->pxonrxc[i] +=
2589 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2590 hw_stats->pxoffrxc[i] +=
2591 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2592 } else {
2593 hw_stats->pxonrxc[i] +=
2594 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2595 hw_stats->pxoffrxc[i] +=
2596 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2597 hw_stats->pxon2offc[i] +=
2598 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2599 }
2600 hw_stats->pxontxc[i] +=
2601 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2602 hw_stats->pxofftxc[i] +=
2603 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2604 }
2605 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2606 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2607 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2608 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2609
2610 delta_gprc += delta_qprc;
2611
2612 hw_stats->qprc[i] += delta_qprc;
2613 hw_stats->qptc[i] += delta_qptc;
2614
2615 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2616 hw_stats->qbrc[i] +=
2617 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2618 if (crc_strip == 0)
2619 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2620
2621 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2622 hw_stats->qbtc[i] +=
2623 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2624
2625 hw_stats->qprdc[i] += delta_qprdc;
2626 *total_qprdc += hw_stats->qprdc[i];
2627
2628 *total_qprc += hw_stats->qprc[i];
2629 *total_qbrc += hw_stats->qbrc[i];
2630 }
2631 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2632 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2633 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2634
2635 /*
2636 * An errata states that gprc actually counts good + missed packets:
2637 * Workaround to set gprc to summated queue packet receives
2638 */
2639 hw_stats->gprc = *total_qprc;
2640
2641 if (hw->mac.type != ixgbe_mac_82598EB) {
2642 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2643 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2644 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2645 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2646 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2647 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2648 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2649 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2650 } else {
2651 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2652 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2653 /* 82598 only has a counter in the high register */
2654 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2655 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2656 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2657 }
2658 uint64_t old_tpr = hw_stats->tpr;
2659
2660 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2661 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2662
2663 if (crc_strip == 0)
2664 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2665
2666 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2667 hw_stats->gptc += delta_gptc;
2668 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2669 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2670
2671 /*
2672 * Workaround: mprc hardware is incorrectly counting
2673 * broadcasts, so for now we subtract those.
2674 */
2675 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2676 hw_stats->bprc += bprc;
2677 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2678 if (hw->mac.type == ixgbe_mac_82598EB)
2679 hw_stats->mprc -= bprc;
2680
2681 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2682 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2683 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2684 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2685 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2686 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2687
2688 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2689 hw_stats->lxontxc += lxon;
2690 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2691 hw_stats->lxofftxc += lxoff;
2692 total = lxon + lxoff;
2693
2694 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2695 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2696 hw_stats->gptc -= total;
2697 hw_stats->mptc -= total;
2698 hw_stats->ptc64 -= total;
2699 hw_stats->gotc -= total * ETHER_MIN_LEN;
2700
2701 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2702 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2703 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2704 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2705 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2706 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2707 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2708 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2709 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2710 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2711 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2712 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2713 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2714 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2715 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2716 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2717 /* Only read FCOE on 82599 */
2718 if (hw->mac.type != ixgbe_mac_82598EB) {
2719 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2720 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2721 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2722 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2723 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2724 }
2725
2726 /* Flow Director Stats registers */
2727 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2728 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2729}
2730
2731/*
2732 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2733 */
2734static void
2735ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2736{
2737 struct ixgbe_hw *hw =
2738 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2739 struct ixgbe_hw_stats *hw_stats =
2740 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2741 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2742 unsigned i;
2743
2744 total_missed_rx = 0;
2745 total_qbrc = 0;
2746 total_qprc = 0;
2747 total_qprdc = 0;
2748
2749 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2750 &total_qprc, &total_qprdc);
2751
2752 if (stats == NULL)
2753 return;
2754
2755 /* Fill out the rte_eth_stats statistics structure */
2756 stats->ipackets = total_qprc;
2757 stats->ibytes = total_qbrc;
2758 stats->opackets = hw_stats->gptc;
2759 stats->obytes = hw_stats->gotc;
2760
2761 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2762 stats->q_ipackets[i] = hw_stats->qprc[i];
2763 stats->q_opackets[i] = hw_stats->qptc[i];
2764 stats->q_ibytes[i] = hw_stats->qbrc[i];
2765 stats->q_obytes[i] = hw_stats->qbtc[i];
2766 stats->q_errors[i] = hw_stats->qprdc[i];
2767 }
2768
2769 /* Rx Errors */
2770 stats->imissed = total_missed_rx;
2771 stats->ierrors = hw_stats->crcerrs +
2772 hw_stats->mspdc +
2773 hw_stats->rlec +
2774 hw_stats->ruc +
2775 hw_stats->roc +
2776 hw_stats->illerrc +
2777 hw_stats->errbc +
2778 hw_stats->rfc +
2779 hw_stats->fccrc +
2780 hw_stats->fclast;
2781
2782 /* Tx Errors */
2783 stats->oerrors = 0;
2784}
2785
2786static void
2787ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2788{
2789 struct ixgbe_hw_stats *stats =
2790 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2791
2792 /* HW registers are cleared on read */
2793 ixgbe_dev_stats_get(dev, NULL);
2794
2795 /* Reset software totals */
2796 memset(stats, 0, sizeof(*stats));
2797}
2798
2799/* This function calculates the number of xstats based on the current config */
2800static unsigned
2801ixgbe_xstats_calc_num(void) {
2802 return IXGBE_NB_HW_STATS +
2803 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2804 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2805}
2806
2807static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2808 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2809{
2810 const unsigned cnt_stats = ixgbe_xstats_calc_num();
2811 unsigned stat, i, count;
2812
2813 if (xstats_names != NULL) {
2814 count = 0;
2815
2816 /* Note: limit >= cnt_stats checked upstream
2817 * in rte_eth_xstats_names()
2818 */
2819
2820 /* Extended stats from ixgbe_hw_stats */
2821 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2822 snprintf(xstats_names[count].name,
2823 sizeof(xstats_names[count].name),
2824 "%s",
2825 rte_ixgbe_stats_strings[i].name);
2826 count++;
2827 }
2828
2829 /* RX Priority Stats */
2830 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2831 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2832 snprintf(xstats_names[count].name,
2833 sizeof(xstats_names[count].name),
2834 "rx_priority%u_%s", i,
2835 rte_ixgbe_rxq_strings[stat].name);
2836 count++;
2837 }
2838 }
2839
2840 /* TX Priority Stats */
2841 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2842 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2843 snprintf(xstats_names[count].name,
2844 sizeof(xstats_names[count].name),
2845 "tx_priority%u_%s", i,
2846 rte_ixgbe_txq_strings[stat].name);
2847 count++;
2848 }
2849 }
2850 }
2851 return cnt_stats;
2852}
2853
2854static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2855 struct rte_eth_xstat_name *xstats_names, unsigned limit)
2856{
2857 unsigned i;
2858
2859 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2860 return -ENOMEM;
2861
2862 if (xstats_names != NULL)
2863 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2864 snprintf(xstats_names[i].name,
2865 sizeof(xstats_names[i].name),
2866 "%s", rte_ixgbevf_stats_strings[i].name);
2867 return IXGBEVF_NB_XSTATS;
2868}
2869
2870static int
2871ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2872 unsigned n)
2873{
2874 struct ixgbe_hw *hw =
2875 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876 struct ixgbe_hw_stats *hw_stats =
2877 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2878 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2879 unsigned i, stat, count = 0;
2880
2881 count = ixgbe_xstats_calc_num();
2882
2883 if (n < count)
2884 return count;
2885
2886 total_missed_rx = 0;
2887 total_qbrc = 0;
2888 total_qprc = 0;
2889 total_qprdc = 0;
2890
2891 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2892 &total_qprc, &total_qprdc);
2893
2894 /* If this is a reset xstats is NULL, and we have cleared the
2895 * registers by reading them.
2896 */
2897 if (!xstats)
2898 return 0;
2899
2900 /* Extended stats from ixgbe_hw_stats */
2901 count = 0;
2902 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2903 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2904 rte_ixgbe_stats_strings[i].offset);
2905 count++;
2906 }
2907
2908 /* RX Priority Stats */
2909 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2910 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2911 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2912 rte_ixgbe_rxq_strings[stat].offset +
2913 (sizeof(uint64_t) * i));
2914 count++;
2915 }
2916 }
2917
2918 /* TX Priority Stats */
2919 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2920 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2921 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2922 rte_ixgbe_txq_strings[stat].offset +
2923 (sizeof(uint64_t) * i));
2924 count++;
2925 }
2926 }
2927 return count;
2928}
2929
2930static void
2931ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2932{
2933 struct ixgbe_hw_stats *stats =
2934 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2935
2936 unsigned count = ixgbe_xstats_calc_num();
2937
2938 /* HW registers are cleared on read */
2939 ixgbe_dev_xstats_get(dev, NULL, count);
2940
2941 /* Reset software totals */
2942 memset(stats, 0, sizeof(*stats));
2943}
2944
2945static void
2946ixgbevf_update_stats(struct rte_eth_dev *dev)
2947{
2948 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2949 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2950 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2951
2952 /* Good Rx packet, include VF loopback */
2953 UPDATE_VF_STAT(IXGBE_VFGPRC,
2954 hw_stats->last_vfgprc, hw_stats->vfgprc);
2955
2956 /* Good Rx octets, include VF loopback */
2957 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2958 hw_stats->last_vfgorc, hw_stats->vfgorc);
2959
2960 /* Good Tx packet, include VF loopback */
2961 UPDATE_VF_STAT(IXGBE_VFGPTC,
2962 hw_stats->last_vfgptc, hw_stats->vfgptc);
2963
2964 /* Good Tx octets, include VF loopback */
2965 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2966 hw_stats->last_vfgotc, hw_stats->vfgotc);
2967
2968 /* Rx Multicst Packet */
2969 UPDATE_VF_STAT(IXGBE_VFMPRC,
2970 hw_stats->last_vfmprc, hw_stats->vfmprc);
2971}
2972
2973static int
2974ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2975 unsigned n)
2976{
2977 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2978 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2979 unsigned i;
2980
2981 if (n < IXGBEVF_NB_XSTATS)
2982 return IXGBEVF_NB_XSTATS;
2983
2984 ixgbevf_update_stats(dev);
2985
2986 if (!xstats)
2987 return 0;
2988
2989 /* Extended stats */
2990 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2991 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2992 rte_ixgbevf_stats_strings[i].offset);
2993 }
2994
2995 return IXGBEVF_NB_XSTATS;
2996}
2997
2998static void
2999ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3000{
3001 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3002 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3003
3004 ixgbevf_update_stats(dev);
3005
3006 if (stats == NULL)
3007 return;
3008
3009 stats->ipackets = hw_stats->vfgprc;
3010 stats->ibytes = hw_stats->vfgorc;
3011 stats->opackets = hw_stats->vfgptc;
3012 stats->obytes = hw_stats->vfgotc;
3013}
3014
3015static void
3016ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3017{
3018 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3019 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3020
3021 /* Sync HW register to the last stats */
3022 ixgbevf_dev_stats_get(dev, NULL);
3023
3024 /* reset HW current stats*/
3025 hw_stats->vfgprc = 0;
3026 hw_stats->vfgorc = 0;
3027 hw_stats->vfgptc = 0;
3028 hw_stats->vfgotc = 0;
3029}
3030
3031static void
3032ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3033{
3034 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3035 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3036
3037 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3038 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3039 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3040 /*
3041 * When DCB/VT is off, maximum number of queues changes,
3042 * except for 82598EB, which remains constant.
3043 */
3044 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3045 hw->mac.type != ixgbe_mac_82598EB)
3046 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3047 }
3048 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3049 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3050 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3051 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3052 dev_info->max_vfs = dev->pci_dev->max_vfs;
3053 if (hw->mac.type == ixgbe_mac_82598EB)
3054 dev_info->max_vmdq_pools = ETH_16_POOLS;
3055 else
3056 dev_info->max_vmdq_pools = ETH_64_POOLS;
3057 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3058 dev_info->rx_offload_capa =
3059 DEV_RX_OFFLOAD_VLAN_STRIP |
3060 DEV_RX_OFFLOAD_IPV4_CKSUM |
3061 DEV_RX_OFFLOAD_UDP_CKSUM |
3062 DEV_RX_OFFLOAD_TCP_CKSUM;
3063
3064 /*
3065 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3066 * mode.
3067 */
3068 if ((hw->mac.type == ixgbe_mac_82599EB ||
3069 hw->mac.type == ixgbe_mac_X540) &&
3070 !RTE_ETH_DEV_SRIOV(dev).active)
3071 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3072
3073 if (hw->mac.type == ixgbe_mac_X550 ||
3074 hw->mac.type == ixgbe_mac_X550EM_x ||
3075 hw->mac.type == ixgbe_mac_X550EM_a)
3076 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3077
3078 dev_info->tx_offload_capa =
3079 DEV_TX_OFFLOAD_VLAN_INSERT |
3080 DEV_TX_OFFLOAD_IPV4_CKSUM |
3081 DEV_TX_OFFLOAD_UDP_CKSUM |
3082 DEV_TX_OFFLOAD_TCP_CKSUM |
3083 DEV_TX_OFFLOAD_SCTP_CKSUM |
3084 DEV_TX_OFFLOAD_TCP_TSO;
3085
3086 if (hw->mac.type == ixgbe_mac_X550 ||
3087 hw->mac.type == ixgbe_mac_X550EM_x ||
3088 hw->mac.type == ixgbe_mac_X550EM_a)
3089 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3090
3091 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3092 .rx_thresh = {
3093 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3094 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3095 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3096 },
3097 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3098 .rx_drop_en = 0,
3099 };
3100
3101 dev_info->default_txconf = (struct rte_eth_txconf) {
3102 .tx_thresh = {
3103 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3104 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3105 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3106 },
3107 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3108 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3109 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3110 ETH_TXQ_FLAGS_NOOFFLOADS,
3111 };
3112
3113 dev_info->rx_desc_lim = rx_desc_lim;
3114 dev_info->tx_desc_lim = tx_desc_lim;
3115
3116 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3117 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3118 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3119
3120 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3121 if (hw->mac.type == ixgbe_mac_X540 ||
3122 hw->mac.type == ixgbe_mac_X540_vf ||
3123 hw->mac.type == ixgbe_mac_X550 ||
3124 hw->mac.type == ixgbe_mac_X550_vf) {
3125 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3126 }
3127}
3128
3129static const uint32_t *
3130ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3131{
3132 static const uint32_t ptypes[] = {
3133 /* For non-vec functions,
3134 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3135 * for vec functions,
3136 * refers to _recv_raw_pkts_vec().
3137 */
3138 RTE_PTYPE_L2_ETHER,
3139 RTE_PTYPE_L3_IPV4,
3140 RTE_PTYPE_L3_IPV4_EXT,
3141 RTE_PTYPE_L3_IPV6,
3142 RTE_PTYPE_L3_IPV6_EXT,
3143 RTE_PTYPE_L4_SCTP,
3144 RTE_PTYPE_L4_TCP,
3145 RTE_PTYPE_L4_UDP,
3146 RTE_PTYPE_TUNNEL_IP,
3147 RTE_PTYPE_INNER_L3_IPV6,
3148 RTE_PTYPE_INNER_L3_IPV6_EXT,
3149 RTE_PTYPE_INNER_L4_TCP,
3150 RTE_PTYPE_INNER_L4_UDP,
3151 RTE_PTYPE_UNKNOWN
3152 };
3153
3154 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3155 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3156 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3157 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3158 return ptypes;
3159 return NULL;
3160}
3161
3162static void
3163ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3164 struct rte_eth_dev_info *dev_info)
3165{
3166 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3167
3168 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3169 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3170 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3171 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3172 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3173 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3174 dev_info->max_vfs = dev->pci_dev->max_vfs;
3175 if (hw->mac.type == ixgbe_mac_82598EB)
3176 dev_info->max_vmdq_pools = ETH_16_POOLS;
3177 else
3178 dev_info->max_vmdq_pools = ETH_64_POOLS;
3179 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3180 DEV_RX_OFFLOAD_IPV4_CKSUM |
3181 DEV_RX_OFFLOAD_UDP_CKSUM |
3182 DEV_RX_OFFLOAD_TCP_CKSUM;
3183 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3184 DEV_TX_OFFLOAD_IPV4_CKSUM |
3185 DEV_TX_OFFLOAD_UDP_CKSUM |
3186 DEV_TX_OFFLOAD_TCP_CKSUM |
3187 DEV_TX_OFFLOAD_SCTP_CKSUM |
3188 DEV_TX_OFFLOAD_TCP_TSO;
3189
3190 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3191 .rx_thresh = {
3192 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3193 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3194 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3195 },
3196 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3197 .rx_drop_en = 0,
3198 };
3199
3200 dev_info->default_txconf = (struct rte_eth_txconf) {
3201 .tx_thresh = {
3202 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3203 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3204 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3205 },
3206 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3207 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3208 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3209 ETH_TXQ_FLAGS_NOOFFLOADS,
3210 };
3211
3212 dev_info->rx_desc_lim = rx_desc_lim;
3213 dev_info->tx_desc_lim = tx_desc_lim;
3214}
3215
3216/* return 0 means link status changed, -1 means not changed */
3217static int
3218ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3219{
3220 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3221 struct rte_eth_link link, old;
3222 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3223 int link_up;
3224 int diag;
3225
3226 link.link_status = ETH_LINK_DOWN;
3227 link.link_speed = 0;
3228 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3229 memset(&old, 0, sizeof(old));
3230 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3231
3232 hw->mac.get_link_status = true;
3233
3234 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3235 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3236 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3237 else
3238 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3239
3240 if (diag != 0) {
3241 link.link_speed = ETH_SPEED_NUM_100M;
3242 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3243 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3244 if (link.link_status == old.link_status)
3245 return -1;
3246 return 0;
3247 }
3248
3249 if (link_up == 0) {
3250 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3251 if (link.link_status == old.link_status)
3252 return -1;
3253 return 0;
3254 }
3255 link.link_status = ETH_LINK_UP;
3256 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3257
3258 switch (link_speed) {
3259 default:
3260 case IXGBE_LINK_SPEED_UNKNOWN:
3261 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3262 link.link_speed = ETH_SPEED_NUM_100M;
3263 break;
3264
3265 case IXGBE_LINK_SPEED_100_FULL:
3266 link.link_speed = ETH_SPEED_NUM_100M;
3267 break;
3268
3269 case IXGBE_LINK_SPEED_1GB_FULL:
3270 link.link_speed = ETH_SPEED_NUM_1G;
3271 break;
3272
3273 case IXGBE_LINK_SPEED_10GB_FULL:
3274 link.link_speed = ETH_SPEED_NUM_10G;
3275 break;
3276 }
3277 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3278
3279 if (link.link_status == old.link_status)
3280 return -1;
3281
3282 return 0;
3283}
3284
3285static void
3286ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3287{
3288 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3289 uint32_t fctrl;
3290
3291 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3292 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3293 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3294}
3295
3296static void
3297ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3298{
3299 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3300 uint32_t fctrl;
3301
3302 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3303 fctrl &= (~IXGBE_FCTRL_UPE);
3304 if (dev->data->all_multicast == 1)
3305 fctrl |= IXGBE_FCTRL_MPE;
3306 else
3307 fctrl &= (~IXGBE_FCTRL_MPE);
3308 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3309}
3310
3311static void
3312ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3313{
3314 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3315 uint32_t fctrl;
3316
3317 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3318 fctrl |= IXGBE_FCTRL_MPE;
3319 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3320}
3321
3322static void
3323ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3324{
3325 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3326 uint32_t fctrl;
3327
3328 if (dev->data->promiscuous == 1)
3329 return; /* must remain in all_multicast mode */
3330
3331 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3332 fctrl &= (~IXGBE_FCTRL_MPE);
3333 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3334}
3335
3336/**
3337 * It clears the interrupt causes and enables the interrupt.
3338 * It will be called once only during nic initialized.
3339 *
3340 * @param dev
3341 * Pointer to struct rte_eth_dev.
3342 *
3343 * @return
3344 * - On success, zero.
3345 * - On failure, a negative value.
3346 */
3347static int
3348ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3349{
3350 struct ixgbe_interrupt *intr =
3351 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3352
3353 ixgbe_dev_link_status_print(dev);
3354 intr->mask |= IXGBE_EICR_LSC;
3355
3356 return 0;
3357}
3358
3359/**
3360 * It clears the interrupt causes and enables the interrupt.
3361 * It will be called once only during nic initialized.
3362 *
3363 * @param dev
3364 * Pointer to struct rte_eth_dev.
3365 *
3366 * @return
3367 * - On success, zero.
3368 * - On failure, a negative value.
3369 */
3370static int
3371ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3372{
3373 struct ixgbe_interrupt *intr =
3374 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3375
3376 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3377
3378 return 0;
3379}
3380
3381/*
3382 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3383 *
3384 * @param dev
3385 * Pointer to struct rte_eth_dev.
3386 *
3387 * @return
3388 * - On success, zero.
3389 * - On failure, a negative value.
3390 */
3391static int
3392ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3393{
3394 uint32_t eicr;
3395 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3396 struct ixgbe_interrupt *intr =
3397 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3398
3399 /* clear all cause mask */
3400 ixgbe_disable_intr(hw);
3401
3402 /* read-on-clear nic registers here */
3403 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3404 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3405
3406 intr->flags = 0;
3407
3408 /* set flag for async link update */
3409 if (eicr & IXGBE_EICR_LSC)
3410 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3411
3412 if (eicr & IXGBE_EICR_MAILBOX)
3413 intr->flags |= IXGBE_FLAG_MAILBOX;
3414
3415 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3416 hw->phy.type == ixgbe_phy_x550em_ext_t &&
3417 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3418 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3419
3420 return 0;
3421}
3422
3423/**
3424 * It gets and then prints the link status.
3425 *
3426 * @param dev
3427 * Pointer to struct rte_eth_dev.
3428 *
3429 * @return
3430 * - On success, zero.
3431 * - On failure, a negative value.
3432 */
3433static void
3434ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3435{
3436 struct rte_eth_link link;
3437
3438 memset(&link, 0, sizeof(link));
3439 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3440 if (link.link_status) {
3441 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3442 (int)(dev->data->port_id),
3443 (unsigned)link.link_speed,
3444 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3445 "full-duplex" : "half-duplex");
3446 } else {
3447 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3448 (int)(dev->data->port_id));
3449 }
3450 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3451 dev->pci_dev->addr.domain,
3452 dev->pci_dev->addr.bus,
3453 dev->pci_dev->addr.devid,
3454 dev->pci_dev->addr.function);
3455}
3456
3457/*
3458 * It executes link_update after knowing an interrupt occurred.
3459 *
3460 * @param dev
3461 * Pointer to struct rte_eth_dev.
3462 *
3463 * @return
3464 * - On success, zero.
3465 * - On failure, a negative value.
3466 */
3467static int
3468ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3469{
3470 struct ixgbe_interrupt *intr =
3471 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3472 int64_t timeout;
3473 struct rte_eth_link link;
3474 int intr_enable_delay = false;
3475 struct ixgbe_hw *hw =
3476 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3477
3478 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3479
3480 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3481 ixgbe_pf_mbx_process(dev);
3482 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3483 }
3484
3485 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3486 ixgbe_handle_lasi(hw);
3487 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3488 }
3489
3490 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3491 /* get the link status before link update, for predicting later */
3492 memset(&link, 0, sizeof(link));
3493 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3494
3495 ixgbe_dev_link_update(dev, 0);
3496
3497 /* likely to up */
3498 if (!link.link_status)
3499 /* handle it 1 sec later, wait it being stable */
3500 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3501 /* likely to down */
3502 else
3503 /* handle it 4 sec later, wait it being stable */
3504 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3505
3506 ixgbe_dev_link_status_print(dev);
3507
3508 intr_enable_delay = true;
3509 }
3510
3511 if (intr_enable_delay) {
3512 if (rte_eal_alarm_set(timeout * 1000,
3513 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3514 PMD_DRV_LOG(ERR, "Error setting alarm");
3515 } else {
3516 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3517 ixgbe_enable_intr(dev);
3518 rte_intr_enable(&(dev->pci_dev->intr_handle));
3519 }
3520
3521
3522 return 0;
3523}
3524
3525/**
3526 * Interrupt handler which shall be registered for alarm callback for delayed
3527 * handling specific interrupt to wait for the stable nic state. As the
3528 * NIC interrupt state is not stable for ixgbe after link is just down,
3529 * it needs to wait 4 seconds to get the stable status.
3530 *
3531 * @param handle
3532 * Pointer to interrupt handle.
3533 * @param param
3534 * The address of parameter (struct rte_eth_dev *) regsitered before.
3535 *
3536 * @return
3537 * void
3538 */
3539static void
3540ixgbe_dev_interrupt_delayed_handler(void *param)
3541{
3542 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3543 struct ixgbe_interrupt *intr =
3544 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3545 struct ixgbe_hw *hw =
3546 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3547 uint32_t eicr;
3548
3549 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3550 if (eicr & IXGBE_EICR_MAILBOX)
3551 ixgbe_pf_mbx_process(dev);
3552
3553 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3554 ixgbe_handle_lasi(hw);
3555 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3556 }
3557
3558 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3559 ixgbe_dev_link_update(dev, 0);
3560 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3561 ixgbe_dev_link_status_print(dev);
3562 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3563 }
3564
3565 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3566 ixgbe_enable_intr(dev);
3567 rte_intr_enable(&(dev->pci_dev->intr_handle));
3568}
3569
3570/**
3571 * Interrupt handler triggered by NIC for handling
3572 * specific interrupt.
3573 *
3574 * @param handle
3575 * Pointer to interrupt handle.
3576 * @param param
3577 * The address of parameter (struct rte_eth_dev *) regsitered before.
3578 *
3579 * @return
3580 * void
3581 */
3582static void
3583ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3584 void *param)
3585{
3586 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3587
3588 ixgbe_dev_interrupt_get_status(dev);
3589 ixgbe_dev_interrupt_action(dev);
3590}
3591
3592static int
3593ixgbe_dev_led_on(struct rte_eth_dev *dev)
3594{
3595 struct ixgbe_hw *hw;
3596
3597 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3598 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3599}
3600
3601static int
3602ixgbe_dev_led_off(struct rte_eth_dev *dev)
3603{
3604 struct ixgbe_hw *hw;
3605
3606 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3607 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3608}
3609
3610static int
3611ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3612{
3613 struct ixgbe_hw *hw;
3614 uint32_t mflcn_reg;
3615 uint32_t fccfg_reg;
3616 int rx_pause;
3617 int tx_pause;
3618
3619 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3620
3621 fc_conf->pause_time = hw->fc.pause_time;
3622 fc_conf->high_water = hw->fc.high_water[0];
3623 fc_conf->low_water = hw->fc.low_water[0];
3624 fc_conf->send_xon = hw->fc.send_xon;
3625 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3626
3627 /*
3628 * Return rx_pause status according to actual setting of
3629 * MFLCN register.
3630 */
3631 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3632 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3633 rx_pause = 1;
3634 else
3635 rx_pause = 0;
3636
3637 /*
3638 * Return tx_pause status according to actual setting of
3639 * FCCFG register.
3640 */
3641 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3642 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3643 tx_pause = 1;
3644 else
3645 tx_pause = 0;
3646
3647 if (rx_pause && tx_pause)
3648 fc_conf->mode = RTE_FC_FULL;
3649 else if (rx_pause)
3650 fc_conf->mode = RTE_FC_RX_PAUSE;
3651 else if (tx_pause)
3652 fc_conf->mode = RTE_FC_TX_PAUSE;
3653 else
3654 fc_conf->mode = RTE_FC_NONE;
3655
3656 return 0;
3657}
3658
3659static int
3660ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3661{
3662 struct ixgbe_hw *hw;
3663 int err;
3664 uint32_t rx_buf_size;
3665 uint32_t max_high_water;
3666 uint32_t mflcn;
3667 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3668 ixgbe_fc_none,
3669 ixgbe_fc_rx_pause,
3670 ixgbe_fc_tx_pause,
3671 ixgbe_fc_full
3672 };
3673
3674 PMD_INIT_FUNC_TRACE();
3675
3676 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3677 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3678 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3679
3680 /*
3681 * At least reserve one Ethernet frame for watermark
3682 * high_water/low_water in kilo bytes for ixgbe
3683 */
3684 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3685 if ((fc_conf->high_water > max_high_water) ||
3686 (fc_conf->high_water < fc_conf->low_water)) {
3687 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3688 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3689 return -EINVAL;
3690 }
3691
3692 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3693 hw->fc.pause_time = fc_conf->pause_time;
3694 hw->fc.high_water[0] = fc_conf->high_water;
3695 hw->fc.low_water[0] = fc_conf->low_water;
3696 hw->fc.send_xon = fc_conf->send_xon;
3697 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3698
3699 err = ixgbe_fc_enable(hw);
3700
3701 /* Not negotiated is not an error case */
3702 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3703
3704 /* check if we want to forward MAC frames - driver doesn't have native
3705 * capability to do that, so we'll write the registers ourselves */
3706
3707 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3708
3709 /* set or clear MFLCN.PMCF bit depending on configuration */
3710 if (fc_conf->mac_ctrl_frame_fwd != 0)
3711 mflcn |= IXGBE_MFLCN_PMCF;
3712 else
3713 mflcn &= ~IXGBE_MFLCN_PMCF;
3714
3715 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3716 IXGBE_WRITE_FLUSH(hw);
3717
3718 return 0;
3719 }
3720
3721 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3722 return -EIO;
3723}
3724
3725/**
3726 * ixgbe_pfc_enable_generic - Enable flow control
3727 * @hw: pointer to hardware structure
3728 * @tc_num: traffic class number
3729 * Enable flow control according to the current settings.
3730 */
3731static int
3732ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3733{
3734 int ret_val = 0;
3735 uint32_t mflcn_reg, fccfg_reg;
3736 uint32_t reg;
3737 uint32_t fcrtl, fcrth;
3738 uint8_t i;
3739 uint8_t nb_rx_en;
3740
3741 /* Validate the water mark configuration */
3742 if (!hw->fc.pause_time) {
3743 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3744 goto out;
3745 }
3746
3747 /* Low water mark of zero causes XOFF floods */
3748 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3749 /* High/Low water can not be 0 */
3750 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3751 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3752 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3753 goto out;
3754 }
3755
3756 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3757 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3758 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3759 goto out;
3760 }
3761 }
3762 /* Negotiate the fc mode to use */
3763 ixgbe_fc_autoneg(hw);
3764
3765 /* Disable any previous flow control settings */
3766 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3767 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3768
3769 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3770 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3771
3772 switch (hw->fc.current_mode) {
3773 case ixgbe_fc_none:
3774 /*
3775 * If the count of enabled RX Priority Flow control >1,
3776 * and the TX pause can not be disabled
3777 */
3778 nb_rx_en = 0;
3779 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3780 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3781 if (reg & IXGBE_FCRTH_FCEN)
3782 nb_rx_en++;
3783 }
3784 if (nb_rx_en > 1)
3785 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3786 break;
3787 case ixgbe_fc_rx_pause:
3788 /*
3789 * Rx Flow control is enabled and Tx Flow control is
3790 * disabled by software override. Since there really
3791 * isn't a way to advertise that we are capable of RX
3792 * Pause ONLY, we will advertise that we support both
3793 * symmetric and asymmetric Rx PAUSE. Later, we will
3794 * disable the adapter's ability to send PAUSE frames.
3795 */
3796 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3797 /*
3798 * If the count of enabled RX Priority Flow control >1,
3799 * and the TX pause can not be disabled
3800 */
3801 nb_rx_en = 0;
3802 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3803 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3804 if (reg & IXGBE_FCRTH_FCEN)
3805 nb_rx_en++;
3806 }
3807 if (nb_rx_en > 1)
3808 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3809 break;
3810 case ixgbe_fc_tx_pause:
3811 /*
3812 * Tx Flow control is enabled, and Rx Flow control is
3813 * disabled by software override.
3814 */
3815 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3816 break;
3817 case ixgbe_fc_full:
3818 /* Flow control (both Rx and Tx) is enabled by SW override. */
3819 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3820 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3821 break;
3822 default:
3823 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3824 ret_val = IXGBE_ERR_CONFIG;
3825 goto out;
3826 }
3827
3828 /* Set 802.3x based flow control settings. */
3829 mflcn_reg |= IXGBE_MFLCN_DPF;
3830 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3831 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3832
3833 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3834 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3835 hw->fc.high_water[tc_num]) {
3836 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3837 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3838 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3839 } else {
3840 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3841 /*
3842 * In order to prevent Tx hangs when the internal Tx
3843 * switch is enabled we must set the high water mark
3844 * to the maximum FCRTH value. This allows the Tx
3845 * switch to function even under heavy Rx workloads.
3846 */
3847 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3848 }
3849 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3850
3851 /* Configure pause time (2 TCs per register) */
3852 reg = hw->fc.pause_time * 0x00010001;
3853 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3854 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3855
3856 /* Configure flow control refresh threshold value */
3857 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3858
3859out:
3860 return ret_val;
3861}
3862
3863static int
3864ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
3865{
3866 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3867 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3868
3869 if (hw->mac.type != ixgbe_mac_82598EB) {
3870 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
3871 }
3872 return ret_val;
3873}
3874
3875static int
3876ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3877{
3878 int err;
3879 uint32_t rx_buf_size;
3880 uint32_t max_high_water;
3881 uint8_t tc_num;
3882 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3883 struct ixgbe_hw *hw =
3884 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3885 struct ixgbe_dcb_config *dcb_config =
3886 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3887
3888 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3889 ixgbe_fc_none,
3890 ixgbe_fc_rx_pause,
3891 ixgbe_fc_tx_pause,
3892 ixgbe_fc_full
3893 };
3894
3895 PMD_INIT_FUNC_TRACE();
3896
3897 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3898 tc_num = map[pfc_conf->priority];
3899 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3900 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3901 /*
3902 * At least reserve one Ethernet frame for watermark
3903 * high_water/low_water in kilo bytes for ixgbe
3904 */
3905 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3906 if ((pfc_conf->fc.high_water > max_high_water) ||
3907 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3908 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3909 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3910 return -EINVAL;
3911 }
3912
3913 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3914 hw->fc.pause_time = pfc_conf->fc.pause_time;
3915 hw->fc.send_xon = pfc_conf->fc.send_xon;
3916 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
3917 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3918
3919 err = ixgbe_dcb_pfc_enable(dev, tc_num);
3920
3921 /* Not negotiated is not an error case */
3922 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3923 return 0;
3924
3925 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3926 return -EIO;
3927}
3928
3929static int
3930ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3931 struct rte_eth_rss_reta_entry64 *reta_conf,
3932 uint16_t reta_size)
3933{
3934 uint16_t i, sp_reta_size;
3935 uint8_t j, mask;
3936 uint32_t reta, r;
3937 uint16_t idx, shift;
3938 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3939 uint32_t reta_reg;
3940
3941 PMD_INIT_FUNC_TRACE();
3942
3943 if (!ixgbe_rss_update_sp(hw->mac.type)) {
3944 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3945 "NIC.");
3946 return -ENOTSUP;
3947 }
3948
3949 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3950 if (reta_size != sp_reta_size) {
3951 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3952 "(%d) doesn't match the number hardware can supported "
3953 "(%d)\n", reta_size, sp_reta_size);
3954 return -EINVAL;
3955 }
3956
3957 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3958 idx = i / RTE_RETA_GROUP_SIZE;
3959 shift = i % RTE_RETA_GROUP_SIZE;
3960 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3961 IXGBE_4_BIT_MASK);
3962 if (!mask)
3963 continue;
3964 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3965 if (mask == IXGBE_4_BIT_MASK)
3966 r = 0;
3967 else
3968 r = IXGBE_READ_REG(hw, reta_reg);
3969 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3970 if (mask & (0x1 << j))
3971 reta |= reta_conf[idx].reta[shift + j] <<
3972 (CHAR_BIT * j);
3973 else
3974 reta |= r & (IXGBE_8_BIT_MASK <<
3975 (CHAR_BIT * j));
3976 }
3977 IXGBE_WRITE_REG(hw, reta_reg, reta);
3978 }
3979
3980 return 0;
3981}
3982
3983static int
3984ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3985 struct rte_eth_rss_reta_entry64 *reta_conf,
3986 uint16_t reta_size)
3987{
3988 uint16_t i, sp_reta_size;
3989 uint8_t j, mask;
3990 uint32_t reta;
3991 uint16_t idx, shift;
3992 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3993 uint32_t reta_reg;
3994
3995 PMD_INIT_FUNC_TRACE();
3996 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3997 if (reta_size != sp_reta_size) {
3998 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3999 "(%d) doesn't match the number hardware can supported "
4000 "(%d)\n", reta_size, sp_reta_size);
4001 return -EINVAL;
4002 }
4003
4004 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4005 idx = i / RTE_RETA_GROUP_SIZE;
4006 shift = i % RTE_RETA_GROUP_SIZE;
4007 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4008 IXGBE_4_BIT_MASK);
4009 if (!mask)
4010 continue;
4011
4012 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4013 reta = IXGBE_READ_REG(hw, reta_reg);
4014 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4015 if (mask & (0x1 << j))
4016 reta_conf[idx].reta[shift + j] =
4017 ((reta >> (CHAR_BIT * j)) &
4018 IXGBE_8_BIT_MASK);
4019 }
4020 }
4021
4022 return 0;
4023}
4024
4025static void
4026ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4027 uint32_t index, uint32_t pool)
4028{
4029 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4030 uint32_t enable_addr = 1;
4031
4032 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4033}
4034
4035static void
4036ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4037{
4038 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4039
4040 ixgbe_clear_rar(hw, index);
4041}
4042
4043static void
4044ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4045{
4046 ixgbe_remove_rar(dev, 0);
4047
4048 ixgbe_add_rar(dev, addr, 0, 0);
4049}
4050
4051int
4052rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4053 struct ether_addr *mac_addr)
4054{
4055 struct ixgbe_hw *hw;
4056 struct ixgbe_vf_info *vfinfo;
4057 int rar_entry;
4058 uint8_t *new_mac = (uint8_t *)(mac_addr);
4059 struct rte_eth_dev *dev;
4060 struct rte_eth_dev_info dev_info;
4061
4062 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4063
4064 dev = &rte_eth_devices[port];
4065 rte_eth_dev_info_get(port, &dev_info);
4066
4067 if (vf >= dev_info.max_vfs)
4068 return -EINVAL;
4069
4070 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4071 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4072 rar_entry = hw->mac.num_rar_entries - (vf + 1);
4073
4074 if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4075 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4076 ETHER_ADDR_LEN);
4077 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4078 IXGBE_RAH_AV);
4079 }
4080 return -EINVAL;
4081}
4082
4083static int
4084ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4085{
4086 uint32_t hlreg0;
4087 uint32_t maxfrs;
4088 struct ixgbe_hw *hw;
4089 struct rte_eth_dev_info dev_info;
4090 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4091
4092 ixgbe_dev_info_get(dev, &dev_info);
4093
4094 /* check that mtu is within the allowed range */
4095 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4096 return -EINVAL;
4097
4098 /* refuse mtu that requires the support of scattered packets when this
4099 * feature has not been enabled before.
4100 */
4101 if (!dev->data->scattered_rx &&
4102 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4103 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4104 return -EINVAL;
4105
4106 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4107 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4108
4109 /* switch to jumbo mode if needed */
4110 if (frame_size > ETHER_MAX_LEN) {
4111 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4112 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4113 } else {
4114 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4115 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4116 }
4117 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4118
4119 /* update max frame size */
4120 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4121
4122 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4123 maxfrs &= 0x0000FFFF;
4124 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4125 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4126
4127 return 0;
4128}
4129
4130/*
4131 * Virtual Function operations
4132 */
4133static void
4134ixgbevf_intr_disable(struct ixgbe_hw *hw)
4135{
4136 PMD_INIT_FUNC_TRACE();
4137
4138 /* Clear interrupt mask to stop from interrupts being generated */
4139 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4140
4141 IXGBE_WRITE_FLUSH(hw);
4142}
4143
4144static void
4145ixgbevf_intr_enable(struct ixgbe_hw *hw)
4146{
4147 PMD_INIT_FUNC_TRACE();
4148
4149 /* VF enable interrupt autoclean */
4150 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4151 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4152 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4153
4154 IXGBE_WRITE_FLUSH(hw);
4155}
4156
4157static int
4158ixgbevf_dev_configure(struct rte_eth_dev *dev)
4159{
4160 struct rte_eth_conf *conf = &dev->data->dev_conf;
4161 struct ixgbe_adapter *adapter =
4162 (struct ixgbe_adapter *)dev->data->dev_private;
4163
4164 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4165 dev->data->port_id);
4166
4167 /*
4168 * VF has no ability to enable/disable HW CRC
4169 * Keep the persistent behavior the same as Host PF
4170 */
4171#ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4172 if (!conf->rxmode.hw_strip_crc) {
4173 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4174 conf->rxmode.hw_strip_crc = 1;
4175 }
4176#else
4177 if (conf->rxmode.hw_strip_crc) {
4178 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4179 conf->rxmode.hw_strip_crc = 0;
4180 }
4181#endif
4182
4183 /*
4184 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4185 * allocation or vector Rx preconditions we will reset it.
4186 */
4187 adapter->rx_bulk_alloc_allowed = true;
4188 adapter->rx_vec_allowed = true;
4189
4190 return 0;
4191}
4192
4193static int
4194ixgbevf_dev_start(struct rte_eth_dev *dev)
4195{
4196 struct ixgbe_hw *hw =
4197 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4198 uint32_t intr_vector = 0;
4199 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4200
4201 int err, mask = 0;
4202
4203 PMD_INIT_FUNC_TRACE();
4204
4205 hw->mac.ops.reset_hw(hw);
4206 hw->mac.get_link_status = true;
4207
4208 /* negotiate mailbox API version to use with the PF. */
4209 ixgbevf_negotiate_api(hw);
4210
4211 ixgbevf_dev_tx_init(dev);
4212
4213 /* This can fail when allocating mbufs for descriptor rings */
4214 err = ixgbevf_dev_rx_init(dev);
4215 if (err) {
4216 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4217 ixgbe_dev_clear_queues(dev);
4218 return err;
4219 }
4220
4221 /* Set vfta */
4222 ixgbevf_set_vfta_all(dev, 1);
4223
4224 /* Set HW strip */
4225 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4226 ETH_VLAN_EXTEND_MASK;
4227 ixgbevf_vlan_offload_set(dev, mask);
4228
4229 ixgbevf_dev_rxtx_start(dev);
4230
4231 /* check and configure queue intr-vector mapping */
4232 if (dev->data->dev_conf.intr_conf.rxq != 0) {
4233 intr_vector = dev->data->nb_rx_queues;
4234 if (rte_intr_efd_enable(intr_handle, intr_vector))
4235 return -1;
4236 }
4237
4238 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4239 intr_handle->intr_vec =
4240 rte_zmalloc("intr_vec",
4241 dev->data->nb_rx_queues * sizeof(int), 0);
4242 if (intr_handle->intr_vec == NULL) {
4243 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4244 " intr_vec\n", dev->data->nb_rx_queues);
4245 return -ENOMEM;
4246 }
4247 }
4248 ixgbevf_configure_msix(dev);
4249
4250 rte_intr_enable(intr_handle);
4251
4252 /* Re-enable interrupt for VF */
4253 ixgbevf_intr_enable(hw);
4254
4255 return 0;
4256}
4257
4258static void
4259ixgbevf_dev_stop(struct rte_eth_dev *dev)
4260{
4261 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4262 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4263
4264 PMD_INIT_FUNC_TRACE();
4265
4266 ixgbevf_intr_disable(hw);
4267
4268 hw->adapter_stopped = 1;
4269 ixgbe_stop_adapter(hw);
4270
4271 /*
4272 * Clear what we set, but we still keep shadow_vfta to
4273 * restore after device starts
4274 */
4275 ixgbevf_set_vfta_all(dev, 0);
4276
4277 /* Clear stored conf */
4278 dev->data->scattered_rx = 0;
4279
4280 ixgbe_dev_clear_queues(dev);
4281
4282 /* Clean datapath event and queue/vec mapping */
4283 rte_intr_efd_disable(intr_handle);
4284 if (intr_handle->intr_vec != NULL) {
4285 rte_free(intr_handle->intr_vec);
4286 intr_handle->intr_vec = NULL;
4287 }
4288}
4289
4290static void
4291ixgbevf_dev_close(struct rte_eth_dev *dev)
4292{
4293 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4294
4295 PMD_INIT_FUNC_TRACE();
4296
4297 ixgbe_reset_hw(hw);
4298
4299 ixgbevf_dev_stop(dev);
4300
4301 ixgbe_dev_free_queues(dev);
4302
4303 /**
4304 * Remove the VF MAC address ro ensure
4305 * that the VF traffic goes to the PF
4306 * after stop, close and detach of the VF
4307 **/
4308 ixgbevf_remove_mac_addr(dev, 0);
4309}
4310
4311static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4312{
4313 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4314 struct ixgbe_vfta *shadow_vfta =
4315 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4316 int i = 0, j = 0, vfta = 0, mask = 1;
4317
4318 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4319 vfta = shadow_vfta->vfta[i];
4320 if (vfta) {
4321 mask = 1;
4322 for (j = 0; j < 32; j++) {
4323 if (vfta & mask)
4324 ixgbe_set_vfta(hw, (i<<5)+j, 0,
4325 on, false);
4326 mask <<= 1;
4327 }
4328 }
4329 }
4330
4331}
4332
4333static int
4334ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4335{
4336 struct ixgbe_hw *hw =
4337 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4338 struct ixgbe_vfta *shadow_vfta =
4339 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4340 uint32_t vid_idx = 0;
4341 uint32_t vid_bit = 0;
4342 int ret = 0;
4343
4344 PMD_INIT_FUNC_TRACE();
4345
4346 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4347 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4348 if (ret) {
4349 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4350 return ret;
4351 }
4352 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4353 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4354
4355 /* Save what we set and retore it after device reset */
4356 if (on)
4357 shadow_vfta->vfta[vid_idx] |= vid_bit;
4358 else
4359 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4360
4361 return 0;
4362}
4363
4364static void
4365ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4366{
4367 struct ixgbe_hw *hw =
4368 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4369 uint32_t ctrl;
4370
4371 PMD_INIT_FUNC_TRACE();
4372
4373 if (queue >= hw->mac.max_rx_queues)
4374 return;
4375
4376 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4377 if (on)
4378 ctrl |= IXGBE_RXDCTL_VME;
4379 else
4380 ctrl &= ~IXGBE_RXDCTL_VME;
4381 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4382
4383 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4384}
4385
4386static void
4387ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4388{
4389 struct ixgbe_hw *hw =
4390 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4391 uint16_t i;
4392 int on = 0;
4393
4394 /* VF function only support hw strip feature, others are not support */
4395 if (mask & ETH_VLAN_STRIP_MASK) {
4396 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4397
4398 for (i = 0; i < hw->mac.max_rx_queues; i++)
4399 ixgbevf_vlan_strip_queue_set(dev, i, on);
4400 }
4401}
4402
4403static int
4404ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4405{
4406 uint32_t reg_val;
4407
4408 /* we only need to do this if VMDq is enabled */
4409 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4410 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4411 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4412 return -1;
4413 }
4414
4415 return 0;
4416}
4417
4418static uint32_t
4419ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4420{
4421 uint32_t vector = 0;
4422
4423 switch (hw->mac.mc_filter_type) {
4424 case 0: /* use bits [47:36] of the address */
4425 vector = ((uc_addr->addr_bytes[4] >> 4) |
4426 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4427 break;
4428 case 1: /* use bits [46:35] of the address */
4429 vector = ((uc_addr->addr_bytes[4] >> 3) |
4430 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4431 break;
4432 case 2: /* use bits [45:34] of the address */
4433 vector = ((uc_addr->addr_bytes[4] >> 2) |
4434 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4435 break;
4436 case 3: /* use bits [43:32] of the address */
4437 vector = ((uc_addr->addr_bytes[4]) |
4438 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4439 break;
4440 default: /* Invalid mc_filter_type */
4441 break;
4442 }
4443
4444 /* vector can only be 12-bits or boundary will be exceeded */
4445 vector &= 0xFFF;
4446 return vector;
4447}
4448
4449static int
4450ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4451 uint8_t on)
4452{
4453 uint32_t vector;
4454 uint32_t uta_idx;
4455 uint32_t reg_val;
4456 uint32_t uta_shift;
4457 uint32_t rc;
4458 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4459 const uint32_t ixgbe_uta_bit_shift = 5;
4460 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4461 const uint32_t bit1 = 0x1;
4462
4463 struct ixgbe_hw *hw =
4464 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4465 struct ixgbe_uta_info *uta_info =
4466 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4467
4468 /* The UTA table only exists on 82599 hardware and newer */
4469 if (hw->mac.type < ixgbe_mac_82599EB)
4470 return -ENOTSUP;
4471
4472 vector = ixgbe_uta_vector(hw, mac_addr);
4473 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4474 uta_shift = vector & ixgbe_uta_bit_mask;
4475
4476 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4477 if (rc == on)
4478 return 0;
4479
4480 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4481 if (on) {
4482 uta_info->uta_in_use++;
4483 reg_val |= (bit1 << uta_shift);
4484 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4485 } else {
4486 uta_info->uta_in_use--;
4487 reg_val &= ~(bit1 << uta_shift);
4488 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4489 }
4490
4491 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4492
4493 if (uta_info->uta_in_use > 0)
4494 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4495 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4496 else
4497 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4498
4499 return 0;
4500}
4501
4502static int
4503ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4504{
4505 int i;
4506 struct ixgbe_hw *hw =
4507 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4508 struct ixgbe_uta_info *uta_info =
4509 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4510
4511 /* The UTA table only exists on 82599 hardware and newer */
4512 if (hw->mac.type < ixgbe_mac_82599EB)
4513 return -ENOTSUP;
4514
4515 if (on) {
4516 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4517 uta_info->uta_shadow[i] = ~0;
4518 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4519 }
4520 } else {
4521 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4522 uta_info->uta_shadow[i] = 0;
4523 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4524 }
4525 }
4526 return 0;
4527
4528}
4529
4530uint32_t
4531ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4532{
4533 uint32_t new_val = orig_val;
4534
4535 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4536 new_val |= IXGBE_VMOLR_AUPE;
4537 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4538 new_val |= IXGBE_VMOLR_ROMPE;
4539 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4540 new_val |= IXGBE_VMOLR_ROPE;
4541 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4542 new_val |= IXGBE_VMOLR_BAM;
4543 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4544 new_val |= IXGBE_VMOLR_MPE;
4545
4546 return new_val;
4547}
4548
4549static int
4550ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4551 uint16_t rx_mask, uint8_t on)
4552{
4553 int val = 0;
4554
4555 struct ixgbe_hw *hw =
4556 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4557 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4558
4559 if (hw->mac.type == ixgbe_mac_82598EB) {
4560 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4561 " on 82599 hardware and newer");
4562 return -ENOTSUP;
4563 }
4564 if (ixgbe_vmdq_mode_check(hw) < 0)
4565 return -ENOTSUP;
4566
4567 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4568
4569 if (on)
4570 vmolr |= val;
4571 else
4572 vmolr &= ~val;
4573
4574 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4575
4576 return 0;
4577}
4578
4579static int
4580ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4581{
4582 uint32_t reg, addr;
4583 uint32_t val;
4584 const uint8_t bit1 = 0x1;
4585
4586 struct ixgbe_hw *hw =
4587 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4588
4589 if (ixgbe_vmdq_mode_check(hw) < 0)
4590 return -ENOTSUP;
4591
4592 if (pool >= ETH_64_POOLS)
4593 return -EINVAL;
4594
4595 /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4596 if (pool >= 32) {
4597 addr = IXGBE_VFRE(1);
4598 val = bit1 << (pool - 32);
4599 } else {
4600 addr = IXGBE_VFRE(0);
4601 val = bit1 << pool;
4602 }
4603
4604 reg = IXGBE_READ_REG(hw, addr);
4605
4606 if (on)
4607 reg |= val;
4608 else
4609 reg &= ~val;
4610
4611 IXGBE_WRITE_REG(hw, addr, reg);
4612
4613 return 0;
4614}
4615
4616static int
4617ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4618{
4619 uint32_t reg, addr;
4620 uint32_t val;
4621 const uint8_t bit1 = 0x1;
4622
4623 struct ixgbe_hw *hw =
4624 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4625
4626 if (ixgbe_vmdq_mode_check(hw) < 0)
4627 return -ENOTSUP;
4628
4629 if (pool >= ETH_64_POOLS)
4630 return -EINVAL;
4631
4632 /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4633 if (pool >= 32) {
4634 addr = IXGBE_VFTE(1);
4635 val = bit1 << (pool - 32);
4636 } else {
4637 addr = IXGBE_VFTE(0);
4638 val = bit1 << pool;
4639 }
4640
4641 reg = IXGBE_READ_REG(hw, addr);
4642
4643 if (on)
4644 reg |= val;
4645 else
4646 reg &= ~val;
4647
4648 IXGBE_WRITE_REG(hw, addr, reg);
4649
4650 return 0;
4651}
4652
4653static int
4654ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4655 uint64_t pool_mask, uint8_t vlan_on)
4656{
4657 int ret = 0;
4658 uint16_t pool_idx;
4659 struct ixgbe_hw *hw =
4660 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4661
4662 if (ixgbe_vmdq_mode_check(hw) < 0)
4663 return -ENOTSUP;
4664 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4665 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4666 ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx,
4667 vlan_on, false);
4668 if (ret < 0)
4669 return ret;
4670 }
4671 }
4672
4673 return ret;
4674}
4675
4676int
4677rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4678{
4679 struct ixgbe_hw *hw;
4680 struct ixgbe_mac_info *mac;
4681 struct rte_eth_dev *dev;
4682 struct rte_eth_dev_info dev_info;
4683
4684 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4685
4686 dev = &rte_eth_devices[port];
4687 rte_eth_dev_info_get(port, &dev_info);
4688
4689 if (vf >= dev_info.max_vfs)
4690 return -EINVAL;
4691
4692 if (on > 1)
4693 return -EINVAL;
4694
4695 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4696 mac = &hw->mac;
4697
4698 mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4699
4700 return 0;
4701}
4702
4703int
4704rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4705{
4706 struct ixgbe_hw *hw;
4707 struct ixgbe_mac_info *mac;
4708 struct rte_eth_dev *dev;
4709 struct rte_eth_dev_info dev_info;
4710
4711 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4712
4713 dev = &rte_eth_devices[port];
4714 rte_eth_dev_info_get(port, &dev_info);
4715
4716 if (vf >= dev_info.max_vfs)
4717 return -EINVAL;
4718
4719 if (on > 1)
4720 return -EINVAL;
4721
4722 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4723 mac = &hw->mac;
4724 mac->ops.set_mac_anti_spoofing(hw, on, vf);
4725
4726 return 0;
4727}
4728
4729int
4730rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4731{
4732 struct ixgbe_hw *hw;
4733 uint32_t ctrl;
4734 struct rte_eth_dev *dev;
4735 struct rte_eth_dev_info dev_info;
4736
4737 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4738
4739 dev = &rte_eth_devices[port];
4740 rte_eth_dev_info_get(port, &dev_info);
4741
4742 if (vf >= dev_info.max_vfs)
4743 return -EINVAL;
4744
4745 if (vlan_id > 4095)
4746 return -EINVAL;
4747
4748 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4749 ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4750 if (vlan_id) {
4751 ctrl = vlan_id;
4752 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4753 } else {
4754 ctrl = 0;
4755 }
4756
4757 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4758
4759 return 0;
4760}
4761
4762int
4763rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4764{
4765 struct ixgbe_hw *hw;
4766 uint32_t ctrl;
4767 struct rte_eth_dev *dev;
4768
4769 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4770
4771 dev = &rte_eth_devices[port];
4772
4773 if (on > 1)
4774 return -EINVAL;
4775
4776 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4777 ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4778 /* enable or disable VMDQ loopback */
4779 if (on)
4780 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
4781 else
4782 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4783
4784 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
4785
4786 return 0;
4787}
4788
4789int
4790rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
4791{
4792 struct ixgbe_hw *hw;
4793 uint32_t reg_value;
4794 int i;
4795 int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
4796 struct rte_eth_dev *dev;
4797
4798 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4799
4800 dev = &rte_eth_devices[port];
4801
4802 if (on > 1)
4803 return -EINVAL;
4804
4805 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4806 for (i = 0; i <= num_queues; i++) {
4807 reg_value = IXGBE_QDE_WRITE |
4808 (i << IXGBE_QDE_IDX_SHIFT) |
4809 (on & IXGBE_QDE_ENABLE);
4810 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
4811 }
4812
4813 return 0;
4814}
4815
4816int
4817rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
4818{
4819 struct ixgbe_hw *hw;
4820 uint32_t reg_value;
4821 struct rte_eth_dev *dev;
4822 struct rte_eth_dev_info dev_info;
4823
4824 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4825
4826 dev = &rte_eth_devices[port];
4827 rte_eth_dev_info_get(port, &dev_info);
4828
4829 /* only support VF's 0 to 63 */
4830 if ((vf >= dev_info.max_vfs) || (vf > 63))
4831 return -EINVAL;
4832
4833 if (on > 1)
4834 return -EINVAL;
4835
4836 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4837 reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
4838 if (on)
4839 reg_value |= IXGBE_SRRCTL_DROP_EN;
4840 else
4841 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
4842
4843 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
4844
4845 return 0;
4846}
4847
4848int
4849rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
4850{
4851 struct rte_eth_dev *dev;
4852 struct rte_eth_dev_info dev_info;
4853 uint16_t queues_per_pool;
4854 uint32_t q;
4855
4856 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4857
4858 dev = &rte_eth_devices[port];
4859 rte_eth_dev_info_get(port, &dev_info);
4860
4861 if (vf >= dev_info.max_vfs)
4862 return -EINVAL;
4863
4864 if (on > 1)
4865 return -EINVAL;
4866
4867 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
4868
4869 /* The PF has 128 queue pairs and in SRIOV configuration
4870 * those queues will be assigned to VF's, so RXDCTL
4871 * registers will be dealing with queues which will be
4872 * assigned to VF's.
4873 * Let's say we have SRIOV configured with 31 VF's then the
4874 * first 124 queues 0-123 will be allocated to VF's and only
4875 * the last 4 queues 123-127 will be assigned to the PF.
4876 */
4877
4878 queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
4879
4880 for (q = 0; q < queues_per_pool; q++)
4881 (*dev->dev_ops->vlan_strip_queue_set)(dev,
4882 q + vf * queues_per_pool, on);
4883 return 0;
4884}
4885
4886#define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
4887#define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
4888#define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
4889#define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
4890#define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4891 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4892 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4893
4894static int
4895ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4896 struct rte_eth_mirror_conf *mirror_conf,
4897 uint8_t rule_id, uint8_t on)
4898{
4899 uint32_t mr_ctl, vlvf;
4900 uint32_t mp_lsb = 0;
4901 uint32_t mv_msb = 0;
4902 uint32_t mv_lsb = 0;
4903 uint32_t mp_msb = 0;
4904 uint8_t i = 0;
4905 int reg_index = 0;
4906 uint64_t vlan_mask = 0;
4907
4908 const uint8_t pool_mask_offset = 32;
4909 const uint8_t vlan_mask_offset = 32;
4910 const uint8_t dst_pool_offset = 8;
4911 const uint8_t rule_mr_offset = 4;
4912 const uint8_t mirror_rule_mask = 0x0F;
4913
4914 struct ixgbe_mirror_info *mr_info =
4915 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4916 struct ixgbe_hw *hw =
4917 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4918 uint8_t mirror_type = 0;
4919
4920 if (ixgbe_vmdq_mode_check(hw) < 0)
4921 return -ENOTSUP;
4922
4923 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4924 return -EINVAL;
4925
4926 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4927 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4928 mirror_conf->rule_type);
4929 return -EINVAL;
4930 }
4931
4932 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4933 mirror_type |= IXGBE_MRCTL_VLME;
4934 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4935 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
4936 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4937 /* search vlan id related pool vlan filter index */
4938 reg_index = ixgbe_find_vlvf_slot(hw,
4939 mirror_conf->vlan.vlan_id[i],
4940 false);
4941 if (reg_index < 0)
4942 return -EINVAL;
4943 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4944 if ((vlvf & IXGBE_VLVF_VIEN) &&
4945 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4946 mirror_conf->vlan.vlan_id[i]))
4947 vlan_mask |= (1ULL << reg_index);
4948 else
4949 return -EINVAL;
4950 }
4951 }
4952
4953 if (on) {
4954 mv_lsb = vlan_mask & 0xFFFFFFFF;
4955 mv_msb = vlan_mask >> vlan_mask_offset;
4956
4957 mr_info->mr_conf[rule_id].vlan.vlan_mask =
4958 mirror_conf->vlan.vlan_mask;
4959 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4960 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4961 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4962 mirror_conf->vlan.vlan_id[i];
4963 }
4964 } else {
4965 mv_lsb = 0;
4966 mv_msb = 0;
4967 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4968 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4969 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4970 }
4971 }
4972
4973 /*
4974 * if enable pool mirror, write related pool mask register,if disable
4975 * pool mirror, clear PFMRVM register
4976 */
4977 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4978 mirror_type |= IXGBE_MRCTL_VPME;
4979 if (on) {
4980 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4981 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4982 mr_info->mr_conf[rule_id].pool_mask =
4983 mirror_conf->pool_mask;
4984
4985 } else {
4986 mp_lsb = 0;
4987 mp_msb = 0;
4988 mr_info->mr_conf[rule_id].pool_mask = 0;
4989 }
4990 }
4991 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4992 mirror_type |= IXGBE_MRCTL_UPME;
4993 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4994 mirror_type |= IXGBE_MRCTL_DPME;
4995
4996 /* read mirror control register and recalculate it */
4997 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4998
4999 if (on) {
5000 mr_ctl |= mirror_type;
5001 mr_ctl &= mirror_rule_mask;
5002 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5003 } else
5004 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5005
5006 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5007 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5008
5009 /* write mirrror control register */
5010 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5011
5012 /* write pool mirrror control register */
5013 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5014 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5015 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5016 mp_msb);
5017 }
5018 /* write VLAN mirrror control register */
5019 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5020 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5021 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5022 mv_msb);
5023 }
5024
5025 return 0;
5026}
5027
5028static int
5029ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5030{
5031 int mr_ctl = 0;
5032 uint32_t lsb_val = 0;
5033 uint32_t msb_val = 0;
5034 const uint8_t rule_mr_offset = 4;
5035
5036 struct ixgbe_hw *hw =
5037 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5038 struct ixgbe_mirror_info *mr_info =
5039 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5040
5041 if (ixgbe_vmdq_mode_check(hw) < 0)
5042 return -ENOTSUP;
5043
5044 memset(&mr_info->mr_conf[rule_id], 0,
5045 sizeof(struct rte_eth_mirror_conf));
5046
5047 /* clear PFVMCTL register */
5048 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5049
5050 /* clear pool mask register */
5051 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5052 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5053
5054 /* clear vlan mask register */
5055 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5056 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5057
5058 return 0;
5059}
5060
5061static int
5062ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5063{
5064 uint32_t mask;
5065 struct ixgbe_hw *hw =
5066 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5067
5068 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5069 mask |= (1 << IXGBE_MISC_VEC_ID);
5070 RTE_SET_USED(queue_id);
5071 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5072
5073 rte_intr_enable(&dev->pci_dev->intr_handle);
5074
5075 return 0;
5076}
5077
5078static int
5079ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5080{
5081 uint32_t mask;
5082 struct ixgbe_hw *hw =
5083 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5084
5085 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5086 mask &= ~(1 << IXGBE_MISC_VEC_ID);
5087 RTE_SET_USED(queue_id);
5088 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5089
5090 return 0;
5091}
5092
5093static int
5094ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5095{
5096 uint32_t mask;
5097 struct ixgbe_hw *hw =
5098 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5099 struct ixgbe_interrupt *intr =
5100 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5101
5102 if (queue_id < 16) {
5103 ixgbe_disable_intr(hw);
5104 intr->mask |= (1 << queue_id);
5105 ixgbe_enable_intr(dev);
5106 } else if (queue_id < 32) {
5107 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5108 mask &= (1 << queue_id);
5109 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5110 } else if (queue_id < 64) {
5111 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5112 mask &= (1 << (queue_id - 32));
5113 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5114 }
5115 rte_intr_enable(&dev->pci_dev->intr_handle);
5116
5117 return 0;
5118}
5119
5120static int
5121ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5122{
5123 uint32_t mask;
5124 struct ixgbe_hw *hw =
5125 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5126 struct ixgbe_interrupt *intr =
5127 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5128
5129 if (queue_id < 16) {
5130 ixgbe_disable_intr(hw);
5131 intr->mask &= ~(1 << queue_id);
5132 ixgbe_enable_intr(dev);
5133 } else if (queue_id < 32) {
5134 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5135 mask &= ~(1 << queue_id);
5136 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5137 } else if (queue_id < 64) {
5138 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5139 mask &= ~(1 << (queue_id - 32));
5140 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5141 }
5142
5143 return 0;
5144}
5145
5146static void
5147ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5148 uint8_t queue, uint8_t msix_vector)
5149{
5150 uint32_t tmp, idx;
5151
5152 if (direction == -1) {
5153 /* other causes */
5154 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5155 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5156 tmp &= ~0xFF;
5157 tmp |= msix_vector;
5158 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5159 } else {
5160 /* rx or tx cause */
5161 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5162 idx = ((16 * (queue & 1)) + (8 * direction));
5163 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5164 tmp &= ~(0xFF << idx);
5165 tmp |= (msix_vector << idx);
5166 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5167 }
5168}
5169
5170/**
5171 * set the IVAR registers, mapping interrupt causes to vectors
5172 * @param hw
5173 * pointer to ixgbe_hw struct
5174 * @direction
5175 * 0 for Rx, 1 for Tx, -1 for other causes
5176 * @queue
5177 * queue to map the corresponding interrupt to
5178 * @msix_vector
5179 * the vector to map to the corresponding queue
5180 */
5181static void
5182ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5183 uint8_t queue, uint8_t msix_vector)
5184{
5185 uint32_t tmp, idx;
5186
5187 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5188 if (hw->mac.type == ixgbe_mac_82598EB) {
5189 if (direction == -1)
5190 direction = 0;
5191 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5192 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5193 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5194 tmp |= (msix_vector << (8 * (queue & 0x3)));
5195 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5196 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5197 (hw->mac.type == ixgbe_mac_X540)) {
5198 if (direction == -1) {
5199 /* other causes */
5200 idx = ((queue & 1) * 8);
5201 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5202 tmp &= ~(0xFF << idx);
5203 tmp |= (msix_vector << idx);
5204 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5205 } else {
5206 /* rx or tx causes */
5207 idx = ((16 * (queue & 1)) + (8 * direction));
5208 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5209 tmp &= ~(0xFF << idx);
5210 tmp |= (msix_vector << idx);
5211 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5212 }
5213 }
5214}
5215
5216static void
5217ixgbevf_configure_msix(struct rte_eth_dev *dev)
5218{
5219 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5220 struct ixgbe_hw *hw =
5221 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5222 uint32_t q_idx;
5223 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5224
5225 /* Configure VF other cause ivar */
5226 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5227
5228 /* won't configure msix register if no mapping is done
5229 * between intr vector and event fd.
5230 */
5231 if (!rte_intr_dp_is_en(intr_handle))
5232 return;
5233
5234 /* Configure all RX queues of VF */
5235 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5236 /* Force all queue use vector 0,
5237 * as IXGBE_VF_MAXMSIVECOTR = 1
5238 */
5239 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5240 intr_handle->intr_vec[q_idx] = vector_idx;
5241 }
5242}
5243
5244/**
5245 * Sets up the hardware to properly generate MSI-X interrupts
5246 * @hw
5247 * board private structure
5248 */
5249static void
5250ixgbe_configure_msix(struct rte_eth_dev *dev)
5251{
5252 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5253 struct ixgbe_hw *hw =
5254 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5255 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5256 uint32_t vec = IXGBE_MISC_VEC_ID;
5257 uint32_t mask;
5258 uint32_t gpie;
5259
5260 /* won't configure msix register if no mapping is done
5261 * between intr vector and event fd
5262 */
5263 if (!rte_intr_dp_is_en(intr_handle))
5264 return;
5265
5266 if (rte_intr_allow_others(intr_handle))
5267 vec = base = IXGBE_RX_VEC_START;
5268
5269 /* setup GPIE for MSI-x mode */
5270 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5271 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5272 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5273 /* auto clearing and auto setting corresponding bits in EIMS
5274 * when MSI-X interrupt is triggered
5275 */
5276 if (hw->mac.type == ixgbe_mac_82598EB) {
5277 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5278 } else {
5279 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5280 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5281 }
5282 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5283
5284 /* Populate the IVAR table and set the ITR values to the
5285 * corresponding register.
5286 */
5287 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5288 queue_id++) {
5289 /* by default, 1:1 mapping */
5290 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5291 intr_handle->intr_vec[queue_id] = vec;
5292 if (vec < base + intr_handle->nb_efd - 1)
5293 vec++;
5294 }
5295
5296 switch (hw->mac.type) {
5297 case ixgbe_mac_82598EB:
5298 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5299 IXGBE_MISC_VEC_ID);
5300 break;
5301 case ixgbe_mac_82599EB:
5302 case ixgbe_mac_X540:
5303 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5304 break;
5305 default:
5306 break;
5307 }
5308 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5309 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5310
5311 /* set up to autoclear timer, and the vectors */
5312 mask = IXGBE_EIMS_ENABLE_MASK;
5313 mask &= ~(IXGBE_EIMS_OTHER |
5314 IXGBE_EIMS_MAILBOX |
5315 IXGBE_EIMS_LSC);
5316
5317 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5318}
5319
5320static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5321 uint16_t queue_idx, uint16_t tx_rate)
5322{
5323 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5324 uint32_t rf_dec, rf_int;
5325 uint32_t bcnrc_val;
5326 uint16_t link_speed = dev->data->dev_link.link_speed;
5327
5328 if (queue_idx >= hw->mac.max_tx_queues)
5329 return -EINVAL;
5330
5331 if (tx_rate != 0) {
5332 /* Calculate the rate factor values to set */
5333 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5334 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5335 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5336
5337 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5338 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5339 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5340 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5341 } else {
5342 bcnrc_val = 0;
5343 }
5344
5345 /*
5346 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5347 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5348 * set as 0x4.
5349 */
5350 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5351 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5352 IXGBE_MAX_JUMBO_FRAME_SIZE))
5353 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5354 IXGBE_MMW_SIZE_JUMBO_FRAME);
5355 else
5356 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5357 IXGBE_MMW_SIZE_DEFAULT);
5358
5359 /* Set RTTBCNRC of queue X */
5360 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5361 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5362 IXGBE_WRITE_FLUSH(hw);
5363
5364 return 0;
5365}
5366
5367static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
5368 uint16_t tx_rate, uint64_t q_msk)
5369{
5370 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5371 struct ixgbe_vf_info *vfinfo =
5372 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5373 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5374 uint32_t queue_stride =
5375 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5376 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
5377 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
5378 uint16_t total_rate = 0;
5379
5380 if (queue_end >= hw->mac.max_tx_queues)
5381 return -EINVAL;
5382
5383 if (vfinfo != NULL) {
5384 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
5385 if (vf_idx == vf)
5386 continue;
5387 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5388 idx++)
5389 total_rate += vfinfo[vf_idx].tx_rate[idx];
5390 }
5391 } else
5392 return -EINVAL;
5393
5394 /* Store tx_rate for this vf. */
5395 for (idx = 0; idx < nb_q_per_pool; idx++) {
5396 if (((uint64_t)0x1 << idx) & q_msk) {
5397 if (vfinfo[vf].tx_rate[idx] != tx_rate)
5398 vfinfo[vf].tx_rate[idx] = tx_rate;
5399 total_rate += tx_rate;
5400 }
5401 }
5402
5403 if (total_rate > dev->data->dev_link.link_speed) {
5404 /*
5405 * Reset stored TX rate of the VF if it causes exceed
5406 * link speed.
5407 */
5408 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5409 return -EINVAL;
5410 }
5411
5412 /* Set RTTBCNRC of each queue/pool for vf X */
5413 for (; queue_idx <= queue_end; queue_idx++) {
5414 if (0x1 & q_msk)
5415 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5416 q_msk = q_msk >> 1;
5417 }
5418
5419 return 0;
5420}
5421
5422static void
5423ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5424 __attribute__((unused)) uint32_t index,
5425 __attribute__((unused)) uint32_t pool)
5426{
5427 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5428 int diag;
5429
5430 /*
5431 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5432 * operation. Trap this case to avoid exhausting the [very limited]
5433 * set of PF resources used to store VF MAC addresses.
5434 */
5435 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5436 return;
5437 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5438 if (diag == 0)
5439 return;
5440 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5441}
5442
5443static void
5444ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5445{
5446 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5447 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5448 struct ether_addr *mac_addr;
5449 uint32_t i;
5450 int diag;
5451
5452 /*
5453 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5454 * not support the deletion of a given MAC address.
5455 * Instead, it imposes to delete all MAC addresses, then to add again
5456 * all MAC addresses with the exception of the one to be deleted.
5457 */
5458 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5459
5460 /*
5461 * Add again all MAC addresses, with the exception of the deleted one
5462 * and of the permanent MAC address.
5463 */
5464 for (i = 0, mac_addr = dev->data->mac_addrs;
5465 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5466 /* Skip the deleted MAC address */
5467 if (i == index)
5468 continue;
5469 /* Skip NULL MAC addresses */
5470 if (is_zero_ether_addr(mac_addr))
5471 continue;
5472 /* Skip the permanent MAC address */
5473 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5474 continue;
5475 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5476 if (diag != 0)
5477 PMD_DRV_LOG(ERR,
5478 "Adding again MAC address "
5479 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5480 "diag=%d",
5481 mac_addr->addr_bytes[0],
5482 mac_addr->addr_bytes[1],
5483 mac_addr->addr_bytes[2],
5484 mac_addr->addr_bytes[3],
5485 mac_addr->addr_bytes[4],
5486 mac_addr->addr_bytes[5],
5487 diag);
5488 }
5489}
5490
5491static void
5492ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5493{
5494 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5495
5496 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5497}
5498
5499#define MAC_TYPE_FILTER_SUP(type) do {\
5500 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5501 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5502 (type) != ixgbe_mac_X550EM_a)\
5503 return -ENOTSUP;\
5504} while (0)
5505
5506static int
5507ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5508 struct rte_eth_syn_filter *filter,
5509 bool add)
5510{
5511 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5512 uint32_t synqf;
5513
5514 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5515 return -EINVAL;
5516
5517 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5518
5519 if (add) {
5520 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5521 return -EINVAL;
5522 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5523 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5524
5525 if (filter->hig_pri)
5526 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5527 else
5528 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5529 } else {
5530 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5531 return -ENOENT;
5532 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5533 }
5534 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5535 IXGBE_WRITE_FLUSH(hw);
5536 return 0;
5537}
5538
5539static int
5540ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5541 struct rte_eth_syn_filter *filter)
5542{
5543 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5544 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5545
5546 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5547 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5548 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5549 return 0;
5550 }
5551 return -ENOENT;
5552}
5553
5554static int
5555ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5556 enum rte_filter_op filter_op,
5557 void *arg)
5558{
5559 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5560 int ret;
5561
5562 MAC_TYPE_FILTER_SUP(hw->mac.type);
5563
5564 if (filter_op == RTE_ETH_FILTER_NOP)
5565 return 0;
5566
5567 if (arg == NULL) {
5568 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5569 filter_op);
5570 return -EINVAL;
5571 }
5572
5573 switch (filter_op) {
5574 case RTE_ETH_FILTER_ADD:
5575 ret = ixgbe_syn_filter_set(dev,
5576 (struct rte_eth_syn_filter *)arg,
5577 TRUE);
5578 break;
5579 case RTE_ETH_FILTER_DELETE:
5580 ret = ixgbe_syn_filter_set(dev,
5581 (struct rte_eth_syn_filter *)arg,
5582 FALSE);
5583 break;
5584 case RTE_ETH_FILTER_GET:
5585 ret = ixgbe_syn_filter_get(dev,
5586 (struct rte_eth_syn_filter *)arg);
5587 break;
5588 default:
5589 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5590 ret = -EINVAL;
5591 break;
5592 }
5593
5594 return ret;
5595}
5596
5597
5598static inline enum ixgbe_5tuple_protocol
5599convert_protocol_type(uint8_t protocol_value)
5600{
5601 if (protocol_value == IPPROTO_TCP)
5602 return IXGBE_FILTER_PROTOCOL_TCP;
5603 else if (protocol_value == IPPROTO_UDP)
5604 return IXGBE_FILTER_PROTOCOL_UDP;
5605 else if (protocol_value == IPPROTO_SCTP)
5606 return IXGBE_FILTER_PROTOCOL_SCTP;
5607 else
5608 return IXGBE_FILTER_PROTOCOL_NONE;
5609}
5610
5611/*
5612 * add a 5tuple filter
5613 *
5614 * @param
5615 * dev: Pointer to struct rte_eth_dev.
5616 * index: the index the filter allocates.
5617 * filter: ponter to the filter that will be added.
5618 * rx_queue: the queue id the filter assigned to.
5619 *
5620 * @return
5621 * - On success, zero.
5622 * - On failure, a negative value.
5623 */
5624static int
5625ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5626 struct ixgbe_5tuple_filter *filter)
5627{
5628 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5629 struct ixgbe_filter_info *filter_info =
5630 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5631 int i, idx, shift;
5632 uint32_t ftqf, sdpqf;
5633 uint32_t l34timir = 0;
5634 uint8_t mask = 0xff;
5635
5636 /*
5637 * look for an unused 5tuple filter index,
5638 * and insert the filter to list.
5639 */
5640 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5641 idx = i / (sizeof(uint32_t) * NBBY);
5642 shift = i % (sizeof(uint32_t) * NBBY);
5643 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5644 filter_info->fivetuple_mask[idx] |= 1 << shift;
5645 filter->index = i;
5646 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5647 filter,
5648 entries);
5649 break;
5650 }
5651 }
5652 if (i >= IXGBE_MAX_FTQF_FILTERS) {
5653 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5654 return -ENOSYS;
5655 }
5656
5657 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5658 IXGBE_SDPQF_DSTPORT_SHIFT);
5659 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5660
5661 ftqf = (uint32_t)(filter->filter_info.proto &
5662 IXGBE_FTQF_PROTOCOL_MASK);
5663 ftqf |= (uint32_t)((filter->filter_info.priority &
5664 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5665 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5666 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5667 if (filter->filter_info.dst_ip_mask == 0)
5668 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5669 if (filter->filter_info.src_port_mask == 0)
5670 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5671 if (filter->filter_info.dst_port_mask == 0)
5672 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5673 if (filter->filter_info.proto_mask == 0)
5674 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5675 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5676 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5677 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5678
5679 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5680 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5681 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5682 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5683
5684 l34timir |= IXGBE_L34T_IMIR_RESERVE;
5685 l34timir |= (uint32_t)(filter->queue <<
5686 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5687 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5688 return 0;
5689}
5690
5691/*
5692 * remove a 5tuple filter
5693 *
5694 * @param
5695 * dev: Pointer to struct rte_eth_dev.
5696 * filter: the pointer of the filter will be removed.
5697 */
5698static void
5699ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5700 struct ixgbe_5tuple_filter *filter)
5701{
5702 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5703 struct ixgbe_filter_info *filter_info =
5704 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5705 uint16_t index = filter->index;
5706
5707 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5708 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5709 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5710 rte_free(filter);
5711
5712 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5713 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5714 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5715 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5716 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5717}
5718
5719static int
5720ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5721{
5722 struct ixgbe_hw *hw;
5723 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5724
5725 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5726
5727 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5728 return -EINVAL;
5729
5730 /* refuse mtu that requires the support of scattered packets when this
5731 * feature has not been enabled before.
5732 */
5733 if (!dev->data->scattered_rx &&
5734 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5735 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5736 return -EINVAL;
5737
5738 /*
5739 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5740 * request of the version 2.0 of the mailbox API.
5741 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5742 * of the mailbox API.
5743 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5744 * prior to 3.11.33 which contains the following change:
5745 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5746 */
5747 ixgbevf_rlpml_set_vf(hw, max_frame);
5748
5749 /* update max frame size */
5750 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5751 return 0;
5752}
5753
5754#define MAC_TYPE_FILTER_SUP_EXT(type) do {\
5755 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5756 return -ENOTSUP;\
5757} while (0)
5758
5759static inline struct ixgbe_5tuple_filter *
5760ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5761 struct ixgbe_5tuple_filter_info *key)
5762{
5763 struct ixgbe_5tuple_filter *it;
5764
5765 TAILQ_FOREACH(it, filter_list, entries) {
5766 if (memcmp(key, &it->filter_info,
5767 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5768 return it;
5769 }
5770 }
5771 return NULL;
5772}
5773
5774/* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5775static inline int
5776ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5777 struct ixgbe_5tuple_filter_info *filter_info)
5778{
5779 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5780 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5781 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5782 return -EINVAL;
5783
5784 switch (filter->dst_ip_mask) {
5785 case UINT32_MAX:
5786 filter_info->dst_ip_mask = 0;
5787 filter_info->dst_ip = filter->dst_ip;
5788 break;
5789 case 0:
5790 filter_info->dst_ip_mask = 1;
5791 break;
5792 default:
5793 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5794 return -EINVAL;
5795 }
5796
5797 switch (filter->src_ip_mask) {
5798 case UINT32_MAX:
5799 filter_info->src_ip_mask = 0;
5800 filter_info->src_ip = filter->src_ip;
5801 break;
5802 case 0:
5803 filter_info->src_ip_mask = 1;
5804 break;
5805 default:
5806 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5807 return -EINVAL;
5808 }
5809
5810 switch (filter->dst_port_mask) {
5811 case UINT16_MAX:
5812 filter_info->dst_port_mask = 0;
5813 filter_info->dst_port = filter->dst_port;
5814 break;
5815 case 0:
5816 filter_info->dst_port_mask = 1;
5817 break;
5818 default:
5819 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5820 return -EINVAL;
5821 }
5822
5823 switch (filter->src_port_mask) {
5824 case UINT16_MAX:
5825 filter_info->src_port_mask = 0;
5826 filter_info->src_port = filter->src_port;
5827 break;
5828 case 0:
5829 filter_info->src_port_mask = 1;
5830 break;
5831 default:
5832 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5833 return -EINVAL;
5834 }
5835
5836 switch (filter->proto_mask) {
5837 case UINT8_MAX:
5838 filter_info->proto_mask = 0;
5839 filter_info->proto =
5840 convert_protocol_type(filter->proto);
5841 break;
5842 case 0:
5843 filter_info->proto_mask = 1;
5844 break;
5845 default:
5846 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5847 return -EINVAL;
5848 }
5849
5850 filter_info->priority = (uint8_t)filter->priority;
5851 return 0;
5852}
5853
5854/*
5855 * add or delete a ntuple filter
5856 *
5857 * @param
5858 * dev: Pointer to struct rte_eth_dev.
5859 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5860 * add: if true, add filter, if false, remove filter
5861 *
5862 * @return
5863 * - On success, zero.
5864 * - On failure, a negative value.
5865 */
5866static int
5867ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5868 struct rte_eth_ntuple_filter *ntuple_filter,
5869 bool add)
5870{
5871 struct ixgbe_filter_info *filter_info =
5872 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5873 struct ixgbe_5tuple_filter_info filter_5tuple;
5874 struct ixgbe_5tuple_filter *filter;
5875 int ret;
5876
5877 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5878 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5879 return -EINVAL;
5880 }
5881
5882 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5883 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5884 if (ret < 0)
5885 return ret;
5886
5887 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5888 &filter_5tuple);
5889 if (filter != NULL && add) {
5890 PMD_DRV_LOG(ERR, "filter exists.");
5891 return -EEXIST;
5892 }
5893 if (filter == NULL && !add) {
5894 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5895 return -ENOENT;
5896 }
5897
5898 if (add) {
5899 filter = rte_zmalloc("ixgbe_5tuple_filter",
5900 sizeof(struct ixgbe_5tuple_filter), 0);
5901 if (filter == NULL)
5902 return -ENOMEM;
5903 (void)rte_memcpy(&filter->filter_info,
5904 &filter_5tuple,
5905 sizeof(struct ixgbe_5tuple_filter_info));
5906 filter->queue = ntuple_filter->queue;
5907 ret = ixgbe_add_5tuple_filter(dev, filter);
5908 if (ret < 0) {
5909 rte_free(filter);
5910 return ret;
5911 }
5912 } else
5913 ixgbe_remove_5tuple_filter(dev, filter);
5914
5915 return 0;
5916}
5917
5918/*
5919 * get a ntuple filter
5920 *
5921 * @param
5922 * dev: Pointer to struct rte_eth_dev.
5923 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5924 *
5925 * @return
5926 * - On success, zero.
5927 * - On failure, a negative value.
5928 */
5929static int
5930ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5931 struct rte_eth_ntuple_filter *ntuple_filter)
5932{
5933 struct ixgbe_filter_info *filter_info =
5934 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5935 struct ixgbe_5tuple_filter_info filter_5tuple;
5936 struct ixgbe_5tuple_filter *filter;
5937 int ret;
5938
5939 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5940 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5941 return -EINVAL;
5942 }
5943
5944 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5945 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5946 if (ret < 0)
5947 return ret;
5948
5949 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5950 &filter_5tuple);
5951 if (filter == NULL) {
5952 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5953 return -ENOENT;
5954 }
5955 ntuple_filter->queue = filter->queue;
5956 return 0;
5957}
5958
5959/*
5960 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5961 * @dev: pointer to rte_eth_dev structure
5962 * @filter_op:operation will be taken.
5963 * @arg: a pointer to specific structure corresponding to the filter_op
5964 *
5965 * @return
5966 * - On success, zero.
5967 * - On failure, a negative value.
5968 */
5969static int
5970ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5971 enum rte_filter_op filter_op,
5972 void *arg)
5973{
5974 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5975 int ret;
5976
5977 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5978
5979 if (filter_op == RTE_ETH_FILTER_NOP)
5980 return 0;
5981
5982 if (arg == NULL) {
5983 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5984 filter_op);
5985 return -EINVAL;
5986 }
5987
5988 switch (filter_op) {
5989 case RTE_ETH_FILTER_ADD:
5990 ret = ixgbe_add_del_ntuple_filter(dev,
5991 (struct rte_eth_ntuple_filter *)arg,
5992 TRUE);
5993 break;
5994 case RTE_ETH_FILTER_DELETE:
5995 ret = ixgbe_add_del_ntuple_filter(dev,
5996 (struct rte_eth_ntuple_filter *)arg,
5997 FALSE);
5998 break;
5999 case RTE_ETH_FILTER_GET:
6000 ret = ixgbe_get_ntuple_filter(dev,
6001 (struct rte_eth_ntuple_filter *)arg);
6002 break;
6003 default:
6004 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6005 ret = -EINVAL;
6006 break;
6007 }
6008 return ret;
6009}
6010
6011static inline int
6012ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
6013 uint16_t ethertype)
6014{
6015 int i;
6016
6017 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6018 if (filter_info->ethertype_filters[i] == ethertype &&
6019 (filter_info->ethertype_mask & (1 << i)))
6020 return i;
6021 }
6022 return -1;
6023}
6024
6025static inline int
6026ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
6027 uint16_t ethertype)
6028{
6029 int i;
6030
6031 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6032 if (!(filter_info->ethertype_mask & (1 << i))) {
6033 filter_info->ethertype_mask |= 1 << i;
6034 filter_info->ethertype_filters[i] = ethertype;
6035 return i;
6036 }
6037 }
6038 return -1;
6039}
6040
6041static inline int
6042ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
6043 uint8_t idx)
6044{
6045 if (idx >= IXGBE_MAX_ETQF_FILTERS)
6046 return -1;
6047 filter_info->ethertype_mask &= ~(1 << idx);
6048 filter_info->ethertype_filters[idx] = 0;
6049 return idx;
6050}
6051
6052static int
6053ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6054 struct rte_eth_ethertype_filter *filter,
6055 bool add)
6056{
6057 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6058 struct ixgbe_filter_info *filter_info =
6059 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6060 uint32_t etqf = 0;
6061 uint32_t etqs = 0;
6062 int ret;
6063
6064 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6065 return -EINVAL;
6066
6067 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6068 filter->ether_type == ETHER_TYPE_IPv6) {
6069 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6070 " ethertype filter.", filter->ether_type);
6071 return -EINVAL;
6072 }
6073
6074 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6075 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6076 return -EINVAL;
6077 }
6078 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6079 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6080 return -EINVAL;
6081 }
6082
6083 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6084 if (ret >= 0 && add) {
6085 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6086 filter->ether_type);
6087 return -EEXIST;
6088 }
6089 if (ret < 0 && !add) {
6090 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6091 filter->ether_type);
6092 return -ENOENT;
6093 }
6094
6095 if (add) {
6096 ret = ixgbe_ethertype_filter_insert(filter_info,
6097 filter->ether_type);
6098 if (ret < 0) {
6099 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6100 return -ENOSYS;
6101 }
6102 etqf = IXGBE_ETQF_FILTER_EN;
6103 etqf |= (uint32_t)filter->ether_type;
6104 etqs |= (uint32_t)((filter->queue <<
6105 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6106 IXGBE_ETQS_RX_QUEUE);
6107 etqs |= IXGBE_ETQS_QUEUE_EN;
6108 } else {
6109 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6110 if (ret < 0)
6111 return -ENOSYS;
6112 }
6113 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6114 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6115 IXGBE_WRITE_FLUSH(hw);
6116
6117 return 0;
6118}
6119
6120static int
6121ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6122 struct rte_eth_ethertype_filter *filter)
6123{
6124 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6125 struct ixgbe_filter_info *filter_info =
6126 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6127 uint32_t etqf, etqs;
6128 int ret;
6129
6130 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6131 if (ret < 0) {
6132 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6133 filter->ether_type);
6134 return -ENOENT;
6135 }
6136
6137 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6138 if (etqf & IXGBE_ETQF_FILTER_EN) {
6139 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6140 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6141 filter->flags = 0;
6142 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6143 IXGBE_ETQS_RX_QUEUE_SHIFT;
6144 return 0;
6145 }
6146 return -ENOENT;
6147}
6148
6149/*
6150 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6151 * @dev: pointer to rte_eth_dev structure
6152 * @filter_op:operation will be taken.
6153 * @arg: a pointer to specific structure corresponding to the filter_op
6154 */
6155static int
6156ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6157 enum rte_filter_op filter_op,
6158 void *arg)
6159{
6160 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6161 int ret;
6162
6163 MAC_TYPE_FILTER_SUP(hw->mac.type);
6164
6165 if (filter_op == RTE_ETH_FILTER_NOP)
6166 return 0;
6167
6168 if (arg == NULL) {
6169 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6170 filter_op);
6171 return -EINVAL;
6172 }
6173
6174 switch (filter_op) {
6175 case RTE_ETH_FILTER_ADD:
6176 ret = ixgbe_add_del_ethertype_filter(dev,
6177 (struct rte_eth_ethertype_filter *)arg,
6178 TRUE);
6179 break;
6180 case RTE_ETH_FILTER_DELETE:
6181 ret = ixgbe_add_del_ethertype_filter(dev,
6182 (struct rte_eth_ethertype_filter *)arg,
6183 FALSE);
6184 break;
6185 case RTE_ETH_FILTER_GET:
6186 ret = ixgbe_get_ethertype_filter(dev,
6187 (struct rte_eth_ethertype_filter *)arg);
6188 break;
6189 default:
6190 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6191 ret = -EINVAL;
6192 break;
6193 }
6194 return ret;
6195}
6196
6197static int
6198ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6199 enum rte_filter_type filter_type,
6200 enum rte_filter_op filter_op,
6201 void *arg)
6202{
6203 int ret = -EINVAL;
6204
6205 switch (filter_type) {
6206 case RTE_ETH_FILTER_NTUPLE:
6207 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6208 break;
6209 case RTE_ETH_FILTER_ETHERTYPE:
6210 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6211 break;
6212 case RTE_ETH_FILTER_SYN:
6213 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6214 break;
6215 case RTE_ETH_FILTER_FDIR:
6216 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6217 break;
6218 case RTE_ETH_FILTER_L2_TUNNEL:
6219 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6220 break;
6221 default:
6222 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6223 filter_type);
6224 break;
6225 }
6226
6227 return ret;
6228}
6229
6230static u8 *
6231ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6232 u8 **mc_addr_ptr, u32 *vmdq)
6233{
6234 u8 *mc_addr;
6235
6236 *vmdq = 0;
6237 mc_addr = *mc_addr_ptr;
6238 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6239 return mc_addr;
6240}
6241
6242static int
6243ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6244 struct ether_addr *mc_addr_set,
6245 uint32_t nb_mc_addr)
6246{
6247 struct ixgbe_hw *hw;
6248 u8 *mc_addr_list;
6249
6250 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6251 mc_addr_list = (u8 *)mc_addr_set;
6252 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6253 ixgbe_dev_addr_list_itr, TRUE);
6254}
6255
6256static uint64_t
6257ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6258{
6259 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6260 uint64_t systime_cycles;
6261
6262 switch (hw->mac.type) {
6263 case ixgbe_mac_X550:
6264 case ixgbe_mac_X550EM_x:
6265 case ixgbe_mac_X550EM_a:
6266 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6267 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6268 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6269 * NSEC_PER_SEC;
6270 break;
6271 default:
6272 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6273 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6274 << 32;
6275 }
6276
6277 return systime_cycles;
6278}
6279
6280static uint64_t
6281ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6282{
6283 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6284 uint64_t rx_tstamp_cycles;
6285
6286 switch (hw->mac.type) {
6287 case ixgbe_mac_X550:
6288 case ixgbe_mac_X550EM_x:
6289 case ixgbe_mac_X550EM_a:
6290 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6291 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6292 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6293 * NSEC_PER_SEC;
6294 break;
6295 default:
6296 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6297 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6298 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6299 << 32;
6300 }
6301
6302 return rx_tstamp_cycles;
6303}
6304
6305static uint64_t
6306ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6307{
6308 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6309 uint64_t tx_tstamp_cycles;
6310
6311 switch (hw->mac.type) {
6312 case ixgbe_mac_X550:
6313 case ixgbe_mac_X550EM_x:
6314 case ixgbe_mac_X550EM_a:
6315 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6316 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6317 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6318 * NSEC_PER_SEC;
6319 break;
6320 default:
6321 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6322 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6323 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6324 << 32;
6325 }
6326
6327 return tx_tstamp_cycles;
6328}
6329
6330static void
6331ixgbe_start_timecounters(struct rte_eth_dev *dev)
6332{
6333 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6334 struct ixgbe_adapter *adapter =
6335 (struct ixgbe_adapter *)dev->data->dev_private;
6336 struct rte_eth_link link;
6337 uint32_t incval = 0;
6338 uint32_t shift = 0;
6339
6340 /* Get current link speed. */
6341 memset(&link, 0, sizeof(link));
6342 ixgbe_dev_link_update(dev, 1);
6343 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6344
6345 switch (link.link_speed) {
6346 case ETH_SPEED_NUM_100M:
6347 incval = IXGBE_INCVAL_100;
6348 shift = IXGBE_INCVAL_SHIFT_100;
6349 break;
6350 case ETH_SPEED_NUM_1G:
6351 incval = IXGBE_INCVAL_1GB;
6352 shift = IXGBE_INCVAL_SHIFT_1GB;
6353 break;
6354 case ETH_SPEED_NUM_10G:
6355 default:
6356 incval = IXGBE_INCVAL_10GB;
6357 shift = IXGBE_INCVAL_SHIFT_10GB;
6358 break;
6359 }
6360
6361 switch (hw->mac.type) {
6362 case ixgbe_mac_X550:
6363 case ixgbe_mac_X550EM_x:
6364 case ixgbe_mac_X550EM_a:
6365 /* Independent of link speed. */
6366 incval = 1;
6367 /* Cycles read will be interpreted as ns. */
6368 shift = 0;
6369 /* Fall-through */
6370 case ixgbe_mac_X540:
6371 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6372 break;
6373 case ixgbe_mac_82599EB:
6374 incval >>= IXGBE_INCVAL_SHIFT_82599;
6375 shift -= IXGBE_INCVAL_SHIFT_82599;
6376 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6377 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6378 break;
6379 default:
6380 /* Not supported. */
6381 return;
6382 }
6383
6384 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6385 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6386 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6387
6388 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6389 adapter->systime_tc.cc_shift = shift;
6390 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6391
6392 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6393 adapter->rx_tstamp_tc.cc_shift = shift;
6394 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6395
6396 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6397 adapter->tx_tstamp_tc.cc_shift = shift;
6398 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6399}
6400
6401static int
6402ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6403{
6404 struct ixgbe_adapter *adapter =
6405 (struct ixgbe_adapter *)dev->data->dev_private;
6406
6407 adapter->systime_tc.nsec += delta;
6408 adapter->rx_tstamp_tc.nsec += delta;
6409 adapter->tx_tstamp_tc.nsec += delta;
6410
6411 return 0;
6412}
6413
6414static int
6415ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6416{
6417 uint64_t ns;
6418 struct ixgbe_adapter *adapter =
6419 (struct ixgbe_adapter *)dev->data->dev_private;
6420
6421 ns = rte_timespec_to_ns(ts);
6422 /* Set the timecounters to a new value. */
6423 adapter->systime_tc.nsec = ns;
6424 adapter->rx_tstamp_tc.nsec = ns;
6425 adapter->tx_tstamp_tc.nsec = ns;
6426
6427 return 0;
6428}
6429
6430static int
6431ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6432{
6433 uint64_t ns, systime_cycles;
6434 struct ixgbe_adapter *adapter =
6435 (struct ixgbe_adapter *)dev->data->dev_private;
6436
6437 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6438 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6439 *ts = rte_ns_to_timespec(ns);
6440
6441 return 0;
6442}
6443
6444static int
6445ixgbe_timesync_enable(struct rte_eth_dev *dev)
6446{
6447 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6448 uint32_t tsync_ctl;
6449 uint32_t tsauxc;
6450
6451 /* Stop the timesync system time. */
6452 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6453 /* Reset the timesync system time value. */
6454 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6455 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6456
6457 /* Enable system time for platforms where it isn't on by default. */
6458 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6459 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6460 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6461
6462 ixgbe_start_timecounters(dev);
6463
6464 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6465 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6466 (ETHER_TYPE_1588 |
6467 IXGBE_ETQF_FILTER_EN |
6468 IXGBE_ETQF_1588));
6469
6470 /* Enable timestamping of received PTP packets. */
6471 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6472 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6473 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6474
6475 /* Enable timestamping of transmitted PTP packets. */
6476 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6477 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6478 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6479
6480 IXGBE_WRITE_FLUSH(hw);
6481
6482 return 0;
6483}
6484
6485static int
6486ixgbe_timesync_disable(struct rte_eth_dev *dev)
6487{
6488 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6489 uint32_t tsync_ctl;
6490
6491 /* Disable timestamping of transmitted PTP packets. */
6492 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6493 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6494 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6495
6496 /* Disable timestamping of received PTP packets. */
6497 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6498 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6499 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6500
6501 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6502 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6503
6504 /* Stop incrementating the System Time registers. */
6505 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6506
6507 return 0;
6508}
6509
6510static int
6511ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6512 struct timespec *timestamp,
6513 uint32_t flags __rte_unused)
6514{
6515 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6516 struct ixgbe_adapter *adapter =
6517 (struct ixgbe_adapter *)dev->data->dev_private;
6518 uint32_t tsync_rxctl;
6519 uint64_t rx_tstamp_cycles;
6520 uint64_t ns;
6521
6522 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6523 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6524 return -EINVAL;
6525
6526 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6527 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6528 *timestamp = rte_ns_to_timespec(ns);
6529
6530 return 0;
6531}
6532
6533static int
6534ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6535 struct timespec *timestamp)
6536{
6537 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6538 struct ixgbe_adapter *adapter =
6539 (struct ixgbe_adapter *)dev->data->dev_private;
6540 uint32_t tsync_txctl;
6541 uint64_t tx_tstamp_cycles;
6542 uint64_t ns;
6543
6544 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6545 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6546 return -EINVAL;
6547
6548 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6549 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6550 *timestamp = rte_ns_to_timespec(ns);
6551
6552 return 0;
6553}
6554
6555static int
6556ixgbe_get_reg_length(struct rte_eth_dev *dev)
6557{
6558 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6559 int count = 0;
6560 int g_ind = 0;
6561 const struct reg_info *reg_group;
6562 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6563 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6564
6565 while ((reg_group = reg_set[g_ind++]))
6566 count += ixgbe_regs_group_count(reg_group);
6567
6568 return count;
6569}
6570
6571static int
6572ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6573{
6574 int count = 0;
6575 int g_ind = 0;
6576 const struct reg_info *reg_group;
6577
6578 while ((reg_group = ixgbevf_regs[g_ind++]))
6579 count += ixgbe_regs_group_count(reg_group);
6580
6581 return count;
6582}
6583
6584static int
6585ixgbe_get_regs(struct rte_eth_dev *dev,
6586 struct rte_dev_reg_info *regs)
6587{
6588 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6589 uint32_t *data = regs->data;
6590 int g_ind = 0;
6591 int count = 0;
6592 const struct reg_info *reg_group;
6593 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6594 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6595
6596 if (data == NULL) {
6597 regs->length = ixgbe_get_reg_length(dev);
6598 regs->width = sizeof(uint32_t);
6599 return 0;
6600 }
6601
6602 /* Support only full register dump */
6603 if ((regs->length == 0) ||
6604 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6605 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6606 hw->device_id;
6607 while ((reg_group = reg_set[g_ind++]))
6608 count += ixgbe_read_regs_group(dev, &data[count],
6609 reg_group);
6610 return 0;
6611 }
6612
6613 return -ENOTSUP;
6614}
6615
6616static int
6617ixgbevf_get_regs(struct rte_eth_dev *dev,
6618 struct rte_dev_reg_info *regs)
6619{
6620 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6621 uint32_t *data = regs->data;
6622 int g_ind = 0;
6623 int count = 0;
6624 const struct reg_info *reg_group;
6625
6626 if (data == NULL) {
6627 regs->length = ixgbevf_get_reg_length(dev);
6628 regs->width = sizeof(uint32_t);
6629 return 0;
6630 }
6631
6632 /* Support only full register dump */
6633 if ((regs->length == 0) ||
6634 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6635 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6636 hw->device_id;
6637 while ((reg_group = ixgbevf_regs[g_ind++]))
6638 count += ixgbe_read_regs_group(dev, &data[count],
6639 reg_group);
6640 return 0;
6641 }
6642
6643 return -ENOTSUP;
6644}
6645
6646static int
6647ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6648{
6649 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6650
6651 /* Return unit is byte count */
6652 return hw->eeprom.word_size * 2;
6653}
6654
6655static int
6656ixgbe_get_eeprom(struct rte_eth_dev *dev,
6657 struct rte_dev_eeprom_info *in_eeprom)
6658{
6659 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6660 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6661 uint16_t *data = in_eeprom->data;
6662 int first, length;
6663
6664 first = in_eeprom->offset >> 1;
6665 length = in_eeprom->length >> 1;
6666 if ((first > hw->eeprom.word_size) ||
6667 ((first + length) > hw->eeprom.word_size))
6668 return -EINVAL;
6669
6670 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6671
6672 return eeprom->ops.read_buffer(hw, first, length, data);
6673}
6674
6675static int
6676ixgbe_set_eeprom(struct rte_eth_dev *dev,
6677 struct rte_dev_eeprom_info *in_eeprom)
6678{
6679 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6680 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6681 uint16_t *data = in_eeprom->data;
6682 int first, length;
6683
6684 first = in_eeprom->offset >> 1;
6685 length = in_eeprom->length >> 1;
6686 if ((first > hw->eeprom.word_size) ||
6687 ((first + length) > hw->eeprom.word_size))
6688 return -EINVAL;
6689
6690 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6691
6692 return eeprom->ops.write_buffer(hw, first, length, data);
6693}
6694
6695uint16_t
6696ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6697 switch (mac_type) {
6698 case ixgbe_mac_X550:
6699 case ixgbe_mac_X550EM_x:
6700 case ixgbe_mac_X550EM_a:
6701 return ETH_RSS_RETA_SIZE_512;
6702 case ixgbe_mac_X550_vf:
6703 case ixgbe_mac_X550EM_x_vf:
6704 case ixgbe_mac_X550EM_a_vf:
6705 return ETH_RSS_RETA_SIZE_64;
6706 default:
6707 return ETH_RSS_RETA_SIZE_128;
6708 }
6709}
6710
6711uint32_t
6712ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6713 switch (mac_type) {
6714 case ixgbe_mac_X550:
6715 case ixgbe_mac_X550EM_x:
6716 case ixgbe_mac_X550EM_a:
6717 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6718 return IXGBE_RETA(reta_idx >> 2);
6719 else
6720 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6721 case ixgbe_mac_X550_vf:
6722 case ixgbe_mac_X550EM_x_vf:
6723 case ixgbe_mac_X550EM_a_vf:
6724 return IXGBE_VFRETA(reta_idx >> 2);
6725 default:
6726 return IXGBE_RETA(reta_idx >> 2);
6727 }
6728}
6729
6730uint32_t
6731ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6732 switch (mac_type) {
6733 case ixgbe_mac_X550_vf:
6734 case ixgbe_mac_X550EM_x_vf:
6735 case ixgbe_mac_X550EM_a_vf:
6736 return IXGBE_VFMRQC;
6737 default:
6738 return IXGBE_MRQC;
6739 }
6740}
6741
6742uint32_t
6743ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6744 switch (mac_type) {
6745 case ixgbe_mac_X550_vf:
6746 case ixgbe_mac_X550EM_x_vf:
6747 case ixgbe_mac_X550EM_a_vf:
6748 return IXGBE_VFRSSRK(i);
6749 default:
6750 return IXGBE_RSSRK(i);
6751 }
6752}
6753
6754bool
6755ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6756 switch (mac_type) {
6757 case ixgbe_mac_82599_vf:
6758 case ixgbe_mac_X540_vf:
6759 return 0;
6760 default:
6761 return 1;
6762 }
6763}
6764
6765static int
6766ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6767 struct rte_eth_dcb_info *dcb_info)
6768{
6769 struct ixgbe_dcb_config *dcb_config =
6770 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6771 struct ixgbe_dcb_tc_config *tc;
6772 uint8_t i, j;
6773
6774 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6775 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6776 else
6777 dcb_info->nb_tcs = 1;
6778
6779 if (dcb_config->vt_mode) { /* vt is enabled*/
6780 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6781 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6782 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6783 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6784 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6785 for (j = 0; j < dcb_info->nb_tcs; j++) {
6786 dcb_info->tc_queue.tc_rxq[i][j].base =
6787 i * dcb_info->nb_tcs + j;
6788 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6789 dcb_info->tc_queue.tc_txq[i][j].base =
6790 i * dcb_info->nb_tcs + j;
6791 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6792 }
6793 }
6794 } else { /* vt is disabled*/
6795 struct rte_eth_dcb_rx_conf *rx_conf =
6796 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6797 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6798 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6799 if (dcb_info->nb_tcs == ETH_4_TCS) {
6800 for (i = 0; i < dcb_info->nb_tcs; i++) {
6801 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6802 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6803 }
6804 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6805 dcb_info->tc_queue.tc_txq[0][1].base = 64;
6806 dcb_info->tc_queue.tc_txq[0][2].base = 96;
6807 dcb_info->tc_queue.tc_txq[0][3].base = 112;
6808 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6809 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6810 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6811 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6812 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6813 for (i = 0; i < dcb_info->nb_tcs; i++) {
6814 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6815 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6816 }
6817 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6818 dcb_info->tc_queue.tc_txq[0][1].base = 32;
6819 dcb_info->tc_queue.tc_txq[0][2].base = 64;
6820 dcb_info->tc_queue.tc_txq[0][3].base = 80;
6821 dcb_info->tc_queue.tc_txq[0][4].base = 96;
6822 dcb_info->tc_queue.tc_txq[0][5].base = 104;
6823 dcb_info->tc_queue.tc_txq[0][6].base = 112;
6824 dcb_info->tc_queue.tc_txq[0][7].base = 120;
6825 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6826 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6827 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6828 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6829 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6830 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6831 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6832 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6833 }
6834 }
6835 for (i = 0; i < dcb_info->nb_tcs; i++) {
6836 tc = &dcb_config->tc_config[i];
6837 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6838 }
6839 return 0;
6840}
6841
6842/* Update e-tag ether type */
6843static int
6844ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6845 uint16_t ether_type)
6846{
6847 uint32_t etag_etype;
6848
6849 if (hw->mac.type != ixgbe_mac_X550 &&
6850 hw->mac.type != ixgbe_mac_X550EM_x &&
6851 hw->mac.type != ixgbe_mac_X550EM_a) {
6852 return -ENOTSUP;
6853 }
6854
6855 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6856 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6857 etag_etype |= ether_type;
6858 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6859 IXGBE_WRITE_FLUSH(hw);
6860
6861 return 0;
6862}
6863
6864/* Config l2 tunnel ether type */
6865static int
6866ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6867 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6868{
6869 int ret = 0;
6870 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6871
6872 if (l2_tunnel == NULL)
6873 return -EINVAL;
6874
6875 switch (l2_tunnel->l2_tunnel_type) {
6876 case RTE_L2_TUNNEL_TYPE_E_TAG:
6877 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6878 break;
6879 default:
6880 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6881 ret = -EINVAL;
6882 break;
6883 }
6884
6885 return ret;
6886}
6887
6888/* Enable e-tag tunnel */
6889static int
6890ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6891{
6892 uint32_t etag_etype;
6893
6894 if (hw->mac.type != ixgbe_mac_X550 &&
6895 hw->mac.type != ixgbe_mac_X550EM_x &&
6896 hw->mac.type != ixgbe_mac_X550EM_a) {
6897 return -ENOTSUP;
6898 }
6899
6900 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6901 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6902 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6903 IXGBE_WRITE_FLUSH(hw);
6904
6905 return 0;
6906}
6907
6908/* Enable l2 tunnel */
6909static int
6910ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6911 enum rte_eth_tunnel_type l2_tunnel_type)
6912{
6913 int ret = 0;
6914 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6915
6916 switch (l2_tunnel_type) {
6917 case RTE_L2_TUNNEL_TYPE_E_TAG:
6918 ret = ixgbe_e_tag_enable(hw);
6919 break;
6920 default:
6921 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6922 ret = -EINVAL;
6923 break;
6924 }
6925
6926 return ret;
6927}
6928
6929/* Disable e-tag tunnel */
6930static int
6931ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6932{
6933 uint32_t etag_etype;
6934
6935 if (hw->mac.type != ixgbe_mac_X550 &&
6936 hw->mac.type != ixgbe_mac_X550EM_x &&
6937 hw->mac.type != ixgbe_mac_X550EM_a) {
6938 return -ENOTSUP;
6939 }
6940
6941 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6942 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6943 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6944 IXGBE_WRITE_FLUSH(hw);
6945
6946 return 0;
6947}
6948
6949/* Disable l2 tunnel */
6950static int
6951ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6952 enum rte_eth_tunnel_type l2_tunnel_type)
6953{
6954 int ret = 0;
6955 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6956
6957 switch (l2_tunnel_type) {
6958 case RTE_L2_TUNNEL_TYPE_E_TAG:
6959 ret = ixgbe_e_tag_disable(hw);
6960 break;
6961 default:
6962 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6963 ret = -EINVAL;
6964 break;
6965 }
6966
6967 return ret;
6968}
6969
6970static int
6971ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6972 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6973{
6974 int ret = 0;
6975 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6976 uint32_t i, rar_entries;
6977 uint32_t rar_low, rar_high;
6978
6979 if (hw->mac.type != ixgbe_mac_X550 &&
6980 hw->mac.type != ixgbe_mac_X550EM_x &&
6981 hw->mac.type != ixgbe_mac_X550EM_a) {
6982 return -ENOTSUP;
6983 }
6984
6985 rar_entries = ixgbe_get_num_rx_addrs(hw);
6986
6987 for (i = 1; i < rar_entries; i++) {
6988 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6989 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6990 if ((rar_high & IXGBE_RAH_AV) &&
6991 (rar_high & IXGBE_RAH_ADTYPE) &&
6992 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6993 l2_tunnel->tunnel_id)) {
6994 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6995 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6996
6997 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6998
6999 return ret;
7000 }
7001 }
7002
7003 return ret;
7004}
7005
7006static int
7007ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7008 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7009{
7010 int ret = 0;
7011 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7012 uint32_t i, rar_entries;
7013 uint32_t rar_low, rar_high;
7014
7015 if (hw->mac.type != ixgbe_mac_X550 &&
7016 hw->mac.type != ixgbe_mac_X550EM_x &&
7017 hw->mac.type != ixgbe_mac_X550EM_a) {
7018 return -ENOTSUP;
7019 }
7020
7021 /* One entry for one tunnel. Try to remove potential existing entry. */
7022 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7023
7024 rar_entries = ixgbe_get_num_rx_addrs(hw);
7025
7026 for (i = 1; i < rar_entries; i++) {
7027 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7028 if (rar_high & IXGBE_RAH_AV) {
7029 continue;
7030 } else {
7031 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7032 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7033 rar_low = l2_tunnel->tunnel_id;
7034
7035 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7036 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7037
7038 return ret;
7039 }
7040 }
7041
7042 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7043 " Please remove a rule before adding a new one.");
7044 return -EINVAL;
7045}
7046
7047/* Add l2 tunnel filter */
7048static int
7049ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7050 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7051{
7052 int ret = 0;
7053
7054 switch (l2_tunnel->l2_tunnel_type) {
7055 case RTE_L2_TUNNEL_TYPE_E_TAG:
7056 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7057 break;
7058 default:
7059 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7060 ret = -EINVAL;
7061 break;
7062 }
7063
7064 return ret;
7065}
7066
7067/* Delete l2 tunnel filter */
7068static int
7069ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7070 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7071{
7072 int ret = 0;
7073
7074 switch (l2_tunnel->l2_tunnel_type) {
7075 case RTE_L2_TUNNEL_TYPE_E_TAG:
7076 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7077 break;
7078 default:
7079 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7080 ret = -EINVAL;
7081 break;
7082 }
7083
7084 return ret;
7085}
7086
7087/**
7088 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7089 * @dev: pointer to rte_eth_dev structure
7090 * @filter_op:operation will be taken.
7091 * @arg: a pointer to specific structure corresponding to the filter_op
7092 */
7093static int
7094ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7095 enum rte_filter_op filter_op,
7096 void *arg)
7097{
7098 int ret = 0;
7099
7100 if (filter_op == RTE_ETH_FILTER_NOP)
7101 return 0;
7102
7103 if (arg == NULL) {
7104 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7105 filter_op);
7106 return -EINVAL;
7107 }
7108
7109 switch (filter_op) {
7110 case RTE_ETH_FILTER_ADD:
7111 ret = ixgbe_dev_l2_tunnel_filter_add
7112 (dev,
7113 (struct rte_eth_l2_tunnel_conf *)arg);
7114 break;
7115 case RTE_ETH_FILTER_DELETE:
7116 ret = ixgbe_dev_l2_tunnel_filter_del
7117 (dev,
7118 (struct rte_eth_l2_tunnel_conf *)arg);
7119 break;
7120 default:
7121 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7122 ret = -EINVAL;
7123 break;
7124 }
7125 return ret;
7126}
7127
7128static int
7129ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7130{
7131 int ret = 0;
7132 uint32_t ctrl;
7133 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7134
7135 if (hw->mac.type != ixgbe_mac_X550 &&
7136 hw->mac.type != ixgbe_mac_X550EM_x &&
7137 hw->mac.type != ixgbe_mac_X550EM_a) {
7138 return -ENOTSUP;
7139 }
7140
7141 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7142 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7143 if (en)
7144 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7145 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7146
7147 return ret;
7148}
7149
7150/* Enable l2 tunnel forwarding */
7151static int
7152ixgbe_dev_l2_tunnel_forwarding_enable
7153 (struct rte_eth_dev *dev,
7154 enum rte_eth_tunnel_type l2_tunnel_type)
7155{
7156 int ret = 0;
7157
7158 switch (l2_tunnel_type) {
7159 case RTE_L2_TUNNEL_TYPE_E_TAG:
7160 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7161 break;
7162 default:
7163 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7164 ret = -EINVAL;
7165 break;
7166 }
7167
7168 return ret;
7169}
7170
7171/* Disable l2 tunnel forwarding */
7172static int
7173ixgbe_dev_l2_tunnel_forwarding_disable
7174 (struct rte_eth_dev *dev,
7175 enum rte_eth_tunnel_type l2_tunnel_type)
7176{
7177 int ret = 0;
7178
7179 switch (l2_tunnel_type) {
7180 case RTE_L2_TUNNEL_TYPE_E_TAG:
7181 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7182 break;
7183 default:
7184 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7185 ret = -EINVAL;
7186 break;
7187 }
7188
7189 return ret;
7190}
7191
7192static int
7193ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7194 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7195 bool en)
7196{
7197 int ret = 0;
7198 uint32_t vmtir, vmvir;
7199 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7200
7201 if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
7202 PMD_DRV_LOG(ERR,
7203 "VF id %u should be less than %u",
7204 l2_tunnel->vf_id,
7205 dev->pci_dev->max_vfs);
7206 return -EINVAL;
7207 }
7208
7209 if (hw->mac.type != ixgbe_mac_X550 &&
7210 hw->mac.type != ixgbe_mac_X550EM_x &&
7211 hw->mac.type != ixgbe_mac_X550EM_a) {
7212 return -ENOTSUP;
7213 }
7214
7215 if (en)
7216 vmtir = l2_tunnel->tunnel_id;
7217 else
7218 vmtir = 0;
7219
7220 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7221
7222 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7223 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7224 if (en)
7225 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7226 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7227
7228 return ret;
7229}
7230
7231/* Enable l2 tunnel tag insertion */
7232static int
7233ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7234 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7235{
7236 int ret = 0;
7237
7238 switch (l2_tunnel->l2_tunnel_type) {
7239 case RTE_L2_TUNNEL_TYPE_E_TAG:
7240 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7241 break;
7242 default:
7243 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7244 ret = -EINVAL;
7245 break;
7246 }
7247
7248 return ret;
7249}
7250
7251/* Disable l2 tunnel tag insertion */
7252static int
7253ixgbe_dev_l2_tunnel_insertion_disable
7254 (struct rte_eth_dev *dev,
7255 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7256{
7257 int ret = 0;
7258
7259 switch (l2_tunnel->l2_tunnel_type) {
7260 case RTE_L2_TUNNEL_TYPE_E_TAG:
7261 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7262 break;
7263 default:
7264 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7265 ret = -EINVAL;
7266 break;
7267 }
7268
7269 return ret;
7270}
7271
7272static int
7273ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7274 bool en)
7275{
7276 int ret = 0;
7277 uint32_t qde;
7278 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7279
7280 if (hw->mac.type != ixgbe_mac_X550 &&
7281 hw->mac.type != ixgbe_mac_X550EM_x &&
7282 hw->mac.type != ixgbe_mac_X550EM_a) {
7283 return -ENOTSUP;
7284 }
7285
7286 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7287 if (en)
7288 qde |= IXGBE_QDE_STRIP_TAG;
7289 else
7290 qde &= ~IXGBE_QDE_STRIP_TAG;
7291 qde &= ~IXGBE_QDE_READ;
7292 qde |= IXGBE_QDE_WRITE;
7293 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7294
7295 return ret;
7296}
7297
7298/* Enable l2 tunnel tag stripping */
7299static int
7300ixgbe_dev_l2_tunnel_stripping_enable
7301 (struct rte_eth_dev *dev,
7302 enum rte_eth_tunnel_type l2_tunnel_type)
7303{
7304 int ret = 0;
7305
7306 switch (l2_tunnel_type) {
7307 case RTE_L2_TUNNEL_TYPE_E_TAG:
7308 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7309 break;
7310 default:
7311 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7312 ret = -EINVAL;
7313 break;
7314 }
7315
7316 return ret;
7317}
7318
7319/* Disable l2 tunnel tag stripping */
7320static int
7321ixgbe_dev_l2_tunnel_stripping_disable
7322 (struct rte_eth_dev *dev,
7323 enum rte_eth_tunnel_type l2_tunnel_type)
7324{
7325 int ret = 0;
7326
7327 switch (l2_tunnel_type) {
7328 case RTE_L2_TUNNEL_TYPE_E_TAG:
7329 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7330 break;
7331 default:
7332 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7333 ret = -EINVAL;
7334 break;
7335 }
7336
7337 return ret;
7338}
7339
7340/* Enable/disable l2 tunnel offload functions */
7341static int
7342ixgbe_dev_l2_tunnel_offload_set
7343 (struct rte_eth_dev *dev,
7344 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7345 uint32_t mask,
7346 uint8_t en)
7347{
7348 int ret = 0;
7349
7350 if (l2_tunnel == NULL)
7351 return -EINVAL;
7352
7353 ret = -EINVAL;
7354 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7355 if (en)
7356 ret = ixgbe_dev_l2_tunnel_enable(
7357 dev,
7358 l2_tunnel->l2_tunnel_type);
7359 else
7360 ret = ixgbe_dev_l2_tunnel_disable(
7361 dev,
7362 l2_tunnel->l2_tunnel_type);
7363 }
7364
7365 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7366 if (en)
7367 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7368 dev,
7369 l2_tunnel);
7370 else
7371 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7372 dev,
7373 l2_tunnel);
7374 }
7375
7376 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7377 if (en)
7378 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7379 dev,
7380 l2_tunnel->l2_tunnel_type);
7381 else
7382 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7383 dev,
7384 l2_tunnel->l2_tunnel_type);
7385 }
7386
7387 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7388 if (en)
7389 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7390 dev,
7391 l2_tunnel->l2_tunnel_type);
7392 else
7393 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7394 dev,
7395 l2_tunnel->l2_tunnel_type);
7396 }
7397
7398 return ret;
7399}
7400
7401static int
7402ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7403 uint16_t port)
7404{
7405 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7406 IXGBE_WRITE_FLUSH(hw);
7407
7408 return 0;
7409}
7410
7411/* There's only one register for VxLAN UDP port.
7412 * So, we cannot add several ports. Will update it.
7413 */
7414static int
7415ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7416 uint16_t port)
7417{
7418 if (port == 0) {
7419 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7420 return -EINVAL;
7421 }
7422
7423 return ixgbe_update_vxlan_port(hw, port);
7424}
7425
7426/* We cannot delete the VxLAN port. For there's a register for VxLAN
7427 * UDP port, it must have a value.
7428 * So, will reset it to the original value 0.
7429 */
7430static int
7431ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7432 uint16_t port)
7433{
7434 uint16_t cur_port;
7435
7436 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7437
7438 if (cur_port != port) {
7439 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7440 return -EINVAL;
7441 }
7442
7443 return ixgbe_update_vxlan_port(hw, 0);
7444}
7445
7446/* Add UDP tunneling port */
7447static int
7448ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7449 struct rte_eth_udp_tunnel *udp_tunnel)
7450{
7451 int ret = 0;
7452 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7453
7454 if (hw->mac.type != ixgbe_mac_X550 &&
7455 hw->mac.type != ixgbe_mac_X550EM_x &&
7456 hw->mac.type != ixgbe_mac_X550EM_a) {
7457 return -ENOTSUP;
7458 }
7459
7460 if (udp_tunnel == NULL)
7461 return -EINVAL;
7462
7463 switch (udp_tunnel->prot_type) {
7464 case RTE_TUNNEL_TYPE_VXLAN:
7465 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7466 break;
7467
7468 case RTE_TUNNEL_TYPE_GENEVE:
7469 case RTE_TUNNEL_TYPE_TEREDO:
7470 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7471 ret = -EINVAL;
7472 break;
7473
7474 default:
7475 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7476 ret = -EINVAL;
7477 break;
7478 }
7479
7480 return ret;
7481}
7482
7483/* Remove UDP tunneling port */
7484static int
7485ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7486 struct rte_eth_udp_tunnel *udp_tunnel)
7487{
7488 int ret = 0;
7489 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7490
7491 if (hw->mac.type != ixgbe_mac_X550 &&
7492 hw->mac.type != ixgbe_mac_X550EM_x &&
7493 hw->mac.type != ixgbe_mac_X550EM_a) {
7494 return -ENOTSUP;
7495 }
7496
7497 if (udp_tunnel == NULL)
7498 return -EINVAL;
7499
7500 switch (udp_tunnel->prot_type) {
7501 case RTE_TUNNEL_TYPE_VXLAN:
7502 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7503 break;
7504 case RTE_TUNNEL_TYPE_GENEVE:
7505 case RTE_TUNNEL_TYPE_TEREDO:
7506 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7507 ret = -EINVAL;
7508 break;
7509 default:
7510 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7511 ret = -EINVAL;
7512 break;
7513 }
7514
7515 return ret;
7516}
7517
7518static void
7519ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7520{
7521 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7522
7523 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7524}
7525
7526static void
7527ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7528{
7529 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7530
7531 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7532}
7533
7534static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7535{
7536 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7537 u32 in_msg = 0;
7538
7539 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7540 return;
7541
7542 /* PF reset VF event */
7543 if (in_msg == IXGBE_PF_CONTROL_MSG)
7544 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
7545}
7546
7547static int
7548ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7549{
7550 uint32_t eicr;
7551 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7552 struct ixgbe_interrupt *intr =
7553 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7554 ixgbevf_intr_disable(hw);
7555
7556 /* read-on-clear nic registers here */
7557 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7558 intr->flags = 0;
7559
7560 /* only one misc vector supported - mailbox */
7561 eicr &= IXGBE_VTEICR_MASK;
7562 if (eicr == IXGBE_MISC_VEC_ID)
7563 intr->flags |= IXGBE_FLAG_MAILBOX;
7564
7565 return 0;
7566}
7567
7568static int
7569ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7570{
7571 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7572 struct ixgbe_interrupt *intr =
7573 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7574
7575 if (intr->flags & IXGBE_FLAG_MAILBOX) {
7576 ixgbevf_mbx_process(dev);
7577 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7578 }
7579
7580 ixgbevf_intr_enable(hw);
7581
7582 return 0;
7583}
7584
7585static void
7586ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7587 void *param)
7588{
7589 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7590
7591 ixgbevf_dev_interrupt_get_status(dev);
7592 ixgbevf_dev_interrupt_action(dev);
7593}
7594
7595RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
7596RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
7597RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
7598RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
Ceph