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1 | /*- |
2 | * BSD LICENSE | |
3 | * | |
4 | * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. | |
5 | * All rights reserved. | |
6 | * | |
7 | * Redistribution and use in source and binary forms, with or without | |
8 | * modification, are permitted provided that the following conditions | |
9 | * are met: | |
10 | * | |
11 | * * Redistributions of source code must retain the above copyright | |
12 | * notice, this list of conditions and the following disclaimer. | |
13 | * * Redistributions in binary form must reproduce the above copyright | |
14 | * notice, this list of conditions and the following disclaimer in | |
15 | * the documentation and/or other materials provided with the | |
16 | * distribution. | |
17 | * * Neither the name of Intel Corporation nor the names of its | |
18 | * contributors may be used to endorse or promote products derived | |
19 | * from this software without specific prior written permission. | |
20 | * | |
21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
22 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
23 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
24 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
25 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
26 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
27 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
28 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
29 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | */ | |
33 | ||
34 | #ifndef _IXGBE_ETHDEV_H_ | |
35 | #define _IXGBE_ETHDEV_H_ | |
36 | #include "base/ixgbe_dcb.h" | |
37 | #include "base/ixgbe_dcb_82599.h" | |
38 | #include "base/ixgbe_dcb_82598.h" | |
39 | #include "ixgbe_bypass.h" | |
40 | #include <rte_time.h> | |
41 | ||
42 | /* need update link, bit flag */ | |
43 | #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0) | |
44 | #define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1) | |
45 | #define IXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2) | |
46 | ||
47 | /* | |
48 | * Defines that were not part of ixgbe_type.h as they are not used by the | |
49 | * FreeBSD driver. | |
50 | */ | |
51 | #define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */ | |
52 | #define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */ | |
53 | #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */ | |
54 | #define IXGBE_RXDADV_ERR_CKSUM_BIT 30 | |
55 | #define IXGBE_RXDADV_ERR_CKSUM_MSK 3 | |
56 | #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */ | |
57 | #define IXGBE_NB_STAT_MAPPING_REGS 32 | |
58 | #define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */ | |
59 | #define IXGBE_VFTA_SIZE 128 | |
60 | #define IXGBE_VLAN_TAG_SIZE 4 | |
61 | #define IXGBE_MAX_RX_QUEUE_NUM 128 | |
62 | #define IXGBE_MAX_INTR_QUEUE_NUM 15 | |
63 | #define IXGBE_VMDQ_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM | |
64 | #define IXGBE_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM | |
65 | #define IXGBE_NONE_MODE_TX_NB_QUEUES 64 | |
66 | ||
67 | #ifndef NBBY | |
68 | #define NBBY 8 /* number of bits in a byte */ | |
69 | #endif | |
70 | #define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY)) | |
71 | ||
72 | /* EITR Inteval is in 2048ns uinits for 1G and 10G link */ | |
73 | #define IXGBE_EITR_INTERVAL_UNIT_NS 2048 | |
74 | #define IXGBE_EITR_ITR_INT_SHIFT 3 | |
75 | #define IXGBE_EITR_INTERVAL_US(us) \ | |
76 | (((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \ | |
77 | IXGBE_EITR_ITR_INT_MASK) | |
78 | ||
79 | ||
80 | /* Loopback operation modes */ | |
81 | /* 82599 specific loopback operation types */ | |
82 | #define IXGBE_LPBK_82599_NONE 0x0 /* Default value. Loopback is disabled. */ | |
83 | #define IXGBE_LPBK_82599_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */ | |
84 | ||
85 | #define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */ | |
86 | ||
87 | #define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF | |
88 | #define IXGBE_RTTBCNRC_RF_INT_MASK_M \ | |
89 | (IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT) | |
90 | ||
91 | #define IXGBE_MAX_QUEUE_NUM_PER_VF 8 | |
92 | ||
93 | #define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */ | |
94 | #define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */ | |
95 | #define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */ | |
96 | #define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */ | |
97 | ||
98 | #define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */ | |
99 | #define IXGBE_ETQF_SHIFT 16 | |
100 | #define IXGBE_ETQF_UP_EN 0x00080000 | |
101 | #define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */ | |
102 | #define IXGBE_ETQF_MAX_PRI 7 | |
103 | ||
104 | #define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */ | |
105 | #define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */ | |
106 | #define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */ | |
107 | ||
108 | #define IXGBE_L34T_IMIR_SIZE_BP 0x00001000 | |
109 | #define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */ | |
110 | #define IXGBE_L34T_IMIR_LLI 0x00100000 | |
111 | #define IXGBE_L34T_IMIR_QUEUE 0x0FE00000 | |
112 | #define IXGBE_L34T_IMIR_QUEUE_SHIFT 21 | |
113 | #define IXGBE_5TUPLE_MAX_PRI 7 | |
114 | #define IXGBE_5TUPLE_MIN_PRI 1 | |
115 | ||
116 | #define IXGBE_RSS_OFFLOAD_ALL ( \ | |
117 | ETH_RSS_IPV4 | \ | |
118 | ETH_RSS_NONFRAG_IPV4_TCP | \ | |
119 | ETH_RSS_NONFRAG_IPV4_UDP | \ | |
120 | ETH_RSS_IPV6 | \ | |
121 | ETH_RSS_NONFRAG_IPV6_TCP | \ | |
122 | ETH_RSS_NONFRAG_IPV6_UDP | \ | |
123 | ETH_RSS_IPV6_EX | \ | |
124 | ETH_RSS_IPV6_TCP_EX | \ | |
125 | ETH_RSS_IPV6_UDP_EX) | |
126 | ||
127 | #define IXGBE_VF_IRQ_ENABLE_MASK 3 /* vf irq enable mask */ | |
128 | #define IXGBE_VF_MAXMSIVECTOR 1 | |
129 | ||
130 | #define IXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET | |
131 | #define IXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET | |
132 | ||
133 | /* | |
134 | * Information about the fdir mode. | |
135 | */ | |
136 | ||
137 | struct ixgbe_hw_fdir_mask { | |
138 | uint16_t vlan_tci_mask; | |
139 | uint32_t src_ipv4_mask; | |
140 | uint32_t dst_ipv4_mask; | |
141 | uint16_t src_ipv6_mask; | |
142 | uint16_t dst_ipv6_mask; | |
143 | uint16_t src_port_mask; | |
144 | uint16_t dst_port_mask; | |
145 | uint16_t flex_bytes_mask; | |
146 | uint8_t mac_addr_byte_mask; | |
147 | uint32_t tunnel_id_mask; | |
148 | uint8_t tunnel_type_mask; | |
149 | }; | |
150 | ||
151 | struct ixgbe_hw_fdir_info { | |
152 | struct ixgbe_hw_fdir_mask mask; | |
153 | uint8_t flex_bytes_offset; | |
154 | uint16_t collision; | |
155 | uint16_t free; | |
156 | uint16_t maxhash; | |
157 | uint8_t maxlen; | |
158 | uint64_t add; | |
159 | uint64_t remove; | |
160 | uint64_t f_add; | |
161 | uint64_t f_remove; | |
162 | }; | |
163 | ||
164 | /* structure for interrupt relative data */ | |
165 | struct ixgbe_interrupt { | |
166 | uint32_t flags; | |
167 | uint32_t mask; | |
168 | }; | |
169 | ||
170 | struct ixgbe_stat_mapping_registers { | |
171 | uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS]; | |
172 | uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS]; | |
173 | }; | |
174 | ||
175 | struct ixgbe_vfta { | |
176 | uint32_t vfta[IXGBE_VFTA_SIZE]; | |
177 | }; | |
178 | ||
179 | struct ixgbe_hwstrip { | |
180 | uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE]; | |
181 | }; | |
182 | ||
183 | /* | |
184 | * VF data which used by PF host only | |
185 | */ | |
186 | #define IXGBE_MAX_VF_MC_ENTRIES 30 | |
187 | #define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */ | |
188 | #define IXGBE_MAX_UTA 128 | |
189 | ||
190 | struct ixgbe_uta_info { | |
191 | uint8_t uc_filter_type; | |
192 | uint16_t uta_in_use; | |
193 | uint32_t uta_shadow[IXGBE_MAX_UTA]; | |
194 | }; | |
195 | ||
196 | #define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */ | |
197 | ||
198 | struct ixgbe_mirror_info { | |
199 | struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES]; | |
200 | /**< store PF mirror rules configuration*/ | |
201 | }; | |
202 | ||
203 | struct ixgbe_vf_info { | |
204 | uint8_t vf_mac_addresses[ETHER_ADDR_LEN]; | |
205 | uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; | |
206 | uint16_t num_vf_mc_hashes; | |
207 | uint16_t default_vf_vlan_id; | |
208 | uint16_t vlans_enabled; | |
209 | bool clear_to_send; | |
210 | uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF]; | |
211 | uint16_t vlan_count; | |
212 | uint8_t spoofchk_enabled; | |
213 | uint8_t api_version; | |
214 | }; | |
215 | ||
216 | /* | |
217 | * Possible l4type of 5tuple filters. | |
218 | */ | |
219 | enum ixgbe_5tuple_protocol { | |
220 | IXGBE_FILTER_PROTOCOL_TCP = 0, | |
221 | IXGBE_FILTER_PROTOCOL_UDP, | |
222 | IXGBE_FILTER_PROTOCOL_SCTP, | |
223 | IXGBE_FILTER_PROTOCOL_NONE, | |
224 | }; | |
225 | ||
226 | TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter); | |
227 | ||
228 | struct ixgbe_5tuple_filter_info { | |
229 | uint32_t dst_ip; | |
230 | uint32_t src_ip; | |
231 | uint16_t dst_port; | |
232 | uint16_t src_port; | |
233 | enum ixgbe_5tuple_protocol proto; /* l4 protocol. */ | |
234 | uint8_t priority; /* seven levels (001b-111b), 111b is highest, | |
235 | used when more than one filter matches. */ | |
236 | uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */ | |
237 | src_ip_mask:1, /* if mask is 1b, do not compare src ip. */ | |
238 | dst_port_mask:1, /* if mask is 1b, do not compare dst port. */ | |
239 | src_port_mask:1, /* if mask is 1b, do not compare src port. */ | |
240 | proto_mask:1; /* if mask is 1b, do not compare protocol. */ | |
241 | }; | |
242 | ||
243 | /* 5tuple filter structure */ | |
244 | struct ixgbe_5tuple_filter { | |
245 | TAILQ_ENTRY(ixgbe_5tuple_filter) entries; | |
246 | uint16_t index; /* the index of 5tuple filter */ | |
247 | struct ixgbe_5tuple_filter_info filter_info; | |
248 | uint16_t queue; /* rx queue assigned to */ | |
249 | }; | |
250 | ||
251 | #define IXGBE_5TUPLE_ARRAY_SIZE \ | |
252 | (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \ | |
253 | (sizeof(uint32_t) * NBBY)) | |
254 | ||
255 | /* | |
256 | * Structure to store filters' info. | |
257 | */ | |
258 | struct ixgbe_filter_info { | |
259 | uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */ | |
260 | /* store used ethertype filters*/ | |
261 | uint16_t ethertype_filters[IXGBE_MAX_ETQF_FILTERS]; | |
262 | /* Bit mask for every used 5tuple filter */ | |
263 | uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE]; | |
264 | struct ixgbe_5tuple_filter_list fivetuple_list; | |
265 | }; | |
266 | ||
267 | /* | |
268 | * Structure to store private data for each driver instance (for each port). | |
269 | */ | |
270 | struct ixgbe_adapter { | |
271 | struct ixgbe_hw hw; | |
272 | struct ixgbe_hw_stats stats; | |
273 | struct ixgbe_hw_fdir_info fdir; | |
274 | struct ixgbe_interrupt intr; | |
275 | struct ixgbe_stat_mapping_registers stat_mappings; | |
276 | struct ixgbe_vfta shadow_vfta; | |
277 | struct ixgbe_hwstrip hwstrip; | |
278 | struct ixgbe_dcb_config dcb_config; | |
279 | struct ixgbe_mirror_info mr_data; | |
280 | struct ixgbe_vf_info *vfdata; | |
281 | struct ixgbe_uta_info uta_info; | |
282 | #ifdef RTE_NIC_BYPASS | |
283 | struct ixgbe_bypass_info bps; | |
284 | #endif /* RTE_NIC_BYPASS */ | |
285 | struct ixgbe_filter_info filter; | |
286 | ||
287 | bool rx_bulk_alloc_allowed; | |
288 | bool rx_vec_allowed; | |
289 | struct rte_timecounter systime_tc; | |
290 | struct rte_timecounter rx_tstamp_tc; | |
291 | struct rte_timecounter tx_tstamp_tc; | |
292 | }; | |
293 | ||
294 | #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\ | |
295 | (&((struct ixgbe_adapter *)adapter)->hw) | |
296 | ||
297 | #define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \ | |
298 | (&((struct ixgbe_adapter *)adapter)->stats) | |
299 | ||
300 | #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \ | |
301 | (&((struct ixgbe_adapter *)adapter)->intr) | |
302 | ||
303 | #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \ | |
304 | (&((struct ixgbe_adapter *)adapter)->fdir) | |
305 | ||
306 | #define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \ | |
307 | (&((struct ixgbe_adapter *)adapter)->stat_mappings) | |
308 | ||
309 | #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \ | |
310 | (&((struct ixgbe_adapter *)adapter)->shadow_vfta) | |
311 | ||
312 | #define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \ | |
313 | (&((struct ixgbe_adapter *)adapter)->hwstrip) | |
314 | ||
315 | #define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \ | |
316 | (&((struct ixgbe_adapter *)adapter)->dcb_config) | |
317 | ||
318 | #define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \ | |
319 | (&((struct ixgbe_adapter *)adapter)->vfdata) | |
320 | ||
321 | #define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \ | |
322 | (&((struct ixgbe_adapter *)adapter)->mr_data) | |
323 | ||
324 | #define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \ | |
325 | (&((struct ixgbe_adapter *)adapter)->uta_info) | |
326 | ||
327 | #define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \ | |
328 | (&((struct ixgbe_adapter *)adapter)->filter) | |
329 | ||
330 | /* | |
331 | * RX/TX function prototypes | |
332 | */ | |
333 | void ixgbe_dev_clear_queues(struct rte_eth_dev *dev); | |
334 | ||
335 | void ixgbe_dev_free_queues(struct rte_eth_dev *dev); | |
336 | ||
337 | void ixgbe_dev_rx_queue_release(void *rxq); | |
338 | ||
339 | void ixgbe_dev_tx_queue_release(void *txq); | |
340 | ||
341 | int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, | |
342 | uint16_t nb_rx_desc, unsigned int socket_id, | |
343 | const struct rte_eth_rxconf *rx_conf, | |
344 | struct rte_mempool *mb_pool); | |
345 | ||
346 | int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, | |
347 | uint16_t nb_tx_desc, unsigned int socket_id, | |
348 | const struct rte_eth_txconf *tx_conf); | |
349 | ||
350 | uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, | |
351 | uint16_t rx_queue_id); | |
352 | ||
353 | int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset); | |
354 | int ixgbevf_dev_rx_descriptor_done(void *rx_queue, uint16_t offset); | |
355 | ||
356 | int ixgbe_dev_rx_init(struct rte_eth_dev *dev); | |
357 | ||
358 | void ixgbe_dev_tx_init(struct rte_eth_dev *dev); | |
359 | ||
360 | int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev); | |
361 | ||
362 | int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id); | |
363 | ||
364 | int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); | |
365 | ||
366 | int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id); | |
367 | ||
368 | int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id); | |
369 | ||
370 | void ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, | |
371 | struct rte_eth_rxq_info *qinfo); | |
372 | ||
373 | void ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, | |
374 | struct rte_eth_txq_info *qinfo); | |
375 | ||
376 | int ixgbevf_dev_rx_init(struct rte_eth_dev *dev); | |
377 | ||
378 | void ixgbevf_dev_tx_init(struct rte_eth_dev *dev); | |
379 | ||
380 | void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev); | |
381 | ||
382 | uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, | |
383 | uint16_t nb_pkts); | |
384 | ||
385 | uint16_t ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts, | |
386 | uint16_t nb_pkts); | |
387 | ||
388 | uint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue, | |
389 | struct rte_mbuf **rx_pkts, uint16_t nb_pkts); | |
390 | uint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue, | |
391 | struct rte_mbuf **rx_pkts, uint16_t nb_pkts); | |
392 | ||
393 | uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, | |
394 | uint16_t nb_pkts); | |
395 | ||
396 | uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts, | |
397 | uint16_t nb_pkts); | |
398 | ||
399 | int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev, | |
400 | struct rte_eth_rss_conf *rss_conf); | |
401 | ||
402 | int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, | |
403 | struct rte_eth_rss_conf *rss_conf); | |
404 | ||
405 | uint16_t ixgbe_reta_size_get(enum ixgbe_mac_type mac_type); | |
406 | ||
407 | uint32_t ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx); | |
408 | ||
409 | uint32_t ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type); | |
410 | ||
411 | uint32_t ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i); | |
412 | ||
413 | bool ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type); | |
414 | ||
415 | /* | |
416 | * Flow director function prototypes | |
417 | */ | |
418 | int ixgbe_fdir_configure(struct rte_eth_dev *dev); | |
419 | ||
420 | void ixgbe_configure_dcb(struct rte_eth_dev *dev); | |
421 | ||
422 | /* | |
423 | * misc function prototypes | |
424 | */ | |
425 | void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev); | |
426 | ||
427 | void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev); | |
428 | ||
429 | void ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev); | |
430 | ||
431 | void ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev); | |
432 | ||
433 | void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev); | |
434 | ||
435 | void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev); | |
436 | ||
437 | void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev); | |
438 | ||
439 | int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev); | |
440 | ||
441 | uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val); | |
442 | ||
443 | int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev, | |
444 | enum rte_filter_op filter_op, void *arg); | |
445 | #endif /* _IXGBE_ETHDEV_H_ */ |