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1 | /*- |
2 | * BSD LICENSE | |
3 | * | |
4 | * Copyright(c) 2010-2014 Intel Corporation. All rights reserved. | |
5 | * All rights reserved. | |
6 | * | |
7 | * Redistribution and use in source and binary forms, with or without | |
8 | * modification, are permitted provided that the following conditions | |
9 | * are met: | |
10 | * | |
11 | * * Redistributions of source code must retain the above copyright | |
12 | * notice, this list of conditions and the following disclaimer. | |
13 | * * Redistributions in binary form must reproduce the above copyright | |
14 | * notice, this list of conditions and the following disclaimer in | |
15 | * the documentation and/or other materials provided with the | |
16 | * distribution. | |
17 | * * Neither the name of Intel Corporation nor the names of its | |
18 | * contributors may be used to endorse or promote products derived | |
19 | * from this software without specific prior written permission. | |
20 | * | |
21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
22 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
23 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
24 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
25 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
26 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
27 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
28 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
29 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | */ | |
33 | ||
34 | #ifndef _IXGBE_RXTX_H_ | |
35 | #define _IXGBE_RXTX_H_ | |
36 | ||
37 | /* | |
38 | * Rings setup and release. | |
39 | * | |
40 | * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be | |
41 | * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will | |
42 | * also optimize cache line size effect. H/W supports up to cache line size 128. | |
43 | */ | |
44 | #define IXGBE_ALIGN 128 | |
45 | ||
46 | #define IXGBE_RXD_ALIGN (IXGBE_ALIGN / sizeof(union ixgbe_adv_rx_desc)) | |
47 | #define IXGBE_TXD_ALIGN (IXGBE_ALIGN / sizeof(union ixgbe_adv_tx_desc)) | |
48 | ||
49 | /* | |
50 | * Maximum number of Ring Descriptors. | |
51 | * | |
52 | * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring | |
53 | * descriptors should meet the following condition: | |
54 | * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0 | |
55 | */ | |
56 | #define IXGBE_MIN_RING_DESC 32 | |
57 | #define IXGBE_MAX_RING_DESC 4096 | |
58 | ||
59 | #define RTE_PMD_IXGBE_TX_MAX_BURST 32 | |
60 | #define RTE_PMD_IXGBE_RX_MAX_BURST 32 | |
61 | #define RTE_IXGBE_TX_MAX_FREE_BUF_SZ 64 | |
62 | ||
63 | #define RTE_IXGBE_DESCS_PER_LOOP 4 | |
64 | ||
65 | #ifdef RTE_IXGBE_INC_VECTOR | |
66 | #define RTE_IXGBE_RXQ_REARM_THRESH 32 | |
67 | #define RTE_IXGBE_MAX_RX_BURST RTE_IXGBE_RXQ_REARM_THRESH | |
68 | #endif | |
69 | ||
70 | #define RX_RING_SZ ((IXGBE_MAX_RING_DESC + RTE_IXGBE_DESCS_PER_LOOP - 1) * \ | |
71 | sizeof(union ixgbe_adv_rx_desc)) | |
72 | ||
73 | #ifdef RTE_PMD_PACKET_PREFETCH | |
74 | #define rte_packet_prefetch(p) rte_prefetch1(p) | |
75 | #else | |
76 | #define rte_packet_prefetch(p) do {} while(0) | |
77 | #endif | |
78 | ||
79 | #define RTE_IXGBE_REGISTER_POLL_WAIT_10_MS 10 | |
80 | #define RTE_IXGBE_WAIT_100_US 100 | |
81 | #define RTE_IXGBE_VMTXSW_REGISTER_COUNT 2 | |
82 | ||
83 | #define IXGBE_PACKET_TYPE_MASK_82599 0X7F | |
84 | #define IXGBE_PACKET_TYPE_MASK_X550 0X10FF | |
85 | #define IXGBE_PACKET_TYPE_MASK_TUNNEL 0XFF | |
86 | #define IXGBE_PACKET_TYPE_TUNNEL_BIT 0X1000 | |
87 | ||
88 | /** | |
89 | * Structure associated with each descriptor of the RX ring of a RX queue. | |
90 | */ | |
91 | struct ixgbe_rx_entry { | |
92 | struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */ | |
93 | }; | |
94 | ||
95 | struct ixgbe_scattered_rx_entry { | |
96 | struct rte_mbuf *fbuf; /**< First segment of the fragmented packet. */ | |
97 | }; | |
98 | ||
99 | /** | |
100 | * Structure associated with each descriptor of the TX ring of a TX queue. | |
101 | */ | |
102 | struct ixgbe_tx_entry { | |
103 | struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */ | |
104 | uint16_t next_id; /**< Index of next descriptor in ring. */ | |
105 | uint16_t last_id; /**< Index of last scattered descriptor. */ | |
106 | }; | |
107 | ||
108 | /** | |
109 | * Structure associated with each descriptor of the TX ring of a TX queue. | |
110 | */ | |
111 | struct ixgbe_tx_entry_v { | |
112 | struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */ | |
113 | }; | |
114 | ||
115 | /** | |
116 | * Structure associated with each RX queue. | |
117 | */ | |
118 | struct ixgbe_rx_queue { | |
119 | struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */ | |
120 | volatile union ixgbe_adv_rx_desc *rx_ring; /**< RX ring virtual address. */ | |
121 | uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */ | |
122 | volatile uint32_t *rdt_reg_addr; /**< RDT register address. */ | |
123 | volatile uint32_t *rdh_reg_addr; /**< RDH register address. */ | |
124 | struct ixgbe_rx_entry *sw_ring; /**< address of RX software ring. */ | |
125 | struct ixgbe_scattered_rx_entry *sw_sc_ring; /**< address of scattered Rx software ring. */ | |
126 | struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */ | |
127 | struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */ | |
128 | uint64_t mbuf_initializer; /**< value to init mbufs */ | |
129 | uint16_t nb_rx_desc; /**< number of RX descriptors. */ | |
130 | uint16_t rx_tail; /**< current value of RDT register. */ | |
131 | uint16_t nb_rx_hold; /**< number of held free RX desc. */ | |
132 | uint16_t rx_nb_avail; /**< nr of staged pkts ready to ret to app */ | |
133 | uint16_t rx_next_avail; /**< idx of next staged pkt to ret to app */ | |
134 | uint16_t rx_free_trigger; /**< triggers rx buffer allocation */ | |
135 | uint16_t rx_using_sse; | |
136 | /**< indicates that vector RX is in use */ | |
137 | #ifdef RTE_IXGBE_INC_VECTOR | |
138 | uint16_t rxrearm_nb; /**< number of remaining to be re-armed */ | |
139 | uint16_t rxrearm_start; /**< the idx we start the re-arming from */ | |
140 | #endif | |
141 | uint16_t rx_free_thresh; /**< max free RX desc to hold. */ | |
142 | uint16_t queue_id; /**< RX queue index. */ | |
143 | uint16_t reg_idx; /**< RX queue register index. */ | |
144 | uint16_t pkt_type_mask; /**< Packet type mask for different NICs. */ | |
145 | uint8_t port_id; /**< Device port identifier. */ | |
146 | uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */ | |
147 | uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */ | |
148 | uint8_t rx_deferred_start; /**< not in global dev start. */ | |
149 | /** flags to set in mbuf when a vlan is detected. */ | |
150 | uint64_t vlan_flags; | |
151 | /** need to alloc dummy mbuf, for wraparound when scanning hw ring */ | |
152 | struct rte_mbuf fake_mbuf; | |
153 | /** hold packets to return to application */ | |
154 | struct rte_mbuf *rx_stage[RTE_PMD_IXGBE_RX_MAX_BURST*2]; | |
155 | }; | |
156 | ||
157 | /** | |
158 | * IXGBE CTX Constants | |
159 | */ | |
160 | enum ixgbe_advctx_num { | |
161 | IXGBE_CTX_0 = 0, /**< CTX0 */ | |
162 | IXGBE_CTX_1 = 1, /**< CTX1 */ | |
163 | IXGBE_CTX_NUM = 2, /**< CTX NUMBER */ | |
164 | }; | |
165 | ||
166 | /** Offload features */ | |
167 | union ixgbe_tx_offload { | |
168 | uint64_t data[2]; | |
169 | struct { | |
170 | uint64_t l2_len:7; /**< L2 (MAC) Header Length. */ | |
171 | uint64_t l3_len:9; /**< L3 (IP) Header Length. */ | |
172 | uint64_t l4_len:8; /**< L4 (TCP/UDP) Header Length. */ | |
173 | uint64_t tso_segsz:16; /**< TCP TSO segment size */ | |
174 | uint64_t vlan_tci:16; | |
175 | /**< VLAN Tag Control Identifier (CPU order). */ | |
176 | ||
177 | /* fields for TX offloading of tunnels */ | |
178 | uint64_t outer_l3_len:8; /**< Outer L3 (IP) Hdr Length. */ | |
179 | uint64_t outer_l2_len:8; /**< Outer L2 (MAC) Hdr Length. */ | |
180 | }; | |
181 | }; | |
182 | ||
183 | /* | |
184 | * Compare mask for vlan_macip_len.data, | |
185 | * should be in sync with ixgbe_vlan_macip.f layout. | |
186 | * */ | |
187 | #define TX_VLAN_CMP_MASK 0xFFFF0000 /**< VLAN length - 16-bits. */ | |
188 | #define TX_MAC_LEN_CMP_MASK 0x0000FE00 /**< MAC length - 7-bits. */ | |
189 | #define TX_IP_LEN_CMP_MASK 0x000001FF /**< IP length - 9-bits. */ | |
190 | /** MAC+IP length. */ | |
191 | #define TX_MACIP_LEN_CMP_MASK (TX_MAC_LEN_CMP_MASK | TX_IP_LEN_CMP_MASK) | |
192 | ||
193 | /** | |
194 | * Structure to check if new context need be built | |
195 | */ | |
196 | ||
197 | struct ixgbe_advctx_info { | |
198 | uint64_t flags; /**< ol_flags for context build. */ | |
199 | /**< tx offload: vlan, tso, l2-l3-l4 lengths. */ | |
200 | union ixgbe_tx_offload tx_offload; | |
201 | /** compare mask for tx offload. */ | |
202 | union ixgbe_tx_offload tx_offload_mask; | |
203 | }; | |
204 | ||
205 | /** | |
206 | * Structure associated with each TX queue. | |
207 | */ | |
208 | struct ixgbe_tx_queue { | |
209 | /** TX ring virtual address. */ | |
210 | volatile union ixgbe_adv_tx_desc *tx_ring; | |
211 | uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */ | |
212 | union { | |
213 | struct ixgbe_tx_entry *sw_ring; /**< address of SW ring for scalar PMD. */ | |
214 | struct ixgbe_tx_entry_v *sw_ring_v; /**< address of SW ring for vector PMD */ | |
215 | }; | |
216 | volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */ | |
217 | uint16_t nb_tx_desc; /**< number of TX descriptors. */ | |
218 | uint16_t tx_tail; /**< current value of TDT reg. */ | |
219 | /**< Start freeing TX buffers if there are less free descriptors than | |
220 | this value. */ | |
221 | uint16_t tx_free_thresh; | |
222 | /** Number of TX descriptors to use before RS bit is set. */ | |
223 | uint16_t tx_rs_thresh; | |
224 | /** Number of TX descriptors used since RS bit was set. */ | |
225 | uint16_t nb_tx_used; | |
226 | /** Index to last TX descriptor to have been cleaned. */ | |
227 | uint16_t last_desc_cleaned; | |
228 | /** Total number of TX descriptors ready to be allocated. */ | |
229 | uint16_t nb_tx_free; | |
230 | uint16_t tx_next_dd; /**< next desc to scan for DD bit */ | |
231 | uint16_t tx_next_rs; /**< next desc to set RS bit */ | |
232 | uint16_t queue_id; /**< TX queue index. */ | |
233 | uint16_t reg_idx; /**< TX queue register index. */ | |
234 | uint8_t port_id; /**< Device port identifier. */ | |
235 | uint8_t pthresh; /**< Prefetch threshold register. */ | |
236 | uint8_t hthresh; /**< Host threshold register. */ | |
237 | uint8_t wthresh; /**< Write-back threshold reg. */ | |
238 | uint32_t txq_flags; /**< Holds flags for this TXq */ | |
239 | uint32_t ctx_curr; /**< Hardware context states. */ | |
240 | /** Hardware context0 history. */ | |
241 | struct ixgbe_advctx_info ctx_cache[IXGBE_CTX_NUM]; | |
242 | const struct ixgbe_txq_ops *ops; /**< txq ops */ | |
243 | uint8_t tx_deferred_start; /**< not in global dev start. */ | |
244 | }; | |
245 | ||
246 | struct ixgbe_txq_ops { | |
247 | void (*release_mbufs)(struct ixgbe_tx_queue *txq); | |
248 | void (*free_swring)(struct ixgbe_tx_queue *txq); | |
249 | void (*reset)(struct ixgbe_tx_queue *txq); | |
250 | }; | |
251 | ||
252 | /* | |
253 | * The "simple" TX queue functions require that the following | |
254 | * flags are set when the TX queue is configured: | |
255 | * - ETH_TXQ_FLAGS_NOMULTSEGS | |
256 | * - ETH_TXQ_FLAGS_NOVLANOFFL | |
257 | * - ETH_TXQ_FLAGS_NOXSUMSCTP | |
258 | * - ETH_TXQ_FLAGS_NOXSUMUDP | |
259 | * - ETH_TXQ_FLAGS_NOXSUMTCP | |
260 | * and that the RS bit threshold (tx_rs_thresh) is at least equal to | |
261 | * RTE_PMD_IXGBE_TX_MAX_BURST. | |
262 | */ | |
263 | #define IXGBE_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \ | |
264 | ETH_TXQ_FLAGS_NOOFFLOADS) | |
265 | ||
266 | /* | |
267 | * Populate descriptors with the following info: | |
268 | * 1.) buffer_addr = phys_addr + headroom | |
269 | * 2.) cmd_type_len = DCMD_DTYP_FLAGS | pkt_len | |
270 | * 3.) olinfo_status = pkt_len << PAYLEN_SHIFT | |
271 | */ | |
272 | ||
273 | /* Defines for Tx descriptor */ | |
274 | #define DCMD_DTYP_FLAGS (IXGBE_ADVTXD_DTYP_DATA |\ | |
275 | IXGBE_ADVTXD_DCMD_IFCS |\ | |
276 | IXGBE_ADVTXD_DCMD_DEXT |\ | |
277 | IXGBE_ADVTXD_DCMD_EOP) | |
278 | ||
279 | ||
280 | /* Takes an ethdev and a queue and sets up the tx function to be used based on | |
281 | * the queue parameters. Used in tx_queue_setup by primary process and then | |
282 | * in dev_init by secondary process when attaching to an existing ethdev. | |
283 | */ | |
284 | void ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq); | |
285 | ||
286 | /** | |
287 | * Sets the rx_pkt_burst callback in the ixgbe rte_eth_dev instance. | |
288 | * | |
289 | * Sets the callback based on the device parameters: | |
290 | * - ixgbe_hw.rx_bulk_alloc_allowed | |
291 | * - rte_eth_dev_data.scattered_rx | |
292 | * - rte_eth_dev_data.lro | |
293 | * - conditions checked in ixgbe_rx_vec_condition_check() | |
294 | * | |
295 | * This means that the parameters above have to be configured prior to calling | |
296 | * to this function. | |
297 | * | |
298 | * @dev rte_eth_dev handle | |
299 | */ | |
300 | void ixgbe_set_rx_function(struct rte_eth_dev *dev); | |
301 | ||
302 | uint16_t ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, | |
303 | uint16_t nb_pkts); | |
304 | uint16_t ixgbe_recv_scattered_pkts_vec(void *rx_queue, | |
305 | struct rte_mbuf **rx_pkts, uint16_t nb_pkts); | |
306 | int ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev); | |
307 | int ixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq); | |
308 | void ixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue *rxq); | |
309 | ||
310 | #ifdef RTE_IXGBE_INC_VECTOR | |
311 | ||
312 | uint16_t ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts, | |
313 | uint16_t nb_pkts); | |
314 | int ixgbe_txq_vec_setup(struct ixgbe_tx_queue *txq); | |
315 | ||
316 | #endif /* RTE_IXGBE_INC_VECTOR */ | |
317 | #endif /* _IXGBE_RXTX_H_ */ |