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1 | /* |
2 | * Copyright (c) 2016 QLogic Corporation. | |
3 | * All rights reserved. | |
4 | * www.qlogic.com | |
5 | * | |
6 | * See LICENSE.qede_pmd for copyright and licensing details. | |
7 | */ | |
8 | ||
9 | #ifndef __ATTN_VALUES_H__ | |
10 | #define __ATTN_VALUES_H__ | |
11 | ||
12 | #ifndef __PREVENT_INT_ATTN__ | |
13 | ||
14 | /* HW Attention register */ | |
15 | struct attn_hw_reg { | |
16 | u16 reg_idx; /* Index of this register in its block */ | |
17 | u16 num_of_bits; /* number of valid attention bits */ | |
18 | const u16 *bit_attn_idx; /* attention index per valid bit */ | |
19 | u32 sts_addr; /* Address of the STS register */ | |
20 | u32 sts_clr_addr; /* Address of the STS_CLR register */ | |
21 | u32 sts_wr_addr; /* Address of the STS_WR register */ | |
22 | u32 mask_addr; /* Address of the MASK register */ | |
23 | }; | |
24 | ||
25 | /* HW block attention registers */ | |
26 | struct attn_hw_regs { | |
27 | u16 num_of_int_regs; /* Number of interrupt regs */ | |
28 | u16 num_of_prty_regs; /* Number of parity regs */ | |
29 | struct attn_hw_reg **int_regs; /* interrupt regs */ | |
30 | struct attn_hw_reg **prty_regs; /* parity regs */ | |
31 | }; | |
32 | ||
33 | /* HW block attention registers */ | |
34 | struct attn_hw_block { | |
35 | const char *name; /* Block name */ | |
36 | const char **int_desc; /* Array of interrupt attention descriptions */ | |
37 | const char **prty_desc; /* Array of parity attention descriptions */ | |
38 | struct attn_hw_regs chip_regs[3]; /* attention regs per chip.*/ | |
39 | }; | |
40 | ||
41 | #ifdef ATTN_DESC | |
42 | static const char *grc_int_attn_desc[5] = { | |
43 | "grc_address_error", | |
44 | "grc_timeout_event", | |
45 | "grc_global_reserved_address", | |
46 | "grc_path_isolation_error", | |
47 | "grc_trace_fifo_valid_data", | |
48 | }; | |
49 | #else | |
50 | #define grc_int_attn_desc OSAL_NULL | |
51 | #endif | |
52 | ||
53 | static const u16 grc_int0_bb_a0_attn_idx[4] = { | |
54 | 0, 1, 2, 3, | |
55 | }; | |
56 | ||
57 | static struct attn_hw_reg grc_int0_bb_a0 = { | |
58 | 0, 4, grc_int0_bb_a0_attn_idx, 0x50180, 0x5018c, 0x50188, 0x50184 | |
59 | }; | |
60 | ||
61 | static struct attn_hw_reg *grc_int_bb_a0_regs[1] = { | |
62 | &grc_int0_bb_a0, | |
63 | }; | |
64 | ||
65 | static const u16 grc_int0_bb_b0_attn_idx[4] = { | |
66 | 0, 1, 2, 3, | |
67 | }; | |
68 | ||
69 | static struct attn_hw_reg grc_int0_bb_b0 = { | |
70 | 0, 4, grc_int0_bb_b0_attn_idx, 0x50180, 0x5018c, 0x50188, 0x50184 | |
71 | }; | |
72 | ||
73 | static struct attn_hw_reg *grc_int_bb_b0_regs[1] = { | |
74 | &grc_int0_bb_b0, | |
75 | }; | |
76 | ||
77 | static const u16 grc_int0_k2_attn_idx[5] = { | |
78 | 0, 1, 2, 3, 4, | |
79 | }; | |
80 | ||
81 | static struct attn_hw_reg grc_int0_k2 = { | |
82 | 0, 5, grc_int0_k2_attn_idx, 0x50180, 0x5018c, 0x50188, 0x50184 | |
83 | }; | |
84 | ||
85 | static struct attn_hw_reg *grc_int_k2_regs[1] = { | |
86 | &grc_int0_k2, | |
87 | }; | |
88 | ||
89 | #ifdef ATTN_DESC | |
90 | static const char *grc_prty_attn_desc[3] = { | |
91 | "grc_mem003_i_mem_prty", | |
92 | "grc_mem002_i_mem_prty", | |
93 | "grc_mem001_i_mem_prty", | |
94 | }; | |
95 | #else | |
96 | #define grc_prty_attn_desc OSAL_NULL | |
97 | #endif | |
98 | ||
99 | static const u16 grc_prty1_bb_a0_attn_idx[2] = { | |
100 | 1, 2, | |
101 | }; | |
102 | ||
103 | static struct attn_hw_reg grc_prty1_bb_a0 = { | |
104 | 0, 2, grc_prty1_bb_a0_attn_idx, 0x50200, 0x5020c, 0x50208, 0x50204 | |
105 | }; | |
106 | ||
107 | static struct attn_hw_reg *grc_prty_bb_a0_regs[1] = { | |
108 | &grc_prty1_bb_a0, | |
109 | }; | |
110 | ||
111 | static const u16 grc_prty1_bb_b0_attn_idx[2] = { | |
112 | 0, 1, | |
113 | }; | |
114 | ||
115 | static struct attn_hw_reg grc_prty1_bb_b0 = { | |
116 | 0, 2, grc_prty1_bb_b0_attn_idx, 0x50200, 0x5020c, 0x50208, 0x50204 | |
117 | }; | |
118 | ||
119 | static struct attn_hw_reg *grc_prty_bb_b0_regs[1] = { | |
120 | &grc_prty1_bb_b0, | |
121 | }; | |
122 | ||
123 | static const u16 grc_prty1_k2_attn_idx[2] = { | |
124 | 0, 1, | |
125 | }; | |
126 | ||
127 | static struct attn_hw_reg grc_prty1_k2 = { | |
128 | 0, 2, grc_prty1_k2_attn_idx, 0x50200, 0x5020c, 0x50208, 0x50204 | |
129 | }; | |
130 | ||
131 | static struct attn_hw_reg *grc_prty_k2_regs[1] = { | |
132 | &grc_prty1_k2, | |
133 | }; | |
134 | ||
135 | #ifdef ATTN_DESC | |
136 | static const char *miscs_int_attn_desc[14] = { | |
137 | "miscs_address_error", | |
138 | "miscs_generic_sw", | |
139 | "miscs_cnig_interrupt", | |
140 | "miscs_opte_dorq_fifo_err_eng1", | |
141 | "miscs_opte_dorq_fifo_err_eng0", | |
142 | "miscs_opte_dbg_fifo_err_eng1", | |
143 | "miscs_opte_dbg_fifo_err_eng0", | |
144 | "miscs_opte_btb_if1_fifo_err_eng1", | |
145 | "miscs_opte_btb_if1_fifo_err_eng0", | |
146 | "miscs_opte_btb_if0_fifo_err_eng1", | |
147 | "miscs_opte_btb_if0_fifo_err_eng0", | |
148 | "miscs_opte_btb_sop_fifo_err_eng1", | |
149 | "miscs_opte_btb_sop_fifo_err_eng0", | |
150 | "miscs_opte_storm_fifo_err_eng0", | |
151 | }; | |
152 | #else | |
153 | #define miscs_int_attn_desc OSAL_NULL | |
154 | #endif | |
155 | ||
156 | static const u16 miscs_int0_bb_a0_attn_idx[2] = { | |
157 | 0, 1, | |
158 | }; | |
159 | ||
160 | static struct attn_hw_reg miscs_int0_bb_a0 = { | |
161 | 0, 2, miscs_int0_bb_a0_attn_idx, 0x9180, 0x918c, 0x9188, 0x9184 | |
162 | }; | |
163 | ||
164 | static const u16 miscs_int1_bb_a0_attn_idx[11] = { | |
165 | 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, | |
166 | }; | |
167 | ||
168 | static struct attn_hw_reg miscs_int1_bb_a0 = { | |
169 | 1, 11, miscs_int1_bb_a0_attn_idx, 0x9190, 0x919c, 0x9198, 0x9194 | |
170 | }; | |
171 | ||
172 | static struct attn_hw_reg *miscs_int_bb_a0_regs[2] = { | |
173 | &miscs_int0_bb_a0, &miscs_int1_bb_a0, | |
174 | }; | |
175 | ||
176 | static const u16 miscs_int0_bb_b0_attn_idx[3] = { | |
177 | 0, 1, 2, | |
178 | }; | |
179 | ||
180 | static struct attn_hw_reg miscs_int0_bb_b0 = { | |
181 | 0, 3, miscs_int0_bb_b0_attn_idx, 0x9180, 0x918c, 0x9188, 0x9184 | |
182 | }; | |
183 | ||
184 | static const u16 miscs_int1_bb_b0_attn_idx[11] = { | |
185 | 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, | |
186 | }; | |
187 | ||
188 | static struct attn_hw_reg miscs_int1_bb_b0 = { | |
189 | 1, 11, miscs_int1_bb_b0_attn_idx, 0x9190, 0x919c, 0x9198, 0x9194 | |
190 | }; | |
191 | ||
192 | static struct attn_hw_reg *miscs_int_bb_b0_regs[2] = { | |
193 | &miscs_int0_bb_b0, &miscs_int1_bb_b0, | |
194 | }; | |
195 | ||
196 | static const u16 miscs_int0_k2_attn_idx[3] = { | |
197 | 0, 1, 2, | |
198 | }; | |
199 | ||
200 | static struct attn_hw_reg miscs_int0_k2 = { | |
201 | 0, 3, miscs_int0_k2_attn_idx, 0x9180, 0x918c, 0x9188, 0x9184 | |
202 | }; | |
203 | ||
204 | static struct attn_hw_reg *miscs_int_k2_regs[1] = { | |
205 | &miscs_int0_k2, | |
206 | }; | |
207 | ||
208 | #ifdef ATTN_DESC | |
209 | static const char *miscs_prty_attn_desc[1] = { | |
210 | "miscs_cnig_parity", | |
211 | }; | |
212 | #else | |
213 | #define miscs_prty_attn_desc OSAL_NULL | |
214 | #endif | |
215 | ||
216 | static const u16 miscs_prty0_bb_b0_attn_idx[1] = { | |
217 | 0, | |
218 | }; | |
219 | ||
220 | static struct attn_hw_reg miscs_prty0_bb_b0 = { | |
221 | 0, 1, miscs_prty0_bb_b0_attn_idx, 0x91a0, 0x91ac, 0x91a8, 0x91a4 | |
222 | }; | |
223 | ||
224 | static struct attn_hw_reg *miscs_prty_bb_b0_regs[1] = { | |
225 | &miscs_prty0_bb_b0, | |
226 | }; | |
227 | ||
228 | static const u16 miscs_prty0_k2_attn_idx[1] = { | |
229 | 0, | |
230 | }; | |
231 | ||
232 | static struct attn_hw_reg miscs_prty0_k2 = { | |
233 | 0, 1, miscs_prty0_k2_attn_idx, 0x91a0, 0x91ac, 0x91a8, 0x91a4 | |
234 | }; | |
235 | ||
236 | static struct attn_hw_reg *miscs_prty_k2_regs[1] = { | |
237 | &miscs_prty0_k2, | |
238 | }; | |
239 | ||
240 | #ifdef ATTN_DESC | |
241 | static const char *misc_int_attn_desc[1] = { | |
242 | "misc_address_error", | |
243 | }; | |
244 | #else | |
245 | #define misc_int_attn_desc OSAL_NULL | |
246 | #endif | |
247 | ||
248 | static const u16 misc_int0_bb_a0_attn_idx[1] = { | |
249 | 0, | |
250 | }; | |
251 | ||
252 | static struct attn_hw_reg misc_int0_bb_a0 = { | |
253 | 0, 1, misc_int0_bb_a0_attn_idx, 0x8180, 0x818c, 0x8188, 0x8184 | |
254 | }; | |
255 | ||
256 | static struct attn_hw_reg *misc_int_bb_a0_regs[1] = { | |
257 | &misc_int0_bb_a0, | |
258 | }; | |
259 | ||
260 | static const u16 misc_int0_bb_b0_attn_idx[1] = { | |
261 | 0, | |
262 | }; | |
263 | ||
264 | static struct attn_hw_reg misc_int0_bb_b0 = { | |
265 | 0, 1, misc_int0_bb_b0_attn_idx, 0x8180, 0x818c, 0x8188, 0x8184 | |
266 | }; | |
267 | ||
268 | static struct attn_hw_reg *misc_int_bb_b0_regs[1] = { | |
269 | &misc_int0_bb_b0, | |
270 | }; | |
271 | ||
272 | static const u16 misc_int0_k2_attn_idx[1] = { | |
273 | 0, | |
274 | }; | |
275 | ||
276 | static struct attn_hw_reg misc_int0_k2 = { | |
277 | 0, 1, misc_int0_k2_attn_idx, 0x8180, 0x818c, 0x8188, 0x8184 | |
278 | }; | |
279 | ||
280 | static struct attn_hw_reg *misc_int_k2_regs[1] = { | |
281 | &misc_int0_k2, | |
282 | }; | |
283 | ||
284 | #ifdef ATTN_DESC | |
285 | static const char *pglue_b_int_attn_desc[24] = { | |
286 | "pglue_b_address_error", | |
287 | "pglue_b_incorrect_rcv_behavior", | |
288 | "pglue_b_was_error_attn", | |
289 | "pglue_b_vf_length_violation_attn", | |
290 | "pglue_b_vf_grc_space_violation_attn", | |
291 | "pglue_b_tcpl_error_attn", | |
292 | "pglue_b_tcpl_in_two_rcbs_attn", | |
293 | "pglue_b_cssnoop_fifo_overflow", | |
294 | "pglue_b_tcpl_translation_size_different", | |
295 | "pglue_b_pcie_rx_l0s_timeout", | |
296 | "pglue_b_master_zlr_attn", | |
297 | "pglue_b_admin_window_violation_attn", | |
298 | "pglue_b_out_of_range_function_in_pretend", | |
299 | "pglue_b_illegal_address", | |
300 | "pglue_b_pgl_cpl_err", | |
301 | "pglue_b_pgl_txw_of", | |
302 | "pglue_b_pgl_cpl_aft", | |
303 | "pglue_b_pgl_cpl_of", | |
304 | "pglue_b_pgl_cpl_ecrc", | |
305 | "pglue_b_pgl_pcie_attn", | |
306 | "pglue_b_pgl_read_blocked", | |
307 | "pglue_b_pgl_write_blocked", | |
308 | "pglue_b_vf_ilt_err", | |
309 | "pglue_b_rxobffexception_attn", | |
310 | }; | |
311 | #else | |
312 | #define pglue_b_int_attn_desc OSAL_NULL | |
313 | #endif | |
314 | ||
315 | static const u16 pglue_b_int0_bb_a0_attn_idx[23] = { | |
316 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
317 | 20, | |
318 | 21, 22, | |
319 | }; | |
320 | ||
321 | static struct attn_hw_reg pglue_b_int0_bb_a0 = { | |
322 | 0, 23, pglue_b_int0_bb_a0_attn_idx, 0x2a8180, 0x2a818c, 0x2a8188, | |
323 | 0x2a8184 | |
324 | }; | |
325 | ||
326 | static struct attn_hw_reg *pglue_b_int_bb_a0_regs[1] = { | |
327 | &pglue_b_int0_bb_a0, | |
328 | }; | |
329 | ||
330 | static const u16 pglue_b_int0_bb_b0_attn_idx[23] = { | |
331 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
332 | 20, | |
333 | 21, 22, | |
334 | }; | |
335 | ||
336 | static struct attn_hw_reg pglue_b_int0_bb_b0 = { | |
337 | 0, 23, pglue_b_int0_bb_b0_attn_idx, 0x2a8180, 0x2a818c, 0x2a8188, | |
338 | 0x2a8184 | |
339 | }; | |
340 | ||
341 | static struct attn_hw_reg *pglue_b_int_bb_b0_regs[1] = { | |
342 | &pglue_b_int0_bb_b0, | |
343 | }; | |
344 | ||
345 | static const u16 pglue_b_int0_k2_attn_idx[24] = { | |
346 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
347 | 20, | |
348 | 21, 22, 23, | |
349 | }; | |
350 | ||
351 | static struct attn_hw_reg pglue_b_int0_k2 = { | |
352 | 0, 24, pglue_b_int0_k2_attn_idx, 0x2a8180, 0x2a818c, 0x2a8188, 0x2a8184 | |
353 | }; | |
354 | ||
355 | static struct attn_hw_reg *pglue_b_int_k2_regs[1] = { | |
356 | &pglue_b_int0_k2, | |
357 | }; | |
358 | ||
359 | #ifdef ATTN_DESC | |
360 | static const char *pglue_b_prty_attn_desc[35] = { | |
361 | "pglue_b_datapath_registers", | |
362 | "pglue_b_mem027_i_mem_prty", | |
363 | "pglue_b_mem007_i_mem_prty", | |
364 | "pglue_b_mem009_i_mem_prty", | |
365 | "pglue_b_mem010_i_mem_prty", | |
366 | "pglue_b_mem008_i_mem_prty", | |
367 | "pglue_b_mem022_i_mem_prty", | |
368 | "pglue_b_mem023_i_mem_prty", | |
369 | "pglue_b_mem024_i_mem_prty", | |
370 | "pglue_b_mem025_i_mem_prty", | |
371 | "pglue_b_mem004_i_mem_prty", | |
372 | "pglue_b_mem005_i_mem_prty", | |
373 | "pglue_b_mem011_i_mem_prty", | |
374 | "pglue_b_mem016_i_mem_prty", | |
375 | "pglue_b_mem017_i_mem_prty", | |
376 | "pglue_b_mem012_i_mem_prty", | |
377 | "pglue_b_mem013_i_mem_prty", | |
378 | "pglue_b_mem014_i_mem_prty", | |
379 | "pglue_b_mem015_i_mem_prty", | |
380 | "pglue_b_mem018_i_mem_prty", | |
381 | "pglue_b_mem020_i_mem_prty", | |
382 | "pglue_b_mem021_i_mem_prty", | |
383 | "pglue_b_mem019_i_mem_prty", | |
384 | "pglue_b_mem026_i_mem_prty", | |
385 | "pglue_b_mem006_i_mem_prty", | |
386 | "pglue_b_mem003_i_mem_prty", | |
387 | "pglue_b_mem002_i_mem_prty_0", | |
388 | "pglue_b_mem002_i_mem_prty_1", | |
389 | "pglue_b_mem002_i_mem_prty_2", | |
390 | "pglue_b_mem002_i_mem_prty_3", | |
391 | "pglue_b_mem002_i_mem_prty_4", | |
392 | "pglue_b_mem002_i_mem_prty_5", | |
393 | "pglue_b_mem002_i_mem_prty_6", | |
394 | "pglue_b_mem002_i_mem_prty_7", | |
395 | "pglue_b_mem001_i_mem_prty", | |
396 | }; | |
397 | #else | |
398 | #define pglue_b_prty_attn_desc OSAL_NULL | |
399 | #endif | |
400 | ||
401 | static const u16 pglue_b_prty1_bb_a0_attn_idx[22] = { | |
402 | 2, 3, 4, 5, 10, 11, 12, 15, 16, 17, 18, 24, 25, 26, 27, 28, 29, 30, 31, | |
403 | 32, 33, 34, | |
404 | }; | |
405 | ||
406 | static struct attn_hw_reg pglue_b_prty1_bb_a0 = { | |
407 | 0, 22, pglue_b_prty1_bb_a0_attn_idx, 0x2a8200, 0x2a820c, 0x2a8208, | |
408 | 0x2a8204 | |
409 | }; | |
410 | ||
411 | static struct attn_hw_reg *pglue_b_prty_bb_a0_regs[1] = { | |
412 | &pglue_b_prty1_bb_a0, | |
413 | }; | |
414 | ||
415 | static const u16 pglue_b_prty0_bb_b0_attn_idx[1] = { | |
416 | 0, | |
417 | }; | |
418 | ||
419 | static struct attn_hw_reg pglue_b_prty0_bb_b0 = { | |
420 | 0, 1, pglue_b_prty0_bb_b0_attn_idx, 0x2a8190, 0x2a819c, 0x2a8198, | |
421 | 0x2a8194 | |
422 | }; | |
423 | ||
424 | static const u16 pglue_b_prty1_bb_b0_attn_idx[22] = { | |
425 | 2, 3, 4, 5, 10, 11, 12, 15, 16, 17, 18, 24, 25, 26, 27, 28, 29, 30, 31, | |
426 | 32, 33, 34, | |
427 | }; | |
428 | ||
429 | static struct attn_hw_reg pglue_b_prty1_bb_b0 = { | |
430 | 1, 22, pglue_b_prty1_bb_b0_attn_idx, 0x2a8200, 0x2a820c, 0x2a8208, | |
431 | 0x2a8204 | |
432 | }; | |
433 | ||
434 | static struct attn_hw_reg *pglue_b_prty_bb_b0_regs[2] = { | |
435 | &pglue_b_prty0_bb_b0, &pglue_b_prty1_bb_b0, | |
436 | }; | |
437 | ||
438 | static const u16 pglue_b_prty0_k2_attn_idx[1] = { | |
439 | 0, | |
440 | }; | |
441 | ||
442 | static struct attn_hw_reg pglue_b_prty0_k2 = { | |
443 | 0, 1, pglue_b_prty0_k2_attn_idx, 0x2a8190, 0x2a819c, 0x2a8198, 0x2a8194 | |
444 | }; | |
445 | ||
446 | static const u16 pglue_b_prty1_k2_attn_idx[31] = { | |
447 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, | |
448 | 21, | |
449 | 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
450 | }; | |
451 | ||
452 | static struct attn_hw_reg pglue_b_prty1_k2 = { | |
453 | 1, 31, pglue_b_prty1_k2_attn_idx, 0x2a8200, 0x2a820c, 0x2a8208, | |
454 | 0x2a8204 | |
455 | }; | |
456 | ||
457 | static const u16 pglue_b_prty2_k2_attn_idx[3] = { | |
458 | 32, 33, 34, | |
459 | }; | |
460 | ||
461 | static struct attn_hw_reg pglue_b_prty2_k2 = { | |
462 | 2, 3, pglue_b_prty2_k2_attn_idx, 0x2a8210, 0x2a821c, 0x2a8218, 0x2a8214 | |
463 | }; | |
464 | ||
465 | static struct attn_hw_reg *pglue_b_prty_k2_regs[3] = { | |
466 | &pglue_b_prty0_k2, &pglue_b_prty1_k2, &pglue_b_prty2_k2, | |
467 | }; | |
468 | ||
469 | #ifdef ATTN_DESC | |
470 | static const char *cnig_int_attn_desc[10] = { | |
471 | "cnig_address_error", | |
472 | "cnig_tx_illegal_sop_port0", | |
473 | "cnig_tx_illegal_sop_port1", | |
474 | "cnig_tx_illegal_sop_port2", | |
475 | "cnig_tx_illegal_sop_port3", | |
476 | "cnig_tdm_lane_0_bandwidth_exceed", | |
477 | "cnig_tdm_lane_1_bandwidth_exceed", | |
478 | "cnig_pmeg_intr", | |
479 | "cnig_pmfc_intr", | |
480 | "cnig_fifo_error", | |
481 | }; | |
482 | #else | |
483 | #define cnig_int_attn_desc OSAL_NULL | |
484 | #endif | |
485 | ||
486 | static const u16 cnig_int0_bb_a0_attn_idx[4] = { | |
487 | 0, 7, 8, 9, | |
488 | }; | |
489 | ||
490 | static struct attn_hw_reg cnig_int0_bb_a0 = { | |
491 | 0, 4, cnig_int0_bb_a0_attn_idx, 0x2182e8, 0x2182f4, 0x2182f0, 0x2182ec | |
492 | }; | |
493 | ||
494 | static struct attn_hw_reg *cnig_int_bb_a0_regs[1] = { | |
495 | &cnig_int0_bb_a0, | |
496 | }; | |
497 | ||
498 | static const u16 cnig_int0_bb_b0_attn_idx[6] = { | |
499 | 0, 1, 3, 7, 8, 9, | |
500 | }; | |
501 | ||
502 | static struct attn_hw_reg cnig_int0_bb_b0 = { | |
503 | 0, 6, cnig_int0_bb_b0_attn_idx, 0x2182e8, 0x2182f4, 0x2182f0, 0x2182ec | |
504 | }; | |
505 | ||
506 | static struct attn_hw_reg *cnig_int_bb_b0_regs[1] = { | |
507 | &cnig_int0_bb_b0, | |
508 | }; | |
509 | ||
510 | static const u16 cnig_int0_k2_attn_idx[7] = { | |
511 | 0, 1, 2, 3, 4, 5, 6, | |
512 | }; | |
513 | ||
514 | static struct attn_hw_reg cnig_int0_k2 = { | |
515 | 0, 7, cnig_int0_k2_attn_idx, 0x218218, 0x218224, 0x218220, 0x21821c | |
516 | }; | |
517 | ||
518 | static struct attn_hw_reg *cnig_int_k2_regs[1] = { | |
519 | &cnig_int0_k2, | |
520 | }; | |
521 | ||
522 | #ifdef ATTN_DESC | |
523 | static const char *cnig_prty_attn_desc[3] = { | |
524 | "cnig_unused_0", | |
525 | "cnig_datapath_tx", | |
526 | "cnig_datapath_rx", | |
527 | }; | |
528 | #else | |
529 | #define cnig_prty_attn_desc OSAL_NULL | |
530 | #endif | |
531 | ||
532 | static const u16 cnig_prty0_bb_b0_attn_idx[2] = { | |
533 | 1, 2, | |
534 | }; | |
535 | ||
536 | static struct attn_hw_reg cnig_prty0_bb_b0 = { | |
537 | 0, 2, cnig_prty0_bb_b0_attn_idx, 0x218348, 0x218354, 0x218350, 0x21834c | |
538 | }; | |
539 | ||
540 | static struct attn_hw_reg *cnig_prty_bb_b0_regs[1] = { | |
541 | &cnig_prty0_bb_b0, | |
542 | }; | |
543 | ||
544 | static const u16 cnig_prty0_k2_attn_idx[1] = { | |
545 | 1, | |
546 | }; | |
547 | ||
548 | static struct attn_hw_reg cnig_prty0_k2 = { | |
549 | 0, 1, cnig_prty0_k2_attn_idx, 0x21822c, 0x218238, 0x218234, 0x218230 | |
550 | }; | |
551 | ||
552 | static struct attn_hw_reg *cnig_prty_k2_regs[1] = { | |
553 | &cnig_prty0_k2, | |
554 | }; | |
555 | ||
556 | #ifdef ATTN_DESC | |
557 | static const char *cpmu_int_attn_desc[1] = { | |
558 | "cpmu_address_error", | |
559 | }; | |
560 | #else | |
561 | #define cpmu_int_attn_desc OSAL_NULL | |
562 | #endif | |
563 | ||
564 | static const u16 cpmu_int0_bb_a0_attn_idx[1] = { | |
565 | 0, | |
566 | }; | |
567 | ||
568 | static struct attn_hw_reg cpmu_int0_bb_a0 = { | |
569 | 0, 1, cpmu_int0_bb_a0_attn_idx, 0x303e0, 0x303ec, 0x303e8, 0x303e4 | |
570 | }; | |
571 | ||
572 | static struct attn_hw_reg *cpmu_int_bb_a0_regs[1] = { | |
573 | &cpmu_int0_bb_a0, | |
574 | }; | |
575 | ||
576 | static const u16 cpmu_int0_bb_b0_attn_idx[1] = { | |
577 | 0, | |
578 | }; | |
579 | ||
580 | static struct attn_hw_reg cpmu_int0_bb_b0 = { | |
581 | 0, 1, cpmu_int0_bb_b0_attn_idx, 0x303e0, 0x303ec, 0x303e8, 0x303e4 | |
582 | }; | |
583 | ||
584 | static struct attn_hw_reg *cpmu_int_bb_b0_regs[1] = { | |
585 | &cpmu_int0_bb_b0, | |
586 | }; | |
587 | ||
588 | static const u16 cpmu_int0_k2_attn_idx[1] = { | |
589 | 0, | |
590 | }; | |
591 | ||
592 | static struct attn_hw_reg cpmu_int0_k2 = { | |
593 | 0, 1, cpmu_int0_k2_attn_idx, 0x303e0, 0x303ec, 0x303e8, 0x303e4 | |
594 | }; | |
595 | ||
596 | static struct attn_hw_reg *cpmu_int_k2_regs[1] = { | |
597 | &cpmu_int0_k2, | |
598 | }; | |
599 | ||
600 | #ifdef ATTN_DESC | |
601 | static const char *ncsi_int_attn_desc[1] = { | |
602 | "ncsi_address_error", | |
603 | }; | |
604 | #else | |
605 | #define ncsi_int_attn_desc OSAL_NULL | |
606 | #endif | |
607 | ||
608 | static const u16 ncsi_int0_bb_a0_attn_idx[1] = { | |
609 | 0, | |
610 | }; | |
611 | ||
612 | static struct attn_hw_reg ncsi_int0_bb_a0 = { | |
613 | 0, 1, ncsi_int0_bb_a0_attn_idx, 0x404cc, 0x404d8, 0x404d4, 0x404d0 | |
614 | }; | |
615 | ||
616 | static struct attn_hw_reg *ncsi_int_bb_a0_regs[1] = { | |
617 | &ncsi_int0_bb_a0, | |
618 | }; | |
619 | ||
620 | static const u16 ncsi_int0_bb_b0_attn_idx[1] = { | |
621 | 0, | |
622 | }; | |
623 | ||
624 | static struct attn_hw_reg ncsi_int0_bb_b0 = { | |
625 | 0, 1, ncsi_int0_bb_b0_attn_idx, 0x404cc, 0x404d8, 0x404d4, 0x404d0 | |
626 | }; | |
627 | ||
628 | static struct attn_hw_reg *ncsi_int_bb_b0_regs[1] = { | |
629 | &ncsi_int0_bb_b0, | |
630 | }; | |
631 | ||
632 | static const u16 ncsi_int0_k2_attn_idx[1] = { | |
633 | 0, | |
634 | }; | |
635 | ||
636 | static struct attn_hw_reg ncsi_int0_k2 = { | |
637 | 0, 1, ncsi_int0_k2_attn_idx, 0x404cc, 0x404d8, 0x404d4, 0x404d0 | |
638 | }; | |
639 | ||
640 | static struct attn_hw_reg *ncsi_int_k2_regs[1] = { | |
641 | &ncsi_int0_k2, | |
642 | }; | |
643 | ||
644 | #ifdef ATTN_DESC | |
645 | static const char *ncsi_prty_attn_desc[1] = { | |
646 | "ncsi_mem002_i_mem_prty", | |
647 | }; | |
648 | #else | |
649 | #define ncsi_prty_attn_desc OSAL_NULL | |
650 | #endif | |
651 | ||
652 | static const u16 ncsi_prty1_bb_a0_attn_idx[1] = { | |
653 | 0, | |
654 | }; | |
655 | ||
656 | static struct attn_hw_reg ncsi_prty1_bb_a0 = { | |
657 | 0, 1, ncsi_prty1_bb_a0_attn_idx, 0x40000, 0x4000c, 0x40008, 0x40004 | |
658 | }; | |
659 | ||
660 | static struct attn_hw_reg *ncsi_prty_bb_a0_regs[1] = { | |
661 | &ncsi_prty1_bb_a0, | |
662 | }; | |
663 | ||
664 | static const u16 ncsi_prty1_bb_b0_attn_idx[1] = { | |
665 | 0, | |
666 | }; | |
667 | ||
668 | static struct attn_hw_reg ncsi_prty1_bb_b0 = { | |
669 | 0, 1, ncsi_prty1_bb_b0_attn_idx, 0x40000, 0x4000c, 0x40008, 0x40004 | |
670 | }; | |
671 | ||
672 | static struct attn_hw_reg *ncsi_prty_bb_b0_regs[1] = { | |
673 | &ncsi_prty1_bb_b0, | |
674 | }; | |
675 | ||
676 | static const u16 ncsi_prty1_k2_attn_idx[1] = { | |
677 | 0, | |
678 | }; | |
679 | ||
680 | static struct attn_hw_reg ncsi_prty1_k2 = { | |
681 | 0, 1, ncsi_prty1_k2_attn_idx, 0x40000, 0x4000c, 0x40008, 0x40004 | |
682 | }; | |
683 | ||
684 | static struct attn_hw_reg *ncsi_prty_k2_regs[1] = { | |
685 | &ncsi_prty1_k2, | |
686 | }; | |
687 | ||
688 | #ifdef ATTN_DESC | |
689 | static const char *opte_prty_attn_desc[12] = { | |
690 | "opte_mem009_i_mem_prty", | |
691 | "opte_mem010_i_mem_prty", | |
692 | "opte_mem005_i_mem_prty", | |
693 | "opte_mem006_i_mem_prty", | |
694 | "opte_mem007_i_mem_prty", | |
695 | "opte_mem008_i_mem_prty", | |
696 | "opte_mem001_i_mem_prty", | |
697 | "opte_mem002_i_mem_prty", | |
698 | "opte_mem003_i_mem_prty", | |
699 | "opte_mem004_i_mem_prty", | |
700 | "opte_mem011_i_mem_prty", | |
701 | "opte_datapath_parity_error", | |
702 | }; | |
703 | #else | |
704 | #define opte_prty_attn_desc OSAL_NULL | |
705 | #endif | |
706 | ||
707 | static const u16 opte_prty1_bb_a0_attn_idx[11] = { | |
708 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, | |
709 | }; | |
710 | ||
711 | static struct attn_hw_reg opte_prty1_bb_a0 = { | |
712 | 0, 11, opte_prty1_bb_a0_attn_idx, 0x53000, 0x5300c, 0x53008, 0x53004 | |
713 | }; | |
714 | ||
715 | static struct attn_hw_reg *opte_prty_bb_a0_regs[1] = { | |
716 | &opte_prty1_bb_a0, | |
717 | }; | |
718 | ||
719 | static const u16 opte_prty1_bb_b0_attn_idx[11] = { | |
720 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, | |
721 | }; | |
722 | ||
723 | static struct attn_hw_reg opte_prty1_bb_b0 = { | |
724 | 0, 11, opte_prty1_bb_b0_attn_idx, 0x53000, 0x5300c, 0x53008, 0x53004 | |
725 | }; | |
726 | ||
727 | static const u16 opte_prty0_bb_b0_attn_idx[1] = { | |
728 | 11, | |
729 | }; | |
730 | ||
731 | static struct attn_hw_reg opte_prty0_bb_b0 = { | |
732 | 1, 1, opte_prty0_bb_b0_attn_idx, 0x53208, 0x53214, 0x53210, 0x5320c | |
733 | }; | |
734 | ||
735 | static struct attn_hw_reg *opte_prty_bb_b0_regs[2] = { | |
736 | &opte_prty1_bb_b0, &opte_prty0_bb_b0, | |
737 | }; | |
738 | ||
739 | static const u16 opte_prty1_k2_attn_idx[11] = { | |
740 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, | |
741 | }; | |
742 | ||
743 | static struct attn_hw_reg opte_prty1_k2 = { | |
744 | 0, 11, opte_prty1_k2_attn_idx, 0x53000, 0x5300c, 0x53008, 0x53004 | |
745 | }; | |
746 | ||
747 | static const u16 opte_prty0_k2_attn_idx[1] = { | |
748 | 11, | |
749 | }; | |
750 | ||
751 | static struct attn_hw_reg opte_prty0_k2 = { | |
752 | 1, 1, opte_prty0_k2_attn_idx, 0x53208, 0x53214, 0x53210, 0x5320c | |
753 | }; | |
754 | ||
755 | static struct attn_hw_reg *opte_prty_k2_regs[2] = { | |
756 | &opte_prty1_k2, &opte_prty0_k2, | |
757 | }; | |
758 | ||
759 | #ifdef ATTN_DESC | |
760 | static const char *bmb_int_attn_desc[297] = { | |
761 | "bmb_address_error", | |
762 | "bmb_rc_pkt0_rls_error", | |
763 | "bmb_unused_0", | |
764 | "bmb_rc_pkt0_protocol_error", | |
765 | "bmb_rc_pkt1_rls_error", | |
766 | "bmb_unused_1", | |
767 | "bmb_rc_pkt1_protocol_error", | |
768 | "bmb_rc_pkt2_rls_error", | |
769 | "bmb_unused_2", | |
770 | "bmb_rc_pkt2_protocol_error", | |
771 | "bmb_rc_pkt3_rls_error", | |
772 | "bmb_unused_3", | |
773 | "bmb_rc_pkt3_protocol_error", | |
774 | "bmb_rc_sop_req_tc_port_error", | |
775 | "bmb_unused_4", | |
776 | "bmb_wc0_protocol_error", | |
777 | "bmb_wc1_protocol_error", | |
778 | "bmb_wc2_protocol_error", | |
779 | "bmb_wc3_protocol_error", | |
780 | "bmb_unused_5", | |
781 | "bmb_ll_blk_error", | |
782 | "bmb_unused_6", | |
783 | "bmb_mac0_fc_cnt_error", | |
784 | "bmb_ll_arb_calc_error", | |
785 | "bmb_wc0_inp_fifo_error", | |
786 | "bmb_wc0_sop_fifo_error", | |
787 | "bmb_wc0_len_fifo_error", | |
788 | "bmb_wc0_queue_fifo_error", | |
789 | "bmb_wc0_free_point_fifo_error", | |
790 | "bmb_wc0_next_point_fifo_error", | |
791 | "bmb_wc0_strt_fifo_error", | |
792 | "bmb_wc0_second_dscr_fifo_error", | |
793 | "bmb_wc0_pkt_avail_fifo_error", | |
794 | "bmb_wc0_cos_cnt_fifo_error", | |
795 | "bmb_wc0_notify_fifo_error", | |
796 | "bmb_wc0_ll_req_fifo_error", | |
797 | "bmb_wc0_ll_pa_cnt_error", | |
798 | "bmb_wc0_bb_pa_cnt_error", | |
799 | "bmb_wc1_inp_fifo_error", | |
800 | "bmb_wc1_sop_fifo_error", | |
801 | "bmb_wc1_queue_fifo_error", | |
802 | "bmb_wc1_free_point_fifo_error", | |
803 | "bmb_wc1_next_point_fifo_error", | |
804 | "bmb_wc1_strt_fifo_error", | |
805 | "bmb_wc1_second_dscr_fifo_error", | |
806 | "bmb_wc1_pkt_avail_fifo_error", | |
807 | "bmb_wc1_cos_cnt_fifo_error", | |
808 | "bmb_wc1_notify_fifo_error", | |
809 | "bmb_wc1_ll_req_fifo_error", | |
810 | "bmb_wc1_ll_pa_cnt_error", | |
811 | "bmb_wc1_bb_pa_cnt_error", | |
812 | "bmb_wc2_inp_fifo_error", | |
813 | "bmb_wc2_sop_fifo_error", | |
814 | "bmb_wc2_queue_fifo_error", | |
815 | "bmb_wc2_free_point_fifo_error", | |
816 | "bmb_wc2_next_point_fifo_error", | |
817 | "bmb_wc2_strt_fifo_error", | |
818 | "bmb_wc2_second_dscr_fifo_error", | |
819 | "bmb_wc2_pkt_avail_fifo_error", | |
820 | "bmb_wc2_cos_cnt_fifo_error", | |
821 | "bmb_wc2_notify_fifo_error", | |
822 | "bmb_wc2_ll_req_fifo_error", | |
823 | "bmb_wc2_ll_pa_cnt_error", | |
824 | "bmb_wc2_bb_pa_cnt_error", | |
825 | "bmb_wc3_inp_fifo_error", | |
826 | "bmb_wc3_sop_fifo_error", | |
827 | "bmb_wc3_queue_fifo_error", | |
828 | "bmb_wc3_free_point_fifo_error", | |
829 | "bmb_wc3_next_point_fifo_error", | |
830 | "bmb_wc3_strt_fifo_error", | |
831 | "bmb_wc3_second_dscr_fifo_error", | |
832 | "bmb_wc3_pkt_avail_fifo_error", | |
833 | "bmb_wc3_cos_cnt_fifo_error", | |
834 | "bmb_wc3_notify_fifo_error", | |
835 | "bmb_wc3_ll_req_fifo_error", | |
836 | "bmb_wc3_ll_pa_cnt_error", | |
837 | "bmb_wc3_bb_pa_cnt_error", | |
838 | "bmb_rc_pkt0_side_fifo_error", | |
839 | "bmb_rc_pkt0_req_fifo_error", | |
840 | "bmb_rc_pkt0_blk_fifo_error", | |
841 | "bmb_rc_pkt0_rls_left_fifo_error", | |
842 | "bmb_rc_pkt0_strt_ptr_fifo_error", | |
843 | "bmb_rc_pkt0_second_ptr_fifo_error", | |
844 | "bmb_rc_pkt0_rsp_fifo_error", | |
845 | "bmb_rc_pkt0_dscr_fifo_error", | |
846 | "bmb_rc_pkt1_side_fifo_error", | |
847 | "bmb_rc_pkt1_req_fifo_error", | |
848 | "bmb_rc_pkt1_blk_fifo_error", | |
849 | "bmb_rc_pkt1_rls_left_fifo_error", | |
850 | "bmb_rc_pkt1_strt_ptr_fifo_error", | |
851 | "bmb_rc_pkt1_second_ptr_fifo_error", | |
852 | "bmb_rc_pkt1_rsp_fifo_error", | |
853 | "bmb_rc_pkt1_dscr_fifo_error", | |
854 | "bmb_rc_pkt2_side_fifo_error", | |
855 | "bmb_rc_pkt2_req_fifo_error", | |
856 | "bmb_rc_pkt2_blk_fifo_error", | |
857 | "bmb_rc_pkt2_rls_left_fifo_error", | |
858 | "bmb_rc_pkt2_strt_ptr_fifo_error", | |
859 | "bmb_rc_pkt2_second_ptr_fifo_error", | |
860 | "bmb_rc_pkt2_rsp_fifo_error", | |
861 | "bmb_rc_pkt2_dscr_fifo_error", | |
862 | "bmb_rc_pkt3_side_fifo_error", | |
863 | "bmb_rc_pkt3_req_fifo_error", | |
864 | "bmb_rc_pkt3_blk_fifo_error", | |
865 | "bmb_rc_pkt3_rls_left_fifo_error", | |
866 | "bmb_rc_pkt3_strt_ptr_fifo_error", | |
867 | "bmb_rc_pkt3_second_ptr_fifo_error", | |
868 | "bmb_rc_pkt3_rsp_fifo_error", | |
869 | "bmb_rc_pkt3_dscr_fifo_error", | |
870 | "bmb_rc_sop_strt_fifo_error", | |
871 | "bmb_rc_sop_req_fifo_error", | |
872 | "bmb_rc_sop_dscr_fifo_error", | |
873 | "bmb_rc_sop_queue_fifo_error", | |
874 | "bmb_ll_arb_rls_fifo_error", | |
875 | "bmb_ll_arb_prefetch_fifo_error", | |
876 | "bmb_rc_pkt0_rls_fifo_error", | |
877 | "bmb_rc_pkt1_rls_fifo_error", | |
878 | "bmb_rc_pkt2_rls_fifo_error", | |
879 | "bmb_rc_pkt3_rls_fifo_error", | |
880 | "bmb_rc_pkt4_rls_fifo_error", | |
881 | "bmb_rc_pkt5_rls_fifo_error", | |
882 | "bmb_rc_pkt6_rls_fifo_error", | |
883 | "bmb_rc_pkt7_rls_fifo_error", | |
884 | "bmb_rc_pkt8_rls_fifo_error", | |
885 | "bmb_rc_pkt9_rls_fifo_error", | |
886 | "bmb_rc_pkt4_rls_error", | |
887 | "bmb_rc_pkt4_protocol_error", | |
888 | "bmb_rc_pkt4_side_fifo_error", | |
889 | "bmb_rc_pkt4_req_fifo_error", | |
890 | "bmb_rc_pkt4_blk_fifo_error", | |
891 | "bmb_rc_pkt4_rls_left_fifo_error", | |
892 | "bmb_rc_pkt4_strt_ptr_fifo_error", | |
893 | "bmb_rc_pkt4_second_ptr_fifo_error", | |
894 | "bmb_rc_pkt4_rsp_fifo_error", | |
895 | "bmb_rc_pkt4_dscr_fifo_error", | |
896 | "bmb_rc_pkt5_rls_error", | |
897 | "bmb_rc_pkt5_protocol_error", | |
898 | "bmb_rc_pkt5_side_fifo_error", | |
899 | "bmb_rc_pkt5_req_fifo_error", | |
900 | "bmb_rc_pkt5_blk_fifo_error", | |
901 | "bmb_rc_pkt5_rls_left_fifo_error", | |
902 | "bmb_rc_pkt5_strt_ptr_fifo_error", | |
903 | "bmb_rc_pkt5_second_ptr_fifo_error", | |
904 | "bmb_rc_pkt5_rsp_fifo_error", | |
905 | "bmb_rc_pkt5_dscr_fifo_error", | |
906 | "bmb_rc_pkt6_rls_error", | |
907 | "bmb_rc_pkt6_protocol_error", | |
908 | "bmb_rc_pkt6_side_fifo_error", | |
909 | "bmb_rc_pkt6_req_fifo_error", | |
910 | "bmb_rc_pkt6_blk_fifo_error", | |
911 | "bmb_rc_pkt6_rls_left_fifo_error", | |
912 | "bmb_rc_pkt6_strt_ptr_fifo_error", | |
913 | "bmb_rc_pkt6_second_ptr_fifo_error", | |
914 | "bmb_rc_pkt6_rsp_fifo_error", | |
915 | "bmb_rc_pkt6_dscr_fifo_error", | |
916 | "bmb_rc_pkt7_rls_error", | |
917 | "bmb_rc_pkt7_protocol_error", | |
918 | "bmb_rc_pkt7_side_fifo_error", | |
919 | "bmb_rc_pkt7_req_fifo_error", | |
920 | "bmb_rc_pkt7_blk_fifo_error", | |
921 | "bmb_rc_pkt7_rls_left_fifo_error", | |
922 | "bmb_rc_pkt7_strt_ptr_fifo_error", | |
923 | "bmb_rc_pkt7_second_ptr_fifo_error", | |
924 | "bmb_rc_pkt7_rsp_fifo_error", | |
925 | "bmb_packet_available_sync_fifo_push_error", | |
926 | "bmb_rc_pkt8_rls_error", | |
927 | "bmb_rc_pkt8_protocol_error", | |
928 | "bmb_rc_pkt8_side_fifo_error", | |
929 | "bmb_rc_pkt8_req_fifo_error", | |
930 | "bmb_rc_pkt8_blk_fifo_error", | |
931 | "bmb_rc_pkt8_rls_left_fifo_error", | |
932 | "bmb_rc_pkt8_strt_ptr_fifo_error", | |
933 | "bmb_rc_pkt8_second_ptr_fifo_error", | |
934 | "bmb_rc_pkt8_rsp_fifo_error", | |
935 | "bmb_rc_pkt8_dscr_fifo_error", | |
936 | "bmb_rc_pkt9_rls_error", | |
937 | "bmb_rc_pkt9_protocol_error", | |
938 | "bmb_rc_pkt9_side_fifo_error", | |
939 | "bmb_rc_pkt9_req_fifo_error", | |
940 | "bmb_rc_pkt9_blk_fifo_error", | |
941 | "bmb_rc_pkt9_rls_left_fifo_error", | |
942 | "bmb_rc_pkt9_strt_ptr_fifo_error", | |
943 | "bmb_rc_pkt9_second_ptr_fifo_error", | |
944 | "bmb_rc_pkt9_rsp_fifo_error", | |
945 | "bmb_rc_pkt9_dscr_fifo_error", | |
946 | "bmb_wc4_protocol_error", | |
947 | "bmb_wc5_protocol_error", | |
948 | "bmb_wc6_protocol_error", | |
949 | "bmb_wc7_protocol_error", | |
950 | "bmb_wc8_protocol_error", | |
951 | "bmb_wc9_protocol_error", | |
952 | "bmb_wc4_inp_fifo_error", | |
953 | "bmb_wc4_sop_fifo_error", | |
954 | "bmb_wc4_queue_fifo_error", | |
955 | "bmb_wc4_free_point_fifo_error", | |
956 | "bmb_wc4_next_point_fifo_error", | |
957 | "bmb_wc4_strt_fifo_error", | |
958 | "bmb_wc4_second_dscr_fifo_error", | |
959 | "bmb_wc4_pkt_avail_fifo_error", | |
960 | "bmb_wc4_cos_cnt_fifo_error", | |
961 | "bmb_wc4_notify_fifo_error", | |
962 | "bmb_wc4_ll_req_fifo_error", | |
963 | "bmb_wc4_ll_pa_cnt_error", | |
964 | "bmb_wc4_bb_pa_cnt_error", | |
965 | "bmb_wc5_inp_fifo_error", | |
966 | "bmb_wc5_sop_fifo_error", | |
967 | "bmb_wc5_queue_fifo_error", | |
968 | "bmb_wc5_free_point_fifo_error", | |
969 | "bmb_wc5_next_point_fifo_error", | |
970 | "bmb_wc5_strt_fifo_error", | |
971 | "bmb_wc5_second_dscr_fifo_error", | |
972 | "bmb_wc5_pkt_avail_fifo_error", | |
973 | "bmb_wc5_cos_cnt_fifo_error", | |
974 | "bmb_wc5_notify_fifo_error", | |
975 | "bmb_wc5_ll_req_fifo_error", | |
976 | "bmb_wc5_ll_pa_cnt_error", | |
977 | "bmb_wc5_bb_pa_cnt_error", | |
978 | "bmb_wc6_inp_fifo_error", | |
979 | "bmb_wc6_sop_fifo_error", | |
980 | "bmb_wc6_queue_fifo_error", | |
981 | "bmb_wc6_free_point_fifo_error", | |
982 | "bmb_wc6_next_point_fifo_error", | |
983 | "bmb_wc6_strt_fifo_error", | |
984 | "bmb_wc6_second_dscr_fifo_error", | |
985 | "bmb_wc6_pkt_avail_fifo_error", | |
986 | "bmb_wc6_cos_cnt_fifo_error", | |
987 | "bmb_wc6_notify_fifo_error", | |
988 | "bmb_wc6_ll_req_fifo_error", | |
989 | "bmb_wc6_ll_pa_cnt_error", | |
990 | "bmb_wc6_bb_pa_cnt_error", | |
991 | "bmb_wc7_inp_fifo_error", | |
992 | "bmb_wc7_sop_fifo_error", | |
993 | "bmb_wc7_queue_fifo_error", | |
994 | "bmb_wc7_free_point_fifo_error", | |
995 | "bmb_wc7_next_point_fifo_error", | |
996 | "bmb_wc7_strt_fifo_error", | |
997 | "bmb_wc7_second_dscr_fifo_error", | |
998 | "bmb_wc7_pkt_avail_fifo_error", | |
999 | "bmb_wc7_cos_cnt_fifo_error", | |
1000 | "bmb_wc7_notify_fifo_error", | |
1001 | "bmb_wc7_ll_req_fifo_error", | |
1002 | "bmb_wc7_ll_pa_cnt_error", | |
1003 | "bmb_wc7_bb_pa_cnt_error", | |
1004 | "bmb_wc8_inp_fifo_error", | |
1005 | "bmb_wc8_sop_fifo_error", | |
1006 | "bmb_wc8_queue_fifo_error", | |
1007 | "bmb_wc8_free_point_fifo_error", | |
1008 | "bmb_wc8_next_point_fifo_error", | |
1009 | "bmb_wc8_strt_fifo_error", | |
1010 | "bmb_wc8_second_dscr_fifo_error", | |
1011 | "bmb_wc8_pkt_avail_fifo_error", | |
1012 | "bmb_wc8_cos_cnt_fifo_error", | |
1013 | "bmb_wc8_notify_fifo_error", | |
1014 | "bmb_wc8_ll_req_fifo_error", | |
1015 | "bmb_wc8_ll_pa_cnt_error", | |
1016 | "bmb_wc8_bb_pa_cnt_error", | |
1017 | "bmb_wc9_inp_fifo_error", | |
1018 | "bmb_wc9_sop_fifo_error", | |
1019 | "bmb_wc9_queue_fifo_error", | |
1020 | "bmb_wc9_free_point_fifo_error", | |
1021 | "bmb_wc9_next_point_fifo_error", | |
1022 | "bmb_wc9_strt_fifo_error", | |
1023 | "bmb_wc9_second_dscr_fifo_error", | |
1024 | "bmb_wc9_pkt_avail_fifo_error", | |
1025 | "bmb_wc9_cos_cnt_fifo_error", | |
1026 | "bmb_wc9_notify_fifo_error", | |
1027 | "bmb_wc9_ll_req_fifo_error", | |
1028 | "bmb_wc9_ll_pa_cnt_error", | |
1029 | "bmb_wc9_bb_pa_cnt_error", | |
1030 | "bmb_rc9_sop_rc_out_sync_fifo_error", | |
1031 | "bmb_rc9_sop_out_sync_fifo_push_error", | |
1032 | "bmb_rc0_sop_pend_fifo_error", | |
1033 | "bmb_rc1_sop_pend_fifo_error", | |
1034 | "bmb_rc2_sop_pend_fifo_error", | |
1035 | "bmb_rc3_sop_pend_fifo_error", | |
1036 | "bmb_rc4_sop_pend_fifo_error", | |
1037 | "bmb_rc5_sop_pend_fifo_error", | |
1038 | "bmb_rc6_sop_pend_fifo_error", | |
1039 | "bmb_rc7_sop_pend_fifo_error", | |
1040 | "bmb_rc0_dscr_pend_fifo_error", | |
1041 | "bmb_rc1_dscr_pend_fifo_error", | |
1042 | "bmb_rc2_dscr_pend_fifo_error", | |
1043 | "bmb_rc3_dscr_pend_fifo_error", | |
1044 | "bmb_rc4_dscr_pend_fifo_error", | |
1045 | "bmb_rc5_dscr_pend_fifo_error", | |
1046 | "bmb_rc6_dscr_pend_fifo_error", | |
1047 | "bmb_rc7_dscr_pend_fifo_error", | |
1048 | "bmb_rc8_sop_inp_sync_fifo_push_error", | |
1049 | "bmb_rc9_sop_inp_sync_fifo_push_error", | |
1050 | "bmb_rc8_sop_out_sync_fifo_push_error", | |
1051 | "bmb_rc_gnt_pend_fifo_error", | |
1052 | "bmb_rc8_out_sync_fifo_push_error", | |
1053 | "bmb_rc9_out_sync_fifo_push_error", | |
1054 | "bmb_wc8_sync_fifo_push_error", | |
1055 | "bmb_wc9_sync_fifo_push_error", | |
1056 | "bmb_rc8_sop_rc_out_sync_fifo_error", | |
1057 | "bmb_rc_pkt7_dscr_fifo_error", | |
1058 | }; | |
1059 | #else | |
1060 | #define bmb_int_attn_desc OSAL_NULL | |
1061 | #endif | |
1062 | ||
1063 | static const u16 bmb_int0_bb_a0_attn_idx[16] = { | |
1064 | 0, 1, 3, 4, 6, 7, 9, 10, 12, 13, 15, 16, 17, 18, 20, 22, | |
1065 | }; | |
1066 | ||
1067 | static struct attn_hw_reg bmb_int0_bb_a0 = { | |
1068 | 0, 16, bmb_int0_bb_a0_attn_idx, 0x5400c0, 0x5400cc, 0x5400c8, 0x5400c4 | |
1069 | }; | |
1070 | ||
1071 | static const u16 bmb_int1_bb_a0_attn_idx[28] = { | |
1072 | 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, | |
1073 | 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, | |
1074 | }; | |
1075 | ||
1076 | static struct attn_hw_reg bmb_int1_bb_a0 = { | |
1077 | 1, 28, bmb_int1_bb_a0_attn_idx, 0x5400d8, 0x5400e4, 0x5400e0, 0x5400dc | |
1078 | }; | |
1079 | ||
1080 | static const u16 bmb_int2_bb_a0_attn_idx[26] = { | |
1081 | 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, | |
1082 | 69, 70, 71, 72, 73, 74, 75, 76, | |
1083 | }; | |
1084 | ||
1085 | static struct attn_hw_reg bmb_int2_bb_a0 = { | |
1086 | 2, 26, bmb_int2_bb_a0_attn_idx, 0x5400f0, 0x5400fc, 0x5400f8, 0x5400f4 | |
1087 | }; | |
1088 | ||
1089 | static const u16 bmb_int3_bb_a0_attn_idx[31] = { | |
1090 | 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, | |
1091 | 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, | |
1092 | }; | |
1093 | ||
1094 | static struct attn_hw_reg bmb_int3_bb_a0 = { | |
1095 | 3, 31, bmb_int3_bb_a0_attn_idx, 0x540108, 0x540114, 0x540110, 0x54010c | |
1096 | }; | |
1097 | ||
1098 | static const u16 bmb_int4_bb_a0_attn_idx[27] = { | |
1099 | 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, | |
1100 | 122, | |
1101 | 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, | |
1102 | }; | |
1103 | ||
1104 | static struct attn_hw_reg bmb_int4_bb_a0 = { | |
1105 | 4, 27, bmb_int4_bb_a0_attn_idx, 0x540120, 0x54012c, 0x540128, 0x540124 | |
1106 | }; | |
1107 | ||
1108 | static const u16 bmb_int5_bb_a0_attn_idx[29] = { | |
1109 | 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, | |
1110 | 149, | |
1111 | 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, | |
1112 | }; | |
1113 | ||
1114 | static struct attn_hw_reg bmb_int5_bb_a0 = { | |
1115 | 5, 29, bmb_int5_bb_a0_attn_idx, 0x540138, 0x540144, 0x540140, 0x54013c | |
1116 | }; | |
1117 | ||
1118 | static const u16 bmb_int6_bb_a0_attn_idx[30] = { | |
1119 | 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, | |
1120 | 178, | |
1121 | 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, | |
1122 | 193, | |
1123 | }; | |
1124 | ||
1125 | static struct attn_hw_reg bmb_int6_bb_a0 = { | |
1126 | 6, 30, bmb_int6_bb_a0_attn_idx, 0x540150, 0x54015c, 0x540158, 0x540154 | |
1127 | }; | |
1128 | ||
1129 | static const u16 bmb_int7_bb_a0_attn_idx[32] = { | |
1130 | 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, | |
1131 | 208, | |
1132 | 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, | |
1133 | 223, 224, | |
1134 | 225, | |
1135 | }; | |
1136 | ||
1137 | static struct attn_hw_reg bmb_int7_bb_a0 = { | |
1138 | 7, 32, bmb_int7_bb_a0_attn_idx, 0x540168, 0x540174, 0x540170, 0x54016c | |
1139 | }; | |
1140 | ||
1141 | static const u16 bmb_int8_bb_a0_attn_idx[32] = { | |
1142 | 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, | |
1143 | 240, | |
1144 | 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, | |
1145 | 255, 256, | |
1146 | 257, | |
1147 | }; | |
1148 | ||
1149 | static struct attn_hw_reg bmb_int8_bb_a0 = { | |
1150 | 8, 32, bmb_int8_bb_a0_attn_idx, 0x540184, 0x540190, 0x54018c, 0x540188 | |
1151 | }; | |
1152 | ||
1153 | static const u16 bmb_int9_bb_a0_attn_idx[32] = { | |
1154 | 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, | |
1155 | 272, | |
1156 | 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, | |
1157 | 287, 288, | |
1158 | 289, | |
1159 | }; | |
1160 | ||
1161 | static struct attn_hw_reg bmb_int9_bb_a0 = { | |
1162 | 9, 32, bmb_int9_bb_a0_attn_idx, 0x54019c, 0x5401a8, 0x5401a4, 0x5401a0 | |
1163 | }; | |
1164 | ||
1165 | static const u16 bmb_int10_bb_a0_attn_idx[3] = { | |
1166 | 290, 291, 292, | |
1167 | }; | |
1168 | ||
1169 | static struct attn_hw_reg bmb_int10_bb_a0 = { | |
1170 | 10, 3, bmb_int10_bb_a0_attn_idx, 0x5401b4, 0x5401c0, 0x5401bc, 0x5401b8 | |
1171 | }; | |
1172 | ||
1173 | static const u16 bmb_int11_bb_a0_attn_idx[4] = { | |
1174 | 293, 294, 295, 296, | |
1175 | }; | |
1176 | ||
1177 | static struct attn_hw_reg bmb_int11_bb_a0 = { | |
1178 | 11, 4, bmb_int11_bb_a0_attn_idx, 0x5401cc, 0x5401d8, 0x5401d4, 0x5401d0 | |
1179 | }; | |
1180 | ||
1181 | static struct attn_hw_reg *bmb_int_bb_a0_regs[12] = { | |
1182 | &bmb_int0_bb_a0, &bmb_int1_bb_a0, &bmb_int2_bb_a0, &bmb_int3_bb_a0, | |
1183 | &bmb_int4_bb_a0, &bmb_int5_bb_a0, &bmb_int6_bb_a0, &bmb_int7_bb_a0, | |
1184 | &bmb_int8_bb_a0, &bmb_int9_bb_a0, | |
1185 | &bmb_int10_bb_a0, &bmb_int11_bb_a0, | |
1186 | }; | |
1187 | ||
1188 | static const u16 bmb_int0_bb_b0_attn_idx[16] = { | |
1189 | 0, 1, 3, 4, 6, 7, 9, 10, 12, 13, 15, 16, 17, 18, 20, 22, | |
1190 | }; | |
1191 | ||
1192 | static struct attn_hw_reg bmb_int0_bb_b0 = { | |
1193 | 0, 16, bmb_int0_bb_b0_attn_idx, 0x5400c0, 0x5400cc, 0x5400c8, 0x5400c4 | |
1194 | }; | |
1195 | ||
1196 | static const u16 bmb_int1_bb_b0_attn_idx[28] = { | |
1197 | 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, | |
1198 | 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, | |
1199 | }; | |
1200 | ||
1201 | static struct attn_hw_reg bmb_int1_bb_b0 = { | |
1202 | 1, 28, bmb_int1_bb_b0_attn_idx, 0x5400d8, 0x5400e4, 0x5400e0, 0x5400dc | |
1203 | }; | |
1204 | ||
1205 | static const u16 bmb_int2_bb_b0_attn_idx[26] = { | |
1206 | 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, | |
1207 | 69, 70, 71, 72, 73, 74, 75, 76, | |
1208 | }; | |
1209 | ||
1210 | static struct attn_hw_reg bmb_int2_bb_b0 = { | |
1211 | 2, 26, bmb_int2_bb_b0_attn_idx, 0x5400f0, 0x5400fc, 0x5400f8, 0x5400f4 | |
1212 | }; | |
1213 | ||
1214 | static const u16 bmb_int3_bb_b0_attn_idx[31] = { | |
1215 | 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, | |
1216 | 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, | |
1217 | }; | |
1218 | ||
1219 | static struct attn_hw_reg bmb_int3_bb_b0 = { | |
1220 | 3, 31, bmb_int3_bb_b0_attn_idx, 0x540108, 0x540114, 0x540110, 0x54010c | |
1221 | }; | |
1222 | ||
1223 | static const u16 bmb_int4_bb_b0_attn_idx[27] = { | |
1224 | 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, | |
1225 | 122, | |
1226 | 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, | |
1227 | }; | |
1228 | ||
1229 | static struct attn_hw_reg bmb_int4_bb_b0 = { | |
1230 | 4, 27, bmb_int4_bb_b0_attn_idx, 0x540120, 0x54012c, 0x540128, 0x540124 | |
1231 | }; | |
1232 | ||
1233 | static const u16 bmb_int5_bb_b0_attn_idx[29] = { | |
1234 | 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, | |
1235 | 149, | |
1236 | 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, | |
1237 | }; | |
1238 | ||
1239 | static struct attn_hw_reg bmb_int5_bb_b0 = { | |
1240 | 5, 29, bmb_int5_bb_b0_attn_idx, 0x540138, 0x540144, 0x540140, 0x54013c | |
1241 | }; | |
1242 | ||
1243 | static const u16 bmb_int6_bb_b0_attn_idx[30] = { | |
1244 | 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, | |
1245 | 178, | |
1246 | 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, | |
1247 | 193, | |
1248 | }; | |
1249 | ||
1250 | static struct attn_hw_reg bmb_int6_bb_b0 = { | |
1251 | 6, 30, bmb_int6_bb_b0_attn_idx, 0x540150, 0x54015c, 0x540158, 0x540154 | |
1252 | }; | |
1253 | ||
1254 | static const u16 bmb_int7_bb_b0_attn_idx[32] = { | |
1255 | 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, | |
1256 | 208, | |
1257 | 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, | |
1258 | 223, 224, | |
1259 | 225, | |
1260 | }; | |
1261 | ||
1262 | static struct attn_hw_reg bmb_int7_bb_b0 = { | |
1263 | 7, 32, bmb_int7_bb_b0_attn_idx, 0x540168, 0x540174, 0x540170, 0x54016c | |
1264 | }; | |
1265 | ||
1266 | static const u16 bmb_int8_bb_b0_attn_idx[32] = { | |
1267 | 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, | |
1268 | 240, | |
1269 | 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, | |
1270 | 255, 256, | |
1271 | 257, | |
1272 | }; | |
1273 | ||
1274 | static struct attn_hw_reg bmb_int8_bb_b0 = { | |
1275 | 8, 32, bmb_int8_bb_b0_attn_idx, 0x540184, 0x540190, 0x54018c, 0x540188 | |
1276 | }; | |
1277 | ||
1278 | static const u16 bmb_int9_bb_b0_attn_idx[32] = { | |
1279 | 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, | |
1280 | 272, | |
1281 | 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, | |
1282 | 287, 288, | |
1283 | 289, | |
1284 | }; | |
1285 | ||
1286 | static struct attn_hw_reg bmb_int9_bb_b0 = { | |
1287 | 9, 32, bmb_int9_bb_b0_attn_idx, 0x54019c, 0x5401a8, 0x5401a4, 0x5401a0 | |
1288 | }; | |
1289 | ||
1290 | static const u16 bmb_int10_bb_b0_attn_idx[3] = { | |
1291 | 290, 291, 292, | |
1292 | }; | |
1293 | ||
1294 | static struct attn_hw_reg bmb_int10_bb_b0 = { | |
1295 | 10, 3, bmb_int10_bb_b0_attn_idx, 0x5401b4, 0x5401c0, 0x5401bc, 0x5401b8 | |
1296 | }; | |
1297 | ||
1298 | static const u16 bmb_int11_bb_b0_attn_idx[4] = { | |
1299 | 293, 294, 295, 296, | |
1300 | }; | |
1301 | ||
1302 | static struct attn_hw_reg bmb_int11_bb_b0 = { | |
1303 | 11, 4, bmb_int11_bb_b0_attn_idx, 0x5401cc, 0x5401d8, 0x5401d4, 0x5401d0 | |
1304 | }; | |
1305 | ||
1306 | static struct attn_hw_reg *bmb_int_bb_b0_regs[12] = { | |
1307 | &bmb_int0_bb_b0, &bmb_int1_bb_b0, &bmb_int2_bb_b0, &bmb_int3_bb_b0, | |
1308 | &bmb_int4_bb_b0, &bmb_int5_bb_b0, &bmb_int6_bb_b0, &bmb_int7_bb_b0, | |
1309 | &bmb_int8_bb_b0, &bmb_int9_bb_b0, | |
1310 | &bmb_int10_bb_b0, &bmb_int11_bb_b0, | |
1311 | }; | |
1312 | ||
1313 | static const u16 bmb_int0_k2_attn_idx[16] = { | |
1314 | 0, 1, 3, 4, 6, 7, 9, 10, 12, 13, 15, 16, 17, 18, 20, 22, | |
1315 | }; | |
1316 | ||
1317 | static struct attn_hw_reg bmb_int0_k2 = { | |
1318 | 0, 16, bmb_int0_k2_attn_idx, 0x5400c0, 0x5400cc, 0x5400c8, 0x5400c4 | |
1319 | }; | |
1320 | ||
1321 | static const u16 bmb_int1_k2_attn_idx[28] = { | |
1322 | 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, | |
1323 | 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, | |
1324 | }; | |
1325 | ||
1326 | static struct attn_hw_reg bmb_int1_k2 = { | |
1327 | 1, 28, bmb_int1_k2_attn_idx, 0x5400d8, 0x5400e4, 0x5400e0, 0x5400dc | |
1328 | }; | |
1329 | ||
1330 | static const u16 bmb_int2_k2_attn_idx[26] = { | |
1331 | 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, | |
1332 | 69, 70, 71, 72, 73, 74, 75, 76, | |
1333 | }; | |
1334 | ||
1335 | static struct attn_hw_reg bmb_int2_k2 = { | |
1336 | 2, 26, bmb_int2_k2_attn_idx, 0x5400f0, 0x5400fc, 0x5400f8, 0x5400f4 | |
1337 | }; | |
1338 | ||
1339 | static const u16 bmb_int3_k2_attn_idx[31] = { | |
1340 | 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, | |
1341 | 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, | |
1342 | }; | |
1343 | ||
1344 | static struct attn_hw_reg bmb_int3_k2 = { | |
1345 | 3, 31, bmb_int3_k2_attn_idx, 0x540108, 0x540114, 0x540110, 0x54010c | |
1346 | }; | |
1347 | ||
1348 | static const u16 bmb_int4_k2_attn_idx[27] = { | |
1349 | 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, | |
1350 | 122, | |
1351 | 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, | |
1352 | }; | |
1353 | ||
1354 | static struct attn_hw_reg bmb_int4_k2 = { | |
1355 | 4, 27, bmb_int4_k2_attn_idx, 0x540120, 0x54012c, 0x540128, 0x540124 | |
1356 | }; | |
1357 | ||
1358 | static const u16 bmb_int5_k2_attn_idx[29] = { | |
1359 | 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, | |
1360 | 149, | |
1361 | 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, | |
1362 | }; | |
1363 | ||
1364 | static struct attn_hw_reg bmb_int5_k2 = { | |
1365 | 5, 29, bmb_int5_k2_attn_idx, 0x540138, 0x540144, 0x540140, 0x54013c | |
1366 | }; | |
1367 | ||
1368 | static const u16 bmb_int6_k2_attn_idx[30] = { | |
1369 | 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, | |
1370 | 178, | |
1371 | 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, | |
1372 | 193, | |
1373 | }; | |
1374 | ||
1375 | static struct attn_hw_reg bmb_int6_k2 = { | |
1376 | 6, 30, bmb_int6_k2_attn_idx, 0x540150, 0x54015c, 0x540158, 0x540154 | |
1377 | }; | |
1378 | ||
1379 | static const u16 bmb_int7_k2_attn_idx[32] = { | |
1380 | 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, | |
1381 | 208, | |
1382 | 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, | |
1383 | 223, 224, | |
1384 | 225, | |
1385 | }; | |
1386 | ||
1387 | static struct attn_hw_reg bmb_int7_k2 = { | |
1388 | 7, 32, bmb_int7_k2_attn_idx, 0x540168, 0x540174, 0x540170, 0x54016c | |
1389 | }; | |
1390 | ||
1391 | static const u16 bmb_int8_k2_attn_idx[32] = { | |
1392 | 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, | |
1393 | 240, | |
1394 | 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, | |
1395 | 255, 256, | |
1396 | 257, | |
1397 | }; | |
1398 | ||
1399 | static struct attn_hw_reg bmb_int8_k2 = { | |
1400 | 8, 32, bmb_int8_k2_attn_idx, 0x540184, 0x540190, 0x54018c, 0x540188 | |
1401 | }; | |
1402 | ||
1403 | static const u16 bmb_int9_k2_attn_idx[32] = { | |
1404 | 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, | |
1405 | 272, | |
1406 | 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, | |
1407 | 287, 288, | |
1408 | 289, | |
1409 | }; | |
1410 | ||
1411 | static struct attn_hw_reg bmb_int9_k2 = { | |
1412 | 9, 32, bmb_int9_k2_attn_idx, 0x54019c, 0x5401a8, 0x5401a4, 0x5401a0 | |
1413 | }; | |
1414 | ||
1415 | static const u16 bmb_int10_k2_attn_idx[3] = { | |
1416 | 290, 291, 292, | |
1417 | }; | |
1418 | ||
1419 | static struct attn_hw_reg bmb_int10_k2 = { | |
1420 | 10, 3, bmb_int10_k2_attn_idx, 0x5401b4, 0x5401c0, 0x5401bc, 0x5401b8 | |
1421 | }; | |
1422 | ||
1423 | static const u16 bmb_int11_k2_attn_idx[4] = { | |
1424 | 293, 294, 295, 296, | |
1425 | }; | |
1426 | ||
1427 | static struct attn_hw_reg bmb_int11_k2 = { | |
1428 | 11, 4, bmb_int11_k2_attn_idx, 0x5401cc, 0x5401d8, 0x5401d4, 0x5401d0 | |
1429 | }; | |
1430 | ||
1431 | static struct attn_hw_reg *bmb_int_k2_regs[12] = { | |
1432 | &bmb_int0_k2, &bmb_int1_k2, &bmb_int2_k2, &bmb_int3_k2, &bmb_int4_k2, | |
1433 | &bmb_int5_k2, &bmb_int6_k2, &bmb_int7_k2, &bmb_int8_k2, &bmb_int9_k2, | |
1434 | &bmb_int10_k2, &bmb_int11_k2, | |
1435 | }; | |
1436 | ||
1437 | #ifdef ATTN_DESC | |
1438 | static const char *bmb_prty_attn_desc[61] = { | |
1439 | "bmb_ll_bank0_mem_prty", | |
1440 | "bmb_ll_bank1_mem_prty", | |
1441 | "bmb_ll_bank2_mem_prty", | |
1442 | "bmb_ll_bank3_mem_prty", | |
1443 | "bmb_datapath_registers", | |
1444 | "bmb_mem001_i_ecc_rf_int", | |
1445 | "bmb_mem008_i_ecc_rf_int", | |
1446 | "bmb_mem009_i_ecc_rf_int", | |
1447 | "bmb_mem010_i_ecc_rf_int", | |
1448 | "bmb_mem011_i_ecc_rf_int", | |
1449 | "bmb_mem012_i_ecc_rf_int", | |
1450 | "bmb_mem013_i_ecc_rf_int", | |
1451 | "bmb_mem014_i_ecc_rf_int", | |
1452 | "bmb_mem015_i_ecc_rf_int", | |
1453 | "bmb_mem016_i_ecc_rf_int", | |
1454 | "bmb_mem002_i_ecc_rf_int", | |
1455 | "bmb_mem003_i_ecc_rf_int", | |
1456 | "bmb_mem004_i_ecc_rf_int", | |
1457 | "bmb_mem005_i_ecc_rf_int", | |
1458 | "bmb_mem006_i_ecc_rf_int", | |
1459 | "bmb_mem007_i_ecc_rf_int", | |
1460 | "bmb_mem059_i_mem_prty", | |
1461 | "bmb_mem060_i_mem_prty", | |
1462 | "bmb_mem037_i_mem_prty", | |
1463 | "bmb_mem038_i_mem_prty", | |
1464 | "bmb_mem039_i_mem_prty", | |
1465 | "bmb_mem040_i_mem_prty", | |
1466 | "bmb_mem041_i_mem_prty", | |
1467 | "bmb_mem042_i_mem_prty", | |
1468 | "bmb_mem043_i_mem_prty", | |
1469 | "bmb_mem044_i_mem_prty", | |
1470 | "bmb_mem045_i_mem_prty", | |
1471 | "bmb_mem046_i_mem_prty", | |
1472 | "bmb_mem047_i_mem_prty", | |
1473 | "bmb_mem048_i_mem_prty", | |
1474 | "bmb_mem049_i_mem_prty", | |
1475 | "bmb_mem050_i_mem_prty", | |
1476 | "bmb_mem051_i_mem_prty", | |
1477 | "bmb_mem052_i_mem_prty", | |
1478 | "bmb_mem053_i_mem_prty", | |
1479 | "bmb_mem054_i_mem_prty", | |
1480 | "bmb_mem055_i_mem_prty", | |
1481 | "bmb_mem056_i_mem_prty", | |
1482 | "bmb_mem057_i_mem_prty", | |
1483 | "bmb_mem058_i_mem_prty", | |
1484 | "bmb_mem033_i_mem_prty", | |
1485 | "bmb_mem034_i_mem_prty", | |
1486 | "bmb_mem035_i_mem_prty", | |
1487 | "bmb_mem036_i_mem_prty", | |
1488 | "bmb_mem021_i_mem_prty", | |
1489 | "bmb_mem022_i_mem_prty", | |
1490 | "bmb_mem023_i_mem_prty", | |
1491 | "bmb_mem024_i_mem_prty", | |
1492 | "bmb_mem025_i_mem_prty", | |
1493 | "bmb_mem026_i_mem_prty", | |
1494 | "bmb_mem027_i_mem_prty", | |
1495 | "bmb_mem028_i_mem_prty", | |
1496 | "bmb_mem029_i_mem_prty", | |
1497 | "bmb_mem030_i_mem_prty", | |
1498 | "bmb_mem031_i_mem_prty", | |
1499 | "bmb_mem032_i_mem_prty", | |
1500 | }; | |
1501 | #else | |
1502 | #define bmb_prty_attn_desc OSAL_NULL | |
1503 | #endif | |
1504 | ||
1505 | static const u16 bmb_prty1_bb_a0_attn_idx[31] = { | |
1506 | 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, | |
1507 | 24, | |
1508 | 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, | |
1509 | }; | |
1510 | ||
1511 | static struct attn_hw_reg bmb_prty1_bb_a0 = { | |
1512 | 0, 31, bmb_prty1_bb_a0_attn_idx, 0x540400, 0x54040c, 0x540408, 0x540404 | |
1513 | }; | |
1514 | ||
1515 | static const u16 bmb_prty2_bb_a0_attn_idx[25] = { | |
1516 | 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, | |
1517 | 54, 55, 56, 57, 58, 59, 60, | |
1518 | }; | |
1519 | ||
1520 | static struct attn_hw_reg bmb_prty2_bb_a0 = { | |
1521 | 1, 25, bmb_prty2_bb_a0_attn_idx, 0x540410, 0x54041c, 0x540418, 0x540414 | |
1522 | }; | |
1523 | ||
1524 | static struct attn_hw_reg *bmb_prty_bb_a0_regs[2] = { | |
1525 | &bmb_prty1_bb_a0, &bmb_prty2_bb_a0, | |
1526 | }; | |
1527 | ||
1528 | static const u16 bmb_prty0_bb_b0_attn_idx[5] = { | |
1529 | 0, 1, 2, 3, 4, | |
1530 | }; | |
1531 | ||
1532 | static struct attn_hw_reg bmb_prty0_bb_b0 = { | |
1533 | 0, 5, bmb_prty0_bb_b0_attn_idx, 0x5401dc, 0x5401e8, 0x5401e4, 0x5401e0 | |
1534 | }; | |
1535 | ||
1536 | static const u16 bmb_prty1_bb_b0_attn_idx[31] = { | |
1537 | 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, | |
1538 | 24, | |
1539 | 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, | |
1540 | }; | |
1541 | ||
1542 | static struct attn_hw_reg bmb_prty1_bb_b0 = { | |
1543 | 1, 31, bmb_prty1_bb_b0_attn_idx, 0x540400, 0x54040c, 0x540408, 0x540404 | |
1544 | }; | |
1545 | ||
1546 | static const u16 bmb_prty2_bb_b0_attn_idx[15] = { | |
1547 | 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, | |
1548 | }; | |
1549 | ||
1550 | static struct attn_hw_reg bmb_prty2_bb_b0 = { | |
1551 | 2, 15, bmb_prty2_bb_b0_attn_idx, 0x540410, 0x54041c, 0x540418, 0x540414 | |
1552 | }; | |
1553 | ||
1554 | static struct attn_hw_reg *bmb_prty_bb_b0_regs[3] = { | |
1555 | &bmb_prty0_bb_b0, &bmb_prty1_bb_b0, &bmb_prty2_bb_b0, | |
1556 | }; | |
1557 | ||
1558 | static const u16 bmb_prty0_k2_attn_idx[5] = { | |
1559 | 0, 1, 2, 3, 4, | |
1560 | }; | |
1561 | ||
1562 | static struct attn_hw_reg bmb_prty0_k2 = { | |
1563 | 0, 5, bmb_prty0_k2_attn_idx, 0x5401dc, 0x5401e8, 0x5401e4, 0x5401e0 | |
1564 | }; | |
1565 | ||
1566 | static const u16 bmb_prty1_k2_attn_idx[31] = { | |
1567 | 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, | |
1568 | 24, | |
1569 | 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, | |
1570 | }; | |
1571 | ||
1572 | static struct attn_hw_reg bmb_prty1_k2 = { | |
1573 | 1, 31, bmb_prty1_k2_attn_idx, 0x540400, 0x54040c, 0x540408, 0x540404 | |
1574 | }; | |
1575 | ||
1576 | static const u16 bmb_prty2_k2_attn_idx[15] = { | |
1577 | 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, | |
1578 | }; | |
1579 | ||
1580 | static struct attn_hw_reg bmb_prty2_k2 = { | |
1581 | 2, 15, bmb_prty2_k2_attn_idx, 0x540410, 0x54041c, 0x540418, 0x540414 | |
1582 | }; | |
1583 | ||
1584 | static struct attn_hw_reg *bmb_prty_k2_regs[3] = { | |
1585 | &bmb_prty0_k2, &bmb_prty1_k2, &bmb_prty2_k2, | |
1586 | }; | |
1587 | ||
1588 | #ifdef ATTN_DESC | |
1589 | static const char *pcie_int_attn_desc[17] = { | |
1590 | "pcie_address_error", | |
1591 | "pcie_link_down_detect", | |
1592 | "pcie_link_up_detect", | |
1593 | "pcie_cfg_link_eq_req_int", | |
1594 | "pcie_pcie_bandwidth_change_detect", | |
1595 | "pcie_early_hot_reset_detect", | |
1596 | "pcie_hot_reset_detect", | |
1597 | "pcie_l1_entry_detect", | |
1598 | "pcie_l1_exit_detect", | |
1599 | "pcie_ltssm_state_match_detect", | |
1600 | "pcie_fc_timeout_detect", | |
1601 | "pcie_pme_turnoff_message_detect", | |
1602 | "pcie_cfg_send_cor_err", | |
1603 | "pcie_cfg_send_nf_err", | |
1604 | "pcie_cfg_send_f_err", | |
1605 | "pcie_qoverflow_detect", | |
1606 | "pcie_vdm_detect", | |
1607 | }; | |
1608 | #else | |
1609 | #define pcie_int_attn_desc OSAL_NULL | |
1610 | #endif | |
1611 | ||
1612 | static const u16 pcie_int0_k2_attn_idx[17] = { | |
1613 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, | |
1614 | }; | |
1615 | ||
1616 | static struct attn_hw_reg pcie_int0_k2 = { | |
1617 | 0, 17, pcie_int0_k2_attn_idx, 0x547a0, 0x547ac, 0x547a8, 0x547a4 | |
1618 | }; | |
1619 | ||
1620 | static struct attn_hw_reg *pcie_int_k2_regs[1] = { | |
1621 | &pcie_int0_k2, | |
1622 | }; | |
1623 | ||
1624 | #ifdef ATTN_DESC | |
1625 | static const char *pcie_prty_attn_desc[24] = { | |
1626 | "pcie_mem003_i_ecc_rf_int", | |
1627 | "pcie_mem004_i_ecc_rf_int", | |
1628 | "pcie_mem008_i_mem_prty", | |
1629 | "pcie_mem007_i_mem_prty", | |
1630 | "pcie_mem005_i_mem_prty", | |
1631 | "pcie_mem006_i_mem_prty", | |
1632 | "pcie_mem001_i_mem_prty", | |
1633 | "pcie_mem002_i_mem_prty", | |
1634 | "pcie_mem001_i_ecc_rf_int", | |
1635 | "pcie_mem005_i_ecc_rf_int", | |
1636 | "pcie_mem010_i_ecc_rf_int", | |
1637 | "pcie_mem009_i_ecc_rf_int", | |
1638 | "pcie_mem007_i_ecc_rf_int", | |
1639 | "pcie_mem004_i_mem_prty_0", | |
1640 | "pcie_mem004_i_mem_prty_1", | |
1641 | "pcie_mem004_i_mem_prty_2", | |
1642 | "pcie_mem004_i_mem_prty_3", | |
1643 | "pcie_mem011_i_mem_prty_1", | |
1644 | "pcie_mem011_i_mem_prty_2", | |
1645 | "pcie_mem012_i_mem_prty_1", | |
1646 | "pcie_mem012_i_mem_prty_2", | |
1647 | "pcie_app_parity_errs_0", | |
1648 | "pcie_app_parity_errs_1", | |
1649 | "pcie_app_parity_errs_2", | |
1650 | }; | |
1651 | #else | |
1652 | #define pcie_prty_attn_desc OSAL_NULL | |
1653 | #endif | |
1654 | ||
1655 | static const u16 pcie_prty1_bb_a0_attn_idx[17] = { | |
1656 | 0, 2, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, | |
1657 | }; | |
1658 | ||
1659 | static struct attn_hw_reg pcie_prty1_bb_a0 = { | |
1660 | 0, 17, pcie_prty1_bb_a0_attn_idx, 0x54000, 0x5400c, 0x54008, 0x54004 | |
1661 | }; | |
1662 | ||
1663 | static struct attn_hw_reg *pcie_prty_bb_a0_regs[1] = { | |
1664 | &pcie_prty1_bb_a0, | |
1665 | }; | |
1666 | ||
1667 | static const u16 pcie_prty1_bb_b0_attn_idx[17] = { | |
1668 | 0, 2, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, | |
1669 | }; | |
1670 | ||
1671 | static struct attn_hw_reg pcie_prty1_bb_b0 = { | |
1672 | 0, 17, pcie_prty1_bb_b0_attn_idx, 0x54000, 0x5400c, 0x54008, 0x54004 | |
1673 | }; | |
1674 | ||
1675 | static struct attn_hw_reg *pcie_prty_bb_b0_regs[1] = { | |
1676 | &pcie_prty1_bb_b0, | |
1677 | }; | |
1678 | ||
1679 | static const u16 pcie_prty1_k2_attn_idx[8] = { | |
1680 | 0, 1, 2, 3, 4, 5, 6, 7, | |
1681 | }; | |
1682 | ||
1683 | static struct attn_hw_reg pcie_prty1_k2 = { | |
1684 | 0, 8, pcie_prty1_k2_attn_idx, 0x54000, 0x5400c, 0x54008, 0x54004 | |
1685 | }; | |
1686 | ||
1687 | static const u16 pcie_prty0_k2_attn_idx[3] = { | |
1688 | 21, 22, 23, | |
1689 | }; | |
1690 | ||
1691 | static struct attn_hw_reg pcie_prty0_k2 = { | |
1692 | 1, 3, pcie_prty0_k2_attn_idx, 0x547b0, 0x547bc, 0x547b8, 0x547b4 | |
1693 | }; | |
1694 | ||
1695 | static struct attn_hw_reg *pcie_prty_k2_regs[2] = { | |
1696 | &pcie_prty1_k2, &pcie_prty0_k2, | |
1697 | }; | |
1698 | ||
1699 | #ifdef ATTN_DESC | |
1700 | static const char *mcp2_prty_attn_desc[13] = { | |
1701 | "mcp2_rom_parity", | |
1702 | "mcp2_mem001_i_ecc_rf_int", | |
1703 | "mcp2_mem006_i_ecc_0_rf_int", | |
1704 | "mcp2_mem006_i_ecc_1_rf_int", | |
1705 | "mcp2_mem006_i_ecc_2_rf_int", | |
1706 | "mcp2_mem006_i_ecc_3_rf_int", | |
1707 | "mcp2_mem007_i_ecc_rf_int", | |
1708 | "mcp2_mem004_i_mem_prty", | |
1709 | "mcp2_mem003_i_mem_prty", | |
1710 | "mcp2_mem002_i_mem_prty", | |
1711 | "mcp2_mem009_i_mem_prty", | |
1712 | "mcp2_mem008_i_mem_prty", | |
1713 | "mcp2_mem005_i_mem_prty", | |
1714 | }; | |
1715 | #else | |
1716 | #define mcp2_prty_attn_desc OSAL_NULL | |
1717 | #endif | |
1718 | ||
1719 | static const u16 mcp2_prty0_bb_a0_attn_idx[1] = { | |
1720 | 0, | |
1721 | }; | |
1722 | ||
1723 | static struct attn_hw_reg mcp2_prty0_bb_a0 = { | |
1724 | 0, 1, mcp2_prty0_bb_a0_attn_idx, 0x52040, 0x5204c, 0x52048, 0x52044 | |
1725 | }; | |
1726 | ||
1727 | static const u16 mcp2_prty1_bb_a0_attn_idx[12] = { | |
1728 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, | |
1729 | }; | |
1730 | ||
1731 | static struct attn_hw_reg mcp2_prty1_bb_a0 = { | |
1732 | 1, 12, mcp2_prty1_bb_a0_attn_idx, 0x52204, 0x52210, 0x5220c, 0x52208 | |
1733 | }; | |
1734 | ||
1735 | static struct attn_hw_reg *mcp2_prty_bb_a0_regs[2] = { | |
1736 | &mcp2_prty0_bb_a0, &mcp2_prty1_bb_a0, | |
1737 | }; | |
1738 | ||
1739 | static const u16 mcp2_prty0_bb_b0_attn_idx[1] = { | |
1740 | 0, | |
1741 | }; | |
1742 | ||
1743 | static struct attn_hw_reg mcp2_prty0_bb_b0 = { | |
1744 | 0, 1, mcp2_prty0_bb_b0_attn_idx, 0x52040, 0x5204c, 0x52048, 0x52044 | |
1745 | }; | |
1746 | ||
1747 | static const u16 mcp2_prty1_bb_b0_attn_idx[12] = { | |
1748 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, | |
1749 | }; | |
1750 | ||
1751 | static struct attn_hw_reg mcp2_prty1_bb_b0 = { | |
1752 | 1, 12, mcp2_prty1_bb_b0_attn_idx, 0x52204, 0x52210, 0x5220c, 0x52208 | |
1753 | }; | |
1754 | ||
1755 | static struct attn_hw_reg *mcp2_prty_bb_b0_regs[2] = { | |
1756 | &mcp2_prty0_bb_b0, &mcp2_prty1_bb_b0, | |
1757 | }; | |
1758 | ||
1759 | static const u16 mcp2_prty0_k2_attn_idx[1] = { | |
1760 | 0, | |
1761 | }; | |
1762 | ||
1763 | static struct attn_hw_reg mcp2_prty0_k2 = { | |
1764 | 0, 1, mcp2_prty0_k2_attn_idx, 0x52040, 0x5204c, 0x52048, 0x52044 | |
1765 | }; | |
1766 | ||
1767 | static const u16 mcp2_prty1_k2_attn_idx[12] = { | |
1768 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, | |
1769 | }; | |
1770 | ||
1771 | static struct attn_hw_reg mcp2_prty1_k2 = { | |
1772 | 1, 12, mcp2_prty1_k2_attn_idx, 0x52204, 0x52210, 0x5220c, 0x52208 | |
1773 | }; | |
1774 | ||
1775 | static struct attn_hw_reg *mcp2_prty_k2_regs[2] = { | |
1776 | &mcp2_prty0_k2, &mcp2_prty1_k2, | |
1777 | }; | |
1778 | ||
1779 | #ifdef ATTN_DESC | |
1780 | static const char *pswhst_int_attn_desc[18] = { | |
1781 | "pswhst_address_error", | |
1782 | "pswhst_hst_src_fifo1_err", | |
1783 | "pswhst_hst_src_fifo2_err", | |
1784 | "pswhst_hst_src_fifo3_err", | |
1785 | "pswhst_hst_src_fifo4_err", | |
1786 | "pswhst_hst_src_fifo5_err", | |
1787 | "pswhst_hst_hdr_sync_fifo_err", | |
1788 | "pswhst_hst_data_sync_fifo_err", | |
1789 | "pswhst_hst_cpl_sync_fifo_err", | |
1790 | "pswhst_hst_vf_disabled_access", | |
1791 | "pswhst_hst_permission_violation", | |
1792 | "pswhst_hst_incorrect_access", | |
1793 | "pswhst_hst_src_fifo6_err", | |
1794 | "pswhst_hst_src_fifo7_err", | |
1795 | "pswhst_hst_src_fifo8_err", | |
1796 | "pswhst_hst_src_fifo9_err", | |
1797 | "pswhst_hst_source_credit_violation", | |
1798 | "pswhst_hst_timeout", | |
1799 | }; | |
1800 | #else | |
1801 | #define pswhst_int_attn_desc OSAL_NULL | |
1802 | #endif | |
1803 | ||
1804 | static const u16 pswhst_int0_bb_a0_attn_idx[18] = { | |
1805 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, | |
1806 | }; | |
1807 | ||
1808 | static struct attn_hw_reg pswhst_int0_bb_a0 = { | |
1809 | 0, 18, pswhst_int0_bb_a0_attn_idx, 0x2a0180, 0x2a018c, 0x2a0188, | |
1810 | 0x2a0184 | |
1811 | }; | |
1812 | ||
1813 | static struct attn_hw_reg *pswhst_int_bb_a0_regs[1] = { | |
1814 | &pswhst_int0_bb_a0, | |
1815 | }; | |
1816 | ||
1817 | static const u16 pswhst_int0_bb_b0_attn_idx[18] = { | |
1818 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, | |
1819 | }; | |
1820 | ||
1821 | static struct attn_hw_reg pswhst_int0_bb_b0 = { | |
1822 | 0, 18, pswhst_int0_bb_b0_attn_idx, 0x2a0180, 0x2a018c, 0x2a0188, | |
1823 | 0x2a0184 | |
1824 | }; | |
1825 | ||
1826 | static struct attn_hw_reg *pswhst_int_bb_b0_regs[1] = { | |
1827 | &pswhst_int0_bb_b0, | |
1828 | }; | |
1829 | ||
1830 | static const u16 pswhst_int0_k2_attn_idx[18] = { | |
1831 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, | |
1832 | }; | |
1833 | ||
1834 | static struct attn_hw_reg pswhst_int0_k2 = { | |
1835 | 0, 18, pswhst_int0_k2_attn_idx, 0x2a0180, 0x2a018c, 0x2a0188, 0x2a0184 | |
1836 | }; | |
1837 | ||
1838 | static struct attn_hw_reg *pswhst_int_k2_regs[1] = { | |
1839 | &pswhst_int0_k2, | |
1840 | }; | |
1841 | ||
1842 | #ifdef ATTN_DESC | |
1843 | static const char *pswhst_prty_attn_desc[18] = { | |
1844 | "pswhst_datapath_registers", | |
1845 | "pswhst_mem006_i_mem_prty", | |
1846 | "pswhst_mem007_i_mem_prty", | |
1847 | "pswhst_mem005_i_mem_prty", | |
1848 | "pswhst_mem002_i_mem_prty", | |
1849 | "pswhst_mem003_i_mem_prty", | |
1850 | "pswhst_mem001_i_mem_prty", | |
1851 | "pswhst_mem008_i_mem_prty", | |
1852 | "pswhst_mem004_i_mem_prty", | |
1853 | "pswhst_mem009_i_mem_prty", | |
1854 | "pswhst_mem010_i_mem_prty", | |
1855 | "pswhst_mem016_i_mem_prty", | |
1856 | "pswhst_mem012_i_mem_prty", | |
1857 | "pswhst_mem013_i_mem_prty", | |
1858 | "pswhst_mem014_i_mem_prty", | |
1859 | "pswhst_mem015_i_mem_prty", | |
1860 | "pswhst_mem011_i_mem_prty", | |
1861 | "pswhst_mem017_i_mem_prty", | |
1862 | }; | |
1863 | #else | |
1864 | #define pswhst_prty_attn_desc OSAL_NULL | |
1865 | #endif | |
1866 | ||
1867 | static const u16 pswhst_prty1_bb_a0_attn_idx[17] = { | |
1868 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, | |
1869 | }; | |
1870 | ||
1871 | static struct attn_hw_reg pswhst_prty1_bb_a0 = { | |
1872 | 0, 17, pswhst_prty1_bb_a0_attn_idx, 0x2a0200, 0x2a020c, 0x2a0208, | |
1873 | 0x2a0204 | |
1874 | }; | |
1875 | ||
1876 | static struct attn_hw_reg *pswhst_prty_bb_a0_regs[1] = { | |
1877 | &pswhst_prty1_bb_a0, | |
1878 | }; | |
1879 | ||
1880 | static const u16 pswhst_prty0_bb_b0_attn_idx[1] = { | |
1881 | 0, | |
1882 | }; | |
1883 | ||
1884 | static struct attn_hw_reg pswhst_prty0_bb_b0 = { | |
1885 | 0, 1, pswhst_prty0_bb_b0_attn_idx, 0x2a0190, 0x2a019c, 0x2a0198, | |
1886 | 0x2a0194 | |
1887 | }; | |
1888 | ||
1889 | static const u16 pswhst_prty1_bb_b0_attn_idx[17] = { | |
1890 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, | |
1891 | }; | |
1892 | ||
1893 | static struct attn_hw_reg pswhst_prty1_bb_b0 = { | |
1894 | 1, 17, pswhst_prty1_bb_b0_attn_idx, 0x2a0200, 0x2a020c, 0x2a0208, | |
1895 | 0x2a0204 | |
1896 | }; | |
1897 | ||
1898 | static struct attn_hw_reg *pswhst_prty_bb_b0_regs[2] = { | |
1899 | &pswhst_prty0_bb_b0, &pswhst_prty1_bb_b0, | |
1900 | }; | |
1901 | ||
1902 | static const u16 pswhst_prty0_k2_attn_idx[1] = { | |
1903 | 0, | |
1904 | }; | |
1905 | ||
1906 | static struct attn_hw_reg pswhst_prty0_k2 = { | |
1907 | 0, 1, pswhst_prty0_k2_attn_idx, 0x2a0190, 0x2a019c, 0x2a0198, 0x2a0194 | |
1908 | }; | |
1909 | ||
1910 | static const u16 pswhst_prty1_k2_attn_idx[17] = { | |
1911 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, | |
1912 | }; | |
1913 | ||
1914 | static struct attn_hw_reg pswhst_prty1_k2 = { | |
1915 | 1, 17, pswhst_prty1_k2_attn_idx, 0x2a0200, 0x2a020c, 0x2a0208, 0x2a0204 | |
1916 | }; | |
1917 | ||
1918 | static struct attn_hw_reg *pswhst_prty_k2_regs[2] = { | |
1919 | &pswhst_prty0_k2, &pswhst_prty1_k2, | |
1920 | }; | |
1921 | ||
1922 | #ifdef ATTN_DESC | |
1923 | static const char *pswhst2_int_attn_desc[5] = { | |
1924 | "pswhst2_address_error", | |
1925 | "pswhst2_hst_header_fifo_err", | |
1926 | "pswhst2_hst_data_fifo_err", | |
1927 | "pswhst2_hst_cpl_fifo_err", | |
1928 | "pswhst2_hst_ireq_fifo_err", | |
1929 | }; | |
1930 | #else | |
1931 | #define pswhst2_int_attn_desc OSAL_NULL | |
1932 | #endif | |
1933 | ||
1934 | static const u16 pswhst2_int0_bb_a0_attn_idx[5] = { | |
1935 | 0, 1, 2, 3, 4, | |
1936 | }; | |
1937 | ||
1938 | static struct attn_hw_reg pswhst2_int0_bb_a0 = { | |
1939 | 0, 5, pswhst2_int0_bb_a0_attn_idx, 0x29e180, 0x29e18c, 0x29e188, | |
1940 | 0x29e184 | |
1941 | }; | |
1942 | ||
1943 | static struct attn_hw_reg *pswhst2_int_bb_a0_regs[1] = { | |
1944 | &pswhst2_int0_bb_a0, | |
1945 | }; | |
1946 | ||
1947 | static const u16 pswhst2_int0_bb_b0_attn_idx[5] = { | |
1948 | 0, 1, 2, 3, 4, | |
1949 | }; | |
1950 | ||
1951 | static struct attn_hw_reg pswhst2_int0_bb_b0 = { | |
1952 | 0, 5, pswhst2_int0_bb_b0_attn_idx, 0x29e180, 0x29e18c, 0x29e188, | |
1953 | 0x29e184 | |
1954 | }; | |
1955 | ||
1956 | static struct attn_hw_reg *pswhst2_int_bb_b0_regs[1] = { | |
1957 | &pswhst2_int0_bb_b0, | |
1958 | }; | |
1959 | ||
1960 | static const u16 pswhst2_int0_k2_attn_idx[5] = { | |
1961 | 0, 1, 2, 3, 4, | |
1962 | }; | |
1963 | ||
1964 | static struct attn_hw_reg pswhst2_int0_k2 = { | |
1965 | 0, 5, pswhst2_int0_k2_attn_idx, 0x29e180, 0x29e18c, 0x29e188, 0x29e184 | |
1966 | }; | |
1967 | ||
1968 | static struct attn_hw_reg *pswhst2_int_k2_regs[1] = { | |
1969 | &pswhst2_int0_k2, | |
1970 | }; | |
1971 | ||
1972 | #ifdef ATTN_DESC | |
1973 | static const char *pswhst2_prty_attn_desc[1] = { | |
1974 | "pswhst2_datapath_registers", | |
1975 | }; | |
1976 | #else | |
1977 | #define pswhst2_prty_attn_desc OSAL_NULL | |
1978 | #endif | |
1979 | ||
1980 | static const u16 pswhst2_prty0_bb_b0_attn_idx[1] = { | |
1981 | 0, | |
1982 | }; | |
1983 | ||
1984 | static struct attn_hw_reg pswhst2_prty0_bb_b0 = { | |
1985 | 0, 1, pswhst2_prty0_bb_b0_attn_idx, 0x29e190, 0x29e19c, 0x29e198, | |
1986 | 0x29e194 | |
1987 | }; | |
1988 | ||
1989 | static struct attn_hw_reg *pswhst2_prty_bb_b0_regs[1] = { | |
1990 | &pswhst2_prty0_bb_b0, | |
1991 | }; | |
1992 | ||
1993 | static const u16 pswhst2_prty0_k2_attn_idx[1] = { | |
1994 | 0, | |
1995 | }; | |
1996 | ||
1997 | static struct attn_hw_reg pswhst2_prty0_k2 = { | |
1998 | 0, 1, pswhst2_prty0_k2_attn_idx, 0x29e190, 0x29e19c, 0x29e198, 0x29e194 | |
1999 | }; | |
2000 | ||
2001 | static struct attn_hw_reg *pswhst2_prty_k2_regs[1] = { | |
2002 | &pswhst2_prty0_k2, | |
2003 | }; | |
2004 | ||
2005 | #ifdef ATTN_DESC | |
2006 | static const char *pswrd_int_attn_desc[3] = { | |
2007 | "pswrd_address_error", | |
2008 | "pswrd_pop_error", | |
2009 | "pswrd_pop_pbf_error", | |
2010 | }; | |
2011 | #else | |
2012 | #define pswrd_int_attn_desc OSAL_NULL | |
2013 | #endif | |
2014 | ||
2015 | static const u16 pswrd_int0_bb_a0_attn_idx[3] = { | |
2016 | 0, 1, 2, | |
2017 | }; | |
2018 | ||
2019 | static struct attn_hw_reg pswrd_int0_bb_a0 = { | |
2020 | 0, 3, pswrd_int0_bb_a0_attn_idx, 0x29c180, 0x29c18c, 0x29c188, 0x29c184 | |
2021 | }; | |
2022 | ||
2023 | static struct attn_hw_reg *pswrd_int_bb_a0_regs[1] = { | |
2024 | &pswrd_int0_bb_a0, | |
2025 | }; | |
2026 | ||
2027 | static const u16 pswrd_int0_bb_b0_attn_idx[3] = { | |
2028 | 0, 1, 2, | |
2029 | }; | |
2030 | ||
2031 | static struct attn_hw_reg pswrd_int0_bb_b0 = { | |
2032 | 0, 3, pswrd_int0_bb_b0_attn_idx, 0x29c180, 0x29c18c, 0x29c188, 0x29c184 | |
2033 | }; | |
2034 | ||
2035 | static struct attn_hw_reg *pswrd_int_bb_b0_regs[1] = { | |
2036 | &pswrd_int0_bb_b0, | |
2037 | }; | |
2038 | ||
2039 | static const u16 pswrd_int0_k2_attn_idx[3] = { | |
2040 | 0, 1, 2, | |
2041 | }; | |
2042 | ||
2043 | static struct attn_hw_reg pswrd_int0_k2 = { | |
2044 | 0, 3, pswrd_int0_k2_attn_idx, 0x29c180, 0x29c18c, 0x29c188, 0x29c184 | |
2045 | }; | |
2046 | ||
2047 | static struct attn_hw_reg *pswrd_int_k2_regs[1] = { | |
2048 | &pswrd_int0_k2, | |
2049 | }; | |
2050 | ||
2051 | #ifdef ATTN_DESC | |
2052 | static const char *pswrd_prty_attn_desc[1] = { | |
2053 | "pswrd_datapath_registers", | |
2054 | }; | |
2055 | #else | |
2056 | #define pswrd_prty_attn_desc OSAL_NULL | |
2057 | #endif | |
2058 | ||
2059 | static const u16 pswrd_prty0_bb_b0_attn_idx[1] = { | |
2060 | 0, | |
2061 | }; | |
2062 | ||
2063 | static struct attn_hw_reg pswrd_prty0_bb_b0 = { | |
2064 | 0, 1, pswrd_prty0_bb_b0_attn_idx, 0x29c190, 0x29c19c, 0x29c198, | |
2065 | 0x29c194 | |
2066 | }; | |
2067 | ||
2068 | static struct attn_hw_reg *pswrd_prty_bb_b0_regs[1] = { | |
2069 | &pswrd_prty0_bb_b0, | |
2070 | }; | |
2071 | ||
2072 | static const u16 pswrd_prty0_k2_attn_idx[1] = { | |
2073 | 0, | |
2074 | }; | |
2075 | ||
2076 | static struct attn_hw_reg pswrd_prty0_k2 = { | |
2077 | 0, 1, pswrd_prty0_k2_attn_idx, 0x29c190, 0x29c19c, 0x29c198, 0x29c194 | |
2078 | }; | |
2079 | ||
2080 | static struct attn_hw_reg *pswrd_prty_k2_regs[1] = { | |
2081 | &pswrd_prty0_k2, | |
2082 | }; | |
2083 | ||
2084 | #ifdef ATTN_DESC | |
2085 | static const char *pswrd2_int_attn_desc[5] = { | |
2086 | "pswrd2_address_error", | |
2087 | "pswrd2_sr_fifo_error", | |
2088 | "pswrd2_blk_fifo_error", | |
2089 | "pswrd2_push_error", | |
2090 | "pswrd2_push_pbf_error", | |
2091 | }; | |
2092 | #else | |
2093 | #define pswrd2_int_attn_desc OSAL_NULL | |
2094 | #endif | |
2095 | ||
2096 | static const u16 pswrd2_int0_bb_a0_attn_idx[5] = { | |
2097 | 0, 1, 2, 3, 4, | |
2098 | }; | |
2099 | ||
2100 | static struct attn_hw_reg pswrd2_int0_bb_a0 = { | |
2101 | 0, 5, pswrd2_int0_bb_a0_attn_idx, 0x29d180, 0x29d18c, 0x29d188, | |
2102 | 0x29d184 | |
2103 | }; | |
2104 | ||
2105 | static struct attn_hw_reg *pswrd2_int_bb_a0_regs[1] = { | |
2106 | &pswrd2_int0_bb_a0, | |
2107 | }; | |
2108 | ||
2109 | static const u16 pswrd2_int0_bb_b0_attn_idx[5] = { | |
2110 | 0, 1, 2, 3, 4, | |
2111 | }; | |
2112 | ||
2113 | static struct attn_hw_reg pswrd2_int0_bb_b0 = { | |
2114 | 0, 5, pswrd2_int0_bb_b0_attn_idx, 0x29d180, 0x29d18c, 0x29d188, | |
2115 | 0x29d184 | |
2116 | }; | |
2117 | ||
2118 | static struct attn_hw_reg *pswrd2_int_bb_b0_regs[1] = { | |
2119 | &pswrd2_int0_bb_b0, | |
2120 | }; | |
2121 | ||
2122 | static const u16 pswrd2_int0_k2_attn_idx[5] = { | |
2123 | 0, 1, 2, 3, 4, | |
2124 | }; | |
2125 | ||
2126 | static struct attn_hw_reg pswrd2_int0_k2 = { | |
2127 | 0, 5, pswrd2_int0_k2_attn_idx, 0x29d180, 0x29d18c, 0x29d188, 0x29d184 | |
2128 | }; | |
2129 | ||
2130 | static struct attn_hw_reg *pswrd2_int_k2_regs[1] = { | |
2131 | &pswrd2_int0_k2, | |
2132 | }; | |
2133 | ||
2134 | #ifdef ATTN_DESC | |
2135 | static const char *pswrd2_prty_attn_desc[36] = { | |
2136 | "pswrd2_datapath_registers", | |
2137 | "pswrd2_mem017_i_ecc_rf_int", | |
2138 | "pswrd2_mem018_i_ecc_rf_int", | |
2139 | "pswrd2_mem019_i_ecc_rf_int", | |
2140 | "pswrd2_mem020_i_ecc_rf_int", | |
2141 | "pswrd2_mem021_i_ecc_rf_int", | |
2142 | "pswrd2_mem022_i_ecc_rf_int", | |
2143 | "pswrd2_mem023_i_ecc_rf_int", | |
2144 | "pswrd2_mem024_i_ecc_rf_int", | |
2145 | "pswrd2_mem025_i_ecc_rf_int", | |
2146 | "pswrd2_mem015_i_ecc_rf_int", | |
2147 | "pswrd2_mem034_i_mem_prty", | |
2148 | "pswrd2_mem032_i_mem_prty", | |
2149 | "pswrd2_mem028_i_mem_prty", | |
2150 | "pswrd2_mem033_i_mem_prty", | |
2151 | "pswrd2_mem030_i_mem_prty", | |
2152 | "pswrd2_mem029_i_mem_prty", | |
2153 | "pswrd2_mem031_i_mem_prty", | |
2154 | "pswrd2_mem027_i_mem_prty", | |
2155 | "pswrd2_mem026_i_mem_prty", | |
2156 | "pswrd2_mem001_i_mem_prty", | |
2157 | "pswrd2_mem007_i_mem_prty", | |
2158 | "pswrd2_mem008_i_mem_prty", | |
2159 | "pswrd2_mem009_i_mem_prty", | |
2160 | "pswrd2_mem010_i_mem_prty", | |
2161 | "pswrd2_mem011_i_mem_prty", | |
2162 | "pswrd2_mem012_i_mem_prty", | |
2163 | "pswrd2_mem013_i_mem_prty", | |
2164 | "pswrd2_mem014_i_mem_prty", | |
2165 | "pswrd2_mem002_i_mem_prty", | |
2166 | "pswrd2_mem003_i_mem_prty", | |
2167 | "pswrd2_mem004_i_mem_prty", | |
2168 | "pswrd2_mem005_i_mem_prty", | |
2169 | "pswrd2_mem006_i_mem_prty", | |
2170 | "pswrd2_mem016_i_mem_prty", | |
2171 | "pswrd2_mem015_i_mem_prty", | |
2172 | }; | |
2173 | #else | |
2174 | #define pswrd2_prty_attn_desc OSAL_NULL | |
2175 | #endif | |
2176 | ||
2177 | static const u16 pswrd2_prty1_bb_a0_attn_idx[31] = { | |
2178 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, | |
2179 | 22, | |
2180 | 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, | |
2181 | }; | |
2182 | ||
2183 | static struct attn_hw_reg pswrd2_prty1_bb_a0 = { | |
2184 | 0, 31, pswrd2_prty1_bb_a0_attn_idx, 0x29d200, 0x29d20c, 0x29d208, | |
2185 | 0x29d204 | |
2186 | }; | |
2187 | ||
2188 | static const u16 pswrd2_prty2_bb_a0_attn_idx[3] = { | |
2189 | 33, 34, 35, | |
2190 | }; | |
2191 | ||
2192 | static struct attn_hw_reg pswrd2_prty2_bb_a0 = { | |
2193 | 1, 3, pswrd2_prty2_bb_a0_attn_idx, 0x29d210, 0x29d21c, 0x29d218, | |
2194 | 0x29d214 | |
2195 | }; | |
2196 | ||
2197 | static struct attn_hw_reg *pswrd2_prty_bb_a0_regs[2] = { | |
2198 | &pswrd2_prty1_bb_a0, &pswrd2_prty2_bb_a0, | |
2199 | }; | |
2200 | ||
2201 | static const u16 pswrd2_prty0_bb_b0_attn_idx[1] = { | |
2202 | 0, | |
2203 | }; | |
2204 | ||
2205 | static struct attn_hw_reg pswrd2_prty0_bb_b0 = { | |
2206 | 0, 1, pswrd2_prty0_bb_b0_attn_idx, 0x29d190, 0x29d19c, 0x29d198, | |
2207 | 0x29d194 | |
2208 | }; | |
2209 | ||
2210 | static const u16 pswrd2_prty1_bb_b0_attn_idx[31] = { | |
2211 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, | |
2212 | 21, | |
2213 | 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
2214 | }; | |
2215 | ||
2216 | static struct attn_hw_reg pswrd2_prty1_bb_b0 = { | |
2217 | 1, 31, pswrd2_prty1_bb_b0_attn_idx, 0x29d200, 0x29d20c, 0x29d208, | |
2218 | 0x29d204 | |
2219 | }; | |
2220 | ||
2221 | static const u16 pswrd2_prty2_bb_b0_attn_idx[3] = { | |
2222 | 32, 33, 34, | |
2223 | }; | |
2224 | ||
2225 | static struct attn_hw_reg pswrd2_prty2_bb_b0 = { | |
2226 | 2, 3, pswrd2_prty2_bb_b0_attn_idx, 0x29d210, 0x29d21c, 0x29d218, | |
2227 | 0x29d214 | |
2228 | }; | |
2229 | ||
2230 | static struct attn_hw_reg *pswrd2_prty_bb_b0_regs[3] = { | |
2231 | &pswrd2_prty0_bb_b0, &pswrd2_prty1_bb_b0, &pswrd2_prty2_bb_b0, | |
2232 | }; | |
2233 | ||
2234 | static const u16 pswrd2_prty0_k2_attn_idx[1] = { | |
2235 | 0, | |
2236 | }; | |
2237 | ||
2238 | static struct attn_hw_reg pswrd2_prty0_k2 = { | |
2239 | 0, 1, pswrd2_prty0_k2_attn_idx, 0x29d190, 0x29d19c, 0x29d198, 0x29d194 | |
2240 | }; | |
2241 | ||
2242 | static const u16 pswrd2_prty1_k2_attn_idx[31] = { | |
2243 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, | |
2244 | 21, | |
2245 | 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
2246 | }; | |
2247 | ||
2248 | static struct attn_hw_reg pswrd2_prty1_k2 = { | |
2249 | 1, 31, pswrd2_prty1_k2_attn_idx, 0x29d200, 0x29d20c, 0x29d208, 0x29d204 | |
2250 | }; | |
2251 | ||
2252 | static const u16 pswrd2_prty2_k2_attn_idx[3] = { | |
2253 | 32, 33, 34, | |
2254 | }; | |
2255 | ||
2256 | static struct attn_hw_reg pswrd2_prty2_k2 = { | |
2257 | 2, 3, pswrd2_prty2_k2_attn_idx, 0x29d210, 0x29d21c, 0x29d218, 0x29d214 | |
2258 | }; | |
2259 | ||
2260 | static struct attn_hw_reg *pswrd2_prty_k2_regs[3] = { | |
2261 | &pswrd2_prty0_k2, &pswrd2_prty1_k2, &pswrd2_prty2_k2, | |
2262 | }; | |
2263 | ||
2264 | #ifdef ATTN_DESC | |
2265 | static const char *pswwr_int_attn_desc[16] = { | |
2266 | "pswwr_address_error", | |
2267 | "pswwr_src_fifo_overflow", | |
2268 | "pswwr_qm_fifo_overflow", | |
2269 | "pswwr_tm_fifo_overflow", | |
2270 | "pswwr_usdm_fifo_overflow", | |
2271 | "pswwr_usdmdp_fifo_overflow", | |
2272 | "pswwr_xsdm_fifo_overflow", | |
2273 | "pswwr_tsdm_fifo_overflow", | |
2274 | "pswwr_cduwr_fifo_overflow", | |
2275 | "pswwr_dbg_fifo_overflow", | |
2276 | "pswwr_dmae_fifo_overflow", | |
2277 | "pswwr_hc_fifo_overflow", | |
2278 | "pswwr_msdm_fifo_overflow", | |
2279 | "pswwr_ysdm_fifo_overflow", | |
2280 | "pswwr_psdm_fifo_overflow", | |
2281 | "pswwr_m2p_fifo_overflow", | |
2282 | }; | |
2283 | #else | |
2284 | #define pswwr_int_attn_desc OSAL_NULL | |
2285 | #endif | |
2286 | ||
2287 | static const u16 pswwr_int0_bb_a0_attn_idx[16] = { | |
2288 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, | |
2289 | }; | |
2290 | ||
2291 | static struct attn_hw_reg pswwr_int0_bb_a0 = { | |
2292 | 0, 16, pswwr_int0_bb_a0_attn_idx, 0x29a180, 0x29a18c, 0x29a188, | |
2293 | 0x29a184 | |
2294 | }; | |
2295 | ||
2296 | static struct attn_hw_reg *pswwr_int_bb_a0_regs[1] = { | |
2297 | &pswwr_int0_bb_a0, | |
2298 | }; | |
2299 | ||
2300 | static const u16 pswwr_int0_bb_b0_attn_idx[16] = { | |
2301 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, | |
2302 | }; | |
2303 | ||
2304 | static struct attn_hw_reg pswwr_int0_bb_b0 = { | |
2305 | 0, 16, pswwr_int0_bb_b0_attn_idx, 0x29a180, 0x29a18c, 0x29a188, | |
2306 | 0x29a184 | |
2307 | }; | |
2308 | ||
2309 | static struct attn_hw_reg *pswwr_int_bb_b0_regs[1] = { | |
2310 | &pswwr_int0_bb_b0, | |
2311 | }; | |
2312 | ||
2313 | static const u16 pswwr_int0_k2_attn_idx[16] = { | |
2314 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, | |
2315 | }; | |
2316 | ||
2317 | static struct attn_hw_reg pswwr_int0_k2 = { | |
2318 | 0, 16, pswwr_int0_k2_attn_idx, 0x29a180, 0x29a18c, 0x29a188, 0x29a184 | |
2319 | }; | |
2320 | ||
2321 | static struct attn_hw_reg *pswwr_int_k2_regs[1] = { | |
2322 | &pswwr_int0_k2, | |
2323 | }; | |
2324 | ||
2325 | #ifdef ATTN_DESC | |
2326 | static const char *pswwr_prty_attn_desc[1] = { | |
2327 | "pswwr_datapath_registers", | |
2328 | }; | |
2329 | #else | |
2330 | #define pswwr_prty_attn_desc OSAL_NULL | |
2331 | #endif | |
2332 | ||
2333 | static const u16 pswwr_prty0_bb_b0_attn_idx[1] = { | |
2334 | 0, | |
2335 | }; | |
2336 | ||
2337 | static struct attn_hw_reg pswwr_prty0_bb_b0 = { | |
2338 | 0, 1, pswwr_prty0_bb_b0_attn_idx, 0x29a190, 0x29a19c, 0x29a198, | |
2339 | 0x29a194 | |
2340 | }; | |
2341 | ||
2342 | static struct attn_hw_reg *pswwr_prty_bb_b0_regs[1] = { | |
2343 | &pswwr_prty0_bb_b0, | |
2344 | }; | |
2345 | ||
2346 | static const u16 pswwr_prty0_k2_attn_idx[1] = { | |
2347 | 0, | |
2348 | }; | |
2349 | ||
2350 | static struct attn_hw_reg pswwr_prty0_k2 = { | |
2351 | 0, 1, pswwr_prty0_k2_attn_idx, 0x29a190, 0x29a19c, 0x29a198, 0x29a194 | |
2352 | }; | |
2353 | ||
2354 | static struct attn_hw_reg *pswwr_prty_k2_regs[1] = { | |
2355 | &pswwr_prty0_k2, | |
2356 | }; | |
2357 | ||
2358 | #ifdef ATTN_DESC | |
2359 | static const char *pswwr2_int_attn_desc[19] = { | |
2360 | "pswwr2_address_error", | |
2361 | "pswwr2_pglue_eop_error", | |
2362 | "pswwr2_pglue_lsr_error", | |
2363 | "pswwr2_tm_underflow", | |
2364 | "pswwr2_qm_underflow", | |
2365 | "pswwr2_src_underflow", | |
2366 | "pswwr2_usdm_underflow", | |
2367 | "pswwr2_tsdm_underflow", | |
2368 | "pswwr2_xsdm_underflow", | |
2369 | "pswwr2_usdmdp_underflow", | |
2370 | "pswwr2_cdu_underflow", | |
2371 | "pswwr2_dbg_underflow", | |
2372 | "pswwr2_dmae_underflow", | |
2373 | "pswwr2_hc_underflow", | |
2374 | "pswwr2_msdm_underflow", | |
2375 | "pswwr2_ysdm_underflow", | |
2376 | "pswwr2_psdm_underflow", | |
2377 | "pswwr2_m2p_underflow", | |
2378 | "pswwr2_pglue_eop_error_in_line", | |
2379 | }; | |
2380 | #else | |
2381 | #define pswwr2_int_attn_desc OSAL_NULL | |
2382 | #endif | |
2383 | ||
2384 | static const u16 pswwr2_int0_bb_a0_attn_idx[19] = { | |
2385 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, | |
2386 | }; | |
2387 | ||
2388 | static struct attn_hw_reg pswwr2_int0_bb_a0 = { | |
2389 | 0, 19, pswwr2_int0_bb_a0_attn_idx, 0x29b180, 0x29b18c, 0x29b188, | |
2390 | 0x29b184 | |
2391 | }; | |
2392 | ||
2393 | static struct attn_hw_reg *pswwr2_int_bb_a0_regs[1] = { | |
2394 | &pswwr2_int0_bb_a0, | |
2395 | }; | |
2396 | ||
2397 | static const u16 pswwr2_int0_bb_b0_attn_idx[19] = { | |
2398 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, | |
2399 | }; | |
2400 | ||
2401 | static struct attn_hw_reg pswwr2_int0_bb_b0 = { | |
2402 | 0, 19, pswwr2_int0_bb_b0_attn_idx, 0x29b180, 0x29b18c, 0x29b188, | |
2403 | 0x29b184 | |
2404 | }; | |
2405 | ||
2406 | static struct attn_hw_reg *pswwr2_int_bb_b0_regs[1] = { | |
2407 | &pswwr2_int0_bb_b0, | |
2408 | }; | |
2409 | ||
2410 | static const u16 pswwr2_int0_k2_attn_idx[19] = { | |
2411 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, | |
2412 | }; | |
2413 | ||
2414 | static struct attn_hw_reg pswwr2_int0_k2 = { | |
2415 | 0, 19, pswwr2_int0_k2_attn_idx, 0x29b180, 0x29b18c, 0x29b188, 0x29b184 | |
2416 | }; | |
2417 | ||
2418 | static struct attn_hw_reg *pswwr2_int_k2_regs[1] = { | |
2419 | &pswwr2_int0_k2, | |
2420 | }; | |
2421 | ||
2422 | #ifdef ATTN_DESC | |
2423 | static const char *pswwr2_prty_attn_desc[114] = { | |
2424 | "pswwr2_datapath_registers", | |
2425 | "pswwr2_mem008_i_ecc_rf_int", | |
2426 | "pswwr2_mem001_i_mem_prty", | |
2427 | "pswwr2_mem014_i_mem_prty_0", | |
2428 | "pswwr2_mem014_i_mem_prty_1", | |
2429 | "pswwr2_mem014_i_mem_prty_2", | |
2430 | "pswwr2_mem014_i_mem_prty_3", | |
2431 | "pswwr2_mem014_i_mem_prty_4", | |
2432 | "pswwr2_mem014_i_mem_prty_5", | |
2433 | "pswwr2_mem014_i_mem_prty_6", | |
2434 | "pswwr2_mem014_i_mem_prty_7", | |
2435 | "pswwr2_mem014_i_mem_prty_8", | |
2436 | "pswwr2_mem016_i_mem_prty_0", | |
2437 | "pswwr2_mem016_i_mem_prty_1", | |
2438 | "pswwr2_mem016_i_mem_prty_2", | |
2439 | "pswwr2_mem016_i_mem_prty_3", | |
2440 | "pswwr2_mem016_i_mem_prty_4", | |
2441 | "pswwr2_mem016_i_mem_prty_5", | |
2442 | "pswwr2_mem016_i_mem_prty_6", | |
2443 | "pswwr2_mem016_i_mem_prty_7", | |
2444 | "pswwr2_mem016_i_mem_prty_8", | |
2445 | "pswwr2_mem007_i_mem_prty_0", | |
2446 | "pswwr2_mem007_i_mem_prty_1", | |
2447 | "pswwr2_mem007_i_mem_prty_2", | |
2448 | "pswwr2_mem007_i_mem_prty_3", | |
2449 | "pswwr2_mem007_i_mem_prty_4", | |
2450 | "pswwr2_mem007_i_mem_prty_5", | |
2451 | "pswwr2_mem007_i_mem_prty_6", | |
2452 | "pswwr2_mem007_i_mem_prty_7", | |
2453 | "pswwr2_mem007_i_mem_prty_8", | |
2454 | "pswwr2_mem017_i_mem_prty_0", | |
2455 | "pswwr2_mem017_i_mem_prty_1", | |
2456 | "pswwr2_mem017_i_mem_prty_2", | |
2457 | "pswwr2_mem017_i_mem_prty_3", | |
2458 | "pswwr2_mem017_i_mem_prty_4", | |
2459 | "pswwr2_mem017_i_mem_prty_5", | |
2460 | "pswwr2_mem017_i_mem_prty_6", | |
2461 | "pswwr2_mem017_i_mem_prty_7", | |
2462 | "pswwr2_mem017_i_mem_prty_8", | |
2463 | "pswwr2_mem009_i_mem_prty_0", | |
2464 | "pswwr2_mem009_i_mem_prty_1", | |
2465 | "pswwr2_mem009_i_mem_prty_2", | |
2466 | "pswwr2_mem009_i_mem_prty_3", | |
2467 | "pswwr2_mem009_i_mem_prty_4", | |
2468 | "pswwr2_mem009_i_mem_prty_5", | |
2469 | "pswwr2_mem009_i_mem_prty_6", | |
2470 | "pswwr2_mem009_i_mem_prty_7", | |
2471 | "pswwr2_mem009_i_mem_prty_8", | |
2472 | "pswwr2_mem013_i_mem_prty_0", | |
2473 | "pswwr2_mem013_i_mem_prty_1", | |
2474 | "pswwr2_mem013_i_mem_prty_2", | |
2475 | "pswwr2_mem013_i_mem_prty_3", | |
2476 | "pswwr2_mem013_i_mem_prty_4", | |
2477 | "pswwr2_mem013_i_mem_prty_5", | |
2478 | "pswwr2_mem013_i_mem_prty_6", | |
2479 | "pswwr2_mem013_i_mem_prty_7", | |
2480 | "pswwr2_mem013_i_mem_prty_8", | |
2481 | "pswwr2_mem006_i_mem_prty_0", | |
2482 | "pswwr2_mem006_i_mem_prty_1", | |
2483 | "pswwr2_mem006_i_mem_prty_2", | |
2484 | "pswwr2_mem006_i_mem_prty_3", | |
2485 | "pswwr2_mem006_i_mem_prty_4", | |
2486 | "pswwr2_mem006_i_mem_prty_5", | |
2487 | "pswwr2_mem006_i_mem_prty_6", | |
2488 | "pswwr2_mem006_i_mem_prty_7", | |
2489 | "pswwr2_mem006_i_mem_prty_8", | |
2490 | "pswwr2_mem010_i_mem_prty_0", | |
2491 | "pswwr2_mem010_i_mem_prty_1", | |
2492 | "pswwr2_mem010_i_mem_prty_2", | |
2493 | "pswwr2_mem010_i_mem_prty_3", | |
2494 | "pswwr2_mem010_i_mem_prty_4", | |
2495 | "pswwr2_mem010_i_mem_prty_5", | |
2496 | "pswwr2_mem010_i_mem_prty_6", | |
2497 | "pswwr2_mem010_i_mem_prty_7", | |
2498 | "pswwr2_mem010_i_mem_prty_8", | |
2499 | "pswwr2_mem012_i_mem_prty", | |
2500 | "pswwr2_mem011_i_mem_prty_0", | |
2501 | "pswwr2_mem011_i_mem_prty_1", | |
2502 | "pswwr2_mem011_i_mem_prty_2", | |
2503 | "pswwr2_mem011_i_mem_prty_3", | |
2504 | "pswwr2_mem011_i_mem_prty_4", | |
2505 | "pswwr2_mem011_i_mem_prty_5", | |
2506 | "pswwr2_mem011_i_mem_prty_6", | |
2507 | "pswwr2_mem011_i_mem_prty_7", | |
2508 | "pswwr2_mem011_i_mem_prty_8", | |
2509 | "pswwr2_mem004_i_mem_prty_0", | |
2510 | "pswwr2_mem004_i_mem_prty_1", | |
2511 | "pswwr2_mem004_i_mem_prty_2", | |
2512 | "pswwr2_mem004_i_mem_prty_3", | |
2513 | "pswwr2_mem004_i_mem_prty_4", | |
2514 | "pswwr2_mem004_i_mem_prty_5", | |
2515 | "pswwr2_mem004_i_mem_prty_6", | |
2516 | "pswwr2_mem004_i_mem_prty_7", | |
2517 | "pswwr2_mem004_i_mem_prty_8", | |
2518 | "pswwr2_mem015_i_mem_prty_0", | |
2519 | "pswwr2_mem015_i_mem_prty_1", | |
2520 | "pswwr2_mem015_i_mem_prty_2", | |
2521 | "pswwr2_mem005_i_mem_prty_0", | |
2522 | "pswwr2_mem005_i_mem_prty_1", | |
2523 | "pswwr2_mem005_i_mem_prty_2", | |
2524 | "pswwr2_mem005_i_mem_prty_3", | |
2525 | "pswwr2_mem005_i_mem_prty_4", | |
2526 | "pswwr2_mem005_i_mem_prty_5", | |
2527 | "pswwr2_mem005_i_mem_prty_6", | |
2528 | "pswwr2_mem005_i_mem_prty_7", | |
2529 | "pswwr2_mem005_i_mem_prty_8", | |
2530 | "pswwr2_mem002_i_mem_prty_0", | |
2531 | "pswwr2_mem002_i_mem_prty_1", | |
2532 | "pswwr2_mem002_i_mem_prty_2", | |
2533 | "pswwr2_mem002_i_mem_prty_3", | |
2534 | "pswwr2_mem002_i_mem_prty_4", | |
2535 | "pswwr2_mem003_i_mem_prty_0", | |
2536 | "pswwr2_mem003_i_mem_prty_1", | |
2537 | "pswwr2_mem003_i_mem_prty_2", | |
2538 | }; | |
2539 | #else | |
2540 | #define pswwr2_prty_attn_desc OSAL_NULL | |
2541 | #endif | |
2542 | ||
2543 | static const u16 pswwr2_prty1_bb_a0_attn_idx[31] = { | |
2544 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, | |
2545 | 21, | |
2546 | 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
2547 | }; | |
2548 | ||
2549 | static struct attn_hw_reg pswwr2_prty1_bb_a0 = { | |
2550 | 0, 31, pswwr2_prty1_bb_a0_attn_idx, 0x29b200, 0x29b20c, 0x29b208, | |
2551 | 0x29b204 | |
2552 | }; | |
2553 | ||
2554 | static const u16 pswwr2_prty2_bb_a0_attn_idx[31] = { | |
2555 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, | |
2556 | 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, | |
2557 | }; | |
2558 | ||
2559 | static struct attn_hw_reg pswwr2_prty2_bb_a0 = { | |
2560 | 1, 31, pswwr2_prty2_bb_a0_attn_idx, 0x29b210, 0x29b21c, 0x29b218, | |
2561 | 0x29b214 | |
2562 | }; | |
2563 | ||
2564 | static const u16 pswwr2_prty3_bb_a0_attn_idx[31] = { | |
2565 | 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, | |
2566 | 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, | |
2567 | }; | |
2568 | ||
2569 | static struct attn_hw_reg pswwr2_prty3_bb_a0 = { | |
2570 | 2, 31, pswwr2_prty3_bb_a0_attn_idx, 0x29b220, 0x29b22c, 0x29b228, | |
2571 | 0x29b224 | |
2572 | }; | |
2573 | ||
2574 | static const u16 pswwr2_prty4_bb_a0_attn_idx[20] = { | |
2575 | 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, | |
2576 | 109, | |
2577 | 110, 111, 112, 113, | |
2578 | }; | |
2579 | ||
2580 | static struct attn_hw_reg pswwr2_prty4_bb_a0 = { | |
2581 | 3, 20, pswwr2_prty4_bb_a0_attn_idx, 0x29b230, 0x29b23c, 0x29b238, | |
2582 | 0x29b234 | |
2583 | }; | |
2584 | ||
2585 | static struct attn_hw_reg *pswwr2_prty_bb_a0_regs[4] = { | |
2586 | &pswwr2_prty1_bb_a0, &pswwr2_prty2_bb_a0, &pswwr2_prty3_bb_a0, | |
2587 | &pswwr2_prty4_bb_a0, | |
2588 | }; | |
2589 | ||
2590 | static const u16 pswwr2_prty0_bb_b0_attn_idx[1] = { | |
2591 | 0, | |
2592 | }; | |
2593 | ||
2594 | static struct attn_hw_reg pswwr2_prty0_bb_b0 = { | |
2595 | 0, 1, pswwr2_prty0_bb_b0_attn_idx, 0x29b190, 0x29b19c, 0x29b198, | |
2596 | 0x29b194 | |
2597 | }; | |
2598 | ||
2599 | static const u16 pswwr2_prty1_bb_b0_attn_idx[31] = { | |
2600 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, | |
2601 | 21, | |
2602 | 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
2603 | }; | |
2604 | ||
2605 | static struct attn_hw_reg pswwr2_prty1_bb_b0 = { | |
2606 | 1, 31, pswwr2_prty1_bb_b0_attn_idx, 0x29b200, 0x29b20c, 0x29b208, | |
2607 | 0x29b204 | |
2608 | }; | |
2609 | ||
2610 | static const u16 pswwr2_prty2_bb_b0_attn_idx[31] = { | |
2611 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, | |
2612 | 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, | |
2613 | }; | |
2614 | ||
2615 | static struct attn_hw_reg pswwr2_prty2_bb_b0 = { | |
2616 | 2, 31, pswwr2_prty2_bb_b0_attn_idx, 0x29b210, 0x29b21c, 0x29b218, | |
2617 | 0x29b214 | |
2618 | }; | |
2619 | ||
2620 | static const u16 pswwr2_prty3_bb_b0_attn_idx[31] = { | |
2621 | 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, | |
2622 | 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, | |
2623 | }; | |
2624 | ||
2625 | static struct attn_hw_reg pswwr2_prty3_bb_b0 = { | |
2626 | 3, 31, pswwr2_prty3_bb_b0_attn_idx, 0x29b220, 0x29b22c, 0x29b228, | |
2627 | 0x29b224 | |
2628 | }; | |
2629 | ||
2630 | static const u16 pswwr2_prty4_bb_b0_attn_idx[20] = { | |
2631 | 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, | |
2632 | 109, | |
2633 | 110, 111, 112, 113, | |
2634 | }; | |
2635 | ||
2636 | static struct attn_hw_reg pswwr2_prty4_bb_b0 = { | |
2637 | 4, 20, pswwr2_prty4_bb_b0_attn_idx, 0x29b230, 0x29b23c, 0x29b238, | |
2638 | 0x29b234 | |
2639 | }; | |
2640 | ||
2641 | static struct attn_hw_reg *pswwr2_prty_bb_b0_regs[5] = { | |
2642 | &pswwr2_prty0_bb_b0, &pswwr2_prty1_bb_b0, &pswwr2_prty2_bb_b0, | |
2643 | &pswwr2_prty3_bb_b0, &pswwr2_prty4_bb_b0, | |
2644 | }; | |
2645 | ||
2646 | static const u16 pswwr2_prty0_k2_attn_idx[1] = { | |
2647 | 0, | |
2648 | }; | |
2649 | ||
2650 | static struct attn_hw_reg pswwr2_prty0_k2 = { | |
2651 | 0, 1, pswwr2_prty0_k2_attn_idx, 0x29b190, 0x29b19c, 0x29b198, 0x29b194 | |
2652 | }; | |
2653 | ||
2654 | static const u16 pswwr2_prty1_k2_attn_idx[31] = { | |
2655 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, | |
2656 | 21, | |
2657 | 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
2658 | }; | |
2659 | ||
2660 | static struct attn_hw_reg pswwr2_prty1_k2 = { | |
2661 | 1, 31, pswwr2_prty1_k2_attn_idx, 0x29b200, 0x29b20c, 0x29b208, 0x29b204 | |
2662 | }; | |
2663 | ||
2664 | static const u16 pswwr2_prty2_k2_attn_idx[31] = { | |
2665 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, | |
2666 | 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, | |
2667 | }; | |
2668 | ||
2669 | static struct attn_hw_reg pswwr2_prty2_k2 = { | |
2670 | 2, 31, pswwr2_prty2_k2_attn_idx, 0x29b210, 0x29b21c, 0x29b218, 0x29b214 | |
2671 | }; | |
2672 | ||
2673 | static const u16 pswwr2_prty3_k2_attn_idx[31] = { | |
2674 | 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, | |
2675 | 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, | |
2676 | }; | |
2677 | ||
2678 | static struct attn_hw_reg pswwr2_prty3_k2 = { | |
2679 | 3, 31, pswwr2_prty3_k2_attn_idx, 0x29b220, 0x29b22c, 0x29b228, 0x29b224 | |
2680 | }; | |
2681 | ||
2682 | static const u16 pswwr2_prty4_k2_attn_idx[20] = { | |
2683 | 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, | |
2684 | 109, | |
2685 | 110, 111, 112, 113, | |
2686 | }; | |
2687 | ||
2688 | static struct attn_hw_reg pswwr2_prty4_k2 = { | |
2689 | 4, 20, pswwr2_prty4_k2_attn_idx, 0x29b230, 0x29b23c, 0x29b238, 0x29b234 | |
2690 | }; | |
2691 | ||
2692 | static struct attn_hw_reg *pswwr2_prty_k2_regs[5] = { | |
2693 | &pswwr2_prty0_k2, &pswwr2_prty1_k2, &pswwr2_prty2_k2, &pswwr2_prty3_k2, | |
2694 | &pswwr2_prty4_k2, | |
2695 | }; | |
2696 | ||
2697 | #ifdef ATTN_DESC | |
2698 | static const char *pswrq_int_attn_desc[21] = { | |
2699 | "pswrq_address_error", | |
2700 | "pswrq_pbf_fifo_overflow", | |
2701 | "pswrq_src_fifo_overflow", | |
2702 | "pswrq_qm_fifo_overflow", | |
2703 | "pswrq_tm_fifo_overflow", | |
2704 | "pswrq_usdm_fifo_overflow", | |
2705 | "pswrq_m2p_fifo_overflow", | |
2706 | "pswrq_xsdm_fifo_overflow", | |
2707 | "pswrq_tsdm_fifo_overflow", | |
2708 | "pswrq_ptu_fifo_overflow", | |
2709 | "pswrq_cduwr_fifo_overflow", | |
2710 | "pswrq_cdurd_fifo_overflow", | |
2711 | "pswrq_dmae_fifo_overflow", | |
2712 | "pswrq_hc_fifo_overflow", | |
2713 | "pswrq_dbg_fifo_overflow", | |
2714 | "pswrq_msdm_fifo_overflow", | |
2715 | "pswrq_ysdm_fifo_overflow", | |
2716 | "pswrq_psdm_fifo_overflow", | |
2717 | "pswrq_prm_fifo_overflow", | |
2718 | "pswrq_muld_fifo_overflow", | |
2719 | "pswrq_xyld_fifo_overflow", | |
2720 | }; | |
2721 | #else | |
2722 | #define pswrq_int_attn_desc OSAL_NULL | |
2723 | #endif | |
2724 | ||
2725 | static const u16 pswrq_int0_bb_a0_attn_idx[21] = { | |
2726 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
2727 | 20, | |
2728 | }; | |
2729 | ||
2730 | static struct attn_hw_reg pswrq_int0_bb_a0 = { | |
2731 | 0, 21, pswrq_int0_bb_a0_attn_idx, 0x280180, 0x28018c, 0x280188, | |
2732 | 0x280184 | |
2733 | }; | |
2734 | ||
2735 | static struct attn_hw_reg *pswrq_int_bb_a0_regs[1] = { | |
2736 | &pswrq_int0_bb_a0, | |
2737 | }; | |
2738 | ||
2739 | static const u16 pswrq_int0_bb_b0_attn_idx[21] = { | |
2740 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
2741 | 20, | |
2742 | }; | |
2743 | ||
2744 | static struct attn_hw_reg pswrq_int0_bb_b0 = { | |
2745 | 0, 21, pswrq_int0_bb_b0_attn_idx, 0x280180, 0x28018c, 0x280188, | |
2746 | 0x280184 | |
2747 | }; | |
2748 | ||
2749 | static struct attn_hw_reg *pswrq_int_bb_b0_regs[1] = { | |
2750 | &pswrq_int0_bb_b0, | |
2751 | }; | |
2752 | ||
2753 | static const u16 pswrq_int0_k2_attn_idx[21] = { | |
2754 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
2755 | 20, | |
2756 | }; | |
2757 | ||
2758 | static struct attn_hw_reg pswrq_int0_k2 = { | |
2759 | 0, 21, pswrq_int0_k2_attn_idx, 0x280180, 0x28018c, 0x280188, 0x280184 | |
2760 | }; | |
2761 | ||
2762 | static struct attn_hw_reg *pswrq_int_k2_regs[1] = { | |
2763 | &pswrq_int0_k2, | |
2764 | }; | |
2765 | ||
2766 | #ifdef ATTN_DESC | |
2767 | static const char *pswrq_prty_attn_desc[1] = { | |
2768 | "pswrq_pxp_busip_parity", | |
2769 | }; | |
2770 | #else | |
2771 | #define pswrq_prty_attn_desc OSAL_NULL | |
2772 | #endif | |
2773 | ||
2774 | static const u16 pswrq_prty0_bb_b0_attn_idx[1] = { | |
2775 | 0, | |
2776 | }; | |
2777 | ||
2778 | static struct attn_hw_reg pswrq_prty0_bb_b0 = { | |
2779 | 0, 1, pswrq_prty0_bb_b0_attn_idx, 0x280190, 0x28019c, 0x280198, | |
2780 | 0x280194 | |
2781 | }; | |
2782 | ||
2783 | static struct attn_hw_reg *pswrq_prty_bb_b0_regs[1] = { | |
2784 | &pswrq_prty0_bb_b0, | |
2785 | }; | |
2786 | ||
2787 | static const u16 pswrq_prty0_k2_attn_idx[1] = { | |
2788 | 0, | |
2789 | }; | |
2790 | ||
2791 | static struct attn_hw_reg pswrq_prty0_k2 = { | |
2792 | 0, 1, pswrq_prty0_k2_attn_idx, 0x280190, 0x28019c, 0x280198, 0x280194 | |
2793 | }; | |
2794 | ||
2795 | static struct attn_hw_reg *pswrq_prty_k2_regs[1] = { | |
2796 | &pswrq_prty0_k2, | |
2797 | }; | |
2798 | ||
2799 | #ifdef ATTN_DESC | |
2800 | static const char *pswrq2_int_attn_desc[15] = { | |
2801 | "pswrq2_address_error", | |
2802 | "pswrq2_l2p_fifo_overflow", | |
2803 | "pswrq2_wdfifo_overflow", | |
2804 | "pswrq2_phyaddr_fifo_of", | |
2805 | "pswrq2_l2p_violation_1", | |
2806 | "pswrq2_l2p_violation_2", | |
2807 | "pswrq2_free_list_empty", | |
2808 | "pswrq2_elt_addr", | |
2809 | "pswrq2_l2p_vf_err", | |
2810 | "pswrq2_core_wdone_overflow", | |
2811 | "pswrq2_treq_fifo_underflow", | |
2812 | "pswrq2_treq_fifo_overflow", | |
2813 | "pswrq2_icpl_fifo_underflow", | |
2814 | "pswrq2_icpl_fifo_overflow", | |
2815 | "pswrq2_back2back_atc_response", | |
2816 | }; | |
2817 | #else | |
2818 | #define pswrq2_int_attn_desc OSAL_NULL | |
2819 | #endif | |
2820 | ||
2821 | static const u16 pswrq2_int0_bb_a0_attn_idx[15] = { | |
2822 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, | |
2823 | }; | |
2824 | ||
2825 | static struct attn_hw_reg pswrq2_int0_bb_a0 = { | |
2826 | 0, 15, pswrq2_int0_bb_a0_attn_idx, 0x240180, 0x24018c, 0x240188, | |
2827 | 0x240184 | |
2828 | }; | |
2829 | ||
2830 | static struct attn_hw_reg *pswrq2_int_bb_a0_regs[1] = { | |
2831 | &pswrq2_int0_bb_a0, | |
2832 | }; | |
2833 | ||
2834 | static const u16 pswrq2_int0_bb_b0_attn_idx[15] = { | |
2835 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, | |
2836 | }; | |
2837 | ||
2838 | static struct attn_hw_reg pswrq2_int0_bb_b0 = { | |
2839 | 0, 15, pswrq2_int0_bb_b0_attn_idx, 0x240180, 0x24018c, 0x240188, | |
2840 | 0x240184 | |
2841 | }; | |
2842 | ||
2843 | static struct attn_hw_reg *pswrq2_int_bb_b0_regs[1] = { | |
2844 | &pswrq2_int0_bb_b0, | |
2845 | }; | |
2846 | ||
2847 | static const u16 pswrq2_int0_k2_attn_idx[15] = { | |
2848 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, | |
2849 | }; | |
2850 | ||
2851 | static struct attn_hw_reg pswrq2_int0_k2 = { | |
2852 | 0, 15, pswrq2_int0_k2_attn_idx, 0x240180, 0x24018c, 0x240188, 0x240184 | |
2853 | }; | |
2854 | ||
2855 | static struct attn_hw_reg *pswrq2_int_k2_regs[1] = { | |
2856 | &pswrq2_int0_k2, | |
2857 | }; | |
2858 | ||
2859 | #ifdef ATTN_DESC | |
2860 | static const char *pswrq2_prty_attn_desc[11] = { | |
2861 | "pswrq2_mem004_i_ecc_rf_int", | |
2862 | "pswrq2_mem005_i_ecc_rf_int", | |
2863 | "pswrq2_mem001_i_ecc_rf_int", | |
2864 | "pswrq2_mem006_i_mem_prty", | |
2865 | "pswrq2_mem008_i_mem_prty", | |
2866 | "pswrq2_mem009_i_mem_prty", | |
2867 | "pswrq2_mem003_i_mem_prty", | |
2868 | "pswrq2_mem002_i_mem_prty", | |
2869 | "pswrq2_mem010_i_mem_prty", | |
2870 | "pswrq2_mem007_i_mem_prty", | |
2871 | "pswrq2_mem005_i_mem_prty", | |
2872 | }; | |
2873 | #else | |
2874 | #define pswrq2_prty_attn_desc OSAL_NULL | |
2875 | #endif | |
2876 | ||
2877 | static const u16 pswrq2_prty1_bb_a0_attn_idx[9] = { | |
2878 | 0, 2, 3, 4, 5, 6, 7, 9, 10, | |
2879 | }; | |
2880 | ||
2881 | static struct attn_hw_reg pswrq2_prty1_bb_a0 = { | |
2882 | 0, 9, pswrq2_prty1_bb_a0_attn_idx, 0x240200, 0x24020c, 0x240208, | |
2883 | 0x240204 | |
2884 | }; | |
2885 | ||
2886 | static struct attn_hw_reg *pswrq2_prty_bb_a0_regs[1] = { | |
2887 | &pswrq2_prty1_bb_a0, | |
2888 | }; | |
2889 | ||
2890 | static const u16 pswrq2_prty1_bb_b0_attn_idx[9] = { | |
2891 | 0, 2, 3, 4, 5, 6, 7, 9, 10, | |
2892 | }; | |
2893 | ||
2894 | static struct attn_hw_reg pswrq2_prty1_bb_b0 = { | |
2895 | 0, 9, pswrq2_prty1_bb_b0_attn_idx, 0x240200, 0x24020c, 0x240208, | |
2896 | 0x240204 | |
2897 | }; | |
2898 | ||
2899 | static struct attn_hw_reg *pswrq2_prty_bb_b0_regs[1] = { | |
2900 | &pswrq2_prty1_bb_b0, | |
2901 | }; | |
2902 | ||
2903 | static const u16 pswrq2_prty1_k2_attn_idx[10] = { | |
2904 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, | |
2905 | }; | |
2906 | ||
2907 | static struct attn_hw_reg pswrq2_prty1_k2 = { | |
2908 | 0, 10, pswrq2_prty1_k2_attn_idx, 0x240200, 0x24020c, 0x240208, 0x240204 | |
2909 | }; | |
2910 | ||
2911 | static struct attn_hw_reg *pswrq2_prty_k2_regs[1] = { | |
2912 | &pswrq2_prty1_k2, | |
2913 | }; | |
2914 | ||
2915 | #ifdef ATTN_DESC | |
2916 | static const char *pglcs_int_attn_desc[2] = { | |
2917 | "pglcs_address_error", | |
2918 | "pglcs_rasdp_error", | |
2919 | }; | |
2920 | #else | |
2921 | #define pglcs_int_attn_desc OSAL_NULL | |
2922 | #endif | |
2923 | ||
2924 | static const u16 pglcs_int0_bb_a0_attn_idx[1] = { | |
2925 | 0, | |
2926 | }; | |
2927 | ||
2928 | static struct attn_hw_reg pglcs_int0_bb_a0 = { | |
2929 | 0, 1, pglcs_int0_bb_a0_attn_idx, 0x1d00, 0x1d0c, 0x1d08, 0x1d04 | |
2930 | }; | |
2931 | ||
2932 | static struct attn_hw_reg *pglcs_int_bb_a0_regs[1] = { | |
2933 | &pglcs_int0_bb_a0, | |
2934 | }; | |
2935 | ||
2936 | static const u16 pglcs_int0_bb_b0_attn_idx[1] = { | |
2937 | 0, | |
2938 | }; | |
2939 | ||
2940 | static struct attn_hw_reg pglcs_int0_bb_b0 = { | |
2941 | 0, 1, pglcs_int0_bb_b0_attn_idx, 0x1d00, 0x1d0c, 0x1d08, 0x1d04 | |
2942 | }; | |
2943 | ||
2944 | static struct attn_hw_reg *pglcs_int_bb_b0_regs[1] = { | |
2945 | &pglcs_int0_bb_b0, | |
2946 | }; | |
2947 | ||
2948 | static const u16 pglcs_int0_k2_attn_idx[2] = { | |
2949 | 0, 1, | |
2950 | }; | |
2951 | ||
2952 | static struct attn_hw_reg pglcs_int0_k2 = { | |
2953 | 0, 2, pglcs_int0_k2_attn_idx, 0x1d00, 0x1d0c, 0x1d08, 0x1d04 | |
2954 | }; | |
2955 | ||
2956 | static struct attn_hw_reg *pglcs_int_k2_regs[1] = { | |
2957 | &pglcs_int0_k2, | |
2958 | }; | |
2959 | ||
2960 | #ifdef ATTN_DESC | |
2961 | static const char *dmae_int_attn_desc[2] = { | |
2962 | "dmae_address_error", | |
2963 | "dmae_pci_rd_buf_err", | |
2964 | }; | |
2965 | #else | |
2966 | #define dmae_int_attn_desc OSAL_NULL | |
2967 | #endif | |
2968 | ||
2969 | static const u16 dmae_int0_bb_a0_attn_idx[2] = { | |
2970 | 0, 1, | |
2971 | }; | |
2972 | ||
2973 | static struct attn_hw_reg dmae_int0_bb_a0 = { | |
2974 | 0, 2, dmae_int0_bb_a0_attn_idx, 0xc180, 0xc18c, 0xc188, 0xc184 | |
2975 | }; | |
2976 | ||
2977 | static struct attn_hw_reg *dmae_int_bb_a0_regs[1] = { | |
2978 | &dmae_int0_bb_a0, | |
2979 | }; | |
2980 | ||
2981 | static const u16 dmae_int0_bb_b0_attn_idx[2] = { | |
2982 | 0, 1, | |
2983 | }; | |
2984 | ||
2985 | static struct attn_hw_reg dmae_int0_bb_b0 = { | |
2986 | 0, 2, dmae_int0_bb_b0_attn_idx, 0xc180, 0xc18c, 0xc188, 0xc184 | |
2987 | }; | |
2988 | ||
2989 | static struct attn_hw_reg *dmae_int_bb_b0_regs[1] = { | |
2990 | &dmae_int0_bb_b0, | |
2991 | }; | |
2992 | ||
2993 | static const u16 dmae_int0_k2_attn_idx[2] = { | |
2994 | 0, 1, | |
2995 | }; | |
2996 | ||
2997 | static struct attn_hw_reg dmae_int0_k2 = { | |
2998 | 0, 2, dmae_int0_k2_attn_idx, 0xc180, 0xc18c, 0xc188, 0xc184 | |
2999 | }; | |
3000 | ||
3001 | static struct attn_hw_reg *dmae_int_k2_regs[1] = { | |
3002 | &dmae_int0_k2, | |
3003 | }; | |
3004 | ||
3005 | #ifdef ATTN_DESC | |
3006 | static const char *dmae_prty_attn_desc[3] = { | |
3007 | "dmae_mem002_i_mem_prty", | |
3008 | "dmae_mem001_i_mem_prty", | |
3009 | "dmae_mem003_i_mem_prty", | |
3010 | }; | |
3011 | #else | |
3012 | #define dmae_prty_attn_desc OSAL_NULL | |
3013 | #endif | |
3014 | ||
3015 | static const u16 dmae_prty1_bb_a0_attn_idx[3] = { | |
3016 | 0, 1, 2, | |
3017 | }; | |
3018 | ||
3019 | static struct attn_hw_reg dmae_prty1_bb_a0 = { | |
3020 | 0, 3, dmae_prty1_bb_a0_attn_idx, 0xc200, 0xc20c, 0xc208, 0xc204 | |
3021 | }; | |
3022 | ||
3023 | static struct attn_hw_reg *dmae_prty_bb_a0_regs[1] = { | |
3024 | &dmae_prty1_bb_a0, | |
3025 | }; | |
3026 | ||
3027 | static const u16 dmae_prty1_bb_b0_attn_idx[3] = { | |
3028 | 0, 1, 2, | |
3029 | }; | |
3030 | ||
3031 | static struct attn_hw_reg dmae_prty1_bb_b0 = { | |
3032 | 0, 3, dmae_prty1_bb_b0_attn_idx, 0xc200, 0xc20c, 0xc208, 0xc204 | |
3033 | }; | |
3034 | ||
3035 | static struct attn_hw_reg *dmae_prty_bb_b0_regs[1] = { | |
3036 | &dmae_prty1_bb_b0, | |
3037 | }; | |
3038 | ||
3039 | static const u16 dmae_prty1_k2_attn_idx[3] = { | |
3040 | 0, 1, 2, | |
3041 | }; | |
3042 | ||
3043 | static struct attn_hw_reg dmae_prty1_k2 = { | |
3044 | 0, 3, dmae_prty1_k2_attn_idx, 0xc200, 0xc20c, 0xc208, 0xc204 | |
3045 | }; | |
3046 | ||
3047 | static struct attn_hw_reg *dmae_prty_k2_regs[1] = { | |
3048 | &dmae_prty1_k2, | |
3049 | }; | |
3050 | ||
3051 | #ifdef ATTN_DESC | |
3052 | static const char *ptu_int_attn_desc[8] = { | |
3053 | "ptu_address_error", | |
3054 | "ptu_atc_tcpl_to_not_pend", | |
3055 | "ptu_atc_gpa_multiple_hits", | |
3056 | "ptu_atc_rcpl_to_empty_cnt", | |
3057 | "ptu_atc_tcpl_error", | |
3058 | "ptu_atc_inv_halt", | |
3059 | "ptu_atc_reuse_transpend", | |
3060 | "ptu_atc_ireq_less_than_stu", | |
3061 | }; | |
3062 | #else | |
3063 | #define ptu_int_attn_desc OSAL_NULL | |
3064 | #endif | |
3065 | ||
3066 | static const u16 ptu_int0_bb_a0_attn_idx[8] = { | |
3067 | 0, 1, 2, 3, 4, 5, 6, 7, | |
3068 | }; | |
3069 | ||
3070 | static struct attn_hw_reg ptu_int0_bb_a0 = { | |
3071 | 0, 8, ptu_int0_bb_a0_attn_idx, 0x560180, 0x56018c, 0x560188, 0x560184 | |
3072 | }; | |
3073 | ||
3074 | static struct attn_hw_reg *ptu_int_bb_a0_regs[1] = { | |
3075 | &ptu_int0_bb_a0, | |
3076 | }; | |
3077 | ||
3078 | static const u16 ptu_int0_bb_b0_attn_idx[8] = { | |
3079 | 0, 1, 2, 3, 4, 5, 6, 7, | |
3080 | }; | |
3081 | ||
3082 | static struct attn_hw_reg ptu_int0_bb_b0 = { | |
3083 | 0, 8, ptu_int0_bb_b0_attn_idx, 0x560180, 0x56018c, 0x560188, 0x560184 | |
3084 | }; | |
3085 | ||
3086 | static struct attn_hw_reg *ptu_int_bb_b0_regs[1] = { | |
3087 | &ptu_int0_bb_b0, | |
3088 | }; | |
3089 | ||
3090 | static const u16 ptu_int0_k2_attn_idx[8] = { | |
3091 | 0, 1, 2, 3, 4, 5, 6, 7, | |
3092 | }; | |
3093 | ||
3094 | static struct attn_hw_reg ptu_int0_k2 = { | |
3095 | 0, 8, ptu_int0_k2_attn_idx, 0x560180, 0x56018c, 0x560188, 0x560184 | |
3096 | }; | |
3097 | ||
3098 | static struct attn_hw_reg *ptu_int_k2_regs[1] = { | |
3099 | &ptu_int0_k2, | |
3100 | }; | |
3101 | ||
3102 | #ifdef ATTN_DESC | |
3103 | static const char *ptu_prty_attn_desc[18] = { | |
3104 | "ptu_mem017_i_ecc_rf_int", | |
3105 | "ptu_mem018_i_mem_prty", | |
3106 | "ptu_mem006_i_mem_prty", | |
3107 | "ptu_mem001_i_mem_prty", | |
3108 | "ptu_mem002_i_mem_prty", | |
3109 | "ptu_mem003_i_mem_prty", | |
3110 | "ptu_mem004_i_mem_prty", | |
3111 | "ptu_mem005_i_mem_prty", | |
3112 | "ptu_mem009_i_mem_prty", | |
3113 | "ptu_mem010_i_mem_prty", | |
3114 | "ptu_mem016_i_mem_prty", | |
3115 | "ptu_mem007_i_mem_prty", | |
3116 | "ptu_mem015_i_mem_prty", | |
3117 | "ptu_mem013_i_mem_prty", | |
3118 | "ptu_mem012_i_mem_prty", | |
3119 | "ptu_mem014_i_mem_prty", | |
3120 | "ptu_mem011_i_mem_prty", | |
3121 | "ptu_mem008_i_mem_prty", | |
3122 | }; | |
3123 | #else | |
3124 | #define ptu_prty_attn_desc OSAL_NULL | |
3125 | #endif | |
3126 | ||
3127 | static const u16 ptu_prty1_bb_a0_attn_idx[18] = { | |
3128 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, | |
3129 | }; | |
3130 | ||
3131 | static struct attn_hw_reg ptu_prty1_bb_a0 = { | |
3132 | 0, 18, ptu_prty1_bb_a0_attn_idx, 0x560200, 0x56020c, 0x560208, 0x560204 | |
3133 | }; | |
3134 | ||
3135 | static struct attn_hw_reg *ptu_prty_bb_a0_regs[1] = { | |
3136 | &ptu_prty1_bb_a0, | |
3137 | }; | |
3138 | ||
3139 | static const u16 ptu_prty1_bb_b0_attn_idx[18] = { | |
3140 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, | |
3141 | }; | |
3142 | ||
3143 | static struct attn_hw_reg ptu_prty1_bb_b0 = { | |
3144 | 0, 18, ptu_prty1_bb_b0_attn_idx, 0x560200, 0x56020c, 0x560208, 0x560204 | |
3145 | }; | |
3146 | ||
3147 | static struct attn_hw_reg *ptu_prty_bb_b0_regs[1] = { | |
3148 | &ptu_prty1_bb_b0, | |
3149 | }; | |
3150 | ||
3151 | static const u16 ptu_prty1_k2_attn_idx[18] = { | |
3152 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, | |
3153 | }; | |
3154 | ||
3155 | static struct attn_hw_reg ptu_prty1_k2 = { | |
3156 | 0, 18, ptu_prty1_k2_attn_idx, 0x560200, 0x56020c, 0x560208, 0x560204 | |
3157 | }; | |
3158 | ||
3159 | static struct attn_hw_reg *ptu_prty_k2_regs[1] = { | |
3160 | &ptu_prty1_k2, | |
3161 | }; | |
3162 | ||
3163 | #ifdef ATTN_DESC | |
3164 | static const char *tcm_int_attn_desc[41] = { | |
3165 | "tcm_address_error", | |
3166 | "tcm_is_storm_ovfl_err", | |
3167 | "tcm_is_storm_under_err", | |
3168 | "tcm_is_tsdm_ovfl_err", | |
3169 | "tcm_is_tsdm_under_err", | |
3170 | "tcm_is_msem_ovfl_err", | |
3171 | "tcm_is_msem_under_err", | |
3172 | "tcm_is_ysem_ovfl_err", | |
3173 | "tcm_is_ysem_under_err", | |
3174 | "tcm_is_dorq_ovfl_err", | |
3175 | "tcm_is_dorq_under_err", | |
3176 | "tcm_is_pbf_ovfl_err", | |
3177 | "tcm_is_pbf_under_err", | |
3178 | "tcm_is_prs_ovfl_err", | |
3179 | "tcm_is_prs_under_err", | |
3180 | "tcm_is_tm_ovfl_err", | |
3181 | "tcm_is_tm_under_err", | |
3182 | "tcm_is_qm_p_ovfl_err", | |
3183 | "tcm_is_qm_p_under_err", | |
3184 | "tcm_is_qm_s_ovfl_err", | |
3185 | "tcm_is_qm_s_under_err", | |
3186 | "tcm_is_grc_ovfl_err0", | |
3187 | "tcm_is_grc_under_err0", | |
3188 | "tcm_is_grc_ovfl_err1", | |
3189 | "tcm_is_grc_under_err1", | |
3190 | "tcm_is_grc_ovfl_err2", | |
3191 | "tcm_is_grc_under_err2", | |
3192 | "tcm_is_grc_ovfl_err3", | |
3193 | "tcm_is_grc_under_err3", | |
3194 | "tcm_in_prcs_tbl_ovfl", | |
3195 | "tcm_agg_con_data_buf_ovfl", | |
3196 | "tcm_agg_con_cmd_buf_ovfl", | |
3197 | "tcm_sm_con_data_buf_ovfl", | |
3198 | "tcm_sm_con_cmd_buf_ovfl", | |
3199 | "tcm_agg_task_data_buf_ovfl", | |
3200 | "tcm_agg_task_cmd_buf_ovfl", | |
3201 | "tcm_sm_task_data_buf_ovfl", | |
3202 | "tcm_sm_task_cmd_buf_ovfl", | |
3203 | "tcm_fi_desc_input_violate", | |
3204 | "tcm_se_desc_input_violate", | |
3205 | "tcm_qmreg_more4", | |
3206 | }; | |
3207 | #else | |
3208 | #define tcm_int_attn_desc OSAL_NULL | |
3209 | #endif | |
3210 | ||
3211 | static const u16 tcm_int0_bb_a0_attn_idx[8] = { | |
3212 | 0, 1, 2, 3, 4, 5, 6, 7, | |
3213 | }; | |
3214 | ||
3215 | static struct attn_hw_reg tcm_int0_bb_a0 = { | |
3216 | 0, 8, tcm_int0_bb_a0_attn_idx, 0x1180180, 0x118018c, 0x1180188, | |
3217 | 0x1180184 | |
3218 | }; | |
3219 | ||
3220 | static const u16 tcm_int1_bb_a0_attn_idx[32] = { | |
3221 | 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, | |
3222 | 26, | |
3223 | 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, | |
3224 | }; | |
3225 | ||
3226 | static struct attn_hw_reg tcm_int1_bb_a0 = { | |
3227 | 1, 32, tcm_int1_bb_a0_attn_idx, 0x1180190, 0x118019c, 0x1180198, | |
3228 | 0x1180194 | |
3229 | }; | |
3230 | ||
3231 | static const u16 tcm_int2_bb_a0_attn_idx[1] = { | |
3232 | 40, | |
3233 | }; | |
3234 | ||
3235 | static struct attn_hw_reg tcm_int2_bb_a0 = { | |
3236 | 2, 1, tcm_int2_bb_a0_attn_idx, 0x11801a0, 0x11801ac, 0x11801a8, | |
3237 | 0x11801a4 | |
3238 | }; | |
3239 | ||
3240 | static struct attn_hw_reg *tcm_int_bb_a0_regs[3] = { | |
3241 | &tcm_int0_bb_a0, &tcm_int1_bb_a0, &tcm_int2_bb_a0, | |
3242 | }; | |
3243 | ||
3244 | static const u16 tcm_int0_bb_b0_attn_idx[8] = { | |
3245 | 0, 1, 2, 3, 4, 5, 6, 7, | |
3246 | }; | |
3247 | ||
3248 | static struct attn_hw_reg tcm_int0_bb_b0 = { | |
3249 | 0, 8, tcm_int0_bb_b0_attn_idx, 0x1180180, 0x118018c, 0x1180188, | |
3250 | 0x1180184 | |
3251 | }; | |
3252 | ||
3253 | static const u16 tcm_int1_bb_b0_attn_idx[32] = { | |
3254 | 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, | |
3255 | 26, | |
3256 | 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, | |
3257 | }; | |
3258 | ||
3259 | static struct attn_hw_reg tcm_int1_bb_b0 = { | |
3260 | 1, 32, tcm_int1_bb_b0_attn_idx, 0x1180190, 0x118019c, 0x1180198, | |
3261 | 0x1180194 | |
3262 | }; | |
3263 | ||
3264 | static const u16 tcm_int2_bb_b0_attn_idx[1] = { | |
3265 | 40, | |
3266 | }; | |
3267 | ||
3268 | static struct attn_hw_reg tcm_int2_bb_b0 = { | |
3269 | 2, 1, tcm_int2_bb_b0_attn_idx, 0x11801a0, 0x11801ac, 0x11801a8, | |
3270 | 0x11801a4 | |
3271 | }; | |
3272 | ||
3273 | static struct attn_hw_reg *tcm_int_bb_b0_regs[3] = { | |
3274 | &tcm_int0_bb_b0, &tcm_int1_bb_b0, &tcm_int2_bb_b0, | |
3275 | }; | |
3276 | ||
3277 | static const u16 tcm_int0_k2_attn_idx[8] = { | |
3278 | 0, 1, 2, 3, 4, 5, 6, 7, | |
3279 | }; | |
3280 | ||
3281 | static struct attn_hw_reg tcm_int0_k2 = { | |
3282 | 0, 8, tcm_int0_k2_attn_idx, 0x1180180, 0x118018c, 0x1180188, 0x1180184 | |
3283 | }; | |
3284 | ||
3285 | static const u16 tcm_int1_k2_attn_idx[32] = { | |
3286 | 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, | |
3287 | 26, | |
3288 | 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, | |
3289 | }; | |
3290 | ||
3291 | static struct attn_hw_reg tcm_int1_k2 = { | |
3292 | 1, 32, tcm_int1_k2_attn_idx, 0x1180190, 0x118019c, 0x1180198, 0x1180194 | |
3293 | }; | |
3294 | ||
3295 | static const u16 tcm_int2_k2_attn_idx[1] = { | |
3296 | 40, | |
3297 | }; | |
3298 | ||
3299 | static struct attn_hw_reg tcm_int2_k2 = { | |
3300 | 2, 1, tcm_int2_k2_attn_idx, 0x11801a0, 0x11801ac, 0x11801a8, 0x11801a4 | |
3301 | }; | |
3302 | ||
3303 | static struct attn_hw_reg *tcm_int_k2_regs[3] = { | |
3304 | &tcm_int0_k2, &tcm_int1_k2, &tcm_int2_k2, | |
3305 | }; | |
3306 | ||
3307 | #ifdef ATTN_DESC | |
3308 | static const char *tcm_prty_attn_desc[51] = { | |
3309 | "tcm_mem026_i_ecc_rf_int", | |
3310 | "tcm_mem003_i_ecc_0_rf_int", | |
3311 | "tcm_mem003_i_ecc_1_rf_int", | |
3312 | "tcm_mem022_i_ecc_0_rf_int", | |
3313 | "tcm_mem022_i_ecc_1_rf_int", | |
3314 | "tcm_mem005_i_ecc_0_rf_int", | |
3315 | "tcm_mem005_i_ecc_1_rf_int", | |
3316 | "tcm_mem024_i_ecc_0_rf_int", | |
3317 | "tcm_mem024_i_ecc_1_rf_int", | |
3318 | "tcm_mem018_i_mem_prty", | |
3319 | "tcm_mem019_i_mem_prty", | |
3320 | "tcm_mem015_i_mem_prty", | |
3321 | "tcm_mem016_i_mem_prty", | |
3322 | "tcm_mem017_i_mem_prty", | |
3323 | "tcm_mem010_i_mem_prty", | |
3324 | "tcm_mem020_i_mem_prty", | |
3325 | "tcm_mem011_i_mem_prty", | |
3326 | "tcm_mem012_i_mem_prty", | |
3327 | "tcm_mem013_i_mem_prty", | |
3328 | "tcm_mem014_i_mem_prty", | |
3329 | "tcm_mem029_i_mem_prty", | |
3330 | "tcm_mem028_i_mem_prty", | |
3331 | "tcm_mem027_i_mem_prty", | |
3332 | "tcm_mem004_i_mem_prty", | |
3333 | "tcm_mem023_i_mem_prty", | |
3334 | "tcm_mem006_i_mem_prty", | |
3335 | "tcm_mem025_i_mem_prty", | |
3336 | "tcm_mem021_i_mem_prty", | |
3337 | "tcm_mem007_i_mem_prty_0", | |
3338 | "tcm_mem007_i_mem_prty_1", | |
3339 | "tcm_mem008_i_mem_prty", | |
3340 | "tcm_mem025_i_ecc_rf_int", | |
3341 | "tcm_mem021_i_ecc_0_rf_int", | |
3342 | "tcm_mem021_i_ecc_1_rf_int", | |
3343 | "tcm_mem023_i_ecc_0_rf_int", | |
3344 | "tcm_mem023_i_ecc_1_rf_int", | |
3345 | "tcm_mem026_i_mem_prty", | |
3346 | "tcm_mem022_i_mem_prty", | |
3347 | "tcm_mem024_i_mem_prty", | |
3348 | "tcm_mem009_i_mem_prty", | |
3349 | "tcm_mem024_i_ecc_rf_int", | |
3350 | "tcm_mem001_i_ecc_0_rf_int", | |
3351 | "tcm_mem001_i_ecc_1_rf_int", | |
3352 | "tcm_mem019_i_ecc_0_rf_int", | |
3353 | "tcm_mem019_i_ecc_1_rf_int", | |
3354 | "tcm_mem022_i_ecc_rf_int", | |
3355 | "tcm_mem002_i_mem_prty", | |
3356 | "tcm_mem005_i_mem_prty_0", | |
3357 | "tcm_mem005_i_mem_prty_1", | |
3358 | "tcm_mem001_i_mem_prty", | |
3359 | "tcm_mem007_i_mem_prty", | |
3360 | }; | |
3361 | #else | |
3362 | #define tcm_prty_attn_desc OSAL_NULL | |
3363 | #endif | |
3364 | ||
3365 | static const u16 tcm_prty1_bb_a0_attn_idx[31] = { | |
3366 | 1, 2, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, 30, 32, | |
3367 | 33, 36, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, | |
3368 | }; | |
3369 | ||
3370 | static struct attn_hw_reg tcm_prty1_bb_a0 = { | |
3371 | 0, 31, tcm_prty1_bb_a0_attn_idx, 0x1180200, 0x118020c, 0x1180208, | |
3372 | 0x1180204 | |
3373 | }; | |
3374 | ||
3375 | static const u16 tcm_prty2_bb_a0_attn_idx[3] = { | |
3376 | 50, 21, 20, | |
3377 | }; | |
3378 | ||
3379 | static struct attn_hw_reg tcm_prty2_bb_a0 = { | |
3380 | 1, 3, tcm_prty2_bb_a0_attn_idx, 0x1180210, 0x118021c, 0x1180218, | |
3381 | 0x1180214 | |
3382 | }; | |
3383 | ||
3384 | static struct attn_hw_reg *tcm_prty_bb_a0_regs[2] = { | |
3385 | &tcm_prty1_bb_a0, &tcm_prty2_bb_a0, | |
3386 | }; | |
3387 | ||
3388 | static const u16 tcm_prty1_bb_b0_attn_idx[31] = { | |
3389 | 1, 2, 5, 6, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21, 22, 23, 25, | |
3390 | 28, | |
3391 | 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, | |
3392 | }; | |
3393 | ||
3394 | static struct attn_hw_reg tcm_prty1_bb_b0 = { | |
3395 | 0, 31, tcm_prty1_bb_b0_attn_idx, 0x1180200, 0x118020c, 0x1180208, | |
3396 | 0x1180204 | |
3397 | }; | |
3398 | ||
3399 | static const u16 tcm_prty2_bb_b0_attn_idx[2] = { | |
3400 | 49, 46, | |
3401 | }; | |
3402 | ||
3403 | static struct attn_hw_reg tcm_prty2_bb_b0 = { | |
3404 | 1, 2, tcm_prty2_bb_b0_attn_idx, 0x1180210, 0x118021c, 0x1180218, | |
3405 | 0x1180214 | |
3406 | }; | |
3407 | ||
3408 | static struct attn_hw_reg *tcm_prty_bb_b0_regs[2] = { | |
3409 | &tcm_prty1_bb_b0, &tcm_prty2_bb_b0, | |
3410 | }; | |
3411 | ||
3412 | static const u16 tcm_prty1_k2_attn_idx[31] = { | |
3413 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
3414 | 20, | |
3415 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, | |
3416 | }; | |
3417 | ||
3418 | static struct attn_hw_reg tcm_prty1_k2 = { | |
3419 | 0, 31, tcm_prty1_k2_attn_idx, 0x1180200, 0x118020c, 0x1180208, | |
3420 | 0x1180204 | |
3421 | }; | |
3422 | ||
3423 | static const u16 tcm_prty2_k2_attn_idx[3] = { | |
3424 | 39, 49, 46, | |
3425 | }; | |
3426 | ||
3427 | static struct attn_hw_reg tcm_prty2_k2 = { | |
3428 | 1, 3, tcm_prty2_k2_attn_idx, 0x1180210, 0x118021c, 0x1180218, 0x1180214 | |
3429 | }; | |
3430 | ||
3431 | static struct attn_hw_reg *tcm_prty_k2_regs[2] = { | |
3432 | &tcm_prty1_k2, &tcm_prty2_k2, | |
3433 | }; | |
3434 | ||
3435 | #ifdef ATTN_DESC | |
3436 | static const char *mcm_int_attn_desc[41] = { | |
3437 | "mcm_address_error", | |
3438 | "mcm_is_storm_ovfl_err", | |
3439 | "mcm_is_storm_under_err", | |
3440 | "mcm_is_msdm_ovfl_err", | |
3441 | "mcm_is_msdm_under_err", | |
3442 | "mcm_is_ysdm_ovfl_err", | |
3443 | "mcm_is_ysdm_under_err", | |
3444 | "mcm_is_usdm_ovfl_err", | |
3445 | "mcm_is_usdm_under_err", | |
3446 | "mcm_is_tmld_ovfl_err", | |
3447 | "mcm_is_tmld_under_err", | |
3448 | "mcm_is_usem_ovfl_err", | |
3449 | "mcm_is_usem_under_err", | |
3450 | "mcm_is_ysem_ovfl_err", | |
3451 | "mcm_is_ysem_under_err", | |
3452 | "mcm_is_pbf_ovfl_err", | |
3453 | "mcm_is_pbf_under_err", | |
3454 | "mcm_is_qm_p_ovfl_err", | |
3455 | "mcm_is_qm_p_under_err", | |
3456 | "mcm_is_qm_s_ovfl_err", | |
3457 | "mcm_is_qm_s_under_err", | |
3458 | "mcm_is_grc_ovfl_err0", | |
3459 | "mcm_is_grc_under_err0", | |
3460 | "mcm_is_grc_ovfl_err1", | |
3461 | "mcm_is_grc_under_err1", | |
3462 | "mcm_is_grc_ovfl_err2", | |
3463 | "mcm_is_grc_under_err2", | |
3464 | "mcm_is_grc_ovfl_err3", | |
3465 | "mcm_is_grc_under_err3", | |
3466 | "mcm_in_prcs_tbl_ovfl", | |
3467 | "mcm_agg_con_data_buf_ovfl", | |
3468 | "mcm_agg_con_cmd_buf_ovfl", | |
3469 | "mcm_sm_con_data_buf_ovfl", | |
3470 | "mcm_sm_con_cmd_buf_ovfl", | |
3471 | "mcm_agg_task_data_buf_ovfl", | |
3472 | "mcm_agg_task_cmd_buf_ovfl", | |
3473 | "mcm_sm_task_data_buf_ovfl", | |
3474 | "mcm_sm_task_cmd_buf_ovfl", | |
3475 | "mcm_fi_desc_input_violate", | |
3476 | "mcm_se_desc_input_violate", | |
3477 | "mcm_qmreg_more4", | |
3478 | }; | |
3479 | #else | |
3480 | #define mcm_int_attn_desc OSAL_NULL | |
3481 | #endif | |
3482 | ||
3483 | static const u16 mcm_int0_bb_a0_attn_idx[14] = { | |
3484 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, | |
3485 | }; | |
3486 | ||
3487 | static struct attn_hw_reg mcm_int0_bb_a0 = { | |
3488 | 0, 14, mcm_int0_bb_a0_attn_idx, 0x1200180, 0x120018c, 0x1200188, | |
3489 | 0x1200184 | |
3490 | }; | |
3491 | ||
3492 | static const u16 mcm_int1_bb_a0_attn_idx[26] = { | |
3493 | 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
3494 | 32, 33, 34, 35, 36, 37, 38, 39, | |
3495 | }; | |
3496 | ||
3497 | static struct attn_hw_reg mcm_int1_bb_a0 = { | |
3498 | 1, 26, mcm_int1_bb_a0_attn_idx, 0x1200190, 0x120019c, 0x1200198, | |
3499 | 0x1200194 | |
3500 | }; | |
3501 | ||
3502 | static const u16 mcm_int2_bb_a0_attn_idx[1] = { | |
3503 | 40, | |
3504 | }; | |
3505 | ||
3506 | static struct attn_hw_reg mcm_int2_bb_a0 = { | |
3507 | 2, 1, mcm_int2_bb_a0_attn_idx, 0x12001a0, 0x12001ac, 0x12001a8, | |
3508 | 0x12001a4 | |
3509 | }; | |
3510 | ||
3511 | static struct attn_hw_reg *mcm_int_bb_a0_regs[3] = { | |
3512 | &mcm_int0_bb_a0, &mcm_int1_bb_a0, &mcm_int2_bb_a0, | |
3513 | }; | |
3514 | ||
3515 | static const u16 mcm_int0_bb_b0_attn_idx[14] = { | |
3516 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, | |
3517 | }; | |
3518 | ||
3519 | static struct attn_hw_reg mcm_int0_bb_b0 = { | |
3520 | 0, 14, mcm_int0_bb_b0_attn_idx, 0x1200180, 0x120018c, 0x1200188, | |
3521 | 0x1200184 | |
3522 | }; | |
3523 | ||
3524 | static const u16 mcm_int1_bb_b0_attn_idx[26] = { | |
3525 | 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
3526 | 32, 33, 34, 35, 36, 37, 38, 39, | |
3527 | }; | |
3528 | ||
3529 | static struct attn_hw_reg mcm_int1_bb_b0 = { | |
3530 | 1, 26, mcm_int1_bb_b0_attn_idx, 0x1200190, 0x120019c, 0x1200198, | |
3531 | 0x1200194 | |
3532 | }; | |
3533 | ||
3534 | static const u16 mcm_int2_bb_b0_attn_idx[1] = { | |
3535 | 40, | |
3536 | }; | |
3537 | ||
3538 | static struct attn_hw_reg mcm_int2_bb_b0 = { | |
3539 | 2, 1, mcm_int2_bb_b0_attn_idx, 0x12001a0, 0x12001ac, 0x12001a8, | |
3540 | 0x12001a4 | |
3541 | }; | |
3542 | ||
3543 | static struct attn_hw_reg *mcm_int_bb_b0_regs[3] = { | |
3544 | &mcm_int0_bb_b0, &mcm_int1_bb_b0, &mcm_int2_bb_b0, | |
3545 | }; | |
3546 | ||
3547 | static const u16 mcm_int0_k2_attn_idx[14] = { | |
3548 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, | |
3549 | }; | |
3550 | ||
3551 | static struct attn_hw_reg mcm_int0_k2 = { | |
3552 | 0, 14, mcm_int0_k2_attn_idx, 0x1200180, 0x120018c, 0x1200188, 0x1200184 | |
3553 | }; | |
3554 | ||
3555 | static const u16 mcm_int1_k2_attn_idx[26] = { | |
3556 | 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
3557 | 32, 33, 34, 35, 36, 37, 38, 39, | |
3558 | }; | |
3559 | ||
3560 | static struct attn_hw_reg mcm_int1_k2 = { | |
3561 | 1, 26, mcm_int1_k2_attn_idx, 0x1200190, 0x120019c, 0x1200198, 0x1200194 | |
3562 | }; | |
3563 | ||
3564 | static const u16 mcm_int2_k2_attn_idx[1] = { | |
3565 | 40, | |
3566 | }; | |
3567 | ||
3568 | static struct attn_hw_reg mcm_int2_k2 = { | |
3569 | 2, 1, mcm_int2_k2_attn_idx, 0x12001a0, 0x12001ac, 0x12001a8, 0x12001a4 | |
3570 | }; | |
3571 | ||
3572 | static struct attn_hw_reg *mcm_int_k2_regs[3] = { | |
3573 | &mcm_int0_k2, &mcm_int1_k2, &mcm_int2_k2, | |
3574 | }; | |
3575 | ||
3576 | #ifdef ATTN_DESC | |
3577 | static const char *mcm_prty_attn_desc[46] = { | |
3578 | "mcm_mem028_i_ecc_rf_int", | |
3579 | "mcm_mem003_i_ecc_rf_int", | |
3580 | "mcm_mem023_i_ecc_0_rf_int", | |
3581 | "mcm_mem023_i_ecc_1_rf_int", | |
3582 | "mcm_mem005_i_ecc_0_rf_int", | |
3583 | "mcm_mem005_i_ecc_1_rf_int", | |
3584 | "mcm_mem025_i_ecc_0_rf_int", | |
3585 | "mcm_mem025_i_ecc_1_rf_int", | |
3586 | "mcm_mem026_i_ecc_rf_int", | |
3587 | "mcm_mem017_i_mem_prty", | |
3588 | "mcm_mem019_i_mem_prty", | |
3589 | "mcm_mem016_i_mem_prty", | |
3590 | "mcm_mem015_i_mem_prty", | |
3591 | "mcm_mem020_i_mem_prty", | |
3592 | "mcm_mem021_i_mem_prty", | |
3593 | "mcm_mem018_i_mem_prty", | |
3594 | "mcm_mem011_i_mem_prty", | |
3595 | "mcm_mem012_i_mem_prty", | |
3596 | "mcm_mem013_i_mem_prty", | |
3597 | "mcm_mem014_i_mem_prty", | |
3598 | "mcm_mem031_i_mem_prty", | |
3599 | "mcm_mem030_i_mem_prty", | |
3600 | "mcm_mem029_i_mem_prty", | |
3601 | "mcm_mem004_i_mem_prty", | |
3602 | "mcm_mem024_i_mem_prty", | |
3603 | "mcm_mem006_i_mem_prty", | |
3604 | "mcm_mem027_i_mem_prty", | |
3605 | "mcm_mem022_i_mem_prty", | |
3606 | "mcm_mem007_i_mem_prty_0", | |
3607 | "mcm_mem007_i_mem_prty_1", | |
3608 | "mcm_mem008_i_mem_prty", | |
3609 | "mcm_mem001_i_ecc_rf_int", | |
3610 | "mcm_mem021_i_ecc_0_rf_int", | |
3611 | "mcm_mem021_i_ecc_1_rf_int", | |
3612 | "mcm_mem003_i_ecc_0_rf_int", | |
3613 | "mcm_mem003_i_ecc_1_rf_int", | |
3614 | "mcm_mem024_i_ecc_rf_int", | |
3615 | "mcm_mem009_i_mem_prty", | |
3616 | "mcm_mem010_i_mem_prty", | |
3617 | "mcm_mem028_i_mem_prty", | |
3618 | "mcm_mem002_i_mem_prty", | |
3619 | "mcm_mem025_i_mem_prty", | |
3620 | "mcm_mem005_i_mem_prty_0", | |
3621 | "mcm_mem005_i_mem_prty_1", | |
3622 | "mcm_mem001_i_mem_prty", | |
3623 | "mcm_mem007_i_mem_prty", | |
3624 | }; | |
3625 | #else | |
3626 | #define mcm_prty_attn_desc OSAL_NULL | |
3627 | #endif | |
3628 | ||
3629 | static const u16 mcm_prty1_bb_a0_attn_idx[31] = { | |
3630 | 2, 3, 8, 9, 10, 11, 12, 13, 15, 16, 17, 18, 19, 22, 23, 25, 26, 27, 31, | |
3631 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, | |
3632 | }; | |
3633 | ||
3634 | static struct attn_hw_reg mcm_prty1_bb_a0 = { | |
3635 | 0, 31, mcm_prty1_bb_a0_attn_idx, 0x1200200, 0x120020c, 0x1200208, | |
3636 | 0x1200204 | |
3637 | }; | |
3638 | ||
3639 | static const u16 mcm_prty2_bb_a0_attn_idx[4] = { | |
3640 | 45, 30, 21, 20, | |
3641 | }; | |
3642 | ||
3643 | static struct attn_hw_reg mcm_prty2_bb_a0 = { | |
3644 | 1, 4, mcm_prty2_bb_a0_attn_idx, 0x1200210, 0x120021c, 0x1200218, | |
3645 | 0x1200214 | |
3646 | }; | |
3647 | ||
3648 | static struct attn_hw_reg *mcm_prty_bb_a0_regs[2] = { | |
3649 | &mcm_prty1_bb_a0, &mcm_prty2_bb_a0, | |
3650 | }; | |
3651 | ||
3652 | static const u16 mcm_prty1_bb_b0_attn_idx[31] = { | |
3653 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
3654 | 20, | |
3655 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, | |
3656 | }; | |
3657 | ||
3658 | static struct attn_hw_reg mcm_prty1_bb_b0 = { | |
3659 | 0, 31, mcm_prty1_bb_b0_attn_idx, 0x1200200, 0x120020c, 0x1200208, | |
3660 | 0x1200204 | |
3661 | }; | |
3662 | ||
3663 | static const u16 mcm_prty2_bb_b0_attn_idx[4] = { | |
3664 | 37, 38, 44, 40, | |
3665 | }; | |
3666 | ||
3667 | static struct attn_hw_reg mcm_prty2_bb_b0 = { | |
3668 | 1, 4, mcm_prty2_bb_b0_attn_idx, 0x1200210, 0x120021c, 0x1200218, | |
3669 | 0x1200214 | |
3670 | }; | |
3671 | ||
3672 | static struct attn_hw_reg *mcm_prty_bb_b0_regs[2] = { | |
3673 | &mcm_prty1_bb_b0, &mcm_prty2_bb_b0, | |
3674 | }; | |
3675 | ||
3676 | static const u16 mcm_prty1_k2_attn_idx[31] = { | |
3677 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
3678 | 20, | |
3679 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, | |
3680 | }; | |
3681 | ||
3682 | static struct attn_hw_reg mcm_prty1_k2 = { | |
3683 | 0, 31, mcm_prty1_k2_attn_idx, 0x1200200, 0x120020c, 0x1200208, | |
3684 | 0x1200204 | |
3685 | }; | |
3686 | ||
3687 | static const u16 mcm_prty2_k2_attn_idx[4] = { | |
3688 | 37, 38, 44, 40, | |
3689 | }; | |
3690 | ||
3691 | static struct attn_hw_reg mcm_prty2_k2 = { | |
3692 | 1, 4, mcm_prty2_k2_attn_idx, 0x1200210, 0x120021c, 0x1200218, 0x1200214 | |
3693 | }; | |
3694 | ||
3695 | static struct attn_hw_reg *mcm_prty_k2_regs[2] = { | |
3696 | &mcm_prty1_k2, &mcm_prty2_k2, | |
3697 | }; | |
3698 | ||
3699 | #ifdef ATTN_DESC | |
3700 | static const char *ucm_int_attn_desc[47] = { | |
3701 | "ucm_address_error", | |
3702 | "ucm_is_storm_ovfl_err", | |
3703 | "ucm_is_storm_under_err", | |
3704 | "ucm_is_xsdm_ovfl_err", | |
3705 | "ucm_is_xsdm_under_err", | |
3706 | "ucm_is_ysdm_ovfl_err", | |
3707 | "ucm_is_ysdm_under_err", | |
3708 | "ucm_is_usdm_ovfl_err", | |
3709 | "ucm_is_usdm_under_err", | |
3710 | "ucm_is_rdif_ovfl_err", | |
3711 | "ucm_is_rdif_under_err", | |
3712 | "ucm_is_tdif_ovfl_err", | |
3713 | "ucm_is_tdif_under_err", | |
3714 | "ucm_is_muld_ovfl_err", | |
3715 | "ucm_is_muld_under_err", | |
3716 | "ucm_is_yuld_ovfl_err", | |
3717 | "ucm_is_yuld_under_err", | |
3718 | "ucm_is_dorq_ovfl_err", | |
3719 | "ucm_is_dorq_under_err", | |
3720 | "ucm_is_pbf_ovfl_err", | |
3721 | "ucm_is_pbf_under_err", | |
3722 | "ucm_is_tm_ovfl_err", | |
3723 | "ucm_is_tm_under_err", | |
3724 | "ucm_is_qm_p_ovfl_err", | |
3725 | "ucm_is_qm_p_under_err", | |
3726 | "ucm_is_qm_s_ovfl_err", | |
3727 | "ucm_is_qm_s_under_err", | |
3728 | "ucm_is_grc_ovfl_err0", | |
3729 | "ucm_is_grc_under_err0", | |
3730 | "ucm_is_grc_ovfl_err1", | |
3731 | "ucm_is_grc_under_err1", | |
3732 | "ucm_is_grc_ovfl_err2", | |
3733 | "ucm_is_grc_under_err2", | |
3734 | "ucm_is_grc_ovfl_err3", | |
3735 | "ucm_is_grc_under_err3", | |
3736 | "ucm_in_prcs_tbl_ovfl", | |
3737 | "ucm_agg_con_data_buf_ovfl", | |
3738 | "ucm_agg_con_cmd_buf_ovfl", | |
3739 | "ucm_sm_con_data_buf_ovfl", | |
3740 | "ucm_sm_con_cmd_buf_ovfl", | |
3741 | "ucm_agg_task_data_buf_ovfl", | |
3742 | "ucm_agg_task_cmd_buf_ovfl", | |
3743 | "ucm_sm_task_data_buf_ovfl", | |
3744 | "ucm_sm_task_cmd_buf_ovfl", | |
3745 | "ucm_fi_desc_input_violate", | |
3746 | "ucm_se_desc_input_violate", | |
3747 | "ucm_qmreg_more4", | |
3748 | }; | |
3749 | #else | |
3750 | #define ucm_int_attn_desc OSAL_NULL | |
3751 | #endif | |
3752 | ||
3753 | static const u16 ucm_int0_bb_a0_attn_idx[17] = { | |
3754 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, | |
3755 | }; | |
3756 | ||
3757 | static struct attn_hw_reg ucm_int0_bb_a0 = { | |
3758 | 0, 17, ucm_int0_bb_a0_attn_idx, 0x1280180, 0x128018c, 0x1280188, | |
3759 | 0x1280184 | |
3760 | }; | |
3761 | ||
3762 | static const u16 ucm_int1_bb_a0_attn_idx[29] = { | |
3763 | 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, | |
3764 | 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, | |
3765 | }; | |
3766 | ||
3767 | static struct attn_hw_reg ucm_int1_bb_a0 = { | |
3768 | 1, 29, ucm_int1_bb_a0_attn_idx, 0x1280190, 0x128019c, 0x1280198, | |
3769 | 0x1280194 | |
3770 | }; | |
3771 | ||
3772 | static const u16 ucm_int2_bb_a0_attn_idx[1] = { | |
3773 | 46, | |
3774 | }; | |
3775 | ||
3776 | static struct attn_hw_reg ucm_int2_bb_a0 = { | |
3777 | 2, 1, ucm_int2_bb_a0_attn_idx, 0x12801a0, 0x12801ac, 0x12801a8, | |
3778 | 0x12801a4 | |
3779 | }; | |
3780 | ||
3781 | static struct attn_hw_reg *ucm_int_bb_a0_regs[3] = { | |
3782 | &ucm_int0_bb_a0, &ucm_int1_bb_a0, &ucm_int2_bb_a0, | |
3783 | }; | |
3784 | ||
3785 | static const u16 ucm_int0_bb_b0_attn_idx[17] = { | |
3786 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, | |
3787 | }; | |
3788 | ||
3789 | static struct attn_hw_reg ucm_int0_bb_b0 = { | |
3790 | 0, 17, ucm_int0_bb_b0_attn_idx, 0x1280180, 0x128018c, 0x1280188, | |
3791 | 0x1280184 | |
3792 | }; | |
3793 | ||
3794 | static const u16 ucm_int1_bb_b0_attn_idx[29] = { | |
3795 | 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, | |
3796 | 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, | |
3797 | }; | |
3798 | ||
3799 | static struct attn_hw_reg ucm_int1_bb_b0 = { | |
3800 | 1, 29, ucm_int1_bb_b0_attn_idx, 0x1280190, 0x128019c, 0x1280198, | |
3801 | 0x1280194 | |
3802 | }; | |
3803 | ||
3804 | static const u16 ucm_int2_bb_b0_attn_idx[1] = { | |
3805 | 46, | |
3806 | }; | |
3807 | ||
3808 | static struct attn_hw_reg ucm_int2_bb_b0 = { | |
3809 | 2, 1, ucm_int2_bb_b0_attn_idx, 0x12801a0, 0x12801ac, 0x12801a8, | |
3810 | 0x12801a4 | |
3811 | }; | |
3812 | ||
3813 | static struct attn_hw_reg *ucm_int_bb_b0_regs[3] = { | |
3814 | &ucm_int0_bb_b0, &ucm_int1_bb_b0, &ucm_int2_bb_b0, | |
3815 | }; | |
3816 | ||
3817 | static const u16 ucm_int0_k2_attn_idx[17] = { | |
3818 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, | |
3819 | }; | |
3820 | ||
3821 | static struct attn_hw_reg ucm_int0_k2 = { | |
3822 | 0, 17, ucm_int0_k2_attn_idx, 0x1280180, 0x128018c, 0x1280188, 0x1280184 | |
3823 | }; | |
3824 | ||
3825 | static const u16 ucm_int1_k2_attn_idx[29] = { | |
3826 | 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, | |
3827 | 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, | |
3828 | }; | |
3829 | ||
3830 | static struct attn_hw_reg ucm_int1_k2 = { | |
3831 | 1, 29, ucm_int1_k2_attn_idx, 0x1280190, 0x128019c, 0x1280198, 0x1280194 | |
3832 | }; | |
3833 | ||
3834 | static const u16 ucm_int2_k2_attn_idx[1] = { | |
3835 | 46, | |
3836 | }; | |
3837 | ||
3838 | static struct attn_hw_reg ucm_int2_k2 = { | |
3839 | 2, 1, ucm_int2_k2_attn_idx, 0x12801a0, 0x12801ac, 0x12801a8, 0x12801a4 | |
3840 | }; | |
3841 | ||
3842 | static struct attn_hw_reg *ucm_int_k2_regs[3] = { | |
3843 | &ucm_int0_k2, &ucm_int1_k2, &ucm_int2_k2, | |
3844 | }; | |
3845 | ||
3846 | #ifdef ATTN_DESC | |
3847 | static const char *ucm_prty_attn_desc[54] = { | |
3848 | "ucm_mem030_i_ecc_rf_int", | |
3849 | "ucm_mem005_i_ecc_0_rf_int", | |
3850 | "ucm_mem005_i_ecc_1_rf_int", | |
3851 | "ucm_mem024_i_ecc_0_rf_int", | |
3852 | "ucm_mem024_i_ecc_1_rf_int", | |
3853 | "ucm_mem025_i_ecc_rf_int", | |
3854 | "ucm_mem007_i_ecc_0_rf_int", | |
3855 | "ucm_mem007_i_ecc_1_rf_int", | |
3856 | "ucm_mem008_i_ecc_rf_int", | |
3857 | "ucm_mem027_i_ecc_0_rf_int", | |
3858 | "ucm_mem027_i_ecc_1_rf_int", | |
3859 | "ucm_mem028_i_ecc_rf_int", | |
3860 | "ucm_mem020_i_mem_prty", | |
3861 | "ucm_mem021_i_mem_prty", | |
3862 | "ucm_mem019_i_mem_prty", | |
3863 | "ucm_mem013_i_mem_prty", | |
3864 | "ucm_mem018_i_mem_prty", | |
3865 | "ucm_mem022_i_mem_prty", | |
3866 | "ucm_mem014_i_mem_prty", | |
3867 | "ucm_mem015_i_mem_prty", | |
3868 | "ucm_mem016_i_mem_prty", | |
3869 | "ucm_mem017_i_mem_prty", | |
3870 | "ucm_mem033_i_mem_prty", | |
3871 | "ucm_mem032_i_mem_prty", | |
3872 | "ucm_mem031_i_mem_prty", | |
3873 | "ucm_mem006_i_mem_prty", | |
3874 | "ucm_mem026_i_mem_prty", | |
3875 | "ucm_mem009_i_mem_prty", | |
3876 | "ucm_mem029_i_mem_prty", | |
3877 | "ucm_mem023_i_mem_prty", | |
3878 | "ucm_mem010_i_mem_prty_0", | |
3879 | "ucm_mem003_i_ecc_0_rf_int", | |
3880 | "ucm_mem003_i_ecc_1_rf_int", | |
3881 | "ucm_mem022_i_ecc_0_rf_int", | |
3882 | "ucm_mem022_i_ecc_1_rf_int", | |
3883 | "ucm_mem023_i_ecc_rf_int", | |
3884 | "ucm_mem006_i_ecc_rf_int", | |
3885 | "ucm_mem025_i_ecc_0_rf_int", | |
3886 | "ucm_mem025_i_ecc_1_rf_int", | |
3887 | "ucm_mem026_i_ecc_rf_int", | |
3888 | "ucm_mem011_i_mem_prty", | |
3889 | "ucm_mem012_i_mem_prty", | |
3890 | "ucm_mem030_i_mem_prty", | |
3891 | "ucm_mem004_i_mem_prty", | |
3892 | "ucm_mem024_i_mem_prty", | |
3893 | "ucm_mem007_i_mem_prty", | |
3894 | "ucm_mem027_i_mem_prty", | |
3895 | "ucm_mem008_i_mem_prty_0", | |
3896 | "ucm_mem010_i_mem_prty_1", | |
3897 | "ucm_mem003_i_mem_prty", | |
3898 | "ucm_mem001_i_mem_prty", | |
3899 | "ucm_mem002_i_mem_prty", | |
3900 | "ucm_mem008_i_mem_prty_1", | |
3901 | "ucm_mem010_i_mem_prty", | |
3902 | }; | |
3903 | #else | |
3904 | #define ucm_prty_attn_desc OSAL_NULL | |
3905 | #endif | |
3906 | ||
3907 | static const u16 ucm_prty1_bb_a0_attn_idx[31] = { | |
3908 | 1, 2, 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 24, 28, 31, 32, 33, 34, | |
3909 | 35, | |
3910 | 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, | |
3911 | }; | |
3912 | ||
3913 | static struct attn_hw_reg ucm_prty1_bb_a0 = { | |
3914 | 0, 31, ucm_prty1_bb_a0_attn_idx, 0x1280200, 0x128020c, 0x1280208, | |
3915 | 0x1280204 | |
3916 | }; | |
3917 | ||
3918 | static const u16 ucm_prty2_bb_a0_attn_idx[7] = { | |
3919 | 50, 51, 52, 27, 53, 23, 22, | |
3920 | }; | |
3921 | ||
3922 | static struct attn_hw_reg ucm_prty2_bb_a0 = { | |
3923 | 1, 7, ucm_prty2_bb_a0_attn_idx, 0x1280210, 0x128021c, 0x1280218, | |
3924 | 0x1280214 | |
3925 | }; | |
3926 | ||
3927 | static struct attn_hw_reg *ucm_prty_bb_a0_regs[2] = { | |
3928 | &ucm_prty1_bb_a0, &ucm_prty2_bb_a0, | |
3929 | }; | |
3930 | ||
3931 | static const u16 ucm_prty1_bb_b0_attn_idx[31] = { | |
3932 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
3933 | 20, | |
3934 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, | |
3935 | }; | |
3936 | ||
3937 | static struct attn_hw_reg ucm_prty1_bb_b0 = { | |
3938 | 0, 31, ucm_prty1_bb_b0_attn_idx, 0x1280200, 0x128020c, 0x1280208, | |
3939 | 0x1280204 | |
3940 | }; | |
3941 | ||
3942 | static const u16 ucm_prty2_bb_b0_attn_idx[7] = { | |
3943 | 48, 40, 41, 49, 43, 50, 51, | |
3944 | }; | |
3945 | ||
3946 | static struct attn_hw_reg ucm_prty2_bb_b0 = { | |
3947 | 1, 7, ucm_prty2_bb_b0_attn_idx, 0x1280210, 0x128021c, 0x1280218, | |
3948 | 0x1280214 | |
3949 | }; | |
3950 | ||
3951 | static struct attn_hw_reg *ucm_prty_bb_b0_regs[2] = { | |
3952 | &ucm_prty1_bb_b0, &ucm_prty2_bb_b0, | |
3953 | }; | |
3954 | ||
3955 | static const u16 ucm_prty1_k2_attn_idx[31] = { | |
3956 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
3957 | 20, | |
3958 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, | |
3959 | }; | |
3960 | ||
3961 | static struct attn_hw_reg ucm_prty1_k2 = { | |
3962 | 0, 31, ucm_prty1_k2_attn_idx, 0x1280200, 0x128020c, 0x1280208, | |
3963 | 0x1280204 | |
3964 | }; | |
3965 | ||
3966 | static const u16 ucm_prty2_k2_attn_idx[7] = { | |
3967 | 48, 40, 41, 49, 43, 50, 51, | |
3968 | }; | |
3969 | ||
3970 | static struct attn_hw_reg ucm_prty2_k2 = { | |
3971 | 1, 7, ucm_prty2_k2_attn_idx, 0x1280210, 0x128021c, 0x1280218, 0x1280214 | |
3972 | }; | |
3973 | ||
3974 | static struct attn_hw_reg *ucm_prty_k2_regs[2] = { | |
3975 | &ucm_prty1_k2, &ucm_prty2_k2, | |
3976 | }; | |
3977 | ||
3978 | #ifdef ATTN_DESC | |
3979 | static const char *xcm_int_attn_desc[49] = { | |
3980 | "xcm_address_error", | |
3981 | "xcm_is_storm_ovfl_err", | |
3982 | "xcm_is_storm_under_err", | |
3983 | "xcm_is_msdm_ovfl_err", | |
3984 | "xcm_is_msdm_under_err", | |
3985 | "xcm_is_xsdm_ovfl_err", | |
3986 | "xcm_is_xsdm_under_err", | |
3987 | "xcm_is_ysdm_ovfl_err", | |
3988 | "xcm_is_ysdm_under_err", | |
3989 | "xcm_is_usdm_ovfl_err", | |
3990 | "xcm_is_usdm_under_err", | |
3991 | "xcm_is_msem_ovfl_err", | |
3992 | "xcm_is_msem_under_err", | |
3993 | "xcm_is_usem_ovfl_err", | |
3994 | "xcm_is_usem_under_err", | |
3995 | "xcm_is_ysem_ovfl_err", | |
3996 | "xcm_is_ysem_under_err", | |
3997 | "xcm_is_dorq_ovfl_err", | |
3998 | "xcm_is_dorq_under_err", | |
3999 | "xcm_is_pbf_ovfl_err", | |
4000 | "xcm_is_pbf_under_err", | |
4001 | "xcm_is_tm_ovfl_err", | |
4002 | "xcm_is_tm_under_err", | |
4003 | "xcm_is_qm_p_ovfl_err", | |
4004 | "xcm_is_qm_p_under_err", | |
4005 | "xcm_is_qm_s_ovfl_err", | |
4006 | "xcm_is_qm_s_under_err", | |
4007 | "xcm_is_grc_ovfl_err0", | |
4008 | "xcm_is_grc_under_err0", | |
4009 | "xcm_is_grc_ovfl_err1", | |
4010 | "xcm_is_grc_under_err1", | |
4011 | "xcm_is_grc_ovfl_err2", | |
4012 | "xcm_is_grc_under_err2", | |
4013 | "xcm_is_grc_ovfl_err3", | |
4014 | "xcm_is_grc_under_err3", | |
4015 | "xcm_in_prcs_tbl_ovfl", | |
4016 | "xcm_agg_con_data_buf_ovfl", | |
4017 | "xcm_agg_con_cmd_buf_ovfl", | |
4018 | "xcm_sm_con_data_buf_ovfl", | |
4019 | "xcm_sm_con_cmd_buf_ovfl", | |
4020 | "xcm_fi_desc_input_violate", | |
4021 | "xcm_qm_act_st_cnt_msg_prcs_under", | |
4022 | "xcm_qm_act_st_cnt_msg_prcs_ovfl", | |
4023 | "xcm_qm_act_st_cnt_ext_ld_under", | |
4024 | "xcm_qm_act_st_cnt_ext_ld_ovfl", | |
4025 | "xcm_qm_act_st_cnt_rbc_under", | |
4026 | "xcm_qm_act_st_cnt_rbc_ovfl", | |
4027 | "xcm_qm_act_st_cnt_drop_under", | |
4028 | "xcm_qm_act_st_cnt_illeg_pqnum", | |
4029 | }; | |
4030 | #else | |
4031 | #define xcm_int_attn_desc OSAL_NULL | |
4032 | #endif | |
4033 | ||
4034 | static const u16 xcm_int0_bb_a0_attn_idx[16] = { | |
4035 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, | |
4036 | }; | |
4037 | ||
4038 | static struct attn_hw_reg xcm_int0_bb_a0 = { | |
4039 | 0, 16, xcm_int0_bb_a0_attn_idx, 0x1000180, 0x100018c, 0x1000188, | |
4040 | 0x1000184 | |
4041 | }; | |
4042 | ||
4043 | static const u16 xcm_int1_bb_a0_attn_idx[25] = { | |
4044 | 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, | |
4045 | 34, 35, 36, 37, 38, 39, 40, | |
4046 | }; | |
4047 | ||
4048 | static struct attn_hw_reg xcm_int1_bb_a0 = { | |
4049 | 1, 25, xcm_int1_bb_a0_attn_idx, 0x1000190, 0x100019c, 0x1000198, | |
4050 | 0x1000194 | |
4051 | }; | |
4052 | ||
4053 | static const u16 xcm_int2_bb_a0_attn_idx[8] = { | |
4054 | 41, 42, 43, 44, 45, 46, 47, 48, | |
4055 | }; | |
4056 | ||
4057 | static struct attn_hw_reg xcm_int2_bb_a0 = { | |
4058 | 2, 8, xcm_int2_bb_a0_attn_idx, 0x10001a0, 0x10001ac, 0x10001a8, | |
4059 | 0x10001a4 | |
4060 | }; | |
4061 | ||
4062 | static struct attn_hw_reg *xcm_int_bb_a0_regs[3] = { | |
4063 | &xcm_int0_bb_a0, &xcm_int1_bb_a0, &xcm_int2_bb_a0, | |
4064 | }; | |
4065 | ||
4066 | static const u16 xcm_int0_bb_b0_attn_idx[16] = { | |
4067 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, | |
4068 | }; | |
4069 | ||
4070 | static struct attn_hw_reg xcm_int0_bb_b0 = { | |
4071 | 0, 16, xcm_int0_bb_b0_attn_idx, 0x1000180, 0x100018c, 0x1000188, | |
4072 | 0x1000184 | |
4073 | }; | |
4074 | ||
4075 | static const u16 xcm_int1_bb_b0_attn_idx[25] = { | |
4076 | 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, | |
4077 | 34, 35, 36, 37, 38, 39, 40, | |
4078 | }; | |
4079 | ||
4080 | static struct attn_hw_reg xcm_int1_bb_b0 = { | |
4081 | 1, 25, xcm_int1_bb_b0_attn_idx, 0x1000190, 0x100019c, 0x1000198, | |
4082 | 0x1000194 | |
4083 | }; | |
4084 | ||
4085 | static const u16 xcm_int2_bb_b0_attn_idx[8] = { | |
4086 | 41, 42, 43, 44, 45, 46, 47, 48, | |
4087 | }; | |
4088 | ||
4089 | static struct attn_hw_reg xcm_int2_bb_b0 = { | |
4090 | 2, 8, xcm_int2_bb_b0_attn_idx, 0x10001a0, 0x10001ac, 0x10001a8, | |
4091 | 0x10001a4 | |
4092 | }; | |
4093 | ||
4094 | static struct attn_hw_reg *xcm_int_bb_b0_regs[3] = { | |
4095 | &xcm_int0_bb_b0, &xcm_int1_bb_b0, &xcm_int2_bb_b0, | |
4096 | }; | |
4097 | ||
4098 | static const u16 xcm_int0_k2_attn_idx[16] = { | |
4099 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, | |
4100 | }; | |
4101 | ||
4102 | static struct attn_hw_reg xcm_int0_k2 = { | |
4103 | 0, 16, xcm_int0_k2_attn_idx, 0x1000180, 0x100018c, 0x1000188, 0x1000184 | |
4104 | }; | |
4105 | ||
4106 | static const u16 xcm_int1_k2_attn_idx[25] = { | |
4107 | 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, | |
4108 | 34, 35, 36, 37, 38, 39, 40, | |
4109 | }; | |
4110 | ||
4111 | static struct attn_hw_reg xcm_int1_k2 = { | |
4112 | 1, 25, xcm_int1_k2_attn_idx, 0x1000190, 0x100019c, 0x1000198, 0x1000194 | |
4113 | }; | |
4114 | ||
4115 | static const u16 xcm_int2_k2_attn_idx[8] = { | |
4116 | 41, 42, 43, 44, 45, 46, 47, 48, | |
4117 | }; | |
4118 | ||
4119 | static struct attn_hw_reg xcm_int2_k2 = { | |
4120 | 2, 8, xcm_int2_k2_attn_idx, 0x10001a0, 0x10001ac, 0x10001a8, 0x10001a4 | |
4121 | }; | |
4122 | ||
4123 | static struct attn_hw_reg *xcm_int_k2_regs[3] = { | |
4124 | &xcm_int0_k2, &xcm_int1_k2, &xcm_int2_k2, | |
4125 | }; | |
4126 | ||
4127 | #ifdef ATTN_DESC | |
4128 | static const char *xcm_prty_attn_desc[59] = { | |
4129 | "xcm_mem036_i_ecc_rf_int", | |
4130 | "xcm_mem003_i_ecc_0_rf_int", | |
4131 | "xcm_mem003_i_ecc_1_rf_int", | |
4132 | "xcm_mem003_i_ecc_2_rf_int", | |
4133 | "xcm_mem003_i_ecc_3_rf_int", | |
4134 | "xcm_mem004_i_ecc_rf_int", | |
4135 | "xcm_mem033_i_ecc_0_rf_int", | |
4136 | "xcm_mem033_i_ecc_1_rf_int", | |
4137 | "xcm_mem034_i_ecc_rf_int", | |
4138 | "xcm_mem026_i_mem_prty", | |
4139 | "xcm_mem025_i_mem_prty", | |
4140 | "xcm_mem022_i_mem_prty", | |
4141 | "xcm_mem029_i_mem_prty", | |
4142 | "xcm_mem023_i_mem_prty", | |
4143 | "xcm_mem028_i_mem_prty", | |
4144 | "xcm_mem030_i_mem_prty", | |
4145 | "xcm_mem017_i_mem_prty", | |
4146 | "xcm_mem024_i_mem_prty", | |
4147 | "xcm_mem027_i_mem_prty", | |
4148 | "xcm_mem018_i_mem_prty", | |
4149 | "xcm_mem019_i_mem_prty", | |
4150 | "xcm_mem020_i_mem_prty", | |
4151 | "xcm_mem021_i_mem_prty", | |
4152 | "xcm_mem039_i_mem_prty", | |
4153 | "xcm_mem038_i_mem_prty", | |
4154 | "xcm_mem037_i_mem_prty", | |
4155 | "xcm_mem005_i_mem_prty", | |
4156 | "xcm_mem035_i_mem_prty", | |
4157 | "xcm_mem031_i_mem_prty", | |
4158 | "xcm_mem006_i_mem_prty", | |
4159 | "xcm_mem015_i_mem_prty", | |
4160 | "xcm_mem035_i_ecc_rf_int", | |
4161 | "xcm_mem032_i_ecc_0_rf_int", | |
4162 | "xcm_mem032_i_ecc_1_rf_int", | |
4163 | "xcm_mem033_i_ecc_rf_int", | |
4164 | "xcm_mem036_i_mem_prty", | |
4165 | "xcm_mem034_i_mem_prty", | |
4166 | "xcm_mem016_i_mem_prty", | |
4167 | "xcm_mem002_i_ecc_0_rf_int", | |
4168 | "xcm_mem002_i_ecc_1_rf_int", | |
4169 | "xcm_mem002_i_ecc_2_rf_int", | |
4170 | "xcm_mem002_i_ecc_3_rf_int", | |
4171 | "xcm_mem003_i_ecc_rf_int", | |
4172 | "xcm_mem031_i_ecc_0_rf_int", | |
4173 | "xcm_mem031_i_ecc_1_rf_int", | |
4174 | "xcm_mem032_i_ecc_rf_int", | |
4175 | "xcm_mem004_i_mem_prty", | |
4176 | "xcm_mem033_i_mem_prty", | |
4177 | "xcm_mem014_i_mem_prty", | |
4178 | "xcm_mem032_i_mem_prty", | |
4179 | "xcm_mem007_i_mem_prty", | |
4180 | "xcm_mem008_i_mem_prty", | |
4181 | "xcm_mem009_i_mem_prty", | |
4182 | "xcm_mem010_i_mem_prty", | |
4183 | "xcm_mem011_i_mem_prty", | |
4184 | "xcm_mem012_i_mem_prty", | |
4185 | "xcm_mem013_i_mem_prty", | |
4186 | "xcm_mem001_i_mem_prty", | |
4187 | "xcm_mem002_i_mem_prty", | |
4188 | }; | |
4189 | #else | |
4190 | #define xcm_prty_attn_desc OSAL_NULL | |
4191 | #endif | |
4192 | ||
4193 | static const u16 xcm_prty1_bb_a0_attn_idx[31] = { | |
4194 | 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 19, 20, 21, 22, 25, 26, 27, 30, | |
4195 | 35, | |
4196 | 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, | |
4197 | }; | |
4198 | ||
4199 | static struct attn_hw_reg xcm_prty1_bb_a0 = { | |
4200 | 0, 31, xcm_prty1_bb_a0_attn_idx, 0x1000200, 0x100020c, 0x1000208, | |
4201 | 0x1000204 | |
4202 | }; | |
4203 | ||
4204 | static const u16 xcm_prty2_bb_a0_attn_idx[11] = { | |
4205 | 50, 51, 52, 53, 54, 55, 56, 57, 15, 29, 24, | |
4206 | }; | |
4207 | ||
4208 | static struct attn_hw_reg xcm_prty2_bb_a0 = { | |
4209 | 1, 11, xcm_prty2_bb_a0_attn_idx, 0x1000210, 0x100021c, 0x1000218, | |
4210 | 0x1000214 | |
4211 | }; | |
4212 | ||
4213 | static struct attn_hw_reg *xcm_prty_bb_a0_regs[2] = { | |
4214 | &xcm_prty1_bb_a0, &xcm_prty2_bb_a0, | |
4215 | }; | |
4216 | ||
4217 | static const u16 xcm_prty1_bb_b0_attn_idx[31] = { | |
4218 | 1, 2, 3, 4, 5, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, | |
4219 | 24, | |
4220 | 25, 26, 29, 30, 31, 32, 33, 34, 35, 36, 37, | |
4221 | }; | |
4222 | ||
4223 | static struct attn_hw_reg xcm_prty1_bb_b0 = { | |
4224 | 0, 31, xcm_prty1_bb_b0_attn_idx, 0x1000200, 0x100020c, 0x1000208, | |
4225 | 0x1000204 | |
4226 | }; | |
4227 | ||
4228 | static const u16 xcm_prty2_bb_b0_attn_idx[11] = { | |
4229 | 50, 51, 52, 53, 54, 55, 56, 48, 57, 58, 28, | |
4230 | }; | |
4231 | ||
4232 | static struct attn_hw_reg xcm_prty2_bb_b0 = { | |
4233 | 1, 11, xcm_prty2_bb_b0_attn_idx, 0x1000210, 0x100021c, 0x1000218, | |
4234 | 0x1000214 | |
4235 | }; | |
4236 | ||
4237 | static struct attn_hw_reg *xcm_prty_bb_b0_regs[2] = { | |
4238 | &xcm_prty1_bb_b0, &xcm_prty2_bb_b0, | |
4239 | }; | |
4240 | ||
4241 | static const u16 xcm_prty1_k2_attn_idx[31] = { | |
4242 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
4243 | 20, | |
4244 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, | |
4245 | }; | |
4246 | ||
4247 | static struct attn_hw_reg xcm_prty1_k2 = { | |
4248 | 0, 31, xcm_prty1_k2_attn_idx, 0x1000200, 0x100020c, 0x1000208, | |
4249 | 0x1000204 | |
4250 | }; | |
4251 | ||
4252 | static const u16 xcm_prty2_k2_attn_idx[12] = { | |
4253 | 37, 49, 50, 51, 52, 53, 54, 55, 56, 48, 57, 58, | |
4254 | }; | |
4255 | ||
4256 | static struct attn_hw_reg xcm_prty2_k2 = { | |
4257 | 1, 12, xcm_prty2_k2_attn_idx, 0x1000210, 0x100021c, 0x1000218, | |
4258 | 0x1000214 | |
4259 | }; | |
4260 | ||
4261 | static struct attn_hw_reg *xcm_prty_k2_regs[2] = { | |
4262 | &xcm_prty1_k2, &xcm_prty2_k2, | |
4263 | }; | |
4264 | ||
4265 | #ifdef ATTN_DESC | |
4266 | static const char *ycm_int_attn_desc[37] = { | |
4267 | "ycm_address_error", | |
4268 | "ycm_is_storm_ovfl_err", | |
4269 | "ycm_is_storm_under_err", | |
4270 | "ycm_is_msdm_ovfl_err", | |
4271 | "ycm_is_msdm_under_err", | |
4272 | "ycm_is_ysdm_ovfl_err", | |
4273 | "ycm_is_ysdm_under_err", | |
4274 | "ycm_is_xyld_ovfl_err", | |
4275 | "ycm_is_xyld_under_err", | |
4276 | "ycm_is_msem_ovfl_err", | |
4277 | "ycm_is_msem_under_err", | |
4278 | "ycm_is_usem_ovfl_err", | |
4279 | "ycm_is_usem_under_err", | |
4280 | "ycm_is_pbf_ovfl_err", | |
4281 | "ycm_is_pbf_under_err", | |
4282 | "ycm_is_qm_p_ovfl_err", | |
4283 | "ycm_is_qm_p_under_err", | |
4284 | "ycm_is_qm_s_ovfl_err", | |
4285 | "ycm_is_qm_s_under_err", | |
4286 | "ycm_is_grc_ovfl_err0", | |
4287 | "ycm_is_grc_under_err0", | |
4288 | "ycm_is_grc_ovfl_err1", | |
4289 | "ycm_is_grc_under_err1", | |
4290 | "ycm_is_grc_ovfl_err2", | |
4291 | "ycm_is_grc_under_err2", | |
4292 | "ycm_is_grc_ovfl_err3", | |
4293 | "ycm_is_grc_under_err3", | |
4294 | "ycm_in_prcs_tbl_ovfl", | |
4295 | "ycm_sm_con_data_buf_ovfl", | |
4296 | "ycm_sm_con_cmd_buf_ovfl", | |
4297 | "ycm_agg_task_data_buf_ovfl", | |
4298 | "ycm_agg_task_cmd_buf_ovfl", | |
4299 | "ycm_sm_task_data_buf_ovfl", | |
4300 | "ycm_sm_task_cmd_buf_ovfl", | |
4301 | "ycm_fi_desc_input_violate", | |
4302 | "ycm_se_desc_input_violate", | |
4303 | "ycm_qmreg_more4", | |
4304 | }; | |
4305 | #else | |
4306 | #define ycm_int_attn_desc OSAL_NULL | |
4307 | #endif | |
4308 | ||
4309 | static const u16 ycm_int0_bb_a0_attn_idx[13] = { | |
4310 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, | |
4311 | }; | |
4312 | ||
4313 | static struct attn_hw_reg ycm_int0_bb_a0 = { | |
4314 | 0, 13, ycm_int0_bb_a0_attn_idx, 0x1080180, 0x108018c, 0x1080188, | |
4315 | 0x1080184 | |
4316 | }; | |
4317 | ||
4318 | static const u16 ycm_int1_bb_a0_attn_idx[23] = { | |
4319 | 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, | |
4320 | 31, 32, 33, 34, 35, | |
4321 | }; | |
4322 | ||
4323 | static struct attn_hw_reg ycm_int1_bb_a0 = { | |
4324 | 1, 23, ycm_int1_bb_a0_attn_idx, 0x1080190, 0x108019c, 0x1080198, | |
4325 | 0x1080194 | |
4326 | }; | |
4327 | ||
4328 | static const u16 ycm_int2_bb_a0_attn_idx[1] = { | |
4329 | 36, | |
4330 | }; | |
4331 | ||
4332 | static struct attn_hw_reg ycm_int2_bb_a0 = { | |
4333 | 2, 1, ycm_int2_bb_a0_attn_idx, 0x10801a0, 0x10801ac, 0x10801a8, | |
4334 | 0x10801a4 | |
4335 | }; | |
4336 | ||
4337 | static struct attn_hw_reg *ycm_int_bb_a0_regs[3] = { | |
4338 | &ycm_int0_bb_a0, &ycm_int1_bb_a0, &ycm_int2_bb_a0, | |
4339 | }; | |
4340 | ||
4341 | static const u16 ycm_int0_bb_b0_attn_idx[13] = { | |
4342 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, | |
4343 | }; | |
4344 | ||
4345 | static struct attn_hw_reg ycm_int0_bb_b0 = { | |
4346 | 0, 13, ycm_int0_bb_b0_attn_idx, 0x1080180, 0x108018c, 0x1080188, | |
4347 | 0x1080184 | |
4348 | }; | |
4349 | ||
4350 | static const u16 ycm_int1_bb_b0_attn_idx[23] = { | |
4351 | 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, | |
4352 | 31, 32, 33, 34, 35, | |
4353 | }; | |
4354 | ||
4355 | static struct attn_hw_reg ycm_int1_bb_b0 = { | |
4356 | 1, 23, ycm_int1_bb_b0_attn_idx, 0x1080190, 0x108019c, 0x1080198, | |
4357 | 0x1080194 | |
4358 | }; | |
4359 | ||
4360 | static const u16 ycm_int2_bb_b0_attn_idx[1] = { | |
4361 | 36, | |
4362 | }; | |
4363 | ||
4364 | static struct attn_hw_reg ycm_int2_bb_b0 = { | |
4365 | 2, 1, ycm_int2_bb_b0_attn_idx, 0x10801a0, 0x10801ac, 0x10801a8, | |
4366 | 0x10801a4 | |
4367 | }; | |
4368 | ||
4369 | static struct attn_hw_reg *ycm_int_bb_b0_regs[3] = { | |
4370 | &ycm_int0_bb_b0, &ycm_int1_bb_b0, &ycm_int2_bb_b0, | |
4371 | }; | |
4372 | ||
4373 | static const u16 ycm_int0_k2_attn_idx[13] = { | |
4374 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, | |
4375 | }; | |
4376 | ||
4377 | static struct attn_hw_reg ycm_int0_k2 = { | |
4378 | 0, 13, ycm_int0_k2_attn_idx, 0x1080180, 0x108018c, 0x1080188, 0x1080184 | |
4379 | }; | |
4380 | ||
4381 | static const u16 ycm_int1_k2_attn_idx[23] = { | |
4382 | 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, | |
4383 | 31, 32, 33, 34, 35, | |
4384 | }; | |
4385 | ||
4386 | static struct attn_hw_reg ycm_int1_k2 = { | |
4387 | 1, 23, ycm_int1_k2_attn_idx, 0x1080190, 0x108019c, 0x1080198, 0x1080194 | |
4388 | }; | |
4389 | ||
4390 | static const u16 ycm_int2_k2_attn_idx[1] = { | |
4391 | 36, | |
4392 | }; | |
4393 | ||
4394 | static struct attn_hw_reg ycm_int2_k2 = { | |
4395 | 2, 1, ycm_int2_k2_attn_idx, 0x10801a0, 0x10801ac, 0x10801a8, 0x10801a4 | |
4396 | }; | |
4397 | ||
4398 | static struct attn_hw_reg *ycm_int_k2_regs[3] = { | |
4399 | &ycm_int0_k2, &ycm_int1_k2, &ycm_int2_k2, | |
4400 | }; | |
4401 | ||
4402 | #ifdef ATTN_DESC | |
4403 | static const char *ycm_prty_attn_desc[44] = { | |
4404 | "ycm_mem027_i_ecc_rf_int", | |
4405 | "ycm_mem003_i_ecc_0_rf_int", | |
4406 | "ycm_mem003_i_ecc_1_rf_int", | |
4407 | "ycm_mem022_i_ecc_0_rf_int", | |
4408 | "ycm_mem022_i_ecc_1_rf_int", | |
4409 | "ycm_mem023_i_ecc_rf_int", | |
4410 | "ycm_mem005_i_ecc_0_rf_int", | |
4411 | "ycm_mem005_i_ecc_1_rf_int", | |
4412 | "ycm_mem025_i_ecc_0_rf_int", | |
4413 | "ycm_mem025_i_ecc_1_rf_int", | |
4414 | "ycm_mem018_i_mem_prty", | |
4415 | "ycm_mem020_i_mem_prty", | |
4416 | "ycm_mem017_i_mem_prty", | |
4417 | "ycm_mem016_i_mem_prty", | |
4418 | "ycm_mem019_i_mem_prty", | |
4419 | "ycm_mem015_i_mem_prty", | |
4420 | "ycm_mem011_i_mem_prty", | |
4421 | "ycm_mem012_i_mem_prty", | |
4422 | "ycm_mem013_i_mem_prty", | |
4423 | "ycm_mem014_i_mem_prty", | |
4424 | "ycm_mem030_i_mem_prty", | |
4425 | "ycm_mem029_i_mem_prty", | |
4426 | "ycm_mem028_i_mem_prty", | |
4427 | "ycm_mem004_i_mem_prty", | |
4428 | "ycm_mem024_i_mem_prty", | |
4429 | "ycm_mem006_i_mem_prty", | |
4430 | "ycm_mem026_i_mem_prty", | |
4431 | "ycm_mem021_i_mem_prty", | |
4432 | "ycm_mem007_i_mem_prty_0", | |
4433 | "ycm_mem007_i_mem_prty_1", | |
4434 | "ycm_mem008_i_mem_prty", | |
4435 | "ycm_mem026_i_ecc_rf_int", | |
4436 | "ycm_mem021_i_ecc_0_rf_int", | |
4437 | "ycm_mem021_i_ecc_1_rf_int", | |
4438 | "ycm_mem022_i_ecc_rf_int", | |
4439 | "ycm_mem024_i_ecc_0_rf_int", | |
4440 | "ycm_mem024_i_ecc_1_rf_int", | |
4441 | "ycm_mem027_i_mem_prty", | |
4442 | "ycm_mem023_i_mem_prty", | |
4443 | "ycm_mem025_i_mem_prty", | |
4444 | "ycm_mem009_i_mem_prty", | |
4445 | "ycm_mem010_i_mem_prty", | |
4446 | "ycm_mem001_i_mem_prty", | |
4447 | "ycm_mem002_i_mem_prty", | |
4448 | }; | |
4449 | #else | |
4450 | #define ycm_prty_attn_desc OSAL_NULL | |
4451 | #endif | |
4452 | ||
4453 | static const u16 ycm_prty1_bb_a0_attn_idx[31] = { | |
4454 | 1, 2, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21, 22, 23, 25, 28, | |
4455 | 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, | |
4456 | }; | |
4457 | ||
4458 | static struct attn_hw_reg ycm_prty1_bb_a0 = { | |
4459 | 0, 31, ycm_prty1_bb_a0_attn_idx, 0x1080200, 0x108020c, 0x1080208, | |
4460 | 0x1080204 | |
4461 | }; | |
4462 | ||
4463 | static const u16 ycm_prty2_bb_a0_attn_idx[3] = { | |
4464 | 41, 42, 43, | |
4465 | }; | |
4466 | ||
4467 | static struct attn_hw_reg ycm_prty2_bb_a0 = { | |
4468 | 1, 3, ycm_prty2_bb_a0_attn_idx, 0x1080210, 0x108021c, 0x1080218, | |
4469 | 0x1080214 | |
4470 | }; | |
4471 | ||
4472 | static struct attn_hw_reg *ycm_prty_bb_a0_regs[2] = { | |
4473 | &ycm_prty1_bb_a0, &ycm_prty2_bb_a0, | |
4474 | }; | |
4475 | ||
4476 | static const u16 ycm_prty1_bb_b0_attn_idx[31] = { | |
4477 | 1, 2, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21, 22, 23, 25, 28, | |
4478 | 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, | |
4479 | }; | |
4480 | ||
4481 | static struct attn_hw_reg ycm_prty1_bb_b0 = { | |
4482 | 0, 31, ycm_prty1_bb_b0_attn_idx, 0x1080200, 0x108020c, 0x1080208, | |
4483 | 0x1080204 | |
4484 | }; | |
4485 | ||
4486 | static const u16 ycm_prty2_bb_b0_attn_idx[3] = { | |
4487 | 41, 42, 43, | |
4488 | }; | |
4489 | ||
4490 | static struct attn_hw_reg ycm_prty2_bb_b0 = { | |
4491 | 1, 3, ycm_prty2_bb_b0_attn_idx, 0x1080210, 0x108021c, 0x1080218, | |
4492 | 0x1080214 | |
4493 | }; | |
4494 | ||
4495 | static struct attn_hw_reg *ycm_prty_bb_b0_regs[2] = { | |
4496 | &ycm_prty1_bb_b0, &ycm_prty2_bb_b0, | |
4497 | }; | |
4498 | ||
4499 | static const u16 ycm_prty1_k2_attn_idx[31] = { | |
4500 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
4501 | 20, | |
4502 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, | |
4503 | }; | |
4504 | ||
4505 | static struct attn_hw_reg ycm_prty1_k2 = { | |
4506 | 0, 31, ycm_prty1_k2_attn_idx, 0x1080200, 0x108020c, 0x1080208, | |
4507 | 0x1080204 | |
4508 | }; | |
4509 | ||
4510 | static const u16 ycm_prty2_k2_attn_idx[4] = { | |
4511 | 40, 41, 42, 43, | |
4512 | }; | |
4513 | ||
4514 | static struct attn_hw_reg ycm_prty2_k2 = { | |
4515 | 1, 4, ycm_prty2_k2_attn_idx, 0x1080210, 0x108021c, 0x1080218, 0x1080214 | |
4516 | }; | |
4517 | ||
4518 | static struct attn_hw_reg *ycm_prty_k2_regs[2] = { | |
4519 | &ycm_prty1_k2, &ycm_prty2_k2, | |
4520 | }; | |
4521 | ||
4522 | #ifdef ATTN_DESC | |
4523 | static const char *pcm_int_attn_desc[20] = { | |
4524 | "pcm_address_error", | |
4525 | "pcm_is_storm_ovfl_err", | |
4526 | "pcm_is_storm_under_err", | |
4527 | "pcm_is_psdm_ovfl_err", | |
4528 | "pcm_is_psdm_under_err", | |
4529 | "pcm_is_pbf_ovfl_err", | |
4530 | "pcm_is_pbf_under_err", | |
4531 | "pcm_is_grc_ovfl_err0", | |
4532 | "pcm_is_grc_under_err0", | |
4533 | "pcm_is_grc_ovfl_err1", | |
4534 | "pcm_is_grc_under_err1", | |
4535 | "pcm_is_grc_ovfl_err2", | |
4536 | "pcm_is_grc_under_err2", | |
4537 | "pcm_is_grc_ovfl_err3", | |
4538 | "pcm_is_grc_under_err3", | |
4539 | "pcm_in_prcs_tbl_ovfl", | |
4540 | "pcm_sm_con_data_buf_ovfl", | |
4541 | "pcm_sm_con_cmd_buf_ovfl", | |
4542 | "pcm_fi_desc_input_violate", | |
4543 | "pcm_qmreg_more4", | |
4544 | }; | |
4545 | #else | |
4546 | #define pcm_int_attn_desc OSAL_NULL | |
4547 | #endif | |
4548 | ||
4549 | static const u16 pcm_int0_bb_a0_attn_idx[5] = { | |
4550 | 0, 1, 2, 3, 4, | |
4551 | }; | |
4552 | ||
4553 | static struct attn_hw_reg pcm_int0_bb_a0 = { | |
4554 | 0, 5, pcm_int0_bb_a0_attn_idx, 0x1100180, 0x110018c, 0x1100188, | |
4555 | 0x1100184 | |
4556 | }; | |
4557 | ||
4558 | static const u16 pcm_int1_bb_a0_attn_idx[14] = { | |
4559 | 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, | |
4560 | }; | |
4561 | ||
4562 | static struct attn_hw_reg pcm_int1_bb_a0 = { | |
4563 | 1, 14, pcm_int1_bb_a0_attn_idx, 0x1100190, 0x110019c, 0x1100198, | |
4564 | 0x1100194 | |
4565 | }; | |
4566 | ||
4567 | static const u16 pcm_int2_bb_a0_attn_idx[1] = { | |
4568 | 19, | |
4569 | }; | |
4570 | ||
4571 | static struct attn_hw_reg pcm_int2_bb_a0 = { | |
4572 | 2, 1, pcm_int2_bb_a0_attn_idx, 0x11001a0, 0x11001ac, 0x11001a8, | |
4573 | 0x11001a4 | |
4574 | }; | |
4575 | ||
4576 | static struct attn_hw_reg *pcm_int_bb_a0_regs[3] = { | |
4577 | &pcm_int0_bb_a0, &pcm_int1_bb_a0, &pcm_int2_bb_a0, | |
4578 | }; | |
4579 | ||
4580 | static const u16 pcm_int0_bb_b0_attn_idx[5] = { | |
4581 | 0, 1, 2, 3, 4, | |
4582 | }; | |
4583 | ||
4584 | static struct attn_hw_reg pcm_int0_bb_b0 = { | |
4585 | 0, 5, pcm_int0_bb_b0_attn_idx, 0x1100180, 0x110018c, 0x1100188, | |
4586 | 0x1100184 | |
4587 | }; | |
4588 | ||
4589 | static const u16 pcm_int1_bb_b0_attn_idx[14] = { | |
4590 | 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, | |
4591 | }; | |
4592 | ||
4593 | static struct attn_hw_reg pcm_int1_bb_b0 = { | |
4594 | 1, 14, pcm_int1_bb_b0_attn_idx, 0x1100190, 0x110019c, 0x1100198, | |
4595 | 0x1100194 | |
4596 | }; | |
4597 | ||
4598 | static const u16 pcm_int2_bb_b0_attn_idx[1] = { | |
4599 | 19, | |
4600 | }; | |
4601 | ||
4602 | static struct attn_hw_reg pcm_int2_bb_b0 = { | |
4603 | 2, 1, pcm_int2_bb_b0_attn_idx, 0x11001a0, 0x11001ac, 0x11001a8, | |
4604 | 0x11001a4 | |
4605 | }; | |
4606 | ||
4607 | static struct attn_hw_reg *pcm_int_bb_b0_regs[3] = { | |
4608 | &pcm_int0_bb_b0, &pcm_int1_bb_b0, &pcm_int2_bb_b0, | |
4609 | }; | |
4610 | ||
4611 | static const u16 pcm_int0_k2_attn_idx[5] = { | |
4612 | 0, 1, 2, 3, 4, | |
4613 | }; | |
4614 | ||
4615 | static struct attn_hw_reg pcm_int0_k2 = { | |
4616 | 0, 5, pcm_int0_k2_attn_idx, 0x1100180, 0x110018c, 0x1100188, 0x1100184 | |
4617 | }; | |
4618 | ||
4619 | static const u16 pcm_int1_k2_attn_idx[14] = { | |
4620 | 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, | |
4621 | }; | |
4622 | ||
4623 | static struct attn_hw_reg pcm_int1_k2 = { | |
4624 | 1, 14, pcm_int1_k2_attn_idx, 0x1100190, 0x110019c, 0x1100198, 0x1100194 | |
4625 | }; | |
4626 | ||
4627 | static const u16 pcm_int2_k2_attn_idx[1] = { | |
4628 | 19, | |
4629 | }; | |
4630 | ||
4631 | static struct attn_hw_reg pcm_int2_k2 = { | |
4632 | 2, 1, pcm_int2_k2_attn_idx, 0x11001a0, 0x11001ac, 0x11001a8, 0x11001a4 | |
4633 | }; | |
4634 | ||
4635 | static struct attn_hw_reg *pcm_int_k2_regs[3] = { | |
4636 | &pcm_int0_k2, &pcm_int1_k2, &pcm_int2_k2, | |
4637 | }; | |
4638 | ||
4639 | #ifdef ATTN_DESC | |
4640 | static const char *pcm_prty_attn_desc[18] = { | |
4641 | "pcm_mem012_i_ecc_rf_int", | |
4642 | "pcm_mem010_i_ecc_0_rf_int", | |
4643 | "pcm_mem010_i_ecc_1_rf_int", | |
4644 | "pcm_mem008_i_mem_prty", | |
4645 | "pcm_mem007_i_mem_prty", | |
4646 | "pcm_mem006_i_mem_prty", | |
4647 | "pcm_mem002_i_mem_prty", | |
4648 | "pcm_mem003_i_mem_prty", | |
4649 | "pcm_mem004_i_mem_prty", | |
4650 | "pcm_mem005_i_mem_prty", | |
4651 | "pcm_mem011_i_mem_prty", | |
4652 | "pcm_mem001_i_mem_prty", | |
4653 | "pcm_mem011_i_ecc_rf_int", | |
4654 | "pcm_mem009_i_ecc_0_rf_int", | |
4655 | "pcm_mem009_i_ecc_1_rf_int", | |
4656 | "pcm_mem010_i_mem_prty", | |
4657 | "pcm_mem013_i_mem_prty", | |
4658 | "pcm_mem012_i_mem_prty", | |
4659 | }; | |
4660 | #else | |
4661 | #define pcm_prty_attn_desc OSAL_NULL | |
4662 | #endif | |
4663 | ||
4664 | static const u16 pcm_prty1_bb_a0_attn_idx[14] = { | |
4665 | 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, | |
4666 | }; | |
4667 | ||
4668 | static struct attn_hw_reg pcm_prty1_bb_a0 = { | |
4669 | 0, 14, pcm_prty1_bb_a0_attn_idx, 0x1100200, 0x110020c, 0x1100208, | |
4670 | 0x1100204 | |
4671 | }; | |
4672 | ||
4673 | static struct attn_hw_reg *pcm_prty_bb_a0_regs[1] = { | |
4674 | &pcm_prty1_bb_a0, | |
4675 | }; | |
4676 | ||
4677 | static const u16 pcm_prty1_bb_b0_attn_idx[11] = { | |
4678 | 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, | |
4679 | }; | |
4680 | ||
4681 | static struct attn_hw_reg pcm_prty1_bb_b0 = { | |
4682 | 0, 11, pcm_prty1_bb_b0_attn_idx, 0x1100200, 0x110020c, 0x1100208, | |
4683 | 0x1100204 | |
4684 | }; | |
4685 | ||
4686 | static struct attn_hw_reg *pcm_prty_bb_b0_regs[1] = { | |
4687 | &pcm_prty1_bb_b0, | |
4688 | }; | |
4689 | ||
4690 | static const u16 pcm_prty1_k2_attn_idx[12] = { | |
4691 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, | |
4692 | }; | |
4693 | ||
4694 | static struct attn_hw_reg pcm_prty1_k2 = { | |
4695 | 0, 12, pcm_prty1_k2_attn_idx, 0x1100200, 0x110020c, 0x1100208, | |
4696 | 0x1100204 | |
4697 | }; | |
4698 | ||
4699 | static struct attn_hw_reg *pcm_prty_k2_regs[1] = { | |
4700 | &pcm_prty1_k2, | |
4701 | }; | |
4702 | ||
4703 | #ifdef ATTN_DESC | |
4704 | static const char *qm_int_attn_desc[22] = { | |
4705 | "qm_address_error", | |
4706 | "qm_ovf_err_tx", | |
4707 | "qm_ovf_err_other", | |
4708 | "qm_pf_usg_cnt_err", | |
4709 | "qm_vf_usg_cnt_err", | |
4710 | "qm_voq_crd_inc_err", | |
4711 | "qm_voq_crd_dec_err", | |
4712 | "qm_byte_crd_inc_err", | |
4713 | "qm_byte_crd_dec_err", | |
4714 | "qm_err_incdec_rlglblcrd", | |
4715 | "qm_err_incdec_rlpfcrd", | |
4716 | "qm_err_incdec_wfqpfcrd", | |
4717 | "qm_err_incdec_wfqvpcrd", | |
4718 | "qm_err_incdec_voqlinecrd", | |
4719 | "qm_err_incdec_voqbytecrd", | |
4720 | "qm_fifos_error", | |
4721 | "qm_qm_rl_dc_exp_pf_controller_pop_error", | |
4722 | "qm_qm_rl_dc_exp_pf_controller_push_error", | |
4723 | "qm_qm_rl_dc_rf_req_controller_pop_error", | |
4724 | "qm_qm_rl_dc_rf_req_controller_push_error", | |
4725 | "qm_qm_rl_dc_rf_res_controller_pop_error", | |
4726 | "qm_qm_rl_dc_rf_res_controller_push_error", | |
4727 | }; | |
4728 | #else | |
4729 | #define qm_int_attn_desc OSAL_NULL | |
4730 | #endif | |
4731 | ||
4732 | static const u16 qm_int0_bb_a0_attn_idx[16] = { | |
4733 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, | |
4734 | }; | |
4735 | ||
4736 | static struct attn_hw_reg qm_int0_bb_a0 = { | |
4737 | 0, 16, qm_int0_bb_a0_attn_idx, 0x2f0180, 0x2f018c, 0x2f0188, 0x2f0184 | |
4738 | }; | |
4739 | ||
4740 | static struct attn_hw_reg *qm_int_bb_a0_regs[1] = { | |
4741 | &qm_int0_bb_a0, | |
4742 | }; | |
4743 | ||
4744 | static const u16 qm_int0_bb_b0_attn_idx[22] = { | |
4745 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
4746 | 20, | |
4747 | 21, | |
4748 | }; | |
4749 | ||
4750 | static struct attn_hw_reg qm_int0_bb_b0 = { | |
4751 | 0, 22, qm_int0_bb_b0_attn_idx, 0x2f0180, 0x2f018c, 0x2f0188, 0x2f0184 | |
4752 | }; | |
4753 | ||
4754 | static struct attn_hw_reg *qm_int_bb_b0_regs[1] = { | |
4755 | &qm_int0_bb_b0, | |
4756 | }; | |
4757 | ||
4758 | static const u16 qm_int0_k2_attn_idx[22] = { | |
4759 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
4760 | 20, | |
4761 | 21, | |
4762 | }; | |
4763 | ||
4764 | static struct attn_hw_reg qm_int0_k2 = { | |
4765 | 0, 22, qm_int0_k2_attn_idx, 0x2f0180, 0x2f018c, 0x2f0188, 0x2f0184 | |
4766 | }; | |
4767 | ||
4768 | static struct attn_hw_reg *qm_int_k2_regs[1] = { | |
4769 | &qm_int0_k2, | |
4770 | }; | |
4771 | ||
4772 | #ifdef ATTN_DESC | |
4773 | static const char *qm_prty_attn_desc[109] = { | |
4774 | "qm_xcm_wrc_fifo", | |
4775 | "qm_ucm_wrc_fifo", | |
4776 | "qm_tcm_wrc_fifo", | |
4777 | "qm_ccm_wrc_fifo", | |
4778 | "qm_bigramhigh", | |
4779 | "qm_bigramlow", | |
4780 | "qm_base_address", | |
4781 | "qm_wrbuff", | |
4782 | "qm_bigramhigh_ext_a", | |
4783 | "qm_bigramlow_ext_a", | |
4784 | "qm_base_address_ext_a", | |
4785 | "qm_mem006_i_ecc_0_rf_int", | |
4786 | "qm_mem006_i_ecc_1_rf_int", | |
4787 | "qm_mem005_i_ecc_0_rf_int", | |
4788 | "qm_mem005_i_ecc_1_rf_int", | |
4789 | "qm_mem012_i_ecc_rf_int", | |
4790 | "qm_mem037_i_mem_prty", | |
4791 | "qm_mem036_i_mem_prty", | |
4792 | "qm_mem039_i_mem_prty", | |
4793 | "qm_mem038_i_mem_prty", | |
4794 | "qm_mem040_i_mem_prty", | |
4795 | "qm_mem042_i_mem_prty", | |
4796 | "qm_mem041_i_mem_prty", | |
4797 | "qm_mem056_i_mem_prty", | |
4798 | "qm_mem055_i_mem_prty", | |
4799 | "qm_mem053_i_mem_prty", | |
4800 | "qm_mem054_i_mem_prty", | |
4801 | "qm_mem057_i_mem_prty", | |
4802 | "qm_mem058_i_mem_prty", | |
4803 | "qm_mem062_i_mem_prty", | |
4804 | "qm_mem061_i_mem_prty", | |
4805 | "qm_mem059_i_mem_prty", | |
4806 | "qm_mem060_i_mem_prty", | |
4807 | "qm_mem063_i_mem_prty", | |
4808 | "qm_mem064_i_mem_prty", | |
4809 | "qm_mem033_i_mem_prty", | |
4810 | "qm_mem032_i_mem_prty", | |
4811 | "qm_mem030_i_mem_prty", | |
4812 | "qm_mem031_i_mem_prty", | |
4813 | "qm_mem034_i_mem_prty", | |
4814 | "qm_mem035_i_mem_prty", | |
4815 | "qm_mem051_i_mem_prty", | |
4816 | "qm_mem042_i_ecc_0_rf_int", | |
4817 | "qm_mem042_i_ecc_1_rf_int", | |
4818 | "qm_mem041_i_ecc_0_rf_int", | |
4819 | "qm_mem041_i_ecc_1_rf_int", | |
4820 | "qm_mem048_i_ecc_rf_int", | |
4821 | "qm_mem009_i_mem_prty", | |
4822 | "qm_mem008_i_mem_prty", | |
4823 | "qm_mem011_i_mem_prty", | |
4824 | "qm_mem010_i_mem_prty", | |
4825 | "qm_mem012_i_mem_prty", | |
4826 | "qm_mem014_i_mem_prty", | |
4827 | "qm_mem013_i_mem_prty", | |
4828 | "qm_mem028_i_mem_prty", | |
4829 | "qm_mem027_i_mem_prty", | |
4830 | "qm_mem025_i_mem_prty", | |
4831 | "qm_mem026_i_mem_prty", | |
4832 | "qm_mem029_i_mem_prty", | |
4833 | "qm_mem005_i_mem_prty", | |
4834 | "qm_mem004_i_mem_prty", | |
4835 | "qm_mem002_i_mem_prty", | |
4836 | "qm_mem003_i_mem_prty", | |
4837 | "qm_mem006_i_mem_prty", | |
4838 | "qm_mem007_i_mem_prty", | |
4839 | "qm_mem023_i_mem_prty", | |
4840 | "qm_mem047_i_mem_prty", | |
4841 | "qm_mem049_i_mem_prty", | |
4842 | "qm_mem048_i_mem_prty", | |
4843 | "qm_mem052_i_mem_prty", | |
4844 | "qm_mem050_i_mem_prty", | |
4845 | "qm_mem045_i_mem_prty", | |
4846 | "qm_mem046_i_mem_prty", | |
4847 | "qm_mem043_i_mem_prty", | |
4848 | "qm_mem044_i_mem_prty", | |
4849 | "qm_mem017_i_mem_prty", | |
4850 | "qm_mem016_i_mem_prty", | |
4851 | "qm_mem021_i_mem_prty", | |
4852 | "qm_mem024_i_mem_prty", | |
4853 | "qm_mem019_i_mem_prty", | |
4854 | "qm_mem018_i_mem_prty", | |
4855 | "qm_mem015_i_mem_prty", | |
4856 | "qm_mem022_i_mem_prty", | |
4857 | "qm_mem020_i_mem_prty", | |
4858 | "qm_mem007_i_mem_prty_0", | |
4859 | "qm_mem007_i_mem_prty_1", | |
4860 | "qm_mem007_i_mem_prty_2", | |
4861 | "qm_mem001_i_mem_prty", | |
4862 | "qm_mem043_i_mem_prty_0", | |
4863 | "qm_mem043_i_mem_prty_1", | |
4864 | "qm_mem043_i_mem_prty_2", | |
4865 | "qm_mem007_i_mem_prty_3", | |
4866 | "qm_mem007_i_mem_prty_4", | |
4867 | "qm_mem007_i_mem_prty_5", | |
4868 | "qm_mem007_i_mem_prty_6", | |
4869 | "qm_mem007_i_mem_prty_7", | |
4870 | "qm_mem007_i_mem_prty_8", | |
4871 | "qm_mem007_i_mem_prty_9", | |
4872 | "qm_mem007_i_mem_prty_10", | |
4873 | "qm_mem007_i_mem_prty_11", | |
4874 | "qm_mem007_i_mem_prty_12", | |
4875 | "qm_mem007_i_mem_prty_13", | |
4876 | "qm_mem007_i_mem_prty_14", | |
4877 | "qm_mem007_i_mem_prty_15", | |
4878 | "qm_mem043_i_mem_prty_3", | |
4879 | "qm_mem043_i_mem_prty_4", | |
4880 | "qm_mem043_i_mem_prty_5", | |
4881 | "qm_mem043_i_mem_prty_6", | |
4882 | "qm_mem043_i_mem_prty_7", | |
4883 | }; | |
4884 | #else | |
4885 | #define qm_prty_attn_desc OSAL_NULL | |
4886 | #endif | |
4887 | ||
4888 | static const u16 qm_prty0_bb_a0_attn_idx[11] = { | |
4889 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, | |
4890 | }; | |
4891 | ||
4892 | static struct attn_hw_reg qm_prty0_bb_a0 = { | |
4893 | 0, 11, qm_prty0_bb_a0_attn_idx, 0x2f0190, 0x2f019c, 0x2f0198, 0x2f0194 | |
4894 | }; | |
4895 | ||
4896 | static const u16 qm_prty1_bb_a0_attn_idx[31] = { | |
4897 | 17, 35, 36, 37, 38, 39, 40, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, | |
4898 | 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, | |
4899 | }; | |
4900 | ||
4901 | static struct attn_hw_reg qm_prty1_bb_a0 = { | |
4902 | 1, 31, qm_prty1_bb_a0_attn_idx, 0x2f0200, 0x2f020c, 0x2f0208, 0x2f0204 | |
4903 | }; | |
4904 | ||
4905 | static const u16 qm_prty2_bb_a0_attn_idx[31] = { | |
4906 | 66, 67, 69, 70, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 87, 20, 18, 25, | |
4907 | 27, 32, 24, 26, 41, 31, 29, 28, 30, 23, 88, 89, 90, | |
4908 | }; | |
4909 | ||
4910 | static struct attn_hw_reg qm_prty2_bb_a0 = { | |
4911 | 2, 31, qm_prty2_bb_a0_attn_idx, 0x2f0210, 0x2f021c, 0x2f0218, 0x2f0214 | |
4912 | }; | |
4913 | ||
4914 | static const u16 qm_prty3_bb_a0_attn_idx[11] = { | |
4915 | 104, 105, 106, 107, 108, 33, 16, 34, 19, 72, 71, | |
4916 | }; | |
4917 | ||
4918 | static struct attn_hw_reg qm_prty3_bb_a0 = { | |
4919 | 3, 11, qm_prty3_bb_a0_attn_idx, 0x2f0220, 0x2f022c, 0x2f0228, 0x2f0224 | |
4920 | }; | |
4921 | ||
4922 | static struct attn_hw_reg *qm_prty_bb_a0_regs[4] = { | |
4923 | &qm_prty0_bb_a0, &qm_prty1_bb_a0, &qm_prty2_bb_a0, &qm_prty3_bb_a0, | |
4924 | }; | |
4925 | ||
4926 | static const u16 qm_prty0_bb_b0_attn_idx[11] = { | |
4927 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, | |
4928 | }; | |
4929 | ||
4930 | static struct attn_hw_reg qm_prty0_bb_b0 = { | |
4931 | 0, 11, qm_prty0_bb_b0_attn_idx, 0x2f0190, 0x2f019c, 0x2f0198, 0x2f0194 | |
4932 | }; | |
4933 | ||
4934 | static const u16 qm_prty1_bb_b0_attn_idx[31] = { | |
4935 | 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, | |
4936 | 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, | |
4937 | }; | |
4938 | ||
4939 | static struct attn_hw_reg qm_prty1_bb_b0 = { | |
4940 | 1, 31, qm_prty1_bb_b0_attn_idx, 0x2f0200, 0x2f020c, 0x2f0208, 0x2f0204 | |
4941 | }; | |
4942 | ||
4943 | static const u16 qm_prty2_bb_b0_attn_idx[31] = { | |
4944 | 66, 67, 68, 69, 70, 71, 72, 73, 74, 58, 60, 62, 49, 75, 76, 53, 77, 78, | |
4945 | 79, 80, 81, 52, 65, 57, 82, 56, 83, 48, 84, 85, 86, | |
4946 | }; | |
4947 | ||
4948 | static struct attn_hw_reg qm_prty2_bb_b0 = { | |
4949 | 2, 31, qm_prty2_bb_b0_attn_idx, 0x2f0210, 0x2f021c, 0x2f0218, 0x2f0214 | |
4950 | }; | |
4951 | ||
4952 | static const u16 qm_prty3_bb_b0_attn_idx[11] = { | |
4953 | 91, 92, 93, 94, 95, 55, 87, 54, 61, 50, 47, | |
4954 | }; | |
4955 | ||
4956 | static struct attn_hw_reg qm_prty3_bb_b0 = { | |
4957 | 3, 11, qm_prty3_bb_b0_attn_idx, 0x2f0220, 0x2f022c, 0x2f0228, 0x2f0224 | |
4958 | }; | |
4959 | ||
4960 | static struct attn_hw_reg *qm_prty_bb_b0_regs[4] = { | |
4961 | &qm_prty0_bb_b0, &qm_prty1_bb_b0, &qm_prty2_bb_b0, &qm_prty3_bb_b0, | |
4962 | }; | |
4963 | ||
4964 | static const u16 qm_prty0_k2_attn_idx[11] = { | |
4965 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, | |
4966 | }; | |
4967 | ||
4968 | static struct attn_hw_reg qm_prty0_k2 = { | |
4969 | 0, 11, qm_prty0_k2_attn_idx, 0x2f0190, 0x2f019c, 0x2f0198, 0x2f0194 | |
4970 | }; | |
4971 | ||
4972 | static const u16 qm_prty1_k2_attn_idx[31] = { | |
4973 | 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, | |
4974 | 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, | |
4975 | }; | |
4976 | ||
4977 | static struct attn_hw_reg qm_prty1_k2 = { | |
4978 | 1, 31, qm_prty1_k2_attn_idx, 0x2f0200, 0x2f020c, 0x2f0208, 0x2f0204 | |
4979 | }; | |
4980 | ||
4981 | static const u16 qm_prty2_k2_attn_idx[31] = { | |
4982 | 66, 67, 68, 69, 70, 71, 72, 73, 74, 58, 60, 62, 49, 75, 76, 53, 77, 78, | |
4983 | 79, 80, 81, 52, 65, 57, 82, 56, 83, 48, 84, 85, 86, | |
4984 | }; | |
4985 | ||
4986 | static struct attn_hw_reg qm_prty2_k2 = { | |
4987 | 2, 31, qm_prty2_k2_attn_idx, 0x2f0210, 0x2f021c, 0x2f0218, 0x2f0214 | |
4988 | }; | |
4989 | ||
4990 | static const u16 qm_prty3_k2_attn_idx[19] = { | |
4991 | 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 55, 87, 54, 61, | |
4992 | 50, 47, | |
4993 | }; | |
4994 | ||
4995 | static struct attn_hw_reg qm_prty3_k2 = { | |
4996 | 3, 19, qm_prty3_k2_attn_idx, 0x2f0220, 0x2f022c, 0x2f0228, 0x2f0224 | |
4997 | }; | |
4998 | ||
4999 | static struct attn_hw_reg *qm_prty_k2_regs[4] = { | |
5000 | &qm_prty0_k2, &qm_prty1_k2, &qm_prty2_k2, &qm_prty3_k2, | |
5001 | }; | |
5002 | ||
5003 | #ifdef ATTN_DESC | |
5004 | static const char *tm_int_attn_desc[43] = { | |
5005 | "tm_address_error", | |
5006 | "tm_pxp_read_data_fifo_ov", | |
5007 | "tm_pxp_read_data_fifo_un", | |
5008 | "tm_pxp_read_ctrl_fifo_ov", | |
5009 | "tm_pxp_read_ctrl_fifo_un", | |
5010 | "tm_cfc_load_command_fifo_ov", | |
5011 | "tm_cfc_load_command_fifo_un", | |
5012 | "tm_cfc_load_echo_fifo_ov", | |
5013 | "tm_cfc_load_echo_fifo_un", | |
5014 | "tm_client_out_fifo_ov", | |
5015 | "tm_client_out_fifo_un", | |
5016 | "tm_ac_command_fifo_ov", | |
5017 | "tm_ac_command_fifo_un", | |
5018 | "tm_client_in_pbf_fifo_ov", | |
5019 | "tm_client_in_pbf_fifo_un", | |
5020 | "tm_client_in_ucm_fifo_ov", | |
5021 | "tm_client_in_ucm_fifo_un", | |
5022 | "tm_client_in_tcm_fifo_ov", | |
5023 | "tm_client_in_tcm_fifo_un", | |
5024 | "tm_client_in_xcm_fifo_ov", | |
5025 | "tm_client_in_xcm_fifo_un", | |
5026 | "tm_expiration_cmd_fifo_ov", | |
5027 | "tm_expiration_cmd_fifo_un", | |
5028 | "tm_stop_all_lc_invalid", | |
5029 | "tm_command_lc_invalid_0", | |
5030 | "tm_command_lc_invalid_1", | |
5031 | "tm_init_command_lc_valid", | |
5032 | "tm_stop_all_exp_lc_valid", | |
5033 | "tm_command_cid_invalid_0", | |
5034 | "tm_reserved_command", | |
5035 | "tm_command_cid_invalid_1", | |
5036 | "tm_cload_res_loaderr_conn", | |
5037 | "tm_cload_res_loadcancel_conn", | |
5038 | "tm_cload_res_validerr_conn", | |
5039 | "tm_context_rd_last", | |
5040 | "tm_context_wr_last", | |
5041 | "tm_pxp_rd_data_eop_bvalid", | |
5042 | "tm_pend_conn_scan", | |
5043 | "tm_pend_task_scan", | |
5044 | "tm_pxp_rd_data_eop_error", | |
5045 | "tm_cload_res_loaderr_task", | |
5046 | "tm_cload_res_loadcancel_task", | |
5047 | "tm_cload_res_validerr_task", | |
5048 | }; | |
5049 | #else | |
5050 | #define tm_int_attn_desc OSAL_NULL | |
5051 | #endif | |
5052 | ||
5053 | static const u16 tm_int0_bb_a0_attn_idx[32] = { | |
5054 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
5055 | 20, | |
5056 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
5057 | }; | |
5058 | ||
5059 | static struct attn_hw_reg tm_int0_bb_a0 = { | |
5060 | 0, 32, tm_int0_bb_a0_attn_idx, 0x2c0180, 0x2c018c, 0x2c0188, 0x2c0184 | |
5061 | }; | |
5062 | ||
5063 | static const u16 tm_int1_bb_a0_attn_idx[11] = { | |
5064 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, | |
5065 | }; | |
5066 | ||
5067 | static struct attn_hw_reg tm_int1_bb_a0 = { | |
5068 | 1, 11, tm_int1_bb_a0_attn_idx, 0x2c0190, 0x2c019c, 0x2c0198, 0x2c0194 | |
5069 | }; | |
5070 | ||
5071 | static struct attn_hw_reg *tm_int_bb_a0_regs[2] = { | |
5072 | &tm_int0_bb_a0, &tm_int1_bb_a0, | |
5073 | }; | |
5074 | ||
5075 | static const u16 tm_int0_bb_b0_attn_idx[32] = { | |
5076 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
5077 | 20, | |
5078 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
5079 | }; | |
5080 | ||
5081 | static struct attn_hw_reg tm_int0_bb_b0 = { | |
5082 | 0, 32, tm_int0_bb_b0_attn_idx, 0x2c0180, 0x2c018c, 0x2c0188, 0x2c0184 | |
5083 | }; | |
5084 | ||
5085 | static const u16 tm_int1_bb_b0_attn_idx[11] = { | |
5086 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, | |
5087 | }; | |
5088 | ||
5089 | static struct attn_hw_reg tm_int1_bb_b0 = { | |
5090 | 1, 11, tm_int1_bb_b0_attn_idx, 0x2c0190, 0x2c019c, 0x2c0198, 0x2c0194 | |
5091 | }; | |
5092 | ||
5093 | static struct attn_hw_reg *tm_int_bb_b0_regs[2] = { | |
5094 | &tm_int0_bb_b0, &tm_int1_bb_b0, | |
5095 | }; | |
5096 | ||
5097 | static const u16 tm_int0_k2_attn_idx[32] = { | |
5098 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
5099 | 20, | |
5100 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
5101 | }; | |
5102 | ||
5103 | static struct attn_hw_reg tm_int0_k2 = { | |
5104 | 0, 32, tm_int0_k2_attn_idx, 0x2c0180, 0x2c018c, 0x2c0188, 0x2c0184 | |
5105 | }; | |
5106 | ||
5107 | static const u16 tm_int1_k2_attn_idx[11] = { | |
5108 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, | |
5109 | }; | |
5110 | ||
5111 | static struct attn_hw_reg tm_int1_k2 = { | |
5112 | 1, 11, tm_int1_k2_attn_idx, 0x2c0190, 0x2c019c, 0x2c0198, 0x2c0194 | |
5113 | }; | |
5114 | ||
5115 | static struct attn_hw_reg *tm_int_k2_regs[2] = { | |
5116 | &tm_int0_k2, &tm_int1_k2, | |
5117 | }; | |
5118 | ||
5119 | #ifdef ATTN_DESC | |
5120 | static const char *tm_prty_attn_desc[17] = { | |
5121 | "tm_mem012_i_ecc_0_rf_int", | |
5122 | "tm_mem012_i_ecc_1_rf_int", | |
5123 | "tm_mem003_i_ecc_rf_int", | |
5124 | "tm_mem016_i_mem_prty", | |
5125 | "tm_mem007_i_mem_prty", | |
5126 | "tm_mem010_i_mem_prty", | |
5127 | "tm_mem008_i_mem_prty", | |
5128 | "tm_mem009_i_mem_prty", | |
5129 | "tm_mem013_i_mem_prty", | |
5130 | "tm_mem015_i_mem_prty", | |
5131 | "tm_mem014_i_mem_prty", | |
5132 | "tm_mem004_i_mem_prty", | |
5133 | "tm_mem005_i_mem_prty", | |
5134 | "tm_mem006_i_mem_prty", | |
5135 | "tm_mem011_i_mem_prty", | |
5136 | "tm_mem001_i_mem_prty", | |
5137 | "tm_mem002_i_mem_prty", | |
5138 | }; | |
5139 | #else | |
5140 | #define tm_prty_attn_desc OSAL_NULL | |
5141 | #endif | |
5142 | ||
5143 | static const u16 tm_prty1_bb_a0_attn_idx[17] = { | |
5144 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, | |
5145 | }; | |
5146 | ||
5147 | static struct attn_hw_reg tm_prty1_bb_a0 = { | |
5148 | 0, 17, tm_prty1_bb_a0_attn_idx, 0x2c0200, 0x2c020c, 0x2c0208, 0x2c0204 | |
5149 | }; | |
5150 | ||
5151 | static struct attn_hw_reg *tm_prty_bb_a0_regs[1] = { | |
5152 | &tm_prty1_bb_a0, | |
5153 | }; | |
5154 | ||
5155 | static const u16 tm_prty1_bb_b0_attn_idx[17] = { | |
5156 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, | |
5157 | }; | |
5158 | ||
5159 | static struct attn_hw_reg tm_prty1_bb_b0 = { | |
5160 | 0, 17, tm_prty1_bb_b0_attn_idx, 0x2c0200, 0x2c020c, 0x2c0208, 0x2c0204 | |
5161 | }; | |
5162 | ||
5163 | static struct attn_hw_reg *tm_prty_bb_b0_regs[1] = { | |
5164 | &tm_prty1_bb_b0, | |
5165 | }; | |
5166 | ||
5167 | static const u16 tm_prty1_k2_attn_idx[17] = { | |
5168 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, | |
5169 | }; | |
5170 | ||
5171 | static struct attn_hw_reg tm_prty1_k2 = { | |
5172 | 0, 17, tm_prty1_k2_attn_idx, 0x2c0200, 0x2c020c, 0x2c0208, 0x2c0204 | |
5173 | }; | |
5174 | ||
5175 | static struct attn_hw_reg *tm_prty_k2_regs[1] = { | |
5176 | &tm_prty1_k2, | |
5177 | }; | |
5178 | ||
5179 | #ifdef ATTN_DESC | |
5180 | static const char *dorq_int_attn_desc[9] = { | |
5181 | "dorq_address_error", | |
5182 | "dorq_db_drop", | |
5183 | "dorq_dorq_fifo_ovfl_err", | |
5184 | "dorq_dorq_fifo_afull", | |
5185 | "dorq_cfc_byp_validation_err", | |
5186 | "dorq_cfc_ld_resp_err", | |
5187 | "dorq_xcm_done_cnt_err", | |
5188 | "dorq_cfc_ld_req_fifo_ovfl_err", | |
5189 | "dorq_cfc_ld_req_fifo_under_err", | |
5190 | }; | |
5191 | #else | |
5192 | #define dorq_int_attn_desc OSAL_NULL | |
5193 | #endif | |
5194 | ||
5195 | static const u16 dorq_int0_bb_a0_attn_idx[9] = { | |
5196 | 0, 1, 2, 3, 4, 5, 6, 7, 8, | |
5197 | }; | |
5198 | ||
5199 | static struct attn_hw_reg dorq_int0_bb_a0 = { | |
5200 | 0, 9, dorq_int0_bb_a0_attn_idx, 0x100180, 0x10018c, 0x100188, 0x100184 | |
5201 | }; | |
5202 | ||
5203 | static struct attn_hw_reg *dorq_int_bb_a0_regs[1] = { | |
5204 | &dorq_int0_bb_a0, | |
5205 | }; | |
5206 | ||
5207 | static const u16 dorq_int0_bb_b0_attn_idx[9] = { | |
5208 | 0, 1, 2, 3, 4, 5, 6, 7, 8, | |
5209 | }; | |
5210 | ||
5211 | static struct attn_hw_reg dorq_int0_bb_b0 = { | |
5212 | 0, 9, dorq_int0_bb_b0_attn_idx, 0x100180, 0x10018c, 0x100188, 0x100184 | |
5213 | }; | |
5214 | ||
5215 | static struct attn_hw_reg *dorq_int_bb_b0_regs[1] = { | |
5216 | &dorq_int0_bb_b0, | |
5217 | }; | |
5218 | ||
5219 | static const u16 dorq_int0_k2_attn_idx[9] = { | |
5220 | 0, 1, 2, 3, 4, 5, 6, 7, 8, | |
5221 | }; | |
5222 | ||
5223 | static struct attn_hw_reg dorq_int0_k2 = { | |
5224 | 0, 9, dorq_int0_k2_attn_idx, 0x100180, 0x10018c, 0x100188, 0x100184 | |
5225 | }; | |
5226 | ||
5227 | static struct attn_hw_reg *dorq_int_k2_regs[1] = { | |
5228 | &dorq_int0_k2, | |
5229 | }; | |
5230 | ||
5231 | #ifdef ATTN_DESC | |
5232 | static const char *dorq_prty_attn_desc[7] = { | |
5233 | "dorq_datapath_registers", | |
5234 | "dorq_mem002_i_ecc_rf_int", | |
5235 | "dorq_mem001_i_mem_prty", | |
5236 | "dorq_mem003_i_mem_prty", | |
5237 | "dorq_mem004_i_mem_prty", | |
5238 | "dorq_mem005_i_mem_prty", | |
5239 | "dorq_mem006_i_mem_prty", | |
5240 | }; | |
5241 | #else | |
5242 | #define dorq_prty_attn_desc OSAL_NULL | |
5243 | #endif | |
5244 | ||
5245 | static const u16 dorq_prty1_bb_a0_attn_idx[6] = { | |
5246 | 1, 2, 3, 4, 5, 6, | |
5247 | }; | |
5248 | ||
5249 | static struct attn_hw_reg dorq_prty1_bb_a0 = { | |
5250 | 0, 6, dorq_prty1_bb_a0_attn_idx, 0x100200, 0x10020c, 0x100208, 0x100204 | |
5251 | }; | |
5252 | ||
5253 | static struct attn_hw_reg *dorq_prty_bb_a0_regs[1] = { | |
5254 | &dorq_prty1_bb_a0, | |
5255 | }; | |
5256 | ||
5257 | static const u16 dorq_prty0_bb_b0_attn_idx[1] = { | |
5258 | 0, | |
5259 | }; | |
5260 | ||
5261 | static struct attn_hw_reg dorq_prty0_bb_b0 = { | |
5262 | 0, 1, dorq_prty0_bb_b0_attn_idx, 0x100190, 0x10019c, 0x100198, 0x100194 | |
5263 | }; | |
5264 | ||
5265 | static const u16 dorq_prty1_bb_b0_attn_idx[6] = { | |
5266 | 1, 2, 3, 4, 5, 6, | |
5267 | }; | |
5268 | ||
5269 | static struct attn_hw_reg dorq_prty1_bb_b0 = { | |
5270 | 1, 6, dorq_prty1_bb_b0_attn_idx, 0x100200, 0x10020c, 0x100208, 0x100204 | |
5271 | }; | |
5272 | ||
5273 | static struct attn_hw_reg *dorq_prty_bb_b0_regs[2] = { | |
5274 | &dorq_prty0_bb_b0, &dorq_prty1_bb_b0, | |
5275 | }; | |
5276 | ||
5277 | static const u16 dorq_prty0_k2_attn_idx[1] = { | |
5278 | 0, | |
5279 | }; | |
5280 | ||
5281 | static struct attn_hw_reg dorq_prty0_k2 = { | |
5282 | 0, 1, dorq_prty0_k2_attn_idx, 0x100190, 0x10019c, 0x100198, 0x100194 | |
5283 | }; | |
5284 | ||
5285 | static const u16 dorq_prty1_k2_attn_idx[6] = { | |
5286 | 1, 2, 3, 4, 5, 6, | |
5287 | }; | |
5288 | ||
5289 | static struct attn_hw_reg dorq_prty1_k2 = { | |
5290 | 1, 6, dorq_prty1_k2_attn_idx, 0x100200, 0x10020c, 0x100208, 0x100204 | |
5291 | }; | |
5292 | ||
5293 | static struct attn_hw_reg *dorq_prty_k2_regs[2] = { | |
5294 | &dorq_prty0_k2, &dorq_prty1_k2, | |
5295 | }; | |
5296 | ||
5297 | #ifdef ATTN_DESC | |
5298 | static const char *brb_int_attn_desc[237] = { | |
5299 | "brb_address_error", | |
5300 | "brb_rc_pkt0_rls_error", | |
5301 | "brb_rc_pkt0_1st_error", | |
5302 | "brb_rc_pkt0_len_error", | |
5303 | "brb_rc_pkt0_middle_error", | |
5304 | "brb_rc_pkt0_protocol_error", | |
5305 | "brb_rc_pkt1_rls_error", | |
5306 | "brb_rc_pkt1_1st_error", | |
5307 | "brb_rc_pkt1_len_error", | |
5308 | "brb_rc_pkt1_middle_error", | |
5309 | "brb_rc_pkt1_protocol_error", | |
5310 | "brb_rc_pkt2_rls_error", | |
5311 | "brb_rc_pkt2_1st_error", | |
5312 | "brb_rc_pkt2_len_error", | |
5313 | "brb_rc_pkt2_middle_error", | |
5314 | "brb_rc_pkt2_protocol_error", | |
5315 | "brb_rc_pkt3_rls_error", | |
5316 | "brb_rc_pkt3_1st_error", | |
5317 | "brb_rc_pkt3_len_error", | |
5318 | "brb_rc_pkt3_middle_error", | |
5319 | "brb_rc_pkt3_protocol_error", | |
5320 | "brb_rc_sop_req_tc_port_error", | |
5321 | "brb_uncomplient_lossless_error", | |
5322 | "brb_wc0_protocol_error", | |
5323 | "brb_wc1_protocol_error", | |
5324 | "brb_wc2_protocol_error", | |
5325 | "brb_wc3_protocol_error", | |
5326 | "brb_ll_arb_prefetch_sop_error", | |
5327 | "brb_ll_blk_error", | |
5328 | "brb_packet_counter_error", | |
5329 | "brb_byte_counter_error", | |
5330 | "brb_mac0_fc_cnt_error", | |
5331 | "brb_mac1_fc_cnt_error", | |
5332 | "brb_ll_arb_calc_error", | |
5333 | "brb_unused_0", | |
5334 | "brb_wc0_inp_fifo_error", | |
5335 | "brb_wc0_sop_fifo_error", | |
5336 | "brb_unused_1", | |
5337 | "brb_wc0_eop_fifo_error", | |
5338 | "brb_wc0_queue_fifo_error", | |
5339 | "brb_wc0_free_point_fifo_error", | |
5340 | "brb_wc0_next_point_fifo_error", | |
5341 | "brb_wc0_strt_fifo_error", | |
5342 | "brb_wc0_second_dscr_fifo_error", | |
5343 | "brb_wc0_pkt_avail_fifo_error", | |
5344 | "brb_wc0_cos_cnt_fifo_error", | |
5345 | "brb_wc0_notify_fifo_error", | |
5346 | "brb_wc0_ll_req_fifo_error", | |
5347 | "brb_wc0_ll_pa_cnt_error", | |
5348 | "brb_wc0_bb_pa_cnt_error", | |
5349 | "brb_wc1_inp_fifo_error", | |
5350 | "brb_wc1_sop_fifo_error", | |
5351 | "brb_wc1_eop_fifo_error", | |
5352 | "brb_wc1_queue_fifo_error", | |
5353 | "brb_wc1_free_point_fifo_error", | |
5354 | "brb_wc1_next_point_fifo_error", | |
5355 | "brb_wc1_strt_fifo_error", | |
5356 | "brb_wc1_second_dscr_fifo_error", | |
5357 | "brb_wc1_pkt_avail_fifo_error", | |
5358 | "brb_wc1_cos_cnt_fifo_error", | |
5359 | "brb_wc1_notify_fifo_error", | |
5360 | "brb_wc1_ll_req_fifo_error", | |
5361 | "brb_wc1_ll_pa_cnt_error", | |
5362 | "brb_wc1_bb_pa_cnt_error", | |
5363 | "brb_wc2_inp_fifo_error", | |
5364 | "brb_wc2_sop_fifo_error", | |
5365 | "brb_wc2_eop_fifo_error", | |
5366 | "brb_wc2_queue_fifo_error", | |
5367 | "brb_wc2_free_point_fifo_error", | |
5368 | "brb_wc2_next_point_fifo_error", | |
5369 | "brb_wc2_strt_fifo_error", | |
5370 | "brb_wc2_second_dscr_fifo_error", | |
5371 | "brb_wc2_pkt_avail_fifo_error", | |
5372 | "brb_wc2_cos_cnt_fifo_error", | |
5373 | "brb_wc2_notify_fifo_error", | |
5374 | "brb_wc2_ll_req_fifo_error", | |
5375 | "brb_wc2_ll_pa_cnt_error", | |
5376 | "brb_wc2_bb_pa_cnt_error", | |
5377 | "brb_wc3_inp_fifo_error", | |
5378 | "brb_wc3_sop_fifo_error", | |
5379 | "brb_wc3_eop_fifo_error", | |
5380 | "brb_wc3_queue_fifo_error", | |
5381 | "brb_wc3_free_point_fifo_error", | |
5382 | "brb_wc3_next_point_fifo_error", | |
5383 | "brb_wc3_strt_fifo_error", | |
5384 | "brb_wc3_second_dscr_fifo_error", | |
5385 | "brb_wc3_pkt_avail_fifo_error", | |
5386 | "brb_wc3_cos_cnt_fifo_error", | |
5387 | "brb_wc3_notify_fifo_error", | |
5388 | "brb_wc3_ll_req_fifo_error", | |
5389 | "brb_wc3_ll_pa_cnt_error", | |
5390 | "brb_wc3_bb_pa_cnt_error", | |
5391 | "brb_rc_pkt0_side_fifo_error", | |
5392 | "brb_rc_pkt0_req_fifo_error", | |
5393 | "brb_rc_pkt0_blk_fifo_error", | |
5394 | "brb_rc_pkt0_rls_left_fifo_error", | |
5395 | "brb_rc_pkt0_strt_ptr_fifo_error", | |
5396 | "brb_rc_pkt0_second_ptr_fifo_error", | |
5397 | "brb_rc_pkt0_rsp_fifo_error", | |
5398 | "brb_rc_pkt0_dscr_fifo_error", | |
5399 | "brb_rc_pkt1_side_fifo_error", | |
5400 | "brb_rc_pkt1_req_fifo_error", | |
5401 | "brb_rc_pkt1_blk_fifo_error", | |
5402 | "brb_rc_pkt1_rls_left_fifo_error", | |
5403 | "brb_rc_pkt1_strt_ptr_fifo_error", | |
5404 | "brb_rc_pkt1_second_ptr_fifo_error", | |
5405 | "brb_rc_pkt1_rsp_fifo_error", | |
5406 | "brb_rc_pkt1_dscr_fifo_error", | |
5407 | "brb_rc_pkt2_side_fifo_error", | |
5408 | "brb_rc_pkt2_req_fifo_error", | |
5409 | "brb_rc_pkt2_blk_fifo_error", | |
5410 | "brb_rc_pkt2_rls_left_fifo_error", | |
5411 | "brb_rc_pkt2_strt_ptr_fifo_error", | |
5412 | "brb_rc_pkt2_second_ptr_fifo_error", | |
5413 | "brb_rc_pkt2_rsp_fifo_error", | |
5414 | "brb_rc_pkt2_dscr_fifo_error", | |
5415 | "brb_rc_pkt3_side_fifo_error", | |
5416 | "brb_rc_pkt3_req_fifo_error", | |
5417 | "brb_rc_pkt3_blk_fifo_error", | |
5418 | "brb_rc_pkt3_rls_left_fifo_error", | |
5419 | "brb_rc_pkt3_strt_ptr_fifo_error", | |
5420 | "brb_rc_pkt3_second_ptr_fifo_error", | |
5421 | "brb_rc_pkt3_rsp_fifo_error", | |
5422 | "brb_rc_pkt3_dscr_fifo_error", | |
5423 | "brb_rc_sop_strt_fifo_error", | |
5424 | "brb_rc_sop_req_fifo_error", | |
5425 | "brb_rc_sop_dscr_fifo_error", | |
5426 | "brb_rc_sop_queue_fifo_error", | |
5427 | "brb_rc0_eop_error", | |
5428 | "brb_rc1_eop_error", | |
5429 | "brb_ll_arb_rls_fifo_error", | |
5430 | "brb_ll_arb_prefetch_fifo_error", | |
5431 | "brb_rc_pkt0_rls_fifo_error", | |
5432 | "brb_rc_pkt1_rls_fifo_error", | |
5433 | "brb_rc_pkt2_rls_fifo_error", | |
5434 | "brb_rc_pkt3_rls_fifo_error", | |
5435 | "brb_rc_pkt4_rls_fifo_error", | |
5436 | "brb_rc_pkt4_rls_error", | |
5437 | "brb_rc_pkt4_1st_error", | |
5438 | "brb_rc_pkt4_len_error", | |
5439 | "brb_rc_pkt4_middle_error", | |
5440 | "brb_rc_pkt4_protocol_error", | |
5441 | "brb_rc_pkt4_side_fifo_error", | |
5442 | "brb_rc_pkt4_req_fifo_error", | |
5443 | "brb_rc_pkt4_blk_fifo_error", | |
5444 | "brb_rc_pkt4_rls_left_fifo_error", | |
5445 | "brb_rc_pkt4_strt_ptr_fifo_error", | |
5446 | "brb_rc_pkt4_second_ptr_fifo_error", | |
5447 | "brb_rc_pkt4_rsp_fifo_error", | |
5448 | "brb_rc_pkt4_dscr_fifo_error", | |
5449 | "brb_rc_pkt5_rls_error", | |
5450 | "brb_packet_available_sync_fifo_push_error", | |
5451 | "brb_wc4_protocol_error", | |
5452 | "brb_wc5_protocol_error", | |
5453 | "brb_wc6_protocol_error", | |
5454 | "brb_wc7_protocol_error", | |
5455 | "brb_wc4_inp_fifo_error", | |
5456 | "brb_wc4_sop_fifo_error", | |
5457 | "brb_wc4_queue_fifo_error", | |
5458 | "brb_wc4_free_point_fifo_error", | |
5459 | "brb_wc4_next_point_fifo_error", | |
5460 | "brb_wc4_strt_fifo_error", | |
5461 | "brb_wc4_second_dscr_fifo_error", | |
5462 | "brb_wc4_pkt_avail_fifo_error", | |
5463 | "brb_wc4_cos_cnt_fifo_error", | |
5464 | "brb_wc4_notify_fifo_error", | |
5465 | "brb_wc4_ll_req_fifo_error", | |
5466 | "brb_wc4_ll_pa_cnt_error", | |
5467 | "brb_wc4_bb_pa_cnt_error", | |
5468 | "brb_wc5_inp_fifo_error", | |
5469 | "brb_wc5_sop_fifo_error", | |
5470 | "brb_wc5_queue_fifo_error", | |
5471 | "brb_wc5_free_point_fifo_error", | |
5472 | "brb_wc5_next_point_fifo_error", | |
5473 | "brb_wc5_strt_fifo_error", | |
5474 | "brb_wc5_second_dscr_fifo_error", | |
5475 | "brb_wc5_pkt_avail_fifo_error", | |
5476 | "brb_wc5_cos_cnt_fifo_error", | |
5477 | "brb_wc5_notify_fifo_error", | |
5478 | "brb_wc5_ll_req_fifo_error", | |
5479 | "brb_wc5_ll_pa_cnt_error", | |
5480 | "brb_wc5_bb_pa_cnt_error", | |
5481 | "brb_wc6_inp_fifo_error", | |
5482 | "brb_wc6_sop_fifo_error", | |
5483 | "brb_wc6_queue_fifo_error", | |
5484 | "brb_wc6_free_point_fifo_error", | |
5485 | "brb_wc6_next_point_fifo_error", | |
5486 | "brb_wc6_strt_fifo_error", | |
5487 | "brb_wc6_second_dscr_fifo_error", | |
5488 | "brb_wc6_pkt_avail_fifo_error", | |
5489 | "brb_wc6_cos_cnt_fifo_error", | |
5490 | "brb_wc6_notify_fifo_error", | |
5491 | "brb_wc6_ll_req_fifo_error", | |
5492 | "brb_wc6_ll_pa_cnt_error", | |
5493 | "brb_wc6_bb_pa_cnt_error", | |
5494 | "brb_wc7_inp_fifo_error", | |
5495 | "brb_wc7_sop_fifo_error", | |
5496 | "brb_wc7_queue_fifo_error", | |
5497 | "brb_wc7_free_point_fifo_error", | |
5498 | "brb_wc7_next_point_fifo_error", | |
5499 | "brb_wc7_strt_fifo_error", | |
5500 | "brb_wc7_second_dscr_fifo_error", | |
5501 | "brb_wc7_pkt_avail_fifo_error", | |
5502 | "brb_wc7_cos_cnt_fifo_error", | |
5503 | "brb_wc7_notify_fifo_error", | |
5504 | "brb_wc7_ll_req_fifo_error", | |
5505 | "brb_wc7_ll_pa_cnt_error", | |
5506 | "brb_wc7_bb_pa_cnt_error", | |
5507 | "brb_wc9_queue_fifo_error", | |
5508 | "brb_rc_sop_inp_sync_fifo_push_error", | |
5509 | "brb_rc0_inp_sync_fifo_push_error", | |
5510 | "brb_rc1_inp_sync_fifo_push_error", | |
5511 | "brb_rc2_inp_sync_fifo_push_error", | |
5512 | "brb_rc3_inp_sync_fifo_push_error", | |
5513 | "brb_rc0_out_sync_fifo_push_error", | |
5514 | "brb_rc1_out_sync_fifo_push_error", | |
5515 | "brb_rc2_out_sync_fifo_push_error", | |
5516 | "brb_rc3_out_sync_fifo_push_error", | |
5517 | "brb_rc4_out_sync_fifo_push_error", | |
5518 | "brb_unused_2", | |
5519 | "brb_rc0_eop_inp_sync_fifo_push_error", | |
5520 | "brb_rc1_eop_inp_sync_fifo_push_error", | |
5521 | "brb_rc2_eop_inp_sync_fifo_push_error", | |
5522 | "brb_rc3_eop_inp_sync_fifo_push_error", | |
5523 | "brb_rc0_eop_out_sync_fifo_push_error", | |
5524 | "brb_rc1_eop_out_sync_fifo_push_error", | |
5525 | "brb_rc2_eop_out_sync_fifo_push_error", | |
5526 | "brb_rc3_eop_out_sync_fifo_push_error", | |
5527 | "brb_unused_3", | |
5528 | "brb_rc2_eop_error", | |
5529 | "brb_rc3_eop_error", | |
5530 | "brb_mac2_fc_cnt_error", | |
5531 | "brb_mac3_fc_cnt_error", | |
5532 | "brb_wc4_eop_fifo_error", | |
5533 | "brb_wc5_eop_fifo_error", | |
5534 | "brb_wc6_eop_fifo_error", | |
5535 | "brb_wc7_eop_fifo_error", | |
5536 | }; | |
5537 | #else | |
5538 | #define brb_int_attn_desc OSAL_NULL | |
5539 | #endif | |
5540 | ||
5541 | static const u16 brb_int0_bb_a0_attn_idx[32] = { | |
5542 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
5543 | 20, | |
5544 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
5545 | }; | |
5546 | ||
5547 | static struct attn_hw_reg brb_int0_bb_a0 = { | |
5548 | 0, 32, brb_int0_bb_a0_attn_idx, 0x3400c0, 0x3400cc, 0x3400c8, 0x3400c4 | |
5549 | }; | |
5550 | ||
5551 | static const u16 brb_int1_bb_a0_attn_idx[30] = { | |
5552 | 32, 33, 35, 36, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, | |
5553 | 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, | |
5554 | }; | |
5555 | ||
5556 | static struct attn_hw_reg brb_int1_bb_a0 = { | |
5557 | 1, 30, brb_int1_bb_a0_attn_idx, 0x3400d8, 0x3400e4, 0x3400e0, 0x3400dc | |
5558 | }; | |
5559 | ||
5560 | static const u16 brb_int2_bb_a0_attn_idx[28] = { | |
5561 | 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, | |
5562 | 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, | |
5563 | }; | |
5564 | ||
5565 | static struct attn_hw_reg brb_int2_bb_a0 = { | |
5566 | 2, 28, brb_int2_bb_a0_attn_idx, 0x3400f0, 0x3400fc, 0x3400f8, 0x3400f4 | |
5567 | }; | |
5568 | ||
5569 | static const u16 brb_int3_bb_a0_attn_idx[31] = { | |
5570 | 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, | |
5571 | 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, | |
5572 | 122, | |
5573 | }; | |
5574 | ||
5575 | static struct attn_hw_reg brb_int3_bb_a0 = { | |
5576 | 3, 31, brb_int3_bb_a0_attn_idx, 0x340108, 0x340114, 0x340110, 0x34010c | |
5577 | }; | |
5578 | ||
5579 | static const u16 brb_int4_bb_a0_attn_idx[27] = { | |
5580 | 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, | |
5581 | 137, | |
5582 | 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, | |
5583 | }; | |
5584 | ||
5585 | static struct attn_hw_reg brb_int4_bb_a0 = { | |
5586 | 4, 27, brb_int4_bb_a0_attn_idx, 0x340120, 0x34012c, 0x340128, 0x340124 | |
5587 | }; | |
5588 | ||
5589 | static const u16 brb_int5_bb_a0_attn_idx[1] = { | |
5590 | 150, | |
5591 | }; | |
5592 | ||
5593 | static struct attn_hw_reg brb_int5_bb_a0 = { | |
5594 | 5, 1, brb_int5_bb_a0_attn_idx, 0x340138, 0x340144, 0x340140, 0x34013c | |
5595 | }; | |
5596 | ||
5597 | static const u16 brb_int6_bb_a0_attn_idx[8] = { | |
5598 | 151, 152, 153, 154, 155, 156, 157, 158, | |
5599 | }; | |
5600 | ||
5601 | static struct attn_hw_reg brb_int6_bb_a0 = { | |
5602 | 6, 8, brb_int6_bb_a0_attn_idx, 0x340150, 0x34015c, 0x340158, 0x340154 | |
5603 | }; | |
5604 | ||
5605 | static const u16 brb_int7_bb_a0_attn_idx[32] = { | |
5606 | 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, | |
5607 | 173, | |
5608 | 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, | |
5609 | 188, 189, | |
5610 | 190, | |
5611 | }; | |
5612 | ||
5613 | static struct attn_hw_reg brb_int7_bb_a0 = { | |
5614 | 7, 32, brb_int7_bb_a0_attn_idx, 0x340168, 0x340174, 0x340170, 0x34016c | |
5615 | }; | |
5616 | ||
5617 | static const u16 brb_int8_bb_a0_attn_idx[17] = { | |
5618 | 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, | |
5619 | 205, | |
5620 | 206, 207, | |
5621 | }; | |
5622 | ||
5623 | static struct attn_hw_reg brb_int8_bb_a0 = { | |
5624 | 8, 17, brb_int8_bb_a0_attn_idx, 0x340184, 0x340190, 0x34018c, 0x340188 | |
5625 | }; | |
5626 | ||
5627 | static const u16 brb_int9_bb_a0_attn_idx[1] = { | |
5628 | 208, | |
5629 | }; | |
5630 | ||
5631 | static struct attn_hw_reg brb_int9_bb_a0 = { | |
5632 | 9, 1, brb_int9_bb_a0_attn_idx, 0x34019c, 0x3401a8, 0x3401a4, 0x3401a0 | |
5633 | }; | |
5634 | ||
5635 | static const u16 brb_int10_bb_a0_attn_idx[14] = { | |
5636 | 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 220, 221, 224, 225, | |
5637 | }; | |
5638 | ||
5639 | static struct attn_hw_reg brb_int10_bb_a0 = { | |
5640 | 10, 14, brb_int10_bb_a0_attn_idx, 0x3401b4, 0x3401c0, 0x3401bc, | |
5641 | 0x3401b8 | |
5642 | }; | |
5643 | ||
5644 | static const u16 brb_int11_bb_a0_attn_idx[8] = { | |
5645 | 229, 230, 231, 232, 233, 234, 235, 236, | |
5646 | }; | |
5647 | ||
5648 | static struct attn_hw_reg brb_int11_bb_a0 = { | |
5649 | 11, 8, brb_int11_bb_a0_attn_idx, 0x3401cc, 0x3401d8, 0x3401d4, 0x3401d0 | |
5650 | }; | |
5651 | ||
5652 | static struct attn_hw_reg *brb_int_bb_a0_regs[12] = { | |
5653 | &brb_int0_bb_a0, &brb_int1_bb_a0, &brb_int2_bb_a0, &brb_int3_bb_a0, | |
5654 | &brb_int4_bb_a0, &brb_int5_bb_a0, &brb_int6_bb_a0, &brb_int7_bb_a0, | |
5655 | &brb_int8_bb_a0, &brb_int9_bb_a0, | |
5656 | &brb_int10_bb_a0, &brb_int11_bb_a0, | |
5657 | }; | |
5658 | ||
5659 | static const u16 brb_int0_bb_b0_attn_idx[32] = { | |
5660 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
5661 | 20, | |
5662 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
5663 | }; | |
5664 | ||
5665 | static struct attn_hw_reg brb_int0_bb_b0 = { | |
5666 | 0, 32, brb_int0_bb_b0_attn_idx, 0x3400c0, 0x3400cc, 0x3400c8, 0x3400c4 | |
5667 | }; | |
5668 | ||
5669 | static const u16 brb_int1_bb_b0_attn_idx[30] = { | |
5670 | 32, 33, 35, 36, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, | |
5671 | 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, | |
5672 | }; | |
5673 | ||
5674 | static struct attn_hw_reg brb_int1_bb_b0 = { | |
5675 | 1, 30, brb_int1_bb_b0_attn_idx, 0x3400d8, 0x3400e4, 0x3400e0, 0x3400dc | |
5676 | }; | |
5677 | ||
5678 | static const u16 brb_int2_bb_b0_attn_idx[28] = { | |
5679 | 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, | |
5680 | 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, | |
5681 | }; | |
5682 | ||
5683 | static struct attn_hw_reg brb_int2_bb_b0 = { | |
5684 | 2, 28, brb_int2_bb_b0_attn_idx, 0x3400f0, 0x3400fc, 0x3400f8, 0x3400f4 | |
5685 | }; | |
5686 | ||
5687 | static const u16 brb_int3_bb_b0_attn_idx[31] = { | |
5688 | 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, | |
5689 | 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, | |
5690 | 122, | |
5691 | }; | |
5692 | ||
5693 | static struct attn_hw_reg brb_int3_bb_b0 = { | |
5694 | 3, 31, brb_int3_bb_b0_attn_idx, 0x340108, 0x340114, 0x340110, 0x34010c | |
5695 | }; | |
5696 | ||
5697 | static const u16 brb_int4_bb_b0_attn_idx[27] = { | |
5698 | 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, | |
5699 | 137, | |
5700 | 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, | |
5701 | }; | |
5702 | ||
5703 | static struct attn_hw_reg brb_int4_bb_b0 = { | |
5704 | 4, 27, brb_int4_bb_b0_attn_idx, 0x340120, 0x34012c, 0x340128, 0x340124 | |
5705 | }; | |
5706 | ||
5707 | static const u16 brb_int5_bb_b0_attn_idx[1] = { | |
5708 | 150, | |
5709 | }; | |
5710 | ||
5711 | static struct attn_hw_reg brb_int5_bb_b0 = { | |
5712 | 5, 1, brb_int5_bb_b0_attn_idx, 0x340138, 0x340144, 0x340140, 0x34013c | |
5713 | }; | |
5714 | ||
5715 | static const u16 brb_int6_bb_b0_attn_idx[8] = { | |
5716 | 151, 152, 153, 154, 155, 156, 157, 158, | |
5717 | }; | |
5718 | ||
5719 | static struct attn_hw_reg brb_int6_bb_b0 = { | |
5720 | 6, 8, brb_int6_bb_b0_attn_idx, 0x340150, 0x34015c, 0x340158, 0x340154 | |
5721 | }; | |
5722 | ||
5723 | static const u16 brb_int7_bb_b0_attn_idx[32] = { | |
5724 | 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, | |
5725 | 173, | |
5726 | 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, | |
5727 | 188, 189, | |
5728 | 190, | |
5729 | }; | |
5730 | ||
5731 | static struct attn_hw_reg brb_int7_bb_b0 = { | |
5732 | 7, 32, brb_int7_bb_b0_attn_idx, 0x340168, 0x340174, 0x340170, 0x34016c | |
5733 | }; | |
5734 | ||
5735 | static const u16 brb_int8_bb_b0_attn_idx[17] = { | |
5736 | 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, | |
5737 | 205, | |
5738 | 206, 207, | |
5739 | }; | |
5740 | ||
5741 | static struct attn_hw_reg brb_int8_bb_b0 = { | |
5742 | 8, 17, brb_int8_bb_b0_attn_idx, 0x340184, 0x340190, 0x34018c, 0x340188 | |
5743 | }; | |
5744 | ||
5745 | static const u16 brb_int9_bb_b0_attn_idx[1] = { | |
5746 | 208, | |
5747 | }; | |
5748 | ||
5749 | static struct attn_hw_reg brb_int9_bb_b0 = { | |
5750 | 9, 1, brb_int9_bb_b0_attn_idx, 0x34019c, 0x3401a8, 0x3401a4, 0x3401a0 | |
5751 | }; | |
5752 | ||
5753 | static const u16 brb_int10_bb_b0_attn_idx[14] = { | |
5754 | 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 220, 221, 224, 225, | |
5755 | }; | |
5756 | ||
5757 | static struct attn_hw_reg brb_int10_bb_b0 = { | |
5758 | 10, 14, brb_int10_bb_b0_attn_idx, 0x3401b4, 0x3401c0, 0x3401bc, | |
5759 | 0x3401b8 | |
5760 | }; | |
5761 | ||
5762 | static const u16 brb_int11_bb_b0_attn_idx[8] = { | |
5763 | 229, 230, 231, 232, 233, 234, 235, 236, | |
5764 | }; | |
5765 | ||
5766 | static struct attn_hw_reg brb_int11_bb_b0 = { | |
5767 | 11, 8, brb_int11_bb_b0_attn_idx, 0x3401cc, 0x3401d8, 0x3401d4, 0x3401d0 | |
5768 | }; | |
5769 | ||
5770 | static struct attn_hw_reg *brb_int_bb_b0_regs[12] = { | |
5771 | &brb_int0_bb_b0, &brb_int1_bb_b0, &brb_int2_bb_b0, &brb_int3_bb_b0, | |
5772 | &brb_int4_bb_b0, &brb_int5_bb_b0, &brb_int6_bb_b0, &brb_int7_bb_b0, | |
5773 | &brb_int8_bb_b0, &brb_int9_bb_b0, | |
5774 | &brb_int10_bb_b0, &brb_int11_bb_b0, | |
5775 | }; | |
5776 | ||
5777 | static const u16 brb_int0_k2_attn_idx[32] = { | |
5778 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
5779 | 20, | |
5780 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
5781 | }; | |
5782 | ||
5783 | static struct attn_hw_reg brb_int0_k2 = { | |
5784 | 0, 32, brb_int0_k2_attn_idx, 0x3400c0, 0x3400cc, 0x3400c8, 0x3400c4 | |
5785 | }; | |
5786 | ||
5787 | static const u16 brb_int1_k2_attn_idx[30] = { | |
5788 | 32, 33, 35, 36, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, | |
5789 | 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, | |
5790 | }; | |
5791 | ||
5792 | static struct attn_hw_reg brb_int1_k2 = { | |
5793 | 1, 30, brb_int1_k2_attn_idx, 0x3400d8, 0x3400e4, 0x3400e0, 0x3400dc | |
5794 | }; | |
5795 | ||
5796 | static const u16 brb_int2_k2_attn_idx[28] = { | |
5797 | 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, | |
5798 | 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, | |
5799 | }; | |
5800 | ||
5801 | static struct attn_hw_reg brb_int2_k2 = { | |
5802 | 2, 28, brb_int2_k2_attn_idx, 0x3400f0, 0x3400fc, 0x3400f8, 0x3400f4 | |
5803 | }; | |
5804 | ||
5805 | static const u16 brb_int3_k2_attn_idx[31] = { | |
5806 | 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, | |
5807 | 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, | |
5808 | 122, | |
5809 | }; | |
5810 | ||
5811 | static struct attn_hw_reg brb_int3_k2 = { | |
5812 | 3, 31, brb_int3_k2_attn_idx, 0x340108, 0x340114, 0x340110, 0x34010c | |
5813 | }; | |
5814 | ||
5815 | static const u16 brb_int4_k2_attn_idx[27] = { | |
5816 | 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, | |
5817 | 137, | |
5818 | 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, | |
5819 | }; | |
5820 | ||
5821 | static struct attn_hw_reg brb_int4_k2 = { | |
5822 | 4, 27, brb_int4_k2_attn_idx, 0x340120, 0x34012c, 0x340128, 0x340124 | |
5823 | }; | |
5824 | ||
5825 | static const u16 brb_int5_k2_attn_idx[1] = { | |
5826 | 150, | |
5827 | }; | |
5828 | ||
5829 | static struct attn_hw_reg brb_int5_k2 = { | |
5830 | 5, 1, brb_int5_k2_attn_idx, 0x340138, 0x340144, 0x340140, 0x34013c | |
5831 | }; | |
5832 | ||
5833 | static const u16 brb_int6_k2_attn_idx[8] = { | |
5834 | 151, 152, 153, 154, 155, 156, 157, 158, | |
5835 | }; | |
5836 | ||
5837 | static struct attn_hw_reg brb_int6_k2 = { | |
5838 | 6, 8, brb_int6_k2_attn_idx, 0x340150, 0x34015c, 0x340158, 0x340154 | |
5839 | }; | |
5840 | ||
5841 | static const u16 brb_int7_k2_attn_idx[32] = { | |
5842 | 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, | |
5843 | 173, | |
5844 | 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, | |
5845 | 188, 189, | |
5846 | 190, | |
5847 | }; | |
5848 | ||
5849 | static struct attn_hw_reg brb_int7_k2 = { | |
5850 | 7, 32, brb_int7_k2_attn_idx, 0x340168, 0x340174, 0x340170, 0x34016c | |
5851 | }; | |
5852 | ||
5853 | static const u16 brb_int8_k2_attn_idx[17] = { | |
5854 | 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, | |
5855 | 205, | |
5856 | 206, 207, | |
5857 | }; | |
5858 | ||
5859 | static struct attn_hw_reg brb_int8_k2 = { | |
5860 | 8, 17, brb_int8_k2_attn_idx, 0x340184, 0x340190, 0x34018c, 0x340188 | |
5861 | }; | |
5862 | ||
5863 | static const u16 brb_int9_k2_attn_idx[1] = { | |
5864 | 208, | |
5865 | }; | |
5866 | ||
5867 | static struct attn_hw_reg brb_int9_k2 = { | |
5868 | 9, 1, brb_int9_k2_attn_idx, 0x34019c, 0x3401a8, 0x3401a4, 0x3401a0 | |
5869 | }; | |
5870 | ||
5871 | static const u16 brb_int10_k2_attn_idx[18] = { | |
5872 | 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 220, 221, 222, 223, | |
5873 | 224, | |
5874 | 225, 226, 227, | |
5875 | }; | |
5876 | ||
5877 | static struct attn_hw_reg brb_int10_k2 = { | |
5878 | 10, 18, brb_int10_k2_attn_idx, 0x3401b4, 0x3401c0, 0x3401bc, 0x3401b8 | |
5879 | }; | |
5880 | ||
5881 | static const u16 brb_int11_k2_attn_idx[8] = { | |
5882 | 229, 230, 231, 232, 233, 234, 235, 236, | |
5883 | }; | |
5884 | ||
5885 | static struct attn_hw_reg brb_int11_k2 = { | |
5886 | 11, 8, brb_int11_k2_attn_idx, 0x3401cc, 0x3401d8, 0x3401d4, 0x3401d0 | |
5887 | }; | |
5888 | ||
5889 | static struct attn_hw_reg *brb_int_k2_regs[12] = { | |
5890 | &brb_int0_k2, &brb_int1_k2, &brb_int2_k2, &brb_int3_k2, &brb_int4_k2, | |
5891 | &brb_int5_k2, &brb_int6_k2, &brb_int7_k2, &brb_int8_k2, &brb_int9_k2, | |
5892 | &brb_int10_k2, &brb_int11_k2, | |
5893 | }; | |
5894 | ||
5895 | #ifdef ATTN_DESC | |
5896 | static const char *brb_prty_attn_desc[75] = { | |
5897 | "brb_ll_bank0_mem_prty", | |
5898 | "brb_ll_bank1_mem_prty", | |
5899 | "brb_ll_bank2_mem_prty", | |
5900 | "brb_ll_bank3_mem_prty", | |
5901 | "brb_datapath_registers", | |
5902 | "brb_mem001_i_ecc_rf_int", | |
5903 | "brb_mem008_i_ecc_rf_int", | |
5904 | "brb_mem009_i_ecc_rf_int", | |
5905 | "brb_mem010_i_ecc_rf_int", | |
5906 | "brb_mem011_i_ecc_rf_int", | |
5907 | "brb_mem012_i_ecc_rf_int", | |
5908 | "brb_mem013_i_ecc_rf_int", | |
5909 | "brb_mem014_i_ecc_rf_int", | |
5910 | "brb_mem015_i_ecc_rf_int", | |
5911 | "brb_mem016_i_ecc_rf_int", | |
5912 | "brb_mem002_i_ecc_rf_int", | |
5913 | "brb_mem003_i_ecc_rf_int", | |
5914 | "brb_mem004_i_ecc_rf_int", | |
5915 | "brb_mem005_i_ecc_rf_int", | |
5916 | "brb_mem006_i_ecc_rf_int", | |
5917 | "brb_mem007_i_ecc_rf_int", | |
5918 | "brb_mem070_i_mem_prty", | |
5919 | "brb_mem069_i_mem_prty", | |
5920 | "brb_mem053_i_mem_prty", | |
5921 | "brb_mem054_i_mem_prty", | |
5922 | "brb_mem055_i_mem_prty", | |
5923 | "brb_mem056_i_mem_prty", | |
5924 | "brb_mem057_i_mem_prty", | |
5925 | "brb_mem058_i_mem_prty", | |
5926 | "brb_mem059_i_mem_prty", | |
5927 | "brb_mem060_i_mem_prty", | |
5928 | "brb_mem061_i_mem_prty", | |
5929 | "brb_mem062_i_mem_prty", | |
5930 | "brb_mem063_i_mem_prty", | |
5931 | "brb_mem064_i_mem_prty", | |
5932 | "brb_mem065_i_mem_prty", | |
5933 | "brb_mem045_i_mem_prty", | |
5934 | "brb_mem046_i_mem_prty", | |
5935 | "brb_mem047_i_mem_prty", | |
5936 | "brb_mem048_i_mem_prty", | |
5937 | "brb_mem049_i_mem_prty", | |
5938 | "brb_mem050_i_mem_prty", | |
5939 | "brb_mem051_i_mem_prty", | |
5940 | "brb_mem052_i_mem_prty", | |
5941 | "brb_mem041_i_mem_prty", | |
5942 | "brb_mem042_i_mem_prty", | |
5943 | "brb_mem043_i_mem_prty", | |
5944 | "brb_mem044_i_mem_prty", | |
5945 | "brb_mem040_i_mem_prty", | |
5946 | "brb_mem035_i_mem_prty", | |
5947 | "brb_mem066_i_mem_prty", | |
5948 | "brb_mem067_i_mem_prty", | |
5949 | "brb_mem068_i_mem_prty", | |
5950 | "brb_mem030_i_mem_prty", | |
5951 | "brb_mem031_i_mem_prty", | |
5952 | "brb_mem032_i_mem_prty", | |
5953 | "brb_mem033_i_mem_prty", | |
5954 | "brb_mem037_i_mem_prty", | |
5955 | "brb_mem038_i_mem_prty", | |
5956 | "brb_mem034_i_mem_prty", | |
5957 | "brb_mem036_i_mem_prty", | |
5958 | "brb_mem017_i_mem_prty", | |
5959 | "brb_mem018_i_mem_prty", | |
5960 | "brb_mem019_i_mem_prty", | |
5961 | "brb_mem020_i_mem_prty", | |
5962 | "brb_mem021_i_mem_prty", | |
5963 | "brb_mem022_i_mem_prty", | |
5964 | "brb_mem023_i_mem_prty", | |
5965 | "brb_mem024_i_mem_prty", | |
5966 | "brb_mem029_i_mem_prty", | |
5967 | "brb_mem026_i_mem_prty", | |
5968 | "brb_mem027_i_mem_prty", | |
5969 | "brb_mem028_i_mem_prty", | |
5970 | "brb_mem025_i_mem_prty", | |
5971 | "brb_mem039_i_mem_prty", | |
5972 | }; | |
5973 | #else | |
5974 | #define brb_prty_attn_desc OSAL_NULL | |
5975 | #endif | |
5976 | ||
5977 | static const u16 brb_prty1_bb_a0_attn_idx[31] = { | |
5978 | 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 23, 24, 36, | |
5979 | 37, | |
5980 | 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 49, | |
5981 | }; | |
5982 | ||
5983 | static struct attn_hw_reg brb_prty1_bb_a0 = { | |
5984 | 0, 31, brb_prty1_bb_a0_attn_idx, 0x340400, 0x34040c, 0x340408, 0x340404 | |
5985 | }; | |
5986 | ||
5987 | static const u16 brb_prty2_bb_a0_attn_idx[19] = { | |
5988 | 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 69, 70, 71, 72, 73, 74, | |
5989 | 48, | |
5990 | }; | |
5991 | ||
5992 | static struct attn_hw_reg brb_prty2_bb_a0 = { | |
5993 | 1, 19, brb_prty2_bb_a0_attn_idx, 0x340410, 0x34041c, 0x340418, 0x340414 | |
5994 | }; | |
5995 | ||
5996 | static struct attn_hw_reg *brb_prty_bb_a0_regs[2] = { | |
5997 | &brb_prty1_bb_a0, &brb_prty2_bb_a0, | |
5998 | }; | |
5999 | ||
6000 | static const u16 brb_prty0_bb_b0_attn_idx[5] = { | |
6001 | 0, 1, 2, 3, 4, | |
6002 | }; | |
6003 | ||
6004 | static struct attn_hw_reg brb_prty0_bb_b0 = { | |
6005 | 0, 5, brb_prty0_bb_b0_attn_idx, 0x3401dc, 0x3401e8, 0x3401e4, 0x3401e0 | |
6006 | }; | |
6007 | ||
6008 | static const u16 brb_prty1_bb_b0_attn_idx[31] = { | |
6009 | 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 23, 24, 36, | |
6010 | 37, | |
6011 | 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, | |
6012 | }; | |
6013 | ||
6014 | static struct attn_hw_reg brb_prty1_bb_b0 = { | |
6015 | 1, 31, brb_prty1_bb_b0_attn_idx, 0x340400, 0x34040c, 0x340408, 0x340404 | |
6016 | }; | |
6017 | ||
6018 | static const u16 brb_prty2_bb_b0_attn_idx[14] = { | |
6019 | 53, 54, 55, 56, 59, 61, 62, 63, 64, 69, 70, 71, 72, 73, | |
6020 | }; | |
6021 | ||
6022 | static struct attn_hw_reg brb_prty2_bb_b0 = { | |
6023 | 2, 14, brb_prty2_bb_b0_attn_idx, 0x340410, 0x34041c, 0x340418, 0x340414 | |
6024 | }; | |
6025 | ||
6026 | static struct attn_hw_reg *brb_prty_bb_b0_regs[3] = { | |
6027 | &brb_prty0_bb_b0, &brb_prty1_bb_b0, &brb_prty2_bb_b0, | |
6028 | }; | |
6029 | ||
6030 | static const u16 brb_prty0_k2_attn_idx[5] = { | |
6031 | 0, 1, 2, 3, 4, | |
6032 | }; | |
6033 | ||
6034 | static struct attn_hw_reg brb_prty0_k2 = { | |
6035 | 0, 5, brb_prty0_k2_attn_idx, 0x3401dc, 0x3401e8, 0x3401e4, 0x3401e0 | |
6036 | }; | |
6037 | ||
6038 | static const u16 brb_prty1_k2_attn_idx[31] = { | |
6039 | 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, | |
6040 | 24, | |
6041 | 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, | |
6042 | }; | |
6043 | ||
6044 | static struct attn_hw_reg brb_prty1_k2 = { | |
6045 | 1, 31, brb_prty1_k2_attn_idx, 0x340400, 0x34040c, 0x340408, 0x340404 | |
6046 | }; | |
6047 | ||
6048 | static const u16 brb_prty2_k2_attn_idx[30] = { | |
6049 | 50, 51, 52, 36, 37, 38, 39, 40, 41, 42, 43, 47, 53, 54, 55, 56, 57, 58, | |
6050 | 59, 49, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, | |
6051 | }; | |
6052 | ||
6053 | static struct attn_hw_reg brb_prty2_k2 = { | |
6054 | 2, 30, brb_prty2_k2_attn_idx, 0x340410, 0x34041c, 0x340418, 0x340414 | |
6055 | }; | |
6056 | ||
6057 | static struct attn_hw_reg *brb_prty_k2_regs[3] = { | |
6058 | &brb_prty0_k2, &brb_prty1_k2, &brb_prty2_k2, | |
6059 | }; | |
6060 | ||
6061 | #ifdef ATTN_DESC | |
6062 | static const char *src_int_attn_desc[1] = { | |
6063 | "src_address_error", | |
6064 | }; | |
6065 | #else | |
6066 | #define src_int_attn_desc OSAL_NULL | |
6067 | #endif | |
6068 | ||
6069 | static const u16 src_int0_bb_a0_attn_idx[1] = { | |
6070 | 0, | |
6071 | }; | |
6072 | ||
6073 | static struct attn_hw_reg src_int0_bb_a0 = { | |
6074 | 0, 1, src_int0_bb_a0_attn_idx, 0x2381d8, 0x2381dc, 0x2381e0, 0x2381e4 | |
6075 | }; | |
6076 | ||
6077 | static struct attn_hw_reg *src_int_bb_a0_regs[1] = { | |
6078 | &src_int0_bb_a0, | |
6079 | }; | |
6080 | ||
6081 | static const u16 src_int0_bb_b0_attn_idx[1] = { | |
6082 | 0, | |
6083 | }; | |
6084 | ||
6085 | static struct attn_hw_reg src_int0_bb_b0 = { | |
6086 | 0, 1, src_int0_bb_b0_attn_idx, 0x2381d8, 0x2381dc, 0x2381e0, 0x2381e4 | |
6087 | }; | |
6088 | ||
6089 | static struct attn_hw_reg *src_int_bb_b0_regs[1] = { | |
6090 | &src_int0_bb_b0, | |
6091 | }; | |
6092 | ||
6093 | static const u16 src_int0_k2_attn_idx[1] = { | |
6094 | 0, | |
6095 | }; | |
6096 | ||
6097 | static struct attn_hw_reg src_int0_k2 = { | |
6098 | 0, 1, src_int0_k2_attn_idx, 0x2381d8, 0x2381dc, 0x2381e0, 0x2381e4 | |
6099 | }; | |
6100 | ||
6101 | static struct attn_hw_reg *src_int_k2_regs[1] = { | |
6102 | &src_int0_k2, | |
6103 | }; | |
6104 | ||
6105 | #ifdef ATTN_DESC | |
6106 | static const char *prs_int_attn_desc[2] = { | |
6107 | "prs_address_error", | |
6108 | "prs_lcid_validation_err", | |
6109 | }; | |
6110 | #else | |
6111 | #define prs_int_attn_desc OSAL_NULL | |
6112 | #endif | |
6113 | ||
6114 | static const u16 prs_int0_bb_a0_attn_idx[2] = { | |
6115 | 0, 1, | |
6116 | }; | |
6117 | ||
6118 | static struct attn_hw_reg prs_int0_bb_a0 = { | |
6119 | 0, 2, prs_int0_bb_a0_attn_idx, 0x1f0040, 0x1f004c, 0x1f0048, 0x1f0044 | |
6120 | }; | |
6121 | ||
6122 | static struct attn_hw_reg *prs_int_bb_a0_regs[1] = { | |
6123 | &prs_int0_bb_a0, | |
6124 | }; | |
6125 | ||
6126 | static const u16 prs_int0_bb_b0_attn_idx[2] = { | |
6127 | 0, 1, | |
6128 | }; | |
6129 | ||
6130 | static struct attn_hw_reg prs_int0_bb_b0 = { | |
6131 | 0, 2, prs_int0_bb_b0_attn_idx, 0x1f0040, 0x1f004c, 0x1f0048, 0x1f0044 | |
6132 | }; | |
6133 | ||
6134 | static struct attn_hw_reg *prs_int_bb_b0_regs[1] = { | |
6135 | &prs_int0_bb_b0, | |
6136 | }; | |
6137 | ||
6138 | static const u16 prs_int0_k2_attn_idx[2] = { | |
6139 | 0, 1, | |
6140 | }; | |
6141 | ||
6142 | static struct attn_hw_reg prs_int0_k2 = { | |
6143 | 0, 2, prs_int0_k2_attn_idx, 0x1f0040, 0x1f004c, 0x1f0048, 0x1f0044 | |
6144 | }; | |
6145 | ||
6146 | static struct attn_hw_reg *prs_int_k2_regs[1] = { | |
6147 | &prs_int0_k2, | |
6148 | }; | |
6149 | ||
6150 | #ifdef ATTN_DESC | |
6151 | static const char *prs_prty_attn_desc[75] = { | |
6152 | "prs_cam_parity", | |
6153 | "prs_gft_cam_parity", | |
6154 | "prs_mem011_i_ecc_rf_int", | |
6155 | "prs_mem012_i_ecc_rf_int", | |
6156 | "prs_mem016_i_ecc_rf_int", | |
6157 | "prs_mem017_i_ecc_rf_int", | |
6158 | "prs_mem021_i_ecc_rf_int", | |
6159 | "prs_mem022_i_ecc_rf_int", | |
6160 | "prs_mem026_i_ecc_rf_int", | |
6161 | "prs_mem027_i_ecc_rf_int", | |
6162 | "prs_mem064_i_mem_prty", | |
6163 | "prs_mem044_i_mem_prty", | |
6164 | "prs_mem043_i_mem_prty", | |
6165 | "prs_mem037_i_mem_prty", | |
6166 | "prs_mem033_i_mem_prty", | |
6167 | "prs_mem034_i_mem_prty", | |
6168 | "prs_mem035_i_mem_prty", | |
6169 | "prs_mem036_i_mem_prty", | |
6170 | "prs_mem029_i_mem_prty", | |
6171 | "prs_mem030_i_mem_prty", | |
6172 | "prs_mem031_i_mem_prty", | |
6173 | "prs_mem032_i_mem_prty", | |
6174 | "prs_mem007_i_mem_prty", | |
6175 | "prs_mem028_i_mem_prty", | |
6176 | "prs_mem039_i_mem_prty", | |
6177 | "prs_mem040_i_mem_prty", | |
6178 | "prs_mem058_i_mem_prty", | |
6179 | "prs_mem059_i_mem_prty", | |
6180 | "prs_mem041_i_mem_prty", | |
6181 | "prs_mem042_i_mem_prty", | |
6182 | "prs_mem060_i_mem_prty", | |
6183 | "prs_mem061_i_mem_prty", | |
6184 | "prs_mem009_i_mem_prty", | |
6185 | "prs_mem009_i_ecc_rf_int", | |
6186 | "prs_mem010_i_ecc_rf_int", | |
6187 | "prs_mem014_i_ecc_rf_int", | |
6188 | "prs_mem015_i_ecc_rf_int", | |
6189 | "prs_mem026_i_mem_prty", | |
6190 | "prs_mem025_i_mem_prty", | |
6191 | "prs_mem021_i_mem_prty", | |
6192 | "prs_mem019_i_mem_prty", | |
6193 | "prs_mem020_i_mem_prty", | |
6194 | "prs_mem017_i_mem_prty", | |
6195 | "prs_mem018_i_mem_prty", | |
6196 | "prs_mem005_i_mem_prty", | |
6197 | "prs_mem016_i_mem_prty", | |
6198 | "prs_mem023_i_mem_prty", | |
6199 | "prs_mem024_i_mem_prty", | |
6200 | "prs_mem008_i_mem_prty", | |
6201 | "prs_mem012_i_mem_prty", | |
6202 | "prs_mem013_i_mem_prty", | |
6203 | "prs_mem006_i_mem_prty", | |
6204 | "prs_mem011_i_mem_prty", | |
6205 | "prs_mem003_i_mem_prty", | |
6206 | "prs_mem004_i_mem_prty", | |
6207 | "prs_mem027_i_mem_prty", | |
6208 | "prs_mem010_i_mem_prty", | |
6209 | "prs_mem014_i_mem_prty", | |
6210 | "prs_mem015_i_mem_prty", | |
6211 | "prs_mem054_i_mem_prty", | |
6212 | "prs_mem055_i_mem_prty", | |
6213 | "prs_mem056_i_mem_prty", | |
6214 | "prs_mem057_i_mem_prty", | |
6215 | "prs_mem046_i_mem_prty", | |
6216 | "prs_mem047_i_mem_prty", | |
6217 | "prs_mem048_i_mem_prty", | |
6218 | "prs_mem049_i_mem_prty", | |
6219 | "prs_mem050_i_mem_prty", | |
6220 | "prs_mem051_i_mem_prty", | |
6221 | "prs_mem052_i_mem_prty", | |
6222 | "prs_mem053_i_mem_prty", | |
6223 | "prs_mem062_i_mem_prty", | |
6224 | "prs_mem045_i_mem_prty", | |
6225 | "prs_mem002_i_mem_prty", | |
6226 | "prs_mem001_i_mem_prty", | |
6227 | }; | |
6228 | #else | |
6229 | #define prs_prty_attn_desc OSAL_NULL | |
6230 | #endif | |
6231 | ||
6232 | static const u16 prs_prty0_bb_a0_attn_idx[1] = { | |
6233 | 0, | |
6234 | }; | |
6235 | ||
6236 | static struct attn_hw_reg prs_prty0_bb_a0 = { | |
6237 | 0, 1, prs_prty0_bb_a0_attn_idx, 0x1f0050, 0x1f005c, 0x1f0058, 0x1f0054 | |
6238 | }; | |
6239 | ||
6240 | static const u16 prs_prty1_bb_a0_attn_idx[31] = { | |
6241 | 13, 14, 15, 16, 18, 21, 22, 23, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, | |
6242 | 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, | |
6243 | }; | |
6244 | ||
6245 | static struct attn_hw_reg prs_prty1_bb_a0 = { | |
6246 | 1, 31, prs_prty1_bb_a0_attn_idx, 0x1f0204, 0x1f0210, 0x1f020c, 0x1f0208 | |
6247 | }; | |
6248 | ||
6249 | static const u16 prs_prty2_bb_a0_attn_idx[5] = { | |
6250 | 73, 74, 20, 17, 19, | |
6251 | }; | |
6252 | ||
6253 | static struct attn_hw_reg prs_prty2_bb_a0 = { | |
6254 | 2, 5, prs_prty2_bb_a0_attn_idx, 0x1f0214, 0x1f0220, 0x1f021c, 0x1f0218 | |
6255 | }; | |
6256 | ||
6257 | static struct attn_hw_reg *prs_prty_bb_a0_regs[3] = { | |
6258 | &prs_prty0_bb_a0, &prs_prty1_bb_a0, &prs_prty2_bb_a0, | |
6259 | }; | |
6260 | ||
6261 | static const u16 prs_prty0_bb_b0_attn_idx[2] = { | |
6262 | 0, 1, | |
6263 | }; | |
6264 | ||
6265 | static struct attn_hw_reg prs_prty0_bb_b0 = { | |
6266 | 0, 2, prs_prty0_bb_b0_attn_idx, 0x1f0050, 0x1f005c, 0x1f0058, 0x1f0054 | |
6267 | }; | |
6268 | ||
6269 | static const u16 prs_prty1_bb_b0_attn_idx[31] = { | |
6270 | 13, 14, 15, 16, 18, 19, 21, 22, 23, 33, 34, 35, 36, 37, 38, 39, 40, 41, | |
6271 | 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, | |
6272 | }; | |
6273 | ||
6274 | static struct attn_hw_reg prs_prty1_bb_b0 = { | |
6275 | 1, 31, prs_prty1_bb_b0_attn_idx, 0x1f0204, 0x1f0210, 0x1f020c, 0x1f0208 | |
6276 | }; | |
6277 | ||
6278 | static const u16 prs_prty2_bb_b0_attn_idx[5] = { | |
6279 | 73, 74, 20, 17, 55, | |
6280 | }; | |
6281 | ||
6282 | static struct attn_hw_reg prs_prty2_bb_b0 = { | |
6283 | 2, 5, prs_prty2_bb_b0_attn_idx, 0x1f0214, 0x1f0220, 0x1f021c, 0x1f0218 | |
6284 | }; | |
6285 | ||
6286 | static struct attn_hw_reg *prs_prty_bb_b0_regs[3] = { | |
6287 | &prs_prty0_bb_b0, &prs_prty1_bb_b0, &prs_prty2_bb_b0, | |
6288 | }; | |
6289 | ||
6290 | static const u16 prs_prty0_k2_attn_idx[2] = { | |
6291 | 0, 1, | |
6292 | }; | |
6293 | ||
6294 | static struct attn_hw_reg prs_prty0_k2 = { | |
6295 | 0, 2, prs_prty0_k2_attn_idx, 0x1f0050, 0x1f005c, 0x1f0058, 0x1f0054 | |
6296 | }; | |
6297 | ||
6298 | static const u16 prs_prty1_k2_attn_idx[31] = { | |
6299 | 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, | |
6300 | 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, | |
6301 | }; | |
6302 | ||
6303 | static struct attn_hw_reg prs_prty1_k2 = { | |
6304 | 1, 31, prs_prty1_k2_attn_idx, 0x1f0204, 0x1f0210, 0x1f020c, 0x1f0208 | |
6305 | }; | |
6306 | ||
6307 | static const u16 prs_prty2_k2_attn_idx[31] = { | |
6308 | 56, 57, 58, 40, 41, 47, 38, 48, 50, 43, 46, 59, 60, 61, 62, 53, 54, 44, | |
6309 | 51, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, | |
6310 | }; | |
6311 | ||
6312 | static struct attn_hw_reg prs_prty2_k2 = { | |
6313 | 2, 31, prs_prty2_k2_attn_idx, 0x1f0214, 0x1f0220, 0x1f021c, 0x1f0218 | |
6314 | }; | |
6315 | ||
6316 | static struct attn_hw_reg *prs_prty_k2_regs[3] = { | |
6317 | &prs_prty0_k2, &prs_prty1_k2, &prs_prty2_k2, | |
6318 | }; | |
6319 | ||
6320 | #ifdef ATTN_DESC | |
6321 | static const char *tsdm_int_attn_desc[28] = { | |
6322 | "tsdm_address_error", | |
6323 | "tsdm_inp_queue_error", | |
6324 | "tsdm_delay_fifo_error", | |
6325 | "tsdm_async_host_error", | |
6326 | "tsdm_prm_fifo_error", | |
6327 | "tsdm_ccfc_load_pend_error", | |
6328 | "tsdm_tcfc_load_pend_error", | |
6329 | "tsdm_dst_int_ram_wait_error", | |
6330 | "tsdm_dst_pas_buf_wait_error", | |
6331 | "tsdm_dst_pxp_immed_error", | |
6332 | "tsdm_dst_pxp_dst_pend_error", | |
6333 | "tsdm_dst_brb_src_pend_error", | |
6334 | "tsdm_dst_brb_src_addr_error", | |
6335 | "tsdm_rsp_brb_pend_error", | |
6336 | "tsdm_rsp_int_ram_pend_error", | |
6337 | "tsdm_rsp_brb_rd_data_error", | |
6338 | "tsdm_rsp_int_ram_rd_data_error", | |
6339 | "tsdm_rsp_pxp_rd_data_error", | |
6340 | "tsdm_cm_delay_error", | |
6341 | "tsdm_sh_delay_error", | |
6342 | "tsdm_cmpl_pend_error", | |
6343 | "tsdm_cprm_pend_error", | |
6344 | "tsdm_timer_addr_error", | |
6345 | "tsdm_timer_pend_error", | |
6346 | "tsdm_dorq_dpm_error", | |
6347 | "tsdm_dst_pxp_done_error", | |
6348 | "tsdm_xcm_rmt_buffer_error", | |
6349 | "tsdm_ycm_rmt_buffer_error", | |
6350 | }; | |
6351 | #else | |
6352 | #define tsdm_int_attn_desc OSAL_NULL | |
6353 | #endif | |
6354 | ||
6355 | static const u16 tsdm_int0_bb_a0_attn_idx[26] = { | |
6356 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
6357 | 20, | |
6358 | 21, 22, 23, 24, 25, | |
6359 | }; | |
6360 | ||
6361 | static struct attn_hw_reg tsdm_int0_bb_a0 = { | |
6362 | 0, 26, tsdm_int0_bb_a0_attn_idx, 0xfb0040, 0xfb004c, 0xfb0048, 0xfb0044 | |
6363 | }; | |
6364 | ||
6365 | static struct attn_hw_reg *tsdm_int_bb_a0_regs[1] = { | |
6366 | &tsdm_int0_bb_a0, | |
6367 | }; | |
6368 | ||
6369 | static const u16 tsdm_int0_bb_b0_attn_idx[26] = { | |
6370 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
6371 | 20, | |
6372 | 21, 22, 23, 24, 25, | |
6373 | }; | |
6374 | ||
6375 | static struct attn_hw_reg tsdm_int0_bb_b0 = { | |
6376 | 0, 26, tsdm_int0_bb_b0_attn_idx, 0xfb0040, 0xfb004c, 0xfb0048, 0xfb0044 | |
6377 | }; | |
6378 | ||
6379 | static struct attn_hw_reg *tsdm_int_bb_b0_regs[1] = { | |
6380 | &tsdm_int0_bb_b0, | |
6381 | }; | |
6382 | ||
6383 | static const u16 tsdm_int0_k2_attn_idx[28] = { | |
6384 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
6385 | 20, | |
6386 | 21, 22, 23, 24, 25, 26, 27, | |
6387 | }; | |
6388 | ||
6389 | static struct attn_hw_reg tsdm_int0_k2 = { | |
6390 | 0, 28, tsdm_int0_k2_attn_idx, 0xfb0040, 0xfb004c, 0xfb0048, 0xfb0044 | |
6391 | }; | |
6392 | ||
6393 | static struct attn_hw_reg *tsdm_int_k2_regs[1] = { | |
6394 | &tsdm_int0_k2, | |
6395 | }; | |
6396 | ||
6397 | #ifdef ATTN_DESC | |
6398 | static const char *tsdm_prty_attn_desc[10] = { | |
6399 | "tsdm_mem009_i_mem_prty", | |
6400 | "tsdm_mem008_i_mem_prty", | |
6401 | "tsdm_mem007_i_mem_prty", | |
6402 | "tsdm_mem006_i_mem_prty", | |
6403 | "tsdm_mem005_i_mem_prty", | |
6404 | "tsdm_mem002_i_mem_prty", | |
6405 | "tsdm_mem010_i_mem_prty", | |
6406 | "tsdm_mem001_i_mem_prty", | |
6407 | "tsdm_mem003_i_mem_prty", | |
6408 | "tsdm_mem004_i_mem_prty", | |
6409 | }; | |
6410 | #else | |
6411 | #define tsdm_prty_attn_desc OSAL_NULL | |
6412 | #endif | |
6413 | ||
6414 | static const u16 tsdm_prty1_bb_a0_attn_idx[10] = { | |
6415 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, | |
6416 | }; | |
6417 | ||
6418 | static struct attn_hw_reg tsdm_prty1_bb_a0 = { | |
6419 | 0, 10, tsdm_prty1_bb_a0_attn_idx, 0xfb0200, 0xfb020c, 0xfb0208, | |
6420 | 0xfb0204 | |
6421 | }; | |
6422 | ||
6423 | static struct attn_hw_reg *tsdm_prty_bb_a0_regs[1] = { | |
6424 | &tsdm_prty1_bb_a0, | |
6425 | }; | |
6426 | ||
6427 | static const u16 tsdm_prty1_bb_b0_attn_idx[10] = { | |
6428 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, | |
6429 | }; | |
6430 | ||
6431 | static struct attn_hw_reg tsdm_prty1_bb_b0 = { | |
6432 | 0, 10, tsdm_prty1_bb_b0_attn_idx, 0xfb0200, 0xfb020c, 0xfb0208, | |
6433 | 0xfb0204 | |
6434 | }; | |
6435 | ||
6436 | static struct attn_hw_reg *tsdm_prty_bb_b0_regs[1] = { | |
6437 | &tsdm_prty1_bb_b0, | |
6438 | }; | |
6439 | ||
6440 | static const u16 tsdm_prty1_k2_attn_idx[10] = { | |
6441 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, | |
6442 | }; | |
6443 | ||
6444 | static struct attn_hw_reg tsdm_prty1_k2 = { | |
6445 | 0, 10, tsdm_prty1_k2_attn_idx, 0xfb0200, 0xfb020c, 0xfb0208, 0xfb0204 | |
6446 | }; | |
6447 | ||
6448 | static struct attn_hw_reg *tsdm_prty_k2_regs[1] = { | |
6449 | &tsdm_prty1_k2, | |
6450 | }; | |
6451 | ||
6452 | #ifdef ATTN_DESC | |
6453 | static const char *msdm_int_attn_desc[28] = { | |
6454 | "msdm_address_error", | |
6455 | "msdm_inp_queue_error", | |
6456 | "msdm_delay_fifo_error", | |
6457 | "msdm_async_host_error", | |
6458 | "msdm_prm_fifo_error", | |
6459 | "msdm_ccfc_load_pend_error", | |
6460 | "msdm_tcfc_load_pend_error", | |
6461 | "msdm_dst_int_ram_wait_error", | |
6462 | "msdm_dst_pas_buf_wait_error", | |
6463 | "msdm_dst_pxp_immed_error", | |
6464 | "msdm_dst_pxp_dst_pend_error", | |
6465 | "msdm_dst_brb_src_pend_error", | |
6466 | "msdm_dst_brb_src_addr_error", | |
6467 | "msdm_rsp_brb_pend_error", | |
6468 | "msdm_rsp_int_ram_pend_error", | |
6469 | "msdm_rsp_brb_rd_data_error", | |
6470 | "msdm_rsp_int_ram_rd_data_error", | |
6471 | "msdm_rsp_pxp_rd_data_error", | |
6472 | "msdm_cm_delay_error", | |
6473 | "msdm_sh_delay_error", | |
6474 | "msdm_cmpl_pend_error", | |
6475 | "msdm_cprm_pend_error", | |
6476 | "msdm_timer_addr_error", | |
6477 | "msdm_timer_pend_error", | |
6478 | "msdm_dorq_dpm_error", | |
6479 | "msdm_dst_pxp_done_error", | |
6480 | "msdm_xcm_rmt_buffer_error", | |
6481 | "msdm_ycm_rmt_buffer_error", | |
6482 | }; | |
6483 | #else | |
6484 | #define msdm_int_attn_desc OSAL_NULL | |
6485 | #endif | |
6486 | ||
6487 | static const u16 msdm_int0_bb_a0_attn_idx[26] = { | |
6488 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
6489 | 20, | |
6490 | 21, 22, 23, 24, 25, | |
6491 | }; | |
6492 | ||
6493 | static struct attn_hw_reg msdm_int0_bb_a0 = { | |
6494 | 0, 26, msdm_int0_bb_a0_attn_idx, 0xfc0040, 0xfc004c, 0xfc0048, 0xfc0044 | |
6495 | }; | |
6496 | ||
6497 | static struct attn_hw_reg *msdm_int_bb_a0_regs[1] = { | |
6498 | &msdm_int0_bb_a0, | |
6499 | }; | |
6500 | ||
6501 | static const u16 msdm_int0_bb_b0_attn_idx[26] = { | |
6502 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
6503 | 20, | |
6504 | 21, 22, 23, 24, 25, | |
6505 | }; | |
6506 | ||
6507 | static struct attn_hw_reg msdm_int0_bb_b0 = { | |
6508 | 0, 26, msdm_int0_bb_b0_attn_idx, 0xfc0040, 0xfc004c, 0xfc0048, 0xfc0044 | |
6509 | }; | |
6510 | ||
6511 | static struct attn_hw_reg *msdm_int_bb_b0_regs[1] = { | |
6512 | &msdm_int0_bb_b0, | |
6513 | }; | |
6514 | ||
6515 | static const u16 msdm_int0_k2_attn_idx[28] = { | |
6516 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
6517 | 20, | |
6518 | 21, 22, 23, 24, 25, 26, 27, | |
6519 | }; | |
6520 | ||
6521 | static struct attn_hw_reg msdm_int0_k2 = { | |
6522 | 0, 28, msdm_int0_k2_attn_idx, 0xfc0040, 0xfc004c, 0xfc0048, 0xfc0044 | |
6523 | }; | |
6524 | ||
6525 | static struct attn_hw_reg *msdm_int_k2_regs[1] = { | |
6526 | &msdm_int0_k2, | |
6527 | }; | |
6528 | ||
6529 | #ifdef ATTN_DESC | |
6530 | static const char *msdm_prty_attn_desc[11] = { | |
6531 | "msdm_mem009_i_mem_prty", | |
6532 | "msdm_mem008_i_mem_prty", | |
6533 | "msdm_mem007_i_mem_prty", | |
6534 | "msdm_mem006_i_mem_prty", | |
6535 | "msdm_mem005_i_mem_prty", | |
6536 | "msdm_mem002_i_mem_prty", | |
6537 | "msdm_mem011_i_mem_prty", | |
6538 | "msdm_mem001_i_mem_prty", | |
6539 | "msdm_mem003_i_mem_prty", | |
6540 | "msdm_mem004_i_mem_prty", | |
6541 | "msdm_mem010_i_mem_prty", | |
6542 | }; | |
6543 | #else | |
6544 | #define msdm_prty_attn_desc OSAL_NULL | |
6545 | #endif | |
6546 | ||
6547 | static const u16 msdm_prty1_bb_a0_attn_idx[11] = { | |
6548 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, | |
6549 | }; | |
6550 | ||
6551 | static struct attn_hw_reg msdm_prty1_bb_a0 = { | |
6552 | 0, 11, msdm_prty1_bb_a0_attn_idx, 0xfc0200, 0xfc020c, 0xfc0208, | |
6553 | 0xfc0204 | |
6554 | }; | |
6555 | ||
6556 | static struct attn_hw_reg *msdm_prty_bb_a0_regs[1] = { | |
6557 | &msdm_prty1_bb_a0, | |
6558 | }; | |
6559 | ||
6560 | static const u16 msdm_prty1_bb_b0_attn_idx[11] = { | |
6561 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, | |
6562 | }; | |
6563 | ||
6564 | static struct attn_hw_reg msdm_prty1_bb_b0 = { | |
6565 | 0, 11, msdm_prty1_bb_b0_attn_idx, 0xfc0200, 0xfc020c, 0xfc0208, | |
6566 | 0xfc0204 | |
6567 | }; | |
6568 | ||
6569 | static struct attn_hw_reg *msdm_prty_bb_b0_regs[1] = { | |
6570 | &msdm_prty1_bb_b0, | |
6571 | }; | |
6572 | ||
6573 | static const u16 msdm_prty1_k2_attn_idx[11] = { | |
6574 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, | |
6575 | }; | |
6576 | ||
6577 | static struct attn_hw_reg msdm_prty1_k2 = { | |
6578 | 0, 11, msdm_prty1_k2_attn_idx, 0xfc0200, 0xfc020c, 0xfc0208, 0xfc0204 | |
6579 | }; | |
6580 | ||
6581 | static struct attn_hw_reg *msdm_prty_k2_regs[1] = { | |
6582 | &msdm_prty1_k2, | |
6583 | }; | |
6584 | ||
6585 | #ifdef ATTN_DESC | |
6586 | static const char *usdm_int_attn_desc[28] = { | |
6587 | "usdm_address_error", | |
6588 | "usdm_inp_queue_error", | |
6589 | "usdm_delay_fifo_error", | |
6590 | "usdm_async_host_error", | |
6591 | "usdm_prm_fifo_error", | |
6592 | "usdm_ccfc_load_pend_error", | |
6593 | "usdm_tcfc_load_pend_error", | |
6594 | "usdm_dst_int_ram_wait_error", | |
6595 | "usdm_dst_pas_buf_wait_error", | |
6596 | "usdm_dst_pxp_immed_error", | |
6597 | "usdm_dst_pxp_dst_pend_error", | |
6598 | "usdm_dst_brb_src_pend_error", | |
6599 | "usdm_dst_brb_src_addr_error", | |
6600 | "usdm_rsp_brb_pend_error", | |
6601 | "usdm_rsp_int_ram_pend_error", | |
6602 | "usdm_rsp_brb_rd_data_error", | |
6603 | "usdm_rsp_int_ram_rd_data_error", | |
6604 | "usdm_rsp_pxp_rd_data_error", | |
6605 | "usdm_cm_delay_error", | |
6606 | "usdm_sh_delay_error", | |
6607 | "usdm_cmpl_pend_error", | |
6608 | "usdm_cprm_pend_error", | |
6609 | "usdm_timer_addr_error", | |
6610 | "usdm_timer_pend_error", | |
6611 | "usdm_dorq_dpm_error", | |
6612 | "usdm_dst_pxp_done_error", | |
6613 | "usdm_xcm_rmt_buffer_error", | |
6614 | "usdm_ycm_rmt_buffer_error", | |
6615 | }; | |
6616 | #else | |
6617 | #define usdm_int_attn_desc OSAL_NULL | |
6618 | #endif | |
6619 | ||
6620 | static const u16 usdm_int0_bb_a0_attn_idx[26] = { | |
6621 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
6622 | 20, | |
6623 | 21, 22, 23, 24, 25, | |
6624 | }; | |
6625 | ||
6626 | static struct attn_hw_reg usdm_int0_bb_a0 = { | |
6627 | 0, 26, usdm_int0_bb_a0_attn_idx, 0xfd0040, 0xfd004c, 0xfd0048, 0xfd0044 | |
6628 | }; | |
6629 | ||
6630 | static struct attn_hw_reg *usdm_int_bb_a0_regs[1] = { | |
6631 | &usdm_int0_bb_a0, | |
6632 | }; | |
6633 | ||
6634 | static const u16 usdm_int0_bb_b0_attn_idx[26] = { | |
6635 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
6636 | 20, | |
6637 | 21, 22, 23, 24, 25, | |
6638 | }; | |
6639 | ||
6640 | static struct attn_hw_reg usdm_int0_bb_b0 = { | |
6641 | 0, 26, usdm_int0_bb_b0_attn_idx, 0xfd0040, 0xfd004c, 0xfd0048, 0xfd0044 | |
6642 | }; | |
6643 | ||
6644 | static struct attn_hw_reg *usdm_int_bb_b0_regs[1] = { | |
6645 | &usdm_int0_bb_b0, | |
6646 | }; | |
6647 | ||
6648 | static const u16 usdm_int0_k2_attn_idx[28] = { | |
6649 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
6650 | 20, | |
6651 | 21, 22, 23, 24, 25, 26, 27, | |
6652 | }; | |
6653 | ||
6654 | static struct attn_hw_reg usdm_int0_k2 = { | |
6655 | 0, 28, usdm_int0_k2_attn_idx, 0xfd0040, 0xfd004c, 0xfd0048, 0xfd0044 | |
6656 | }; | |
6657 | ||
6658 | static struct attn_hw_reg *usdm_int_k2_regs[1] = { | |
6659 | &usdm_int0_k2, | |
6660 | }; | |
6661 | ||
6662 | #ifdef ATTN_DESC | |
6663 | static const char *usdm_prty_attn_desc[10] = { | |
6664 | "usdm_mem008_i_mem_prty", | |
6665 | "usdm_mem007_i_mem_prty", | |
6666 | "usdm_mem006_i_mem_prty", | |
6667 | "usdm_mem005_i_mem_prty", | |
6668 | "usdm_mem002_i_mem_prty", | |
6669 | "usdm_mem010_i_mem_prty", | |
6670 | "usdm_mem001_i_mem_prty", | |
6671 | "usdm_mem003_i_mem_prty", | |
6672 | "usdm_mem004_i_mem_prty", | |
6673 | "usdm_mem009_i_mem_prty", | |
6674 | }; | |
6675 | #else | |
6676 | #define usdm_prty_attn_desc OSAL_NULL | |
6677 | #endif | |
6678 | ||
6679 | static const u16 usdm_prty1_bb_a0_attn_idx[10] = { | |
6680 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, | |
6681 | }; | |
6682 | ||
6683 | static struct attn_hw_reg usdm_prty1_bb_a0 = { | |
6684 | 0, 10, usdm_prty1_bb_a0_attn_idx, 0xfd0200, 0xfd020c, 0xfd0208, | |
6685 | 0xfd0204 | |
6686 | }; | |
6687 | ||
6688 | static struct attn_hw_reg *usdm_prty_bb_a0_regs[1] = { | |
6689 | &usdm_prty1_bb_a0, | |
6690 | }; | |
6691 | ||
6692 | static const u16 usdm_prty1_bb_b0_attn_idx[10] = { | |
6693 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, | |
6694 | }; | |
6695 | ||
6696 | static struct attn_hw_reg usdm_prty1_bb_b0 = { | |
6697 | 0, 10, usdm_prty1_bb_b0_attn_idx, 0xfd0200, 0xfd020c, 0xfd0208, | |
6698 | 0xfd0204 | |
6699 | }; | |
6700 | ||
6701 | static struct attn_hw_reg *usdm_prty_bb_b0_regs[1] = { | |
6702 | &usdm_prty1_bb_b0, | |
6703 | }; | |
6704 | ||
6705 | static const u16 usdm_prty1_k2_attn_idx[10] = { | |
6706 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, | |
6707 | }; | |
6708 | ||
6709 | static struct attn_hw_reg usdm_prty1_k2 = { | |
6710 | 0, 10, usdm_prty1_k2_attn_idx, 0xfd0200, 0xfd020c, 0xfd0208, 0xfd0204 | |
6711 | }; | |
6712 | ||
6713 | static struct attn_hw_reg *usdm_prty_k2_regs[1] = { | |
6714 | &usdm_prty1_k2, | |
6715 | }; | |
6716 | ||
6717 | #ifdef ATTN_DESC | |
6718 | static const char *xsdm_int_attn_desc[28] = { | |
6719 | "xsdm_address_error", | |
6720 | "xsdm_inp_queue_error", | |
6721 | "xsdm_delay_fifo_error", | |
6722 | "xsdm_async_host_error", | |
6723 | "xsdm_prm_fifo_error", | |
6724 | "xsdm_ccfc_load_pend_error", | |
6725 | "xsdm_tcfc_load_pend_error", | |
6726 | "xsdm_dst_int_ram_wait_error", | |
6727 | "xsdm_dst_pas_buf_wait_error", | |
6728 | "xsdm_dst_pxp_immed_error", | |
6729 | "xsdm_dst_pxp_dst_pend_error", | |
6730 | "xsdm_dst_brb_src_pend_error", | |
6731 | "xsdm_dst_brb_src_addr_error", | |
6732 | "xsdm_rsp_brb_pend_error", | |
6733 | "xsdm_rsp_int_ram_pend_error", | |
6734 | "xsdm_rsp_brb_rd_data_error", | |
6735 | "xsdm_rsp_int_ram_rd_data_error", | |
6736 | "xsdm_rsp_pxp_rd_data_error", | |
6737 | "xsdm_cm_delay_error", | |
6738 | "xsdm_sh_delay_error", | |
6739 | "xsdm_cmpl_pend_error", | |
6740 | "xsdm_cprm_pend_error", | |
6741 | "xsdm_timer_addr_error", | |
6742 | "xsdm_timer_pend_error", | |
6743 | "xsdm_dorq_dpm_error", | |
6744 | "xsdm_dst_pxp_done_error", | |
6745 | "xsdm_xcm_rmt_buffer_error", | |
6746 | "xsdm_ycm_rmt_buffer_error", | |
6747 | }; | |
6748 | #else | |
6749 | #define xsdm_int_attn_desc OSAL_NULL | |
6750 | #endif | |
6751 | ||
6752 | static const u16 xsdm_int0_bb_a0_attn_idx[26] = { | |
6753 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
6754 | 20, | |
6755 | 21, 22, 23, 24, 25, | |
6756 | }; | |
6757 | ||
6758 | static struct attn_hw_reg xsdm_int0_bb_a0 = { | |
6759 | 0, 26, xsdm_int0_bb_a0_attn_idx, 0xf80040, 0xf8004c, 0xf80048, 0xf80044 | |
6760 | }; | |
6761 | ||
6762 | static struct attn_hw_reg *xsdm_int_bb_a0_regs[1] = { | |
6763 | &xsdm_int0_bb_a0, | |
6764 | }; | |
6765 | ||
6766 | static const u16 xsdm_int0_bb_b0_attn_idx[26] = { | |
6767 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
6768 | 20, | |
6769 | 21, 22, 23, 24, 25, | |
6770 | }; | |
6771 | ||
6772 | static struct attn_hw_reg xsdm_int0_bb_b0 = { | |
6773 | 0, 26, xsdm_int0_bb_b0_attn_idx, 0xf80040, 0xf8004c, 0xf80048, 0xf80044 | |
6774 | }; | |
6775 | ||
6776 | static struct attn_hw_reg *xsdm_int_bb_b0_regs[1] = { | |
6777 | &xsdm_int0_bb_b0, | |
6778 | }; | |
6779 | ||
6780 | static const u16 xsdm_int0_k2_attn_idx[28] = { | |
6781 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
6782 | 20, | |
6783 | 21, 22, 23, 24, 25, 26, 27, | |
6784 | }; | |
6785 | ||
6786 | static struct attn_hw_reg xsdm_int0_k2 = { | |
6787 | 0, 28, xsdm_int0_k2_attn_idx, 0xf80040, 0xf8004c, 0xf80048, 0xf80044 | |
6788 | }; | |
6789 | ||
6790 | static struct attn_hw_reg *xsdm_int_k2_regs[1] = { | |
6791 | &xsdm_int0_k2, | |
6792 | }; | |
6793 | ||
6794 | #ifdef ATTN_DESC | |
6795 | static const char *xsdm_prty_attn_desc[10] = { | |
6796 | "xsdm_mem009_i_mem_prty", | |
6797 | "xsdm_mem008_i_mem_prty", | |
6798 | "xsdm_mem007_i_mem_prty", | |
6799 | "xsdm_mem006_i_mem_prty", | |
6800 | "xsdm_mem003_i_mem_prty", | |
6801 | "xsdm_mem010_i_mem_prty", | |
6802 | "xsdm_mem002_i_mem_prty", | |
6803 | "xsdm_mem004_i_mem_prty", | |
6804 | "xsdm_mem005_i_mem_prty", | |
6805 | "xsdm_mem001_i_mem_prty", | |
6806 | }; | |
6807 | #else | |
6808 | #define xsdm_prty_attn_desc OSAL_NULL | |
6809 | #endif | |
6810 | ||
6811 | static const u16 xsdm_prty1_bb_a0_attn_idx[10] = { | |
6812 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, | |
6813 | }; | |
6814 | ||
6815 | static struct attn_hw_reg xsdm_prty1_bb_a0 = { | |
6816 | 0, 10, xsdm_prty1_bb_a0_attn_idx, 0xf80200, 0xf8020c, 0xf80208, | |
6817 | 0xf80204 | |
6818 | }; | |
6819 | ||
6820 | static struct attn_hw_reg *xsdm_prty_bb_a0_regs[1] = { | |
6821 | &xsdm_prty1_bb_a0, | |
6822 | }; | |
6823 | ||
6824 | static const u16 xsdm_prty1_bb_b0_attn_idx[10] = { | |
6825 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, | |
6826 | }; | |
6827 | ||
6828 | static struct attn_hw_reg xsdm_prty1_bb_b0 = { | |
6829 | 0, 10, xsdm_prty1_bb_b0_attn_idx, 0xf80200, 0xf8020c, 0xf80208, | |
6830 | 0xf80204 | |
6831 | }; | |
6832 | ||
6833 | static struct attn_hw_reg *xsdm_prty_bb_b0_regs[1] = { | |
6834 | &xsdm_prty1_bb_b0, | |
6835 | }; | |
6836 | ||
6837 | static const u16 xsdm_prty1_k2_attn_idx[10] = { | |
6838 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, | |
6839 | }; | |
6840 | ||
6841 | static struct attn_hw_reg xsdm_prty1_k2 = { | |
6842 | 0, 10, xsdm_prty1_k2_attn_idx, 0xf80200, 0xf8020c, 0xf80208, 0xf80204 | |
6843 | }; | |
6844 | ||
6845 | static struct attn_hw_reg *xsdm_prty_k2_regs[1] = { | |
6846 | &xsdm_prty1_k2, | |
6847 | }; | |
6848 | ||
6849 | #ifdef ATTN_DESC | |
6850 | static const char *ysdm_int_attn_desc[28] = { | |
6851 | "ysdm_address_error", | |
6852 | "ysdm_inp_queue_error", | |
6853 | "ysdm_delay_fifo_error", | |
6854 | "ysdm_async_host_error", | |
6855 | "ysdm_prm_fifo_error", | |
6856 | "ysdm_ccfc_load_pend_error", | |
6857 | "ysdm_tcfc_load_pend_error", | |
6858 | "ysdm_dst_int_ram_wait_error", | |
6859 | "ysdm_dst_pas_buf_wait_error", | |
6860 | "ysdm_dst_pxp_immed_error", | |
6861 | "ysdm_dst_pxp_dst_pend_error", | |
6862 | "ysdm_dst_brb_src_pend_error", | |
6863 | "ysdm_dst_brb_src_addr_error", | |
6864 | "ysdm_rsp_brb_pend_error", | |
6865 | "ysdm_rsp_int_ram_pend_error", | |
6866 | "ysdm_rsp_brb_rd_data_error", | |
6867 | "ysdm_rsp_int_ram_rd_data_error", | |
6868 | "ysdm_rsp_pxp_rd_data_error", | |
6869 | "ysdm_cm_delay_error", | |
6870 | "ysdm_sh_delay_error", | |
6871 | "ysdm_cmpl_pend_error", | |
6872 | "ysdm_cprm_pend_error", | |
6873 | "ysdm_timer_addr_error", | |
6874 | "ysdm_timer_pend_error", | |
6875 | "ysdm_dorq_dpm_error", | |
6876 | "ysdm_dst_pxp_done_error", | |
6877 | "ysdm_xcm_rmt_buffer_error", | |
6878 | "ysdm_ycm_rmt_buffer_error", | |
6879 | }; | |
6880 | #else | |
6881 | #define ysdm_int_attn_desc OSAL_NULL | |
6882 | #endif | |
6883 | ||
6884 | static const u16 ysdm_int0_bb_a0_attn_idx[26] = { | |
6885 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
6886 | 20, | |
6887 | 21, 22, 23, 24, 25, | |
6888 | }; | |
6889 | ||
6890 | static struct attn_hw_reg ysdm_int0_bb_a0 = { | |
6891 | 0, 26, ysdm_int0_bb_a0_attn_idx, 0xf90040, 0xf9004c, 0xf90048, 0xf90044 | |
6892 | }; | |
6893 | ||
6894 | static struct attn_hw_reg *ysdm_int_bb_a0_regs[1] = { | |
6895 | &ysdm_int0_bb_a0, | |
6896 | }; | |
6897 | ||
6898 | static const u16 ysdm_int0_bb_b0_attn_idx[26] = { | |
6899 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
6900 | 20, | |
6901 | 21, 22, 23, 24, 25, | |
6902 | }; | |
6903 | ||
6904 | static struct attn_hw_reg ysdm_int0_bb_b0 = { | |
6905 | 0, 26, ysdm_int0_bb_b0_attn_idx, 0xf90040, 0xf9004c, 0xf90048, 0xf90044 | |
6906 | }; | |
6907 | ||
6908 | static struct attn_hw_reg *ysdm_int_bb_b0_regs[1] = { | |
6909 | &ysdm_int0_bb_b0, | |
6910 | }; | |
6911 | ||
6912 | static const u16 ysdm_int0_k2_attn_idx[28] = { | |
6913 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
6914 | 20, | |
6915 | 21, 22, 23, 24, 25, 26, 27, | |
6916 | }; | |
6917 | ||
6918 | static struct attn_hw_reg ysdm_int0_k2 = { | |
6919 | 0, 28, ysdm_int0_k2_attn_idx, 0xf90040, 0xf9004c, 0xf90048, 0xf90044 | |
6920 | }; | |
6921 | ||
6922 | static struct attn_hw_reg *ysdm_int_k2_regs[1] = { | |
6923 | &ysdm_int0_k2, | |
6924 | }; | |
6925 | ||
6926 | #ifdef ATTN_DESC | |
6927 | static const char *ysdm_prty_attn_desc[9] = { | |
6928 | "ysdm_mem008_i_mem_prty", | |
6929 | "ysdm_mem007_i_mem_prty", | |
6930 | "ysdm_mem006_i_mem_prty", | |
6931 | "ysdm_mem005_i_mem_prty", | |
6932 | "ysdm_mem002_i_mem_prty", | |
6933 | "ysdm_mem009_i_mem_prty", | |
6934 | "ysdm_mem001_i_mem_prty", | |
6935 | "ysdm_mem003_i_mem_prty", | |
6936 | "ysdm_mem004_i_mem_prty", | |
6937 | }; | |
6938 | #else | |
6939 | #define ysdm_prty_attn_desc OSAL_NULL | |
6940 | #endif | |
6941 | ||
6942 | static const u16 ysdm_prty1_bb_a0_attn_idx[9] = { | |
6943 | 0, 1, 2, 3, 4, 5, 6, 7, 8, | |
6944 | }; | |
6945 | ||
6946 | static struct attn_hw_reg ysdm_prty1_bb_a0 = { | |
6947 | 0, 9, ysdm_prty1_bb_a0_attn_idx, 0xf90200, 0xf9020c, 0xf90208, 0xf90204 | |
6948 | }; | |
6949 | ||
6950 | static struct attn_hw_reg *ysdm_prty_bb_a0_regs[1] = { | |
6951 | &ysdm_prty1_bb_a0, | |
6952 | }; | |
6953 | ||
6954 | static const u16 ysdm_prty1_bb_b0_attn_idx[9] = { | |
6955 | 0, 1, 2, 3, 4, 5, 6, 7, 8, | |
6956 | }; | |
6957 | ||
6958 | static struct attn_hw_reg ysdm_prty1_bb_b0 = { | |
6959 | 0, 9, ysdm_prty1_bb_b0_attn_idx, 0xf90200, 0xf9020c, 0xf90208, 0xf90204 | |
6960 | }; | |
6961 | ||
6962 | static struct attn_hw_reg *ysdm_prty_bb_b0_regs[1] = { | |
6963 | &ysdm_prty1_bb_b0, | |
6964 | }; | |
6965 | ||
6966 | static const u16 ysdm_prty1_k2_attn_idx[9] = { | |
6967 | 0, 1, 2, 3, 4, 5, 6, 7, 8, | |
6968 | }; | |
6969 | ||
6970 | static struct attn_hw_reg ysdm_prty1_k2 = { | |
6971 | 0, 9, ysdm_prty1_k2_attn_idx, 0xf90200, 0xf9020c, 0xf90208, 0xf90204 | |
6972 | }; | |
6973 | ||
6974 | static struct attn_hw_reg *ysdm_prty_k2_regs[1] = { | |
6975 | &ysdm_prty1_k2, | |
6976 | }; | |
6977 | ||
6978 | #ifdef ATTN_DESC | |
6979 | static const char *psdm_int_attn_desc[28] = { | |
6980 | "psdm_address_error", | |
6981 | "psdm_inp_queue_error", | |
6982 | "psdm_delay_fifo_error", | |
6983 | "psdm_async_host_error", | |
6984 | "psdm_prm_fifo_error", | |
6985 | "psdm_ccfc_load_pend_error", | |
6986 | "psdm_tcfc_load_pend_error", | |
6987 | "psdm_dst_int_ram_wait_error", | |
6988 | "psdm_dst_pas_buf_wait_error", | |
6989 | "psdm_dst_pxp_immed_error", | |
6990 | "psdm_dst_pxp_dst_pend_error", | |
6991 | "psdm_dst_brb_src_pend_error", | |
6992 | "psdm_dst_brb_src_addr_error", | |
6993 | "psdm_rsp_brb_pend_error", | |
6994 | "psdm_rsp_int_ram_pend_error", | |
6995 | "psdm_rsp_brb_rd_data_error", | |
6996 | "psdm_rsp_int_ram_rd_data_error", | |
6997 | "psdm_rsp_pxp_rd_data_error", | |
6998 | "psdm_cm_delay_error", | |
6999 | "psdm_sh_delay_error", | |
7000 | "psdm_cmpl_pend_error", | |
7001 | "psdm_cprm_pend_error", | |
7002 | "psdm_timer_addr_error", | |
7003 | "psdm_timer_pend_error", | |
7004 | "psdm_dorq_dpm_error", | |
7005 | "psdm_dst_pxp_done_error", | |
7006 | "psdm_xcm_rmt_buffer_error", | |
7007 | "psdm_ycm_rmt_buffer_error", | |
7008 | }; | |
7009 | #else | |
7010 | #define psdm_int_attn_desc OSAL_NULL | |
7011 | #endif | |
7012 | ||
7013 | static const u16 psdm_int0_bb_a0_attn_idx[26] = { | |
7014 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
7015 | 20, | |
7016 | 21, 22, 23, 24, 25, | |
7017 | }; | |
7018 | ||
7019 | static struct attn_hw_reg psdm_int0_bb_a0 = { | |
7020 | 0, 26, psdm_int0_bb_a0_attn_idx, 0xfa0040, 0xfa004c, 0xfa0048, 0xfa0044 | |
7021 | }; | |
7022 | ||
7023 | static struct attn_hw_reg *psdm_int_bb_a0_regs[1] = { | |
7024 | &psdm_int0_bb_a0, | |
7025 | }; | |
7026 | ||
7027 | static const u16 psdm_int0_bb_b0_attn_idx[26] = { | |
7028 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
7029 | 20, | |
7030 | 21, 22, 23, 24, 25, | |
7031 | }; | |
7032 | ||
7033 | static struct attn_hw_reg psdm_int0_bb_b0 = { | |
7034 | 0, 26, psdm_int0_bb_b0_attn_idx, 0xfa0040, 0xfa004c, 0xfa0048, 0xfa0044 | |
7035 | }; | |
7036 | ||
7037 | static struct attn_hw_reg *psdm_int_bb_b0_regs[1] = { | |
7038 | &psdm_int0_bb_b0, | |
7039 | }; | |
7040 | ||
7041 | static const u16 psdm_int0_k2_attn_idx[28] = { | |
7042 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
7043 | 20, | |
7044 | 21, 22, 23, 24, 25, 26, 27, | |
7045 | }; | |
7046 | ||
7047 | static struct attn_hw_reg psdm_int0_k2 = { | |
7048 | 0, 28, psdm_int0_k2_attn_idx, 0xfa0040, 0xfa004c, 0xfa0048, 0xfa0044 | |
7049 | }; | |
7050 | ||
7051 | static struct attn_hw_reg *psdm_int_k2_regs[1] = { | |
7052 | &psdm_int0_k2, | |
7053 | }; | |
7054 | ||
7055 | #ifdef ATTN_DESC | |
7056 | static const char *psdm_prty_attn_desc[9] = { | |
7057 | "psdm_mem008_i_mem_prty", | |
7058 | "psdm_mem007_i_mem_prty", | |
7059 | "psdm_mem006_i_mem_prty", | |
7060 | "psdm_mem005_i_mem_prty", | |
7061 | "psdm_mem002_i_mem_prty", | |
7062 | "psdm_mem009_i_mem_prty", | |
7063 | "psdm_mem001_i_mem_prty", | |
7064 | "psdm_mem003_i_mem_prty", | |
7065 | "psdm_mem004_i_mem_prty", | |
7066 | }; | |
7067 | #else | |
7068 | #define psdm_prty_attn_desc OSAL_NULL | |
7069 | #endif | |
7070 | ||
7071 | static const u16 psdm_prty1_bb_a0_attn_idx[9] = { | |
7072 | 0, 1, 2, 3, 4, 5, 6, 7, 8, | |
7073 | }; | |
7074 | ||
7075 | static struct attn_hw_reg psdm_prty1_bb_a0 = { | |
7076 | 0, 9, psdm_prty1_bb_a0_attn_idx, 0xfa0200, 0xfa020c, 0xfa0208, 0xfa0204 | |
7077 | }; | |
7078 | ||
7079 | static struct attn_hw_reg *psdm_prty_bb_a0_regs[1] = { | |
7080 | &psdm_prty1_bb_a0, | |
7081 | }; | |
7082 | ||
7083 | static const u16 psdm_prty1_bb_b0_attn_idx[9] = { | |
7084 | 0, 1, 2, 3, 4, 5, 6, 7, 8, | |
7085 | }; | |
7086 | ||
7087 | static struct attn_hw_reg psdm_prty1_bb_b0 = { | |
7088 | 0, 9, psdm_prty1_bb_b0_attn_idx, 0xfa0200, 0xfa020c, 0xfa0208, 0xfa0204 | |
7089 | }; | |
7090 | ||
7091 | static struct attn_hw_reg *psdm_prty_bb_b0_regs[1] = { | |
7092 | &psdm_prty1_bb_b0, | |
7093 | }; | |
7094 | ||
7095 | static const u16 psdm_prty1_k2_attn_idx[9] = { | |
7096 | 0, 1, 2, 3, 4, 5, 6, 7, 8, | |
7097 | }; | |
7098 | ||
7099 | static struct attn_hw_reg psdm_prty1_k2 = { | |
7100 | 0, 9, psdm_prty1_k2_attn_idx, 0xfa0200, 0xfa020c, 0xfa0208, 0xfa0204 | |
7101 | }; | |
7102 | ||
7103 | static struct attn_hw_reg *psdm_prty_k2_regs[1] = { | |
7104 | &psdm_prty1_k2, | |
7105 | }; | |
7106 | ||
7107 | #ifdef ATTN_DESC | |
7108 | static const char *tsem_int_attn_desc[46] = { | |
7109 | "tsem_address_error", | |
7110 | "tsem_fic_last_error", | |
7111 | "tsem_fic_length_error", | |
7112 | "tsem_fic_fifo_error", | |
7113 | "tsem_pas_buf_fifo_error", | |
7114 | "tsem_sync_fin_pop_error", | |
7115 | "tsem_sync_dra_wr_push_error", | |
7116 | "tsem_sync_dra_wr_pop_error", | |
7117 | "tsem_sync_dra_rd_push_error", | |
7118 | "tsem_sync_dra_rd_pop_error", | |
7119 | "tsem_sync_fin_push_error", | |
7120 | "tsem_sem_fast_address_error", | |
7121 | "tsem_cam_lsb_inp_fifo", | |
7122 | "tsem_cam_msb_inp_fifo", | |
7123 | "tsem_cam_out_fifo", | |
7124 | "tsem_fin_fifo", | |
7125 | "tsem_thread_fifo_error", | |
7126 | "tsem_thread_overrun", | |
7127 | "tsem_sync_ext_store_push_error", | |
7128 | "tsem_sync_ext_store_pop_error", | |
7129 | "tsem_sync_ext_load_push_error", | |
7130 | "tsem_sync_ext_load_pop_error", | |
7131 | "tsem_sync_ram_rd_push_error", | |
7132 | "tsem_sync_ram_rd_pop_error", | |
7133 | "tsem_sync_ram_wr_pop_error", | |
7134 | "tsem_sync_ram_wr_push_error", | |
7135 | "tsem_sync_dbg_push_error", | |
7136 | "tsem_sync_dbg_pop_error", | |
7137 | "tsem_dbg_fifo_error", | |
7138 | "tsem_cam_msb2_inp_fifo", | |
7139 | "tsem_vfc_interrupt", | |
7140 | "tsem_vfc_out_fifo_error", | |
7141 | "tsem_storm_stack_uf_attn", | |
7142 | "tsem_storm_stack_of_attn", | |
7143 | "tsem_storm_runtime_error", | |
7144 | "tsem_ext_load_pend_wr_error", | |
7145 | "tsem_thread_rls_orun_error", | |
7146 | "tsem_thread_rls_aloc_error", | |
7147 | "tsem_thread_rls_vld_error", | |
7148 | "tsem_ext_thread_oor_error", | |
7149 | "tsem_ord_id_fifo_error", | |
7150 | "tsem_invld_foc_error", | |
7151 | "tsem_ext_ld_len_error", | |
7152 | "tsem_thrd_ord_fifo_error", | |
7153 | "tsem_invld_thrd_ord_error", | |
7154 | "tsem_fast_memory_address_error", | |
7155 | }; | |
7156 | #else | |
7157 | #define tsem_int_attn_desc OSAL_NULL | |
7158 | #endif | |
7159 | ||
7160 | static const u16 tsem_int0_bb_a0_attn_idx[32] = { | |
7161 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
7162 | 20, | |
7163 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
7164 | }; | |
7165 | ||
7166 | static struct attn_hw_reg tsem_int0_bb_a0 = { | |
7167 | 0, 32, tsem_int0_bb_a0_attn_idx, 0x1700040, 0x170004c, 0x1700048, | |
7168 | 0x1700044 | |
7169 | }; | |
7170 | ||
7171 | static const u16 tsem_int1_bb_a0_attn_idx[13] = { | |
7172 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, | |
7173 | }; | |
7174 | ||
7175 | static struct attn_hw_reg tsem_int1_bb_a0 = { | |
7176 | 1, 13, tsem_int1_bb_a0_attn_idx, 0x1700050, 0x170005c, 0x1700058, | |
7177 | 0x1700054 | |
7178 | }; | |
7179 | ||
7180 | static const u16 tsem_fast_memory_int0_bb_a0_attn_idx[1] = { | |
7181 | 45, | |
7182 | }; | |
7183 | ||
7184 | static struct attn_hw_reg tsem_fast_memory_int0_bb_a0 = { | |
7185 | 2, 1, tsem_fast_memory_int0_bb_a0_attn_idx, 0x1740040, 0x174004c, | |
7186 | 0x1740048, 0x1740044 | |
7187 | }; | |
7188 | ||
7189 | static struct attn_hw_reg *tsem_int_bb_a0_regs[3] = { | |
7190 | &tsem_int0_bb_a0, &tsem_int1_bb_a0, &tsem_fast_memory_int0_bb_a0, | |
7191 | }; | |
7192 | ||
7193 | static const u16 tsem_int0_bb_b0_attn_idx[32] = { | |
7194 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
7195 | 20, | |
7196 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
7197 | }; | |
7198 | ||
7199 | static struct attn_hw_reg tsem_int0_bb_b0 = { | |
7200 | 0, 32, tsem_int0_bb_b0_attn_idx, 0x1700040, 0x170004c, 0x1700048, | |
7201 | 0x1700044 | |
7202 | }; | |
7203 | ||
7204 | static const u16 tsem_int1_bb_b0_attn_idx[13] = { | |
7205 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, | |
7206 | }; | |
7207 | ||
7208 | static struct attn_hw_reg tsem_int1_bb_b0 = { | |
7209 | 1, 13, tsem_int1_bb_b0_attn_idx, 0x1700050, 0x170005c, 0x1700058, | |
7210 | 0x1700054 | |
7211 | }; | |
7212 | ||
7213 | static const u16 tsem_fast_memory_int0_bb_b0_attn_idx[1] = { | |
7214 | 45, | |
7215 | }; | |
7216 | ||
7217 | static struct attn_hw_reg tsem_fast_memory_int0_bb_b0 = { | |
7218 | 2, 1, tsem_fast_memory_int0_bb_b0_attn_idx, 0x1740040, 0x174004c, | |
7219 | 0x1740048, 0x1740044 | |
7220 | }; | |
7221 | ||
7222 | static struct attn_hw_reg *tsem_int_bb_b0_regs[3] = { | |
7223 | &tsem_int0_bb_b0, &tsem_int1_bb_b0, &tsem_fast_memory_int0_bb_b0, | |
7224 | }; | |
7225 | ||
7226 | static const u16 tsem_int0_k2_attn_idx[32] = { | |
7227 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
7228 | 20, | |
7229 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
7230 | }; | |
7231 | ||
7232 | static struct attn_hw_reg tsem_int0_k2 = { | |
7233 | 0, 32, tsem_int0_k2_attn_idx, 0x1700040, 0x170004c, 0x1700048, | |
7234 | 0x1700044 | |
7235 | }; | |
7236 | ||
7237 | static const u16 tsem_int1_k2_attn_idx[13] = { | |
7238 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, | |
7239 | }; | |
7240 | ||
7241 | static struct attn_hw_reg tsem_int1_k2 = { | |
7242 | 1, 13, tsem_int1_k2_attn_idx, 0x1700050, 0x170005c, 0x1700058, | |
7243 | 0x1700054 | |
7244 | }; | |
7245 | ||
7246 | static const u16 tsem_fast_memory_int0_k2_attn_idx[1] = { | |
7247 | 45, | |
7248 | }; | |
7249 | ||
7250 | static struct attn_hw_reg tsem_fast_memory_int0_k2 = { | |
7251 | 2, 1, tsem_fast_memory_int0_k2_attn_idx, 0x1740040, 0x174004c, | |
7252 | 0x1740048, | |
7253 | 0x1740044 | |
7254 | }; | |
7255 | ||
7256 | static struct attn_hw_reg *tsem_int_k2_regs[3] = { | |
7257 | &tsem_int0_k2, &tsem_int1_k2, &tsem_fast_memory_int0_k2, | |
7258 | }; | |
7259 | ||
7260 | #ifdef ATTN_DESC | |
7261 | static const char *tsem_prty_attn_desc[23] = { | |
7262 | "tsem_vfc_rbc_parity_error", | |
7263 | "tsem_storm_rf_parity_error", | |
7264 | "tsem_reg_gen_parity_error", | |
7265 | "tsem_mem005_i_ecc_0_rf_int", | |
7266 | "tsem_mem005_i_ecc_1_rf_int", | |
7267 | "tsem_mem004_i_mem_prty", | |
7268 | "tsem_mem002_i_mem_prty", | |
7269 | "tsem_mem003_i_mem_prty", | |
7270 | "tsem_mem001_i_mem_prty", | |
7271 | "tsem_fast_memory_mem024_i_mem_prty", | |
7272 | "tsem_fast_memory_mem023_i_mem_prty", | |
7273 | "tsem_fast_memory_mem022_i_mem_prty", | |
7274 | "tsem_fast_memory_mem021_i_mem_prty", | |
7275 | "tsem_fast_memory_mem020_i_mem_prty", | |
7276 | "tsem_fast_memory_mem019_i_mem_prty", | |
7277 | "tsem_fast_memory_mem018_i_mem_prty", | |
7278 | "tsem_fast_memory_vfc_config_mem005_i_ecc_rf_int", | |
7279 | "tsem_fast_memory_vfc_config_mem002_i_ecc_rf_int", | |
7280 | "tsem_fast_memory_vfc_config_mem006_i_mem_prty", | |
7281 | "tsem_fast_memory_vfc_config_mem001_i_mem_prty", | |
7282 | "tsem_fast_memory_vfc_config_mem004_i_mem_prty", | |
7283 | "tsem_fast_memory_vfc_config_mem003_i_mem_prty", | |
7284 | "tsem_fast_memory_vfc_config_mem007_i_mem_prty", | |
7285 | }; | |
7286 | #else | |
7287 | #define tsem_prty_attn_desc OSAL_NULL | |
7288 | #endif | |
7289 | ||
7290 | static const u16 tsem_prty0_bb_a0_attn_idx[3] = { | |
7291 | 0, 1, 2, | |
7292 | }; | |
7293 | ||
7294 | static struct attn_hw_reg tsem_prty0_bb_a0 = { | |
7295 | 0, 3, tsem_prty0_bb_a0_attn_idx, 0x17000c8, 0x17000d4, 0x17000d0, | |
7296 | 0x17000cc | |
7297 | }; | |
7298 | ||
7299 | static const u16 tsem_prty1_bb_a0_attn_idx[6] = { | |
7300 | 3, 4, 5, 6, 7, 8, | |
7301 | }; | |
7302 | ||
7303 | static struct attn_hw_reg tsem_prty1_bb_a0 = { | |
7304 | 1, 6, tsem_prty1_bb_a0_attn_idx, 0x1700200, 0x170020c, 0x1700208, | |
7305 | 0x1700204 | |
7306 | }; | |
7307 | ||
7308 | static const u16 tsem_fast_memory_vfc_config_prty1_bb_a0_attn_idx[6] = { | |
7309 | 16, 17, 19, 20, 21, 22, | |
7310 | }; | |
7311 | ||
7312 | static struct attn_hw_reg tsem_fast_memory_vfc_config_prty1_bb_a0 = { | |
7313 | 2, 6, tsem_fast_memory_vfc_config_prty1_bb_a0_attn_idx, 0x174a200, | |
7314 | 0x174a20c, 0x174a208, 0x174a204 | |
7315 | }; | |
7316 | ||
7317 | static struct attn_hw_reg *tsem_prty_bb_a0_regs[3] = { | |
7318 | &tsem_prty0_bb_a0, &tsem_prty1_bb_a0, | |
7319 | &tsem_fast_memory_vfc_config_prty1_bb_a0, | |
7320 | }; | |
7321 | ||
7322 | static const u16 tsem_prty0_bb_b0_attn_idx[3] = { | |
7323 | 0, 1, 2, | |
7324 | }; | |
7325 | ||
7326 | static struct attn_hw_reg tsem_prty0_bb_b0 = { | |
7327 | 0, 3, tsem_prty0_bb_b0_attn_idx, 0x17000c8, 0x17000d4, 0x17000d0, | |
7328 | 0x17000cc | |
7329 | }; | |
7330 | ||
7331 | static const u16 tsem_prty1_bb_b0_attn_idx[6] = { | |
7332 | 3, 4, 5, 6, 7, 8, | |
7333 | }; | |
7334 | ||
7335 | static struct attn_hw_reg tsem_prty1_bb_b0 = { | |
7336 | 1, 6, tsem_prty1_bb_b0_attn_idx, 0x1700200, 0x170020c, 0x1700208, | |
7337 | 0x1700204 | |
7338 | }; | |
7339 | ||
7340 | static const u16 tsem_fast_memory_vfc_config_prty1_bb_b0_attn_idx[6] = { | |
7341 | 16, 17, 19, 20, 21, 22, | |
7342 | }; | |
7343 | ||
7344 | static struct attn_hw_reg tsem_fast_memory_vfc_config_prty1_bb_b0 = { | |
7345 | 2, 6, tsem_fast_memory_vfc_config_prty1_bb_b0_attn_idx, 0x174a200, | |
7346 | 0x174a20c, 0x174a208, 0x174a204 | |
7347 | }; | |
7348 | ||
7349 | static struct attn_hw_reg *tsem_prty_bb_b0_regs[3] = { | |
7350 | &tsem_prty0_bb_b0, &tsem_prty1_bb_b0, | |
7351 | &tsem_fast_memory_vfc_config_prty1_bb_b0, | |
7352 | }; | |
7353 | ||
7354 | static const u16 tsem_prty0_k2_attn_idx[3] = { | |
7355 | 0, 1, 2, | |
7356 | }; | |
7357 | ||
7358 | static struct attn_hw_reg tsem_prty0_k2 = { | |
7359 | 0, 3, tsem_prty0_k2_attn_idx, 0x17000c8, 0x17000d4, 0x17000d0, | |
7360 | 0x17000cc | |
7361 | }; | |
7362 | ||
7363 | static const u16 tsem_prty1_k2_attn_idx[6] = { | |
7364 | 3, 4, 5, 6, 7, 8, | |
7365 | }; | |
7366 | ||
7367 | static struct attn_hw_reg tsem_prty1_k2 = { | |
7368 | 1, 6, tsem_prty1_k2_attn_idx, 0x1700200, 0x170020c, 0x1700208, | |
7369 | 0x1700204 | |
7370 | }; | |
7371 | ||
7372 | static const u16 tsem_fast_memory_prty1_k2_attn_idx[7] = { | |
7373 | 9, 10, 11, 12, 13, 14, 15, | |
7374 | }; | |
7375 | ||
7376 | static struct attn_hw_reg tsem_fast_memory_prty1_k2 = { | |
7377 | 2, 7, tsem_fast_memory_prty1_k2_attn_idx, 0x1740200, 0x174020c, | |
7378 | 0x1740208, | |
7379 | 0x1740204 | |
7380 | }; | |
7381 | ||
7382 | static const u16 tsem_fast_memory_vfc_config_prty1_k2_attn_idx[6] = { | |
7383 | 16, 17, 18, 19, 20, 21, | |
7384 | }; | |
7385 | ||
7386 | static struct attn_hw_reg tsem_fast_memory_vfc_config_prty1_k2 = { | |
7387 | 3, 6, tsem_fast_memory_vfc_config_prty1_k2_attn_idx, 0x174a200, | |
7388 | 0x174a20c, | |
7389 | 0x174a208, 0x174a204 | |
7390 | }; | |
7391 | ||
7392 | static struct attn_hw_reg *tsem_prty_k2_regs[4] = { | |
7393 | &tsem_prty0_k2, &tsem_prty1_k2, &tsem_fast_memory_prty1_k2, | |
7394 | &tsem_fast_memory_vfc_config_prty1_k2, | |
7395 | }; | |
7396 | ||
7397 | #ifdef ATTN_DESC | |
7398 | static const char *msem_int_attn_desc[46] = { | |
7399 | "msem_address_error", | |
7400 | "msem_fic_last_error", | |
7401 | "msem_fic_length_error", | |
7402 | "msem_fic_fifo_error", | |
7403 | "msem_pas_buf_fifo_error", | |
7404 | "msem_sync_fin_pop_error", | |
7405 | "msem_sync_dra_wr_push_error", | |
7406 | "msem_sync_dra_wr_pop_error", | |
7407 | "msem_sync_dra_rd_push_error", | |
7408 | "msem_sync_dra_rd_pop_error", | |
7409 | "msem_sync_fin_push_error", | |
7410 | "msem_sem_fast_address_error", | |
7411 | "msem_cam_lsb_inp_fifo", | |
7412 | "msem_cam_msb_inp_fifo", | |
7413 | "msem_cam_out_fifo", | |
7414 | "msem_fin_fifo", | |
7415 | "msem_thread_fifo_error", | |
7416 | "msem_thread_overrun", | |
7417 | "msem_sync_ext_store_push_error", | |
7418 | "msem_sync_ext_store_pop_error", | |
7419 | "msem_sync_ext_load_push_error", | |
7420 | "msem_sync_ext_load_pop_error", | |
7421 | "msem_sync_ram_rd_push_error", | |
7422 | "msem_sync_ram_rd_pop_error", | |
7423 | "msem_sync_ram_wr_pop_error", | |
7424 | "msem_sync_ram_wr_push_error", | |
7425 | "msem_sync_dbg_push_error", | |
7426 | "msem_sync_dbg_pop_error", | |
7427 | "msem_dbg_fifo_error", | |
7428 | "msem_cam_msb2_inp_fifo", | |
7429 | "msem_vfc_interrupt", | |
7430 | "msem_vfc_out_fifo_error", | |
7431 | "msem_storm_stack_uf_attn", | |
7432 | "msem_storm_stack_of_attn", | |
7433 | "msem_storm_runtime_error", | |
7434 | "msem_ext_load_pend_wr_error", | |
7435 | "msem_thread_rls_orun_error", | |
7436 | "msem_thread_rls_aloc_error", | |
7437 | "msem_thread_rls_vld_error", | |
7438 | "msem_ext_thread_oor_error", | |
7439 | "msem_ord_id_fifo_error", | |
7440 | "msem_invld_foc_error", | |
7441 | "msem_ext_ld_len_error", | |
7442 | "msem_thrd_ord_fifo_error", | |
7443 | "msem_invld_thrd_ord_error", | |
7444 | "msem_fast_memory_address_error", | |
7445 | }; | |
7446 | #else | |
7447 | #define msem_int_attn_desc OSAL_NULL | |
7448 | #endif | |
7449 | ||
7450 | static const u16 msem_int0_bb_a0_attn_idx[32] = { | |
7451 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
7452 | 20, | |
7453 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
7454 | }; | |
7455 | ||
7456 | static struct attn_hw_reg msem_int0_bb_a0 = { | |
7457 | 0, 32, msem_int0_bb_a0_attn_idx, 0x1800040, 0x180004c, 0x1800048, | |
7458 | 0x1800044 | |
7459 | }; | |
7460 | ||
7461 | static const u16 msem_int1_bb_a0_attn_idx[13] = { | |
7462 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, | |
7463 | }; | |
7464 | ||
7465 | static struct attn_hw_reg msem_int1_bb_a0 = { | |
7466 | 1, 13, msem_int1_bb_a0_attn_idx, 0x1800050, 0x180005c, 0x1800058, | |
7467 | 0x1800054 | |
7468 | }; | |
7469 | ||
7470 | static const u16 msem_fast_memory_int0_bb_a0_attn_idx[1] = { | |
7471 | 45, | |
7472 | }; | |
7473 | ||
7474 | static struct attn_hw_reg msem_fast_memory_int0_bb_a0 = { | |
7475 | 2, 1, msem_fast_memory_int0_bb_a0_attn_idx, 0x1840040, 0x184004c, | |
7476 | 0x1840048, 0x1840044 | |
7477 | }; | |
7478 | ||
7479 | static struct attn_hw_reg *msem_int_bb_a0_regs[3] = { | |
7480 | &msem_int0_bb_a0, &msem_int1_bb_a0, &msem_fast_memory_int0_bb_a0, | |
7481 | }; | |
7482 | ||
7483 | static const u16 msem_int0_bb_b0_attn_idx[32] = { | |
7484 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
7485 | 20, | |
7486 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
7487 | }; | |
7488 | ||
7489 | static struct attn_hw_reg msem_int0_bb_b0 = { | |
7490 | 0, 32, msem_int0_bb_b0_attn_idx, 0x1800040, 0x180004c, 0x1800048, | |
7491 | 0x1800044 | |
7492 | }; | |
7493 | ||
7494 | static const u16 msem_int1_bb_b0_attn_idx[13] = { | |
7495 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, | |
7496 | }; | |
7497 | ||
7498 | static struct attn_hw_reg msem_int1_bb_b0 = { | |
7499 | 1, 13, msem_int1_bb_b0_attn_idx, 0x1800050, 0x180005c, 0x1800058, | |
7500 | 0x1800054 | |
7501 | }; | |
7502 | ||
7503 | static const u16 msem_fast_memory_int0_bb_b0_attn_idx[1] = { | |
7504 | 45, | |
7505 | }; | |
7506 | ||
7507 | static struct attn_hw_reg msem_fast_memory_int0_bb_b0 = { | |
7508 | 2, 1, msem_fast_memory_int0_bb_b0_attn_idx, 0x1840040, 0x184004c, | |
7509 | 0x1840048, 0x1840044 | |
7510 | }; | |
7511 | ||
7512 | static struct attn_hw_reg *msem_int_bb_b0_regs[3] = { | |
7513 | &msem_int0_bb_b0, &msem_int1_bb_b0, &msem_fast_memory_int0_bb_b0, | |
7514 | }; | |
7515 | ||
7516 | static const u16 msem_int0_k2_attn_idx[32] = { | |
7517 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
7518 | 20, | |
7519 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
7520 | }; | |
7521 | ||
7522 | static struct attn_hw_reg msem_int0_k2 = { | |
7523 | 0, 32, msem_int0_k2_attn_idx, 0x1800040, 0x180004c, 0x1800048, | |
7524 | 0x1800044 | |
7525 | }; | |
7526 | ||
7527 | static const u16 msem_int1_k2_attn_idx[13] = { | |
7528 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, | |
7529 | }; | |
7530 | ||
7531 | static struct attn_hw_reg msem_int1_k2 = { | |
7532 | 1, 13, msem_int1_k2_attn_idx, 0x1800050, 0x180005c, 0x1800058, | |
7533 | 0x1800054 | |
7534 | }; | |
7535 | ||
7536 | static const u16 msem_fast_memory_int0_k2_attn_idx[1] = { | |
7537 | 45, | |
7538 | }; | |
7539 | ||
7540 | static struct attn_hw_reg msem_fast_memory_int0_k2 = { | |
7541 | 2, 1, msem_fast_memory_int0_k2_attn_idx, 0x1840040, 0x184004c, | |
7542 | 0x1840048, | |
7543 | 0x1840044 | |
7544 | }; | |
7545 | ||
7546 | static struct attn_hw_reg *msem_int_k2_regs[3] = { | |
7547 | &msem_int0_k2, &msem_int1_k2, &msem_fast_memory_int0_k2, | |
7548 | }; | |
7549 | ||
7550 | #ifdef ATTN_DESC | |
7551 | static const char *msem_prty_attn_desc[23] = { | |
7552 | "msem_vfc_rbc_parity_error", | |
7553 | "msem_storm_rf_parity_error", | |
7554 | "msem_reg_gen_parity_error", | |
7555 | "msem_mem005_i_ecc_0_rf_int", | |
7556 | "msem_mem005_i_ecc_1_rf_int", | |
7557 | "msem_mem004_i_mem_prty", | |
7558 | "msem_mem002_i_mem_prty", | |
7559 | "msem_mem003_i_mem_prty", | |
7560 | "msem_mem001_i_mem_prty", | |
7561 | "msem_fast_memory_mem024_i_mem_prty", | |
7562 | "msem_fast_memory_mem023_i_mem_prty", | |
7563 | "msem_fast_memory_mem022_i_mem_prty", | |
7564 | "msem_fast_memory_mem021_i_mem_prty", | |
7565 | "msem_fast_memory_mem020_i_mem_prty", | |
7566 | "msem_fast_memory_mem019_i_mem_prty", | |
7567 | "msem_fast_memory_mem018_i_mem_prty", | |
7568 | "msem_fast_memory_vfc_config_mem005_i_ecc_rf_int", | |
7569 | "msem_fast_memory_vfc_config_mem002_i_ecc_rf_int", | |
7570 | "msem_fast_memory_vfc_config_mem006_i_mem_prty", | |
7571 | "msem_fast_memory_vfc_config_mem001_i_mem_prty", | |
7572 | "msem_fast_memory_vfc_config_mem004_i_mem_prty", | |
7573 | "msem_fast_memory_vfc_config_mem003_i_mem_prty", | |
7574 | "msem_fast_memory_vfc_config_mem007_i_mem_prty", | |
7575 | }; | |
7576 | #else | |
7577 | #define msem_prty_attn_desc OSAL_NULL | |
7578 | #endif | |
7579 | ||
7580 | static const u16 msem_prty0_bb_a0_attn_idx[3] = { | |
7581 | 0, 1, 2, | |
7582 | }; | |
7583 | ||
7584 | static struct attn_hw_reg msem_prty0_bb_a0 = { | |
7585 | 0, 3, msem_prty0_bb_a0_attn_idx, 0x18000c8, 0x18000d4, 0x18000d0, | |
7586 | 0x18000cc | |
7587 | }; | |
7588 | ||
7589 | static const u16 msem_prty1_bb_a0_attn_idx[6] = { | |
7590 | 3, 4, 5, 6, 7, 8, | |
7591 | }; | |
7592 | ||
7593 | static struct attn_hw_reg msem_prty1_bb_a0 = { | |
7594 | 1, 6, msem_prty1_bb_a0_attn_idx, 0x1800200, 0x180020c, 0x1800208, | |
7595 | 0x1800204 | |
7596 | }; | |
7597 | ||
7598 | static struct attn_hw_reg *msem_prty_bb_a0_regs[2] = { | |
7599 | &msem_prty0_bb_a0, &msem_prty1_bb_a0, | |
7600 | }; | |
7601 | ||
7602 | static const u16 msem_prty0_bb_b0_attn_idx[3] = { | |
7603 | 0, 1, 2, | |
7604 | }; | |
7605 | ||
7606 | static struct attn_hw_reg msem_prty0_bb_b0 = { | |
7607 | 0, 3, msem_prty0_bb_b0_attn_idx, 0x18000c8, 0x18000d4, 0x18000d0, | |
7608 | 0x18000cc | |
7609 | }; | |
7610 | ||
7611 | static const u16 msem_prty1_bb_b0_attn_idx[6] = { | |
7612 | 3, 4, 5, 6, 7, 8, | |
7613 | }; | |
7614 | ||
7615 | static struct attn_hw_reg msem_prty1_bb_b0 = { | |
7616 | 1, 6, msem_prty1_bb_b0_attn_idx, 0x1800200, 0x180020c, 0x1800208, | |
7617 | 0x1800204 | |
7618 | }; | |
7619 | ||
7620 | static struct attn_hw_reg *msem_prty_bb_b0_regs[2] = { | |
7621 | &msem_prty0_bb_b0, &msem_prty1_bb_b0, | |
7622 | }; | |
7623 | ||
7624 | static const u16 msem_prty0_k2_attn_idx[3] = { | |
7625 | 0, 1, 2, | |
7626 | }; | |
7627 | ||
7628 | static struct attn_hw_reg msem_prty0_k2 = { | |
7629 | 0, 3, msem_prty0_k2_attn_idx, 0x18000c8, 0x18000d4, 0x18000d0, | |
7630 | 0x18000cc | |
7631 | }; | |
7632 | ||
7633 | static const u16 msem_prty1_k2_attn_idx[6] = { | |
7634 | 3, 4, 5, 6, 7, 8, | |
7635 | }; | |
7636 | ||
7637 | static struct attn_hw_reg msem_prty1_k2 = { | |
7638 | 1, 6, msem_prty1_k2_attn_idx, 0x1800200, 0x180020c, 0x1800208, | |
7639 | 0x1800204 | |
7640 | }; | |
7641 | ||
7642 | static const u16 msem_fast_memory_prty1_k2_attn_idx[7] = { | |
7643 | 9, 10, 11, 12, 13, 14, 15, | |
7644 | }; | |
7645 | ||
7646 | static struct attn_hw_reg msem_fast_memory_prty1_k2 = { | |
7647 | 2, 7, msem_fast_memory_prty1_k2_attn_idx, 0x1840200, 0x184020c, | |
7648 | 0x1840208, | |
7649 | 0x1840204 | |
7650 | }; | |
7651 | ||
7652 | static struct attn_hw_reg *msem_prty_k2_regs[3] = { | |
7653 | &msem_prty0_k2, &msem_prty1_k2, &msem_fast_memory_prty1_k2, | |
7654 | }; | |
7655 | ||
7656 | #ifdef ATTN_DESC | |
7657 | static const char *usem_int_attn_desc[46] = { | |
7658 | "usem_address_error", | |
7659 | "usem_fic_last_error", | |
7660 | "usem_fic_length_error", | |
7661 | "usem_fic_fifo_error", | |
7662 | "usem_pas_buf_fifo_error", | |
7663 | "usem_sync_fin_pop_error", | |
7664 | "usem_sync_dra_wr_push_error", | |
7665 | "usem_sync_dra_wr_pop_error", | |
7666 | "usem_sync_dra_rd_push_error", | |
7667 | "usem_sync_dra_rd_pop_error", | |
7668 | "usem_sync_fin_push_error", | |
7669 | "usem_sem_fast_address_error", | |
7670 | "usem_cam_lsb_inp_fifo", | |
7671 | "usem_cam_msb_inp_fifo", | |
7672 | "usem_cam_out_fifo", | |
7673 | "usem_fin_fifo", | |
7674 | "usem_thread_fifo_error", | |
7675 | "usem_thread_overrun", | |
7676 | "usem_sync_ext_store_push_error", | |
7677 | "usem_sync_ext_store_pop_error", | |
7678 | "usem_sync_ext_load_push_error", | |
7679 | "usem_sync_ext_load_pop_error", | |
7680 | "usem_sync_ram_rd_push_error", | |
7681 | "usem_sync_ram_rd_pop_error", | |
7682 | "usem_sync_ram_wr_pop_error", | |
7683 | "usem_sync_ram_wr_push_error", | |
7684 | "usem_sync_dbg_push_error", | |
7685 | "usem_sync_dbg_pop_error", | |
7686 | "usem_dbg_fifo_error", | |
7687 | "usem_cam_msb2_inp_fifo", | |
7688 | "usem_vfc_interrupt", | |
7689 | "usem_vfc_out_fifo_error", | |
7690 | "usem_storm_stack_uf_attn", | |
7691 | "usem_storm_stack_of_attn", | |
7692 | "usem_storm_runtime_error", | |
7693 | "usem_ext_load_pend_wr_error", | |
7694 | "usem_thread_rls_orun_error", | |
7695 | "usem_thread_rls_aloc_error", | |
7696 | "usem_thread_rls_vld_error", | |
7697 | "usem_ext_thread_oor_error", | |
7698 | "usem_ord_id_fifo_error", | |
7699 | "usem_invld_foc_error", | |
7700 | "usem_ext_ld_len_error", | |
7701 | "usem_thrd_ord_fifo_error", | |
7702 | "usem_invld_thrd_ord_error", | |
7703 | "usem_fast_memory_address_error", | |
7704 | }; | |
7705 | #else | |
7706 | #define usem_int_attn_desc OSAL_NULL | |
7707 | #endif | |
7708 | ||
7709 | static const u16 usem_int0_bb_a0_attn_idx[32] = { | |
7710 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
7711 | 20, | |
7712 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
7713 | }; | |
7714 | ||
7715 | static struct attn_hw_reg usem_int0_bb_a0 = { | |
7716 | 0, 32, usem_int0_bb_a0_attn_idx, 0x1900040, 0x190004c, 0x1900048, | |
7717 | 0x1900044 | |
7718 | }; | |
7719 | ||
7720 | static const u16 usem_int1_bb_a0_attn_idx[13] = { | |
7721 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, | |
7722 | }; | |
7723 | ||
7724 | static struct attn_hw_reg usem_int1_bb_a0 = { | |
7725 | 1, 13, usem_int1_bb_a0_attn_idx, 0x1900050, 0x190005c, 0x1900058, | |
7726 | 0x1900054 | |
7727 | }; | |
7728 | ||
7729 | static const u16 usem_fast_memory_int0_bb_a0_attn_idx[1] = { | |
7730 | 45, | |
7731 | }; | |
7732 | ||
7733 | static struct attn_hw_reg usem_fast_memory_int0_bb_a0 = { | |
7734 | 2, 1, usem_fast_memory_int0_bb_a0_attn_idx, 0x1940040, 0x194004c, | |
7735 | 0x1940048, 0x1940044 | |
7736 | }; | |
7737 | ||
7738 | static struct attn_hw_reg *usem_int_bb_a0_regs[3] = { | |
7739 | &usem_int0_bb_a0, &usem_int1_bb_a0, &usem_fast_memory_int0_bb_a0, | |
7740 | }; | |
7741 | ||
7742 | static const u16 usem_int0_bb_b0_attn_idx[32] = { | |
7743 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
7744 | 20, | |
7745 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
7746 | }; | |
7747 | ||
7748 | static struct attn_hw_reg usem_int0_bb_b0 = { | |
7749 | 0, 32, usem_int0_bb_b0_attn_idx, 0x1900040, 0x190004c, 0x1900048, | |
7750 | 0x1900044 | |
7751 | }; | |
7752 | ||
7753 | static const u16 usem_int1_bb_b0_attn_idx[13] = { | |
7754 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, | |
7755 | }; | |
7756 | ||
7757 | static struct attn_hw_reg usem_int1_bb_b0 = { | |
7758 | 1, 13, usem_int1_bb_b0_attn_idx, 0x1900050, 0x190005c, 0x1900058, | |
7759 | 0x1900054 | |
7760 | }; | |
7761 | ||
7762 | static const u16 usem_fast_memory_int0_bb_b0_attn_idx[1] = { | |
7763 | 45, | |
7764 | }; | |
7765 | ||
7766 | static struct attn_hw_reg usem_fast_memory_int0_bb_b0 = { | |
7767 | 2, 1, usem_fast_memory_int0_bb_b0_attn_idx, 0x1940040, 0x194004c, | |
7768 | 0x1940048, 0x1940044 | |
7769 | }; | |
7770 | ||
7771 | static struct attn_hw_reg *usem_int_bb_b0_regs[3] = { | |
7772 | &usem_int0_bb_b0, &usem_int1_bb_b0, &usem_fast_memory_int0_bb_b0, | |
7773 | }; | |
7774 | ||
7775 | static const u16 usem_int0_k2_attn_idx[32] = { | |
7776 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
7777 | 20, | |
7778 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
7779 | }; | |
7780 | ||
7781 | static struct attn_hw_reg usem_int0_k2 = { | |
7782 | 0, 32, usem_int0_k2_attn_idx, 0x1900040, 0x190004c, 0x1900048, | |
7783 | 0x1900044 | |
7784 | }; | |
7785 | ||
7786 | static const u16 usem_int1_k2_attn_idx[13] = { | |
7787 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, | |
7788 | }; | |
7789 | ||
7790 | static struct attn_hw_reg usem_int1_k2 = { | |
7791 | 1, 13, usem_int1_k2_attn_idx, 0x1900050, 0x190005c, 0x1900058, | |
7792 | 0x1900054 | |
7793 | }; | |
7794 | ||
7795 | static const u16 usem_fast_memory_int0_k2_attn_idx[1] = { | |
7796 | 45, | |
7797 | }; | |
7798 | ||
7799 | static struct attn_hw_reg usem_fast_memory_int0_k2 = { | |
7800 | 2, 1, usem_fast_memory_int0_k2_attn_idx, 0x1940040, 0x194004c, | |
7801 | 0x1940048, | |
7802 | 0x1940044 | |
7803 | }; | |
7804 | ||
7805 | static struct attn_hw_reg *usem_int_k2_regs[3] = { | |
7806 | &usem_int0_k2, &usem_int1_k2, &usem_fast_memory_int0_k2, | |
7807 | }; | |
7808 | ||
7809 | #ifdef ATTN_DESC | |
7810 | static const char *usem_prty_attn_desc[23] = { | |
7811 | "usem_vfc_rbc_parity_error", | |
7812 | "usem_storm_rf_parity_error", | |
7813 | "usem_reg_gen_parity_error", | |
7814 | "usem_mem005_i_ecc_0_rf_int", | |
7815 | "usem_mem005_i_ecc_1_rf_int", | |
7816 | "usem_mem004_i_mem_prty", | |
7817 | "usem_mem002_i_mem_prty", | |
7818 | "usem_mem003_i_mem_prty", | |
7819 | "usem_mem001_i_mem_prty", | |
7820 | "usem_fast_memory_mem024_i_mem_prty", | |
7821 | "usem_fast_memory_mem023_i_mem_prty", | |
7822 | "usem_fast_memory_mem022_i_mem_prty", | |
7823 | "usem_fast_memory_mem021_i_mem_prty", | |
7824 | "usem_fast_memory_mem020_i_mem_prty", | |
7825 | "usem_fast_memory_mem019_i_mem_prty", | |
7826 | "usem_fast_memory_mem018_i_mem_prty", | |
7827 | "usem_fast_memory_vfc_config_mem005_i_ecc_rf_int", | |
7828 | "usem_fast_memory_vfc_config_mem002_i_ecc_rf_int", | |
7829 | "usem_fast_memory_vfc_config_mem006_i_mem_prty", | |
7830 | "usem_fast_memory_vfc_config_mem001_i_mem_prty", | |
7831 | "usem_fast_memory_vfc_config_mem004_i_mem_prty", | |
7832 | "usem_fast_memory_vfc_config_mem003_i_mem_prty", | |
7833 | "usem_fast_memory_vfc_config_mem007_i_mem_prty", | |
7834 | }; | |
7835 | #else | |
7836 | #define usem_prty_attn_desc OSAL_NULL | |
7837 | #endif | |
7838 | ||
7839 | static const u16 usem_prty0_bb_a0_attn_idx[3] = { | |
7840 | 0, 1, 2, | |
7841 | }; | |
7842 | ||
7843 | static struct attn_hw_reg usem_prty0_bb_a0 = { | |
7844 | 0, 3, usem_prty0_bb_a0_attn_idx, 0x19000c8, 0x19000d4, 0x19000d0, | |
7845 | 0x19000cc | |
7846 | }; | |
7847 | ||
7848 | static const u16 usem_prty1_bb_a0_attn_idx[6] = { | |
7849 | 3, 4, 5, 6, 7, 8, | |
7850 | }; | |
7851 | ||
7852 | static struct attn_hw_reg usem_prty1_bb_a0 = { | |
7853 | 1, 6, usem_prty1_bb_a0_attn_idx, 0x1900200, 0x190020c, 0x1900208, | |
7854 | 0x1900204 | |
7855 | }; | |
7856 | ||
7857 | static struct attn_hw_reg *usem_prty_bb_a0_regs[2] = { | |
7858 | &usem_prty0_bb_a0, &usem_prty1_bb_a0, | |
7859 | }; | |
7860 | ||
7861 | static const u16 usem_prty0_bb_b0_attn_idx[3] = { | |
7862 | 0, 1, 2, | |
7863 | }; | |
7864 | ||
7865 | static struct attn_hw_reg usem_prty0_bb_b0 = { | |
7866 | 0, 3, usem_prty0_bb_b0_attn_idx, 0x19000c8, 0x19000d4, 0x19000d0, | |
7867 | 0x19000cc | |
7868 | }; | |
7869 | ||
7870 | static const u16 usem_prty1_bb_b0_attn_idx[6] = { | |
7871 | 3, 4, 5, 6, 7, 8, | |
7872 | }; | |
7873 | ||
7874 | static struct attn_hw_reg usem_prty1_bb_b0 = { | |
7875 | 1, 6, usem_prty1_bb_b0_attn_idx, 0x1900200, 0x190020c, 0x1900208, | |
7876 | 0x1900204 | |
7877 | }; | |
7878 | ||
7879 | static struct attn_hw_reg *usem_prty_bb_b0_regs[2] = { | |
7880 | &usem_prty0_bb_b0, &usem_prty1_bb_b0, | |
7881 | }; | |
7882 | ||
7883 | static const u16 usem_prty0_k2_attn_idx[3] = { | |
7884 | 0, 1, 2, | |
7885 | }; | |
7886 | ||
7887 | static struct attn_hw_reg usem_prty0_k2 = { | |
7888 | 0, 3, usem_prty0_k2_attn_idx, 0x19000c8, 0x19000d4, 0x19000d0, | |
7889 | 0x19000cc | |
7890 | }; | |
7891 | ||
7892 | static const u16 usem_prty1_k2_attn_idx[6] = { | |
7893 | 3, 4, 5, 6, 7, 8, | |
7894 | }; | |
7895 | ||
7896 | static struct attn_hw_reg usem_prty1_k2 = { | |
7897 | 1, 6, usem_prty1_k2_attn_idx, 0x1900200, 0x190020c, 0x1900208, | |
7898 | 0x1900204 | |
7899 | }; | |
7900 | ||
7901 | static const u16 usem_fast_memory_prty1_k2_attn_idx[7] = { | |
7902 | 9, 10, 11, 12, 13, 14, 15, | |
7903 | }; | |
7904 | ||
7905 | static struct attn_hw_reg usem_fast_memory_prty1_k2 = { | |
7906 | 2, 7, usem_fast_memory_prty1_k2_attn_idx, 0x1940200, 0x194020c, | |
7907 | 0x1940208, | |
7908 | 0x1940204 | |
7909 | }; | |
7910 | ||
7911 | static struct attn_hw_reg *usem_prty_k2_regs[3] = { | |
7912 | &usem_prty0_k2, &usem_prty1_k2, &usem_fast_memory_prty1_k2, | |
7913 | }; | |
7914 | ||
7915 | #ifdef ATTN_DESC | |
7916 | static const char *xsem_int_attn_desc[46] = { | |
7917 | "xsem_address_error", | |
7918 | "xsem_fic_last_error", | |
7919 | "xsem_fic_length_error", | |
7920 | "xsem_fic_fifo_error", | |
7921 | "xsem_pas_buf_fifo_error", | |
7922 | "xsem_sync_fin_pop_error", | |
7923 | "xsem_sync_dra_wr_push_error", | |
7924 | "xsem_sync_dra_wr_pop_error", | |
7925 | "xsem_sync_dra_rd_push_error", | |
7926 | "xsem_sync_dra_rd_pop_error", | |
7927 | "xsem_sync_fin_push_error", | |
7928 | "xsem_sem_fast_address_error", | |
7929 | "xsem_cam_lsb_inp_fifo", | |
7930 | "xsem_cam_msb_inp_fifo", | |
7931 | "xsem_cam_out_fifo", | |
7932 | "xsem_fin_fifo", | |
7933 | "xsem_thread_fifo_error", | |
7934 | "xsem_thread_overrun", | |
7935 | "xsem_sync_ext_store_push_error", | |
7936 | "xsem_sync_ext_store_pop_error", | |
7937 | "xsem_sync_ext_load_push_error", | |
7938 | "xsem_sync_ext_load_pop_error", | |
7939 | "xsem_sync_ram_rd_push_error", | |
7940 | "xsem_sync_ram_rd_pop_error", | |
7941 | "xsem_sync_ram_wr_pop_error", | |
7942 | "xsem_sync_ram_wr_push_error", | |
7943 | "xsem_sync_dbg_push_error", | |
7944 | "xsem_sync_dbg_pop_error", | |
7945 | "xsem_dbg_fifo_error", | |
7946 | "xsem_cam_msb2_inp_fifo", | |
7947 | "xsem_vfc_interrupt", | |
7948 | "xsem_vfc_out_fifo_error", | |
7949 | "xsem_storm_stack_uf_attn", | |
7950 | "xsem_storm_stack_of_attn", | |
7951 | "xsem_storm_runtime_error", | |
7952 | "xsem_ext_load_pend_wr_error", | |
7953 | "xsem_thread_rls_orun_error", | |
7954 | "xsem_thread_rls_aloc_error", | |
7955 | "xsem_thread_rls_vld_error", | |
7956 | "xsem_ext_thread_oor_error", | |
7957 | "xsem_ord_id_fifo_error", | |
7958 | "xsem_invld_foc_error", | |
7959 | "xsem_ext_ld_len_error", | |
7960 | "xsem_thrd_ord_fifo_error", | |
7961 | "xsem_invld_thrd_ord_error", | |
7962 | "xsem_fast_memory_address_error", | |
7963 | }; | |
7964 | #else | |
7965 | #define xsem_int_attn_desc OSAL_NULL | |
7966 | #endif | |
7967 | ||
7968 | static const u16 xsem_int0_bb_a0_attn_idx[32] = { | |
7969 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
7970 | 20, | |
7971 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
7972 | }; | |
7973 | ||
7974 | static struct attn_hw_reg xsem_int0_bb_a0 = { | |
7975 | 0, 32, xsem_int0_bb_a0_attn_idx, 0x1400040, 0x140004c, 0x1400048, | |
7976 | 0x1400044 | |
7977 | }; | |
7978 | ||
7979 | static const u16 xsem_int1_bb_a0_attn_idx[13] = { | |
7980 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, | |
7981 | }; | |
7982 | ||
7983 | static struct attn_hw_reg xsem_int1_bb_a0 = { | |
7984 | 1, 13, xsem_int1_bb_a0_attn_idx, 0x1400050, 0x140005c, 0x1400058, | |
7985 | 0x1400054 | |
7986 | }; | |
7987 | ||
7988 | static const u16 xsem_fast_memory_int0_bb_a0_attn_idx[1] = { | |
7989 | 45, | |
7990 | }; | |
7991 | ||
7992 | static struct attn_hw_reg xsem_fast_memory_int0_bb_a0 = { | |
7993 | 2, 1, xsem_fast_memory_int0_bb_a0_attn_idx, 0x1440040, 0x144004c, | |
7994 | 0x1440048, 0x1440044 | |
7995 | }; | |
7996 | ||
7997 | static struct attn_hw_reg *xsem_int_bb_a0_regs[3] = { | |
7998 | &xsem_int0_bb_a0, &xsem_int1_bb_a0, &xsem_fast_memory_int0_bb_a0, | |
7999 | }; | |
8000 | ||
8001 | static const u16 xsem_int0_bb_b0_attn_idx[32] = { | |
8002 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
8003 | 20, | |
8004 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
8005 | }; | |
8006 | ||
8007 | static struct attn_hw_reg xsem_int0_bb_b0 = { | |
8008 | 0, 32, xsem_int0_bb_b0_attn_idx, 0x1400040, 0x140004c, 0x1400048, | |
8009 | 0x1400044 | |
8010 | }; | |
8011 | ||
8012 | static const u16 xsem_int1_bb_b0_attn_idx[13] = { | |
8013 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, | |
8014 | }; | |
8015 | ||
8016 | static struct attn_hw_reg xsem_int1_bb_b0 = { | |
8017 | 1, 13, xsem_int1_bb_b0_attn_idx, 0x1400050, 0x140005c, 0x1400058, | |
8018 | 0x1400054 | |
8019 | }; | |
8020 | ||
8021 | static const u16 xsem_fast_memory_int0_bb_b0_attn_idx[1] = { | |
8022 | 45, | |
8023 | }; | |
8024 | ||
8025 | static struct attn_hw_reg xsem_fast_memory_int0_bb_b0 = { | |
8026 | 2, 1, xsem_fast_memory_int0_bb_b0_attn_idx, 0x1440040, 0x144004c, | |
8027 | 0x1440048, 0x1440044 | |
8028 | }; | |
8029 | ||
8030 | static struct attn_hw_reg *xsem_int_bb_b0_regs[3] = { | |
8031 | &xsem_int0_bb_b0, &xsem_int1_bb_b0, &xsem_fast_memory_int0_bb_b0, | |
8032 | }; | |
8033 | ||
8034 | static const u16 xsem_int0_k2_attn_idx[32] = { | |
8035 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
8036 | 20, | |
8037 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
8038 | }; | |
8039 | ||
8040 | static struct attn_hw_reg xsem_int0_k2 = { | |
8041 | 0, 32, xsem_int0_k2_attn_idx, 0x1400040, 0x140004c, 0x1400048, | |
8042 | 0x1400044 | |
8043 | }; | |
8044 | ||
8045 | static const u16 xsem_int1_k2_attn_idx[13] = { | |
8046 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, | |
8047 | }; | |
8048 | ||
8049 | static struct attn_hw_reg xsem_int1_k2 = { | |
8050 | 1, 13, xsem_int1_k2_attn_idx, 0x1400050, 0x140005c, 0x1400058, | |
8051 | 0x1400054 | |
8052 | }; | |
8053 | ||
8054 | static const u16 xsem_fast_memory_int0_k2_attn_idx[1] = { | |
8055 | 45, | |
8056 | }; | |
8057 | ||
8058 | static struct attn_hw_reg xsem_fast_memory_int0_k2 = { | |
8059 | 2, 1, xsem_fast_memory_int0_k2_attn_idx, 0x1440040, 0x144004c, | |
8060 | 0x1440048, | |
8061 | 0x1440044 | |
8062 | }; | |
8063 | ||
8064 | static struct attn_hw_reg *xsem_int_k2_regs[3] = { | |
8065 | &xsem_int0_k2, &xsem_int1_k2, &xsem_fast_memory_int0_k2, | |
8066 | }; | |
8067 | ||
8068 | #ifdef ATTN_DESC | |
8069 | static const char *xsem_prty_attn_desc[24] = { | |
8070 | "xsem_vfc_rbc_parity_error", | |
8071 | "xsem_storm_rf_parity_error", | |
8072 | "xsem_reg_gen_parity_error", | |
8073 | "xsem_mem006_i_ecc_0_rf_int", | |
8074 | "xsem_mem006_i_ecc_1_rf_int", | |
8075 | "xsem_mem005_i_mem_prty", | |
8076 | "xsem_mem002_i_mem_prty", | |
8077 | "xsem_mem004_i_mem_prty", | |
8078 | "xsem_mem003_i_mem_prty", | |
8079 | "xsem_mem001_i_mem_prty", | |
8080 | "xsem_fast_memory_mem024_i_mem_prty", | |
8081 | "xsem_fast_memory_mem023_i_mem_prty", | |
8082 | "xsem_fast_memory_mem022_i_mem_prty", | |
8083 | "xsem_fast_memory_mem021_i_mem_prty", | |
8084 | "xsem_fast_memory_mem020_i_mem_prty", | |
8085 | "xsem_fast_memory_mem019_i_mem_prty", | |
8086 | "xsem_fast_memory_mem018_i_mem_prty", | |
8087 | "xsem_fast_memory_vfc_config_mem005_i_ecc_rf_int", | |
8088 | "xsem_fast_memory_vfc_config_mem002_i_ecc_rf_int", | |
8089 | "xsem_fast_memory_vfc_config_mem006_i_mem_prty", | |
8090 | "xsem_fast_memory_vfc_config_mem001_i_mem_prty", | |
8091 | "xsem_fast_memory_vfc_config_mem004_i_mem_prty", | |
8092 | "xsem_fast_memory_vfc_config_mem003_i_mem_prty", | |
8093 | "xsem_fast_memory_vfc_config_mem007_i_mem_prty", | |
8094 | }; | |
8095 | #else | |
8096 | #define xsem_prty_attn_desc OSAL_NULL | |
8097 | #endif | |
8098 | ||
8099 | static const u16 xsem_prty0_bb_a0_attn_idx[3] = { | |
8100 | 0, 1, 2, | |
8101 | }; | |
8102 | ||
8103 | static struct attn_hw_reg xsem_prty0_bb_a0 = { | |
8104 | 0, 3, xsem_prty0_bb_a0_attn_idx, 0x14000c8, 0x14000d4, 0x14000d0, | |
8105 | 0x14000cc | |
8106 | }; | |
8107 | ||
8108 | static const u16 xsem_prty1_bb_a0_attn_idx[7] = { | |
8109 | 3, 4, 5, 6, 7, 8, 9, | |
8110 | }; | |
8111 | ||
8112 | static struct attn_hw_reg xsem_prty1_bb_a0 = { | |
8113 | 1, 7, xsem_prty1_bb_a0_attn_idx, 0x1400200, 0x140020c, 0x1400208, | |
8114 | 0x1400204 | |
8115 | }; | |
8116 | ||
8117 | static struct attn_hw_reg *xsem_prty_bb_a0_regs[2] = { | |
8118 | &xsem_prty0_bb_a0, &xsem_prty1_bb_a0, | |
8119 | }; | |
8120 | ||
8121 | static const u16 xsem_prty0_bb_b0_attn_idx[3] = { | |
8122 | 0, 1, 2, | |
8123 | }; | |
8124 | ||
8125 | static struct attn_hw_reg xsem_prty0_bb_b0 = { | |
8126 | 0, 3, xsem_prty0_bb_b0_attn_idx, 0x14000c8, 0x14000d4, 0x14000d0, | |
8127 | 0x14000cc | |
8128 | }; | |
8129 | ||
8130 | static const u16 xsem_prty1_bb_b0_attn_idx[7] = { | |
8131 | 3, 4, 5, 6, 7, 8, 9, | |
8132 | }; | |
8133 | ||
8134 | static struct attn_hw_reg xsem_prty1_bb_b0 = { | |
8135 | 1, 7, xsem_prty1_bb_b0_attn_idx, 0x1400200, 0x140020c, 0x1400208, | |
8136 | 0x1400204 | |
8137 | }; | |
8138 | ||
8139 | static struct attn_hw_reg *xsem_prty_bb_b0_regs[2] = { | |
8140 | &xsem_prty0_bb_b0, &xsem_prty1_bb_b0, | |
8141 | }; | |
8142 | ||
8143 | static const u16 xsem_prty0_k2_attn_idx[3] = { | |
8144 | 0, 1, 2, | |
8145 | }; | |
8146 | ||
8147 | static struct attn_hw_reg xsem_prty0_k2 = { | |
8148 | 0, 3, xsem_prty0_k2_attn_idx, 0x14000c8, 0x14000d4, 0x14000d0, | |
8149 | 0x14000cc | |
8150 | }; | |
8151 | ||
8152 | static const u16 xsem_prty1_k2_attn_idx[7] = { | |
8153 | 3, 4, 5, 6, 7, 8, 9, | |
8154 | }; | |
8155 | ||
8156 | static struct attn_hw_reg xsem_prty1_k2 = { | |
8157 | 1, 7, xsem_prty1_k2_attn_idx, 0x1400200, 0x140020c, 0x1400208, | |
8158 | 0x1400204 | |
8159 | }; | |
8160 | ||
8161 | static const u16 xsem_fast_memory_prty1_k2_attn_idx[7] = { | |
8162 | 10, 11, 12, 13, 14, 15, 16, | |
8163 | }; | |
8164 | ||
8165 | static struct attn_hw_reg xsem_fast_memory_prty1_k2 = { | |
8166 | 2, 7, xsem_fast_memory_prty1_k2_attn_idx, 0x1440200, 0x144020c, | |
8167 | 0x1440208, | |
8168 | 0x1440204 | |
8169 | }; | |
8170 | ||
8171 | static struct attn_hw_reg *xsem_prty_k2_regs[3] = { | |
8172 | &xsem_prty0_k2, &xsem_prty1_k2, &xsem_fast_memory_prty1_k2, | |
8173 | }; | |
8174 | ||
8175 | #ifdef ATTN_DESC | |
8176 | static const char *ysem_int_attn_desc[46] = { | |
8177 | "ysem_address_error", | |
8178 | "ysem_fic_last_error", | |
8179 | "ysem_fic_length_error", | |
8180 | "ysem_fic_fifo_error", | |
8181 | "ysem_pas_buf_fifo_error", | |
8182 | "ysem_sync_fin_pop_error", | |
8183 | "ysem_sync_dra_wr_push_error", | |
8184 | "ysem_sync_dra_wr_pop_error", | |
8185 | "ysem_sync_dra_rd_push_error", | |
8186 | "ysem_sync_dra_rd_pop_error", | |
8187 | "ysem_sync_fin_push_error", | |
8188 | "ysem_sem_fast_address_error", | |
8189 | "ysem_cam_lsb_inp_fifo", | |
8190 | "ysem_cam_msb_inp_fifo", | |
8191 | "ysem_cam_out_fifo", | |
8192 | "ysem_fin_fifo", | |
8193 | "ysem_thread_fifo_error", | |
8194 | "ysem_thread_overrun", | |
8195 | "ysem_sync_ext_store_push_error", | |
8196 | "ysem_sync_ext_store_pop_error", | |
8197 | "ysem_sync_ext_load_push_error", | |
8198 | "ysem_sync_ext_load_pop_error", | |
8199 | "ysem_sync_ram_rd_push_error", | |
8200 | "ysem_sync_ram_rd_pop_error", | |
8201 | "ysem_sync_ram_wr_pop_error", | |
8202 | "ysem_sync_ram_wr_push_error", | |
8203 | "ysem_sync_dbg_push_error", | |
8204 | "ysem_sync_dbg_pop_error", | |
8205 | "ysem_dbg_fifo_error", | |
8206 | "ysem_cam_msb2_inp_fifo", | |
8207 | "ysem_vfc_interrupt", | |
8208 | "ysem_vfc_out_fifo_error", | |
8209 | "ysem_storm_stack_uf_attn", | |
8210 | "ysem_storm_stack_of_attn", | |
8211 | "ysem_storm_runtime_error", | |
8212 | "ysem_ext_load_pend_wr_error", | |
8213 | "ysem_thread_rls_orun_error", | |
8214 | "ysem_thread_rls_aloc_error", | |
8215 | "ysem_thread_rls_vld_error", | |
8216 | "ysem_ext_thread_oor_error", | |
8217 | "ysem_ord_id_fifo_error", | |
8218 | "ysem_invld_foc_error", | |
8219 | "ysem_ext_ld_len_error", | |
8220 | "ysem_thrd_ord_fifo_error", | |
8221 | "ysem_invld_thrd_ord_error", | |
8222 | "ysem_fast_memory_address_error", | |
8223 | }; | |
8224 | #else | |
8225 | #define ysem_int_attn_desc OSAL_NULL | |
8226 | #endif | |
8227 | ||
8228 | static const u16 ysem_int0_bb_a0_attn_idx[32] = { | |
8229 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
8230 | 20, | |
8231 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
8232 | }; | |
8233 | ||
8234 | static struct attn_hw_reg ysem_int0_bb_a0 = { | |
8235 | 0, 32, ysem_int0_bb_a0_attn_idx, 0x1500040, 0x150004c, 0x1500048, | |
8236 | 0x1500044 | |
8237 | }; | |
8238 | ||
8239 | static const u16 ysem_int1_bb_a0_attn_idx[13] = { | |
8240 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, | |
8241 | }; | |
8242 | ||
8243 | static struct attn_hw_reg ysem_int1_bb_a0 = { | |
8244 | 1, 13, ysem_int1_bb_a0_attn_idx, 0x1500050, 0x150005c, 0x1500058, | |
8245 | 0x1500054 | |
8246 | }; | |
8247 | ||
8248 | static const u16 ysem_fast_memory_int0_bb_a0_attn_idx[1] = { | |
8249 | 45, | |
8250 | }; | |
8251 | ||
8252 | static struct attn_hw_reg ysem_fast_memory_int0_bb_a0 = { | |
8253 | 2, 1, ysem_fast_memory_int0_bb_a0_attn_idx, 0x1540040, 0x154004c, | |
8254 | 0x1540048, 0x1540044 | |
8255 | }; | |
8256 | ||
8257 | static struct attn_hw_reg *ysem_int_bb_a0_regs[3] = { | |
8258 | &ysem_int0_bb_a0, &ysem_int1_bb_a0, &ysem_fast_memory_int0_bb_a0, | |
8259 | }; | |
8260 | ||
8261 | static const u16 ysem_int0_bb_b0_attn_idx[32] = { | |
8262 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
8263 | 20, | |
8264 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
8265 | }; | |
8266 | ||
8267 | static struct attn_hw_reg ysem_int0_bb_b0 = { | |
8268 | 0, 32, ysem_int0_bb_b0_attn_idx, 0x1500040, 0x150004c, 0x1500048, | |
8269 | 0x1500044 | |
8270 | }; | |
8271 | ||
8272 | static const u16 ysem_int1_bb_b0_attn_idx[13] = { | |
8273 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, | |
8274 | }; | |
8275 | ||
8276 | static struct attn_hw_reg ysem_int1_bb_b0 = { | |
8277 | 1, 13, ysem_int1_bb_b0_attn_idx, 0x1500050, 0x150005c, 0x1500058, | |
8278 | 0x1500054 | |
8279 | }; | |
8280 | ||
8281 | static const u16 ysem_fast_memory_int0_bb_b0_attn_idx[1] = { | |
8282 | 45, | |
8283 | }; | |
8284 | ||
8285 | static struct attn_hw_reg ysem_fast_memory_int0_bb_b0 = { | |
8286 | 2, 1, ysem_fast_memory_int0_bb_b0_attn_idx, 0x1540040, 0x154004c, | |
8287 | 0x1540048, 0x1540044 | |
8288 | }; | |
8289 | ||
8290 | static struct attn_hw_reg *ysem_int_bb_b0_regs[3] = { | |
8291 | &ysem_int0_bb_b0, &ysem_int1_bb_b0, &ysem_fast_memory_int0_bb_b0, | |
8292 | }; | |
8293 | ||
8294 | static const u16 ysem_int0_k2_attn_idx[32] = { | |
8295 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
8296 | 20, | |
8297 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
8298 | }; | |
8299 | ||
8300 | static struct attn_hw_reg ysem_int0_k2 = { | |
8301 | 0, 32, ysem_int0_k2_attn_idx, 0x1500040, 0x150004c, 0x1500048, | |
8302 | 0x1500044 | |
8303 | }; | |
8304 | ||
8305 | static const u16 ysem_int1_k2_attn_idx[13] = { | |
8306 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, | |
8307 | }; | |
8308 | ||
8309 | static struct attn_hw_reg ysem_int1_k2 = { | |
8310 | 1, 13, ysem_int1_k2_attn_idx, 0x1500050, 0x150005c, 0x1500058, | |
8311 | 0x1500054 | |
8312 | }; | |
8313 | ||
8314 | static const u16 ysem_fast_memory_int0_k2_attn_idx[1] = { | |
8315 | 45, | |
8316 | }; | |
8317 | ||
8318 | static struct attn_hw_reg ysem_fast_memory_int0_k2 = { | |
8319 | 2, 1, ysem_fast_memory_int0_k2_attn_idx, 0x1540040, 0x154004c, | |
8320 | 0x1540048, | |
8321 | 0x1540044 | |
8322 | }; | |
8323 | ||
8324 | static struct attn_hw_reg *ysem_int_k2_regs[3] = { | |
8325 | &ysem_int0_k2, &ysem_int1_k2, &ysem_fast_memory_int0_k2, | |
8326 | }; | |
8327 | ||
8328 | #ifdef ATTN_DESC | |
8329 | static const char *ysem_prty_attn_desc[24] = { | |
8330 | "ysem_vfc_rbc_parity_error", | |
8331 | "ysem_storm_rf_parity_error", | |
8332 | "ysem_reg_gen_parity_error", | |
8333 | "ysem_mem006_i_ecc_0_rf_int", | |
8334 | "ysem_mem006_i_ecc_1_rf_int", | |
8335 | "ysem_mem005_i_mem_prty", | |
8336 | "ysem_mem002_i_mem_prty", | |
8337 | "ysem_mem004_i_mem_prty", | |
8338 | "ysem_mem003_i_mem_prty", | |
8339 | "ysem_mem001_i_mem_prty", | |
8340 | "ysem_fast_memory_mem024_i_mem_prty", | |
8341 | "ysem_fast_memory_mem023_i_mem_prty", | |
8342 | "ysem_fast_memory_mem022_i_mem_prty", | |
8343 | "ysem_fast_memory_mem021_i_mem_prty", | |
8344 | "ysem_fast_memory_mem020_i_mem_prty", | |
8345 | "ysem_fast_memory_mem019_i_mem_prty", | |
8346 | "ysem_fast_memory_mem018_i_mem_prty", | |
8347 | "ysem_fast_memory_vfc_config_mem005_i_ecc_rf_int", | |
8348 | "ysem_fast_memory_vfc_config_mem002_i_ecc_rf_int", | |
8349 | "ysem_fast_memory_vfc_config_mem006_i_mem_prty", | |
8350 | "ysem_fast_memory_vfc_config_mem001_i_mem_prty", | |
8351 | "ysem_fast_memory_vfc_config_mem004_i_mem_prty", | |
8352 | "ysem_fast_memory_vfc_config_mem003_i_mem_prty", | |
8353 | "ysem_fast_memory_vfc_config_mem007_i_mem_prty", | |
8354 | }; | |
8355 | #else | |
8356 | #define ysem_prty_attn_desc OSAL_NULL | |
8357 | #endif | |
8358 | ||
8359 | static const u16 ysem_prty0_bb_a0_attn_idx[3] = { | |
8360 | 0, 1, 2, | |
8361 | }; | |
8362 | ||
8363 | static struct attn_hw_reg ysem_prty0_bb_a0 = { | |
8364 | 0, 3, ysem_prty0_bb_a0_attn_idx, 0x15000c8, 0x15000d4, 0x15000d0, | |
8365 | 0x15000cc | |
8366 | }; | |
8367 | ||
8368 | static const u16 ysem_prty1_bb_a0_attn_idx[7] = { | |
8369 | 3, 4, 5, 6, 7, 8, 9, | |
8370 | }; | |
8371 | ||
8372 | static struct attn_hw_reg ysem_prty1_bb_a0 = { | |
8373 | 1, 7, ysem_prty1_bb_a0_attn_idx, 0x1500200, 0x150020c, 0x1500208, | |
8374 | 0x1500204 | |
8375 | }; | |
8376 | ||
8377 | static struct attn_hw_reg *ysem_prty_bb_a0_regs[2] = { | |
8378 | &ysem_prty0_bb_a0, &ysem_prty1_bb_a0, | |
8379 | }; | |
8380 | ||
8381 | static const u16 ysem_prty0_bb_b0_attn_idx[3] = { | |
8382 | 0, 1, 2, | |
8383 | }; | |
8384 | ||
8385 | static struct attn_hw_reg ysem_prty0_bb_b0 = { | |
8386 | 0, 3, ysem_prty0_bb_b0_attn_idx, 0x15000c8, 0x15000d4, 0x15000d0, | |
8387 | 0x15000cc | |
8388 | }; | |
8389 | ||
8390 | static const u16 ysem_prty1_bb_b0_attn_idx[7] = { | |
8391 | 3, 4, 5, 6, 7, 8, 9, | |
8392 | }; | |
8393 | ||
8394 | static struct attn_hw_reg ysem_prty1_bb_b0 = { | |
8395 | 1, 7, ysem_prty1_bb_b0_attn_idx, 0x1500200, 0x150020c, 0x1500208, | |
8396 | 0x1500204 | |
8397 | }; | |
8398 | ||
8399 | static struct attn_hw_reg *ysem_prty_bb_b0_regs[2] = { | |
8400 | &ysem_prty0_bb_b0, &ysem_prty1_bb_b0, | |
8401 | }; | |
8402 | ||
8403 | static const u16 ysem_prty0_k2_attn_idx[3] = { | |
8404 | 0, 1, 2, | |
8405 | }; | |
8406 | ||
8407 | static struct attn_hw_reg ysem_prty0_k2 = { | |
8408 | 0, 3, ysem_prty0_k2_attn_idx, 0x15000c8, 0x15000d4, 0x15000d0, | |
8409 | 0x15000cc | |
8410 | }; | |
8411 | ||
8412 | static const u16 ysem_prty1_k2_attn_idx[7] = { | |
8413 | 3, 4, 5, 6, 7, 8, 9, | |
8414 | }; | |
8415 | ||
8416 | static struct attn_hw_reg ysem_prty1_k2 = { | |
8417 | 1, 7, ysem_prty1_k2_attn_idx, 0x1500200, 0x150020c, 0x1500208, | |
8418 | 0x1500204 | |
8419 | }; | |
8420 | ||
8421 | static const u16 ysem_fast_memory_prty1_k2_attn_idx[7] = { | |
8422 | 10, 11, 12, 13, 14, 15, 16, | |
8423 | }; | |
8424 | ||
8425 | static struct attn_hw_reg ysem_fast_memory_prty1_k2 = { | |
8426 | 2, 7, ysem_fast_memory_prty1_k2_attn_idx, 0x1540200, 0x154020c, | |
8427 | 0x1540208, | |
8428 | 0x1540204 | |
8429 | }; | |
8430 | ||
8431 | static struct attn_hw_reg *ysem_prty_k2_regs[3] = { | |
8432 | &ysem_prty0_k2, &ysem_prty1_k2, &ysem_fast_memory_prty1_k2, | |
8433 | }; | |
8434 | ||
8435 | #ifdef ATTN_DESC | |
8436 | static const char *psem_int_attn_desc[46] = { | |
8437 | "psem_address_error", | |
8438 | "psem_fic_last_error", | |
8439 | "psem_fic_length_error", | |
8440 | "psem_fic_fifo_error", | |
8441 | "psem_pas_buf_fifo_error", | |
8442 | "psem_sync_fin_pop_error", | |
8443 | "psem_sync_dra_wr_push_error", | |
8444 | "psem_sync_dra_wr_pop_error", | |
8445 | "psem_sync_dra_rd_push_error", | |
8446 | "psem_sync_dra_rd_pop_error", | |
8447 | "psem_sync_fin_push_error", | |
8448 | "psem_sem_fast_address_error", | |
8449 | "psem_cam_lsb_inp_fifo", | |
8450 | "psem_cam_msb_inp_fifo", | |
8451 | "psem_cam_out_fifo", | |
8452 | "psem_fin_fifo", | |
8453 | "psem_thread_fifo_error", | |
8454 | "psem_thread_overrun", | |
8455 | "psem_sync_ext_store_push_error", | |
8456 | "psem_sync_ext_store_pop_error", | |
8457 | "psem_sync_ext_load_push_error", | |
8458 | "psem_sync_ext_load_pop_error", | |
8459 | "psem_sync_ram_rd_push_error", | |
8460 | "psem_sync_ram_rd_pop_error", | |
8461 | "psem_sync_ram_wr_pop_error", | |
8462 | "psem_sync_ram_wr_push_error", | |
8463 | "psem_sync_dbg_push_error", | |
8464 | "psem_sync_dbg_pop_error", | |
8465 | "psem_dbg_fifo_error", | |
8466 | "psem_cam_msb2_inp_fifo", | |
8467 | "psem_vfc_interrupt", | |
8468 | "psem_vfc_out_fifo_error", | |
8469 | "psem_storm_stack_uf_attn", | |
8470 | "psem_storm_stack_of_attn", | |
8471 | "psem_storm_runtime_error", | |
8472 | "psem_ext_load_pend_wr_error", | |
8473 | "psem_thread_rls_orun_error", | |
8474 | "psem_thread_rls_aloc_error", | |
8475 | "psem_thread_rls_vld_error", | |
8476 | "psem_ext_thread_oor_error", | |
8477 | "psem_ord_id_fifo_error", | |
8478 | "psem_invld_foc_error", | |
8479 | "psem_ext_ld_len_error", | |
8480 | "psem_thrd_ord_fifo_error", | |
8481 | "psem_invld_thrd_ord_error", | |
8482 | "psem_fast_memory_address_error", | |
8483 | }; | |
8484 | #else | |
8485 | #define psem_int_attn_desc OSAL_NULL | |
8486 | #endif | |
8487 | ||
8488 | static const u16 psem_int0_bb_a0_attn_idx[32] = { | |
8489 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
8490 | 20, | |
8491 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
8492 | }; | |
8493 | ||
8494 | static struct attn_hw_reg psem_int0_bb_a0 = { | |
8495 | 0, 32, psem_int0_bb_a0_attn_idx, 0x1600040, 0x160004c, 0x1600048, | |
8496 | 0x1600044 | |
8497 | }; | |
8498 | ||
8499 | static const u16 psem_int1_bb_a0_attn_idx[13] = { | |
8500 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, | |
8501 | }; | |
8502 | ||
8503 | static struct attn_hw_reg psem_int1_bb_a0 = { | |
8504 | 1, 13, psem_int1_bb_a0_attn_idx, 0x1600050, 0x160005c, 0x1600058, | |
8505 | 0x1600054 | |
8506 | }; | |
8507 | ||
8508 | static const u16 psem_fast_memory_int0_bb_a0_attn_idx[1] = { | |
8509 | 45, | |
8510 | }; | |
8511 | ||
8512 | static struct attn_hw_reg psem_fast_memory_int0_bb_a0 = { | |
8513 | 2, 1, psem_fast_memory_int0_bb_a0_attn_idx, 0x1640040, 0x164004c, | |
8514 | 0x1640048, 0x1640044 | |
8515 | }; | |
8516 | ||
8517 | static struct attn_hw_reg *psem_int_bb_a0_regs[3] = { | |
8518 | &psem_int0_bb_a0, &psem_int1_bb_a0, &psem_fast_memory_int0_bb_a0, | |
8519 | }; | |
8520 | ||
8521 | static const u16 psem_int0_bb_b0_attn_idx[32] = { | |
8522 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
8523 | 20, | |
8524 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
8525 | }; | |
8526 | ||
8527 | static struct attn_hw_reg psem_int0_bb_b0 = { | |
8528 | 0, 32, psem_int0_bb_b0_attn_idx, 0x1600040, 0x160004c, 0x1600048, | |
8529 | 0x1600044 | |
8530 | }; | |
8531 | ||
8532 | static const u16 psem_int1_bb_b0_attn_idx[13] = { | |
8533 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, | |
8534 | }; | |
8535 | ||
8536 | static struct attn_hw_reg psem_int1_bb_b0 = { | |
8537 | 1, 13, psem_int1_bb_b0_attn_idx, 0x1600050, 0x160005c, 0x1600058, | |
8538 | 0x1600054 | |
8539 | }; | |
8540 | ||
8541 | static const u16 psem_fast_memory_int0_bb_b0_attn_idx[1] = { | |
8542 | 45, | |
8543 | }; | |
8544 | ||
8545 | static struct attn_hw_reg psem_fast_memory_int0_bb_b0 = { | |
8546 | 2, 1, psem_fast_memory_int0_bb_b0_attn_idx, 0x1640040, 0x164004c, | |
8547 | 0x1640048, 0x1640044 | |
8548 | }; | |
8549 | ||
8550 | static struct attn_hw_reg *psem_int_bb_b0_regs[3] = { | |
8551 | &psem_int0_bb_b0, &psem_int1_bb_b0, &psem_fast_memory_int0_bb_b0, | |
8552 | }; | |
8553 | ||
8554 | static const u16 psem_int0_k2_attn_idx[32] = { | |
8555 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
8556 | 20, | |
8557 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
8558 | }; | |
8559 | ||
8560 | static struct attn_hw_reg psem_int0_k2 = { | |
8561 | 0, 32, psem_int0_k2_attn_idx, 0x1600040, 0x160004c, 0x1600048, | |
8562 | 0x1600044 | |
8563 | }; | |
8564 | ||
8565 | static const u16 psem_int1_k2_attn_idx[13] = { | |
8566 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, | |
8567 | }; | |
8568 | ||
8569 | static struct attn_hw_reg psem_int1_k2 = { | |
8570 | 1, 13, psem_int1_k2_attn_idx, 0x1600050, 0x160005c, 0x1600058, | |
8571 | 0x1600054 | |
8572 | }; | |
8573 | ||
8574 | static const u16 psem_fast_memory_int0_k2_attn_idx[1] = { | |
8575 | 45, | |
8576 | }; | |
8577 | ||
8578 | static struct attn_hw_reg psem_fast_memory_int0_k2 = { | |
8579 | 2, 1, psem_fast_memory_int0_k2_attn_idx, 0x1640040, 0x164004c, | |
8580 | 0x1640048, | |
8581 | 0x1640044 | |
8582 | }; | |
8583 | ||
8584 | static struct attn_hw_reg *psem_int_k2_regs[3] = { | |
8585 | &psem_int0_k2, &psem_int1_k2, &psem_fast_memory_int0_k2, | |
8586 | }; | |
8587 | ||
8588 | #ifdef ATTN_DESC | |
8589 | static const char *psem_prty_attn_desc[23] = { | |
8590 | "psem_vfc_rbc_parity_error", | |
8591 | "psem_storm_rf_parity_error", | |
8592 | "psem_reg_gen_parity_error", | |
8593 | "psem_mem005_i_ecc_0_rf_int", | |
8594 | "psem_mem005_i_ecc_1_rf_int", | |
8595 | "psem_mem004_i_mem_prty", | |
8596 | "psem_mem002_i_mem_prty", | |
8597 | "psem_mem003_i_mem_prty", | |
8598 | "psem_mem001_i_mem_prty", | |
8599 | "psem_fast_memory_mem024_i_mem_prty", | |
8600 | "psem_fast_memory_mem023_i_mem_prty", | |
8601 | "psem_fast_memory_mem022_i_mem_prty", | |
8602 | "psem_fast_memory_mem021_i_mem_prty", | |
8603 | "psem_fast_memory_mem020_i_mem_prty", | |
8604 | "psem_fast_memory_mem019_i_mem_prty", | |
8605 | "psem_fast_memory_mem018_i_mem_prty", | |
8606 | "psem_fast_memory_vfc_config_mem005_i_ecc_rf_int", | |
8607 | "psem_fast_memory_vfc_config_mem002_i_ecc_rf_int", | |
8608 | "psem_fast_memory_vfc_config_mem006_i_mem_prty", | |
8609 | "psem_fast_memory_vfc_config_mem001_i_mem_prty", | |
8610 | "psem_fast_memory_vfc_config_mem004_i_mem_prty", | |
8611 | "psem_fast_memory_vfc_config_mem003_i_mem_prty", | |
8612 | "psem_fast_memory_vfc_config_mem007_i_mem_prty", | |
8613 | }; | |
8614 | #else | |
8615 | #define psem_prty_attn_desc OSAL_NULL | |
8616 | #endif | |
8617 | ||
8618 | static const u16 psem_prty0_bb_a0_attn_idx[3] = { | |
8619 | 0, 1, 2, | |
8620 | }; | |
8621 | ||
8622 | static struct attn_hw_reg psem_prty0_bb_a0 = { | |
8623 | 0, 3, psem_prty0_bb_a0_attn_idx, 0x16000c8, 0x16000d4, 0x16000d0, | |
8624 | 0x16000cc | |
8625 | }; | |
8626 | ||
8627 | static const u16 psem_prty1_bb_a0_attn_idx[6] = { | |
8628 | 3, 4, 5, 6, 7, 8, | |
8629 | }; | |
8630 | ||
8631 | static struct attn_hw_reg psem_prty1_bb_a0 = { | |
8632 | 1, 6, psem_prty1_bb_a0_attn_idx, 0x1600200, 0x160020c, 0x1600208, | |
8633 | 0x1600204 | |
8634 | }; | |
8635 | ||
8636 | static const u16 psem_fast_memory_vfc_config_prty1_bb_a0_attn_idx[6] = { | |
8637 | 16, 17, 19, 20, 21, 22, | |
8638 | }; | |
8639 | ||
8640 | static struct attn_hw_reg psem_fast_memory_vfc_config_prty1_bb_a0 = { | |
8641 | 2, 6, psem_fast_memory_vfc_config_prty1_bb_a0_attn_idx, 0x164a200, | |
8642 | 0x164a20c, 0x164a208, 0x164a204 | |
8643 | }; | |
8644 | ||
8645 | static struct attn_hw_reg *psem_prty_bb_a0_regs[3] = { | |
8646 | &psem_prty0_bb_a0, &psem_prty1_bb_a0, | |
8647 | &psem_fast_memory_vfc_config_prty1_bb_a0, | |
8648 | }; | |
8649 | ||
8650 | static const u16 psem_prty0_bb_b0_attn_idx[3] = { | |
8651 | 0, 1, 2, | |
8652 | }; | |
8653 | ||
8654 | static struct attn_hw_reg psem_prty0_bb_b0 = { | |
8655 | 0, 3, psem_prty0_bb_b0_attn_idx, 0x16000c8, 0x16000d4, 0x16000d0, | |
8656 | 0x16000cc | |
8657 | }; | |
8658 | ||
8659 | static const u16 psem_prty1_bb_b0_attn_idx[6] = { | |
8660 | 3, 4, 5, 6, 7, 8, | |
8661 | }; | |
8662 | ||
8663 | static struct attn_hw_reg psem_prty1_bb_b0 = { | |
8664 | 1, 6, psem_prty1_bb_b0_attn_idx, 0x1600200, 0x160020c, 0x1600208, | |
8665 | 0x1600204 | |
8666 | }; | |
8667 | ||
8668 | static const u16 psem_fast_memory_vfc_config_prty1_bb_b0_attn_idx[6] = { | |
8669 | 16, 17, 19, 20, 21, 22, | |
8670 | }; | |
8671 | ||
8672 | static struct attn_hw_reg psem_fast_memory_vfc_config_prty1_bb_b0 = { | |
8673 | 2, 6, psem_fast_memory_vfc_config_prty1_bb_b0_attn_idx, 0x164a200, | |
8674 | 0x164a20c, 0x164a208, 0x164a204 | |
8675 | }; | |
8676 | ||
8677 | static struct attn_hw_reg *psem_prty_bb_b0_regs[3] = { | |
8678 | &psem_prty0_bb_b0, &psem_prty1_bb_b0, | |
8679 | &psem_fast_memory_vfc_config_prty1_bb_b0, | |
8680 | }; | |
8681 | ||
8682 | static const u16 psem_prty0_k2_attn_idx[3] = { | |
8683 | 0, 1, 2, | |
8684 | }; | |
8685 | ||
8686 | static struct attn_hw_reg psem_prty0_k2 = { | |
8687 | 0, 3, psem_prty0_k2_attn_idx, 0x16000c8, 0x16000d4, 0x16000d0, | |
8688 | 0x16000cc | |
8689 | }; | |
8690 | ||
8691 | static const u16 psem_prty1_k2_attn_idx[6] = { | |
8692 | 3, 4, 5, 6, 7, 8, | |
8693 | }; | |
8694 | ||
8695 | static struct attn_hw_reg psem_prty1_k2 = { | |
8696 | 1, 6, psem_prty1_k2_attn_idx, 0x1600200, 0x160020c, 0x1600208, | |
8697 | 0x1600204 | |
8698 | }; | |
8699 | ||
8700 | static const u16 psem_fast_memory_prty1_k2_attn_idx[7] = { | |
8701 | 9, 10, 11, 12, 13, 14, 15, | |
8702 | }; | |
8703 | ||
8704 | static struct attn_hw_reg psem_fast_memory_prty1_k2 = { | |
8705 | 2, 7, psem_fast_memory_prty1_k2_attn_idx, 0x1640200, 0x164020c, | |
8706 | 0x1640208, | |
8707 | 0x1640204 | |
8708 | }; | |
8709 | ||
8710 | static const u16 psem_fast_memory_vfc_config_prty1_k2_attn_idx[6] = { | |
8711 | 16, 17, 18, 19, 20, 21, | |
8712 | }; | |
8713 | ||
8714 | static struct attn_hw_reg psem_fast_memory_vfc_config_prty1_k2 = { | |
8715 | 3, 6, psem_fast_memory_vfc_config_prty1_k2_attn_idx, 0x164a200, | |
8716 | 0x164a20c, | |
8717 | 0x164a208, 0x164a204 | |
8718 | }; | |
8719 | ||
8720 | static struct attn_hw_reg *psem_prty_k2_regs[4] = { | |
8721 | &psem_prty0_k2, &psem_prty1_k2, &psem_fast_memory_prty1_k2, | |
8722 | &psem_fast_memory_vfc_config_prty1_k2, | |
8723 | }; | |
8724 | ||
8725 | #ifdef ATTN_DESC | |
8726 | static const char *rss_int_attn_desc[12] = { | |
8727 | "rss_address_error", | |
8728 | "rss_msg_inp_cnt_error", | |
8729 | "rss_msg_out_cnt_error", | |
8730 | "rss_inp_state_error", | |
8731 | "rss_out_state_error", | |
8732 | "rss_main_state_error", | |
8733 | "rss_calc_state_error", | |
8734 | "rss_inp_fifo_error", | |
8735 | "rss_cmd_fifo_error", | |
8736 | "rss_msg_fifo_error", | |
8737 | "rss_rsp_fifo_error", | |
8738 | "rss_hdr_fifo_error", | |
8739 | }; | |
8740 | #else | |
8741 | #define rss_int_attn_desc OSAL_NULL | |
8742 | #endif | |
8743 | ||
8744 | static const u16 rss_int0_bb_a0_attn_idx[12] = { | |
8745 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, | |
8746 | }; | |
8747 | ||
8748 | static struct attn_hw_reg rss_int0_bb_a0 = { | |
8749 | 0, 12, rss_int0_bb_a0_attn_idx, 0x238980, 0x23898c, 0x238988, 0x238984 | |
8750 | }; | |
8751 | ||
8752 | static struct attn_hw_reg *rss_int_bb_a0_regs[1] = { | |
8753 | &rss_int0_bb_a0, | |
8754 | }; | |
8755 | ||
8756 | static const u16 rss_int0_bb_b0_attn_idx[12] = { | |
8757 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, | |
8758 | }; | |
8759 | ||
8760 | static struct attn_hw_reg rss_int0_bb_b0 = { | |
8761 | 0, 12, rss_int0_bb_b0_attn_idx, 0x238980, 0x23898c, 0x238988, 0x238984 | |
8762 | }; | |
8763 | ||
8764 | static struct attn_hw_reg *rss_int_bb_b0_regs[1] = { | |
8765 | &rss_int0_bb_b0, | |
8766 | }; | |
8767 | ||
8768 | static const u16 rss_int0_k2_attn_idx[12] = { | |
8769 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, | |
8770 | }; | |
8771 | ||
8772 | static struct attn_hw_reg rss_int0_k2 = { | |
8773 | 0, 12, rss_int0_k2_attn_idx, 0x238980, 0x23898c, 0x238988, 0x238984 | |
8774 | }; | |
8775 | ||
8776 | static struct attn_hw_reg *rss_int_k2_regs[1] = { | |
8777 | &rss_int0_k2, | |
8778 | }; | |
8779 | ||
8780 | #ifdef ATTN_DESC | |
8781 | static const char *rss_prty_attn_desc[4] = { | |
8782 | "rss_mem002_i_ecc_rf_int", | |
8783 | "rss_mem001_i_ecc_rf_int", | |
8784 | "rss_mem003_i_mem_prty", | |
8785 | "rss_mem004_i_mem_prty", | |
8786 | }; | |
8787 | #else | |
8788 | #define rss_prty_attn_desc OSAL_NULL | |
8789 | #endif | |
8790 | ||
8791 | static const u16 rss_prty1_bb_a0_attn_idx[4] = { | |
8792 | 0, 1, 2, 3, | |
8793 | }; | |
8794 | ||
8795 | static struct attn_hw_reg rss_prty1_bb_a0 = { | |
8796 | 0, 4, rss_prty1_bb_a0_attn_idx, 0x238a00, 0x238a0c, 0x238a08, 0x238a04 | |
8797 | }; | |
8798 | ||
8799 | static struct attn_hw_reg *rss_prty_bb_a0_regs[1] = { | |
8800 | &rss_prty1_bb_a0, | |
8801 | }; | |
8802 | ||
8803 | static const u16 rss_prty1_bb_b0_attn_idx[4] = { | |
8804 | 0, 1, 2, 3, | |
8805 | }; | |
8806 | ||
8807 | static struct attn_hw_reg rss_prty1_bb_b0 = { | |
8808 | 0, 4, rss_prty1_bb_b0_attn_idx, 0x238a00, 0x238a0c, 0x238a08, 0x238a04 | |
8809 | }; | |
8810 | ||
8811 | static struct attn_hw_reg *rss_prty_bb_b0_regs[1] = { | |
8812 | &rss_prty1_bb_b0, | |
8813 | }; | |
8814 | ||
8815 | static const u16 rss_prty1_k2_attn_idx[4] = { | |
8816 | 0, 1, 2, 3, | |
8817 | }; | |
8818 | ||
8819 | static struct attn_hw_reg rss_prty1_k2 = { | |
8820 | 0, 4, rss_prty1_k2_attn_idx, 0x238a00, 0x238a0c, 0x238a08, 0x238a04 | |
8821 | }; | |
8822 | ||
8823 | static struct attn_hw_reg *rss_prty_k2_regs[1] = { | |
8824 | &rss_prty1_k2, | |
8825 | }; | |
8826 | ||
8827 | #ifdef ATTN_DESC | |
8828 | static const char *tmld_int_attn_desc[6] = { | |
8829 | "tmld_address_error", | |
8830 | "tmld_ld_hdr_err", | |
8831 | "tmld_ld_seg_msg_err", | |
8832 | "tmld_ld_tid_mini_cache_err", | |
8833 | "tmld_ld_cid_mini_cache_err", | |
8834 | "tmld_ld_long_message", | |
8835 | }; | |
8836 | #else | |
8837 | #define tmld_int_attn_desc OSAL_NULL | |
8838 | #endif | |
8839 | ||
8840 | static const u16 tmld_int0_bb_a0_attn_idx[6] = { | |
8841 | 0, 1, 2, 3, 4, 5, | |
8842 | }; | |
8843 | ||
8844 | static struct attn_hw_reg tmld_int0_bb_a0 = { | |
8845 | 0, 6, tmld_int0_bb_a0_attn_idx, 0x4d0180, 0x4d018c, 0x4d0188, 0x4d0184 | |
8846 | }; | |
8847 | ||
8848 | static struct attn_hw_reg *tmld_int_bb_a0_regs[1] = { | |
8849 | &tmld_int0_bb_a0, | |
8850 | }; | |
8851 | ||
8852 | static const u16 tmld_int0_bb_b0_attn_idx[6] = { | |
8853 | 0, 1, 2, 3, 4, 5, | |
8854 | }; | |
8855 | ||
8856 | static struct attn_hw_reg tmld_int0_bb_b0 = { | |
8857 | 0, 6, tmld_int0_bb_b0_attn_idx, 0x4d0180, 0x4d018c, 0x4d0188, 0x4d0184 | |
8858 | }; | |
8859 | ||
8860 | static struct attn_hw_reg *tmld_int_bb_b0_regs[1] = { | |
8861 | &tmld_int0_bb_b0, | |
8862 | }; | |
8863 | ||
8864 | static const u16 tmld_int0_k2_attn_idx[6] = { | |
8865 | 0, 1, 2, 3, 4, 5, | |
8866 | }; | |
8867 | ||
8868 | static struct attn_hw_reg tmld_int0_k2 = { | |
8869 | 0, 6, tmld_int0_k2_attn_idx, 0x4d0180, 0x4d018c, 0x4d0188, 0x4d0184 | |
8870 | }; | |
8871 | ||
8872 | static struct attn_hw_reg *tmld_int_k2_regs[1] = { | |
8873 | &tmld_int0_k2, | |
8874 | }; | |
8875 | ||
8876 | #ifdef ATTN_DESC | |
8877 | static const char *tmld_prty_attn_desc[8] = { | |
8878 | "tmld_mem006_i_ecc_rf_int", | |
8879 | "tmld_mem002_i_ecc_rf_int", | |
8880 | "tmld_mem003_i_mem_prty", | |
8881 | "tmld_mem004_i_mem_prty", | |
8882 | "tmld_mem007_i_mem_prty", | |
8883 | "tmld_mem008_i_mem_prty", | |
8884 | "tmld_mem005_i_mem_prty", | |
8885 | "tmld_mem001_i_mem_prty", | |
8886 | }; | |
8887 | #else | |
8888 | #define tmld_prty_attn_desc OSAL_NULL | |
8889 | #endif | |
8890 | ||
8891 | static const u16 tmld_prty1_bb_a0_attn_idx[8] = { | |
8892 | 0, 1, 2, 3, 4, 5, 6, 7, | |
8893 | }; | |
8894 | ||
8895 | static struct attn_hw_reg tmld_prty1_bb_a0 = { | |
8896 | 0, 8, tmld_prty1_bb_a0_attn_idx, 0x4d0200, 0x4d020c, 0x4d0208, 0x4d0204 | |
8897 | }; | |
8898 | ||
8899 | static struct attn_hw_reg *tmld_prty_bb_a0_regs[1] = { | |
8900 | &tmld_prty1_bb_a0, | |
8901 | }; | |
8902 | ||
8903 | static const u16 tmld_prty1_bb_b0_attn_idx[8] = { | |
8904 | 0, 1, 2, 3, 4, 5, 6, 7, | |
8905 | }; | |
8906 | ||
8907 | static struct attn_hw_reg tmld_prty1_bb_b0 = { | |
8908 | 0, 8, tmld_prty1_bb_b0_attn_idx, 0x4d0200, 0x4d020c, 0x4d0208, 0x4d0204 | |
8909 | }; | |
8910 | ||
8911 | static struct attn_hw_reg *tmld_prty_bb_b0_regs[1] = { | |
8912 | &tmld_prty1_bb_b0, | |
8913 | }; | |
8914 | ||
8915 | static const u16 tmld_prty1_k2_attn_idx[8] = { | |
8916 | 0, 1, 2, 3, 4, 5, 6, 7, | |
8917 | }; | |
8918 | ||
8919 | static struct attn_hw_reg tmld_prty1_k2 = { | |
8920 | 0, 8, tmld_prty1_k2_attn_idx, 0x4d0200, 0x4d020c, 0x4d0208, 0x4d0204 | |
8921 | }; | |
8922 | ||
8923 | static struct attn_hw_reg *tmld_prty_k2_regs[1] = { | |
8924 | &tmld_prty1_k2, | |
8925 | }; | |
8926 | ||
8927 | #ifdef ATTN_DESC | |
8928 | static const char *muld_int_attn_desc[6] = { | |
8929 | "muld_address_error", | |
8930 | "muld_ld_hdr_err", | |
8931 | "muld_ld_seg_msg_err", | |
8932 | "muld_ld_tid_mini_cache_err", | |
8933 | "muld_ld_cid_mini_cache_err", | |
8934 | "muld_ld_long_message", | |
8935 | }; | |
8936 | #else | |
8937 | #define muld_int_attn_desc OSAL_NULL | |
8938 | #endif | |
8939 | ||
8940 | static const u16 muld_int0_bb_a0_attn_idx[6] = { | |
8941 | 0, 1, 2, 3, 4, 5, | |
8942 | }; | |
8943 | ||
8944 | static struct attn_hw_reg muld_int0_bb_a0 = { | |
8945 | 0, 6, muld_int0_bb_a0_attn_idx, 0x4e0180, 0x4e018c, 0x4e0188, 0x4e0184 | |
8946 | }; | |
8947 | ||
8948 | static struct attn_hw_reg *muld_int_bb_a0_regs[1] = { | |
8949 | &muld_int0_bb_a0, | |
8950 | }; | |
8951 | ||
8952 | static const u16 muld_int0_bb_b0_attn_idx[6] = { | |
8953 | 0, 1, 2, 3, 4, 5, | |
8954 | }; | |
8955 | ||
8956 | static struct attn_hw_reg muld_int0_bb_b0 = { | |
8957 | 0, 6, muld_int0_bb_b0_attn_idx, 0x4e0180, 0x4e018c, 0x4e0188, 0x4e0184 | |
8958 | }; | |
8959 | ||
8960 | static struct attn_hw_reg *muld_int_bb_b0_regs[1] = { | |
8961 | &muld_int0_bb_b0, | |
8962 | }; | |
8963 | ||
8964 | static const u16 muld_int0_k2_attn_idx[6] = { | |
8965 | 0, 1, 2, 3, 4, 5, | |
8966 | }; | |
8967 | ||
8968 | static struct attn_hw_reg muld_int0_k2 = { | |
8969 | 0, 6, muld_int0_k2_attn_idx, 0x4e0180, 0x4e018c, 0x4e0188, 0x4e0184 | |
8970 | }; | |
8971 | ||
8972 | static struct attn_hw_reg *muld_int_k2_regs[1] = { | |
8973 | &muld_int0_k2, | |
8974 | }; | |
8975 | ||
8976 | #ifdef ATTN_DESC | |
8977 | static const char *muld_prty_attn_desc[10] = { | |
8978 | "muld_mem005_i_ecc_rf_int", | |
8979 | "muld_mem001_i_ecc_rf_int", | |
8980 | "muld_mem008_i_ecc_rf_int", | |
8981 | "muld_mem007_i_ecc_rf_int", | |
8982 | "muld_mem002_i_mem_prty", | |
8983 | "muld_mem003_i_mem_prty", | |
8984 | "muld_mem009_i_mem_prty", | |
8985 | "muld_mem010_i_mem_prty", | |
8986 | "muld_mem004_i_mem_prty", | |
8987 | "muld_mem006_i_mem_prty", | |
8988 | }; | |
8989 | #else | |
8990 | #define muld_prty_attn_desc OSAL_NULL | |
8991 | #endif | |
8992 | ||
8993 | static const u16 muld_prty1_bb_a0_attn_idx[10] = { | |
8994 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, | |
8995 | }; | |
8996 | ||
8997 | static struct attn_hw_reg muld_prty1_bb_a0 = { | |
8998 | 0, 10, muld_prty1_bb_a0_attn_idx, 0x4e0200, 0x4e020c, 0x4e0208, | |
8999 | 0x4e0204 | |
9000 | }; | |
9001 | ||
9002 | static struct attn_hw_reg *muld_prty_bb_a0_regs[1] = { | |
9003 | &muld_prty1_bb_a0, | |
9004 | }; | |
9005 | ||
9006 | static const u16 muld_prty1_bb_b0_attn_idx[10] = { | |
9007 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, | |
9008 | }; | |
9009 | ||
9010 | static struct attn_hw_reg muld_prty1_bb_b0 = { | |
9011 | 0, 10, muld_prty1_bb_b0_attn_idx, 0x4e0200, 0x4e020c, 0x4e0208, | |
9012 | 0x4e0204 | |
9013 | }; | |
9014 | ||
9015 | static struct attn_hw_reg *muld_prty_bb_b0_regs[1] = { | |
9016 | &muld_prty1_bb_b0, | |
9017 | }; | |
9018 | ||
9019 | static const u16 muld_prty1_k2_attn_idx[10] = { | |
9020 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, | |
9021 | }; | |
9022 | ||
9023 | static struct attn_hw_reg muld_prty1_k2 = { | |
9024 | 0, 10, muld_prty1_k2_attn_idx, 0x4e0200, 0x4e020c, 0x4e0208, 0x4e0204 | |
9025 | }; | |
9026 | ||
9027 | static struct attn_hw_reg *muld_prty_k2_regs[1] = { | |
9028 | &muld_prty1_k2, | |
9029 | }; | |
9030 | ||
9031 | #ifdef ATTN_DESC | |
9032 | static const char *yuld_int_attn_desc[6] = { | |
9033 | "yuld_address_error", | |
9034 | "yuld_ld_hdr_err", | |
9035 | "yuld_ld_seg_msg_err", | |
9036 | "yuld_ld_tid_mini_cache_err", | |
9037 | "yuld_ld_cid_mini_cache_err", | |
9038 | "yuld_ld_long_message", | |
9039 | }; | |
9040 | #else | |
9041 | #define yuld_int_attn_desc OSAL_NULL | |
9042 | #endif | |
9043 | ||
9044 | static const u16 yuld_int0_bb_a0_attn_idx[6] = { | |
9045 | 0, 1, 2, 3, 4, 5, | |
9046 | }; | |
9047 | ||
9048 | static struct attn_hw_reg yuld_int0_bb_a0 = { | |
9049 | 0, 6, yuld_int0_bb_a0_attn_idx, 0x4c8180, 0x4c818c, 0x4c8188, 0x4c8184 | |
9050 | }; | |
9051 | ||
9052 | static struct attn_hw_reg *yuld_int_bb_a0_regs[1] = { | |
9053 | &yuld_int0_bb_a0, | |
9054 | }; | |
9055 | ||
9056 | static const u16 yuld_int0_bb_b0_attn_idx[6] = { | |
9057 | 0, 1, 2, 3, 4, 5, | |
9058 | }; | |
9059 | ||
9060 | static struct attn_hw_reg yuld_int0_bb_b0 = { | |
9061 | 0, 6, yuld_int0_bb_b0_attn_idx, 0x4c8180, 0x4c818c, 0x4c8188, 0x4c8184 | |
9062 | }; | |
9063 | ||
9064 | static struct attn_hw_reg *yuld_int_bb_b0_regs[1] = { | |
9065 | &yuld_int0_bb_b0, | |
9066 | }; | |
9067 | ||
9068 | static const u16 yuld_int0_k2_attn_idx[6] = { | |
9069 | 0, 1, 2, 3, 4, 5, | |
9070 | }; | |
9071 | ||
9072 | static struct attn_hw_reg yuld_int0_k2 = { | |
9073 | 0, 6, yuld_int0_k2_attn_idx, 0x4c8180, 0x4c818c, 0x4c8188, 0x4c8184 | |
9074 | }; | |
9075 | ||
9076 | static struct attn_hw_reg *yuld_int_k2_regs[1] = { | |
9077 | &yuld_int0_k2, | |
9078 | }; | |
9079 | ||
9080 | #ifdef ATTN_DESC | |
9081 | static const char *yuld_prty_attn_desc[6] = { | |
9082 | "yuld_mem001_i_mem_prty", | |
9083 | "yuld_mem002_i_mem_prty", | |
9084 | "yuld_mem005_i_mem_prty", | |
9085 | "yuld_mem006_i_mem_prty", | |
9086 | "yuld_mem004_i_mem_prty", | |
9087 | "yuld_mem003_i_mem_prty", | |
9088 | }; | |
9089 | #else | |
9090 | #define yuld_prty_attn_desc OSAL_NULL | |
9091 | #endif | |
9092 | ||
9093 | static const u16 yuld_prty1_bb_a0_attn_idx[6] = { | |
9094 | 0, 1, 2, 3, 4, 5, | |
9095 | }; | |
9096 | ||
9097 | static struct attn_hw_reg yuld_prty1_bb_a0 = { | |
9098 | 0, 6, yuld_prty1_bb_a0_attn_idx, 0x4c8200, 0x4c820c, 0x4c8208, 0x4c8204 | |
9099 | }; | |
9100 | ||
9101 | static struct attn_hw_reg *yuld_prty_bb_a0_regs[1] = { | |
9102 | &yuld_prty1_bb_a0, | |
9103 | }; | |
9104 | ||
9105 | static const u16 yuld_prty1_bb_b0_attn_idx[6] = { | |
9106 | 0, 1, 2, 3, 4, 5, | |
9107 | }; | |
9108 | ||
9109 | static struct attn_hw_reg yuld_prty1_bb_b0 = { | |
9110 | 0, 6, yuld_prty1_bb_b0_attn_idx, 0x4c8200, 0x4c820c, 0x4c8208, 0x4c8204 | |
9111 | }; | |
9112 | ||
9113 | static struct attn_hw_reg *yuld_prty_bb_b0_regs[1] = { | |
9114 | &yuld_prty1_bb_b0, | |
9115 | }; | |
9116 | ||
9117 | static const u16 yuld_prty1_k2_attn_idx[6] = { | |
9118 | 0, 1, 2, 3, 4, 5, | |
9119 | }; | |
9120 | ||
9121 | static struct attn_hw_reg yuld_prty1_k2 = { | |
9122 | 0, 6, yuld_prty1_k2_attn_idx, 0x4c8200, 0x4c820c, 0x4c8208, 0x4c8204 | |
9123 | }; | |
9124 | ||
9125 | static struct attn_hw_reg *yuld_prty_k2_regs[1] = { | |
9126 | &yuld_prty1_k2, | |
9127 | }; | |
9128 | ||
9129 | #ifdef ATTN_DESC | |
9130 | static const char *xyld_int_attn_desc[6] = { | |
9131 | "xyld_address_error", | |
9132 | "xyld_ld_hdr_err", | |
9133 | "xyld_ld_seg_msg_err", | |
9134 | "xyld_ld_tid_mini_cache_err", | |
9135 | "xyld_ld_cid_mini_cache_err", | |
9136 | "xyld_ld_long_message", | |
9137 | }; | |
9138 | #else | |
9139 | #define xyld_int_attn_desc OSAL_NULL | |
9140 | #endif | |
9141 | ||
9142 | static const u16 xyld_int0_bb_a0_attn_idx[6] = { | |
9143 | 0, 1, 2, 3, 4, 5, | |
9144 | }; | |
9145 | ||
9146 | static struct attn_hw_reg xyld_int0_bb_a0 = { | |
9147 | 0, 6, xyld_int0_bb_a0_attn_idx, 0x4c0180, 0x4c018c, 0x4c0188, 0x4c0184 | |
9148 | }; | |
9149 | ||
9150 | static struct attn_hw_reg *xyld_int_bb_a0_regs[1] = { | |
9151 | &xyld_int0_bb_a0, | |
9152 | }; | |
9153 | ||
9154 | static const u16 xyld_int0_bb_b0_attn_idx[6] = { | |
9155 | 0, 1, 2, 3, 4, 5, | |
9156 | }; | |
9157 | ||
9158 | static struct attn_hw_reg xyld_int0_bb_b0 = { | |
9159 | 0, 6, xyld_int0_bb_b0_attn_idx, 0x4c0180, 0x4c018c, 0x4c0188, 0x4c0184 | |
9160 | }; | |
9161 | ||
9162 | static struct attn_hw_reg *xyld_int_bb_b0_regs[1] = { | |
9163 | &xyld_int0_bb_b0, | |
9164 | }; | |
9165 | ||
9166 | static const u16 xyld_int0_k2_attn_idx[6] = { | |
9167 | 0, 1, 2, 3, 4, 5, | |
9168 | }; | |
9169 | ||
9170 | static struct attn_hw_reg xyld_int0_k2 = { | |
9171 | 0, 6, xyld_int0_k2_attn_idx, 0x4c0180, 0x4c018c, 0x4c0188, 0x4c0184 | |
9172 | }; | |
9173 | ||
9174 | static struct attn_hw_reg *xyld_int_k2_regs[1] = { | |
9175 | &xyld_int0_k2, | |
9176 | }; | |
9177 | ||
9178 | #ifdef ATTN_DESC | |
9179 | static const char *xyld_prty_attn_desc[9] = { | |
9180 | "xyld_mem004_i_ecc_rf_int", | |
9181 | "xyld_mem006_i_ecc_rf_int", | |
9182 | "xyld_mem001_i_mem_prty", | |
9183 | "xyld_mem002_i_mem_prty", | |
9184 | "xyld_mem008_i_mem_prty", | |
9185 | "xyld_mem009_i_mem_prty", | |
9186 | "xyld_mem003_i_mem_prty", | |
9187 | "xyld_mem005_i_mem_prty", | |
9188 | "xyld_mem007_i_mem_prty", | |
9189 | }; | |
9190 | #else | |
9191 | #define xyld_prty_attn_desc OSAL_NULL | |
9192 | #endif | |
9193 | ||
9194 | static const u16 xyld_prty1_bb_a0_attn_idx[9] = { | |
9195 | 0, 1, 2, 3, 4, 5, 6, 7, 8, | |
9196 | }; | |
9197 | ||
9198 | static struct attn_hw_reg xyld_prty1_bb_a0 = { | |
9199 | 0, 9, xyld_prty1_bb_a0_attn_idx, 0x4c0200, 0x4c020c, 0x4c0208, 0x4c0204 | |
9200 | }; | |
9201 | ||
9202 | static struct attn_hw_reg *xyld_prty_bb_a0_regs[1] = { | |
9203 | &xyld_prty1_bb_a0, | |
9204 | }; | |
9205 | ||
9206 | static const u16 xyld_prty1_bb_b0_attn_idx[9] = { | |
9207 | 0, 1, 2, 3, 4, 5, 6, 7, 8, | |
9208 | }; | |
9209 | ||
9210 | static struct attn_hw_reg xyld_prty1_bb_b0 = { | |
9211 | 0, 9, xyld_prty1_bb_b0_attn_idx, 0x4c0200, 0x4c020c, 0x4c0208, 0x4c0204 | |
9212 | }; | |
9213 | ||
9214 | static struct attn_hw_reg *xyld_prty_bb_b0_regs[1] = { | |
9215 | &xyld_prty1_bb_b0, | |
9216 | }; | |
9217 | ||
9218 | static const u16 xyld_prty1_k2_attn_idx[9] = { | |
9219 | 0, 1, 2, 3, 4, 5, 6, 7, 8, | |
9220 | }; | |
9221 | ||
9222 | static struct attn_hw_reg xyld_prty1_k2 = { | |
9223 | 0, 9, xyld_prty1_k2_attn_idx, 0x4c0200, 0x4c020c, 0x4c0208, 0x4c0204 | |
9224 | }; | |
9225 | ||
9226 | static struct attn_hw_reg *xyld_prty_k2_regs[1] = { | |
9227 | &xyld_prty1_k2, | |
9228 | }; | |
9229 | ||
9230 | #ifdef ATTN_DESC | |
9231 | static const char *prm_int_attn_desc[11] = { | |
9232 | "prm_address_error", | |
9233 | "prm_ififo_error", | |
9234 | "prm_immed_fifo_error", | |
9235 | "prm_ofst_pend_error", | |
9236 | "prm_pad_pend_error", | |
9237 | "prm_pbinp_pend_error", | |
9238 | "prm_tag_pend_error", | |
9239 | "prm_mstorm_eop_err", | |
9240 | "prm_ustorm_eop_err", | |
9241 | "prm_mstorm_que_err", | |
9242 | "prm_ustorm_que_err", | |
9243 | }; | |
9244 | #else | |
9245 | #define prm_int_attn_desc OSAL_NULL | |
9246 | #endif | |
9247 | ||
9248 | static const u16 prm_int0_bb_a0_attn_idx[11] = { | |
9249 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, | |
9250 | }; | |
9251 | ||
9252 | static struct attn_hw_reg prm_int0_bb_a0 = { | |
9253 | 0, 11, prm_int0_bb_a0_attn_idx, 0x230040, 0x23004c, 0x230048, 0x230044 | |
9254 | }; | |
9255 | ||
9256 | static struct attn_hw_reg *prm_int_bb_a0_regs[1] = { | |
9257 | &prm_int0_bb_a0, | |
9258 | }; | |
9259 | ||
9260 | static const u16 prm_int0_bb_b0_attn_idx[11] = { | |
9261 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, | |
9262 | }; | |
9263 | ||
9264 | static struct attn_hw_reg prm_int0_bb_b0 = { | |
9265 | 0, 11, prm_int0_bb_b0_attn_idx, 0x230040, 0x23004c, 0x230048, 0x230044 | |
9266 | }; | |
9267 | ||
9268 | static struct attn_hw_reg *prm_int_bb_b0_regs[1] = { | |
9269 | &prm_int0_bb_b0, | |
9270 | }; | |
9271 | ||
9272 | static const u16 prm_int0_k2_attn_idx[11] = { | |
9273 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, | |
9274 | }; | |
9275 | ||
9276 | static struct attn_hw_reg prm_int0_k2 = { | |
9277 | 0, 11, prm_int0_k2_attn_idx, 0x230040, 0x23004c, 0x230048, 0x230044 | |
9278 | }; | |
9279 | ||
9280 | static struct attn_hw_reg *prm_int_k2_regs[1] = { | |
9281 | &prm_int0_k2, | |
9282 | }; | |
9283 | ||
9284 | #ifdef ATTN_DESC | |
9285 | static const char *prm_prty_attn_desc[30] = { | |
9286 | "prm_datapath_registers", | |
9287 | "prm_mem012_i_ecc_rf_int", | |
9288 | "prm_mem013_i_ecc_rf_int", | |
9289 | "prm_mem014_i_ecc_rf_int", | |
9290 | "prm_mem020_i_ecc_rf_int", | |
9291 | "prm_mem004_i_mem_prty", | |
9292 | "prm_mem024_i_mem_prty", | |
9293 | "prm_mem016_i_mem_prty", | |
9294 | "prm_mem017_i_mem_prty", | |
9295 | "prm_mem008_i_mem_prty", | |
9296 | "prm_mem009_i_mem_prty", | |
9297 | "prm_mem010_i_mem_prty", | |
9298 | "prm_mem015_i_mem_prty", | |
9299 | "prm_mem011_i_mem_prty", | |
9300 | "prm_mem003_i_mem_prty", | |
9301 | "prm_mem002_i_mem_prty", | |
9302 | "prm_mem005_i_mem_prty", | |
9303 | "prm_mem023_i_mem_prty", | |
9304 | "prm_mem006_i_mem_prty", | |
9305 | "prm_mem007_i_mem_prty", | |
9306 | "prm_mem001_i_mem_prty", | |
9307 | "prm_mem022_i_mem_prty", | |
9308 | "prm_mem021_i_mem_prty", | |
9309 | "prm_mem019_i_mem_prty", | |
9310 | "prm_mem015_i_ecc_rf_int", | |
9311 | "prm_mem021_i_ecc_rf_int", | |
9312 | "prm_mem025_i_mem_prty", | |
9313 | "prm_mem018_i_mem_prty", | |
9314 | "prm_mem012_i_mem_prty", | |
9315 | "prm_mem020_i_mem_prty", | |
9316 | }; | |
9317 | #else | |
9318 | #define prm_prty_attn_desc OSAL_NULL | |
9319 | #endif | |
9320 | ||
9321 | static const u16 prm_prty1_bb_a0_attn_idx[25] = { | |
9322 | 2, 3, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 23, 24, | |
9323 | 25, 26, 27, 28, 29, | |
9324 | }; | |
9325 | ||
9326 | static struct attn_hw_reg prm_prty1_bb_a0 = { | |
9327 | 0, 25, prm_prty1_bb_a0_attn_idx, 0x230200, 0x23020c, 0x230208, 0x230204 | |
9328 | }; | |
9329 | ||
9330 | static struct attn_hw_reg *prm_prty_bb_a0_regs[1] = { | |
9331 | &prm_prty1_bb_a0, | |
9332 | }; | |
9333 | ||
9334 | static const u16 prm_prty0_bb_b0_attn_idx[1] = { | |
9335 | 0, | |
9336 | }; | |
9337 | ||
9338 | static struct attn_hw_reg prm_prty0_bb_b0 = { | |
9339 | 0, 1, prm_prty0_bb_b0_attn_idx, 0x230050, 0x23005c, 0x230058, 0x230054 | |
9340 | }; | |
9341 | ||
9342 | static const u16 prm_prty1_bb_b0_attn_idx[24] = { | |
9343 | 2, 3, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 24, 25, | |
9344 | 26, 27, 28, 29, | |
9345 | }; | |
9346 | ||
9347 | static struct attn_hw_reg prm_prty1_bb_b0 = { | |
9348 | 1, 24, prm_prty1_bb_b0_attn_idx, 0x230200, 0x23020c, 0x230208, 0x230204 | |
9349 | }; | |
9350 | ||
9351 | static struct attn_hw_reg *prm_prty_bb_b0_regs[2] = { | |
9352 | &prm_prty0_bb_b0, &prm_prty1_bb_b0, | |
9353 | }; | |
9354 | ||
9355 | static const u16 prm_prty0_k2_attn_idx[1] = { | |
9356 | 0, | |
9357 | }; | |
9358 | ||
9359 | static struct attn_hw_reg prm_prty0_k2 = { | |
9360 | 0, 1, prm_prty0_k2_attn_idx, 0x230050, 0x23005c, 0x230058, 0x230054 | |
9361 | }; | |
9362 | ||
9363 | static const u16 prm_prty1_k2_attn_idx[23] = { | |
9364 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, | |
9365 | 21, | |
9366 | 22, 23, | |
9367 | }; | |
9368 | ||
9369 | static struct attn_hw_reg prm_prty1_k2 = { | |
9370 | 1, 23, prm_prty1_k2_attn_idx, 0x230200, 0x23020c, 0x230208, 0x230204 | |
9371 | }; | |
9372 | ||
9373 | static struct attn_hw_reg *prm_prty_k2_regs[2] = { | |
9374 | &prm_prty0_k2, &prm_prty1_k2, | |
9375 | }; | |
9376 | ||
9377 | #ifdef ATTN_DESC | |
9378 | static const char *pbf_pb1_int_attn_desc[9] = { | |
9379 | "pbf_pb1_address_error", | |
9380 | "pbf_pb1_eop_error", | |
9381 | "pbf_pb1_ififo_error", | |
9382 | "pbf_pb1_pfifo_error", | |
9383 | "pbf_pb1_db_buf_error", | |
9384 | "pbf_pb1_th_exec_error", | |
9385 | "pbf_pb1_tq_error_wr", | |
9386 | "pbf_pb1_tq_error_rd_th", | |
9387 | "pbf_pb1_tq_error_rd_ih", | |
9388 | }; | |
9389 | #else | |
9390 | #define pbf_pb1_int_attn_desc OSAL_NULL | |
9391 | #endif | |
9392 | ||
9393 | static const u16 pbf_pb1_int0_bb_a0_attn_idx[9] = { | |
9394 | 0, 1, 2, 3, 4, 5, 6, 7, 8, | |
9395 | }; | |
9396 | ||
9397 | static struct attn_hw_reg pbf_pb1_int0_bb_a0 = { | |
9398 | 0, 9, pbf_pb1_int0_bb_a0_attn_idx, 0xda0040, 0xda004c, 0xda0048, | |
9399 | 0xda0044 | |
9400 | }; | |
9401 | ||
9402 | static struct attn_hw_reg *pbf_pb1_int_bb_a0_regs[1] = { | |
9403 | &pbf_pb1_int0_bb_a0, | |
9404 | }; | |
9405 | ||
9406 | static const u16 pbf_pb1_int0_bb_b0_attn_idx[9] = { | |
9407 | 0, 1, 2, 3, 4, 5, 6, 7, 8, | |
9408 | }; | |
9409 | ||
9410 | static struct attn_hw_reg pbf_pb1_int0_bb_b0 = { | |
9411 | 0, 9, pbf_pb1_int0_bb_b0_attn_idx, 0xda0040, 0xda004c, 0xda0048, | |
9412 | 0xda0044 | |
9413 | }; | |
9414 | ||
9415 | static struct attn_hw_reg *pbf_pb1_int_bb_b0_regs[1] = { | |
9416 | &pbf_pb1_int0_bb_b0, | |
9417 | }; | |
9418 | ||
9419 | static const u16 pbf_pb1_int0_k2_attn_idx[9] = { | |
9420 | 0, 1, 2, 3, 4, 5, 6, 7, 8, | |
9421 | }; | |
9422 | ||
9423 | static struct attn_hw_reg pbf_pb1_int0_k2 = { | |
9424 | 0, 9, pbf_pb1_int0_k2_attn_idx, 0xda0040, 0xda004c, 0xda0048, 0xda0044 | |
9425 | }; | |
9426 | ||
9427 | static struct attn_hw_reg *pbf_pb1_int_k2_regs[1] = { | |
9428 | &pbf_pb1_int0_k2, | |
9429 | }; | |
9430 | ||
9431 | #ifdef ATTN_DESC | |
9432 | static const char *pbf_pb1_prty_attn_desc[1] = { | |
9433 | "pbf_pb1_datapath_registers", | |
9434 | }; | |
9435 | #else | |
9436 | #define pbf_pb1_prty_attn_desc OSAL_NULL | |
9437 | #endif | |
9438 | ||
9439 | static const u16 pbf_pb1_prty0_bb_b0_attn_idx[1] = { | |
9440 | 0, | |
9441 | }; | |
9442 | ||
9443 | static struct attn_hw_reg pbf_pb1_prty0_bb_b0 = { | |
9444 | 0, 1, pbf_pb1_prty0_bb_b0_attn_idx, 0xda0050, 0xda005c, 0xda0058, | |
9445 | 0xda0054 | |
9446 | }; | |
9447 | ||
9448 | static struct attn_hw_reg *pbf_pb1_prty_bb_b0_regs[1] = { | |
9449 | &pbf_pb1_prty0_bb_b0, | |
9450 | }; | |
9451 | ||
9452 | static const u16 pbf_pb1_prty0_k2_attn_idx[1] = { | |
9453 | 0, | |
9454 | }; | |
9455 | ||
9456 | static struct attn_hw_reg pbf_pb1_prty0_k2 = { | |
9457 | 0, 1, pbf_pb1_prty0_k2_attn_idx, 0xda0050, 0xda005c, 0xda0058, 0xda0054 | |
9458 | }; | |
9459 | ||
9460 | static struct attn_hw_reg *pbf_pb1_prty_k2_regs[1] = { | |
9461 | &pbf_pb1_prty0_k2, | |
9462 | }; | |
9463 | ||
9464 | #ifdef ATTN_DESC | |
9465 | static const char *pbf_pb2_int_attn_desc[9] = { | |
9466 | "pbf_pb2_address_error", | |
9467 | "pbf_pb2_eop_error", | |
9468 | "pbf_pb2_ififo_error", | |
9469 | "pbf_pb2_pfifo_error", | |
9470 | "pbf_pb2_db_buf_error", | |
9471 | "pbf_pb2_th_exec_error", | |
9472 | "pbf_pb2_tq_error_wr", | |
9473 | "pbf_pb2_tq_error_rd_th", | |
9474 | "pbf_pb2_tq_error_rd_ih", | |
9475 | }; | |
9476 | #else | |
9477 | #define pbf_pb2_int_attn_desc OSAL_NULL | |
9478 | #endif | |
9479 | ||
9480 | static const u16 pbf_pb2_int0_bb_a0_attn_idx[9] = { | |
9481 | 0, 1, 2, 3, 4, 5, 6, 7, 8, | |
9482 | }; | |
9483 | ||
9484 | static struct attn_hw_reg pbf_pb2_int0_bb_a0 = { | |
9485 | 0, 9, pbf_pb2_int0_bb_a0_attn_idx, 0xda4040, 0xda404c, 0xda4048, | |
9486 | 0xda4044 | |
9487 | }; | |
9488 | ||
9489 | static struct attn_hw_reg *pbf_pb2_int_bb_a0_regs[1] = { | |
9490 | &pbf_pb2_int0_bb_a0, | |
9491 | }; | |
9492 | ||
9493 | static const u16 pbf_pb2_int0_bb_b0_attn_idx[9] = { | |
9494 | 0, 1, 2, 3, 4, 5, 6, 7, 8, | |
9495 | }; | |
9496 | ||
9497 | static struct attn_hw_reg pbf_pb2_int0_bb_b0 = { | |
9498 | 0, 9, pbf_pb2_int0_bb_b0_attn_idx, 0xda4040, 0xda404c, 0xda4048, | |
9499 | 0xda4044 | |
9500 | }; | |
9501 | ||
9502 | static struct attn_hw_reg *pbf_pb2_int_bb_b0_regs[1] = { | |
9503 | &pbf_pb2_int0_bb_b0, | |
9504 | }; | |
9505 | ||
9506 | static const u16 pbf_pb2_int0_k2_attn_idx[9] = { | |
9507 | 0, 1, 2, 3, 4, 5, 6, 7, 8, | |
9508 | }; | |
9509 | ||
9510 | static struct attn_hw_reg pbf_pb2_int0_k2 = { | |
9511 | 0, 9, pbf_pb2_int0_k2_attn_idx, 0xda4040, 0xda404c, 0xda4048, 0xda4044 | |
9512 | }; | |
9513 | ||
9514 | static struct attn_hw_reg *pbf_pb2_int_k2_regs[1] = { | |
9515 | &pbf_pb2_int0_k2, | |
9516 | }; | |
9517 | ||
9518 | #ifdef ATTN_DESC | |
9519 | static const char *pbf_pb2_prty_attn_desc[1] = { | |
9520 | "pbf_pb2_datapath_registers", | |
9521 | }; | |
9522 | #else | |
9523 | #define pbf_pb2_prty_attn_desc OSAL_NULL | |
9524 | #endif | |
9525 | ||
9526 | static const u16 pbf_pb2_prty0_bb_b0_attn_idx[1] = { | |
9527 | 0, | |
9528 | }; | |
9529 | ||
9530 | static struct attn_hw_reg pbf_pb2_prty0_bb_b0 = { | |
9531 | 0, 1, pbf_pb2_prty0_bb_b0_attn_idx, 0xda4050, 0xda405c, 0xda4058, | |
9532 | 0xda4054 | |
9533 | }; | |
9534 | ||
9535 | static struct attn_hw_reg *pbf_pb2_prty_bb_b0_regs[1] = { | |
9536 | &pbf_pb2_prty0_bb_b0, | |
9537 | }; | |
9538 | ||
9539 | static const u16 pbf_pb2_prty0_k2_attn_idx[1] = { | |
9540 | 0, | |
9541 | }; | |
9542 | ||
9543 | static struct attn_hw_reg pbf_pb2_prty0_k2 = { | |
9544 | 0, 1, pbf_pb2_prty0_k2_attn_idx, 0xda4050, 0xda405c, 0xda4058, 0xda4054 | |
9545 | }; | |
9546 | ||
9547 | static struct attn_hw_reg *pbf_pb2_prty_k2_regs[1] = { | |
9548 | &pbf_pb2_prty0_k2, | |
9549 | }; | |
9550 | ||
9551 | #ifdef ATTN_DESC | |
9552 | static const char *rpb_int_attn_desc[9] = { | |
9553 | "rpb_address_error", | |
9554 | "rpb_eop_error", | |
9555 | "rpb_ififo_error", | |
9556 | "rpb_pfifo_error", | |
9557 | "rpb_db_buf_error", | |
9558 | "rpb_th_exec_error", | |
9559 | "rpb_tq_error_wr", | |
9560 | "rpb_tq_error_rd_th", | |
9561 | "rpb_tq_error_rd_ih", | |
9562 | }; | |
9563 | #else | |
9564 | #define rpb_int_attn_desc OSAL_NULL | |
9565 | #endif | |
9566 | ||
9567 | static const u16 rpb_int0_bb_a0_attn_idx[9] = { | |
9568 | 0, 1, 2, 3, 4, 5, 6, 7, 8, | |
9569 | }; | |
9570 | ||
9571 | static struct attn_hw_reg rpb_int0_bb_a0 = { | |
9572 | 0, 9, rpb_int0_bb_a0_attn_idx, 0x23c040, 0x23c04c, 0x23c048, 0x23c044 | |
9573 | }; | |
9574 | ||
9575 | static struct attn_hw_reg *rpb_int_bb_a0_regs[1] = { | |
9576 | &rpb_int0_bb_a0, | |
9577 | }; | |
9578 | ||
9579 | static const u16 rpb_int0_bb_b0_attn_idx[9] = { | |
9580 | 0, 1, 2, 3, 4, 5, 6, 7, 8, | |
9581 | }; | |
9582 | ||
9583 | static struct attn_hw_reg rpb_int0_bb_b0 = { | |
9584 | 0, 9, rpb_int0_bb_b0_attn_idx, 0x23c040, 0x23c04c, 0x23c048, 0x23c044 | |
9585 | }; | |
9586 | ||
9587 | static struct attn_hw_reg *rpb_int_bb_b0_regs[1] = { | |
9588 | &rpb_int0_bb_b0, | |
9589 | }; | |
9590 | ||
9591 | static const u16 rpb_int0_k2_attn_idx[9] = { | |
9592 | 0, 1, 2, 3, 4, 5, 6, 7, 8, | |
9593 | }; | |
9594 | ||
9595 | static struct attn_hw_reg rpb_int0_k2 = { | |
9596 | 0, 9, rpb_int0_k2_attn_idx, 0x23c040, 0x23c04c, 0x23c048, 0x23c044 | |
9597 | }; | |
9598 | ||
9599 | static struct attn_hw_reg *rpb_int_k2_regs[1] = { | |
9600 | &rpb_int0_k2, | |
9601 | }; | |
9602 | ||
9603 | #ifdef ATTN_DESC | |
9604 | static const char *rpb_prty_attn_desc[1] = { | |
9605 | "rpb_datapath_registers", | |
9606 | }; | |
9607 | #else | |
9608 | #define rpb_prty_attn_desc OSAL_NULL | |
9609 | #endif | |
9610 | ||
9611 | static const u16 rpb_prty0_bb_b0_attn_idx[1] = { | |
9612 | 0, | |
9613 | }; | |
9614 | ||
9615 | static struct attn_hw_reg rpb_prty0_bb_b0 = { | |
9616 | 0, 1, rpb_prty0_bb_b0_attn_idx, 0x23c050, 0x23c05c, 0x23c058, 0x23c054 | |
9617 | }; | |
9618 | ||
9619 | static struct attn_hw_reg *rpb_prty_bb_b0_regs[1] = { | |
9620 | &rpb_prty0_bb_b0, | |
9621 | }; | |
9622 | ||
9623 | static const u16 rpb_prty0_k2_attn_idx[1] = { | |
9624 | 0, | |
9625 | }; | |
9626 | ||
9627 | static struct attn_hw_reg rpb_prty0_k2 = { | |
9628 | 0, 1, rpb_prty0_k2_attn_idx, 0x23c050, 0x23c05c, 0x23c058, 0x23c054 | |
9629 | }; | |
9630 | ||
9631 | static struct attn_hw_reg *rpb_prty_k2_regs[1] = { | |
9632 | &rpb_prty0_k2, | |
9633 | }; | |
9634 | ||
9635 | #ifdef ATTN_DESC | |
9636 | static const char *btb_int_attn_desc[139] = { | |
9637 | "btb_address_error", | |
9638 | "btb_rc_pkt0_rls_error", | |
9639 | "btb_unused_0", | |
9640 | "btb_rc_pkt0_len_error", | |
9641 | "btb_unused_1", | |
9642 | "btb_rc_pkt0_protocol_error", | |
9643 | "btb_rc_pkt1_rls_error", | |
9644 | "btb_unused_2", | |
9645 | "btb_rc_pkt1_len_error", | |
9646 | "btb_unused_3", | |
9647 | "btb_rc_pkt1_protocol_error", | |
9648 | "btb_rc_pkt2_rls_error", | |
9649 | "btb_unused_4", | |
9650 | "btb_rc_pkt2_len_error", | |
9651 | "btb_unused_5", | |
9652 | "btb_rc_pkt2_protocol_error", | |
9653 | "btb_rc_pkt3_rls_error", | |
9654 | "btb_unused_6", | |
9655 | "btb_rc_pkt3_len_error", | |
9656 | "btb_unused_7", | |
9657 | "btb_rc_pkt3_protocol_error", | |
9658 | "btb_rc_sop_req_tc_port_error", | |
9659 | "btb_unused_8", | |
9660 | "btb_wc0_protocol_error", | |
9661 | "btb_unused_9", | |
9662 | "btb_ll_blk_error", | |
9663 | "btb_ll_arb_calc_error", | |
9664 | "btb_fc_alm_calc_error", | |
9665 | "btb_wc0_inp_fifo_error", | |
9666 | "btb_wc0_sop_fifo_error", | |
9667 | "btb_wc0_len_fifo_error", | |
9668 | "btb_wc0_eop_fifo_error", | |
9669 | "btb_wc0_queue_fifo_error", | |
9670 | "btb_wc0_free_point_fifo_error", | |
9671 | "btb_wc0_next_point_fifo_error", | |
9672 | "btb_wc0_strt_fifo_error", | |
9673 | "btb_wc0_second_dscr_fifo_error", | |
9674 | "btb_wc0_pkt_avail_fifo_error", | |
9675 | "btb_wc0_notify_fifo_error", | |
9676 | "btb_wc0_ll_req_fifo_error", | |
9677 | "btb_wc0_ll_pa_cnt_error", | |
9678 | "btb_wc0_bb_pa_cnt_error", | |
9679 | "btb_wc_dup_upd_data_fifo_error", | |
9680 | "btb_wc_dup_rsp_dscr_fifo_error", | |
9681 | "btb_wc_dup_upd_point_fifo_error", | |
9682 | "btb_wc_dup_pkt_avail_fifo_error", | |
9683 | "btb_wc_dup_pkt_avail_cnt_error", | |
9684 | "btb_rc_pkt0_side_fifo_error", | |
9685 | "btb_rc_pkt0_req_fifo_error", | |
9686 | "btb_rc_pkt0_blk_fifo_error", | |
9687 | "btb_rc_pkt0_rls_left_fifo_error", | |
9688 | "btb_rc_pkt0_strt_ptr_fifo_error", | |
9689 | "btb_rc_pkt0_second_ptr_fifo_error", | |
9690 | "btb_rc_pkt0_rsp_fifo_error", | |
9691 | "btb_rc_pkt0_dscr_fifo_error", | |
9692 | "btb_rc_pkt1_side_fifo_error", | |
9693 | "btb_rc_pkt1_req_fifo_error", | |
9694 | "btb_rc_pkt1_blk_fifo_error", | |
9695 | "btb_rc_pkt1_rls_left_fifo_error", | |
9696 | "btb_rc_pkt1_strt_ptr_fifo_error", | |
9697 | "btb_rc_pkt1_second_ptr_fifo_error", | |
9698 | "btb_rc_pkt1_rsp_fifo_error", | |
9699 | "btb_rc_pkt1_dscr_fifo_error", | |
9700 | "btb_rc_pkt2_side_fifo_error", | |
9701 | "btb_rc_pkt2_req_fifo_error", | |
9702 | "btb_rc_pkt2_blk_fifo_error", | |
9703 | "btb_rc_pkt2_rls_left_fifo_error", | |
9704 | "btb_rc_pkt2_strt_ptr_fifo_error", | |
9705 | "btb_rc_pkt2_second_ptr_fifo_error", | |
9706 | "btb_rc_pkt2_rsp_fifo_error", | |
9707 | "btb_rc_pkt2_dscr_fifo_error", | |
9708 | "btb_rc_pkt3_side_fifo_error", | |
9709 | "btb_rc_pkt3_req_fifo_error", | |
9710 | "btb_rc_pkt3_blk_fifo_error", | |
9711 | "btb_rc_pkt3_rls_left_fifo_error", | |
9712 | "btb_rc_pkt3_strt_ptr_fifo_error", | |
9713 | "btb_rc_pkt3_second_ptr_fifo_error", | |
9714 | "btb_rc_pkt3_rsp_fifo_error", | |
9715 | "btb_rc_pkt3_dscr_fifo_error", | |
9716 | "btb_rc_sop_queue_fifo_error", | |
9717 | "btb_ll_arb_rls_fifo_error", | |
9718 | "btb_ll_arb_prefetch_fifo_error", | |
9719 | "btb_rc_pkt0_rls_fifo_error", | |
9720 | "btb_rc_pkt1_rls_fifo_error", | |
9721 | "btb_rc_pkt2_rls_fifo_error", | |
9722 | "btb_rc_pkt3_rls_fifo_error", | |
9723 | "btb_rc_pkt4_rls_fifo_error", | |
9724 | "btb_rc_pkt5_rls_fifo_error", | |
9725 | "btb_rc_pkt6_rls_fifo_error", | |
9726 | "btb_rc_pkt7_rls_fifo_error", | |
9727 | "btb_rc_pkt4_rls_error", | |
9728 | "btb_rc_pkt4_len_error", | |
9729 | "btb_rc_pkt4_protocol_error", | |
9730 | "btb_rc_pkt4_side_fifo_error", | |
9731 | "btb_rc_pkt4_req_fifo_error", | |
9732 | "btb_rc_pkt4_blk_fifo_error", | |
9733 | "btb_rc_pkt4_rls_left_fifo_error", | |
9734 | "btb_rc_pkt4_strt_ptr_fifo_error", | |
9735 | "btb_rc_pkt4_second_ptr_fifo_error", | |
9736 | "btb_rc_pkt4_rsp_fifo_error", | |
9737 | "btb_rc_pkt4_dscr_fifo_error", | |
9738 | "btb_rc_pkt5_rls_error", | |
9739 | "btb_rc_pkt5_len_error", | |
9740 | "btb_rc_pkt5_protocol_error", | |
9741 | "btb_rc_pkt5_side_fifo_error", | |
9742 | "btb_rc_pkt5_req_fifo_error", | |
9743 | "btb_rc_pkt5_blk_fifo_error", | |
9744 | "btb_rc_pkt5_rls_left_fifo_error", | |
9745 | "btb_rc_pkt5_strt_ptr_fifo_error", | |
9746 | "btb_rc_pkt5_second_ptr_fifo_error", | |
9747 | "btb_rc_pkt5_rsp_fifo_error", | |
9748 | "btb_rc_pkt5_dscr_fifo_error", | |
9749 | "btb_rc_pkt6_rls_error", | |
9750 | "btb_rc_pkt6_len_error", | |
9751 | "btb_rc_pkt6_protocol_error", | |
9752 | "btb_rc_pkt6_side_fifo_error", | |
9753 | "btb_rc_pkt6_req_fifo_error", | |
9754 | "btb_rc_pkt6_blk_fifo_error", | |
9755 | "btb_rc_pkt6_rls_left_fifo_error", | |
9756 | "btb_rc_pkt6_strt_ptr_fifo_error", | |
9757 | "btb_rc_pkt6_second_ptr_fifo_error", | |
9758 | "btb_rc_pkt6_rsp_fifo_error", | |
9759 | "btb_rc_pkt6_dscr_fifo_error", | |
9760 | "btb_rc_pkt7_rls_error", | |
9761 | "btb_rc_pkt7_len_error", | |
9762 | "btb_rc_pkt7_protocol_error", | |
9763 | "btb_rc_pkt7_side_fifo_error", | |
9764 | "btb_rc_pkt7_req_fifo_error", | |
9765 | "btb_rc_pkt7_blk_fifo_error", | |
9766 | "btb_rc_pkt7_rls_left_fifo_error", | |
9767 | "btb_rc_pkt7_strt_ptr_fifo_error", | |
9768 | "btb_rc_pkt7_second_ptr_fifo_error", | |
9769 | "btb_rc_pkt7_rsp_fifo_error", | |
9770 | "btb_packet_available_sync_fifo_push_error", | |
9771 | "btb_wc6_notify_fifo_error", | |
9772 | "btb_wc9_queue_fifo_error", | |
9773 | "btb_wc0_sync_fifo_push_error", | |
9774 | "btb_rls_sync_fifo_push_error", | |
9775 | "btb_rc_pkt7_dscr_fifo_error", | |
9776 | }; | |
9777 | #else | |
9778 | #define btb_int_attn_desc OSAL_NULL | |
9779 | #endif | |
9780 | ||
9781 | static const u16 btb_int0_bb_a0_attn_idx[16] = { | |
9782 | 0, 1, 3, 5, 6, 8, 10, 11, 13, 15, 16, 18, 20, 21, 23, 25, | |
9783 | }; | |
9784 | ||
9785 | static struct attn_hw_reg btb_int0_bb_a0 = { | |
9786 | 0, 16, btb_int0_bb_a0_attn_idx, 0xdb00c0, 0xdb00cc, 0xdb00c8, 0xdb00c4 | |
9787 | }; | |
9788 | ||
9789 | static const u16 btb_int1_bb_a0_attn_idx[16] = { | |
9790 | 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, | |
9791 | }; | |
9792 | ||
9793 | static struct attn_hw_reg btb_int1_bb_a0 = { | |
9794 | 1, 16, btb_int1_bb_a0_attn_idx, 0xdb00d8, 0xdb00e4, 0xdb00e0, 0xdb00dc | |
9795 | }; | |
9796 | ||
9797 | static const u16 btb_int2_bb_a0_attn_idx[4] = { | |
9798 | 42, 43, 44, 45, | |
9799 | }; | |
9800 | ||
9801 | static struct attn_hw_reg btb_int2_bb_a0 = { | |
9802 | 2, 4, btb_int2_bb_a0_attn_idx, 0xdb00f0, 0xdb00fc, 0xdb00f8, 0xdb00f4 | |
9803 | }; | |
9804 | ||
9805 | static const u16 btb_int3_bb_a0_attn_idx[32] = { | |
9806 | 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, | |
9807 | 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, | |
9808 | }; | |
9809 | ||
9810 | static struct attn_hw_reg btb_int3_bb_a0 = { | |
9811 | 3, 32, btb_int3_bb_a0_attn_idx, 0xdb0108, 0xdb0114, 0xdb0110, 0xdb010c | |
9812 | }; | |
9813 | ||
9814 | static const u16 btb_int4_bb_a0_attn_idx[23] = { | |
9815 | 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, | |
9816 | 96, 97, 98, 99, 100, | |
9817 | }; | |
9818 | ||
9819 | static struct attn_hw_reg btb_int4_bb_a0 = { | |
9820 | 4, 23, btb_int4_bb_a0_attn_idx, 0xdb0120, 0xdb012c, 0xdb0128, 0xdb0124 | |
9821 | }; | |
9822 | ||
9823 | static const u16 btb_int5_bb_a0_attn_idx[32] = { | |
9824 | 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, | |
9825 | 115, | |
9826 | 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, | |
9827 | 130, 131, | |
9828 | 132, | |
9829 | }; | |
9830 | ||
9831 | static struct attn_hw_reg btb_int5_bb_a0 = { | |
9832 | 5, 32, btb_int5_bb_a0_attn_idx, 0xdb0138, 0xdb0144, 0xdb0140, 0xdb013c | |
9833 | }; | |
9834 | ||
9835 | static const u16 btb_int6_bb_a0_attn_idx[1] = { | |
9836 | 133, | |
9837 | }; | |
9838 | ||
9839 | static struct attn_hw_reg btb_int6_bb_a0 = { | |
9840 | 6, 1, btb_int6_bb_a0_attn_idx, 0xdb0150, 0xdb015c, 0xdb0158, 0xdb0154 | |
9841 | }; | |
9842 | ||
9843 | static const u16 btb_int8_bb_a0_attn_idx[1] = { | |
9844 | 134, | |
9845 | }; | |
9846 | ||
9847 | static struct attn_hw_reg btb_int8_bb_a0 = { | |
9848 | 7, 1, btb_int8_bb_a0_attn_idx, 0xdb0184, 0xdb0190, 0xdb018c, 0xdb0188 | |
9849 | }; | |
9850 | ||
9851 | static const u16 btb_int9_bb_a0_attn_idx[1] = { | |
9852 | 135, | |
9853 | }; | |
9854 | ||
9855 | static struct attn_hw_reg btb_int9_bb_a0 = { | |
9856 | 8, 1, btb_int9_bb_a0_attn_idx, 0xdb019c, 0xdb01a8, 0xdb01a4, 0xdb01a0 | |
9857 | }; | |
9858 | ||
9859 | static const u16 btb_int10_bb_a0_attn_idx[1] = { | |
9860 | 136, | |
9861 | }; | |
9862 | ||
9863 | static struct attn_hw_reg btb_int10_bb_a0 = { | |
9864 | 9, 1, btb_int10_bb_a0_attn_idx, 0xdb01b4, 0xdb01c0, 0xdb01bc, 0xdb01b8 | |
9865 | }; | |
9866 | ||
9867 | static const u16 btb_int11_bb_a0_attn_idx[2] = { | |
9868 | 137, 138, | |
9869 | }; | |
9870 | ||
9871 | static struct attn_hw_reg btb_int11_bb_a0 = { | |
9872 | 10, 2, btb_int11_bb_a0_attn_idx, 0xdb01cc, 0xdb01d8, 0xdb01d4, 0xdb01d0 | |
9873 | }; | |
9874 | ||
9875 | static struct attn_hw_reg *btb_int_bb_a0_regs[11] = { | |
9876 | &btb_int0_bb_a0, &btb_int1_bb_a0, &btb_int2_bb_a0, &btb_int3_bb_a0, | |
9877 | &btb_int4_bb_a0, &btb_int5_bb_a0, &btb_int6_bb_a0, &btb_int8_bb_a0, | |
9878 | &btb_int9_bb_a0, &btb_int10_bb_a0, | |
9879 | &btb_int11_bb_a0, | |
9880 | }; | |
9881 | ||
9882 | static const u16 btb_int0_bb_b0_attn_idx[16] = { | |
9883 | 0, 1, 3, 5, 6, 8, 10, 11, 13, 15, 16, 18, 20, 21, 23, 25, | |
9884 | }; | |
9885 | ||
9886 | static struct attn_hw_reg btb_int0_bb_b0 = { | |
9887 | 0, 16, btb_int0_bb_b0_attn_idx, 0xdb00c0, 0xdb00cc, 0xdb00c8, 0xdb00c4 | |
9888 | }; | |
9889 | ||
9890 | static const u16 btb_int1_bb_b0_attn_idx[16] = { | |
9891 | 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, | |
9892 | }; | |
9893 | ||
9894 | static struct attn_hw_reg btb_int1_bb_b0 = { | |
9895 | 1, 16, btb_int1_bb_b0_attn_idx, 0xdb00d8, 0xdb00e4, 0xdb00e0, 0xdb00dc | |
9896 | }; | |
9897 | ||
9898 | static const u16 btb_int2_bb_b0_attn_idx[4] = { | |
9899 | 42, 43, 44, 45, | |
9900 | }; | |
9901 | ||
9902 | static struct attn_hw_reg btb_int2_bb_b0 = { | |
9903 | 2, 4, btb_int2_bb_b0_attn_idx, 0xdb00f0, 0xdb00fc, 0xdb00f8, 0xdb00f4 | |
9904 | }; | |
9905 | ||
9906 | static const u16 btb_int3_bb_b0_attn_idx[32] = { | |
9907 | 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, | |
9908 | 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, | |
9909 | }; | |
9910 | ||
9911 | static struct attn_hw_reg btb_int3_bb_b0 = { | |
9912 | 3, 32, btb_int3_bb_b0_attn_idx, 0xdb0108, 0xdb0114, 0xdb0110, 0xdb010c | |
9913 | }; | |
9914 | ||
9915 | static const u16 btb_int4_bb_b0_attn_idx[23] = { | |
9916 | 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, | |
9917 | 96, 97, 98, 99, 100, | |
9918 | }; | |
9919 | ||
9920 | static struct attn_hw_reg btb_int4_bb_b0 = { | |
9921 | 4, 23, btb_int4_bb_b0_attn_idx, 0xdb0120, 0xdb012c, 0xdb0128, 0xdb0124 | |
9922 | }; | |
9923 | ||
9924 | static const u16 btb_int5_bb_b0_attn_idx[32] = { | |
9925 | 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, | |
9926 | 115, | |
9927 | 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, | |
9928 | 130, 131, | |
9929 | 132, | |
9930 | }; | |
9931 | ||
9932 | static struct attn_hw_reg btb_int5_bb_b0 = { | |
9933 | 5, 32, btb_int5_bb_b0_attn_idx, 0xdb0138, 0xdb0144, 0xdb0140, 0xdb013c | |
9934 | }; | |
9935 | ||
9936 | static const u16 btb_int6_bb_b0_attn_idx[1] = { | |
9937 | 133, | |
9938 | }; | |
9939 | ||
9940 | static struct attn_hw_reg btb_int6_bb_b0 = { | |
9941 | 6, 1, btb_int6_bb_b0_attn_idx, 0xdb0150, 0xdb015c, 0xdb0158, 0xdb0154 | |
9942 | }; | |
9943 | ||
9944 | static const u16 btb_int8_bb_b0_attn_idx[1] = { | |
9945 | 134, | |
9946 | }; | |
9947 | ||
9948 | static struct attn_hw_reg btb_int8_bb_b0 = { | |
9949 | 7, 1, btb_int8_bb_b0_attn_idx, 0xdb0184, 0xdb0190, 0xdb018c, 0xdb0188 | |
9950 | }; | |
9951 | ||
9952 | static const u16 btb_int9_bb_b0_attn_idx[1] = { | |
9953 | 135, | |
9954 | }; | |
9955 | ||
9956 | static struct attn_hw_reg btb_int9_bb_b0 = { | |
9957 | 8, 1, btb_int9_bb_b0_attn_idx, 0xdb019c, 0xdb01a8, 0xdb01a4, 0xdb01a0 | |
9958 | }; | |
9959 | ||
9960 | static const u16 btb_int10_bb_b0_attn_idx[1] = { | |
9961 | 136, | |
9962 | }; | |
9963 | ||
9964 | static struct attn_hw_reg btb_int10_bb_b0 = { | |
9965 | 9, 1, btb_int10_bb_b0_attn_idx, 0xdb01b4, 0xdb01c0, 0xdb01bc, 0xdb01b8 | |
9966 | }; | |
9967 | ||
9968 | static const u16 btb_int11_bb_b0_attn_idx[2] = { | |
9969 | 137, 138, | |
9970 | }; | |
9971 | ||
9972 | static struct attn_hw_reg btb_int11_bb_b0 = { | |
9973 | 10, 2, btb_int11_bb_b0_attn_idx, 0xdb01cc, 0xdb01d8, 0xdb01d4, 0xdb01d0 | |
9974 | }; | |
9975 | ||
9976 | static struct attn_hw_reg *btb_int_bb_b0_regs[11] = { | |
9977 | &btb_int0_bb_b0, &btb_int1_bb_b0, &btb_int2_bb_b0, &btb_int3_bb_b0, | |
9978 | &btb_int4_bb_b0, &btb_int5_bb_b0, &btb_int6_bb_b0, &btb_int8_bb_b0, | |
9979 | &btb_int9_bb_b0, &btb_int10_bb_b0, | |
9980 | &btb_int11_bb_b0, | |
9981 | }; | |
9982 | ||
9983 | static const u16 btb_int0_k2_attn_idx[16] = { | |
9984 | 0, 1, 3, 5, 6, 8, 10, 11, 13, 15, 16, 18, 20, 21, 23, 25, | |
9985 | }; | |
9986 | ||
9987 | static struct attn_hw_reg btb_int0_k2 = { | |
9988 | 0, 16, btb_int0_k2_attn_idx, 0xdb00c0, 0xdb00cc, 0xdb00c8, 0xdb00c4 | |
9989 | }; | |
9990 | ||
9991 | static const u16 btb_int1_k2_attn_idx[16] = { | |
9992 | 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, | |
9993 | }; | |
9994 | ||
9995 | static struct attn_hw_reg btb_int1_k2 = { | |
9996 | 1, 16, btb_int1_k2_attn_idx, 0xdb00d8, 0xdb00e4, 0xdb00e0, 0xdb00dc | |
9997 | }; | |
9998 | ||
9999 | static const u16 btb_int2_k2_attn_idx[4] = { | |
10000 | 42, 43, 44, 45, | |
10001 | }; | |
10002 | ||
10003 | static struct attn_hw_reg btb_int2_k2 = { | |
10004 | 2, 4, btb_int2_k2_attn_idx, 0xdb00f0, 0xdb00fc, 0xdb00f8, 0xdb00f4 | |
10005 | }; | |
10006 | ||
10007 | static const u16 btb_int3_k2_attn_idx[32] = { | |
10008 | 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, | |
10009 | 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, | |
10010 | }; | |
10011 | ||
10012 | static struct attn_hw_reg btb_int3_k2 = { | |
10013 | 3, 32, btb_int3_k2_attn_idx, 0xdb0108, 0xdb0114, 0xdb0110, 0xdb010c | |
10014 | }; | |
10015 | ||
10016 | static const u16 btb_int4_k2_attn_idx[23] = { | |
10017 | 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, | |
10018 | 96, 97, 98, 99, 100, | |
10019 | }; | |
10020 | ||
10021 | static struct attn_hw_reg btb_int4_k2 = { | |
10022 | 4, 23, btb_int4_k2_attn_idx, 0xdb0120, 0xdb012c, 0xdb0128, 0xdb0124 | |
10023 | }; | |
10024 | ||
10025 | static const u16 btb_int5_k2_attn_idx[32] = { | |
10026 | 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, | |
10027 | 115, | |
10028 | 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, | |
10029 | 130, 131, | |
10030 | 132, | |
10031 | }; | |
10032 | ||
10033 | static struct attn_hw_reg btb_int5_k2 = { | |
10034 | 5, 32, btb_int5_k2_attn_idx, 0xdb0138, 0xdb0144, 0xdb0140, 0xdb013c | |
10035 | }; | |
10036 | ||
10037 | static const u16 btb_int6_k2_attn_idx[1] = { | |
10038 | 133, | |
10039 | }; | |
10040 | ||
10041 | static struct attn_hw_reg btb_int6_k2 = { | |
10042 | 6, 1, btb_int6_k2_attn_idx, 0xdb0150, 0xdb015c, 0xdb0158, 0xdb0154 | |
10043 | }; | |
10044 | ||
10045 | static const u16 btb_int8_k2_attn_idx[1] = { | |
10046 | 134, | |
10047 | }; | |
10048 | ||
10049 | static struct attn_hw_reg btb_int8_k2 = { | |
10050 | 7, 1, btb_int8_k2_attn_idx, 0xdb0184, 0xdb0190, 0xdb018c, 0xdb0188 | |
10051 | }; | |
10052 | ||
10053 | static const u16 btb_int9_k2_attn_idx[1] = { | |
10054 | 135, | |
10055 | }; | |
10056 | ||
10057 | static struct attn_hw_reg btb_int9_k2 = { | |
10058 | 8, 1, btb_int9_k2_attn_idx, 0xdb019c, 0xdb01a8, 0xdb01a4, 0xdb01a0 | |
10059 | }; | |
10060 | ||
10061 | static const u16 btb_int10_k2_attn_idx[1] = { | |
10062 | 136, | |
10063 | }; | |
10064 | ||
10065 | static struct attn_hw_reg btb_int10_k2 = { | |
10066 | 9, 1, btb_int10_k2_attn_idx, 0xdb01b4, 0xdb01c0, 0xdb01bc, 0xdb01b8 | |
10067 | }; | |
10068 | ||
10069 | static const u16 btb_int11_k2_attn_idx[2] = { | |
10070 | 137, 138, | |
10071 | }; | |
10072 | ||
10073 | static struct attn_hw_reg btb_int11_k2 = { | |
10074 | 10, 2, btb_int11_k2_attn_idx, 0xdb01cc, 0xdb01d8, 0xdb01d4, 0xdb01d0 | |
10075 | }; | |
10076 | ||
10077 | static struct attn_hw_reg *btb_int_k2_regs[11] = { | |
10078 | &btb_int0_k2, &btb_int1_k2, &btb_int2_k2, &btb_int3_k2, &btb_int4_k2, | |
10079 | &btb_int5_k2, &btb_int6_k2, &btb_int8_k2, &btb_int9_k2, &btb_int10_k2, | |
10080 | &btb_int11_k2, | |
10081 | }; | |
10082 | ||
10083 | #ifdef ATTN_DESC | |
10084 | static const char *btb_prty_attn_desc[36] = { | |
10085 | "btb_ll_bank0_mem_prty", | |
10086 | "btb_ll_bank1_mem_prty", | |
10087 | "btb_ll_bank2_mem_prty", | |
10088 | "btb_ll_bank3_mem_prty", | |
10089 | "btb_datapath_registers", | |
10090 | "btb_mem001_i_ecc_rf_int", | |
10091 | "btb_mem008_i_ecc_rf_int", | |
10092 | "btb_mem009_i_ecc_rf_int", | |
10093 | "btb_mem010_i_ecc_rf_int", | |
10094 | "btb_mem011_i_ecc_rf_int", | |
10095 | "btb_mem012_i_ecc_rf_int", | |
10096 | "btb_mem013_i_ecc_rf_int", | |
10097 | "btb_mem014_i_ecc_rf_int", | |
10098 | "btb_mem015_i_ecc_rf_int", | |
10099 | "btb_mem016_i_ecc_rf_int", | |
10100 | "btb_mem002_i_ecc_rf_int", | |
10101 | "btb_mem003_i_ecc_rf_int", | |
10102 | "btb_mem004_i_ecc_rf_int", | |
10103 | "btb_mem005_i_ecc_rf_int", | |
10104 | "btb_mem006_i_ecc_rf_int", | |
10105 | "btb_mem007_i_ecc_rf_int", | |
10106 | "btb_mem033_i_mem_prty", | |
10107 | "btb_mem035_i_mem_prty", | |
10108 | "btb_mem034_i_mem_prty", | |
10109 | "btb_mem032_i_mem_prty", | |
10110 | "btb_mem031_i_mem_prty", | |
10111 | "btb_mem021_i_mem_prty", | |
10112 | "btb_mem022_i_mem_prty", | |
10113 | "btb_mem023_i_mem_prty", | |
10114 | "btb_mem024_i_mem_prty", | |
10115 | "btb_mem025_i_mem_prty", | |
10116 | "btb_mem026_i_mem_prty", | |
10117 | "btb_mem027_i_mem_prty", | |
10118 | "btb_mem028_i_mem_prty", | |
10119 | "btb_mem030_i_mem_prty", | |
10120 | "btb_mem029_i_mem_prty", | |
10121 | }; | |
10122 | #else | |
10123 | #define btb_prty_attn_desc OSAL_NULL | |
10124 | #endif | |
10125 | ||
10126 | static const u16 btb_prty1_bb_a0_attn_idx[27] = { | |
10127 | 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 25, 26, 27, | |
10128 | 28, | |
10129 | 29, 30, 31, 32, 33, 34, 35, | |
10130 | }; | |
10131 | ||
10132 | static struct attn_hw_reg btb_prty1_bb_a0 = { | |
10133 | 0, 27, btb_prty1_bb_a0_attn_idx, 0xdb0400, 0xdb040c, 0xdb0408, 0xdb0404 | |
10134 | }; | |
10135 | ||
10136 | static struct attn_hw_reg *btb_prty_bb_a0_regs[1] = { | |
10137 | &btb_prty1_bb_a0, | |
10138 | }; | |
10139 | ||
10140 | static const u16 btb_prty0_bb_b0_attn_idx[5] = { | |
10141 | 0, 1, 2, 3, 4, | |
10142 | }; | |
10143 | ||
10144 | static struct attn_hw_reg btb_prty0_bb_b0 = { | |
10145 | 0, 5, btb_prty0_bb_b0_attn_idx, 0xdb01dc, 0xdb01e8, 0xdb01e4, 0xdb01e0 | |
10146 | }; | |
10147 | ||
10148 | static const u16 btb_prty1_bb_b0_attn_idx[23] = { | |
10149 | 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 25, 30, 31, | |
10150 | 32, | |
10151 | 33, 34, 35, | |
10152 | }; | |
10153 | ||
10154 | static struct attn_hw_reg btb_prty1_bb_b0 = { | |
10155 | 1, 23, btb_prty1_bb_b0_attn_idx, 0xdb0400, 0xdb040c, 0xdb0408, 0xdb0404 | |
10156 | }; | |
10157 | ||
10158 | static struct attn_hw_reg *btb_prty_bb_b0_regs[2] = { | |
10159 | &btb_prty0_bb_b0, &btb_prty1_bb_b0, | |
10160 | }; | |
10161 | ||
10162 | static const u16 btb_prty0_k2_attn_idx[5] = { | |
10163 | 0, 1, 2, 3, 4, | |
10164 | }; | |
10165 | ||
10166 | static struct attn_hw_reg btb_prty0_k2 = { | |
10167 | 0, 5, btb_prty0_k2_attn_idx, 0xdb01dc, 0xdb01e8, 0xdb01e4, 0xdb01e0 | |
10168 | }; | |
10169 | ||
10170 | static const u16 btb_prty1_k2_attn_idx[31] = { | |
10171 | 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, | |
10172 | 24, | |
10173 | 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, | |
10174 | }; | |
10175 | ||
10176 | static struct attn_hw_reg btb_prty1_k2 = { | |
10177 | 1, 31, btb_prty1_k2_attn_idx, 0xdb0400, 0xdb040c, 0xdb0408, 0xdb0404 | |
10178 | }; | |
10179 | ||
10180 | static struct attn_hw_reg *btb_prty_k2_regs[2] = { | |
10181 | &btb_prty0_k2, &btb_prty1_k2, | |
10182 | }; | |
10183 | ||
10184 | #ifdef ATTN_DESC | |
10185 | static const char *pbf_int_attn_desc[1] = { | |
10186 | "pbf_address_error", | |
10187 | }; | |
10188 | #else | |
10189 | #define pbf_int_attn_desc OSAL_NULL | |
10190 | #endif | |
10191 | ||
10192 | static const u16 pbf_int0_bb_a0_attn_idx[1] = { | |
10193 | 0, | |
10194 | }; | |
10195 | ||
10196 | static struct attn_hw_reg pbf_int0_bb_a0 = { | |
10197 | 0, 1, pbf_int0_bb_a0_attn_idx, 0xd80180, 0xd8018c, 0xd80188, 0xd80184 | |
10198 | }; | |
10199 | ||
10200 | static struct attn_hw_reg *pbf_int_bb_a0_regs[1] = { | |
10201 | &pbf_int0_bb_a0, | |
10202 | }; | |
10203 | ||
10204 | static const u16 pbf_int0_bb_b0_attn_idx[1] = { | |
10205 | 0, | |
10206 | }; | |
10207 | ||
10208 | static struct attn_hw_reg pbf_int0_bb_b0 = { | |
10209 | 0, 1, pbf_int0_bb_b0_attn_idx, 0xd80180, 0xd8018c, 0xd80188, 0xd80184 | |
10210 | }; | |
10211 | ||
10212 | static struct attn_hw_reg *pbf_int_bb_b0_regs[1] = { | |
10213 | &pbf_int0_bb_b0, | |
10214 | }; | |
10215 | ||
10216 | static const u16 pbf_int0_k2_attn_idx[1] = { | |
10217 | 0, | |
10218 | }; | |
10219 | ||
10220 | static struct attn_hw_reg pbf_int0_k2 = { | |
10221 | 0, 1, pbf_int0_k2_attn_idx, 0xd80180, 0xd8018c, 0xd80188, 0xd80184 | |
10222 | }; | |
10223 | ||
10224 | static struct attn_hw_reg *pbf_int_k2_regs[1] = { | |
10225 | &pbf_int0_k2, | |
10226 | }; | |
10227 | ||
10228 | #ifdef ATTN_DESC | |
10229 | static const char *pbf_prty_attn_desc[59] = { | |
10230 | "pbf_datapath_registers", | |
10231 | "pbf_mem041_i_ecc_rf_int", | |
10232 | "pbf_mem042_i_ecc_rf_int", | |
10233 | "pbf_mem033_i_ecc_rf_int", | |
10234 | "pbf_mem003_i_ecc_rf_int", | |
10235 | "pbf_mem018_i_ecc_rf_int", | |
10236 | "pbf_mem009_i_ecc_0_rf_int", | |
10237 | "pbf_mem009_i_ecc_1_rf_int", | |
10238 | "pbf_mem012_i_ecc_0_rf_int", | |
10239 | "pbf_mem012_i_ecc_1_rf_int", | |
10240 | "pbf_mem012_i_ecc_2_rf_int", | |
10241 | "pbf_mem012_i_ecc_3_rf_int", | |
10242 | "pbf_mem012_i_ecc_4_rf_int", | |
10243 | "pbf_mem012_i_ecc_5_rf_int", | |
10244 | "pbf_mem012_i_ecc_6_rf_int", | |
10245 | "pbf_mem012_i_ecc_7_rf_int", | |
10246 | "pbf_mem012_i_ecc_8_rf_int", | |
10247 | "pbf_mem012_i_ecc_9_rf_int", | |
10248 | "pbf_mem012_i_ecc_10_rf_int", | |
10249 | "pbf_mem012_i_ecc_11_rf_int", | |
10250 | "pbf_mem012_i_ecc_12_rf_int", | |
10251 | "pbf_mem012_i_ecc_13_rf_int", | |
10252 | "pbf_mem012_i_ecc_14_rf_int", | |
10253 | "pbf_mem012_i_ecc_15_rf_int", | |
10254 | "pbf_mem040_i_mem_prty", | |
10255 | "pbf_mem039_i_mem_prty", | |
10256 | "pbf_mem038_i_mem_prty", | |
10257 | "pbf_mem034_i_mem_prty", | |
10258 | "pbf_mem032_i_mem_prty", | |
10259 | "pbf_mem031_i_mem_prty", | |
10260 | "pbf_mem030_i_mem_prty", | |
10261 | "pbf_mem029_i_mem_prty", | |
10262 | "pbf_mem022_i_mem_prty", | |
10263 | "pbf_mem023_i_mem_prty", | |
10264 | "pbf_mem021_i_mem_prty", | |
10265 | "pbf_mem020_i_mem_prty", | |
10266 | "pbf_mem001_i_mem_prty", | |
10267 | "pbf_mem002_i_mem_prty", | |
10268 | "pbf_mem006_i_mem_prty", | |
10269 | "pbf_mem007_i_mem_prty", | |
10270 | "pbf_mem005_i_mem_prty", | |
10271 | "pbf_mem004_i_mem_prty", | |
10272 | "pbf_mem028_i_mem_prty", | |
10273 | "pbf_mem026_i_mem_prty", | |
10274 | "pbf_mem027_i_mem_prty", | |
10275 | "pbf_mem019_i_mem_prty", | |
10276 | "pbf_mem016_i_mem_prty", | |
10277 | "pbf_mem017_i_mem_prty", | |
10278 | "pbf_mem008_i_mem_prty", | |
10279 | "pbf_mem011_i_mem_prty", | |
10280 | "pbf_mem010_i_mem_prty", | |
10281 | "pbf_mem024_i_mem_prty", | |
10282 | "pbf_mem025_i_mem_prty", | |
10283 | "pbf_mem037_i_mem_prty", | |
10284 | "pbf_mem036_i_mem_prty", | |
10285 | "pbf_mem035_i_mem_prty", | |
10286 | "pbf_mem014_i_mem_prty", | |
10287 | "pbf_mem015_i_mem_prty", | |
10288 | "pbf_mem013_i_mem_prty", | |
10289 | }; | |
10290 | #else | |
10291 | #define pbf_prty_attn_desc OSAL_NULL | |
10292 | #endif | |
10293 | ||
10294 | static const u16 pbf_prty1_bb_a0_attn_idx[31] = { | |
10295 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, | |
10296 | 21, | |
10297 | 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
10298 | }; | |
10299 | ||
10300 | static struct attn_hw_reg pbf_prty1_bb_a0 = { | |
10301 | 0, 31, pbf_prty1_bb_a0_attn_idx, 0xd80200, 0xd8020c, 0xd80208, 0xd80204 | |
10302 | }; | |
10303 | ||
10304 | static const u16 pbf_prty2_bb_a0_attn_idx[27] = { | |
10305 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, | |
10306 | 50, 51, 52, 53, 54, 55, 56, 57, 58, | |
10307 | }; | |
10308 | ||
10309 | static struct attn_hw_reg pbf_prty2_bb_a0 = { | |
10310 | 1, 27, pbf_prty2_bb_a0_attn_idx, 0xd80210, 0xd8021c, 0xd80218, 0xd80214 | |
10311 | }; | |
10312 | ||
10313 | static struct attn_hw_reg *pbf_prty_bb_a0_regs[2] = { | |
10314 | &pbf_prty1_bb_a0, &pbf_prty2_bb_a0, | |
10315 | }; | |
10316 | ||
10317 | static const u16 pbf_prty0_bb_b0_attn_idx[1] = { | |
10318 | 0, | |
10319 | }; | |
10320 | ||
10321 | static struct attn_hw_reg pbf_prty0_bb_b0 = { | |
10322 | 0, 1, pbf_prty0_bb_b0_attn_idx, 0xd80190, 0xd8019c, 0xd80198, 0xd80194 | |
10323 | }; | |
10324 | ||
10325 | static const u16 pbf_prty1_bb_b0_attn_idx[31] = { | |
10326 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, | |
10327 | 21, | |
10328 | 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
10329 | }; | |
10330 | ||
10331 | static struct attn_hw_reg pbf_prty1_bb_b0 = { | |
10332 | 1, 31, pbf_prty1_bb_b0_attn_idx, 0xd80200, 0xd8020c, 0xd80208, 0xd80204 | |
10333 | }; | |
10334 | ||
10335 | static const u16 pbf_prty2_bb_b0_attn_idx[27] = { | |
10336 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, | |
10337 | 50, 51, 52, 53, 54, 55, 56, 57, 58, | |
10338 | }; | |
10339 | ||
10340 | static struct attn_hw_reg pbf_prty2_bb_b0 = { | |
10341 | 2, 27, pbf_prty2_bb_b0_attn_idx, 0xd80210, 0xd8021c, 0xd80218, 0xd80214 | |
10342 | }; | |
10343 | ||
10344 | static struct attn_hw_reg *pbf_prty_bb_b0_regs[3] = { | |
10345 | &pbf_prty0_bb_b0, &pbf_prty1_bb_b0, &pbf_prty2_bb_b0, | |
10346 | }; | |
10347 | ||
10348 | static const u16 pbf_prty0_k2_attn_idx[1] = { | |
10349 | 0, | |
10350 | }; | |
10351 | ||
10352 | static struct attn_hw_reg pbf_prty0_k2 = { | |
10353 | 0, 1, pbf_prty0_k2_attn_idx, 0xd80190, 0xd8019c, 0xd80198, 0xd80194 | |
10354 | }; | |
10355 | ||
10356 | static const u16 pbf_prty1_k2_attn_idx[31] = { | |
10357 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, | |
10358 | 21, | |
10359 | 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
10360 | }; | |
10361 | ||
10362 | static struct attn_hw_reg pbf_prty1_k2 = { | |
10363 | 1, 31, pbf_prty1_k2_attn_idx, 0xd80200, 0xd8020c, 0xd80208, 0xd80204 | |
10364 | }; | |
10365 | ||
10366 | static const u16 pbf_prty2_k2_attn_idx[27] = { | |
10367 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, | |
10368 | 50, 51, 52, 53, 54, 55, 56, 57, 58, | |
10369 | }; | |
10370 | ||
10371 | static struct attn_hw_reg pbf_prty2_k2 = { | |
10372 | 2, 27, pbf_prty2_k2_attn_idx, 0xd80210, 0xd8021c, 0xd80218, 0xd80214 | |
10373 | }; | |
10374 | ||
10375 | static struct attn_hw_reg *pbf_prty_k2_regs[3] = { | |
10376 | &pbf_prty0_k2, &pbf_prty1_k2, &pbf_prty2_k2, | |
10377 | }; | |
10378 | ||
10379 | #ifdef ATTN_DESC | |
10380 | static const char *rdif_int_attn_desc[9] = { | |
10381 | "rdif_address_error", | |
10382 | "rdif_fatal_dix_err", | |
10383 | "rdif_fatal_config_err", | |
10384 | "rdif_cmd_fifo_err", | |
10385 | "rdif_order_fifo_err", | |
10386 | "rdif_rdata_fifo_err", | |
10387 | "rdif_dif_stop_err", | |
10388 | "rdif_partial_dif_w_eob", | |
10389 | "rdif_l1_dirty_bit", | |
10390 | }; | |
10391 | #else | |
10392 | #define rdif_int_attn_desc OSAL_NULL | |
10393 | #endif | |
10394 | ||
10395 | static const u16 rdif_int0_bb_a0_attn_idx[8] = { | |
10396 | 0, 1, 2, 3, 4, 5, 6, 7, | |
10397 | }; | |
10398 | ||
10399 | static struct attn_hw_reg rdif_int0_bb_a0 = { | |
10400 | 0, 8, rdif_int0_bb_a0_attn_idx, 0x300180, 0x30018c, 0x300188, 0x300184 | |
10401 | }; | |
10402 | ||
10403 | static struct attn_hw_reg *rdif_int_bb_a0_regs[1] = { | |
10404 | &rdif_int0_bb_a0, | |
10405 | }; | |
10406 | ||
10407 | static const u16 rdif_int0_bb_b0_attn_idx[8] = { | |
10408 | 0, 1, 2, 3, 4, 5, 6, 7, | |
10409 | }; | |
10410 | ||
10411 | static struct attn_hw_reg rdif_int0_bb_b0 = { | |
10412 | 0, 8, rdif_int0_bb_b0_attn_idx, 0x300180, 0x30018c, 0x300188, 0x300184 | |
10413 | }; | |
10414 | ||
10415 | static struct attn_hw_reg *rdif_int_bb_b0_regs[1] = { | |
10416 | &rdif_int0_bb_b0, | |
10417 | }; | |
10418 | ||
10419 | static const u16 rdif_int0_k2_attn_idx[9] = { | |
10420 | 0, 1, 2, 3, 4, 5, 6, 7, 8, | |
10421 | }; | |
10422 | ||
10423 | static struct attn_hw_reg rdif_int0_k2 = { | |
10424 | 0, 9, rdif_int0_k2_attn_idx, 0x300180, 0x30018c, 0x300188, 0x300184 | |
10425 | }; | |
10426 | ||
10427 | static struct attn_hw_reg *rdif_int_k2_regs[1] = { | |
10428 | &rdif_int0_k2, | |
10429 | }; | |
10430 | ||
10431 | #ifdef ATTN_DESC | |
10432 | static const char *rdif_prty_attn_desc[2] = { | |
10433 | "rdif_unused_0", | |
10434 | "rdif_datapath_registers", | |
10435 | }; | |
10436 | #else | |
10437 | #define rdif_prty_attn_desc OSAL_NULL | |
10438 | #endif | |
10439 | ||
10440 | static const u16 rdif_prty0_bb_b0_attn_idx[1] = { | |
10441 | 1, | |
10442 | }; | |
10443 | ||
10444 | static struct attn_hw_reg rdif_prty0_bb_b0 = { | |
10445 | 0, 1, rdif_prty0_bb_b0_attn_idx, 0x300190, 0x30019c, 0x300198, 0x300194 | |
10446 | }; | |
10447 | ||
10448 | static struct attn_hw_reg *rdif_prty_bb_b0_regs[1] = { | |
10449 | &rdif_prty0_bb_b0, | |
10450 | }; | |
10451 | ||
10452 | static const u16 rdif_prty0_k2_attn_idx[1] = { | |
10453 | 1, | |
10454 | }; | |
10455 | ||
10456 | static struct attn_hw_reg rdif_prty0_k2 = { | |
10457 | 0, 1, rdif_prty0_k2_attn_idx, 0x300190, 0x30019c, 0x300198, 0x300194 | |
10458 | }; | |
10459 | ||
10460 | static struct attn_hw_reg *rdif_prty_k2_regs[1] = { | |
10461 | &rdif_prty0_k2, | |
10462 | }; | |
10463 | ||
10464 | #ifdef ATTN_DESC | |
10465 | static const char *tdif_int_attn_desc[9] = { | |
10466 | "tdif_address_error", | |
10467 | "tdif_fatal_dix_err", | |
10468 | "tdif_fatal_config_err", | |
10469 | "tdif_cmd_fifo_err", | |
10470 | "tdif_order_fifo_err", | |
10471 | "tdif_rdata_fifo_err", | |
10472 | "tdif_dif_stop_err", | |
10473 | "tdif_partial_dif_w_eob", | |
10474 | "tdif_l1_dirty_bit", | |
10475 | }; | |
10476 | #else | |
10477 | #define tdif_int_attn_desc OSAL_NULL | |
10478 | #endif | |
10479 | ||
10480 | static const u16 tdif_int0_bb_a0_attn_idx[8] = { | |
10481 | 0, 1, 2, 3, 4, 5, 6, 7, | |
10482 | }; | |
10483 | ||
10484 | static struct attn_hw_reg tdif_int0_bb_a0 = { | |
10485 | 0, 8, tdif_int0_bb_a0_attn_idx, 0x310180, 0x31018c, 0x310188, 0x310184 | |
10486 | }; | |
10487 | ||
10488 | static struct attn_hw_reg *tdif_int_bb_a0_regs[1] = { | |
10489 | &tdif_int0_bb_a0, | |
10490 | }; | |
10491 | ||
10492 | static const u16 tdif_int0_bb_b0_attn_idx[8] = { | |
10493 | 0, 1, 2, 3, 4, 5, 6, 7, | |
10494 | }; | |
10495 | ||
10496 | static struct attn_hw_reg tdif_int0_bb_b0 = { | |
10497 | 0, 8, tdif_int0_bb_b0_attn_idx, 0x310180, 0x31018c, 0x310188, 0x310184 | |
10498 | }; | |
10499 | ||
10500 | static struct attn_hw_reg *tdif_int_bb_b0_regs[1] = { | |
10501 | &tdif_int0_bb_b0, | |
10502 | }; | |
10503 | ||
10504 | static const u16 tdif_int0_k2_attn_idx[9] = { | |
10505 | 0, 1, 2, 3, 4, 5, 6, 7, 8, | |
10506 | }; | |
10507 | ||
10508 | static struct attn_hw_reg tdif_int0_k2 = { | |
10509 | 0, 9, tdif_int0_k2_attn_idx, 0x310180, 0x31018c, 0x310188, 0x310184 | |
10510 | }; | |
10511 | ||
10512 | static struct attn_hw_reg *tdif_int_k2_regs[1] = { | |
10513 | &tdif_int0_k2, | |
10514 | }; | |
10515 | ||
10516 | #ifdef ATTN_DESC | |
10517 | static const char *tdif_prty_attn_desc[13] = { | |
10518 | "tdif_unused_0", | |
10519 | "tdif_datapath_registers", | |
10520 | "tdif_mem005_i_ecc_rf_int", | |
10521 | "tdif_mem009_i_ecc_rf_int", | |
10522 | "tdif_mem010_i_ecc_rf_int", | |
10523 | "tdif_mem011_i_ecc_rf_int", | |
10524 | "tdif_mem001_i_mem_prty", | |
10525 | "tdif_mem003_i_mem_prty", | |
10526 | "tdif_mem002_i_mem_prty", | |
10527 | "tdif_mem006_i_mem_prty", | |
10528 | "tdif_mem007_i_mem_prty", | |
10529 | "tdif_mem008_i_mem_prty", | |
10530 | "tdif_mem004_i_mem_prty", | |
10531 | }; | |
10532 | #else | |
10533 | #define tdif_prty_attn_desc OSAL_NULL | |
10534 | #endif | |
10535 | ||
10536 | static const u16 tdif_prty1_bb_a0_attn_idx[11] = { | |
10537 | 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, | |
10538 | }; | |
10539 | ||
10540 | static struct attn_hw_reg tdif_prty1_bb_a0 = { | |
10541 | 0, 11, tdif_prty1_bb_a0_attn_idx, 0x310200, 0x31020c, 0x310208, | |
10542 | 0x310204 | |
10543 | }; | |
10544 | ||
10545 | static struct attn_hw_reg *tdif_prty_bb_a0_regs[1] = { | |
10546 | &tdif_prty1_bb_a0, | |
10547 | }; | |
10548 | ||
10549 | static const u16 tdif_prty0_bb_b0_attn_idx[1] = { | |
10550 | 1, | |
10551 | }; | |
10552 | ||
10553 | static struct attn_hw_reg tdif_prty0_bb_b0 = { | |
10554 | 0, 1, tdif_prty0_bb_b0_attn_idx, 0x310190, 0x31019c, 0x310198, 0x310194 | |
10555 | }; | |
10556 | ||
10557 | static const u16 tdif_prty1_bb_b0_attn_idx[11] = { | |
10558 | 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, | |
10559 | }; | |
10560 | ||
10561 | static struct attn_hw_reg tdif_prty1_bb_b0 = { | |
10562 | 1, 11, tdif_prty1_bb_b0_attn_idx, 0x310200, 0x31020c, 0x310208, | |
10563 | 0x310204 | |
10564 | }; | |
10565 | ||
10566 | static struct attn_hw_reg *tdif_prty_bb_b0_regs[2] = { | |
10567 | &tdif_prty0_bb_b0, &tdif_prty1_bb_b0, | |
10568 | }; | |
10569 | ||
10570 | static const u16 tdif_prty0_k2_attn_idx[1] = { | |
10571 | 1, | |
10572 | }; | |
10573 | ||
10574 | static struct attn_hw_reg tdif_prty0_k2 = { | |
10575 | 0, 1, tdif_prty0_k2_attn_idx, 0x310190, 0x31019c, 0x310198, 0x310194 | |
10576 | }; | |
10577 | ||
10578 | static const u16 tdif_prty1_k2_attn_idx[11] = { | |
10579 | 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, | |
10580 | }; | |
10581 | ||
10582 | static struct attn_hw_reg tdif_prty1_k2 = { | |
10583 | 1, 11, tdif_prty1_k2_attn_idx, 0x310200, 0x31020c, 0x310208, 0x310204 | |
10584 | }; | |
10585 | ||
10586 | static struct attn_hw_reg *tdif_prty_k2_regs[2] = { | |
10587 | &tdif_prty0_k2, &tdif_prty1_k2, | |
10588 | }; | |
10589 | ||
10590 | #ifdef ATTN_DESC | |
10591 | static const char *cdu_int_attn_desc[8] = { | |
10592 | "cdu_address_error", | |
10593 | "cdu_ccfc_ld_l1_num_error", | |
10594 | "cdu_tcfc_ld_l1_num_error", | |
10595 | "cdu_ccfc_wb_l1_num_error", | |
10596 | "cdu_tcfc_wb_l1_num_error", | |
10597 | "cdu_ccfc_cvld_error", | |
10598 | "cdu_tcfc_cvld_error", | |
10599 | "cdu_bvalid_error", | |
10600 | }; | |
10601 | #else | |
10602 | #define cdu_int_attn_desc OSAL_NULL | |
10603 | #endif | |
10604 | ||
10605 | static const u16 cdu_int0_bb_a0_attn_idx[8] = { | |
10606 | 0, 1, 2, 3, 4, 5, 6, 7, | |
10607 | }; | |
10608 | ||
10609 | static struct attn_hw_reg cdu_int0_bb_a0 = { | |
10610 | 0, 8, cdu_int0_bb_a0_attn_idx, 0x5801c0, 0x5801c4, 0x5801c8, 0x5801cc | |
10611 | }; | |
10612 | ||
10613 | static struct attn_hw_reg *cdu_int_bb_a0_regs[1] = { | |
10614 | &cdu_int0_bb_a0, | |
10615 | }; | |
10616 | ||
10617 | static const u16 cdu_int0_bb_b0_attn_idx[8] = { | |
10618 | 0, 1, 2, 3, 4, 5, 6, 7, | |
10619 | }; | |
10620 | ||
10621 | static struct attn_hw_reg cdu_int0_bb_b0 = { | |
10622 | 0, 8, cdu_int0_bb_b0_attn_idx, 0x5801c0, 0x5801c4, 0x5801c8, 0x5801cc | |
10623 | }; | |
10624 | ||
10625 | static struct attn_hw_reg *cdu_int_bb_b0_regs[1] = { | |
10626 | &cdu_int0_bb_b0, | |
10627 | }; | |
10628 | ||
10629 | static const u16 cdu_int0_k2_attn_idx[8] = { | |
10630 | 0, 1, 2, 3, 4, 5, 6, 7, | |
10631 | }; | |
10632 | ||
10633 | static struct attn_hw_reg cdu_int0_k2 = { | |
10634 | 0, 8, cdu_int0_k2_attn_idx, 0x5801c0, 0x5801c4, 0x5801c8, 0x5801cc | |
10635 | }; | |
10636 | ||
10637 | static struct attn_hw_reg *cdu_int_k2_regs[1] = { | |
10638 | &cdu_int0_k2, | |
10639 | }; | |
10640 | ||
10641 | #ifdef ATTN_DESC | |
10642 | static const char *cdu_prty_attn_desc[5] = { | |
10643 | "cdu_mem001_i_mem_prty", | |
10644 | "cdu_mem004_i_mem_prty", | |
10645 | "cdu_mem002_i_mem_prty", | |
10646 | "cdu_mem005_i_mem_prty", | |
10647 | "cdu_mem003_i_mem_prty", | |
10648 | }; | |
10649 | #else | |
10650 | #define cdu_prty_attn_desc OSAL_NULL | |
10651 | #endif | |
10652 | ||
10653 | static const u16 cdu_prty1_bb_a0_attn_idx[5] = { | |
10654 | 0, 1, 2, 3, 4, | |
10655 | }; | |
10656 | ||
10657 | static struct attn_hw_reg cdu_prty1_bb_a0 = { | |
10658 | 0, 5, cdu_prty1_bb_a0_attn_idx, 0x580200, 0x58020c, 0x580208, 0x580204 | |
10659 | }; | |
10660 | ||
10661 | static struct attn_hw_reg *cdu_prty_bb_a0_regs[1] = { | |
10662 | &cdu_prty1_bb_a0, | |
10663 | }; | |
10664 | ||
10665 | static const u16 cdu_prty1_bb_b0_attn_idx[5] = { | |
10666 | 0, 1, 2, 3, 4, | |
10667 | }; | |
10668 | ||
10669 | static struct attn_hw_reg cdu_prty1_bb_b0 = { | |
10670 | 0, 5, cdu_prty1_bb_b0_attn_idx, 0x580200, 0x58020c, 0x580208, 0x580204 | |
10671 | }; | |
10672 | ||
10673 | static struct attn_hw_reg *cdu_prty_bb_b0_regs[1] = { | |
10674 | &cdu_prty1_bb_b0, | |
10675 | }; | |
10676 | ||
10677 | static const u16 cdu_prty1_k2_attn_idx[5] = { | |
10678 | 0, 1, 2, 3, 4, | |
10679 | }; | |
10680 | ||
10681 | static struct attn_hw_reg cdu_prty1_k2 = { | |
10682 | 0, 5, cdu_prty1_k2_attn_idx, 0x580200, 0x58020c, 0x580208, 0x580204 | |
10683 | }; | |
10684 | ||
10685 | static struct attn_hw_reg *cdu_prty_k2_regs[1] = { | |
10686 | &cdu_prty1_k2, | |
10687 | }; | |
10688 | ||
10689 | #ifdef ATTN_DESC | |
10690 | static const char *ccfc_int_attn_desc[2] = { | |
10691 | "ccfc_address_error", | |
10692 | "ccfc_exe_error", | |
10693 | }; | |
10694 | #else | |
10695 | #define ccfc_int_attn_desc OSAL_NULL | |
10696 | #endif | |
10697 | ||
10698 | static const u16 ccfc_int0_bb_a0_attn_idx[2] = { | |
10699 | 0, 1, | |
10700 | }; | |
10701 | ||
10702 | static struct attn_hw_reg ccfc_int0_bb_a0 = { | |
10703 | 0, 2, ccfc_int0_bb_a0_attn_idx, 0x2e0180, 0x2e018c, 0x2e0188, 0x2e0184 | |
10704 | }; | |
10705 | ||
10706 | static struct attn_hw_reg *ccfc_int_bb_a0_regs[1] = { | |
10707 | &ccfc_int0_bb_a0, | |
10708 | }; | |
10709 | ||
10710 | static const u16 ccfc_int0_bb_b0_attn_idx[2] = { | |
10711 | 0, 1, | |
10712 | }; | |
10713 | ||
10714 | static struct attn_hw_reg ccfc_int0_bb_b0 = { | |
10715 | 0, 2, ccfc_int0_bb_b0_attn_idx, 0x2e0180, 0x2e018c, 0x2e0188, 0x2e0184 | |
10716 | }; | |
10717 | ||
10718 | static struct attn_hw_reg *ccfc_int_bb_b0_regs[1] = { | |
10719 | &ccfc_int0_bb_b0, | |
10720 | }; | |
10721 | ||
10722 | static const u16 ccfc_int0_k2_attn_idx[2] = { | |
10723 | 0, 1, | |
10724 | }; | |
10725 | ||
10726 | static struct attn_hw_reg ccfc_int0_k2 = { | |
10727 | 0, 2, ccfc_int0_k2_attn_idx, 0x2e0180, 0x2e018c, 0x2e0188, 0x2e0184 | |
10728 | }; | |
10729 | ||
10730 | static struct attn_hw_reg *ccfc_int_k2_regs[1] = { | |
10731 | &ccfc_int0_k2, | |
10732 | }; | |
10733 | ||
10734 | #ifdef ATTN_DESC | |
10735 | static const char *ccfc_prty_attn_desc[10] = { | |
10736 | "ccfc_mem001_i_ecc_rf_int", | |
10737 | "ccfc_mem003_i_mem_prty", | |
10738 | "ccfc_mem007_i_mem_prty", | |
10739 | "ccfc_mem006_i_mem_prty", | |
10740 | "ccfc_ccam_par_err", | |
10741 | "ccfc_scam_par_err", | |
10742 | "ccfc_lc_que_ram_porta_lsb_par_err", | |
10743 | "ccfc_lc_que_ram_porta_msb_par_err", | |
10744 | "ccfc_lc_que_ram_portb_lsb_par_err", | |
10745 | "ccfc_lc_que_ram_portb_msb_par_err", | |
10746 | }; | |
10747 | #else | |
10748 | #define ccfc_prty_attn_desc OSAL_NULL | |
10749 | #endif | |
10750 | ||
10751 | static const u16 ccfc_prty1_bb_a0_attn_idx[4] = { | |
10752 | 0, 1, 2, 3, | |
10753 | }; | |
10754 | ||
10755 | static struct attn_hw_reg ccfc_prty1_bb_a0 = { | |
10756 | 0, 4, ccfc_prty1_bb_a0_attn_idx, 0x2e0200, 0x2e020c, 0x2e0208, 0x2e0204 | |
10757 | }; | |
10758 | ||
10759 | static const u16 ccfc_prty0_bb_a0_attn_idx[2] = { | |
10760 | 4, 5, | |
10761 | }; | |
10762 | ||
10763 | static struct attn_hw_reg ccfc_prty0_bb_a0 = { | |
10764 | 1, 2, ccfc_prty0_bb_a0_attn_idx, 0x2e05e4, 0x2e05f0, 0x2e05ec, 0x2e05e8 | |
10765 | }; | |
10766 | ||
10767 | static struct attn_hw_reg *ccfc_prty_bb_a0_regs[2] = { | |
10768 | &ccfc_prty1_bb_a0, &ccfc_prty0_bb_a0, | |
10769 | }; | |
10770 | ||
10771 | static const u16 ccfc_prty1_bb_b0_attn_idx[2] = { | |
10772 | 0, 1, | |
10773 | }; | |
10774 | ||
10775 | static struct attn_hw_reg ccfc_prty1_bb_b0 = { | |
10776 | 0, 2, ccfc_prty1_bb_b0_attn_idx, 0x2e0200, 0x2e020c, 0x2e0208, 0x2e0204 | |
10777 | }; | |
10778 | ||
10779 | static const u16 ccfc_prty0_bb_b0_attn_idx[6] = { | |
10780 | 4, 5, 6, 7, 8, 9, | |
10781 | }; | |
10782 | ||
10783 | static struct attn_hw_reg ccfc_prty0_bb_b0 = { | |
10784 | 1, 6, ccfc_prty0_bb_b0_attn_idx, 0x2e05e4, 0x2e05f0, 0x2e05ec, 0x2e05e8 | |
10785 | }; | |
10786 | ||
10787 | static struct attn_hw_reg *ccfc_prty_bb_b0_regs[2] = { | |
10788 | &ccfc_prty1_bb_b0, &ccfc_prty0_bb_b0, | |
10789 | }; | |
10790 | ||
10791 | static const u16 ccfc_prty1_k2_attn_idx[2] = { | |
10792 | 0, 1, | |
10793 | }; | |
10794 | ||
10795 | static struct attn_hw_reg ccfc_prty1_k2 = { | |
10796 | 0, 2, ccfc_prty1_k2_attn_idx, 0x2e0200, 0x2e020c, 0x2e0208, 0x2e0204 | |
10797 | }; | |
10798 | ||
10799 | static const u16 ccfc_prty0_k2_attn_idx[6] = { | |
10800 | 4, 5, 6, 7, 8, 9, | |
10801 | }; | |
10802 | ||
10803 | static struct attn_hw_reg ccfc_prty0_k2 = { | |
10804 | 1, 6, ccfc_prty0_k2_attn_idx, 0x2e05e4, 0x2e05f0, 0x2e05ec, 0x2e05e8 | |
10805 | }; | |
10806 | ||
10807 | static struct attn_hw_reg *ccfc_prty_k2_regs[2] = { | |
10808 | &ccfc_prty1_k2, &ccfc_prty0_k2, | |
10809 | }; | |
10810 | ||
10811 | #ifdef ATTN_DESC | |
10812 | static const char *tcfc_int_attn_desc[2] = { | |
10813 | "tcfc_address_error", | |
10814 | "tcfc_exe_error", | |
10815 | }; | |
10816 | #else | |
10817 | #define tcfc_int_attn_desc OSAL_NULL | |
10818 | #endif | |
10819 | ||
10820 | static const u16 tcfc_int0_bb_a0_attn_idx[2] = { | |
10821 | 0, 1, | |
10822 | }; | |
10823 | ||
10824 | static struct attn_hw_reg tcfc_int0_bb_a0 = { | |
10825 | 0, 2, tcfc_int0_bb_a0_attn_idx, 0x2d0180, 0x2d018c, 0x2d0188, 0x2d0184 | |
10826 | }; | |
10827 | ||
10828 | static struct attn_hw_reg *tcfc_int_bb_a0_regs[1] = { | |
10829 | &tcfc_int0_bb_a0, | |
10830 | }; | |
10831 | ||
10832 | static const u16 tcfc_int0_bb_b0_attn_idx[2] = { | |
10833 | 0, 1, | |
10834 | }; | |
10835 | ||
10836 | static struct attn_hw_reg tcfc_int0_bb_b0 = { | |
10837 | 0, 2, tcfc_int0_bb_b0_attn_idx, 0x2d0180, 0x2d018c, 0x2d0188, 0x2d0184 | |
10838 | }; | |
10839 | ||
10840 | static struct attn_hw_reg *tcfc_int_bb_b0_regs[1] = { | |
10841 | &tcfc_int0_bb_b0, | |
10842 | }; | |
10843 | ||
10844 | static const u16 tcfc_int0_k2_attn_idx[2] = { | |
10845 | 0, 1, | |
10846 | }; | |
10847 | ||
10848 | static struct attn_hw_reg tcfc_int0_k2 = { | |
10849 | 0, 2, tcfc_int0_k2_attn_idx, 0x2d0180, 0x2d018c, 0x2d0188, 0x2d0184 | |
10850 | }; | |
10851 | ||
10852 | static struct attn_hw_reg *tcfc_int_k2_regs[1] = { | |
10853 | &tcfc_int0_k2, | |
10854 | }; | |
10855 | ||
10856 | #ifdef ATTN_DESC | |
10857 | static const char *tcfc_prty_attn_desc[10] = { | |
10858 | "tcfc_mem002_i_mem_prty", | |
10859 | "tcfc_mem001_i_mem_prty", | |
10860 | "tcfc_mem006_i_mem_prty", | |
10861 | "tcfc_mem005_i_mem_prty", | |
10862 | "tcfc_ccam_par_err", | |
10863 | "tcfc_scam_par_err", | |
10864 | "tcfc_lc_que_ram_porta_lsb_par_err", | |
10865 | "tcfc_lc_que_ram_porta_msb_par_err", | |
10866 | "tcfc_lc_que_ram_portb_lsb_par_err", | |
10867 | "tcfc_lc_que_ram_portb_msb_par_err", | |
10868 | }; | |
10869 | #else | |
10870 | #define tcfc_prty_attn_desc OSAL_NULL | |
10871 | #endif | |
10872 | ||
10873 | static const u16 tcfc_prty1_bb_a0_attn_idx[4] = { | |
10874 | 0, 1, 2, 3, | |
10875 | }; | |
10876 | ||
10877 | static struct attn_hw_reg tcfc_prty1_bb_a0 = { | |
10878 | 0, 4, tcfc_prty1_bb_a0_attn_idx, 0x2d0200, 0x2d020c, 0x2d0208, 0x2d0204 | |
10879 | }; | |
10880 | ||
10881 | static const u16 tcfc_prty0_bb_a0_attn_idx[2] = { | |
10882 | 4, 5, | |
10883 | }; | |
10884 | ||
10885 | static struct attn_hw_reg tcfc_prty0_bb_a0 = { | |
10886 | 1, 2, tcfc_prty0_bb_a0_attn_idx, 0x2d05e4, 0x2d05f0, 0x2d05ec, 0x2d05e8 | |
10887 | }; | |
10888 | ||
10889 | static struct attn_hw_reg *tcfc_prty_bb_a0_regs[2] = { | |
10890 | &tcfc_prty1_bb_a0, &tcfc_prty0_bb_a0, | |
10891 | }; | |
10892 | ||
10893 | static const u16 tcfc_prty1_bb_b0_attn_idx[2] = { | |
10894 | 0, 1, | |
10895 | }; | |
10896 | ||
10897 | static struct attn_hw_reg tcfc_prty1_bb_b0 = { | |
10898 | 0, 2, tcfc_prty1_bb_b0_attn_idx, 0x2d0200, 0x2d020c, 0x2d0208, 0x2d0204 | |
10899 | }; | |
10900 | ||
10901 | static const u16 tcfc_prty0_bb_b0_attn_idx[6] = { | |
10902 | 4, 5, 6, 7, 8, 9, | |
10903 | }; | |
10904 | ||
10905 | static struct attn_hw_reg tcfc_prty0_bb_b0 = { | |
10906 | 1, 6, tcfc_prty0_bb_b0_attn_idx, 0x2d05e4, 0x2d05f0, 0x2d05ec, 0x2d05e8 | |
10907 | }; | |
10908 | ||
10909 | static struct attn_hw_reg *tcfc_prty_bb_b0_regs[2] = { | |
10910 | &tcfc_prty1_bb_b0, &tcfc_prty0_bb_b0, | |
10911 | }; | |
10912 | ||
10913 | static const u16 tcfc_prty1_k2_attn_idx[2] = { | |
10914 | 0, 1, | |
10915 | }; | |
10916 | ||
10917 | static struct attn_hw_reg tcfc_prty1_k2 = { | |
10918 | 0, 2, tcfc_prty1_k2_attn_idx, 0x2d0200, 0x2d020c, 0x2d0208, 0x2d0204 | |
10919 | }; | |
10920 | ||
10921 | static const u16 tcfc_prty0_k2_attn_idx[6] = { | |
10922 | 4, 5, 6, 7, 8, 9, | |
10923 | }; | |
10924 | ||
10925 | static struct attn_hw_reg tcfc_prty0_k2 = { | |
10926 | 1, 6, tcfc_prty0_k2_attn_idx, 0x2d05e4, 0x2d05f0, 0x2d05ec, 0x2d05e8 | |
10927 | }; | |
10928 | ||
10929 | static struct attn_hw_reg *tcfc_prty_k2_regs[2] = { | |
10930 | &tcfc_prty1_k2, &tcfc_prty0_k2, | |
10931 | }; | |
10932 | ||
10933 | #ifdef ATTN_DESC | |
10934 | static const char *igu_int_attn_desc[11] = { | |
10935 | "igu_address_error", | |
10936 | "igu_ctrl_fifo_error_err", | |
10937 | "igu_pxp_req_length_too_big", | |
10938 | "igu_host_tries2access_prod_upd", | |
10939 | "igu_vf_tries2acc_attn_cmd", | |
10940 | "igu_mme_bigger_then_5", | |
10941 | "igu_sb_index_is_not_valid", | |
10942 | "igu_durin_int_read_with_simd_dis", | |
10943 | "igu_cmd_fid_not_match", | |
10944 | "igu_segment_access_invalid", | |
10945 | "igu_attn_prod_acc", | |
10946 | }; | |
10947 | #else | |
10948 | #define igu_int_attn_desc OSAL_NULL | |
10949 | #endif | |
10950 | ||
10951 | static const u16 igu_int0_bb_a0_attn_idx[11] = { | |
10952 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, | |
10953 | }; | |
10954 | ||
10955 | static struct attn_hw_reg igu_int0_bb_a0 = { | |
10956 | 0, 11, igu_int0_bb_a0_attn_idx, 0x180180, 0x18018c, 0x180188, 0x180184 | |
10957 | }; | |
10958 | ||
10959 | static struct attn_hw_reg *igu_int_bb_a0_regs[1] = { | |
10960 | &igu_int0_bb_a0, | |
10961 | }; | |
10962 | ||
10963 | static const u16 igu_int0_bb_b0_attn_idx[11] = { | |
10964 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, | |
10965 | }; | |
10966 | ||
10967 | static struct attn_hw_reg igu_int0_bb_b0 = { | |
10968 | 0, 11, igu_int0_bb_b0_attn_idx, 0x180180, 0x18018c, 0x180188, 0x180184 | |
10969 | }; | |
10970 | ||
10971 | static struct attn_hw_reg *igu_int_bb_b0_regs[1] = { | |
10972 | &igu_int0_bb_b0, | |
10973 | }; | |
10974 | ||
10975 | static const u16 igu_int0_k2_attn_idx[11] = { | |
10976 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, | |
10977 | }; | |
10978 | ||
10979 | static struct attn_hw_reg igu_int0_k2 = { | |
10980 | 0, 11, igu_int0_k2_attn_idx, 0x180180, 0x18018c, 0x180188, 0x180184 | |
10981 | }; | |
10982 | ||
10983 | static struct attn_hw_reg *igu_int_k2_regs[1] = { | |
10984 | &igu_int0_k2, | |
10985 | }; | |
10986 | ||
10987 | #ifdef ATTN_DESC | |
10988 | static const char *igu_prty_attn_desc[42] = { | |
10989 | "igu_cam_parity", | |
10990 | "igu_mem009_i_ecc_rf_int", | |
10991 | "igu_mem015_i_mem_prty", | |
10992 | "igu_mem016_i_mem_prty", | |
10993 | "igu_mem017_i_mem_prty", | |
10994 | "igu_mem018_i_mem_prty", | |
10995 | "igu_mem019_i_mem_prty", | |
10996 | "igu_mem001_i_mem_prty", | |
10997 | "igu_mem002_i_mem_prty_0", | |
10998 | "igu_mem002_i_mem_prty_1", | |
10999 | "igu_mem004_i_mem_prty_0", | |
11000 | "igu_mem004_i_mem_prty_1", | |
11001 | "igu_mem004_i_mem_prty_2", | |
11002 | "igu_mem003_i_mem_prty", | |
11003 | "igu_mem005_i_mem_prty", | |
11004 | "igu_mem006_i_mem_prty_0", | |
11005 | "igu_mem006_i_mem_prty_1", | |
11006 | "igu_mem008_i_mem_prty_0", | |
11007 | "igu_mem008_i_mem_prty_1", | |
11008 | "igu_mem008_i_mem_prty_2", | |
11009 | "igu_mem007_i_mem_prty", | |
11010 | "igu_mem010_i_mem_prty_0", | |
11011 | "igu_mem010_i_mem_prty_1", | |
11012 | "igu_mem012_i_mem_prty_0", | |
11013 | "igu_mem012_i_mem_prty_1", | |
11014 | "igu_mem012_i_mem_prty_2", | |
11015 | "igu_mem011_i_mem_prty", | |
11016 | "igu_mem013_i_mem_prty", | |
11017 | "igu_mem014_i_mem_prty", | |
11018 | "igu_mem020_i_mem_prty", | |
11019 | "igu_mem003_i_mem_prty_0", | |
11020 | "igu_mem003_i_mem_prty_1", | |
11021 | "igu_mem003_i_mem_prty_2", | |
11022 | "igu_mem002_i_mem_prty", | |
11023 | "igu_mem007_i_mem_prty_0", | |
11024 | "igu_mem007_i_mem_prty_1", | |
11025 | "igu_mem007_i_mem_prty_2", | |
11026 | "igu_mem006_i_mem_prty", | |
11027 | "igu_mem010_i_mem_prty_2", | |
11028 | "igu_mem010_i_mem_prty_3", | |
11029 | "igu_mem013_i_mem_prty_0", | |
11030 | "igu_mem013_i_mem_prty_1", | |
11031 | }; | |
11032 | #else | |
11033 | #define igu_prty_attn_desc OSAL_NULL | |
11034 | #endif | |
11035 | ||
11036 | static const u16 igu_prty0_bb_a0_attn_idx[1] = { | |
11037 | 0, | |
11038 | }; | |
11039 | ||
11040 | static struct attn_hw_reg igu_prty0_bb_a0 = { | |
11041 | 0, 1, igu_prty0_bb_a0_attn_idx, 0x180190, 0x18019c, 0x180198, 0x180194 | |
11042 | }; | |
11043 | ||
11044 | static const u16 igu_prty1_bb_a0_attn_idx[31] = { | |
11045 | 1, 3, 4, 5, 6, 7, 10, 11, 14, 17, 18, 21, 22, 23, 24, 25, 26, 28, 29, | |
11046 | 30, | |
11047 | 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, | |
11048 | }; | |
11049 | ||
11050 | static struct attn_hw_reg igu_prty1_bb_a0 = { | |
11051 | 1, 31, igu_prty1_bb_a0_attn_idx, 0x180200, 0x18020c, 0x180208, 0x180204 | |
11052 | }; | |
11053 | ||
11054 | static const u16 igu_prty2_bb_a0_attn_idx[1] = { | |
11055 | 2, | |
11056 | }; | |
11057 | ||
11058 | static struct attn_hw_reg igu_prty2_bb_a0 = { | |
11059 | 2, 1, igu_prty2_bb_a0_attn_idx, 0x180210, 0x18021c, 0x180218, 0x180214 | |
11060 | }; | |
11061 | ||
11062 | static struct attn_hw_reg *igu_prty_bb_a0_regs[3] = { | |
11063 | &igu_prty0_bb_a0, &igu_prty1_bb_a0, &igu_prty2_bb_a0, | |
11064 | }; | |
11065 | ||
11066 | static const u16 igu_prty0_bb_b0_attn_idx[1] = { | |
11067 | 0, | |
11068 | }; | |
11069 | ||
11070 | static struct attn_hw_reg igu_prty0_bb_b0 = { | |
11071 | 0, 1, igu_prty0_bb_b0_attn_idx, 0x180190, 0x18019c, 0x180198, 0x180194 | |
11072 | }; | |
11073 | ||
11074 | static const u16 igu_prty1_bb_b0_attn_idx[31] = { | |
11075 | 1, 3, 4, 5, 6, 7, 10, 11, 14, 17, 18, 21, 22, 23, 24, 25, 26, 28, 29, | |
11076 | 30, | |
11077 | 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, | |
11078 | }; | |
11079 | ||
11080 | static struct attn_hw_reg igu_prty1_bb_b0 = { | |
11081 | 1, 31, igu_prty1_bb_b0_attn_idx, 0x180200, 0x18020c, 0x180208, 0x180204 | |
11082 | }; | |
11083 | ||
11084 | static const u16 igu_prty2_bb_b0_attn_idx[1] = { | |
11085 | 2, | |
11086 | }; | |
11087 | ||
11088 | static struct attn_hw_reg igu_prty2_bb_b0 = { | |
11089 | 2, 1, igu_prty2_bb_b0_attn_idx, 0x180210, 0x18021c, 0x180218, 0x180214 | |
11090 | }; | |
11091 | ||
11092 | static struct attn_hw_reg *igu_prty_bb_b0_regs[3] = { | |
11093 | &igu_prty0_bb_b0, &igu_prty1_bb_b0, &igu_prty2_bb_b0, | |
11094 | }; | |
11095 | ||
11096 | static const u16 igu_prty0_k2_attn_idx[1] = { | |
11097 | 0, | |
11098 | }; | |
11099 | ||
11100 | static struct attn_hw_reg igu_prty0_k2 = { | |
11101 | 0, 1, igu_prty0_k2_attn_idx, 0x180190, 0x18019c, 0x180198, 0x180194 | |
11102 | }; | |
11103 | ||
11104 | static const u16 igu_prty1_k2_attn_idx[28] = { | |
11105 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, | |
11106 | 21, | |
11107 | 22, 23, 24, 25, 26, 27, 28, | |
11108 | }; | |
11109 | ||
11110 | static struct attn_hw_reg igu_prty1_k2 = { | |
11111 | 1, 28, igu_prty1_k2_attn_idx, 0x180200, 0x18020c, 0x180208, 0x180204 | |
11112 | }; | |
11113 | ||
11114 | static struct attn_hw_reg *igu_prty_k2_regs[2] = { | |
11115 | &igu_prty0_k2, &igu_prty1_k2, | |
11116 | }; | |
11117 | ||
11118 | #ifdef ATTN_DESC | |
11119 | static const char *cau_int_attn_desc[11] = { | |
11120 | "cau_address_error", | |
11121 | "cau_unauthorized_pxp_rd_cmd", | |
11122 | "cau_unauthorized_pxp_length_cmd", | |
11123 | "cau_pxp_sb_address_error", | |
11124 | "cau_pxp_pi_number_error", | |
11125 | "cau_cleanup_reg_sb_idx_error", | |
11126 | "cau_fsm_invalid_line", | |
11127 | "cau_cqe_fifo_err", | |
11128 | "cau_igu_wdata_fifo_err", | |
11129 | "cau_igu_req_fifo_err", | |
11130 | "cau_igu_cmd_fifo_err", | |
11131 | }; | |
11132 | #else | |
11133 | #define cau_int_attn_desc OSAL_NULL | |
11134 | #endif | |
11135 | ||
11136 | static const u16 cau_int0_bb_a0_attn_idx[11] = { | |
11137 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, | |
11138 | }; | |
11139 | ||
11140 | static struct attn_hw_reg cau_int0_bb_a0 = { | |
11141 | 0, 11, cau_int0_bb_a0_attn_idx, 0x1c00d4, 0x1c00d8, 0x1c00dc, 0x1c00e0 | |
11142 | }; | |
11143 | ||
11144 | static struct attn_hw_reg *cau_int_bb_a0_regs[1] = { | |
11145 | &cau_int0_bb_a0, | |
11146 | }; | |
11147 | ||
11148 | static const u16 cau_int0_bb_b0_attn_idx[11] = { | |
11149 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, | |
11150 | }; | |
11151 | ||
11152 | static struct attn_hw_reg cau_int0_bb_b0 = { | |
11153 | 0, 11, cau_int0_bb_b0_attn_idx, 0x1c00d4, 0x1c00d8, 0x1c00dc, 0x1c00e0 | |
11154 | }; | |
11155 | ||
11156 | static struct attn_hw_reg *cau_int_bb_b0_regs[1] = { | |
11157 | &cau_int0_bb_b0, | |
11158 | }; | |
11159 | ||
11160 | static const u16 cau_int0_k2_attn_idx[11] = { | |
11161 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, | |
11162 | }; | |
11163 | ||
11164 | static struct attn_hw_reg cau_int0_k2 = { | |
11165 | 0, 11, cau_int0_k2_attn_idx, 0x1c00d4, 0x1c00d8, 0x1c00dc, 0x1c00e0 | |
11166 | }; | |
11167 | ||
11168 | static struct attn_hw_reg *cau_int_k2_regs[1] = { | |
11169 | &cau_int0_k2, | |
11170 | }; | |
11171 | ||
11172 | #ifdef ATTN_DESC | |
11173 | static const char *cau_prty_attn_desc[15] = { | |
11174 | "cau_mem006_i_ecc_rf_int", | |
11175 | "cau_mem001_i_ecc_0_rf_int", | |
11176 | "cau_mem001_i_ecc_1_rf_int", | |
11177 | "cau_mem002_i_ecc_rf_int", | |
11178 | "cau_mem004_i_ecc_rf_int", | |
11179 | "cau_mem005_i_mem_prty", | |
11180 | "cau_mem007_i_mem_prty", | |
11181 | "cau_mem008_i_mem_prty", | |
11182 | "cau_mem009_i_mem_prty", | |
11183 | "cau_mem010_i_mem_prty", | |
11184 | "cau_mem011_i_mem_prty", | |
11185 | "cau_mem003_i_mem_prty_0", | |
11186 | "cau_mem003_i_mem_prty_1", | |
11187 | "cau_mem002_i_mem_prty", | |
11188 | "cau_mem004_i_mem_prty", | |
11189 | }; | |
11190 | #else | |
11191 | #define cau_prty_attn_desc OSAL_NULL | |
11192 | #endif | |
11193 | ||
11194 | static const u16 cau_prty1_bb_a0_attn_idx[13] = { | |
11195 | 0, 1, 2, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, | |
11196 | }; | |
11197 | ||
11198 | static struct attn_hw_reg cau_prty1_bb_a0 = { | |
11199 | 0, 13, cau_prty1_bb_a0_attn_idx, 0x1c0200, 0x1c020c, 0x1c0208, 0x1c0204 | |
11200 | }; | |
11201 | ||
11202 | static struct attn_hw_reg *cau_prty_bb_a0_regs[1] = { | |
11203 | &cau_prty1_bb_a0, | |
11204 | }; | |
11205 | ||
11206 | static const u16 cau_prty1_bb_b0_attn_idx[13] = { | |
11207 | 0, 1, 2, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, | |
11208 | }; | |
11209 | ||
11210 | static struct attn_hw_reg cau_prty1_bb_b0 = { | |
11211 | 0, 13, cau_prty1_bb_b0_attn_idx, 0x1c0200, 0x1c020c, 0x1c0208, 0x1c0204 | |
11212 | }; | |
11213 | ||
11214 | static struct attn_hw_reg *cau_prty_bb_b0_regs[1] = { | |
11215 | &cau_prty1_bb_b0, | |
11216 | }; | |
11217 | ||
11218 | static const u16 cau_prty1_k2_attn_idx[13] = { | |
11219 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, | |
11220 | }; | |
11221 | ||
11222 | static struct attn_hw_reg cau_prty1_k2 = { | |
11223 | 0, 13, cau_prty1_k2_attn_idx, 0x1c0200, 0x1c020c, 0x1c0208, 0x1c0204 | |
11224 | }; | |
11225 | ||
11226 | static struct attn_hw_reg *cau_prty_k2_regs[1] = { | |
11227 | &cau_prty1_k2, | |
11228 | }; | |
11229 | ||
11230 | #ifdef ATTN_DESC | |
11231 | static const char *umac_int_attn_desc[2] = { | |
11232 | "umac_address_error", | |
11233 | "umac_tx_overflow", | |
11234 | }; | |
11235 | #else | |
11236 | #define umac_int_attn_desc OSAL_NULL | |
11237 | #endif | |
11238 | ||
11239 | static const u16 umac_int0_k2_attn_idx[2] = { | |
11240 | 0, 1, | |
11241 | }; | |
11242 | ||
11243 | static struct attn_hw_reg umac_int0_k2 = { | |
11244 | 0, 2, umac_int0_k2_attn_idx, 0x51180, 0x5118c, 0x51188, 0x51184 | |
11245 | }; | |
11246 | ||
11247 | static struct attn_hw_reg *umac_int_k2_regs[1] = { | |
11248 | &umac_int0_k2, | |
11249 | }; | |
11250 | ||
11251 | #ifdef ATTN_DESC | |
11252 | static const char *dbg_int_attn_desc[1] = { | |
11253 | "dbg_address_error", | |
11254 | }; | |
11255 | #else | |
11256 | #define dbg_int_attn_desc OSAL_NULL | |
11257 | #endif | |
11258 | ||
11259 | static const u16 dbg_int0_bb_a0_attn_idx[1] = { | |
11260 | 0, | |
11261 | }; | |
11262 | ||
11263 | static struct attn_hw_reg dbg_int0_bb_a0 = { | |
11264 | 0, 1, dbg_int0_bb_a0_attn_idx, 0x10180, 0x1018c, 0x10188, 0x10184 | |
11265 | }; | |
11266 | ||
11267 | static struct attn_hw_reg *dbg_int_bb_a0_regs[1] = { | |
11268 | &dbg_int0_bb_a0, | |
11269 | }; | |
11270 | ||
11271 | static const u16 dbg_int0_bb_b0_attn_idx[1] = { | |
11272 | 0, | |
11273 | }; | |
11274 | ||
11275 | static struct attn_hw_reg dbg_int0_bb_b0 = { | |
11276 | 0, 1, dbg_int0_bb_b0_attn_idx, 0x10180, 0x1018c, 0x10188, 0x10184 | |
11277 | }; | |
11278 | ||
11279 | static struct attn_hw_reg *dbg_int_bb_b0_regs[1] = { | |
11280 | &dbg_int0_bb_b0, | |
11281 | }; | |
11282 | ||
11283 | static const u16 dbg_int0_k2_attn_idx[1] = { | |
11284 | 0, | |
11285 | }; | |
11286 | ||
11287 | static struct attn_hw_reg dbg_int0_k2 = { | |
11288 | 0, 1, dbg_int0_k2_attn_idx, 0x10180, 0x1018c, 0x10188, 0x10184 | |
11289 | }; | |
11290 | ||
11291 | static struct attn_hw_reg *dbg_int_k2_regs[1] = { | |
11292 | &dbg_int0_k2, | |
11293 | }; | |
11294 | ||
11295 | #ifdef ATTN_DESC | |
11296 | static const char *dbg_prty_attn_desc[1] = { | |
11297 | "dbg_mem001_i_mem_prty", | |
11298 | }; | |
11299 | #else | |
11300 | #define dbg_prty_attn_desc OSAL_NULL | |
11301 | #endif | |
11302 | ||
11303 | static const u16 dbg_prty1_bb_a0_attn_idx[1] = { | |
11304 | 0, | |
11305 | }; | |
11306 | ||
11307 | static struct attn_hw_reg dbg_prty1_bb_a0 = { | |
11308 | 0, 1, dbg_prty1_bb_a0_attn_idx, 0x10200, 0x1020c, 0x10208, 0x10204 | |
11309 | }; | |
11310 | ||
11311 | static struct attn_hw_reg *dbg_prty_bb_a0_regs[1] = { | |
11312 | &dbg_prty1_bb_a0, | |
11313 | }; | |
11314 | ||
11315 | static const u16 dbg_prty1_bb_b0_attn_idx[1] = { | |
11316 | 0, | |
11317 | }; | |
11318 | ||
11319 | static struct attn_hw_reg dbg_prty1_bb_b0 = { | |
11320 | 0, 1, dbg_prty1_bb_b0_attn_idx, 0x10200, 0x1020c, 0x10208, 0x10204 | |
11321 | }; | |
11322 | ||
11323 | static struct attn_hw_reg *dbg_prty_bb_b0_regs[1] = { | |
11324 | &dbg_prty1_bb_b0, | |
11325 | }; | |
11326 | ||
11327 | static const u16 dbg_prty1_k2_attn_idx[1] = { | |
11328 | 0, | |
11329 | }; | |
11330 | ||
11331 | static struct attn_hw_reg dbg_prty1_k2 = { | |
11332 | 0, 1, dbg_prty1_k2_attn_idx, 0x10200, 0x1020c, 0x10208, 0x10204 | |
11333 | }; | |
11334 | ||
11335 | static struct attn_hw_reg *dbg_prty_k2_regs[1] = { | |
11336 | &dbg_prty1_k2, | |
11337 | }; | |
11338 | ||
11339 | #ifdef ATTN_DESC | |
11340 | static const char *nig_int_attn_desc[196] = { | |
11341 | "nig_address_error", | |
11342 | "nig_debug_fifo_error", | |
11343 | "nig_dorq_fifo_error", | |
11344 | "nig_dbg_syncfifo_error_wr", | |
11345 | "nig_dorq_syncfifo_error_wr", | |
11346 | "nig_storm_syncfifo_error_wr", | |
11347 | "nig_dbgmux_syncfifo_error_wr", | |
11348 | "nig_msdm_syncfifo_error_wr", | |
11349 | "nig_tsdm_syncfifo_error_wr", | |
11350 | "nig_usdm_syncfifo_error_wr", | |
11351 | "nig_xsdm_syncfifo_error_wr", | |
11352 | "nig_ysdm_syncfifo_error_wr", | |
11353 | "nig_tx_sopq0_error", | |
11354 | "nig_tx_sopq1_error", | |
11355 | "nig_tx_sopq2_error", | |
11356 | "nig_tx_sopq3_error", | |
11357 | "nig_tx_sopq4_error", | |
11358 | "nig_tx_sopq5_error", | |
11359 | "nig_tx_sopq6_error", | |
11360 | "nig_tx_sopq7_error", | |
11361 | "nig_tx_sopq8_error", | |
11362 | "nig_tx_sopq9_error", | |
11363 | "nig_tx_sopq10_error", | |
11364 | "nig_tx_sopq11_error", | |
11365 | "nig_tx_sopq12_error", | |
11366 | "nig_tx_sopq13_error", | |
11367 | "nig_tx_sopq14_error", | |
11368 | "nig_tx_sopq15_error", | |
11369 | "nig_lb_sopq0_error", | |
11370 | "nig_lb_sopq1_error", | |
11371 | "nig_lb_sopq2_error", | |
11372 | "nig_lb_sopq3_error", | |
11373 | "nig_lb_sopq4_error", | |
11374 | "nig_lb_sopq5_error", | |
11375 | "nig_lb_sopq6_error", | |
11376 | "nig_lb_sopq7_error", | |
11377 | "nig_lb_sopq8_error", | |
11378 | "nig_lb_sopq9_error", | |
11379 | "nig_lb_sopq10_error", | |
11380 | "nig_lb_sopq11_error", | |
11381 | "nig_lb_sopq12_error", | |
11382 | "nig_lb_sopq13_error", | |
11383 | "nig_lb_sopq14_error", | |
11384 | "nig_lb_sopq15_error", | |
11385 | "nig_p0_purelb_sopq_error", | |
11386 | "nig_p0_rx_macfifo_error", | |
11387 | "nig_p0_tx_macfifo_error", | |
11388 | "nig_p0_tx_bmb_fifo_error", | |
11389 | "nig_p0_lb_bmb_fifo_error", | |
11390 | "nig_p0_tx_btb_fifo_error", | |
11391 | "nig_p0_lb_btb_fifo_error", | |
11392 | "nig_p0_rx_llh_dfifo_error", | |
11393 | "nig_p0_tx_llh_dfifo_error", | |
11394 | "nig_p0_lb_llh_dfifo_error", | |
11395 | "nig_p0_rx_llh_hfifo_error", | |
11396 | "nig_p0_tx_llh_hfifo_error", | |
11397 | "nig_p0_lb_llh_hfifo_error", | |
11398 | "nig_p0_rx_llh_rfifo_error", | |
11399 | "nig_p0_tx_llh_rfifo_error", | |
11400 | "nig_p0_lb_llh_rfifo_error", | |
11401 | "nig_p0_storm_fifo_error", | |
11402 | "nig_p0_storm_dscr_fifo_error", | |
11403 | "nig_p0_tx_gnt_fifo_error", | |
11404 | "nig_p0_lb_gnt_fifo_error", | |
11405 | "nig_p0_tx_pause_too_long_int", | |
11406 | "nig_p0_tc0_pause_too_long_int", | |
11407 | "nig_p0_tc1_pause_too_long_int", | |
11408 | "nig_p0_tc2_pause_too_long_int", | |
11409 | "nig_p0_tc3_pause_too_long_int", | |
11410 | "nig_p0_tc4_pause_too_long_int", | |
11411 | "nig_p0_tc5_pause_too_long_int", | |
11412 | "nig_p0_tc6_pause_too_long_int", | |
11413 | "nig_p0_tc7_pause_too_long_int", | |
11414 | "nig_p0_lb_tc0_pause_too_long_int", | |
11415 | "nig_p0_lb_tc1_pause_too_long_int", | |
11416 | "nig_p0_lb_tc2_pause_too_long_int", | |
11417 | "nig_p0_lb_tc3_pause_too_long_int", | |
11418 | "nig_p0_lb_tc4_pause_too_long_int", | |
11419 | "nig_p0_lb_tc5_pause_too_long_int", | |
11420 | "nig_p0_lb_tc6_pause_too_long_int", | |
11421 | "nig_p0_lb_tc7_pause_too_long_int", | |
11422 | "nig_p0_lb_tc8_pause_too_long_int", | |
11423 | "nig_p1_purelb_sopq_error", | |
11424 | "nig_p1_rx_macfifo_error", | |
11425 | "nig_p1_tx_macfifo_error", | |
11426 | "nig_p1_tx_bmb_fifo_error", | |
11427 | "nig_p1_lb_bmb_fifo_error", | |
11428 | "nig_p1_tx_btb_fifo_error", | |
11429 | "nig_p1_lb_btb_fifo_error", | |
11430 | "nig_p1_rx_llh_dfifo_error", | |
11431 | "nig_p1_tx_llh_dfifo_error", | |
11432 | "nig_p1_lb_llh_dfifo_error", | |
11433 | "nig_p1_rx_llh_hfifo_error", | |
11434 | "nig_p1_tx_llh_hfifo_error", | |
11435 | "nig_p1_lb_llh_hfifo_error", | |
11436 | "nig_p1_rx_llh_rfifo_error", | |
11437 | "nig_p1_tx_llh_rfifo_error", | |
11438 | "nig_p1_lb_llh_rfifo_error", | |
11439 | "nig_p1_storm_fifo_error", | |
11440 | "nig_p1_storm_dscr_fifo_error", | |
11441 | "nig_p1_tx_gnt_fifo_error", | |
11442 | "nig_p1_lb_gnt_fifo_error", | |
11443 | "nig_p1_tx_pause_too_long_int", | |
11444 | "nig_p1_tc0_pause_too_long_int", | |
11445 | "nig_p1_tc1_pause_too_long_int", | |
11446 | "nig_p1_tc2_pause_too_long_int", | |
11447 | "nig_p1_tc3_pause_too_long_int", | |
11448 | "nig_p1_tc4_pause_too_long_int", | |
11449 | "nig_p1_tc5_pause_too_long_int", | |
11450 | "nig_p1_tc6_pause_too_long_int", | |
11451 | "nig_p1_tc7_pause_too_long_int", | |
11452 | "nig_p1_lb_tc0_pause_too_long_int", | |
11453 | "nig_p1_lb_tc1_pause_too_long_int", | |
11454 | "nig_p1_lb_tc2_pause_too_long_int", | |
11455 | "nig_p1_lb_tc3_pause_too_long_int", | |
11456 | "nig_p1_lb_tc4_pause_too_long_int", | |
11457 | "nig_p1_lb_tc5_pause_too_long_int", | |
11458 | "nig_p1_lb_tc6_pause_too_long_int", | |
11459 | "nig_p1_lb_tc7_pause_too_long_int", | |
11460 | "nig_p1_lb_tc8_pause_too_long_int", | |
11461 | "nig_p2_purelb_sopq_error", | |
11462 | "nig_p2_rx_macfifo_error", | |
11463 | "nig_p2_tx_macfifo_error", | |
11464 | "nig_p2_tx_bmb_fifo_error", | |
11465 | "nig_p2_lb_bmb_fifo_error", | |
11466 | "nig_p2_tx_btb_fifo_error", | |
11467 | "nig_p2_lb_btb_fifo_error", | |
11468 | "nig_p2_rx_llh_dfifo_error", | |
11469 | "nig_p2_tx_llh_dfifo_error", | |
11470 | "nig_p2_lb_llh_dfifo_error", | |
11471 | "nig_p2_rx_llh_hfifo_error", | |
11472 | "nig_p2_tx_llh_hfifo_error", | |
11473 | "nig_p2_lb_llh_hfifo_error", | |
11474 | "nig_p2_rx_llh_rfifo_error", | |
11475 | "nig_p2_tx_llh_rfifo_error", | |
11476 | "nig_p2_lb_llh_rfifo_error", | |
11477 | "nig_p2_storm_fifo_error", | |
11478 | "nig_p2_storm_dscr_fifo_error", | |
11479 | "nig_p2_tx_gnt_fifo_error", | |
11480 | "nig_p2_lb_gnt_fifo_error", | |
11481 | "nig_p2_tx_pause_too_long_int", | |
11482 | "nig_p2_tc0_pause_too_long_int", | |
11483 | "nig_p2_tc1_pause_too_long_int", | |
11484 | "nig_p2_tc2_pause_too_long_int", | |
11485 | "nig_p2_tc3_pause_too_long_int", | |
11486 | "nig_p2_tc4_pause_too_long_int", | |
11487 | "nig_p2_tc5_pause_too_long_int", | |
11488 | "nig_p2_tc6_pause_too_long_int", | |
11489 | "nig_p2_tc7_pause_too_long_int", | |
11490 | "nig_p2_lb_tc0_pause_too_long_int", | |
11491 | "nig_p2_lb_tc1_pause_too_long_int", | |
11492 | "nig_p2_lb_tc2_pause_too_long_int", | |
11493 | "nig_p2_lb_tc3_pause_too_long_int", | |
11494 | "nig_p2_lb_tc4_pause_too_long_int", | |
11495 | "nig_p2_lb_tc5_pause_too_long_int", | |
11496 | "nig_p2_lb_tc6_pause_too_long_int", | |
11497 | "nig_p2_lb_tc7_pause_too_long_int", | |
11498 | "nig_p2_lb_tc8_pause_too_long_int", | |
11499 | "nig_p3_purelb_sopq_error", | |
11500 | "nig_p3_rx_macfifo_error", | |
11501 | "nig_p3_tx_macfifo_error", | |
11502 | "nig_p3_tx_bmb_fifo_error", | |
11503 | "nig_p3_lb_bmb_fifo_error", | |
11504 | "nig_p3_tx_btb_fifo_error", | |
11505 | "nig_p3_lb_btb_fifo_error", | |
11506 | "nig_p3_rx_llh_dfifo_error", | |
11507 | "nig_p3_tx_llh_dfifo_error", | |
11508 | "nig_p3_lb_llh_dfifo_error", | |
11509 | "nig_p3_rx_llh_hfifo_error", | |
11510 | "nig_p3_tx_llh_hfifo_error", | |
11511 | "nig_p3_lb_llh_hfifo_error", | |
11512 | "nig_p3_rx_llh_rfifo_error", | |
11513 | "nig_p3_tx_llh_rfifo_error", | |
11514 | "nig_p3_lb_llh_rfifo_error", | |
11515 | "nig_p3_storm_fifo_error", | |
11516 | "nig_p3_storm_dscr_fifo_error", | |
11517 | "nig_p3_tx_gnt_fifo_error", | |
11518 | "nig_p3_lb_gnt_fifo_error", | |
11519 | "nig_p3_tx_pause_too_long_int", | |
11520 | "nig_p3_tc0_pause_too_long_int", | |
11521 | "nig_p3_tc1_pause_too_long_int", | |
11522 | "nig_p3_tc2_pause_too_long_int", | |
11523 | "nig_p3_tc3_pause_too_long_int", | |
11524 | "nig_p3_tc4_pause_too_long_int", | |
11525 | "nig_p3_tc5_pause_too_long_int", | |
11526 | "nig_p3_tc6_pause_too_long_int", | |
11527 | "nig_p3_tc7_pause_too_long_int", | |
11528 | "nig_p3_lb_tc0_pause_too_long_int", | |
11529 | "nig_p3_lb_tc1_pause_too_long_int", | |
11530 | "nig_p3_lb_tc2_pause_too_long_int", | |
11531 | "nig_p3_lb_tc3_pause_too_long_int", | |
11532 | "nig_p3_lb_tc4_pause_too_long_int", | |
11533 | "nig_p3_lb_tc5_pause_too_long_int", | |
11534 | "nig_p3_lb_tc6_pause_too_long_int", | |
11535 | "nig_p3_lb_tc7_pause_too_long_int", | |
11536 | "nig_p3_lb_tc8_pause_too_long_int", | |
11537 | }; | |
11538 | #else | |
11539 | #define nig_int_attn_desc OSAL_NULL | |
11540 | #endif | |
11541 | ||
11542 | static const u16 nig_int0_bb_a0_attn_idx[12] = { | |
11543 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, | |
11544 | }; | |
11545 | ||
11546 | static struct attn_hw_reg nig_int0_bb_a0 = { | |
11547 | 0, 12, nig_int0_bb_a0_attn_idx, 0x500040, 0x50004c, 0x500048, 0x500044 | |
11548 | }; | |
11549 | ||
11550 | static const u16 nig_int1_bb_a0_attn_idx[32] = { | |
11551 | 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, | |
11552 | 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, | |
11553 | }; | |
11554 | ||
11555 | static struct attn_hw_reg nig_int1_bb_a0 = { | |
11556 | 1, 32, nig_int1_bb_a0_attn_idx, 0x500050, 0x50005c, 0x500058, 0x500054 | |
11557 | }; | |
11558 | ||
11559 | static const u16 nig_int2_bb_a0_attn_idx[20] = { | |
11560 | 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, | |
11561 | 62, 63, | |
11562 | }; | |
11563 | ||
11564 | static struct attn_hw_reg nig_int2_bb_a0 = { | |
11565 | 2, 20, nig_int2_bb_a0_attn_idx, 0x500060, 0x50006c, 0x500068, 0x500064 | |
11566 | }; | |
11567 | ||
11568 | static const u16 nig_int3_bb_a0_attn_idx[18] = { | |
11569 | 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, | |
11570 | }; | |
11571 | ||
11572 | static struct attn_hw_reg nig_int3_bb_a0 = { | |
11573 | 3, 18, nig_int3_bb_a0_attn_idx, 0x500070, 0x50007c, 0x500078, 0x500074 | |
11574 | }; | |
11575 | ||
11576 | static const u16 nig_int4_bb_a0_attn_idx[20] = { | |
11577 | 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, | |
11578 | 100, 101, | |
11579 | }; | |
11580 | ||
11581 | static struct attn_hw_reg nig_int4_bb_a0 = { | |
11582 | 4, 20, nig_int4_bb_a0_attn_idx, 0x500080, 0x50008c, 0x500088, 0x500084 | |
11583 | }; | |
11584 | ||
11585 | static const u16 nig_int5_bb_a0_attn_idx[18] = { | |
11586 | 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, | |
11587 | 116, | |
11588 | 117, 118, 119, | |
11589 | }; | |
11590 | ||
11591 | static struct attn_hw_reg nig_int5_bb_a0 = { | |
11592 | 5, 18, nig_int5_bb_a0_attn_idx, 0x500090, 0x50009c, 0x500098, 0x500094 | |
11593 | }; | |
11594 | ||
11595 | static struct attn_hw_reg *nig_int_bb_a0_regs[6] = { | |
11596 | &nig_int0_bb_a0, &nig_int1_bb_a0, &nig_int2_bb_a0, &nig_int3_bb_a0, | |
11597 | &nig_int4_bb_a0, &nig_int5_bb_a0, | |
11598 | }; | |
11599 | ||
11600 | static const u16 nig_int0_bb_b0_attn_idx[12] = { | |
11601 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, | |
11602 | }; | |
11603 | ||
11604 | static struct attn_hw_reg nig_int0_bb_b0 = { | |
11605 | 0, 12, nig_int0_bb_b0_attn_idx, 0x500040, 0x50004c, 0x500048, 0x500044 | |
11606 | }; | |
11607 | ||
11608 | static const u16 nig_int1_bb_b0_attn_idx[32] = { | |
11609 | 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, | |
11610 | 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, | |
11611 | }; | |
11612 | ||
11613 | static struct attn_hw_reg nig_int1_bb_b0 = { | |
11614 | 1, 32, nig_int1_bb_b0_attn_idx, 0x500050, 0x50005c, 0x500058, 0x500054 | |
11615 | }; | |
11616 | ||
11617 | static const u16 nig_int2_bb_b0_attn_idx[20] = { | |
11618 | 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, | |
11619 | 62, 63, | |
11620 | }; | |
11621 | ||
11622 | static struct attn_hw_reg nig_int2_bb_b0 = { | |
11623 | 2, 20, nig_int2_bb_b0_attn_idx, 0x500060, 0x50006c, 0x500068, 0x500064 | |
11624 | }; | |
11625 | ||
11626 | static const u16 nig_int3_bb_b0_attn_idx[18] = { | |
11627 | 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, | |
11628 | }; | |
11629 | ||
11630 | static struct attn_hw_reg nig_int3_bb_b0 = { | |
11631 | 3, 18, nig_int3_bb_b0_attn_idx, 0x500070, 0x50007c, 0x500078, 0x500074 | |
11632 | }; | |
11633 | ||
11634 | static const u16 nig_int4_bb_b0_attn_idx[20] = { | |
11635 | 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, | |
11636 | 100, 101, | |
11637 | }; | |
11638 | ||
11639 | static struct attn_hw_reg nig_int4_bb_b0 = { | |
11640 | 4, 20, nig_int4_bb_b0_attn_idx, 0x500080, 0x50008c, 0x500088, 0x500084 | |
11641 | }; | |
11642 | ||
11643 | static const u16 nig_int5_bb_b0_attn_idx[18] = { | |
11644 | 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, | |
11645 | 116, | |
11646 | 117, 118, 119, | |
11647 | }; | |
11648 | ||
11649 | static struct attn_hw_reg nig_int5_bb_b0 = { | |
11650 | 5, 18, nig_int5_bb_b0_attn_idx, 0x500090, 0x50009c, 0x500098, 0x500094 | |
11651 | }; | |
11652 | ||
11653 | static struct attn_hw_reg *nig_int_bb_b0_regs[6] = { | |
11654 | &nig_int0_bb_b0, &nig_int1_bb_b0, &nig_int2_bb_b0, &nig_int3_bb_b0, | |
11655 | &nig_int4_bb_b0, &nig_int5_bb_b0, | |
11656 | }; | |
11657 | ||
11658 | static const u16 nig_int0_k2_attn_idx[12] = { | |
11659 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, | |
11660 | }; | |
11661 | ||
11662 | static struct attn_hw_reg nig_int0_k2 = { | |
11663 | 0, 12, nig_int0_k2_attn_idx, 0x500040, 0x50004c, 0x500048, 0x500044 | |
11664 | }; | |
11665 | ||
11666 | static const u16 nig_int1_k2_attn_idx[32] = { | |
11667 | 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, | |
11668 | 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, | |
11669 | }; | |
11670 | ||
11671 | static struct attn_hw_reg nig_int1_k2 = { | |
11672 | 1, 32, nig_int1_k2_attn_idx, 0x500050, 0x50005c, 0x500058, 0x500054 | |
11673 | }; | |
11674 | ||
11675 | static const u16 nig_int2_k2_attn_idx[20] = { | |
11676 | 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, | |
11677 | 62, 63, | |
11678 | }; | |
11679 | ||
11680 | static struct attn_hw_reg nig_int2_k2 = { | |
11681 | 2, 20, nig_int2_k2_attn_idx, 0x500060, 0x50006c, 0x500068, 0x500064 | |
11682 | }; | |
11683 | ||
11684 | static const u16 nig_int3_k2_attn_idx[18] = { | |
11685 | 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, | |
11686 | }; | |
11687 | ||
11688 | static struct attn_hw_reg nig_int3_k2 = { | |
11689 | 3, 18, nig_int3_k2_attn_idx, 0x500070, 0x50007c, 0x500078, 0x500074 | |
11690 | }; | |
11691 | ||
11692 | static const u16 nig_int4_k2_attn_idx[20] = { | |
11693 | 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, | |
11694 | 100, 101, | |
11695 | }; | |
11696 | ||
11697 | static struct attn_hw_reg nig_int4_k2 = { | |
11698 | 4, 20, nig_int4_k2_attn_idx, 0x500080, 0x50008c, 0x500088, 0x500084 | |
11699 | }; | |
11700 | ||
11701 | static const u16 nig_int5_k2_attn_idx[18] = { | |
11702 | 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, | |
11703 | 116, | |
11704 | 117, 118, 119, | |
11705 | }; | |
11706 | ||
11707 | static struct attn_hw_reg nig_int5_k2 = { | |
11708 | 5, 18, nig_int5_k2_attn_idx, 0x500090, 0x50009c, 0x500098, 0x500094 | |
11709 | }; | |
11710 | ||
11711 | static const u16 nig_int6_k2_attn_idx[20] = { | |
11712 | 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, | |
11713 | 134, | |
11714 | 135, 136, 137, 138, 139, | |
11715 | }; | |
11716 | ||
11717 | static struct attn_hw_reg nig_int6_k2 = { | |
11718 | 6, 20, nig_int6_k2_attn_idx, 0x5000a0, 0x5000ac, 0x5000a8, 0x5000a4 | |
11719 | }; | |
11720 | ||
11721 | static const u16 nig_int7_k2_attn_idx[18] = { | |
11722 | 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, | |
11723 | 154, | |
11724 | 155, 156, 157, | |
11725 | }; | |
11726 | ||
11727 | static struct attn_hw_reg nig_int7_k2 = { | |
11728 | 7, 18, nig_int7_k2_attn_idx, 0x5000b0, 0x5000bc, 0x5000b8, 0x5000b4 | |
11729 | }; | |
11730 | ||
11731 | static const u16 nig_int8_k2_attn_idx[20] = { | |
11732 | 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, | |
11733 | 172, | |
11734 | 173, 174, 175, 176, 177, | |
11735 | }; | |
11736 | ||
11737 | static struct attn_hw_reg nig_int8_k2 = { | |
11738 | 8, 20, nig_int8_k2_attn_idx, 0x5000c0, 0x5000cc, 0x5000c8, 0x5000c4 | |
11739 | }; | |
11740 | ||
11741 | static const u16 nig_int9_k2_attn_idx[18] = { | |
11742 | 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, | |
11743 | 192, | |
11744 | 193, 194, 195, | |
11745 | }; | |
11746 | ||
11747 | static struct attn_hw_reg nig_int9_k2 = { | |
11748 | 9, 18, nig_int9_k2_attn_idx, 0x5000d0, 0x5000dc, 0x5000d8, 0x5000d4 | |
11749 | }; | |
11750 | ||
11751 | static struct attn_hw_reg *nig_int_k2_regs[10] = { | |
11752 | &nig_int0_k2, &nig_int1_k2, &nig_int2_k2, &nig_int3_k2, &nig_int4_k2, | |
11753 | &nig_int5_k2, &nig_int6_k2, &nig_int7_k2, &nig_int8_k2, &nig_int9_k2, | |
11754 | }; | |
11755 | ||
11756 | #ifdef ATTN_DESC | |
11757 | static const char *nig_prty_attn_desc[113] = { | |
11758 | "nig_datapath_parity_error", | |
11759 | "nig_mem107_i_mem_prty", | |
11760 | "nig_mem103_i_mem_prty", | |
11761 | "nig_mem104_i_mem_prty", | |
11762 | "nig_mem105_i_mem_prty", | |
11763 | "nig_mem106_i_mem_prty", | |
11764 | "nig_mem072_i_mem_prty", | |
11765 | "nig_mem071_i_mem_prty", | |
11766 | "nig_mem074_i_mem_prty", | |
11767 | "nig_mem073_i_mem_prty", | |
11768 | "nig_mem076_i_mem_prty", | |
11769 | "nig_mem075_i_mem_prty", | |
11770 | "nig_mem078_i_mem_prty", | |
11771 | "nig_mem077_i_mem_prty", | |
11772 | "nig_mem055_i_mem_prty", | |
11773 | "nig_mem062_i_mem_prty", | |
11774 | "nig_mem063_i_mem_prty", | |
11775 | "nig_mem064_i_mem_prty", | |
11776 | "nig_mem065_i_mem_prty", | |
11777 | "nig_mem066_i_mem_prty", | |
11778 | "nig_mem067_i_mem_prty", | |
11779 | "nig_mem068_i_mem_prty", | |
11780 | "nig_mem069_i_mem_prty", | |
11781 | "nig_mem070_i_mem_prty", | |
11782 | "nig_mem056_i_mem_prty", | |
11783 | "nig_mem057_i_mem_prty", | |
11784 | "nig_mem058_i_mem_prty", | |
11785 | "nig_mem059_i_mem_prty", | |
11786 | "nig_mem060_i_mem_prty", | |
11787 | "nig_mem061_i_mem_prty", | |
11788 | "nig_mem035_i_mem_prty", | |
11789 | "nig_mem046_i_mem_prty", | |
11790 | "nig_mem051_i_mem_prty", | |
11791 | "nig_mem052_i_mem_prty", | |
11792 | "nig_mem090_i_mem_prty", | |
11793 | "nig_mem089_i_mem_prty", | |
11794 | "nig_mem092_i_mem_prty", | |
11795 | "nig_mem091_i_mem_prty", | |
11796 | "nig_mem109_i_mem_prty", | |
11797 | "nig_mem110_i_mem_prty", | |
11798 | "nig_mem001_i_mem_prty", | |
11799 | "nig_mem008_i_mem_prty", | |
11800 | "nig_mem009_i_mem_prty", | |
11801 | "nig_mem010_i_mem_prty", | |
11802 | "nig_mem011_i_mem_prty", | |
11803 | "nig_mem012_i_mem_prty", | |
11804 | "nig_mem013_i_mem_prty", | |
11805 | "nig_mem014_i_mem_prty", | |
11806 | "nig_mem015_i_mem_prty", | |
11807 | "nig_mem016_i_mem_prty", | |
11808 | "nig_mem002_i_mem_prty", | |
11809 | "nig_mem003_i_mem_prty", | |
11810 | "nig_mem004_i_mem_prty", | |
11811 | "nig_mem005_i_mem_prty", | |
11812 | "nig_mem006_i_mem_prty", | |
11813 | "nig_mem007_i_mem_prty", | |
11814 | "nig_mem080_i_mem_prty", | |
11815 | "nig_mem081_i_mem_prty", | |
11816 | "nig_mem082_i_mem_prty", | |
11817 | "nig_mem083_i_mem_prty", | |
11818 | "nig_mem048_i_mem_prty", | |
11819 | "nig_mem049_i_mem_prty", | |
11820 | "nig_mem102_i_mem_prty", | |
11821 | "nig_mem087_i_mem_prty", | |
11822 | "nig_mem086_i_mem_prty", | |
11823 | "nig_mem088_i_mem_prty", | |
11824 | "nig_mem079_i_mem_prty", | |
11825 | "nig_mem047_i_mem_prty", | |
11826 | "nig_mem050_i_mem_prty", | |
11827 | "nig_mem053_i_mem_prty", | |
11828 | "nig_mem054_i_mem_prty", | |
11829 | "nig_mem036_i_mem_prty", | |
11830 | "nig_mem037_i_mem_prty", | |
11831 | "nig_mem038_i_mem_prty", | |
11832 | "nig_mem039_i_mem_prty", | |
11833 | "nig_mem040_i_mem_prty", | |
11834 | "nig_mem041_i_mem_prty", | |
11835 | "nig_mem042_i_mem_prty", | |
11836 | "nig_mem043_i_mem_prty", | |
11837 | "nig_mem044_i_mem_prty", | |
11838 | "nig_mem045_i_mem_prty", | |
11839 | "nig_mem093_i_mem_prty", | |
11840 | "nig_mem094_i_mem_prty", | |
11841 | "nig_mem027_i_mem_prty", | |
11842 | "nig_mem028_i_mem_prty", | |
11843 | "nig_mem029_i_mem_prty", | |
11844 | "nig_mem030_i_mem_prty", | |
11845 | "nig_mem017_i_mem_prty", | |
11846 | "nig_mem018_i_mem_prty", | |
11847 | "nig_mem095_i_mem_prty", | |
11848 | "nig_mem084_i_mem_prty", | |
11849 | "nig_mem085_i_mem_prty", | |
11850 | "nig_mem099_i_mem_prty", | |
11851 | "nig_mem100_i_mem_prty", | |
11852 | "nig_mem096_i_mem_prty", | |
11853 | "nig_mem097_i_mem_prty", | |
11854 | "nig_mem098_i_mem_prty", | |
11855 | "nig_mem031_i_mem_prty", | |
11856 | "nig_mem032_i_mem_prty", | |
11857 | "nig_mem033_i_mem_prty", | |
11858 | "nig_mem034_i_mem_prty", | |
11859 | "nig_mem019_i_mem_prty", | |
11860 | "nig_mem020_i_mem_prty", | |
11861 | "nig_mem021_i_mem_prty", | |
11862 | "nig_mem022_i_mem_prty", | |
11863 | "nig_mem101_i_mem_prty", | |
11864 | "nig_mem023_i_mem_prty", | |
11865 | "nig_mem024_i_mem_prty", | |
11866 | "nig_mem025_i_mem_prty", | |
11867 | "nig_mem026_i_mem_prty", | |
11868 | "nig_mem108_i_mem_prty", | |
11869 | "nig_mem031_ext_i_mem_prty", | |
11870 | "nig_mem034_ext_i_mem_prty", | |
11871 | }; | |
11872 | #else | |
11873 | #define nig_prty_attn_desc OSAL_NULL | |
11874 | #endif | |
11875 | ||
11876 | static const u16 nig_prty1_bb_a0_attn_idx[31] = { | |
11877 | 1, 2, 5, 12, 13, 23, 35, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, | |
11878 | 52, 53, 54, 55, 56, 60, 61, 62, 63, 64, 65, 66, | |
11879 | }; | |
11880 | ||
11881 | static struct attn_hw_reg nig_prty1_bb_a0 = { | |
11882 | 0, 31, nig_prty1_bb_a0_attn_idx, 0x500200, 0x50020c, 0x500208, 0x500204 | |
11883 | }; | |
11884 | ||
11885 | static const u16 nig_prty2_bb_a0_attn_idx[31] = { | |
11886 | 33, 69, 70, 90, 91, 8, 11, 10, 14, 17, 18, 19, 20, 21, 22, 7, 6, 24, 25, | |
11887 | 26, 27, 28, 29, 15, 16, 57, 58, 59, 9, 94, 95, | |
11888 | }; | |
11889 | ||
11890 | static struct attn_hw_reg nig_prty2_bb_a0 = { | |
11891 | 1, 31, nig_prty2_bb_a0_attn_idx, 0x500210, 0x50021c, 0x500218, 0x500214 | |
11892 | }; | |
11893 | ||
11894 | static const u16 nig_prty3_bb_a0_attn_idx[31] = { | |
11895 | 96, 97, 98, 103, 104, 92, 93, 105, 106, 107, 108, 109, 80, 31, 67, 83, | |
11896 | 84, | |
11897 | 3, 68, 85, 86, 89, 77, 78, 79, 4, 32, 36, 81, 82, 87, | |
11898 | }; | |
11899 | ||
11900 | static struct attn_hw_reg nig_prty3_bb_a0 = { | |
11901 | 2, 31, nig_prty3_bb_a0_attn_idx, 0x500220, 0x50022c, 0x500228, 0x500224 | |
11902 | }; | |
11903 | ||
11904 | static const u16 nig_prty4_bb_a0_attn_idx[14] = { | |
11905 | 88, 101, 102, 75, 71, 74, 76, 73, 72, 34, 37, 99, 30, 100, | |
11906 | }; | |
11907 | ||
11908 | static struct attn_hw_reg nig_prty4_bb_a0 = { | |
11909 | 3, 14, nig_prty4_bb_a0_attn_idx, 0x500230, 0x50023c, 0x500238, 0x500234 | |
11910 | }; | |
11911 | ||
11912 | static struct attn_hw_reg *nig_prty_bb_a0_regs[4] = { | |
11913 | &nig_prty1_bb_a0, &nig_prty2_bb_a0, &nig_prty3_bb_a0, &nig_prty4_bb_a0, | |
11914 | }; | |
11915 | ||
11916 | static const u16 nig_prty0_bb_b0_attn_idx[1] = { | |
11917 | 0, | |
11918 | }; | |
11919 | ||
11920 | static struct attn_hw_reg nig_prty0_bb_b0 = { | |
11921 | 0, 1, nig_prty0_bb_b0_attn_idx, 0x5000a0, 0x5000ac, 0x5000a8, 0x5000a4 | |
11922 | }; | |
11923 | ||
11924 | static const u16 nig_prty1_bb_b0_attn_idx[31] = { | |
11925 | 4, 5, 9, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, | |
11926 | 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, | |
11927 | }; | |
11928 | ||
11929 | static struct attn_hw_reg nig_prty1_bb_b0 = { | |
11930 | 1, 31, nig_prty1_bb_b0_attn_idx, 0x500200, 0x50020c, 0x500208, 0x500204 | |
11931 | }; | |
11932 | ||
11933 | static const u16 nig_prty2_bb_b0_attn_idx[31] = { | |
11934 | 90, 91, 64, 63, 65, 8, 11, 10, 13, 12, 66, 14, 17, 18, 19, 20, 21, 22, | |
11935 | 23, | |
11936 | 7, 6, 24, 25, 26, 27, 28, 29, 15, 16, 92, 93, | |
11937 | }; | |
11938 | ||
11939 | static struct attn_hw_reg nig_prty2_bb_b0 = { | |
11940 | 2, 31, nig_prty2_bb_b0_attn_idx, 0x500210, 0x50021c, 0x500218, 0x500214 | |
11941 | }; | |
11942 | ||
11943 | static const u16 nig_prty3_bb_b0_attn_idx[31] = { | |
11944 | 94, 95, 96, 97, 99, 100, 103, 104, 105, 62, 108, 109, 80, 31, 1, 67, 60, | |
11945 | 69, 83, 84, 2, 3, 110, 61, 68, 70, 85, 86, 111, 112, 89, | |
11946 | }; | |
11947 | ||
11948 | static struct attn_hw_reg nig_prty3_bb_b0 = { | |
11949 | 3, 31, nig_prty3_bb_b0_attn_idx, 0x500220, 0x50022c, 0x500228, 0x500224 | |
11950 | }; | |
11951 | ||
11952 | static const u16 nig_prty4_bb_b0_attn_idx[17] = { | |
11953 | 106, 107, 87, 88, 81, 82, 101, 102, 75, 71, 74, 76, 77, 78, 79, 73, 72, | |
11954 | }; | |
11955 | ||
11956 | static struct attn_hw_reg nig_prty4_bb_b0 = { | |
11957 | 4, 17, nig_prty4_bb_b0_attn_idx, 0x500230, 0x50023c, 0x500238, 0x500234 | |
11958 | }; | |
11959 | ||
11960 | static struct attn_hw_reg *nig_prty_bb_b0_regs[5] = { | |
11961 | &nig_prty0_bb_b0, &nig_prty1_bb_b0, &nig_prty2_bb_b0, &nig_prty3_bb_b0, | |
11962 | &nig_prty4_bb_b0, | |
11963 | }; | |
11964 | ||
11965 | static const u16 nig_prty0_k2_attn_idx[1] = { | |
11966 | 0, | |
11967 | }; | |
11968 | ||
11969 | static struct attn_hw_reg nig_prty0_k2 = { | |
11970 | 0, 1, nig_prty0_k2_attn_idx, 0x5000e0, 0x5000ec, 0x5000e8, 0x5000e4 | |
11971 | }; | |
11972 | ||
11973 | static const u16 nig_prty1_k2_attn_idx[31] = { | |
11974 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, | |
11975 | 21, | |
11976 | 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
11977 | }; | |
11978 | ||
11979 | static struct attn_hw_reg nig_prty1_k2 = { | |
11980 | 1, 31, nig_prty1_k2_attn_idx, 0x500200, 0x50020c, 0x500208, 0x500204 | |
11981 | }; | |
11982 | ||
11983 | static const u16 nig_prty2_k2_attn_idx[31] = { | |
11984 | 67, 60, 61, 68, 32, 33, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, | |
11985 | 37, 36, 81, 82, 83, 84, 85, 86, 48, 49, 87, 88, 89, | |
11986 | }; | |
11987 | ||
11988 | static struct attn_hw_reg nig_prty2_k2 = { | |
11989 | 2, 31, nig_prty2_k2_attn_idx, 0x500210, 0x50021c, 0x500218, 0x500214 | |
11990 | }; | |
11991 | ||
11992 | static const u16 nig_prty3_k2_attn_idx[31] = { | |
11993 | 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 92, 93, 105, 62, 106, | |
11994 | 107, 108, 109, 59, 90, 91, 64, 55, 41, 42, 43, 63, 65, 35, 34, | |
11995 | }; | |
11996 | ||
11997 | static struct attn_hw_reg nig_prty3_k2 = { | |
11998 | 3, 31, nig_prty3_k2_attn_idx, 0x500220, 0x50022c, 0x500228, 0x500224 | |
11999 | }; | |
12000 | ||
12001 | static const u16 nig_prty4_k2_attn_idx[14] = { | |
12002 | 44, 45, 46, 47, 40, 50, 66, 56, 57, 58, 51, 52, 53, 54, | |
12003 | }; | |
12004 | ||
12005 | static struct attn_hw_reg nig_prty4_k2 = { | |
12006 | 4, 14, nig_prty4_k2_attn_idx, 0x500230, 0x50023c, 0x500238, 0x500234 | |
12007 | }; | |
12008 | ||
12009 | static struct attn_hw_reg *nig_prty_k2_regs[5] = { | |
12010 | &nig_prty0_k2, &nig_prty1_k2, &nig_prty2_k2, &nig_prty3_k2, | |
12011 | &nig_prty4_k2, | |
12012 | }; | |
12013 | ||
12014 | #ifdef ATTN_DESC | |
12015 | static const char *wol_int_attn_desc[1] = { | |
12016 | "wol_address_error", | |
12017 | }; | |
12018 | #else | |
12019 | #define wol_int_attn_desc OSAL_NULL | |
12020 | #endif | |
12021 | ||
12022 | static const u16 wol_int0_k2_attn_idx[1] = { | |
12023 | 0, | |
12024 | }; | |
12025 | ||
12026 | static struct attn_hw_reg wol_int0_k2 = { | |
12027 | 0, 1, wol_int0_k2_attn_idx, 0x600040, 0x60004c, 0x600048, 0x600044 | |
12028 | }; | |
12029 | ||
12030 | static struct attn_hw_reg *wol_int_k2_regs[1] = { | |
12031 | &wol_int0_k2, | |
12032 | }; | |
12033 | ||
12034 | #ifdef ATTN_DESC | |
12035 | static const char *wol_prty_attn_desc[24] = { | |
12036 | "wol_mem017_i_mem_prty", | |
12037 | "wol_mem018_i_mem_prty", | |
12038 | "wol_mem019_i_mem_prty", | |
12039 | "wol_mem020_i_mem_prty", | |
12040 | "wol_mem021_i_mem_prty", | |
12041 | "wol_mem022_i_mem_prty", | |
12042 | "wol_mem023_i_mem_prty", | |
12043 | "wol_mem024_i_mem_prty", | |
12044 | "wol_mem001_i_mem_prty", | |
12045 | "wol_mem008_i_mem_prty", | |
12046 | "wol_mem009_i_mem_prty", | |
12047 | "wol_mem010_i_mem_prty", | |
12048 | "wol_mem011_i_mem_prty", | |
12049 | "wol_mem012_i_mem_prty", | |
12050 | "wol_mem013_i_mem_prty", | |
12051 | "wol_mem014_i_mem_prty", | |
12052 | "wol_mem015_i_mem_prty", | |
12053 | "wol_mem016_i_mem_prty", | |
12054 | "wol_mem002_i_mem_prty", | |
12055 | "wol_mem003_i_mem_prty", | |
12056 | "wol_mem004_i_mem_prty", | |
12057 | "wol_mem005_i_mem_prty", | |
12058 | "wol_mem006_i_mem_prty", | |
12059 | "wol_mem007_i_mem_prty", | |
12060 | }; | |
12061 | #else | |
12062 | #define wol_prty_attn_desc OSAL_NULL | |
12063 | #endif | |
12064 | ||
12065 | static const u16 wol_prty1_k2_attn_idx[24] = { | |
12066 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
12067 | 20, | |
12068 | 21, 22, 23, | |
12069 | }; | |
12070 | ||
12071 | static struct attn_hw_reg wol_prty1_k2 = { | |
12072 | 0, 24, wol_prty1_k2_attn_idx, 0x600200, 0x60020c, 0x600208, 0x600204 | |
12073 | }; | |
12074 | ||
12075 | static struct attn_hw_reg *wol_prty_k2_regs[1] = { | |
12076 | &wol_prty1_k2, | |
12077 | }; | |
12078 | ||
12079 | #ifdef ATTN_DESC | |
12080 | static const char *bmbn_int_attn_desc[1] = { | |
12081 | "bmbn_address_error", | |
12082 | }; | |
12083 | #else | |
12084 | #define bmbn_int_attn_desc OSAL_NULL | |
12085 | #endif | |
12086 | ||
12087 | static const u16 bmbn_int0_k2_attn_idx[1] = { | |
12088 | 0, | |
12089 | }; | |
12090 | ||
12091 | static struct attn_hw_reg bmbn_int0_k2 = { | |
12092 | 0, 1, bmbn_int0_k2_attn_idx, 0x610040, 0x61004c, 0x610048, 0x610044 | |
12093 | }; | |
12094 | ||
12095 | static struct attn_hw_reg *bmbn_int_k2_regs[1] = { | |
12096 | &bmbn_int0_k2, | |
12097 | }; | |
12098 | ||
12099 | #ifdef ATTN_DESC | |
12100 | static const char *ipc_int_attn_desc[14] = { | |
12101 | "ipc_address_error", | |
12102 | "ipc_unused_0", | |
12103 | "ipc_vmain_por_assert", | |
12104 | "ipc_vmain_por_deassert", | |
12105 | "ipc_perst_assert", | |
12106 | "ipc_perst_deassert", | |
12107 | "ipc_otp_ecc_ded_0", | |
12108 | "ipc_otp_ecc_ded_1", | |
12109 | "ipc_otp_ecc_ded_2", | |
12110 | "ipc_otp_ecc_ded_3", | |
12111 | "ipc_otp_ecc_ded_4", | |
12112 | "ipc_otp_ecc_ded_5", | |
12113 | "ipc_otp_ecc_ded_6", | |
12114 | "ipc_otp_ecc_ded_7", | |
12115 | }; | |
12116 | #else | |
12117 | #define ipc_int_attn_desc OSAL_NULL | |
12118 | #endif | |
12119 | ||
12120 | static const u16 ipc_int0_bb_a0_attn_idx[5] = { | |
12121 | 0, 2, 3, 4, 5, | |
12122 | }; | |
12123 | ||
12124 | static struct attn_hw_reg ipc_int0_bb_a0 = { | |
12125 | 0, 5, ipc_int0_bb_a0_attn_idx, 0x2050c, 0x20518, 0x20514, 0x20510 | |
12126 | }; | |
12127 | ||
12128 | static struct attn_hw_reg *ipc_int_bb_a0_regs[1] = { | |
12129 | &ipc_int0_bb_a0, | |
12130 | }; | |
12131 | ||
12132 | static const u16 ipc_int0_bb_b0_attn_idx[13] = { | |
12133 | 0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, | |
12134 | }; | |
12135 | ||
12136 | static struct attn_hw_reg ipc_int0_bb_b0 = { | |
12137 | 0, 13, ipc_int0_bb_b0_attn_idx, 0x2050c, 0x20518, 0x20514, 0x20510 | |
12138 | }; | |
12139 | ||
12140 | static struct attn_hw_reg *ipc_int_bb_b0_regs[1] = { | |
12141 | &ipc_int0_bb_b0, | |
12142 | }; | |
12143 | ||
12144 | static const u16 ipc_int0_k2_attn_idx[5] = { | |
12145 | 0, 2, 3, 4, 5, | |
12146 | }; | |
12147 | ||
12148 | static struct attn_hw_reg ipc_int0_k2 = { | |
12149 | 0, 5, ipc_int0_k2_attn_idx, 0x202dc, 0x202e8, 0x202e4, 0x202e0 | |
12150 | }; | |
12151 | ||
12152 | static struct attn_hw_reg *ipc_int_k2_regs[1] = { | |
12153 | &ipc_int0_k2, | |
12154 | }; | |
12155 | ||
12156 | #ifdef ATTN_DESC | |
12157 | static const char *ipc_prty_attn_desc[1] = { | |
12158 | "ipc_fake_par_err", | |
12159 | }; | |
12160 | #else | |
12161 | #define ipc_prty_attn_desc OSAL_NULL | |
12162 | #endif | |
12163 | ||
12164 | static const u16 ipc_prty0_bb_a0_attn_idx[1] = { | |
12165 | 0, | |
12166 | }; | |
12167 | ||
12168 | static struct attn_hw_reg ipc_prty0_bb_a0 = { | |
12169 | 0, 1, ipc_prty0_bb_a0_attn_idx, 0x2051c, 0x20528, 0x20524, 0x20520 | |
12170 | }; | |
12171 | ||
12172 | static struct attn_hw_reg *ipc_prty_bb_a0_regs[1] = { | |
12173 | &ipc_prty0_bb_a0, | |
12174 | }; | |
12175 | ||
12176 | static const u16 ipc_prty0_bb_b0_attn_idx[1] = { | |
12177 | 0, | |
12178 | }; | |
12179 | ||
12180 | static struct attn_hw_reg ipc_prty0_bb_b0 = { | |
12181 | 0, 1, ipc_prty0_bb_b0_attn_idx, 0x2051c, 0x20528, 0x20524, 0x20520 | |
12182 | }; | |
12183 | ||
12184 | static struct attn_hw_reg *ipc_prty_bb_b0_regs[1] = { | |
12185 | &ipc_prty0_bb_b0, | |
12186 | }; | |
12187 | ||
12188 | #ifdef ATTN_DESC | |
12189 | static const char *nwm_int_attn_desc[18] = { | |
12190 | "nwm_address_error", | |
12191 | "nwm_tx_overflow_0", | |
12192 | "nwm_tx_underflow_0", | |
12193 | "nwm_tx_overflow_1", | |
12194 | "nwm_tx_underflow_1", | |
12195 | "nwm_tx_overflow_2", | |
12196 | "nwm_tx_underflow_2", | |
12197 | "nwm_tx_overflow_3", | |
12198 | "nwm_tx_underflow_3", | |
12199 | "nwm_unused_0", | |
12200 | "nwm_ln0_at_10M", | |
12201 | "nwm_ln0_at_100M", | |
12202 | "nwm_ln1_at_10M", | |
12203 | "nwm_ln1_at_100M", | |
12204 | "nwm_ln2_at_10M", | |
12205 | "nwm_ln2_at_100M", | |
12206 | "nwm_ln3_at_10M", | |
12207 | "nwm_ln3_at_100M", | |
12208 | }; | |
12209 | #else | |
12210 | #define nwm_int_attn_desc OSAL_NULL | |
12211 | #endif | |
12212 | ||
12213 | static const u16 nwm_int0_k2_attn_idx[17] = { | |
12214 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 15, 16, 17, | |
12215 | }; | |
12216 | ||
12217 | static struct attn_hw_reg nwm_int0_k2 = { | |
12218 | 0, 17, nwm_int0_k2_attn_idx, 0x800004, 0x800010, 0x80000c, 0x800008 | |
12219 | }; | |
12220 | ||
12221 | static struct attn_hw_reg *nwm_int_k2_regs[1] = { | |
12222 | &nwm_int0_k2, | |
12223 | }; | |
12224 | ||
12225 | #ifdef ATTN_DESC | |
12226 | static const char *nwm_prty_attn_desc[72] = { | |
12227 | "nwm_mem020_i_mem_prty", | |
12228 | "nwm_mem028_i_mem_prty", | |
12229 | "nwm_mem036_i_mem_prty", | |
12230 | "nwm_mem044_i_mem_prty", | |
12231 | "nwm_mem023_i_mem_prty", | |
12232 | "nwm_mem031_i_mem_prty", | |
12233 | "nwm_mem039_i_mem_prty", | |
12234 | "nwm_mem047_i_mem_prty", | |
12235 | "nwm_mem024_i_mem_prty", | |
12236 | "nwm_mem032_i_mem_prty", | |
12237 | "nwm_mem040_i_mem_prty", | |
12238 | "nwm_mem048_i_mem_prty", | |
12239 | "nwm_mem018_i_mem_prty", | |
12240 | "nwm_mem026_i_mem_prty", | |
12241 | "nwm_mem034_i_mem_prty", | |
12242 | "nwm_mem042_i_mem_prty", | |
12243 | "nwm_mem017_i_mem_prty", | |
12244 | "nwm_mem025_i_mem_prty", | |
12245 | "nwm_mem033_i_mem_prty", | |
12246 | "nwm_mem041_i_mem_prty", | |
12247 | "nwm_mem021_i_mem_prty", | |
12248 | "nwm_mem029_i_mem_prty", | |
12249 | "nwm_mem037_i_mem_prty", | |
12250 | "nwm_mem045_i_mem_prty", | |
12251 | "nwm_mem019_i_mem_prty", | |
12252 | "nwm_mem027_i_mem_prty", | |
12253 | "nwm_mem035_i_mem_prty", | |
12254 | "nwm_mem043_i_mem_prty", | |
12255 | "nwm_mem022_i_mem_prty", | |
12256 | "nwm_mem030_i_mem_prty", | |
12257 | "nwm_mem038_i_mem_prty", | |
12258 | "nwm_mem046_i_mem_prty", | |
12259 | "nwm_mem057_i_mem_prty", | |
12260 | "nwm_mem059_i_mem_prty", | |
12261 | "nwm_mem061_i_mem_prty", | |
12262 | "nwm_mem063_i_mem_prty", | |
12263 | "nwm_mem058_i_mem_prty", | |
12264 | "nwm_mem060_i_mem_prty", | |
12265 | "nwm_mem062_i_mem_prty", | |
12266 | "nwm_mem064_i_mem_prty", | |
12267 | "nwm_mem009_i_mem_prty", | |
12268 | "nwm_mem010_i_mem_prty", | |
12269 | "nwm_mem011_i_mem_prty", | |
12270 | "nwm_mem012_i_mem_prty", | |
12271 | "nwm_mem013_i_mem_prty", | |
12272 | "nwm_mem014_i_mem_prty", | |
12273 | "nwm_mem015_i_mem_prty", | |
12274 | "nwm_mem016_i_mem_prty", | |
12275 | "nwm_mem001_i_mem_prty", | |
12276 | "nwm_mem002_i_mem_prty", | |
12277 | "nwm_mem003_i_mem_prty", | |
12278 | "nwm_mem004_i_mem_prty", | |
12279 | "nwm_mem005_i_mem_prty", | |
12280 | "nwm_mem006_i_mem_prty", | |
12281 | "nwm_mem007_i_mem_prty", | |
12282 | "nwm_mem008_i_mem_prty", | |
12283 | "nwm_mem049_i_mem_prty", | |
12284 | "nwm_mem053_i_mem_prty", | |
12285 | "nwm_mem050_i_mem_prty", | |
12286 | "nwm_mem054_i_mem_prty", | |
12287 | "nwm_mem051_i_mem_prty", | |
12288 | "nwm_mem055_i_mem_prty", | |
12289 | "nwm_mem052_i_mem_prty", | |
12290 | "nwm_mem056_i_mem_prty", | |
12291 | "nwm_mem066_i_mem_prty", | |
12292 | "nwm_mem068_i_mem_prty", | |
12293 | "nwm_mem070_i_mem_prty", | |
12294 | "nwm_mem072_i_mem_prty", | |
12295 | "nwm_mem065_i_mem_prty", | |
12296 | "nwm_mem067_i_mem_prty", | |
12297 | "nwm_mem069_i_mem_prty", | |
12298 | "nwm_mem071_i_mem_prty", | |
12299 | }; | |
12300 | #else | |
12301 | #define nwm_prty_attn_desc OSAL_NULL | |
12302 | #endif | |
12303 | ||
12304 | static const u16 nwm_prty1_k2_attn_idx[31] = { | |
12305 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
12306 | 20, | |
12307 | 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, | |
12308 | }; | |
12309 | ||
12310 | static struct attn_hw_reg nwm_prty1_k2 = { | |
12311 | 0, 31, nwm_prty1_k2_attn_idx, 0x800200, 0x80020c, 0x800208, 0x800204 | |
12312 | }; | |
12313 | ||
12314 | static const u16 nwm_prty2_k2_attn_idx[31] = { | |
12315 | 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, | |
12316 | 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, | |
12317 | }; | |
12318 | ||
12319 | static struct attn_hw_reg nwm_prty2_k2 = { | |
12320 | 1, 31, nwm_prty2_k2_attn_idx, 0x800210, 0x80021c, 0x800218, 0x800214 | |
12321 | }; | |
12322 | ||
12323 | static const u16 nwm_prty3_k2_attn_idx[10] = { | |
12324 | 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, | |
12325 | }; | |
12326 | ||
12327 | static struct attn_hw_reg nwm_prty3_k2 = { | |
12328 | 2, 10, nwm_prty3_k2_attn_idx, 0x800220, 0x80022c, 0x800228, 0x800224 | |
12329 | }; | |
12330 | ||
12331 | static struct attn_hw_reg *nwm_prty_k2_regs[3] = { | |
12332 | &nwm_prty1_k2, &nwm_prty2_k2, &nwm_prty3_k2, | |
12333 | }; | |
12334 | ||
12335 | #ifdef ATTN_DESC | |
12336 | static const char *nws_int_attn_desc[38] = { | |
12337 | "nws_address_error", | |
12338 | "nws_ln0_an_resolve_50g_cr2", | |
12339 | "nws_ln0_an_resolve_50g_kr2", | |
12340 | "nws_ln0_an_resolve_40g_cr4", | |
12341 | "nws_ln0_an_resolve_40g_kr4", | |
12342 | "nws_ln0_an_resolve_25g_gr", | |
12343 | "nws_ln0_an_resolve_25g_cr", | |
12344 | "nws_ln0_an_resolve_25g_kr", | |
12345 | "nws_ln0_an_resolve_10g_kr", | |
12346 | "nws_ln0_an_resolve_1g_kx", | |
12347 | "nws_unused_0", | |
12348 | "nws_ln1_an_resolve_50g_cr2", | |
12349 | "nws_ln1_an_resolve_50g_kr2", | |
12350 | "nws_ln1_an_resolve_40g_cr4", | |
12351 | "nws_ln1_an_resolve_40g_kr4", | |
12352 | "nws_ln1_an_resolve_25g_gr", | |
12353 | "nws_ln1_an_resolve_25g_cr", | |
12354 | "nws_ln1_an_resolve_25g_kr", | |
12355 | "nws_ln1_an_resolve_10g_kr", | |
12356 | "nws_ln1_an_resolve_1g_kx", | |
12357 | "nws_ln2_an_resolve_50g_cr2", | |
12358 | "nws_ln2_an_resolve_50g_kr2", | |
12359 | "nws_ln2_an_resolve_40g_cr4", | |
12360 | "nws_ln2_an_resolve_40g_kr4", | |
12361 | "nws_ln2_an_resolve_25g_gr", | |
12362 | "nws_ln2_an_resolve_25g_cr", | |
12363 | "nws_ln2_an_resolve_25g_kr", | |
12364 | "nws_ln2_an_resolve_10g_kr", | |
12365 | "nws_ln2_an_resolve_1g_kx", | |
12366 | "nws_ln3_an_resolve_50g_cr2", | |
12367 | "nws_ln3_an_resolve_50g_kr2", | |
12368 | "nws_ln3_an_resolve_40g_cr4", | |
12369 | "nws_ln3_an_resolve_40g_kr4", | |
12370 | "nws_ln3_an_resolve_25g_gr", | |
12371 | "nws_ln3_an_resolve_25g_cr", | |
12372 | "nws_ln3_an_resolve_25g_kr", | |
12373 | "nws_ln3_an_resolve_10g_kr", | |
12374 | "nws_ln3_an_resolve_1g_kx", | |
12375 | }; | |
12376 | #else | |
12377 | #define nws_int_attn_desc OSAL_NULL | |
12378 | #endif | |
12379 | ||
12380 | static const u16 nws_int0_k2_attn_idx[10] = { | |
12381 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, | |
12382 | }; | |
12383 | ||
12384 | static struct attn_hw_reg nws_int0_k2 = { | |
12385 | 0, 10, nws_int0_k2_attn_idx, 0x700180, 0x70018c, 0x700188, 0x700184 | |
12386 | }; | |
12387 | ||
12388 | static const u16 nws_int1_k2_attn_idx[9] = { | |
12389 | 11, 12, 13, 14, 15, 16, 17, 18, 19, | |
12390 | }; | |
12391 | ||
12392 | static struct attn_hw_reg nws_int1_k2 = { | |
12393 | 1, 9, nws_int1_k2_attn_idx, 0x700190, 0x70019c, 0x700198, 0x700194 | |
12394 | }; | |
12395 | ||
12396 | static const u16 nws_int2_k2_attn_idx[9] = { | |
12397 | 20, 21, 22, 23, 24, 25, 26, 27, 28, | |
12398 | }; | |
12399 | ||
12400 | static struct attn_hw_reg nws_int2_k2 = { | |
12401 | 2, 9, nws_int2_k2_attn_idx, 0x7001a0, 0x7001ac, 0x7001a8, 0x7001a4 | |
12402 | }; | |
12403 | ||
12404 | static const u16 nws_int3_k2_attn_idx[9] = { | |
12405 | 29, 30, 31, 32, 33, 34, 35, 36, 37, | |
12406 | }; | |
12407 | ||
12408 | static struct attn_hw_reg nws_int3_k2 = { | |
12409 | 3, 9, nws_int3_k2_attn_idx, 0x7001b0, 0x7001bc, 0x7001b8, 0x7001b4 | |
12410 | }; | |
12411 | ||
12412 | static struct attn_hw_reg *nws_int_k2_regs[4] = { | |
12413 | &nws_int0_k2, &nws_int1_k2, &nws_int2_k2, &nws_int3_k2, | |
12414 | }; | |
12415 | ||
12416 | #ifdef ATTN_DESC | |
12417 | static const char *nws_prty_attn_desc[4] = { | |
12418 | "nws_mem003_i_mem_prty", | |
12419 | "nws_mem001_i_mem_prty", | |
12420 | "nws_mem004_i_mem_prty", | |
12421 | "nws_mem002_i_mem_prty", | |
12422 | }; | |
12423 | #else | |
12424 | #define nws_prty_attn_desc OSAL_NULL | |
12425 | #endif | |
12426 | ||
12427 | static const u16 nws_prty1_k2_attn_idx[4] = { | |
12428 | 0, 1, 2, 3, | |
12429 | }; | |
12430 | ||
12431 | static struct attn_hw_reg nws_prty1_k2 = { | |
12432 | 0, 4, nws_prty1_k2_attn_idx, 0x700200, 0x70020c, 0x700208, 0x700204 | |
12433 | }; | |
12434 | ||
12435 | static struct attn_hw_reg *nws_prty_k2_regs[1] = { | |
12436 | &nws_prty1_k2, | |
12437 | }; | |
12438 | ||
12439 | #ifdef ATTN_DESC | |
12440 | static const char *ms_int_attn_desc[1] = { | |
12441 | "ms_address_error", | |
12442 | }; | |
12443 | #else | |
12444 | #define ms_int_attn_desc OSAL_NULL | |
12445 | #endif | |
12446 | ||
12447 | static const u16 ms_int0_k2_attn_idx[1] = { | |
12448 | 0, | |
12449 | }; | |
12450 | ||
12451 | static struct attn_hw_reg ms_int0_k2 = { | |
12452 | 0, 1, ms_int0_k2_attn_idx, 0x6a0180, 0x6a018c, 0x6a0188, 0x6a0184 | |
12453 | }; | |
12454 | ||
12455 | static struct attn_hw_reg *ms_int_k2_regs[1] = { | |
12456 | &ms_int0_k2, | |
12457 | }; | |
12458 | ||
12459 | static struct attn_hw_block attn_blocks[] = { | |
12460 | {"grc", grc_int_attn_desc, grc_prty_attn_desc, { | |
12461 | {1, 1, | |
12462 | grc_int_bb_a0_regs, | |
12463 | grc_prty_bb_a0_regs}, | |
12464 | {1, 1, | |
12465 | grc_int_bb_b0_regs, | |
12466 | grc_prty_bb_b0_regs}, | |
12467 | {1, 1, grc_int_k2_regs, | |
12468 | grc_prty_k2_regs} } }, | |
12469 | {"miscs", miscs_int_attn_desc, miscs_prty_attn_desc, { | |
12470 | {2, 0, | |
12471 | ||
12472 | miscs_int_bb_a0_regs, | |
12473 | OSAL_NULL}, | |
12474 | {2, 1, | |
12475 | ||
12476 | miscs_int_bb_b0_regs, | |
12477 | ||
12478 | miscs_prty_bb_b0_regs}, | |
12479 | {1, 1, | |
12480 | ||
12481 | miscs_int_k2_regs, | |
12482 | ||
12483 | miscs_prty_k2_regs } } }, | |
12484 | {"misc", misc_int_attn_desc, OSAL_NULL, { | |
12485 | {1, 0, misc_int_bb_a0_regs, | |
12486 | OSAL_NULL}, | |
12487 | {1, 0, misc_int_bb_b0_regs, | |
12488 | OSAL_NULL}, | |
12489 | {1, 0, misc_int_k2_regs, | |
12490 | OSAL_NULL } } }, | |
12491 | {"dbu", OSAL_NULL, OSAL_NULL, { | |
12492 | {0, 0, OSAL_NULL, OSAL_NULL}, | |
12493 | {0, 0, OSAL_NULL, OSAL_NULL}, | |
12494 | {0, 0, OSAL_NULL, OSAL_NULL } } }, | |
12495 | {"pglue_b", pglue_b_int_attn_desc, pglue_b_prty_attn_desc, { | |
12496 | {1, 1, | |
12497 | ||
12498 | pglue_b_int_bb_a0_regs, | |
12499 | ||
12500 | pglue_b_prty_bb_a0_regs}, | |
12501 | {1, 2, | |
12502 | ||
12503 | pglue_b_int_bb_b0_regs, | |
12504 | ||
12505 | pglue_b_prty_bb_b0_regs}, | |
12506 | {1, 3, | |
12507 | ||
12508 | pglue_b_int_k2_regs, | |
12509 | ||
12510 | pglue_b_prty_k2_regs } } }, | |
12511 | {"cnig", cnig_int_attn_desc, cnig_prty_attn_desc, { | |
12512 | {1, 0, | |
12513 | cnig_int_bb_a0_regs, | |
12514 | OSAL_NULL}, | |
12515 | {1, 1, | |
12516 | cnig_int_bb_b0_regs, | |
12517 | ||
12518 | cnig_prty_bb_b0_regs}, | |
12519 | {1, 1, | |
12520 | cnig_int_k2_regs, | |
12521 | ||
12522 | cnig_prty_k2_regs } } }, | |
12523 | {"cpmu", cpmu_int_attn_desc, OSAL_NULL, { | |
12524 | {1, 0, cpmu_int_bb_a0_regs, | |
12525 | OSAL_NULL}, | |
12526 | {1, 0, cpmu_int_bb_b0_regs, | |
12527 | OSAL_NULL}, | |
12528 | {1, 0, cpmu_int_k2_regs, | |
12529 | OSAL_NULL } } }, | |
12530 | {"ncsi", ncsi_int_attn_desc, ncsi_prty_attn_desc, { | |
12531 | {1, 1, | |
12532 | ncsi_int_bb_a0_regs, | |
12533 | ||
12534 | ncsi_prty_bb_a0_regs}, | |
12535 | {1, 1, | |
12536 | ncsi_int_bb_b0_regs, | |
12537 | ||
12538 | ncsi_prty_bb_b0_regs}, | |
12539 | {1, 1, | |
12540 | ncsi_int_k2_regs, | |
12541 | ||
12542 | ncsi_prty_k2_regs } } }, | |
12543 | {"opte", OSAL_NULL, opte_prty_attn_desc, { | |
12544 | {0, 1, OSAL_NULL, | |
12545 | opte_prty_bb_a0_regs}, | |
12546 | {0, 2, OSAL_NULL, | |
12547 | opte_prty_bb_b0_regs}, | |
12548 | {0, 2, OSAL_NULL, | |
12549 | opte_prty_k2_regs } } }, | |
12550 | {"bmb", bmb_int_attn_desc, bmb_prty_attn_desc, { | |
12551 | {12, 2, | |
12552 | bmb_int_bb_a0_regs, | |
12553 | bmb_prty_bb_a0_regs}, | |
12554 | {12, 3, | |
12555 | bmb_int_bb_b0_regs, | |
12556 | bmb_prty_bb_b0_regs}, | |
12557 | {12, 3, bmb_int_k2_regs, | |
12558 | bmb_prty_k2_regs } } }, | |
12559 | {"pcie", pcie_int_attn_desc, pcie_prty_attn_desc, { | |
12560 | {0, 1, OSAL_NULL, | |
12561 | ||
12562 | pcie_prty_bb_a0_regs}, | |
12563 | {0, 1, OSAL_NULL, | |
12564 | ||
12565 | pcie_prty_bb_b0_regs}, | |
12566 | {1, 2, | |
12567 | pcie_int_k2_regs, | |
12568 | ||
12569 | pcie_prty_k2_regs } } }, | |
12570 | {"mcp", OSAL_NULL, OSAL_NULL, { | |
12571 | {0, 0, OSAL_NULL, OSAL_NULL}, | |
12572 | {0, 0, OSAL_NULL, OSAL_NULL}, | |
12573 | {0, 0, OSAL_NULL, OSAL_NULL } } }, | |
12574 | {"mcp2", OSAL_NULL, mcp2_prty_attn_desc, { | |
12575 | {0, 2, OSAL_NULL, | |
12576 | mcp2_prty_bb_a0_regs}, | |
12577 | {0, 2, OSAL_NULL, | |
12578 | mcp2_prty_bb_b0_regs}, | |
12579 | {0, 2, OSAL_NULL, | |
12580 | mcp2_prty_k2_regs } } }, | |
12581 | {"pswhst", pswhst_int_attn_desc, pswhst_prty_attn_desc, { | |
12582 | {1, 1, | |
12583 | ||
12584 | pswhst_int_bb_a0_regs, | |
12585 | ||
12586 | pswhst_prty_bb_a0_regs}, | |
12587 | {1, 2, | |
12588 | ||
12589 | pswhst_int_bb_b0_regs, | |
12590 | ||
12591 | pswhst_prty_bb_b0_regs}, | |
12592 | {1, 2, | |
12593 | ||
12594 | pswhst_int_k2_regs, | |
12595 | ||
12596 | pswhst_prty_k2_regs } } }, | |
12597 | {"pswhst2", pswhst2_int_attn_desc, pswhst2_prty_attn_desc, { | |
12598 | {1, 0, | |
12599 | ||
12600 | pswhst2_int_bb_a0_regs, | |
12601 | OSAL_NULL}, | |
12602 | {1, 1, | |
12603 | ||
12604 | pswhst2_int_bb_b0_regs, | |
12605 | ||
12606 | pswhst2_prty_bb_b0_regs}, | |
12607 | {1, 1, | |
12608 | ||
12609 | pswhst2_int_k2_regs, | |
12610 | ||
12611 | pswhst2_prty_k2_regs } } }, | |
12612 | {"pswrd", pswrd_int_attn_desc, pswrd_prty_attn_desc, { | |
12613 | {1, 0, | |
12614 | ||
12615 | pswrd_int_bb_a0_regs, | |
12616 | OSAL_NULL}, | |
12617 | {1, 1, | |
12618 | ||
12619 | pswrd_int_bb_b0_regs, | |
12620 | ||
12621 | pswrd_prty_bb_b0_regs}, | |
12622 | {1, 1, | |
12623 | ||
12624 | pswrd_int_k2_regs, | |
12625 | ||
12626 | pswrd_prty_k2_regs } } }, | |
12627 | {"pswrd2", pswrd2_int_attn_desc, pswrd2_prty_attn_desc, { | |
12628 | {1, 2, | |
12629 | ||
12630 | pswrd2_int_bb_a0_regs, | |
12631 | ||
12632 | pswrd2_prty_bb_a0_regs}, | |
12633 | {1, 3, | |
12634 | ||
12635 | pswrd2_int_bb_b0_regs, | |
12636 | ||
12637 | pswrd2_prty_bb_b0_regs}, | |
12638 | {1, 3, | |
12639 | ||
12640 | pswrd2_int_k2_regs, | |
12641 | ||
12642 | pswrd2_prty_k2_regs } } }, | |
12643 | {"pswwr", pswwr_int_attn_desc, pswwr_prty_attn_desc, { | |
12644 | {1, 0, | |
12645 | ||
12646 | pswwr_int_bb_a0_regs, | |
12647 | OSAL_NULL}, | |
12648 | {1, 1, | |
12649 | ||
12650 | pswwr_int_bb_b0_regs, | |
12651 | ||
12652 | pswwr_prty_bb_b0_regs}, | |
12653 | {1, 1, | |
12654 | ||
12655 | pswwr_int_k2_regs, | |
12656 | ||
12657 | pswwr_prty_k2_regs } } }, | |
12658 | {"pswwr2", pswwr2_int_attn_desc, pswwr2_prty_attn_desc, { | |
12659 | {1, 4, | |
12660 | ||
12661 | pswwr2_int_bb_a0_regs, | |
12662 | ||
12663 | pswwr2_prty_bb_a0_regs}, | |
12664 | {1, 5, | |
12665 | ||
12666 | pswwr2_int_bb_b0_regs, | |
12667 | ||
12668 | pswwr2_prty_bb_b0_regs}, | |
12669 | {1, 5, | |
12670 | ||
12671 | pswwr2_int_k2_regs, | |
12672 | ||
12673 | pswwr2_prty_k2_regs } } }, | |
12674 | {"pswrq", pswrq_int_attn_desc, pswrq_prty_attn_desc, { | |
12675 | {1, 0, | |
12676 | ||
12677 | pswrq_int_bb_a0_regs, | |
12678 | OSAL_NULL}, | |
12679 | {1, 1, | |
12680 | ||
12681 | pswrq_int_bb_b0_regs, | |
12682 | ||
12683 | pswrq_prty_bb_b0_regs}, | |
12684 | {1, 1, | |
12685 | ||
12686 | pswrq_int_k2_regs, | |
12687 | ||
12688 | pswrq_prty_k2_regs } } }, | |
12689 | {"pswrq2", pswrq2_int_attn_desc, pswrq2_prty_attn_desc, { | |
12690 | {1, 1, | |
12691 | ||
12692 | pswrq2_int_bb_a0_regs, | |
12693 | ||
12694 | pswrq2_prty_bb_a0_regs}, | |
12695 | {1, 1, | |
12696 | ||
12697 | pswrq2_int_bb_b0_regs, | |
12698 | ||
12699 | pswrq2_prty_bb_b0_regs}, | |
12700 | {1, 1, | |
12701 | ||
12702 | pswrq2_int_k2_regs, | |
12703 | ||
12704 | pswrq2_prty_k2_regs } } }, | |
12705 | {"pglcs", pglcs_int_attn_desc, OSAL_NULL, { | |
12706 | {1, 0, pglcs_int_bb_a0_regs, | |
12707 | OSAL_NULL}, | |
12708 | {1, 0, pglcs_int_bb_b0_regs, | |
12709 | OSAL_NULL}, | |
12710 | {1, 0, pglcs_int_k2_regs, | |
12711 | OSAL_NULL } } }, | |
12712 | {"dmae", dmae_int_attn_desc, dmae_prty_attn_desc, { | |
12713 | {1, 1, | |
12714 | dmae_int_bb_a0_regs, | |
12715 | ||
12716 | dmae_prty_bb_a0_regs}, | |
12717 | {1, 1, | |
12718 | dmae_int_bb_b0_regs, | |
12719 | ||
12720 | dmae_prty_bb_b0_regs}, | |
12721 | {1, 1, | |
12722 | dmae_int_k2_regs, | |
12723 | ||
12724 | dmae_prty_k2_regs } } }, | |
12725 | {"ptu", ptu_int_attn_desc, ptu_prty_attn_desc, { | |
12726 | {1, 1, | |
12727 | ptu_int_bb_a0_regs, | |
12728 | ptu_prty_bb_a0_regs}, | |
12729 | {1, 1, | |
12730 | ptu_int_bb_b0_regs, | |
12731 | ptu_prty_bb_b0_regs}, | |
12732 | {1, 1, ptu_int_k2_regs, | |
12733 | ptu_prty_k2_regs } } }, | |
12734 | {"tcm", tcm_int_attn_desc, tcm_prty_attn_desc, { | |
12735 | {3, 2, | |
12736 | tcm_int_bb_a0_regs, | |
12737 | tcm_prty_bb_a0_regs}, | |
12738 | {3, 2, | |
12739 | tcm_int_bb_b0_regs, | |
12740 | tcm_prty_bb_b0_regs}, | |
12741 | {3, 2, tcm_int_k2_regs, | |
12742 | tcm_prty_k2_regs } } }, | |
12743 | {"mcm", mcm_int_attn_desc, mcm_prty_attn_desc, { | |
12744 | {3, 2, | |
12745 | mcm_int_bb_a0_regs, | |
12746 | mcm_prty_bb_a0_regs}, | |
12747 | {3, 2, | |
12748 | mcm_int_bb_b0_regs, | |
12749 | mcm_prty_bb_b0_regs}, | |
12750 | {3, 2, mcm_int_k2_regs, | |
12751 | mcm_prty_k2_regs } } }, | |
12752 | {"ucm", ucm_int_attn_desc, ucm_prty_attn_desc, { | |
12753 | {3, 2, | |
12754 | ucm_int_bb_a0_regs, | |
12755 | ucm_prty_bb_a0_regs}, | |
12756 | {3, 2, | |
12757 | ucm_int_bb_b0_regs, | |
12758 | ucm_prty_bb_b0_regs}, | |
12759 | {3, 2, ucm_int_k2_regs, | |
12760 | ucm_prty_k2_regs } } }, | |
12761 | {"xcm", xcm_int_attn_desc, xcm_prty_attn_desc, { | |
12762 | {3, 2, | |
12763 | xcm_int_bb_a0_regs, | |
12764 | xcm_prty_bb_a0_regs}, | |
12765 | {3, 2, | |
12766 | xcm_int_bb_b0_regs, | |
12767 | xcm_prty_bb_b0_regs}, | |
12768 | {3, 2, xcm_int_k2_regs, | |
12769 | xcm_prty_k2_regs } } }, | |
12770 | {"ycm", ycm_int_attn_desc, ycm_prty_attn_desc, { | |
12771 | {3, 2, | |
12772 | ycm_int_bb_a0_regs, | |
12773 | ycm_prty_bb_a0_regs}, | |
12774 | {3, 2, | |
12775 | ycm_int_bb_b0_regs, | |
12776 | ycm_prty_bb_b0_regs}, | |
12777 | {3, 2, ycm_int_k2_regs, | |
12778 | ycm_prty_k2_regs } } }, | |
12779 | {"pcm", pcm_int_attn_desc, pcm_prty_attn_desc, { | |
12780 | {3, 1, | |
12781 | pcm_int_bb_a0_regs, | |
12782 | pcm_prty_bb_a0_regs}, | |
12783 | {3, 1, | |
12784 | pcm_int_bb_b0_regs, | |
12785 | pcm_prty_bb_b0_regs}, | |
12786 | {3, 1, pcm_int_k2_regs, | |
12787 | pcm_prty_k2_regs } } }, | |
12788 | {"qm", qm_int_attn_desc, qm_prty_attn_desc, { | |
12789 | {1, 4, qm_int_bb_a0_regs, | |
12790 | qm_prty_bb_a0_regs}, | |
12791 | {1, 4, qm_int_bb_b0_regs, | |
12792 | qm_prty_bb_b0_regs}, | |
12793 | {1, 4, qm_int_k2_regs, | |
12794 | qm_prty_k2_regs } } }, | |
12795 | {"tm", tm_int_attn_desc, tm_prty_attn_desc, { | |
12796 | {2, 1, tm_int_bb_a0_regs, | |
12797 | tm_prty_bb_a0_regs}, | |
12798 | {2, 1, tm_int_bb_b0_regs, | |
12799 | tm_prty_bb_b0_regs}, | |
12800 | {2, 1, tm_int_k2_regs, | |
12801 | tm_prty_k2_regs } } }, | |
12802 | {"dorq", dorq_int_attn_desc, dorq_prty_attn_desc, { | |
12803 | {1, 1, | |
12804 | dorq_int_bb_a0_regs, | |
12805 | ||
12806 | dorq_prty_bb_a0_regs}, | |
12807 | {1, 2, | |
12808 | dorq_int_bb_b0_regs, | |
12809 | ||
12810 | dorq_prty_bb_b0_regs}, | |
12811 | {1, 2, | |
12812 | dorq_int_k2_regs, | |
12813 | ||
12814 | dorq_prty_k2_regs } } }, | |
12815 | {"brb", brb_int_attn_desc, brb_prty_attn_desc, { | |
12816 | {12, 2, | |
12817 | brb_int_bb_a0_regs, | |
12818 | brb_prty_bb_a0_regs}, | |
12819 | {12, 3, | |
12820 | brb_int_bb_b0_regs, | |
12821 | brb_prty_bb_b0_regs}, | |
12822 | {12, 3, brb_int_k2_regs, | |
12823 | brb_prty_k2_regs } } }, | |
12824 | {"src", src_int_attn_desc, OSAL_NULL, { | |
12825 | {1, 0, src_int_bb_a0_regs, | |
12826 | OSAL_NULL}, | |
12827 | {1, 0, src_int_bb_b0_regs, | |
12828 | OSAL_NULL}, | |
12829 | {1, 0, src_int_k2_regs, | |
12830 | OSAL_NULL } } }, | |
12831 | {"prs", prs_int_attn_desc, prs_prty_attn_desc, { | |
12832 | {1, 3, | |
12833 | prs_int_bb_a0_regs, | |
12834 | prs_prty_bb_a0_regs}, | |
12835 | {1, 3, | |
12836 | prs_int_bb_b0_regs, | |
12837 | prs_prty_bb_b0_regs}, | |
12838 | {1, 3, prs_int_k2_regs, | |
12839 | prs_prty_k2_regs } } }, | |
12840 | {"tsdm", tsdm_int_attn_desc, tsdm_prty_attn_desc, { | |
12841 | {1, 1, | |
12842 | tsdm_int_bb_a0_regs, | |
12843 | ||
12844 | tsdm_prty_bb_a0_regs}, | |
12845 | {1, 1, | |
12846 | tsdm_int_bb_b0_regs, | |
12847 | ||
12848 | tsdm_prty_bb_b0_regs}, | |
12849 | {1, 1, | |
12850 | tsdm_int_k2_regs, | |
12851 | ||
12852 | tsdm_prty_k2_regs } } }, | |
12853 | {"msdm", msdm_int_attn_desc, msdm_prty_attn_desc, { | |
12854 | {1, 1, | |
12855 | msdm_int_bb_a0_regs, | |
12856 | ||
12857 | msdm_prty_bb_a0_regs}, | |
12858 | {1, 1, | |
12859 | msdm_int_bb_b0_regs, | |
12860 | ||
12861 | msdm_prty_bb_b0_regs}, | |
12862 | {1, 1, | |
12863 | msdm_int_k2_regs, | |
12864 | ||
12865 | msdm_prty_k2_regs } } }, | |
12866 | {"usdm", usdm_int_attn_desc, usdm_prty_attn_desc, { | |
12867 | {1, 1, | |
12868 | usdm_int_bb_a0_regs, | |
12869 | ||
12870 | usdm_prty_bb_a0_regs}, | |
12871 | {1, 1, | |
12872 | usdm_int_bb_b0_regs, | |
12873 | ||
12874 | usdm_prty_bb_b0_regs}, | |
12875 | {1, 1, | |
12876 | usdm_int_k2_regs, | |
12877 | ||
12878 | usdm_prty_k2_regs } } }, | |
12879 | {"xsdm", xsdm_int_attn_desc, xsdm_prty_attn_desc, { | |
12880 | {1, 1, | |
12881 | xsdm_int_bb_a0_regs, | |
12882 | ||
12883 | xsdm_prty_bb_a0_regs}, | |
12884 | {1, 1, | |
12885 | xsdm_int_bb_b0_regs, | |
12886 | ||
12887 | xsdm_prty_bb_b0_regs}, | |
12888 | {1, 1, | |
12889 | xsdm_int_k2_regs, | |
12890 | ||
12891 | xsdm_prty_k2_regs } } }, | |
12892 | {"ysdm", ysdm_int_attn_desc, ysdm_prty_attn_desc, { | |
12893 | {1, 1, | |
12894 | ysdm_int_bb_a0_regs, | |
12895 | ||
12896 | ysdm_prty_bb_a0_regs}, | |
12897 | {1, 1, | |
12898 | ysdm_int_bb_b0_regs, | |
12899 | ||
12900 | ysdm_prty_bb_b0_regs}, | |
12901 | {1, 1, | |
12902 | ysdm_int_k2_regs, | |
12903 | ||
12904 | ysdm_prty_k2_regs } } }, | |
12905 | {"psdm", psdm_int_attn_desc, psdm_prty_attn_desc, { | |
12906 | {1, 1, | |
12907 | psdm_int_bb_a0_regs, | |
12908 | ||
12909 | psdm_prty_bb_a0_regs}, | |
12910 | {1, 1, | |
12911 | psdm_int_bb_b0_regs, | |
12912 | ||
12913 | psdm_prty_bb_b0_regs}, | |
12914 | {1, 1, | |
12915 | psdm_int_k2_regs, | |
12916 | ||
12917 | psdm_prty_k2_regs } } }, | |
12918 | {"tsem", tsem_int_attn_desc, tsem_prty_attn_desc, { | |
12919 | {3, 3, | |
12920 | tsem_int_bb_a0_regs, | |
12921 | ||
12922 | tsem_prty_bb_a0_regs}, | |
12923 | {3, 3, | |
12924 | tsem_int_bb_b0_regs, | |
12925 | ||
12926 | tsem_prty_bb_b0_regs}, | |
12927 | {3, 4, | |
12928 | tsem_int_k2_regs, | |
12929 | ||
12930 | tsem_prty_k2_regs } } }, | |
12931 | {"msem", msem_int_attn_desc, msem_prty_attn_desc, { | |
12932 | {3, 2, | |
12933 | msem_int_bb_a0_regs, | |
12934 | ||
12935 | msem_prty_bb_a0_regs}, | |
12936 | {3, 2, | |
12937 | msem_int_bb_b0_regs, | |
12938 | ||
12939 | msem_prty_bb_b0_regs}, | |
12940 | {3, 3, | |
12941 | msem_int_k2_regs, | |
12942 | ||
12943 | msem_prty_k2_regs } } }, | |
12944 | {"usem", usem_int_attn_desc, usem_prty_attn_desc, { | |
12945 | {3, 2, | |
12946 | usem_int_bb_a0_regs, | |
12947 | ||
12948 | usem_prty_bb_a0_regs}, | |
12949 | {3, 2, | |
12950 | usem_int_bb_b0_regs, | |
12951 | ||
12952 | usem_prty_bb_b0_regs}, | |
12953 | {3, 3, | |
12954 | usem_int_k2_regs, | |
12955 | ||
12956 | usem_prty_k2_regs } } }, | |
12957 | {"xsem", xsem_int_attn_desc, xsem_prty_attn_desc, { | |
12958 | {3, 2, | |
12959 | xsem_int_bb_a0_regs, | |
12960 | ||
12961 | xsem_prty_bb_a0_regs}, | |
12962 | {3, 2, | |
12963 | xsem_int_bb_b0_regs, | |
12964 | ||
12965 | xsem_prty_bb_b0_regs}, | |
12966 | {3, 3, | |
12967 | xsem_int_k2_regs, | |
12968 | ||
12969 | xsem_prty_k2_regs } } }, | |
12970 | {"ysem", ysem_int_attn_desc, ysem_prty_attn_desc, { | |
12971 | {3, 2, | |
12972 | ysem_int_bb_a0_regs, | |
12973 | ||
12974 | ysem_prty_bb_a0_regs}, | |
12975 | {3, 2, | |
12976 | ysem_int_bb_b0_regs, | |
12977 | ||
12978 | ysem_prty_bb_b0_regs}, | |
12979 | {3, 3, | |
12980 | ysem_int_k2_regs, | |
12981 | ||
12982 | ysem_prty_k2_regs } } }, | |
12983 | {"psem", psem_int_attn_desc, psem_prty_attn_desc, { | |
12984 | {3, 3, | |
12985 | psem_int_bb_a0_regs, | |
12986 | ||
12987 | psem_prty_bb_a0_regs}, | |
12988 | {3, 3, | |
12989 | psem_int_bb_b0_regs, | |
12990 | ||
12991 | psem_prty_bb_b0_regs}, | |
12992 | {3, 4, | |
12993 | psem_int_k2_regs, | |
12994 | ||
12995 | psem_prty_k2_regs } } }, | |
12996 | {"rss", rss_int_attn_desc, rss_prty_attn_desc, { | |
12997 | {1, 1, | |
12998 | rss_int_bb_a0_regs, | |
12999 | rss_prty_bb_a0_regs}, | |
13000 | {1, 1, | |
13001 | rss_int_bb_b0_regs, | |
13002 | rss_prty_bb_b0_regs}, | |
13003 | {1, 1, rss_int_k2_regs, | |
13004 | rss_prty_k2_regs } } }, | |
13005 | {"tmld", tmld_int_attn_desc, tmld_prty_attn_desc, { | |
13006 | {1, 1, | |
13007 | tmld_int_bb_a0_regs, | |
13008 | ||
13009 | tmld_prty_bb_a0_regs}, | |
13010 | {1, 1, | |
13011 | tmld_int_bb_b0_regs, | |
13012 | ||
13013 | tmld_prty_bb_b0_regs}, | |
13014 | {1, 1, | |
13015 | tmld_int_k2_regs, | |
13016 | ||
13017 | tmld_prty_k2_regs } } }, | |
13018 | {"muld", muld_int_attn_desc, muld_prty_attn_desc, { | |
13019 | {1, 1, | |
13020 | muld_int_bb_a0_regs, | |
13021 | ||
13022 | muld_prty_bb_a0_regs}, | |
13023 | {1, 1, | |
13024 | muld_int_bb_b0_regs, | |
13025 | ||
13026 | muld_prty_bb_b0_regs}, | |
13027 | {1, 1, | |
13028 | muld_int_k2_regs, | |
13029 | ||
13030 | muld_prty_k2_regs } } }, | |
13031 | {"yuld", yuld_int_attn_desc, yuld_prty_attn_desc, { | |
13032 | {1, 1, | |
13033 | yuld_int_bb_a0_regs, | |
13034 | ||
13035 | yuld_prty_bb_a0_regs}, | |
13036 | {1, 1, | |
13037 | yuld_int_bb_b0_regs, | |
13038 | ||
13039 | yuld_prty_bb_b0_regs}, | |
13040 | {1, 1, | |
13041 | yuld_int_k2_regs, | |
13042 | ||
13043 | yuld_prty_k2_regs } } }, | |
13044 | {"xyld", xyld_int_attn_desc, xyld_prty_attn_desc, { | |
13045 | {1, 1, | |
13046 | xyld_int_bb_a0_regs, | |
13047 | ||
13048 | xyld_prty_bb_a0_regs}, | |
13049 | {1, 1, | |
13050 | xyld_int_bb_b0_regs, | |
13051 | ||
13052 | xyld_prty_bb_b0_regs}, | |
13053 | {1, 1, | |
13054 | xyld_int_k2_regs, | |
13055 | ||
13056 | xyld_prty_k2_regs } } }, | |
13057 | {"prm", prm_int_attn_desc, prm_prty_attn_desc, { | |
13058 | {1, 1, | |
13059 | prm_int_bb_a0_regs, | |
13060 | prm_prty_bb_a0_regs}, | |
13061 | {1, 2, | |
13062 | prm_int_bb_b0_regs, | |
13063 | prm_prty_bb_b0_regs}, | |
13064 | {1, 2, prm_int_k2_regs, | |
13065 | prm_prty_k2_regs } } }, | |
13066 | {"pbf_pb1", pbf_pb1_int_attn_desc, pbf_pb1_prty_attn_desc, { | |
13067 | {1, 0, | |
13068 | ||
13069 | pbf_pb1_int_bb_a0_regs, | |
13070 | OSAL_NULL}, | |
13071 | {1, 1, | |
13072 | ||
13073 | pbf_pb1_int_bb_b0_regs, | |
13074 | ||
13075 | pbf_pb1_prty_bb_b0_regs}, | |
13076 | {1, 1, | |
13077 | ||
13078 | pbf_pb1_int_k2_regs, | |
13079 | ||
13080 | pbf_pb1_prty_k2_regs } } }, | |
13081 | {"pbf_pb2", pbf_pb2_int_attn_desc, pbf_pb2_prty_attn_desc, { | |
13082 | {1, 0, | |
13083 | ||
13084 | pbf_pb2_int_bb_a0_regs, | |
13085 | OSAL_NULL}, | |
13086 | {1, 1, | |
13087 | ||
13088 | pbf_pb2_int_bb_b0_regs, | |
13089 | ||
13090 | pbf_pb2_prty_bb_b0_regs}, | |
13091 | {1, 1, | |
13092 | ||
13093 | pbf_pb2_int_k2_regs, | |
13094 | ||
13095 | pbf_pb2_prty_k2_regs } } }, | |
13096 | {"rpb", rpb_int_attn_desc, rpb_prty_attn_desc, { | |
13097 | {1, 0, | |
13098 | rpb_int_bb_a0_regs, | |
13099 | OSAL_NULL}, | |
13100 | {1, 1, | |
13101 | rpb_int_bb_b0_regs, | |
13102 | rpb_prty_bb_b0_regs}, | |
13103 | {1, 1, rpb_int_k2_regs, | |
13104 | rpb_prty_k2_regs } } }, | |
13105 | {"btb", btb_int_attn_desc, btb_prty_attn_desc, { | |
13106 | {11, 1, | |
13107 | btb_int_bb_a0_regs, | |
13108 | btb_prty_bb_a0_regs}, | |
13109 | {11, 2, | |
13110 | btb_int_bb_b0_regs, | |
13111 | btb_prty_bb_b0_regs}, | |
13112 | {11, 2, btb_int_k2_regs, | |
13113 | btb_prty_k2_regs } } }, | |
13114 | {"pbf", pbf_int_attn_desc, pbf_prty_attn_desc, { | |
13115 | {1, 2, | |
13116 | pbf_int_bb_a0_regs, | |
13117 | pbf_prty_bb_a0_regs}, | |
13118 | {1, 3, | |
13119 | pbf_int_bb_b0_regs, | |
13120 | pbf_prty_bb_b0_regs}, | |
13121 | {1, 3, pbf_int_k2_regs, | |
13122 | pbf_prty_k2_regs } } }, | |
13123 | {"rdif", rdif_int_attn_desc, rdif_prty_attn_desc, { | |
13124 | {1, 0, | |
13125 | rdif_int_bb_a0_regs, | |
13126 | OSAL_NULL}, | |
13127 | {1, 1, | |
13128 | rdif_int_bb_b0_regs, | |
13129 | ||
13130 | rdif_prty_bb_b0_regs}, | |
13131 | {1, 1, | |
13132 | rdif_int_k2_regs, | |
13133 | ||
13134 | rdif_prty_k2_regs } } }, | |
13135 | {"tdif", tdif_int_attn_desc, tdif_prty_attn_desc, { | |
13136 | {1, 1, | |
13137 | tdif_int_bb_a0_regs, | |
13138 | ||
13139 | tdif_prty_bb_a0_regs}, | |
13140 | {1, 2, | |
13141 | tdif_int_bb_b0_regs, | |
13142 | ||
13143 | tdif_prty_bb_b0_regs}, | |
13144 | {1, 2, | |
13145 | tdif_int_k2_regs, | |
13146 | ||
13147 | tdif_prty_k2_regs } } }, | |
13148 | {"cdu", cdu_int_attn_desc, cdu_prty_attn_desc, { | |
13149 | {1, 1, | |
13150 | cdu_int_bb_a0_regs, | |
13151 | cdu_prty_bb_a0_regs}, | |
13152 | {1, 1, | |
13153 | cdu_int_bb_b0_regs, | |
13154 | cdu_prty_bb_b0_regs}, | |
13155 | {1, 1, cdu_int_k2_regs, | |
13156 | cdu_prty_k2_regs } } }, | |
13157 | {"ccfc", ccfc_int_attn_desc, ccfc_prty_attn_desc, { | |
13158 | {1, 2, | |
13159 | ccfc_int_bb_a0_regs, | |
13160 | ||
13161 | ccfc_prty_bb_a0_regs}, | |
13162 | {1, 2, | |
13163 | ccfc_int_bb_b0_regs, | |
13164 | ||
13165 | ccfc_prty_bb_b0_regs}, | |
13166 | {1, 2, | |
13167 | ccfc_int_k2_regs, | |
13168 | ||
13169 | ccfc_prty_k2_regs } } }, | |
13170 | {"tcfc", tcfc_int_attn_desc, tcfc_prty_attn_desc, { | |
13171 | {1, 2, | |
13172 | tcfc_int_bb_a0_regs, | |
13173 | ||
13174 | tcfc_prty_bb_a0_regs}, | |
13175 | {1, 2, | |
13176 | tcfc_int_bb_b0_regs, | |
13177 | ||
13178 | tcfc_prty_bb_b0_regs}, | |
13179 | {1, 2, | |
13180 | tcfc_int_k2_regs, | |
13181 | ||
13182 | tcfc_prty_k2_regs } } }, | |
13183 | {"igu", igu_int_attn_desc, igu_prty_attn_desc, { | |
13184 | {1, 3, | |
13185 | igu_int_bb_a0_regs, | |
13186 | igu_prty_bb_a0_regs}, | |
13187 | {1, 3, | |
13188 | igu_int_bb_b0_regs, | |
13189 | igu_prty_bb_b0_regs}, | |
13190 | {1, 2, igu_int_k2_regs, | |
13191 | igu_prty_k2_regs } } }, | |
13192 | {"cau", cau_int_attn_desc, cau_prty_attn_desc, { | |
13193 | {1, 1, | |
13194 | cau_int_bb_a0_regs, | |
13195 | cau_prty_bb_a0_regs}, | |
13196 | {1, 1, | |
13197 | cau_int_bb_b0_regs, | |
13198 | cau_prty_bb_b0_regs}, | |
13199 | {1, 1, cau_int_k2_regs, | |
13200 | cau_prty_k2_regs } } }, | |
13201 | {"umac", umac_int_attn_desc, OSAL_NULL, { | |
13202 | {0, 0, OSAL_NULL, OSAL_NULL}, | |
13203 | {0, 0, OSAL_NULL, OSAL_NULL}, | |
13204 | {1, 0, umac_int_k2_regs, | |
13205 | OSAL_NULL } } }, | |
13206 | {"xmac", OSAL_NULL, OSAL_NULL, { | |
13207 | {0, 0, OSAL_NULL, OSAL_NULL}, | |
13208 | {0, 0, OSAL_NULL, OSAL_NULL}, | |
13209 | {0, 0, OSAL_NULL, OSAL_NULL } } }, | |
13210 | {"dbg", dbg_int_attn_desc, dbg_prty_attn_desc, { | |
13211 | {1, 1, | |
13212 | dbg_int_bb_a0_regs, | |
13213 | dbg_prty_bb_a0_regs}, | |
13214 | {1, 1, | |
13215 | dbg_int_bb_b0_regs, | |
13216 | dbg_prty_bb_b0_regs}, | |
13217 | {1, 1, dbg_int_k2_regs, | |
13218 | dbg_prty_k2_regs } } }, | |
13219 | {"nig", nig_int_attn_desc, nig_prty_attn_desc, { | |
13220 | {6, 4, | |
13221 | nig_int_bb_a0_regs, | |
13222 | nig_prty_bb_a0_regs}, | |
13223 | {6, 5, | |
13224 | nig_int_bb_b0_regs, | |
13225 | nig_prty_bb_b0_regs}, | |
13226 | {10, 5, nig_int_k2_regs, | |
13227 | nig_prty_k2_regs } } }, | |
13228 | {"wol", wol_int_attn_desc, wol_prty_attn_desc, { | |
13229 | {0, 0, OSAL_NULL, | |
13230 | OSAL_NULL}, | |
13231 | {0, 0, OSAL_NULL, | |
13232 | OSAL_NULL}, | |
13233 | {1, 1, wol_int_k2_regs, | |
13234 | wol_prty_k2_regs } } }, | |
13235 | {"bmbn", bmbn_int_attn_desc, OSAL_NULL, { | |
13236 | {0, 0, OSAL_NULL, OSAL_NULL}, | |
13237 | {0, 0, OSAL_NULL, OSAL_NULL}, | |
13238 | {1, 0, bmbn_int_k2_regs, | |
13239 | OSAL_NULL } } }, | |
13240 | {"ipc", ipc_int_attn_desc, ipc_prty_attn_desc, { | |
13241 | {1, 1, | |
13242 | ipc_int_bb_a0_regs, | |
13243 | ipc_prty_bb_a0_regs}, | |
13244 | {1, 1, | |
13245 | ipc_int_bb_b0_regs, | |
13246 | ipc_prty_bb_b0_regs}, | |
13247 | {1, 0, ipc_int_k2_regs, | |
13248 | OSAL_NULL } } }, | |
13249 | {"nwm", nwm_int_attn_desc, nwm_prty_attn_desc, { | |
13250 | {0, 0, OSAL_NULL, | |
13251 | OSAL_NULL}, | |
13252 | {0, 0, OSAL_NULL, | |
13253 | OSAL_NULL}, | |
13254 | {1, 3, nwm_int_k2_regs, | |
13255 | nwm_prty_k2_regs } } }, | |
13256 | {"nws", nws_int_attn_desc, nws_prty_attn_desc, { | |
13257 | {0, 0, OSAL_NULL, | |
13258 | OSAL_NULL}, | |
13259 | {0, 0, OSAL_NULL, | |
13260 | OSAL_NULL}, | |
13261 | {4, 1, nws_int_k2_regs, | |
13262 | nws_prty_k2_regs } } }, | |
13263 | {"ms", ms_int_attn_desc, OSAL_NULL, { | |
13264 | {0, 0, OSAL_NULL, OSAL_NULL}, | |
13265 | {0, 0, OSAL_NULL, OSAL_NULL}, | |
13266 | {1, 0, ms_int_k2_regs, | |
13267 | OSAL_NULL } } }, | |
13268 | {"phy_pcie", OSAL_NULL, OSAL_NULL, { | |
13269 | {0, 0, OSAL_NULL, OSAL_NULL}, | |
13270 | {0, 0, OSAL_NULL, OSAL_NULL}, | |
13271 | {0, 0, OSAL_NULL, OSAL_NULL } } }, | |
13272 | {"misc_aeu", OSAL_NULL, OSAL_NULL, { | |
13273 | {0, 0, OSAL_NULL, OSAL_NULL}, | |
13274 | {0, 0, OSAL_NULL, OSAL_NULL}, | |
13275 | {0, 0, OSAL_NULL, OSAL_NULL } } }, | |
13276 | {"bar0_map", OSAL_NULL, OSAL_NULL, { | |
13277 | {0, 0, OSAL_NULL, OSAL_NULL}, | |
13278 | {0, 0, OSAL_NULL, OSAL_NULL}, | |
13279 | {0, 0, OSAL_NULL, OSAL_NULL } } }, | |
13280 | }; | |
13281 | ||
13282 | #define NUM_INT_REGS 423 | |
13283 | #define NUM_PRTY_REGS 378 | |
13284 | ||
13285 | #endif /* __PREVENT_INT_ATTN__ */ | |
13286 | ||
13287 | #endif /* __ATTN_VALUES_H__ */ |