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[ceph.git] / ceph / src / dpdk / drivers / net / qede / base / ecore_hsi_init_func.h
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1/*
2 * Copyright (c) 2016 QLogic Corporation.
3 * All rights reserved.
4 * www.qlogic.com
5 *
6 * See LICENSE.qede_pmd for copyright and licensing details.
7 */
8
9#ifndef __ECORE_HSI_INIT_FUNC__
10#define __ECORE_HSI_INIT_FUNC__
11/********************************/
12/* HSI Init Functions constants */
13/********************************/
14
15/* Number of VLAN priorities */
16#define NUM_OF_VLAN_PRIORITIES 8
17
18
19/*
20 * BRB RAM init requirements
21 */
22struct init_brb_ram_req {
23 __le32 guranteed_per_tc /* guaranteed size per TC, in bytes */;
24 __le32 headroom_per_tc /* headroom size per TC, in bytes */;
25 __le32 min_pkt_size /* min packet size, in bytes */;
26 __le32 max_ports_per_engine /* min packet size, in bytes */;
27 u8 num_active_tcs[MAX_NUM_PORTS] /* number of active TCs per port */;
28};
29
30
31/*
32 * ETS per-TC init requirements
33 */
34struct init_ets_tc_req {
35/* if set, this TC participates in the arbitration with a strict priority
36 * (the priority is equal to the TC ID)
37 */
38 u8 use_sp;
39/* if set, this TC participates in the arbitration with a WFQ weight
40 * (indicated by the weight field)
41 */
42 u8 use_wfq;
43/* An arbitration weight. Valid only if use_wfq is set. */
44 __le16 weight;
45};
46
47/*
48 * ETS init requirements
49 */
50struct init_ets_req {
51 __le32 mtu /* Max packet size (in bytes) */;
52/* ETS initialization requirements per TC. */
53 struct init_ets_tc_req tc_req[NUM_OF_TCS];
54};
55
56
57
58/*
59 * NIG LB RL init requirements
60 */
61struct init_nig_lb_rl_req {
62/* Global MAC+LB RL rate (in Mbps). If set to 0, the RL will be disabled. */
63 __le16 lb_mac_rate;
64/* Global LB RL rate (in Mbps). If set to 0, the RL will be disabled. */
65 __le16 lb_rate;
66 __le32 mtu /* Max packet size (in bytes) */;
67/* RL rate per physical TC (in Mbps). If set to 0, the RL will be disabled. */
68 __le16 tc_rate[NUM_OF_PHYS_TCS];
69};
70
71
72/*
73 * NIG TC mapping for each priority
74 */
75struct init_nig_pri_tc_map_entry {
76 u8 tc_id /* the mapped TC ID */;
77 u8 valid /* indicates if the mapping entry is valid */;
78};
79
80
81/*
82 * NIG priority to TC map init requirements
83 */
84struct init_nig_pri_tc_map_req {
85 struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
86};
87
88
89/*
90 * QM per-port init parameters
91 */
92struct init_qm_port_params {
93 u8 active /* Indicates if this port is active */;
94/* Vector of valid bits for active TCs used by this port */
95 u8 active_phys_tcs;
96/* number of PBF command lines that can be used by this port */
97 __le16 num_pbf_cmd_lines;
98/* number of BTB blocks that can be used by this port */
99 __le16 num_btb_blocks;
100 __le16 reserved;
101};
102
103
104/*
105 * QM per-PQ init parameters
106 */
107struct init_qm_pq_params {
108 u8 vport_id /* VPORT ID */;
109 u8 tc_id /* TC ID */;
110 u8 wrr_group /* WRR group */;
111/* Indicates if a rate limiter should be allocated for the PQ (0/1) */
112 u8 rl_valid;
113};
114
115
116/*
117 * QM per-vport init parameters
118 */
119struct init_qm_vport_params {
120/* rate limit in Mb/sec units. a value of 0 means dont configure. ignored if
121 * VPORT RL is globally disabled.
122 */
123 __le32 vport_rl;
124/* WFQ weight. A value of 0 means dont configure. ignored if VPORT WFQ is
125 * globally disabled.
126 */
127 __le16 vport_wfq;
128/* the first Tx PQ ID associated with this VPORT for each TC. */
129 __le16 first_tx_pq_id[NUM_OF_TCS];
130};
131
132#endif /* __ECORE_HSI_INIT_FUNC__ */