[ceph.git] / ceph / src / dpdk / drivers / net / qede / base / ecore_hsi_init_tool.h

/*
 * Copyright (c) 2016 QLogic Corporation.
 * All rights reserved.
 * www.qlogic.com
 *
 * See LICENSE.qede_pmd for copyright and licensing details.
 */

#ifndef __ECORE_HSI_INIT_TOOL__
#define __ECORE_HSI_INIT_TOOL__
/**************************************/
/* Init Tool HSI constants and macros */
/**************************************/

/* Width of GRC address in bits (addresses are specified in dwords) */
#define GRC_ADDR_BITS			23
#define MAX_GRC_ADDR			((1 << GRC_ADDR_BITS) - 1)

/* indicates an init that should be applied to any phase ID */
#define ANY_PHASE_ID			0xffff

/* Max size in dwords of a zipped array */
#define MAX_ZIPPED_SIZE			8192


struct fw_asserts_ram_section {
/* The offset of the section in the RAM in RAM lines (64-bit units) */
	__le16 section_ram_line_offset;
/* The size of the section in RAM lines (64-bit units) */
	__le16 section_ram_line_size;
/* The offset of the asserts list within the section in dwords */
	u8 list_dword_offset;
/* The size of an assert list element in dwords */
	u8 list_element_dword_size;
	u8 list_num_elements /* The number of elements in the asserts list */;
/* The offset of the next list index field within the section in dwords */
	u8 list_next_index_dword_offset;
};


struct fw_ver_num {
	u8 major /* Firmware major version number */;
	u8 minor /* Firmware minor version number */;
	u8 rev /* Firmware revision version number */;
/* Firmware engineering version number (for bootleg versions) */
	u8 eng;
};

struct fw_ver_info {
	__le16 tools_ver /* Tools version number */;
	u8 image_id /* FW image ID (e.g. main, l2b, kuku) */;
	u8 reserved1;
	struct fw_ver_num num /* FW version number */;
	__le32 timestamp /* FW Timestamp in unix time  (sec. since 1970) */;
	__le32 reserved2;
};

struct fw_info {
	struct fw_ver_info ver /* FW version information */;
/* Info regarding the FW asserts section in the Storm RAM */
	struct fw_asserts_ram_section fw_asserts_section;
};


struct fw_info_location {
/* GRC address where the fw_info struct is located. */
	__le32 grc_addr;
/* Size of the fw_info structure (thats located at the grc_addr). */
	__le32 size;
};


enum init_modes {
	MODE_BB_A0,
	MODE_BB_B0,
	MODE_K2,
	MODE_ASIC,
	MODE_EMUL_REDUCED,
	MODE_EMUL_FULL,
	MODE_FPGA,
	MODE_CHIPSIM,
	MODE_SF,
	MODE_MF_SD,
	MODE_MF_SI,
	MODE_PORTS_PER_ENG_1,
	MODE_PORTS_PER_ENG_2,
	MODE_PORTS_PER_ENG_4,
	MODE_100G,
	MODE_40G,
	MODE_EAGLE_ENG1_WORKAROUND,
	MAX_INIT_MODES
};


enum init_phases {
	PHASE_ENGINE,
	PHASE_PORT,
	PHASE_PF,
	PHASE_VF,
	PHASE_QM_PF,
	MAX_INIT_PHASES
};


enum init_split_types {
	SPLIT_TYPE_NONE,
	SPLIT_TYPE_PORT,
	SPLIT_TYPE_PF,
	SPLIT_TYPE_PORT_PF,
	SPLIT_TYPE_VF,
	MAX_INIT_SPLIT_TYPES
};


/*
 * Binary buffer header
 */
struct bin_buffer_hdr {
/* buffer offset in bytes from the beginning of the binary file */
	__le32 offset;
	__le32 length /* buffer length in bytes */;
};


/*
 * binary init buffer types
 */
enum bin_init_buffer_type {
	BIN_BUF_INIT_FW_VER_INFO /* fw_ver_info struct */,
	BIN_BUF_INIT_CMD /* init commands */,
	BIN_BUF_INIT_VAL /* init data */,
	BIN_BUF_INIT_MODE_TREE /* init modes tree */,
	BIN_BUF_INIT_IRO /* internal RAM offsets */,
	MAX_BIN_INIT_BUFFER_TYPE
};


/*
 * init array header: raw
 */
struct init_array_raw_hdr {
	__le32 data;
/* Init array type, from init_array_types enum */
#define INIT_ARRAY_RAW_HDR_TYPE_MASK    0xF
#define INIT_ARRAY_RAW_HDR_TYPE_SHIFT   0
/* init array params */
#define INIT_ARRAY_RAW_HDR_PARAMS_MASK  0xFFFFFFF
#define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
};

/*
 * init array header: standard
 */
struct init_array_standard_hdr {
	__le32 data;
/* Init array type, from init_array_types enum */
#define INIT_ARRAY_STANDARD_HDR_TYPE_MASK  0xF
#define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
/* Init array size (in dwords) */
#define INIT_ARRAY_STANDARD_HDR_SIZE_MASK  0xFFFFFFF
#define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
};

/*
 * init array header: zipped
 */
struct init_array_zipped_hdr {
	__le32 data;
/* Init array type, from init_array_types enum */
#define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK         0xF
#define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT        0
/* Init array zipped size (in bytes) */
#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK  0xFFFFFFF
#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
};

/*
 * init array header: pattern
 */
struct init_array_pattern_hdr {
	__le32 data;
/* Init array type, from init_array_types enum */
#define INIT_ARRAY_PATTERN_HDR_TYPE_MASK          0xF
#define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT         0
/* pattern size in dword */
#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK  0xF
#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
/* pattern repetitions */
#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK   0xFFFFFF
#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT  8
};

/*
 * init array header union
 */
union init_array_hdr {
	struct init_array_raw_hdr raw /* raw init array header */;
/* standard init array header */
	struct init_array_standard_hdr standard;
	struct init_array_zipped_hdr zipped /* zipped init array header */;
	struct init_array_pattern_hdr pattern /* pattern init array header */;
};


/*
 * init array types
 */
enum init_array_types {
	INIT_ARR_STANDARD /* standard init array */,
	INIT_ARR_ZIPPED /* zipped init array */,
	INIT_ARR_PATTERN /* a repeated pattern */,
	MAX_INIT_ARRAY_TYPES
};


/*
 * init operation: callback
 */
struct init_callback_op {
	__le32 op_data;
/* Init operation, from init_op_types enum */
#define INIT_CALLBACK_OP_OP_MASK        0xF
#define INIT_CALLBACK_OP_OP_SHIFT       0
#define INIT_CALLBACK_OP_RESERVED_MASK  0xFFFFFFF
#define INIT_CALLBACK_OP_RESERVED_SHIFT 4
	__le16 callback_id /* Callback ID */;
	__le16 block_id /* Blocks ID */;
};


/*
 * init operation: delay
 */
struct init_delay_op {
	__le32 op_data;
/* Init operation, from init_op_types enum */
#define INIT_DELAY_OP_OP_MASK        0xF
#define INIT_DELAY_OP_OP_SHIFT       0
#define INIT_DELAY_OP_RESERVED_MASK  0xFFFFFFF
#define INIT_DELAY_OP_RESERVED_SHIFT 4
	__le32 delay /* delay in us */;
};


/*
 * init operation: if_mode
 */
struct init_if_mode_op {
	__le32 op_data;
/* Init operation, from init_op_types enum */
#define INIT_IF_MODE_OP_OP_MASK          0xF
#define INIT_IF_MODE_OP_OP_SHIFT         0
#define INIT_IF_MODE_OP_RESERVED1_MASK   0xFFF
#define INIT_IF_MODE_OP_RESERVED1_SHIFT  4
/* Commands to skip if the modes dont match */
#define INIT_IF_MODE_OP_CMD_OFFSET_MASK  0xFFFF
#define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
	__le16 reserved2;
/* offset (in bytes) in modes expression buffer */
	__le16 modes_buf_offset;
};


/*
 * init operation: if_phase
 */
struct init_if_phase_op {
	__le32 op_data;
/* Init operation, from init_op_types enum */
#define INIT_IF_PHASE_OP_OP_MASK           0xF
#define INIT_IF_PHASE_OP_OP_SHIFT          0
/* Indicates if DMAE is enabled in this phase */
#define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK  0x1
#define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
#define INIT_IF_PHASE_OP_RESERVED1_MASK    0x7FF
#define INIT_IF_PHASE_OP_RESERVED1_SHIFT   5
/* Commands to skip if the phases dont match */
#define INIT_IF_PHASE_OP_CMD_OFFSET_MASK   0xFFFF
#define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT  16
	__le32 phase_data;
#define INIT_IF_PHASE_OP_PHASE_MASK        0xFF /* Init phase */
#define INIT_IF_PHASE_OP_PHASE_SHIFT       0
#define INIT_IF_PHASE_OP_RESERVED2_MASK    0xFF
#define INIT_IF_PHASE_OP_RESERVED2_SHIFT   8
#define INIT_IF_PHASE_OP_PHASE_ID_MASK     0xFFFF /* Init phase ID */
#define INIT_IF_PHASE_OP_PHASE_ID_SHIFT    16
};


/*
 * init mode operators
 */
enum init_mode_ops {
	INIT_MODE_OP_NOT /* init mode not operator */,
	INIT_MODE_OP_OR /* init mode or operator */,
	INIT_MODE_OP_AND /* init mode and operator */,
	MAX_INIT_MODE_OPS
};


/*
 * init operation: raw
 */
struct init_raw_op {
	__le32 op_data;
/* Init operation, from init_op_types enum */
#define INIT_RAW_OP_OP_MASK      0xF
#define INIT_RAW_OP_OP_SHIFT     0
#define INIT_RAW_OP_PARAM1_MASK  0xFFFFFFF /* init param 1 */
#define INIT_RAW_OP_PARAM1_SHIFT 4
	__le32 param2 /* Init param 2 */;
};

/*
 * init array params
 */
struct init_op_array_params {
	__le16 size /* array size in dwords */;
	__le16 offset /* array start offset in dwords */;
};

/*
 * Write init operation arguments
 */
union init_write_args {
/* value to write, used when init source is INIT_SRC_INLINE */
	__le32 inline_val;
/* number of zeros to write, used when init source is INIT_SRC_ZEROS */
	__le32 zeros_count;
/* array offset to write, used when init source is INIT_SRC_ARRAY */
	__le32 array_offset;
/* runtime array params to write, used when init source is INIT_SRC_RUNTIME */
	struct init_op_array_params runtime;
};

/*
 * init operation: write
 */
struct init_write_op {
	__le32 data;
/* init operation, from init_op_types enum */
#define INIT_WRITE_OP_OP_MASK        0xF
#define INIT_WRITE_OP_OP_SHIFT       0
/* init source type, taken from init_source_types enum */
#define INIT_WRITE_OP_SOURCE_MASK    0x7
#define INIT_WRITE_OP_SOURCE_SHIFT   4
#define INIT_WRITE_OP_RESERVED_MASK  0x1
#define INIT_WRITE_OP_RESERVED_SHIFT 7
/* indicates if the register is wide-bus */
#define INIT_WRITE_OP_WIDE_BUS_MASK  0x1
#define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
/* internal (absolute) GRC address, in dwords */
#define INIT_WRITE_OP_ADDRESS_MASK   0x7FFFFF
#define INIT_WRITE_OP_ADDRESS_SHIFT  9
	union init_write_args args /* Write init operation arguments */;
};

/*
 * init operation: read
 */
struct init_read_op {
	__le32 op_data;
/* init operation, from init_op_types enum */
#define INIT_READ_OP_OP_MASK         0xF
#define INIT_READ_OP_OP_SHIFT        0
/* polling type, from init_poll_types enum */
#define INIT_READ_OP_POLL_TYPE_MASK  0xF
#define INIT_READ_OP_POLL_TYPE_SHIFT 4
#define INIT_READ_OP_RESERVED_MASK   0x1
#define INIT_READ_OP_RESERVED_SHIFT  8
/* internal (absolute) GRC address, in dwords */
#define INIT_READ_OP_ADDRESS_MASK    0x7FFFFF
#define INIT_READ_OP_ADDRESS_SHIFT   9
/* expected polling value, used only when polling is done */
	__le32 expected_val;
};

/*
 * Init operations union
 */
union init_op {
	struct init_raw_op raw /* raw init operation */;
	struct init_write_op write /* write init operation */;
	struct init_read_op read /* read init operation */;
	struct init_if_mode_op if_mode /* if_mode init operation */;
	struct init_if_phase_op if_phase /* if_phase init operation */;
	struct init_callback_op callback /* callback init operation */;
	struct init_delay_op delay /* delay init operation */;
};


/*
 * Init command operation types
 */
enum init_op_types {
	INIT_OP_READ /* GRC read init command */,
	INIT_OP_WRITE /* GRC write init command */,
/* Skip init commands if the init modes expression doesn't match */
	INIT_OP_IF_MODE,
/* Skip init commands if the init phase doesn't match */
	INIT_OP_IF_PHASE,
	INIT_OP_DELAY /* delay init command */,
	INIT_OP_CALLBACK /* callback init command */,
	MAX_INIT_OP_TYPES
};


/*
 * init polling types
 */
enum init_poll_types {
	INIT_POLL_NONE /* No polling */,
	INIT_POLL_EQ /* init value is included in the init command */,
	INIT_POLL_OR /* init value is all zeros */,
	INIT_POLL_AND /* init value is an array of values */,
	MAX_INIT_POLL_TYPES
};


/*
 * init source types
 */
enum init_source_types {
	INIT_SRC_INLINE /* init value is included in the init command */,
	INIT_SRC_ZEROS /* init value is all zeros */,
	INIT_SRC_ARRAY /* init value is an array of values */,
	INIT_SRC_RUNTIME /* init value is provided during runtime */,
	MAX_INIT_SOURCE_TYPES
};


/*
 * Internal RAM Offsets macro data
 */
struct iro {
	__le32 base /* RAM field offset */;
	__le16 m1 /* multiplier 1 */;
	__le16 m2 /* multiplier 2 */;
	__le16 m3 /* multiplier 3 */;
	__le16 size /* RAM field size */;
};

#endif /* __ECORE_HSI_INIT_TOOL__ */
Commit	Line	Data
7c673cae FG	1	/*
	2	* Copyright (c) 2016 QLogic Corporation.
	3	* All rights reserved.
	4	* www.qlogic.com
	5	*
	6	* See LICENSE.qede_pmd for copyright and licensing details.
	7	*/
	8
	9	#ifndef __ECORE_HSI_INIT_TOOL__
	10	#define __ECORE_HSI_INIT_TOOL__
	11	/**************************************/
	12	/* Init Tool HSI constants and macros */
	13	/**************************************/
	14
	15	/* Width of GRC address in bits (addresses are specified in dwords) */
	16	#define GRC_ADDR_BITS 23
	17	#define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1)
	18
	19	/* indicates an init that should be applied to any phase ID */
	20	#define ANY_PHASE_ID 0xffff
	21
	22	/* Max size in dwords of a zipped array */
	23	#define MAX_ZIPPED_SIZE 8192
	24
	25
	26	struct fw_asserts_ram_section {
	27	/* The offset of the section in the RAM in RAM lines (64-bit units) */
	28	__le16 section_ram_line_offset;
	29	/* The size of the section in RAM lines (64-bit units) */
	30	__le16 section_ram_line_size;
	31	/* The offset of the asserts list within the section in dwords */
	32	u8 list_dword_offset;
	33	/* The size of an assert list element in dwords */
	34	u8 list_element_dword_size;
	35	u8 list_num_elements /* The number of elements in the asserts list */;
	36	/* The offset of the next list index field within the section in dwords */
	37	u8 list_next_index_dword_offset;
	38	};
	39
	40
	41	struct fw_ver_num {
	42	u8 major /* Firmware major version number */;
	43	u8 minor /* Firmware minor version number */;
	44	u8 rev /* Firmware revision version number */;
	45	/* Firmware engineering version number (for bootleg versions) */
	46	u8 eng;
	47	};
	48
	49	struct fw_ver_info {
	50	__le16 tools_ver /* Tools version number */;
	51	u8 image_id /* FW image ID (e.g. main, l2b, kuku) */;
	52	u8 reserved1;
	53	struct fw_ver_num num /* FW version number */;
	54	__le32 timestamp /* FW Timestamp in unix time (sec. since 1970) */;
	55	__le32 reserved2;
	56	};
	57
	58	struct fw_info {
	59	struct fw_ver_info ver /* FW version information */;
	60	/* Info regarding the FW asserts section in the Storm RAM */
	61	struct fw_asserts_ram_section fw_asserts_section;
	62	};
	63
	64
65	struct fw_info_location {
66	/* GRC address where the fw_info struct is located. */
67	__le32 grc_addr;
68	/* Size of the fw_info structure (thats located at the grc_addr). */
69	__le32 size;
70	};
71
72
73
74
75	enum init_modes {
76	MODE_BB_A0,
77	MODE_BB_B0,
78	MODE_K2,
79	MODE_ASIC,
80	MODE_EMUL_REDUCED,
81	MODE_EMUL_FULL,
82	MODE_FPGA,
83	MODE_CHIPSIM,
84	MODE_SF,
85	MODE_MF_SD,
86	MODE_MF_SI,
87	MODE_PORTS_PER_ENG_1,
88	MODE_PORTS_PER_ENG_2,
89	MODE_PORTS_PER_ENG_4,
90	MODE_100G,
91	MODE_40G,
92	MODE_EAGLE_ENG1_WORKAROUND,
93	MAX_INIT_MODES
94	};
95
96
97	enum init_phases {
98	PHASE_ENGINE,
99	PHASE_PORT,
100	PHASE_PF,
101	PHASE_VF,
102	PHASE_QM_PF,
103	MAX_INIT_PHASES
104	};
105
106
107	enum init_split_types {
108	SPLIT_TYPE_NONE,
109	SPLIT_TYPE_PORT,
110	SPLIT_TYPE_PF,
111	SPLIT_TYPE_PORT_PF,
112	SPLIT_TYPE_VF,
113	MAX_INIT_SPLIT_TYPES
114	};
115
116
117	/*
118	* Binary buffer header
119	*/
120	struct bin_buffer_hdr {
121	/* buffer offset in bytes from the beginning of the binary file */
122	__le32 offset;
123	__le32 length /* buffer length in bytes */;
124	};
125
126
127	/*
128	* binary init buffer types
129	*/
130	enum bin_init_buffer_type {
131	BIN_BUF_INIT_FW_VER_INFO /* fw_ver_info struct */,
132	BIN_BUF_INIT_CMD /* init commands */,
133	BIN_BUF_INIT_VAL /* init data */,
134	BIN_BUF_INIT_MODE_TREE /* init modes tree */,
135	BIN_BUF_INIT_IRO /* internal RAM offsets */,
136	MAX_BIN_INIT_BUFFER_TYPE
137	};
138
139
140	/*
141	* init array header: raw
142	*/
143	struct init_array_raw_hdr {
144	__le32 data;
145	/* Init array type, from init_array_types enum */
146	#define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
147	#define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
148	/* init array params */
149	#define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF
150	#define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
151	};
152
153	/*
154	* init array header: standard
155	*/
156	struct init_array_standard_hdr {
157	__le32 data;
158	/* Init array type, from init_array_types enum */
159	#define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
160	#define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
161	/* Init array size (in dwords) */
162	#define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
163	#define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
164	};
165
166	/*
167	* init array header: zipped
168	*/
169	struct init_array_zipped_hdr {
170	__le32 data;
171	/* Init array type, from init_array_types enum */
172	#define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
173	#define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
174	/* Init array zipped size (in bytes) */
175	#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
176	#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
177	};
178
179	/*
180	* init array header: pattern
181	*/
182	struct init_array_pattern_hdr {
183	__le32 data;
184	/* Init array type, from init_array_types enum */
185	#define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
186	#define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
187	/* pattern size in dword */
188	#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
189	#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
190	/* pattern repetitions */
191	#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
192	#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8
193	};
194
195	/*
196	* init array header union
197	*/
198	union init_array_hdr {
199	struct init_array_raw_hdr raw /* raw init array header */;
200	/* standard init array header */
201	struct init_array_standard_hdr standard;
202	struct init_array_zipped_hdr zipped /* zipped init array header */;
203	struct init_array_pattern_hdr pattern /* pattern init array header */;
204	};
205
206
207
208
209
210	/*
211	* init array types
212	*/
213	enum init_array_types {
214	INIT_ARR_STANDARD /* standard init array */,
215	INIT_ARR_ZIPPED /* zipped init array */,
216	INIT_ARR_PATTERN /* a repeated pattern */,
217	MAX_INIT_ARRAY_TYPES
218	};
219
220
221
222	/*
223	* init operation: callback
224	*/
225	struct init_callback_op {
226	__le32 op_data;
227	/* Init operation, from init_op_types enum */
228	#define INIT_CALLBACK_OP_OP_MASK 0xF
229	#define INIT_CALLBACK_OP_OP_SHIFT 0
230	#define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
231	#define INIT_CALLBACK_OP_RESERVED_SHIFT 4
232	__le16 callback_id /* Callback ID */;
233	__le16 block_id /* Blocks ID */;
234	};
235
236
237	/*
238	* init operation: delay
239	*/
240	struct init_delay_op {
241	__le32 op_data;
242	/* Init operation, from init_op_types enum */
243	#define INIT_DELAY_OP_OP_MASK 0xF
244	#define INIT_DELAY_OP_OP_SHIFT 0
245	#define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
246	#define INIT_DELAY_OP_RESERVED_SHIFT 4
247	__le32 delay /* delay in us */;
248	};
249
250
251	/*
252	* init operation: if_mode
253	*/
254	struct init_if_mode_op {
255	__le32 op_data;
256	/* Init operation, from init_op_types enum */
257	#define INIT_IF_MODE_OP_OP_MASK 0xF
258	#define INIT_IF_MODE_OP_OP_SHIFT 0
259	#define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
260	#define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
261	/* Commands to skip if the modes dont match */
262	#define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
263	#define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
264	__le16 reserved2;
265	/* offset (in bytes) in modes expression buffer */
266	__le16 modes_buf_offset;
267	};
268
269
270	/*
271	* init operation: if_phase
272	*/
273	struct init_if_phase_op {
274	__le32 op_data;
275	/* Init operation, from init_op_types enum */
276	#define INIT_IF_PHASE_OP_OP_MASK 0xF
277	#define INIT_IF_PHASE_OP_OP_SHIFT 0
278	/* Indicates if DMAE is enabled in this phase */
279	#define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1
280	#define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
281	#define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF
282	#define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5
283	/* Commands to skip if the phases dont match */
284	#define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
285	#define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
286	__le32 phase_data;
287	#define INIT_IF_PHASE_OP_PHASE_MASK 0xFF /* Init phase */
288	#define INIT_IF_PHASE_OP_PHASE_SHIFT 0
289	#define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
290	#define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
291	#define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF /* Init phase ID */
292	#define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
293	};
294
295
296	/*
297	* init mode operators
298	*/
299	enum init_mode_ops {
300	INIT_MODE_OP_NOT /* init mode not operator */,
301	INIT_MODE_OP_OR /* init mode or operator */,
302	INIT_MODE_OP_AND /* init mode and operator */,
303	MAX_INIT_MODE_OPS
304	};
305
306
307	/*
308	* init operation: raw
309	*/
310	struct init_raw_op {
311	__le32 op_data;
312	/* Init operation, from init_op_types enum */
313	#define INIT_RAW_OP_OP_MASK 0xF
314	#define INIT_RAW_OP_OP_SHIFT 0
315	#define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF /* init param 1 */
316	#define INIT_RAW_OP_PARAM1_SHIFT 4
317	__le32 param2 /* Init param 2 */;
318	};
319
320	/*
321	* init array params
322	*/
323	struct init_op_array_params {
324	__le16 size /* array size in dwords */;
325	__le16 offset /* array start offset in dwords */;
326	};
327
328	/*
329	* Write init operation arguments
330	*/
331	union init_write_args {
332	/* value to write, used when init source is INIT_SRC_INLINE */
333	__le32 inline_val;
334	/* number of zeros to write, used when init source is INIT_SRC_ZEROS */
335	__le32 zeros_count;
336	/* array offset to write, used when init source is INIT_SRC_ARRAY */
337	__le32 array_offset;
338	/* runtime array params to write, used when init source is INIT_SRC_RUNTIME */
339	struct init_op_array_params runtime;
340	};
341
342	/*
343	* init operation: write
344	*/
345	struct init_write_op {
346	__le32 data;
347	/* init operation, from init_op_types enum */
348	#define INIT_WRITE_OP_OP_MASK 0xF
349	#define INIT_WRITE_OP_OP_SHIFT 0
350	/* init source type, taken from init_source_types enum */
351	#define INIT_WRITE_OP_SOURCE_MASK 0x7
352	#define INIT_WRITE_OP_SOURCE_SHIFT 4
353	#define INIT_WRITE_OP_RESERVED_MASK 0x1
354	#define INIT_WRITE_OP_RESERVED_SHIFT 7
355	/* indicates if the register is wide-bus */
356	#define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
357	#define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
358	/* internal (absolute) GRC address, in dwords */
359	#define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
360	#define INIT_WRITE_OP_ADDRESS_SHIFT 9
361	union init_write_args args /* Write init operation arguments */;
362	};
363
364	/*
365	* init operation: read
366	*/
367	struct init_read_op {
368	__le32 op_data;
369	/* init operation, from init_op_types enum */
370	#define INIT_READ_OP_OP_MASK 0xF
371	#define INIT_READ_OP_OP_SHIFT 0
372	/* polling type, from init_poll_types enum */
373	#define INIT_READ_OP_POLL_TYPE_MASK 0xF
374	#define INIT_READ_OP_POLL_TYPE_SHIFT 4
375	#define INIT_READ_OP_RESERVED_MASK 0x1
376	#define INIT_READ_OP_RESERVED_SHIFT 8
377	/* internal (absolute) GRC address, in dwords */
378	#define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
379	#define INIT_READ_OP_ADDRESS_SHIFT 9
380	/* expected polling value, used only when polling is done */
381	__le32 expected_val;
382	};
383
384	/*
385	* Init operations union
386	*/
387	union init_op {
388	struct init_raw_op raw /* raw init operation */;
389	struct init_write_op write /* write init operation */;
390	struct init_read_op read /* read init operation */;
391	struct init_if_mode_op if_mode /* if_mode init operation */;
392	struct init_if_phase_op if_phase /* if_phase init operation */;
393	struct init_callback_op callback /* callback init operation */;
394	struct init_delay_op delay /* delay init operation */;
395	};
396
397
398
399	/*
400	* Init command operation types
401	*/
402	enum init_op_types {
403	INIT_OP_READ /* GRC read init command */,
404	INIT_OP_WRITE /* GRC write init command */,
405	/* Skip init commands if the init modes expression doesn't match */
406	INIT_OP_IF_MODE,
407	/* Skip init commands if the init phase doesn't match */
408	INIT_OP_IF_PHASE,
409	INIT_OP_DELAY /* delay init command */,
410	INIT_OP_CALLBACK /* callback init command */,
411	MAX_INIT_OP_TYPES
412	};
413
414
415	/*
416	* init polling types
417	*/
418	enum init_poll_types {
419	INIT_POLL_NONE /* No polling */,
420	INIT_POLL_EQ /* init value is included in the init command */,
421	INIT_POLL_OR /* init value is all zeros */,
422	INIT_POLL_AND /* init value is an array of values */,
423	MAX_INIT_POLL_TYPES
424	};
425
426
427
428
429	/*
430	* init source types
431	*/
432	enum init_source_types {
433	INIT_SRC_INLINE /* init value is included in the init command */,
434	INIT_SRC_ZEROS /* init value is all zeros */,
435	INIT_SRC_ARRAY /* init value is an array of values */,
436	INIT_SRC_RUNTIME /* init value is provided during runtime */,
437	MAX_INIT_SOURCE_TYPES
438	};
439
440
441
442
443	/*
444	* Internal RAM Offsets macro data
445	*/
446	struct iro {
447	__le32 base /* RAM field offset */;
448	__le16 m1 /* multiplier 1 */;
449	__le16 m2 /* multiplier 2 */;
450	__le16 m3 /* multiplier 3 */;
451	__le16 size /* RAM field size */;
452	};
453
454	#endif /* __ECORE_HSI_INIT_TOOL__ */