projects / ceph.git / blame
| Commit | Line | Data |
|---|---|---|
| 7c673cae FG |
1 | /******************************************************************************* |
| 2 | ||
| 3 | Intel 10 Gigabit PCI Express Linux driver | |
| 4 | Copyright(c) 1999 - 2012 Intel Corporation. | |
| 5 | ||
| 6 | This program is free software; you can redistribute it and/or modify it | |
| 7 | under the terms and conditions of the GNU General Public License, | |
| 8 | version 2, as published by the Free Software Foundation. | |
| 9 | ||
| 10 | This program is distributed in the hope it will be useful, but WITHOUT | |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 13 | more details. | |
| 14 | ||
| 15 | You should have received a copy of the GNU General Public License along with | |
| 16 | this program; if not, write to the Free Software Foundation, Inc., | |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 | ||
| 19 | The full GNU General Public License is included in this distribution in | |
| 20 | the file called "LICENSE.GPL". | |
| 21 | ||
| 22 | Contact Information: | |
| 23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
| 24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
| 25 | ||
| 26 | *******************************************************************************/ | |
| 27 | ||
| 28 | #ifndef _IXGBE_API_H_ | |
| 29 | #define _IXGBE_API_H_ | |
| 30 | ||
| 31 | #include "ixgbe_type.h" | |
| 32 | ||
| 33 | s32 ixgbe_init_shared_code(struct ixgbe_hw *hw); | |
| 34 | ||
| 35 | extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw); | |
| 36 | extern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw); | |
| 37 | extern s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw); | |
| 38 | ||
| 39 | s32 ixgbe_set_mac_type(struct ixgbe_hw *hw); | |
| 40 | s32 ixgbe_init_hw(struct ixgbe_hw *hw); | |
| 41 | s32 ixgbe_reset_hw(struct ixgbe_hw *hw); | |
| 42 | s32 ixgbe_start_hw(struct ixgbe_hw *hw); | |
| 43 | s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw); | |
| 44 | enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw); | |
| 45 | s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr); | |
| 46 | s32 ixgbe_get_bus_info(struct ixgbe_hw *hw); | |
| 47 | u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw); | |
| 48 | u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw); | |
| 49 | s32 ixgbe_stop_adapter(struct ixgbe_hw *hw); | |
| 50 | s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size); | |
| 51 | ||
| 52 | s32 ixgbe_identify_phy(struct ixgbe_hw *hw); | |
| 53 | s32 ixgbe_reset_phy(struct ixgbe_hw *hw); | |
| 54 | s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, | |
| 55 | u16 *phy_data); | |
| 56 | s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, | |
| 57 | u16 phy_data); | |
| 58 | ||
| 59 | s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw); | |
| 60 | s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, | |
| 61 | ixgbe_link_speed *speed, | |
| 62 | bool *link_up); | |
| 63 | s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, | |
| 64 | ixgbe_link_speed speed, | |
| 65 | bool autoneg, | |
| 66 | bool autoneg_wait_to_complete); | |
| 67 | void ixgbe_disable_tx_laser(struct ixgbe_hw *hw); | |
| 68 | void ixgbe_enable_tx_laser(struct ixgbe_hw *hw); | |
| 69 | void ixgbe_flap_tx_laser(struct ixgbe_hw *hw); | |
| 70 | s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, | |
| 71 | bool autoneg, bool autoneg_wait_to_complete); | |
| 72 | s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, | |
| 73 | bool *link_up, bool link_up_wait_to_complete); | |
| 74 | s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, | |
| 75 | bool *autoneg); | |
| 76 | s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index); | |
| 77 | s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index); | |
| 78 | s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index); | |
| 79 | s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index); | |
| 80 | ||
| 81 | s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw); | |
| 82 | s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data); | |
| 83 | s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, | |
| 84 | u16 words, u16 *data); | |
| 85 | s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data); | |
| 86 | s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, | |
| 87 | u16 words, u16 *data); | |
| 88 | ||
| 89 | s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val); | |
| 90 | s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw); | |
| 91 | ||
| 92 | s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq); | |
| 93 | s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, | |
| 94 | u32 enable_addr); | |
| 95 | s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index); | |
| 96 | s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq); | |
| 97 | s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq); | |
| 98 | s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq); | |
| 99 | s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw); | |
| 100 | u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw); | |
| 101 | s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, | |
| 102 | u32 addr_count, ixgbe_mc_addr_itr func); | |
| 103 | s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, | |
| 104 | u32 mc_addr_count, ixgbe_mc_addr_itr func, | |
| 105 | bool clear); | |
| 106 | void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr_list, u32 vmdq); | |
| 107 | s32 ixgbe_enable_mc(struct ixgbe_hw *hw); | |
| 108 | s32 ixgbe_disable_mc(struct ixgbe_hw *hw); | |
| 109 | s32 ixgbe_clear_vfta(struct ixgbe_hw *hw); | |
| 110 | s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, | |
| 111 | u32 vind, bool vlan_on); | |
| 112 | s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, | |
| 113 | bool vlan_on, bool *vfta_changed); | |
| 114 | s32 ixgbe_fc_enable(struct ixgbe_hw *hw); | |
| 115 | s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, | |
| 116 | u8 ver); | |
| 117 | s32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw); | |
| 118 | s32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw); | |
| 119 | void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr); | |
| 120 | s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, | |
| 121 | u16 *firmware_version); | |
| 122 | s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val); | |
| 123 | s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val); | |
| 124 | s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw); | |
| 125 | s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data); | |
| 126 | u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw); | |
| 127 | s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval); | |
| 128 | s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw); | |
| 129 | s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw); | |
| 130 | s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); | |
| 131 | s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); | |
| 132 | s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); | |
| 133 | s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, | |
| 134 | union ixgbe_atr_hash_dword input, | |
| 135 | union ixgbe_atr_hash_dword common, | |
| 136 | u8 queue); | |
| 137 | s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, | |
| 138 | union ixgbe_atr_input *input_mask); | |
| 139 | s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, | |
| 140 | union ixgbe_atr_input *input, | |
| 141 | u16 soft_id, u8 queue); | |
| 142 | s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, | |
| 143 | union ixgbe_atr_input *input, | |
| 144 | u16 soft_id); | |
| 145 | s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, | |
| 146 | union ixgbe_atr_input *input, | |
| 147 | union ixgbe_atr_input *mask, | |
| 148 | u16 soft_id, | |
| 149 | u8 queue); | |
| 150 | void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, | |
| 151 | union ixgbe_atr_input *mask); | |
| 152 | u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, | |
| 153 | union ixgbe_atr_hash_dword common); | |
| 154 | s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, | |
| 155 | u8 *data); | |
| 156 | s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, | |
| 157 | u8 data); | |
| 158 | s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data); | |
| 159 | s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr); | |
| 160 | s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr); | |
| 161 | s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps); | |
| 162 | s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask); | |
| 163 | void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask); | |
| 164 | s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, | |
| 165 | u16 *wwpn_prefix); | |
| 166 | s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs); | |
| 167 | ||
| 168 | #endif /* _IXGBE_API_H_ */ |