projects / ceph.git / blame
| Commit | Line | Data |
|---|---|---|
| 7c673cae FG |
1 | /******************************************************************************* |
| 2 | ||
| 3 | Intel 10 Gigabit PCI Express Linux driver | |
| 4 | Copyright(c) 1999 - 2012 Intel Corporation. | |
| 5 | ||
| 6 | This program is free software; you can redistribute it and/or modify it | |
| 7 | under the terms and conditions of the GNU General Public License, | |
| 8 | version 2, as published by the Free Software Foundation. | |
| 9 | ||
| 10 | This program is distributed in the hope it will be useful, but WITHOUT | |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 13 | more details. | |
| 14 | ||
| 15 | You should have received a copy of the GNU General Public License along with | |
| 16 | this program; if not, write to the Free Software Foundation, Inc., | |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 | ||
| 19 | The full GNU General Public License is included in this distribution in | |
| 20 | the file called "LICENSE.GPL". | |
| 21 | ||
| 22 | Contact Information: | |
| 23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
| 24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
| 25 | ||
| 26 | *******************************************************************************/ | |
| 27 | ||
| 28 | #ifndef _IXGBE_FCOE_H | |
| 29 | #define _IXGBE_FCOE_H | |
| 30 | ||
| 31 | #ifdef IXGBE_FCOE | |
| 32 | ||
| 33 | #include <scsi/fc/fc_fs.h> | |
| 34 | #include <scsi/fc/fc_fcoe.h> | |
| 35 | ||
| 36 | /* shift bits within STAT fo FCSTAT */ | |
| 37 | #define IXGBE_RXDADV_FCSTAT_SHIFT 4 | |
| 38 | ||
| 39 | /* ddp user buffer */ | |
| 40 | #define IXGBE_BUFFCNT_MAX 256 /* 8 bits bufcnt */ | |
| 41 | #define IXGBE_FCPTR_ALIGN 16 | |
| 42 | #define IXGBE_FCPTR_MAX (IXGBE_BUFFCNT_MAX * sizeof(dma_addr_t)) | |
| 43 | #define IXGBE_FCBUFF_4KB 0x0 | |
| 44 | #define IXGBE_FCBUFF_8KB 0x1 | |
| 45 | #define IXGBE_FCBUFF_16KB 0x2 | |
| 46 | #define IXGBE_FCBUFF_64KB 0x3 | |
| 47 | #define IXGBE_FCBUFF_MAX 65536 /* 64KB max */ | |
| 48 | #define IXGBE_FCBUFF_MIN 4096 /* 4KB min */ | |
| 49 | #define IXGBE_FCOE_DDP_MAX 512 /* 9 bits xid */ | |
| 50 | ||
| 51 | /* Default traffic class to use for FCoE */ | |
| 52 | #define IXGBE_FCOE_DEFTC 3 | |
| 53 | ||
| 54 | /* fcerr */ | |
| 55 | #define IXGBE_FCERR_BADCRC 0x00100000 | |
| 56 | #define IXGBE_FCERR_EOFSOF 0x00200000 | |
| 57 | #define IXGBE_FCERR_NOFIRST 0x00300000 | |
| 58 | #define IXGBE_FCERR_OOOSEQ 0x00400000 | |
| 59 | #define IXGBE_FCERR_NODMA 0x00500000 | |
| 60 | #define IXGBE_FCERR_PKTLOST 0x00600000 | |
| 61 | ||
| 62 | /* FCoE DDP for target mode */ | |
| 63 | #define __IXGBE_FCOE_TARGET 1 | |
| 64 | ||
| 65 | struct ixgbe_fcoe_ddp { | |
| 66 | int len; | |
| 67 | u32 err; | |
| 68 | unsigned int sgc; | |
| 69 | struct scatterlist *sgl; | |
| 70 | dma_addr_t udp; | |
| 71 | u64 *udl; | |
| 72 | struct pci_pool *pool; | |
| 73 | }; | |
| 74 | ||
| 75 | struct ixgbe_fcoe { | |
| 76 | struct pci_pool **pool; | |
| 77 | atomic_t refcnt; | |
| 78 | spinlock_t lock; | |
| 79 | struct ixgbe_fcoe_ddp ddp[IXGBE_FCOE_DDP_MAX]; | |
| 80 | unsigned char *extra_ddp_buffer; | |
| 81 | dma_addr_t extra_ddp_buffer_dma; | |
| 82 | u64 __percpu *pcpu_noddp; | |
| 83 | u64 __percpu *pcpu_noddp_ext_buff; | |
| 84 | unsigned long mode; | |
| 85 | u8 tc; | |
| 86 | u8 up; | |
| 87 | u8 up_set; | |
| 88 | }; | |
| 89 | #endif /* IXGBE_FCOE */ | |
| 90 | ||
| 91 | #endif /* _IXGBE_FCOE_H */ |