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1 | /********************************************************************** |
2 | Copyright(c) 2019 Arm Corporation All rights reserved. | |
3 | ||
4 | Redistribution and use in source and binary forms, with or without | |
5 | modification, are permitted provided that the following conditions | |
6 | are met: | |
7 | * Redistributions of source code must retain the above copyright | |
8 | notice, this list of conditions and the following disclaimer. | |
9 | * Redistributions in binary form must reproduce the above copyright | |
10 | notice, this list of conditions and the following disclaimer in | |
11 | the documentation and/or other materials provided with the | |
12 | distribution. | |
13 | * Neither the name of Arm Corporation nor the names of its | |
14 | contributors may be used to endorse or promote products derived | |
15 | from this software without specific prior written permission. | |
16 | ||
17 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
18 | "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
19 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
20 | A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
21 | OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
22 | SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
23 | LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
24 | DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
25 | THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
26 | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
27 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
28 | **********************************************************************/ | |
29 | #include <aarch64_multibinary.h> | |
30 | ||
31 | DEFINE_INTERFACE_DISPATCHER(isal_adler32) | |
32 | { | |
33 | unsigned long auxval = getauxval(AT_HWCAP); | |
34 | if (auxval & HWCAP_ASIMD) | |
35 | return PROVIDER_INFO(adler32_neon); | |
36 | ||
37 | return PROVIDER_BASIC(adler32); | |
38 | ||
39 | } | |
40 | ||
41 | DEFINE_INTERFACE_DISPATCHER(isal_deflate_body) | |
42 | { | |
43 | unsigned long auxval = getauxval(AT_HWCAP); | |
44 | ||
45 | if (auxval & HWCAP_CRC32) | |
46 | return PROVIDER_INFO(isal_deflate_body_aarch64); | |
47 | ||
48 | return PROVIDER_BASIC(isal_deflate_body); | |
49 | ||
50 | } | |
51 | ||
52 | DEFINE_INTERFACE_DISPATCHER(isal_deflate_finish) | |
53 | { | |
54 | unsigned long auxval = getauxval(AT_HWCAP); | |
55 | if (auxval & HWCAP_CRC32) | |
56 | return PROVIDER_INFO(isal_deflate_finish_aarch64); | |
57 | ||
58 | return PROVIDER_BASIC(isal_deflate_finish); | |
59 | ||
60 | } | |
61 | ||
62 | DEFINE_INTERFACE_DISPATCHER(isal_deflate_icf_body_lvl1) | |
63 | { | |
64 | unsigned long auxval = getauxval(AT_HWCAP); | |
65 | if (auxval & HWCAP_CRC32) | |
66 | return PROVIDER_INFO(isal_deflate_icf_body_hash_hist_aarch64); | |
67 | ||
68 | return PROVIDER_BASIC(isal_deflate_icf_body_hash_hist); | |
69 | } | |
70 | ||
71 | DEFINE_INTERFACE_DISPATCHER(isal_deflate_icf_finish_lvl1) | |
72 | { | |
73 | unsigned long auxval = getauxval(AT_HWCAP); | |
74 | if (auxval & HWCAP_CRC32) | |
75 | return PROVIDER_INFO(isal_deflate_icf_finish_hash_hist_aarch64); | |
76 | ||
77 | return PROVIDER_BASIC(isal_deflate_icf_finish_hash_hist); | |
78 | } | |
79 | ||
80 | DEFINE_INTERFACE_DISPATCHER(isal_deflate_icf_body_lvl2) | |
81 | { | |
82 | unsigned long auxval = getauxval(AT_HWCAP); | |
83 | if (auxval & HWCAP_CRC32) | |
84 | return PROVIDER_INFO(isal_deflate_icf_body_hash_hist_aarch64); | |
85 | ||
86 | return PROVIDER_BASIC(isal_deflate_icf_body_hash_hist); | |
87 | } | |
88 | ||
89 | DEFINE_INTERFACE_DISPATCHER(isal_deflate_icf_finish_lvl2) | |
90 | { | |
91 | unsigned long auxval = getauxval(AT_HWCAP); | |
92 | if (auxval & HWCAP_CRC32) | |
93 | return PROVIDER_INFO(isal_deflate_icf_finish_hash_hist_aarch64); | |
94 | ||
95 | return PROVIDER_BASIC(isal_deflate_icf_finish_hash_hist); | |
96 | } | |
97 | ||
98 | DEFINE_INTERFACE_DISPATCHER(isal_deflate_icf_body_lvl3) | |
99 | { | |
100 | unsigned long auxval = getauxval(AT_HWCAP); | |
101 | if (auxval & HWCAP_CRC32) | |
102 | return PROVIDER_INFO(icf_body_hash1_fillgreedy_lazy); | |
103 | ||
104 | return PROVIDER_INFO(icf_body_hash1_fillgreedy_lazy); | |
105 | } | |
106 | ||
107 | DEFINE_INTERFACE_DISPATCHER(isal_deflate_icf_finish_lvl3) | |
108 | { | |
109 | unsigned long auxval = getauxval(AT_HWCAP); | |
110 | if (auxval & HWCAP_CRC32) | |
111 | return PROVIDER_INFO(isal_deflate_icf_finish_hash_map_base); | |
112 | ||
113 | return PROVIDER_BASIC(isal_deflate_icf_finish_hash_map); | |
114 | } | |
115 | ||
116 | DEFINE_INTERFACE_DISPATCHER(set_long_icf_fg) | |
117 | { | |
118 | return PROVIDER_INFO(set_long_icf_fg_aarch64); | |
119 | } | |
120 | ||
121 | DEFINE_INTERFACE_DISPATCHER(encode_deflate_icf) | |
122 | { | |
123 | return PROVIDER_INFO(encode_deflate_icf_aarch64); | |
124 | } | |
125 | ||
126 | DEFINE_INTERFACE_DISPATCHER(isal_update_histogram) | |
127 | { | |
128 | unsigned long auxval = getauxval(AT_HWCAP); | |
129 | if (auxval & HWCAP_CRC32) | |
130 | return PROVIDER_INFO(isal_update_histogram_aarch64); | |
131 | ||
132 | return PROVIDER_BASIC(isal_update_histogram); | |
133 | } | |
134 | ||
135 | DEFINE_INTERFACE_DISPATCHER(gen_icf_map_lh1) | |
136 | { | |
137 | unsigned long auxval = getauxval(AT_HWCAP); | |
138 | if (auxval & HWCAP_CRC32) { | |
139 | return PROVIDER_INFO(gen_icf_map_h1_aarch64); | |
140 | } | |
141 | ||
142 | return PROVIDER_BASIC(gen_icf_map_h1); | |
143 | } | |
144 | ||
145 | DEFINE_INTERFACE_DISPATCHER(isal_deflate_hash_lvl0) | |
146 | { | |
147 | unsigned long auxval = getauxval(AT_HWCAP); | |
148 | if (auxval & HWCAP_CRC32) | |
149 | return PROVIDER_INFO(isal_deflate_hash_aarch64); | |
150 | ||
151 | return PROVIDER_BASIC(isal_deflate_hash); | |
152 | } | |
153 | ||
154 | DEFINE_INTERFACE_DISPATCHER(isal_deflate_hash_lvl1) | |
155 | { | |
156 | unsigned long auxval = getauxval(AT_HWCAP); | |
157 | if (auxval & HWCAP_CRC32) | |
158 | return PROVIDER_INFO(isal_deflate_hash_aarch64); | |
159 | ||
160 | return PROVIDER_BASIC(isal_deflate_hash); | |
161 | } | |
162 | ||
163 | DEFINE_INTERFACE_DISPATCHER(isal_deflate_hash_lvl2) | |
164 | { | |
165 | unsigned long auxval = getauxval(AT_HWCAP); | |
166 | if (auxval & HWCAP_CRC32) | |
167 | return PROVIDER_INFO(isal_deflate_hash_aarch64); | |
168 | ||
169 | return PROVIDER_BASIC(isal_deflate_hash); | |
170 | } | |
171 | ||
172 | DEFINE_INTERFACE_DISPATCHER(isal_deflate_hash_lvl3) | |
173 | { | |
174 | unsigned long auxval = getauxval(AT_HWCAP); | |
175 | if (auxval & HWCAP_CRC32) | |
176 | return PROVIDER_INFO(isal_deflate_hash_aarch64); | |
177 | ||
178 | return PROVIDER_BASIC(isal_deflate_hash); | |
179 | } | |
180 | ||
181 | DEFINE_INTERFACE_DISPATCHER(decode_huffman_code_block_stateless) | |
182 | { | |
183 | unsigned long auxval = getauxval(AT_HWCAP); | |
184 | if (auxval & HWCAP_CRC32) | |
185 | return PROVIDER_INFO(decode_huffman_code_block_stateless_aarch64); | |
186 | ||
187 | return PROVIDER_BASIC(decode_huffman_code_block_stateless); | |
188 | } |